Bit spread techniques for radiation-hardened error-tolerant memory systems

Abstract

A technique is provided for an error-tolerant, radiation-tolerant memory system based on the distribution of data bits across multiple random-access memories (RAMs). A memory system implementing the technique according to one embodiment includes a first plurality of RAMs configured to store data bits written to the memory system, the data bits being distributed across the first plurality of RAMs. The system also includes an ECC circuit configured to generate error-correction coding (ECC) codes, each of which is associated with a unique group of data bits. The system further includes a second plurality of RAMs configured to store bits of the ECC codes, so that the bits of each ECC code are distributed across the second plurality of RAMs. The system further includes a reporting circuit configured to report single-bit error correction or double-bit error detection resulting from read operations on the memory system.

Description

Technical Field

[0001] Statement Regarding Government Interests

[0001] This invention was made with government support under Contract No. 100115865 awarded by the National Security Technology Accelerator. The United States government has certain rights in this invention.

[0002]

[0002] This disclosure relates to memory systems, and more particularly to the use of bit diffusion techniques in memory systems to provide radiation hardened memory operation for reducing radiation induced single event effect susceptibility.

Background Art

[0003]

[0003] Memory systems deployed in space - based applications are exposed to relatively high radiation levels, which can cause a significant increase in single - bit errors, multi - bit errors, and single event functional interrupt (SEFI) errors, and can damage the entire memory. In some cases, these errors can cause the memory to stop functioning. Shielding can reduce radiation exposure, but this approach is not practical, especially in space - based applications where severe weight constraints may be imposed, due to the additional weight (e.g., requiring lead or similarly high - density materials). Redundant memory using majority - voting techniques can reduce the error rate, but this approach also increases cost and complexity to a degree that it may not be practical in many applications. Error correction coding (ECC) schemes exist, but they also have limitations.

Brief Description of the Drawings

[0004] [Figure 1]

[0004] A figure showing one implementation of a radiation-resistant error-resistant memory system according to some embodiments of the present disclosure. [Figure 2]

[0005] A block diagram of the error-tolerant memory system shown in Figure 1, configured according to some embodiments of the present disclosure. [Figure 3]

[0006] A diagram of a bit-spread memory unit configured for an 8-bit data word according to some embodiments of the present disclosure. [Figure 4]

[0007] A diagram of a bit-spread memory unit configured for a 16-bit data word according to some embodiments of the present disclosure. [Figure 5]

[0008] A diagram of a bit-spread memory unit configured for a 32-bit data word according to some embodiments of the present disclosure. [Figure 6]

[0009] A diagram of a bit-spread memory unit configured for a 64-bit data word according to some embodiments of the present disclosure. [Figure 7]

[0010] A diagram of a bit-spread memory unit configured for a 128-bit data word according to some embodiments of the present disclosure. [Figure 8]

[0011] A flowchart illustrating a method for providing radiation-tolerant error-resistant memory according to one embodiment of the present disclosure. [Figure 9]

[0012] A block diagram of a processing platform configured to provide radiation-tolerant error-tolerant memory according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0005]

[0013] The embodiments for carrying out the following invention will proceed with reference to exemplary embodiments, but many alternative, modified, and altered forms thereof will become apparent in light of this disclosure.

[0006]

[0014] For example, a single radiation event can corrupt multiple bits or an entire random access memory (RAM). To reduce susceptibility to radiation-induced single-event effects, techniques for error-tolerant memory systems configured to provide radiation-hardened memory operation are provided herein. The techniques are based on the diffusion of data bits across multiple RAMs. As described above, memory systems deployed in space-based applications are exposed to relatively high levels of radiation, which can cause a significant increase in single-bit errors, multi-bit errors, and SEFI errors. In some cases, these errors can render the memory non-functional. As memory circuits become smaller, less radiation energy is required to flip a bit from 0 to 1 or vice versa. Shielding can reduce radiation exposure, but this technique is impractical due to the added weight (e.g., requiring lead or similarly high-density materials), particularly in space-based or aerospace applications where strict weight constraints may be imposed. Redundant memory using majority voting techniques can reduce the error rate, but this technique also increases cost and complexity to some extent, making it impractical in some applications. The ECC method also has limitations, particularly when data bits are stored in a single RAM, which is susceptible to multi-bit errors and SEFI errors from a single radiated event.

[0007]

[0015] For this purpose, and according to one embodiment of the present disclosure, an error-tolerant memory system is disclosed, which accepts a data word to be written to the memory system and distributes or spreads the data bits of the word, along with associated error correction code, to store across several isolated RAMs. This bit-spreading technique enables successful error recovery if a single RAM is subjected to radiation levels (or interference from other sources) that alter the values ​​of one or more bits in that RAM. Since the RAMs are physically isolated from each other to some extent, it is unlikely that a single radiation particle will affect two or more RAMs at once. Furthermore, by providing word-based error prevention as opposed to larger block-based prevention, a failure in error prevention does not result in the greater latency that would arise from recovering data in larger blocks. Thus, the RAMs may fail, and the pipeline of data to be read is not exposed to gaps in empty read cycles.

[0008]

[0016] Error-tolerant memory systems offer improved reliability for memory operation in higher radiation environments, such as space-based applications. The disclosed error-tolerant memory systems can be used with electronic systems in a wide variety of applications, including radar and communication systems, which may be deployed in space-based applications (e.g., satellite-based platforms) or other high-radiation environments, but other applications, including aerospace and ground applications such as automotive products, will also become apparent.

[0009]

[0017] According to one embodiment, an error-tolerant memory system includes one or more memory units, each memory unit configured to store a data word to be written to the memory system. Each memory unit comprises a first plurality of RAMs configured to store the data bits of the data word, so that the data bits are distributed across the first plurality of RAMs. The memory system also includes an ECC circuit configured to generate an ECC code, each of which is associated with a unique group of data bits. Each memory unit further comprises a second plurality of RAMs configured to store the bits of the ECC code, so that the bits of the ECC code are distributed across the second plurality of RAMs. The memory system further includes a reporting circuit configured to report, for example, single-bit error correction or double-bit error detection resulting from a read operation on the memory unit.

[0010]

[0018] It will be understood that the techniques described herein may offer improved error correction and recovery capabilities in terms of cost, reliability, and operating speed compared to systems that require physical shielding or redundant storage. Numerous embodiments and applications will become apparent in light of this disclosure.

[0011] System Architecture

[0019] Figure 1 shows an implementation configuration 100 of a radiation-tolerant error-tolerant memory system according to several embodiments of the present disclosure. Implementation configuration 100 is shown to include a processor 120 and an error-tolerant memory system 130 hosted on a platform 110. In some embodiments, the platform 110 is a space-based or aerospace platform that may be exposed to radiation 140 at higher levels of intensity compared to an earth-based platform. Other applications include those that may operate in environments with high levels of ionizing radiation, such as military and nuclear applications.

[0012]

[0020] The operation of the error-tolerant memory system 130 will be described in more detail below, but at a high level, the error-tolerant memory system 130 is configured to detect and correct errors (for example, errors caused by radiation effects or from other sources). In some embodiments, the error-tolerant memory system 130 employs ECC code associated with groups of data bits, which can correct single-bit errors occurring within those groups of data bits. The ECC code can also detect double-bit errors within groups of data bits, but it cannot necessarily correct them. The error-tolerant memory system provides improved error tolerance by distributing the groups of data bits and associated ECC code across several separate RAMs, so that bit errors in any one of the RAMs, and even failures of an entire single RAM, can be corrected as described below.

[0013]

[0021] Figure 2 is a block diagram of the error-tolerant memory system 130 of Figure 1, configured according to some embodiments of the present disclosure. The error-tolerant memory system 130 is shown to include a memory write circuit 200, a memory read circuit 210, a spread bit memory 215 (equipped with several spread bit memory units 220), an error reporting circuit 230, and an ECC circuit 240.

[0014]

[0022] The memory writing circuit 200 is configured to receive data words from the processor 120 or any other suitable source and write them to the spread-bit memory 215. The data words can be of any desired bit length. In some embodiments, for example, the data words may be 8 bits, 16 bits, 32 bits, 64 bits, or 128 bits, but other lengths are possible, including lengths that are not necessarily powers of 2.

[0015]

[0023] The memory read circuit 210 is configured to read data words from the spread-bit memory 215, for example, when requested by the processor, and to provide those data words to the processor or any other suitable destination.

[0016]

[0024] The bit-spread memory 215 comprises several bit-spread memory units 220. In some embodiments, each of the memory units 220 is configured to store a data word. The memory units may be selected by an address associated with a memory write operation or a memory read operation. Thus, the address specifies which memory unit 220 of memory 215 the data word should be written to or read from. The memory units 220 are configured to store data words in an error-tolerant manner by distributing the data bits of the data word across several separate RAMs in the memory unit, along with an ECC code. In some embodiments, the RAMs may be configured to store two or more data words, and the multiple words may be selectable by address. The operation of memory units of various sizes will be explained in more detail below with respect to Figures 3 to 7, but as can be seen in Figure 5, for example, a 32-bit data word is divided into four groups of data bits (e.g., bits 0-7, 8-15, 16-23, and 24-31), and each data group is spread across eight RAMs (RAM0-7). Also as shown in Figure 5, the ECC code associated with each data group is spread across five additional RAMs (e.g., W0, W1, W2, W3, and W4 across RAM8-12).

[0017]

[0025] The size of the memory 215 can be configured based on the memory requirements of an application (e.g., mission software running on the processor 120), or based on any other suitable considerations. For example, if 1K of memory for 32-bit data words is required, the memory 215 can include 1K memory units 220 each configured to store a 32-bit data word. As described above, in some embodiments, each RAM can be configured to store multiple words, and thus the number of memory units can be correspondingly reduced. For example, if the RAM is configured to store 16 words, only 64 memory units (e.g., 1024 / 16) would be required.

[0018]

[0026] The ECC circuit 240 is configured, for example, to generate an ECC code for each group of data bits when a data word is written to a memory unit. In some embodiments, the ECC code is configured to detect and correct single-bit errors in a group of data bits and to detect double-bit errors in a group of data bits. In some embodiments, the ECC code can be a Hamming code, but in light of the present disclosure, other suitable single-bit error correction codes can be used. In some embodiments, the ECC code is of length M bits, where M = log2(N)+2 bits, where N is the number of bits in the data group for which the ECC code is generated.

[0019]

[0027] The ECC circuit 240 is also configured, for example, to use the ECC code to detect errors in each of the groups of data bits and, optionally, to correct them when a data word is read from a memory unit.

[0020]

[0028] The error reporting circuit 230 is configured to report any single-bit error correction or double-bit error detection that occurs. In some embodiments, the reporting can be directed to a processor, which can use that information to track the error rate and take any appropriate action.

[0021]

[0029] FIG. 3 is a diagram of a bit-dispersive memory unit 220a configured for an 8-bit data word, according to some embodiments of the present disclosure. The memory unit 220a is shown to include five RAMs 300 each configured to store 4 bits. The first two RAMs are configured to store the eight data bits 310 of the data word written to the memory unit, as shown. Specifically, the first group of data bits (0, 1) is stored or dispersed across RAMs 0 and 1 in the first column of the RAMs. Similarly, the second group of data bits (2, 3) is stored in the second column, the third group of data bits (4, 5) is stored in the third column, and the fourth group of data bits (6, 7) is stored in the fourth column.

[0022]

[0030] The remaining three RAMs are configured to store 3-bit ECC codes 320 associated with groups of data bits (e.g., the columns of RAMs 0 and 1). The first ECC code, W0E0~W0E2 (word 0, ECC bits 0~2), is dispersed across the first column of RAMs 2~4 and is associated with data bits 0 and 1. Similarly, the second ECC code, W1E0~W1E2, is dispersed across the second column of RAMs 2~4 and is associated with data bits 2 and 3. The third ECC code, W2E0~W2E2, is dispersed across the third column of RAMs 2~4 and is associated with data bits 4 and 5. Finally, the fourth ECC code, W3E0~W3E2, is dispersed across the fourth column of RAMs 2~4 and is associated with data bits 6 and 7.

[0023]

[0031] If an error occurs in any single bit of a group of data bits (a column of RAM), the error can be corrected based on the ECC code associated with that data bit group. For example, if data bit 0 is corrupted, it can be restored based on ECC code W0. If the entire RAM becomes corrupted (e.g., SEFI), all the data bits in that RAM can be restored based on ECC codes W0-W3. Similarly, a single data bit error in any or all of a group (column) of data bits can be corrected.

[0024]

[0032] The overhead factor OF can be defined as the total number of RAMs used by the memory unit divided by the number of RAMs used to store data. In this example, for an 8-bit data word, only two out of five RAMs are used to store the data, and therefore the overhead factor OF = 2.5, which is relatively inefficient. However, as can be seen below, efficiency increases as the size of the data word increases.

[0025]

[0033] Figure 4 shows a bit-spread memory unit 220b configured for a 16-bit data word according to some embodiments of the present disclosure. The memory unit 220b is shown to include eight RAMs 400, each configured to store 4 bits. The first four RAMs are configured to store 16 data bits 410 of a data word written to the memory unit, as shown. In particular, a first group of data bits (0-3) are stored or distributed across RAMs 0-3 in a first column of RAMs. Similarly, a second group of data bits (4-7) are stored in a second column, a third group of data bits (8-11) are stored in a third column, and a fourth group of data bits (12-15) are stored in a fourth column.

[0026]

[0034] The remaining four RAMs are configured to store 4-bit ECC codes 420 associated with groups of data bits (for example, the columns of RAMs 0-3). The first ECC codes, W0E0-W0E3, are distributed across the first columns of RAMs 4-7 and associated with data bits 0-3. Similarly, the second ECC codes, W1E0-W1E3, are distributed across the second columns of RAMs 4-7 and associated with data bits 4-7. The third ECC codes, W2E0-W2E3, are distributed across the third columns of RAMs 4-7 and associated with data bits 8-11. Finally, the fourth ECC codes, W3E0-W3E3, are distributed across the fourth columns of RAMs 4-7 and associated with data bits 12-15.

[0027]

[0035] With respect to the 8-bit data word configuration in Figure 3, as previously explained, if an error occurs in any single bit of a group of data bits (e.g., a column of RAM), the error can be corrected based on the ECC code associated with that data bit group.

[0028]

[0036] In this example, for a 16-bit data word, four of the eight RAMs are used to store the data, and therefore the overhead factor OF = 2.0, which is an improvement over the 8-bit data word case described above.

[0029]

[0037] Figure 5 shows a bit-spread memory unit 220c configured for a 32-bit data word according to some embodiments of the present disclosure. The memory unit 220c is shown to include 13 RAMs 500, each configured to store 4 bits. The first eight RAMs are configured to store 32 data bits 510 of a data word written to the memory unit, as shown. In particular, a first group of data bits (0-7) are stored or distributed across RAMs 0-7 in a first column of RAMs. Similarly, a second group of data bits (8-15) are stored in a second column, a third group of data bits (16-23) are stored in a third column, and a fourth group of data bits (24-31) are stored in a fourth column.

[0030]

[0038] The remaining five RAMs are configured to store 5-bit ECC codes 520 associated with groups of data bits (for example, columns RAM0-7). The first ECC codes, W0E0-W0E4, are distributed across the first columns of RAM8-12 and associated with data bits 0-7. Similarly, the second ECC codes, W1E0-W1E4, are distributed across the second columns of RAM8-12 and associated with data bits 8-15. The third ECC codes, W2E0-W2E4, are distributed across the third columns of RAM8-12 and associated with data bits 16-23. Finally, the fourth ECC codes, W3E0-W3E4, are distributed across the fourth columns of RAM8-12 and associated with data bits 24-31. As previously described, if an error occurs in any single bit of a group of data bits (a column of RAM), that error can be corrected based on the ECC code associated with that data bit group.

[0031]

[0039] In this example, for a 32-bit data word, eight of the thirteen RAMs are used to store the data, and therefore the efficiency overhead factor OF = 1.625, which is a further improvement over the previously described case.

[0032]

[0040] Figure 6 shows a bit-spread memory unit 220d configured for a 64-bit data word according to some embodiments of the present disclosure. The memory unit 220d is shown to include 22 RAMs 600, each configured to store 4 bits. The first 16 RAMs are configured to store 64 data bits 610 of a data word written to the memory unit, as shown. In particular, a first group of data bits (0-15) are stored or distributed across RAMs 0-15 in a first column of RAMs. Similarly, a second group of data bits (16-31) are stored in a second column, a third group of data bits (32-47) are stored in a third column, and a fourth group of data bits (48-63) are stored in a fourth column.

[0033]

[0041] The remaining six RAMs are configured to store 6-bit ECC codes 620 associated with groups of data bits (for example, columns RAM0-15). The first ECC codes, W0E0-W0E5, are distributed across the first columns of RAM16-21 and associated with data bits 0-15. Similarly, the second ECC codes, W1E0-W1E5, are distributed across the second columns of RAM16-21 and associated with data bits 16-31. The third ECC codes, W2E0-W2E5, are distributed across the third columns of RAM16-21 and associated with data bits 32-47. Finally, the fourth ECC codes, W3E0-W3E5, are distributed across the fourth columns of RAM16-21 and associated with data bits 48-63. As previously explained, if an error occurs in any single bit of a group of data bits (a column in RAM), that error can be corrected based on the ECC code associated with that data bit group.

[0034]

[0042] In this example, for a 64-bit data word, 16 of the 22 RAMs are used to store the data, and therefore the overhead factor OF = 1.375, which is a further improvement over the previously described case.

[0035]

[0043] Figure 7 shows a bit-spread memory unit 220e configured for a 128-bit data word according to some embodiments of the present disclosure. The memory unit 220e is shown to include 39 RAMs 700, each configured to store 4 bits. The first 32 RAMs are configured to store 128 data bits 710 of a data word written to the memory unit, as shown. In particular, a first group of data bits (0-31) are stored or distributed across RAMs 0-31 in a first column of RAMs. Similarly, a second group of data bits (32-63) are stored in a second column, a third group of data bits (64-95) are stored in a third column, and a fourth group of data bits (96-127) are stored in a fourth column.

[0036]

[0044] The remaining seven RAMs are configured to store 7-bit ECC codes 720 associated with groups of data bits (for example, columns RAM0-31). The first ECC codes, W0E0-W0E6, are distributed across the first columns of RAM32-38 and associated with data bits 0-31. Similarly, the second ECC codes, W1E0-W1E6, are distributed across the second columns of RAM32-38 and associated with data bits 32-63. The third ECC codes, W2E0-W2E6, are distributed across the third columns of RAM32-38 and associated with data bits 64-95. Finally, the fourth ECC codes, W3E0-W3E6, are distributed across the fourth columns of RAM32-38 and associated with data bits 96-127. As previously explained, if an error occurs in any single bit of a group of data bits (a column in RAM), that error can be corrected based on the ECC code associated with that data bit group.

[0037]

[0045] In this example, for a 128-bit data word, 32 out of 39 RAMs are used to store the data, and therefore the overhead factor OF = 1.21875, which is a further improvement over the previously described case.

[0038]

[0046] It will be understood that other memory unit configurations are possible and can be adapted to any desired application. For example, RAM may be configured to store more than 4 bits of data, and memory units may be configured for use with data words of different sizes.

[0039] method

[0047] Figure 8 is a flowchart of a method 800 for providing radiation-hardened error-tolerant memory according to one embodiment of the present disclosure. As can be seen, the exemplary method 800 includes several steps and subprocesses, the sequence of which may vary from embodiment to embodiment. However, when considered as a whole, these steps and subprocesses form a process for providing radiation-hardened error-tolerant memory according to some of the embodiments disclosed herein, such as those shown in Figures 1 to 7, as described above. However, as will become apparent in light of the present disclosure, other system architectures may be used in other embodiments. For this purpose, the correlation between the various functions shown in Figure 8 and the specific components shown in the figure is not intended to imply structural and / or usage limitations. Rather, other embodiments may include, for example, different densities of integration, where multiple functions are effectively performed by a single system. Numerous variations and alternative configurations will become apparent in light of the present disclosure.

[0040]

[0048] In one embodiment, method 800 comprises a write process 800a and a read process 800b. In one embodiment, method 800a begins in operation 810 by storing data bits written by the processor to a memory unit of the memory system. The stored data bits are distributed across a first plurality of RAMs of the memory unit, as previously described.

[0041]

[0049] In operation 820, an ECC code is generated. Each ECC code is associated with a unique group of stored data bits. For example, a unique group of stored data bits may be a sequence spanning multiple first RAMs, as previously described. In some embodiments, the ECC code is generated using the Hamming ECC coding technique, but any ECC code capable of correcting single-bit errors may be used.

[0042]

[0050] In operation 830, the bits of the ECC code are stored in a second plurality of RAMs of the memory unit, and thus the bits of the ECC code are distributed across the second plurality of RAMs as previously described. In some embodiments, operations 810-830 may be performed in parallel.

[0043]

[0051] In one embodiment, method 800b begins in operation 840 by reading data bits stored from a first plurality of RAMs in a memory unit and reading ECC codes from a second plurality of RAMs, as previously described.

[0044]

[0052] In operation 850, the ECC code is calculated for the data bits and validated against the ECC code read from a second set of RAMs to potentially generate single-bit error correction and / or double-bit error detection.

[0045]

[0053] In operation 860, any single-bit error correction and / or double-bit error detection are reported to the processor.

[0046] Exemplary System

[0054] Figure 9 is a block diagram of a processing platform 900 configured to provide radiation-hardened error-tolerant memory according to one embodiment of the present disclosure. In some embodiments, the platform 900, or a portion thereof, may be hosted on or otherwise incorporated on an electronic system of a space-based or aerospace platform, including any type of data communication system, radar system, computing system, or embedded system for which enhanced radiation hardiness is particularly useful, but other applications (including ground applications) will also become apparent. The techniques disclosed may also be used to improve memory reliability in other platforms, including data communication devices, personal computers, workstations, laptop computers, tablets, touchpads, portable computers, handheld computers, cellular phones, smartphones, or messaging devices. Any combination of different devices may be used in some embodiments.

[0047]

[0055] In some embodiments, platform 900 may comprise any combination of a processor 120, memory 920, error-tolerant memory system 130, network interface 940, input / output (I / O) system 950, user interface 960, display element 964, and storage system 970. As will be further seen, a bus and / or interconnect 990 is also provided to enable communication between the various components listed above and / or other components not shown. Platform 900 may be coupled to network 994 through network interface 940 to enable communication with other computing devices, platforms, devices, or other resources to be controlled. In light of this disclosure, other components and functions not reflected in the block diagram of Figure 9 will become apparent, and it will be understood that other embodiments are not limited to a particular hardware configuration.

[0048]

[0056] The processor 120 can be any suitable processor and may include one or more coprocessors or controllers, such as an audio processor, a graphics processing unit, or a hardware accelerator, to assist in the execution of mission software associated with the platform 900 and / or any control and processing operations. In some embodiments, the processor 120 can be implemented as any number of processor cores. The processor (or processor core) can be any type of processor, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a graphics processor (GPU), a tensor processing unit (TPU), a network processor, a field-programmable gate array, or any other device configured to execute code. The processor can be a multithreaded core in that they may include two or more hardware thread contexts (or “logical processors”) per core. The processor 120 can be implemented as a composite instruction set computer (CISC) or a reduced instruction set computer (RISC) processor. In some embodiments, the processor 120 can be configured as an x86 instruction set compatible processor.

[0049]

[0057] Memory 920 that is not part of the error-tolerant memory system 130 may be implemented using any suitable type of digital storage, for example, flash memory and / or random access memory (RAM). In some embodiments, memory 920 may include various layers of memory hierarchy and / or memory cache, as known to those skilled in the art. Memory 920 may be implemented as a volatile memory device, such as RAM, dynamic RAM (DRAM), or static RAM (SRAM) devices, but is not limited to these. Storage system 970 may be implemented as a non-volatile storage device, such as one or more of hard disk drives (HDDs), solid-state drives (SSDs), universal serial bus (USB) drives, optical disc drives, tape drives, internal storage devices, accessory storage devices, flash memory, battery-backed synchronous DRAM (SDRAM), and / or network-accessible storage devices, but is not limited to these.

[0050]

[0058] The processor 120 may be configured to run an operating system (OS) 980 which may have any suitable operating system, such as Google Android® (Google Inc., Mountain View, CA), Microsoft Windows® (Microsoft Corp., Redmond, WA), Apple OS X (Apple Inc., Cupertino, CA), Linux®, or a real-time operating system (RTOS). As understood in light of this disclosure, the techniques provided herein may be implemented without regard to any particular operating system provided with platform 900, and therefore may also be implemented using any suitable existing or subsequently developed platform.

[0051]

[0059] The network interface circuit 940 may be any suitable network chip or chipset that enables wired and / or wireless connectivity between platform 900 and / or other components of network 994, thereby enabling platform 900 to communicate with other local and / or remote computing systems and / or other resources. Wired communication may conform to existing (or future to be developed) standards, such as Ethernet®. Wireless communication may conform to existing (or future to be developed) standards, such as cellular communication including LTE® (Long-Term Evolution) and 5G, Wireless Fidelity (Wi-Fi®), Bluetooth®, and / or near-field communication (NFC). Exemplary wireless networks include, but are not limited to, wireless local area networks, wireless personal area networks, wireless metropolitan area networks, cellular networks, and satellite networks.

[0052]

[0060] The I / O system 950 may be configured to interface with various I / O devices and other components of the platform 900. The I / O devices may include, but are not limited to, a user interface 960 and a display element 964. The user interface 960 may include devices (not shown) such as a touchpad, keyboard, and mouse, for example, to allow a user to control the system. The display element 964 may be configured to display information to the user. The I / O system 950 may include a graphics subsystem configured to perform image processing for rendering on the display element 964. The graphics subsystem may be, for example, a graphics processing unit or a visual processing unit (VPU). Analog or digital interfaces may be used to communicatively couple the graphics subsystem and the display element. For example, the interface may be a High Definition Multimedia Interface (HDMI®), DisplayPort, Wireless HDMI, and / or any other suitable interface using wireless high-definition compliant techniques. In some embodiments, the graphics subsystem may be integrated into the processor 120 of the platform 900 or any chipset.

[0053]

[0061] In some embodiments, it will be understood that various components of platform 900 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any preferred combination of hardware, firmware, or software.

[0054]

[0062] The error-tolerant memory system 130 is configured to provide radiation-hardened reliability for the memory using a spread-bit technique, as previously described. The error-tolerant memory system 130 may include any or all of the circuits / components shown in Figures 2 to 7, as described above. These components may be implemented or used together with various suitable software and / or hardware that are coupled to or otherwise form part of the platform 900. These components may be implemented or used together with user I / O devices that are capable of providing information to and receiving information and commands from the user, either as an addition or alternative.

[0055]

[0063] In various embodiments, platform 900 may be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, platform 900 may include components and interfaces suitable for communication over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, and control logic. Examples of a wireless shared medium may include a portion of the wireless spectrum, such as the radio frequency spectrum. When implemented as a wired system, platform 900 may include components and interfaces suitable for communication over a wired communication medium, such as input / output adapters, physical connectors for connecting the input / output adapters to the corresponding wired communication medium, network interface cards (NICs), disk controllers, video controllers, and audio controllers. Examples of a wired communication medium may include wires, cable metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pair wires, coaxial cables, and optical fibers.

[0056]

[0064] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices, digital signal processors, FPGAs, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and / or software elements may vary according to any number of factors, such as desired computation rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0057]

[0065] Some embodiments may be described using the expressions “joined” and “connected” along with their derivatives. These terms are not intended to be synonyms of each other. For example, some embodiments may be described using the terms “connected” and / or “joined” to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “joined” may also mean that two or more elements are not in direct contact with each other, but are still cooperating or interacting with each other. Some embodiments may be described using the expression “each.” This term is not limited to “each and every.”

[0058]

[0066] The various embodiments disclosed herein can be implemented in various forms of hardware, software, firmware, and / or dedicated processors. For example, in one embodiment, at least one non-temporary computer-readable storage medium has instructions encoded thereon, which, when executed by one or more processors, cause one or more of the methods disclosed herein to be implemented. The instructions can be encoded using a preferred programming language such as C, C++, Object-Oriented C, Java®, JavaScript®, Visual Basic.NET, Basic Basic for Beginners (BASIC), or alternatively, using a custom or proprietary instruction set. The instructions can be provided in the form of one or more computer software applications and / or applets that are tangibly embodied on a memory device and can be executed by a computer having any preferred architecture. In one embodiment, the system can be hosted on a given website and implemented, for example, using JavaScript or another preferred browser-based technology. For example, in some embodiments, the system can leverage processing resources provided by a remote computer system accessible via network 994. The computer software applications disclosed herein may include any number of different modules, submodules, or other components of distinct functions that may provide information to or receive information from other components. These modules may be used to communicate with input and / or output devices, such as, for example, a display screen, a touch-sensitive surface, a printer, and / or any other suitable device. In light of this disclosure, other components and functions not reflected in the figures will become apparent, and it will be understood that other embodiments are not limited to a particular hardware or software configuration. Accordingly, in other embodiments, platform 900 may have additional, fewer, or alternative sub-components compared to those included in the exemplary embodiment of Figure 9.

[0059]

[0067] The non-temporary computer-readable media described above may be any suitable medium for storing digital information, such as hard drives, servers, flash memory, and / or random access memory (RAM), or combinations of memories. In alternative embodiments, the components and / or modules disclosed herein may be implemented with hardware including gate-level logic such as field-programmable gate arrays (FPGAs), or alternatively, application-specific semiconductors such as application-specific integrated circuits (ASICs). Yet another embodiment may be implemented with a microcontroller having several input / output ports for receiving and outputting data, and several embedded routines for performing the various functions disclosed herein. It will be apparent that any suitable combination of hardware, software, and firmware may be used, and that other embodiments are not limited to a particular system architecture.

[0060]

[0068] Some embodiments may be implemented, for example, using machine-readable media or articles that, when performed by a machine, can store instructions or sets of instructions that cause the machine to perform the methods, processes, and / or operations according to those embodiments. Such machines may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, process, etc., and may be implemented using any suitable combination of hardware and / or software. Machine-readable media or articles may include, for example, memory, removable or non-removable media, erasable or non-erasable media, writable or rewritable media, digital or analog media, hard disks, floppy disks, compact disc read-only memory (CD-ROM), compact disc recordable (CD-R) memory, compact disc rewritable (CD-RW) memory, optical discs, magnetic media, magneto-optical media, removable memory cards or discs, various types of digital multipurpose discs (DVDs), tapes, cassettes, etc., and any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium, and / or storage unit. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, cryptographic code, etc., and may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0061]

[0069] Unless otherwise specified, terms such as “process,” “calculate,” “calculate,” and “determine” should be understood to refer to actions and / or processes of a computer or computing system, or similar electronic computing device, that manipulate and / or transform data represented as physical quantities (e.g., electrons) in the registers and / or memory units of a computer system into other data similarly represented as physical entities in the registers, memory units, or other such information storage transmissions or displays of a computer system. Embodiments are not limited in this context.

[0062]

[0070] As used in any embodiment herein, the terms “circuit” or “circuitry” are functional and may include, alone or in any combination, hardwired circuits, programmable circuits such as computer processors having one or more individual instruction processing cores, state-machine circuits, and / or firmware that stores instructions executed by programmable circuits. A circuit may include a processor and / or controller configured to execute one or more instructions to perform one or more operations described herein. Instructions may be embodied, for example, as applications, software, firmware, etc., configured to cause the circuit to perform any of the operations described herein. Software may be embodied as software packages, code, instructions, instruction sets, and / or data recorded on a computer-readable storage device. Software may be embodied or implemented to include any number of processes, and processes may be embodied or implemented to include any number of threads, etc., hierarchically. Firmware may be embodied as (e.g., non-volatile) code, instructions or instruction sets, and / or data hardcoded in a memory device. Circuits can be embodied collectively or individually as part of a larger system, such as an integrated circuit (IC), application-specific integrated circuit (ASIC), system-on-a-chip (SoC), desktop computer, laptop computer, tablet computer, server, or smartphone. Other embodiments may be implemented as software executed by a programmable control device. In such cases, the term “circuit” or “circuitry” shall include combinations of software and hardware, such as a programmable control device or processor capable of running software. Various embodiments, as described herein, may be implemented using hardware elements, software elements, or any combination thereof.Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and the like.

[0063]

[0071] Numerous specific details are provided herein to provide a complete understanding of the embodiments. However, it should be understood that other embodiments may be practiced without these specific details, or with a different set of details. Furthermore, it should be understood that certain structural and functional details disclosed herein represent exemplary embodiments and do not necessarily limit the scope of this disclosure. Moreover, while subject matter is described in language specific to structural features and / or methodological actions, it should be understood that subject matter as defined in the appended claims is not necessarily limited to specific features or actions described herein. Rather, certain features and actions described herein are disclosed as exemplary forms of implementing the claims.

[0064] Further exemplary embodiments

[0072] The following examples relate to further embodiments, from which numerous substitutions and configurations will become apparent.

[0065]

[0073] Example 1 is a memory unit comprising: a first plurality of random access memories (RAMs) configured to store data bits of data words written to the memory unit; a second plurality of RAMs configured to store bits of ECC codes, the data bits of which are distributed across the first plurality of RAMs; and each ECC code is associated with a unique group of data bits, and therefore the bits of each ECC code are distributed across the second plurality of RAMs.

[0066]

[0074] Example 2 includes the memory unit described in Example 1, wherein each of the RAMs in the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs in the second plurality of RAMs is configured to store four bits of the ECC code.

[0067]

[0075] Example 3 includes the memory unit described in Example 2, wherein the first multiple RAM has eight RAMs configured to store 32 of the data bits, and the second multiple RAM has five RAMs configured to store four 5-bit ECC codes.

[0068]

[0076] Example 4 includes the memory unit described in Example 2, wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits, and the second plurality of RAMs comprises 6 RAMs such that the memory unit is configured to store four 6-bit ECC codes.

[0069]

[0077] Example 5 includes the memory unit described in Example 2, wherein the first multiple RAM has 32 RAMs configured so that the memory unit stores 128 of the data bits, and the second multiple RAM has 7 RAMs configured so that the memory unit stores four 7-bit ECC codes.

[0070]

[0078] Example 6 includes a memory unit as described in any of Examples 1-5, wherein the ECC code is configured to detect and correct single-bit errors in groups of data bits and to detect double-bit errors in groups of data bits.

[0071]

[0079] Example 7 includes the memory unit described in any of Examples 1 to 5, further comprising a reporting circuit configured to report single-bit error correction or double-bit error detection resulting from a read operation on the memory unit.

[0072]

[0080] Example 8 includes a memory unit as described in any of Examples 1-5, wherein the ECC code is Hamming code.

[0073]

[0081] Example 9 includes a memory unit as described in any of Examples 1-5, where the ECC code is of length log2(N)+2 bits, where N is the number of bits in a group of data bits.

[0074]

[0082] Example 10 is an error-tolerant memory system comprising one or more of the memory units described in Example 1.

[0075]

[0083] Example 11 is a processing system comprising at least one processor configured to run mission software, and an error-tolerant memory system coupled to the processor and comprising one or more memory units, wherein the memory units are configured to store data words written to the memory system by the processor, and the memory units comprise a first plurality of random access memories (RAMs) configured to store data bits of data words, a second plurality of RAMs configured to store bits of ECC codes, the data bits of which are distributed across the first plurality of RAMs, and each ECC code is associated with a unique group of data bits, so that the bits of each ECC code are distributed across the second plurality of RAMs.

[0076]

[0084] Example 12 includes the processing system described in Example 11, wherein each of the RAMs in the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs in the second plurality of RAMs is configured to store four bits of the ECC code.

[0077]

[0085] Example 13 includes the processing system described in Example 12, wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits, and the second plurality of RAMs comprises five RAMs such that the memory unit is configured to store four ECC codes of length 5 bits.

[0078]

[0086] Example 14 includes the processing system described in Example 12, wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits, and the second plurality of RAMs comprises 6 RAMs such that the memory unit is configured to store four 6-bit ECC codes.

[0079]

[0087] Example 15 includes the processing system described in Example 12, wherein the first plurality of RAMs comprises 32 RAMs such that each memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprises 7 RAMs such that each memory unit is configured to store four 7-bit ECC codes.

[0080]

[0088] Example 16 includes a processing system according to any one of Examples 11 to 15, further comprising a reporting circuit configured to report single-bit error correction or double-bit error detection resulting from read operations on the memory unit to the processor.

[0081]

[0089] Example 17 is a method for providing radiation-hardened memory, the method comprising: storing data bits in a first plurality of random access memories (RAMs) of a memory unit; generating error correction codes (ECC codes) in which the data bits are distributed across the first plurality of RAMs; and storing bits of the ECC codes in a second plurality of RAMs of a memory unit, in which each of the ECC codes is associated with a unique group of data bits, so that the bits of the ECC codes are distributed across the second plurality of RAMs.

[0082]

[0090] Example 18 includes the method of Example 17, wherein each of the RAMs in the first plurality of RAMs is configured to store four data bits, and each of the RAMs in the second plurality of RAMs is configured to store four bits of ECC code.

[0083]

[0091] Example 19 includes the method of Example 18, wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits, and the second plurality of RAMs comprises five RAMs such that the memory unit is configured to store four ECC codes of length 5 bits.

[0084]

[0092] Example 20 includes the method of any of Examples 17-19, wherein the ECC code is configured to detect and correct single-bit errors in a group of data bits and to detect double-bit errors in a group of data bits, and the method further comprises reporting single-bit error correction or double-bit error detection resulting from a read operation on a memory unit.

[0085]

[0093] The terms and expressions used herein are for illustrative purposes only, not limitation, and in using such terms and expressions, there is no intention to exclude equivalents (or parts thereof) of the features shown and described, and it should be recognized that various modifications are possible within the claims. Accordingly, the claims shall cover all such equivalents. Various features, aspects, and embodiments have been described herein. These features, aspects, and embodiments are, as will be understood in light of this disclosure, possible to combine with one another, as well as to be modified and altered. Accordingly, this disclosure should be considered to encompass such combinations, modifications, and alterations. The scope of this disclosure shall not be limited by this detailed description, but by the claims attached herein. Future applications claiming priority to this application may claim the disclosed subject matter in different ways and may generally include any set of one or more elements that are variously disclosed or otherwise shown herein.

Claims

1. A memory unit, A first plurality of random access memories (RAMs) configured to store the data bits of a data word written to the memory unit, and the data bits are distributed across the first plurality of RAMs. A second plurality of RAMs configured to store bits of an ECC code, each ECC code associated with a unique group of data bits, and thus the bits of each ECC code are distributed across the second plurality of RAMs. A memory unit equipped with the following features.

2. The memory unit according to claim 1, wherein each of the first plurality of RAMs is configured to store four of the data bits, and each of the second plurality of RAMs is configured to store four bits of the ECC code.

3. The memory unit according to claim 2, wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits, and the second plurality of RAMs comprises five RAMs such that the memory unit is configured to store four ECC codes of length 5 bits.

4. The memory unit according to claim 2, wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits, and the second plurality of RAMs comprises 6 RAMs such that the memory unit is configured to store 4 ECC codes of length 6 bits.

5. The memory unit according to claim 2, wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprises 7 RAMs such that the memory unit is configured to store four ECC codes of length 7 bits.

6. The memory unit according to claim 1, wherein the ECC code is configured to detect and correct single-bit errors in the group of data bits and to detect double-bit errors in the group of data bits.

7. The memory unit according to claim 1, further comprising a reporting circuit configured to report single-bit error correction or double-bit error detection arising from a read operation on the memory unit.

8. The memory unit according to claim 1, wherein the ECC code is a Hamming code.

9. The aforementioned ECC code is length log 2 The memory unit according to claim 1, wherein it is of (N) + 2 bits, where N is the number of bits in the group of data bits.

10. An error-tolerant memory system comprising one or more of the memory units described in claim 1.

11. A processing system, At least one processor configured to run mission software, Coupled with the aforementioned processor, an error-tolerant memory system comprising one or more memory units: The memory unit is configured to store data words written to the memory system by the processor, and the memory unit is A first plurality of random access memories (RAMs) configured to store the data bits of the data word, and the data bits are distributed across the first plurality of RAMs. A second plurality of RAMs configured to store bits of an ECC code, each ECC code associated with a unique group of data bits, and thus the bits of each ECC code are distributed across the second plurality of RAMs. A processing system equipped with the following features.

12. The processing system according to claim 11, wherein each of the RAMs in the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs in the second plurality of RAMs is configured to store four bits of the ECC code.

13. The processing system according to claim 12, wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits, and the second plurality of RAMs comprises five RAMs such that the memory unit is configured to store four ECC codes of length 5 bits.

14. The processing system according to claim 12, wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits, and the second plurality of RAMs comprises 6 RAMs such that the memory unit is configured to store 4 ECC codes of length 6 bits.

15. The processing system according to claim 12, wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprises 7 RAMs such that the memory unit is configured to store four 7-bit ECC codes.

16. The processing system according to claim 11, further comprising a reporting circuit configured to report single-bit error correction or double-bit error detection arising from a read operation on the memory unit to the processor.

17. A method for providing radiation-hardened memory, wherein the method is The data bits are stored in a first plurality of random access memories (RAMs) of a memory unit, and the data bits are distributed across the first plurality of RAMs. The process involves generating error correction codes (ECC codes) and each of the ECC codes being associated with a unique group of data bits. The bits of the ECC code are stored in a second plurality of RAMs of the memory unit, and therefore the bits of the ECC code are distributed across the second plurality of RAMs. A method that includes [a certain feature].

18. The method according to claim 17, wherein each of the first plurality of RAMs is configured to store four data bits, and each of the second plurality of RAMs is configured to store four bits of the ECC code.

19. The method according to claim 18, wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits, and the second plurality of RAMs comprises five RAMs such that the memory unit is configured to store four ECC codes of length 5 bits.

20. The method according to claim 17, wherein the ECC code is configured to detect and correct single-bit errors in the group of data bits and to detect double-bit errors in the group of data bits, and the method further comprises reporting single-bit error correction or double-bit error detection resulting from a read operation on the memory unit.

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