Two-level binning using delayed attribute shading

JP2026521139APending Publication Date: 2026-06-26ADVANCED MICRO DEVICES INC
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Patent Information

Application Number
JP2025570679
Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Priority Date
2023-06-09
Filing Date
2024-06-05
Publication Date
2026-06-26

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Abstract

An Accelerated Processing Unit (APU)[114] is configured to perform one or more attribute shading operations in the fragment shader[358]. For this purpose, the APU includes a processor core[116] configured to assemble one or more primitives from the generated vertex shading data[315]. The processor core culls one or more primitives to produce a set of residual primitives and identifies the primitives of the set of residual primitives that are visible in the bin. The processor core then provides the fragment shader with data[335] that identifies the visible primitives in the bin. Based on the data that identifies the visible primitives in the bin, the fragment shader generates attribute shading data[345] for each visible primitive in the bin.
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