Detecting stuck data lines on a serial data bus

Abstract

A controller is provided that includes an SDA line interface for connecting the controller to the serial data (SDA) line of a two-wire shared serial data bus. The controller includes processing circuitry for sampling the SDA line to obtain samples of the voltage level on the SDA line and monitoring the samples. The processing circuitry detects a predetermined number of consecutive samples from the monitored samples that are at a low voltage level without a low-to-high transition in the voltage level. Based on the detected predetermined number of consecutive samples from the monitored samples, the processing circuitry indicates a stacked SDA state.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to Indian Patent Application No. 202341041041, filed on June 16, 2023, entitled "Detection of a Stuck Data Line of a Serial Data Bus", and U.S. Patent Application No. 18 / 514,639, filed on November 20, 2023, entitled "Detection of a Stuck Data Line of a Serial Data Bus", the contents of which are hereby incorporated by reference in their entirety.

[0002] (Field of the Invention) This disclosure generally relates to serial communication, and more particularly to the detection of a stuck data line on a serial data bus.

Background Art

[0003] Serial communication has played an important role in facilitating communication between chips within an electronic system. This involves transmitting data sequentially bit - by - bit via a communication link between devices. This approach offers advantages such as simplicity, fewer pin counts, and the ability to transmit data over longer distances compared to parallel communication.

[0004] One common serial communication protocol is Inter-Integrated Circuit (I2C), developed in the early 1980s by Philips Semiconductor (now NXP Semiconductors). I2C is a two-wire bus protocol that enables multiple devices to communicate with each other using shared serial data (SDA) and serial clock (SCL) lines. It supports a controller-target (master-slave) architecture, where a controller device initiates and controls communication, and target devices respond to commands or requests from the controller. I2C is commonly used to connect various devices in embedded systems, consumer electronics, and computer peripherals.

[0005] As technology advances and the need for higher data transfer rates, increased flexibility, and improved power efficiency arises, the MIPI Alliance has developed Improved Inter-Integrated Circuit (I3C). Introduced in 2017, I3C builds on the strengths of I2C while offering enhanced and additional features. I3C is backward compatible with I2C, allowing I2C devices to coexist on the same data bus, resulting in higher data transfer rates, increased flexibility for connecting multiple devices, multi-controller support, hot-join capabilities, dynamic address assignment, in-band interrupts, and other improvements. I3C has gained popularity in applications such as smartphones, tablets, Internet of Things (IoT) devices, and automotive systems.

[0006] Serial communication protocols such as I2C and I3C have become essential for inter-chip communication within electronic systems. They enable devices to exchange data, commands, and control signals efficiently and reliably. These protocols are widely adopted and standardized, enabling interoperability between devices from different manufacturers and simplifying the integration of various components within electronic systems. The continuous evolution and development of serial communication protocols contribute to advancements in inter-chip communication and the seamless operation of modern electronic devices. [Overview of the Initiative]

[0007] In I3C, the SDA and SCL lines are expected to be pulled high by the controller during bus idle under normal data bus function. However, during read / write transactions, a stuck SDA condition can occur if, for some reason, a target on the data bus drives the SDA line low for a period of time without releasing it, even though the controller supplies the clock by toggling the SCL line. A stuck SDA condition can hinder further communication from the controller to the target via the data bus. Therefore, the controller needs to detect the stuck SDA condition so that it can implement a recovery method to recover from it.

[0008] Therefore, exemplary implementations of this disclosure relate to the detection of stacked data lines on a data bus for serial communication, such as an I3C data bus. This disclosure includes, without limitation, the following exemplary embodiments.

[0009] Some exemplary implementations provide a controller comprising an SDA line interface for connecting the controller to a serial data (SDA) line of a two-wire shared serial data bus, and a processing circuit, the processing circuit comprising at least sampling the SDA line to obtain a sample of the voltage level on the SDA line, monitoring the sample, detecting a predetermined number of consecutive samples from the monitored sample that are at a low voltage level with no low-to-high transition in the voltage level, and indicating a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored sample.

[0010] Some exemplary implementations provide a method that includes sampling the serial data (SDA) line of a two-wire shared serial data bus to obtain a sample of the voltage level on the SDA line; monitoring the sample; detecting a predetermined number of consecutive samples from the monitored sample that are at a low voltage level without a low-to-high transition in the voltage level; and indicating a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored sample.

[0011] These and other features, aspects, and advantages of the Disclosure will become apparent from reading the following detailed description together with the accompanying drawings, which are briefly described below. The Disclosure includes any combination of two, three, four, or more features or elements described herein, whether such features or elements are expressly combined or otherwise enumerated in the specific exemplary implementations described herein. The Disclosure is intended to be read holistically so that any separable feature or element of the Disclosure should be considered combinable in any aspect or exemplary implementation unless the context of the Disclosure expressly indicates otherwise.

[0012] Therefore, it will be understood that this “Summary of the Invention” is provided solely for the purpose of summarizing some exemplary implementations in order to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be understood that the above-described exemplary implementations are merely examples and should not be interpreted in any way as narrowing the scope or spirit of the present disclosure. Other exemplary implementations, aspects, and advantages will become apparent from understanding the following detailed description in conjunction with the accompanying diagrams illustrating the principles of some of the described exemplary implementations.

[0013] While the exemplary implementations of this disclosure have been described above using general terminology, we now refer to the attached drawings, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0014] [Figure 1] The controller is shown in several exemplary implementation forms of the disclosure. [Figure 2] The system, including the controller shown in Figure 1, is shown in several exemplary implementation configurations. [Figure 3] This document illustrates a system that can correspond to the system shown in Figure 2, including multiple controllers and targets, in several exemplary implementation configurations. [Figure 4A] Figure 2 shows the timing diagram of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and resume conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 4B] Figure 2 shows the timing diagram of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and resume conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 4C]Figure 2 shows the timing diagram of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and resume conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 5] This is a functional block diagram of a stacked SDA state detector that can be implemented by the controller shown in Figure 1, in several exemplary implementation configurations. [Figure 6A] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6B] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6C] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6D] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6E] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6F] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6G] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6H] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6I] This is a flowchart showing the various steps in different exemplary implementations of the method. [Modes for carrying out the invention]

[0015] Some implementations of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, implementations of the disclosure are shown. In fact, the various implementations of the present disclosure may be embodied in many different forms and should not be construed as limited to the implementations set forth herein. Rather, these exemplary implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout, like reference numerals refer to like elements.

[0016] Unless otherwise specified or clear from the context, references to first, second, etc. should not be construed as meaning a particular order. Features described as being above another feature (unless otherwise specified or clear from the context) may instead be below, and vice versa, and similarly, features described as being to the left of another feature may instead be to the right, and vice versa. Also, although this specification may refer to quantitative measures, values, geometric relationships, etc., unless otherwise specifically stated, all or any one or more of these may be approximations to account for possible tolerances, such as those resulting from engineering tolerances.

[0017] As used herein, unless otherwise specified or clear from the context, “or” of a set of operands is an “inclusive logical disjunction” such that, in contrast to an “exclusive logical disjunction” which is false when all of the operands are true, it is true only when one or more of the operands are true. Thus, for example, “[A] or [B]” is true when [A] is true, or when [B] is true, or when both [A] and [B] are true. Further, the articles “a” and “an” mean “one or more” unless otherwise specified or clear from the context that the singular is intended. Further, it should be understood that the terms “data,” “content,” “digital content,” “information,” and similar terms may sometimes be used interchangeably unless otherwise specified.

[0018] Furthermore, while this specification may refer to terminology specific to particular systems or architectures, it should be understood that the exemplary implementations described herein may be equally applicable to any of several systems and architectures. In this regard, some exemplary implementations may be described in the context of serial communication standards for inter-chip communication, such as I3C and its predecessor, I2C. However, it should be understood that the exemplary implementations may be equally applicable to other serial communication standards.

[0019] The exemplary implementations of this disclosure generally relate to serial communication, and more specifically to the detection of stacked data lines on a serial data bus.

[0020] Figure 1 shows a controller 100 in several exemplary implementations of the present disclosure. The controller may be an electronic device such as an integrated circuit (IC). The controller includes, but is not limited to, processing circuits 102 such as a general-purpose or dedicated processor, microprocessor, controller, or microcontroller. The controller may also include one or more interfaces for connecting the controller to a data bus from which the controller can communicate with other electronic devices. In the context of serial communication standards such as I2C and I3C, the data bus may be a two-wire shared serial data bus 104. In this regard, the data bus may include serial data (SDA) lines 104A used to transmit and receive data between electronic devices connected to the data bus, and the controller may include an SDA line interface 106 for connecting the controller to the SDA lines 104A.

[0021] Figure 2 shows a system 200 including a controller 100 in some exemplary implementations of the present disclosure. As shown, the system includes several electronic devices 202, such as ICs, connected to a data bus 104. In addition to the SDA line 104A, the data bus may include an SCL line 204B that provides a clock signal used to synchronize data transfers between the electronic devices. In some examples, the controller may also include an SCL line interface (not shown) for connecting the controller 100 to the SCL line 204B.

[0022] System 200 can operate according to a controller-target architecture in which an electronic device 202 can function as a controller 100 that initiates and controls communication (timing and data) on a data bus 104, and another electronic device 202 can function as a target 208 that responds to commands or requests from the controller. In some examples, the system can support multiple controllers and targets.

[0023] Figure 3 shows a system 300 that may correspond to system 200 in Figure 2, including multiple controllers and targets in several exemplary implementation forms. As shown, for example, system 300 may include a primary controller 100A and one or more secondary controllers 100B, any one of which may be the active controller currently controlling the data bus 104 at any given time. Primary controller 100A can initialize the data bus 104 and perform configuration of target 208. In its initial state, primary controller 100A acts as the authority for the data bus 104, and once the data bus is configured, it may become the first active controller. Secondary controller 100B may initially function as the target, but secondary controller 100B can accept controllership from the active controller and become the new active controller. In the context of I3C, the system may include an I3C primary controller 100A and one or more I3C secondary controllers 100B.

[0024] System 300 may also include one or more targets 208. The system may also include one or more legacy targets 304 from previous communication standards to which System 300 may conform. In this case as well, in the context of I3C, the system may include one or more I3C targets 208, and the system may include one or more I2C targets 304.

[0025] Returning to Figure 2, the system 200 may support multiple data transfer modes, allowing electronic devices 202 to communicate at different speeds based on their capabilities. The modes may include single data rate (SDR) mode and several high data rate (HDR) modes, along with increasing data transfer rates and corresponding signal integrity requirements. In particular, SDR mode may be used for several purposes, such as performing private messaging from controller 100 to target 208, and for entering other modes and states (e.g., HDR mode). In the context of I3C, SDR mode may be used to implement built-in I3C features such as common command code (CCC), in-band interrupt (IBI), and hot joins. SDR mode may also be used to transition from I2C to I3C through dynamic address assignment, and for executing legacy I2C transactions on data bus 104.

[0026] The electronic device 202 can operate in various output modes to drive signals on the data bus 104. Examples of appropriate modes include open-drain mode and push-pull mode, which define how the electronic device controls the voltage levels on the SDA line 104A and the SCL line 204B. In open-drain mode, the electronic device may be configured as open-drain or open-collector at its output. In open-drain mode, the electronic device can pull the signal line (SDA or SCL) to a low voltage level (logic 0) by actively sinking current, while an external pull-up resistor may be used to pull the line to a high voltage level (logic 1). In push-pull mode, the electronic device may be configured as a push-pull driver at its output. In push-pull mode, the electronic device can actively drive both high (logic 1) and low (logic 0) voltage levels on the signal line.

[0027] Figures 4A, 4B, and 4C are timing diagrams of signals on SDA line 104A and SCL line 204B for read / write transactions on data bus 104, in several exemplary implementations. As shown in Figure 4A, a read / write transaction on the data bus can be initiated with an initiated state, which can be implemented as a high-to-low transition on SDA line 104A while asserted by controller 100 and SCL line 204B is kept high. Similarly, a read / write transaction on the data bus can be terminated with a stop condition asserted by the controller. The stop condition can be implemented as a low-to-high transition on SDA line 104A while SCL line 204B is kept high. As an alternative to a stop condition, a resume condition may allow multiple messages to be sent within the same frame without the need to send stop and start signals between messages. A resume condition may look the same as an initiated condition on data bus 104.

[0028] Following the start / restart conditions, a read / write transaction on data bus 104 may include an address header that may contain the destination address, indicate the read or write transaction, and provide an acknowledgment. The address header may be transmitted on SDA line 104A during the period when SCL line 204B is transitioning from low to high (rising edge) or high to low (falling edge). Figure 4B is a timing diagram of SDA line 104A and SCL line 204B for the address header (in push-pull mode) in several exemplary implementations. In the context of I2C and I3C, the address header may include seven address bits, indicated as A6, A5...A0, one read / write (R / W) bit, and one acknowledgment (ACK) / non-acknowledgment (NACK) bit. In the context of I3C, the R / W bit is

[0029]

number

[0030] Once controller 100 transmits the address and R / W bits of the address header on data bus 104, the controller can wait for target 208 to acknowledge (or not acknowledge) the request. This can be done through the ACK / NACK bits in the address header. The target may pull SDA line 104A low (ACK / NACK bits = 0) to respond with an acknowledgment (ACK), or release the SDA line high (ACK / NACK bits = 1) to respond with a negation (NACK).

[0031] As shown in Figure 4C, one or more data words may follow the address header, as indicated by D7, D6...D0. Similar to the address header, data words can be transmitted on the SDA line 104A during periods when the SCL line 204B is transitioning from low to high (rising edge) or high to low (falling edge). In the context of I3C, a data word may be 9 bits wide, containing 8 bits of data and a 9th transition bit (T bit). When the controller 100 is writing data to the target 208, the T bit of each data word may be a parity bit calculated using odd parity, which helps in detecting noise-induced errors on the data bus. Conversely, when the controller 100 is reading data returned from the target 208, the T bit of each data word may represent a data end bit. To terminate a message, the target may return the T bit as "0". To continue a message, the target 208 may return the T bit as "1" and monitor the SDA line 104A. If SDA line 104A remains high on the next falling SCL edge, target 208 may continue to transmit the next data value. If SDA line 204B is low on the next falling SCL edge (restart), controller 100 has stopped data transmission, and target 208 will not transmit any further data.

[0032] The electronic device 202 may implement one or more error detection and recovery methods to handle various error conditions during read / write transactions on the data bus 104. In this regard, in the context of I3C, there is an error condition in which, even when the controller 100 expects the SDA line 104A to be released, the target 208 driving the SDA line 104A on the data bus 104 may continue to drive the SDA line 104A. This error condition may occur, for example, during a read transaction or acknowledgment (ACK) due to a clock cycle miss. In the Management Component Transport Protocol (MCTP) I3C Transport Binding Specification (DSP0233) issued by the Distributed Management Task Force (DMTF), this error condition is called the "stuck SDA" condition.

[0033] According to some exemplary implementations of this disclosure, the controller 100 may detect a stacked SDA state during a read / write transaction on the data bus 104 and implement a recovery method for recovering from the stacked SDA state. In some examples, the stacked SDA state may be characterized as the target 208 maintaining the SDA line 104A at a low voltage level (logical 0). To detect the stacked SDA state during a read / write transaction, the controller 100 may take a sample of the voltage level on the SDA line 104A, monitor the sample, and detect a predetermined number of consecutive samples that are at a low voltage level, i.e., there is no transition from low to high (rising edge) of the voltage level, i.e., the SDA line 104A is maintained at a constant low (this indicates a stacked SDA state).

[0034] As shown in Figure 1, for example, the processing circuit 102 of the controller 100 can sample the SDA line 104A to obtain a sample 108 of the voltage level 110 on the SDA line 104 and monitor the sample 108. In some examples, the processing circuit 102 can filter out noise in the voltage level on the SDA line 104A, and the voltage level 110 can be sampled from the filtered voltage level. The processing circuit 102 can detect a predetermined number of consecutive samples from the monitored samples that are at a low voltage level without a low-to-high transition in the voltage level. The processing circuit 102 can indicate a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored samples, such as by generating a stacked SDA status or interrupt to indicate a stacked SDA state. The processing circuit 102 can then perform at least one action to recover from the stacked SDA state.

[0035] In some examples, the processing circuit 102 may monitor adjacent samples among the samples 108 and detect a high-to-low (falling edge) transition at the voltage level 110 of the monitored adjacent sample. In some of these examples, the processing circuit 102 may set a flag based on the detected high-to-low transition and retain the set flag for consecutive samples at the low voltage level among the monitored sample. Similarly, the processing circuit 102 may detect a low-to-high (rising edge) transition at the voltage level of the monitored adjacent sample, de-set a flag based on the detected low-to-high transition, and retain the de-set flag for consecutive samples at the high voltage level among the monitored sample. The terms “set” and “de-set” mean one or more predefined distinct states of bits, without any restriction on whether the set indicates a “1” state or a “0” state.

[0036] In some examples, the processing circuit 102 can detect a predetermined number of consecutive samples from the monitored samples 108 that are at a low voltage level without a low-to-high transition (indicating a stacked SDA state) based on the flag. In this regard, the processing circuit 102 may sample the flag and monitor the flag samples to obtain samples of the flag. The processing circuit may then detect a threshold number of consecutive samples from the monitored samples of the flag that have the flag set, and the threshold number of consecutive samples from the monitored samples of the flag corresponds to a predetermined number of consecutive samples from the monitored samples 108 at a voltage level 110 on the SDA line 104A.

[0037] In some examples where the data bus 104 includes an SCL line 204B for a clock signal, the processing circuit 102 may sample the flag over each clock period of a reference clock having a frequency higher, equal to, or lower than the frequency of the clock signal on the SCL line 204B. Sampling the flag using a reference clock at a frequency lower than the clock signal on the SCL line 204B may save power compared to sampling the flag at a frequency higher than or equal to the clock signal on the SCL line 204B. In some examples, the threshold number of consecutive samples among the monitored samples 108 of the flag may be represented by a predetermined number of clock periods set to be equal to a predetermined period. In a more specific embodiment where the data bus 104 is an I3C data bus with a 12.5 MHz clock signal on the SCL line 204B, a 32 kHz reference clock may be used to save counter bits and power while detecting a predetermined time period of 30 milliseconds without rising edge transitions.

[0038] To further illustrate some exemplary implementations of the present disclosure, Figure 5 is a functional block diagram of a stacked SDA state detector 500, which may be implemented by a controller 100 (e.g., a processing circuit 102). As shown, the detector includes a glitch filter 502, sample-and-hold logic 504, and detection logic 506. The glitch filter 502 (sometimes called a spike filter) can receive an input (SDA_IN) from the SDA line 104A, filter out unwanted noise on the SDA line 104A, and generate a filtered input (FILTERED_SDA). In this regard, the glitch filter can suppress high-frequency voltage changes on the SDA line 104A.

[0039] The sample-and-hold logic 504 may sample the SDA line 104A asynchronously or synchronously to obtain a sample of the voltage level on the SDA line 104A so that it may be filtered by the glitch filter 502. The sample-and-hold logic 504 may monitor the sample and flag any falling edge transitions in the voltage level. In some examples, the sample-and-hold logic may set a flag (sometimes called an SDA transition flag) when a falling edge transition of the voltage level on the SDA line 104A is detected in the sample. Conversely, the sample-and-hold logic may deset the SDA transition flag to indicate when a rising edge transition of the voltage level on the SDA line is detected in the sample.

[0040] The detection logic 506 samples the SDA transition flag at a reference clock frequency, thereby capturing any falling edge transitions in the voltage level on the SDA line 104A over one clock cycle of the reference clock. The detection logic 506 counts or otherwise tracks the number of consecutive occurrences in which the SDA transition flag is set, and can reset the count / number when the SDA transition flag is deset. Since the detection logic 506 tracks the number of consecutive occurrences in which the SDA transition flag is set, it can detect a stacked SDA state when the number of consecutive occurrences in which the SDA transition flag is set reaches a threshold number of consecutive occurrences, the threshold number may be programmable. The detection logic 506 may then generate a stacked SDA status or interrupt to indicate that a stacked SDA state has been encountered.

[0041] In some examples, the detection logic 506 may sample the SDA transition flag over each clock period of a reference clock. The reference clock may be set to a reference clock frequency that is higher than, equal to, or lower than the frequency of the clock signal on the SCL line 204B. In some more specific examples, the reference clock frequency may be lower than the frequency of the clock signal on the SCL line 204B. The threshold number (the number of consecutive occurrences in which the SDA transition flag is set is compared) may similarly be expressed in clock periods of the reference clock. In some examples, the threshold number may be programmed to a value ranging from 1 clock period to a number of clock periods equal to a given period (e.g., 5 seconds).

[0042] In response to a stacked SDA status or interrupt, the controller 100 may implement a recovery method to recover. For example, the controller 100 may attempt the following sequence in SDR mode with early termination as soon as the SDA line 104A goes high, followed by a stop condition. The controller 100 may drive one clock cycle (up to 8) at a time on the SCL line 204B, which may cause the target 208 to drive the SDA line 104A high for the duration of the 9th T bit. The controller monitors for the SDA line 104A to go high and, in the case of a read transaction, may stop the read by driving the SDA line 104A low when the SCL line 204B is high. If the above does not allow recovery from the stacked SDA state, the controller 100 may hold a voltage level (high or low) on the SCL line 204B for a period of time (e.g., 150 μs). In some of these situations, target 208 may implement a detector that determines whether SCL line 204B has not changed for at least a short time (e.g., 200 μs or more), and switch the target 208 interface to SDA line 204B to high impedance (high Z) to release SDA line 104A and wait for restart or shutdown.

[0043] Figures 6A to 6I are flowcharts showing various steps of Method 600 in various exemplary implementations. The Method includes sampling the Serial Data (SDA) line of a two-wire shared serial data bus to obtain a sample of the voltage level on the SDA line, as shown in block 602 of Figure 6A. The Method includes monitoring the samples, as shown in block 604. The Method includes detecting a predetermined number of consecutive samples from the monitored samples that are at a low voltage level without a low-to-high transition in the voltage level, as shown in block 606. The Method then includes indicating a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored samples, as shown in block 608.

[0044] In some examples, method 600 includes filtering out noise in the voltage level on the SDA line, as shown in block 610 of Figure 6B. In some of these examples, the SDA line is sampled from the filtered voltage level in block 602.

[0045] In some examples, monitoring a sample in block 604 includes monitoring adjacent samples among the samples, as shown in block 612 of Figure 6C. In some of these examples, method 600 includes detecting high-to-low transitions in the voltage levels of adjacent samples being monitored, as shown in blocks 614 and 616, and setting a flag based on the detected high-to-low transitions. In some of these examples, a predetermined number of consecutive samples among the monitored samples that are at a low voltage level without any low-to-high transitions are detected in block 606 based on the flag.

[0046] In some of these examples, method 600 includes setting a flag based on a detected high-to-low transition, as shown in block 618 of Figure 6D, and then retaining the set flag for consecutive samples that are at a low voltage level among the monitored samples.

[0047] In some examples, monitoring a sample in block 604 involves detecting a low-to-high transition in the voltage level of an adjacent sample being monitored, as shown in block 620 of Figure 6E. In some of these examples, monitoring a sample also involves unflagging based on the detected low-to-high transition, as shown in block 622.

[0048] In some examples, method 600 includes, as shown in block 624 of Figure 6F, keeping the flag unset for consecutive samples among the monitored samples that are at a high voltage level after the flag has been unset based on a detected low-to-high transition.

[0049] In some examples, in block 606, detecting a predetermined number of consecutive samples from the monitored samples that are at a low voltage level without a low-to-high transition includes sampling the flag and obtaining a sample of the flag, as shown in block 626 of Figure 6G. Method 600 includes monitoring a sample of the flag, as shown in block 628. The method then includes detecting a threshold number of consecutive samples from the monitored samples of the flag that are set, as shown in block 630, where the threshold number of consecutive samples from the monitored samples of the flag corresponds to a predetermined number of consecutive samples from the monitored samples of the voltage level on the SDA line.

[0050] In some examples, a two-wire shared serial data bus includes a serial clock (SCL) line for the clock signal, and the flag is sampled in block 626 over each clock period of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line.

[0051] In some examples, the flag is sampled in block 626 over each clock period of the reference clock, and the threshold number of consecutive samples among the monitored samples of the flag is represented by a predetermined number of clock periods set to be equal to a predetermined period.

[0052] In some examples, indicating a stack SDA state in block 608 involves generating a stack SDA status or interrupt to indicate a stack SDA state, as shown in block 632 of Figure 6G.

[0053] In some examples, method 600 includes performing at least one action to recover from the stack SDA state, as shown in block 634 of Figure 6I.

[0054] As described above and repeated below, this disclosure includes, without limitation, the following exemplary implementations.

[0055] Clause 1. A controller comprising an SDA line interface for connecting the controller to a serial data (SDA) line of a two-wire shared serial data bus, and a processing circuit, wherein the processing circuit samples the SDA line to obtain a sample of the voltage level on the SDA line, monitors the sample, detects a predetermined number of consecutive samples from the monitored sample that are at a low voltage level with no low-to-high transition in the voltage level, and indicates a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored sample.

[0056] Clause 2. The controller according to Clause 1, comprising a processing circuit for filtering out noise in the voltage level on the SDA line, wherein the SDA line is sampled from the filtered voltage level.

[0057] The controller according to Clause 3, wherein the processing circuit for monitoring samples includes a processing circuit for monitoring adjacent samples among the samples, detecting high-to-low transitions in the voltage level of the monitored adjacent samples among the samples, and setting a flag based on the detected high-to-low transition, wherein a predetermined number of consecutive samples among the monitored samples that are at a low voltage level and have no low-to-high transitions in voltage are detected based on the flag.

[0058] Clause 4. The processing circuit is the controller described in Clause 3, which maintains a flag set for consecutive samples that are at a low voltage level among the monitored samples.

[0059] Clause 5. A controller according to Clause 3 or Clause 4, which includes a processing circuit for monitoring samples, which detects a low-to-high transition in the voltage level of an adjacent sample being monitored among the samples, and for unsetting a flag based on the detected low-to-high transition.

[0060] Clause 6. The controller described in Clause 5, which has a processing circuit that keeps the flag unset for consecutive samples among the monitored samples that are at a high voltage level.

[0061] Clause 7. A controller according to any one of Clauses 3 to 6, for detecting a predetermined number of consecutive samples of monitored samples that are at a low voltage level without a low-to-high transition, comprising a processing circuit for sampling a flag to obtain a sample of the flag, monitoring the sample of the flag, and detecting a threshold number of consecutive samples of monitored samples of the flag that have the flag set, wherein the threshold number of consecutive samples of monitored samples of the flag corresponds to a predetermined number of consecutive samples of the voltage level on the SDA line.

[0062] A wired shared serial data bus, as defined in Clause 8.2, includes a serial clock (SCL) line for a clock signal, and the processing circuit samples a flag over each clock period of a reference clock having a frequency greater than or equal to the frequency of the clock signal on the SCL line, as described in Clause 7.

[0063] A wired shared serial data bus includes a serial clock (SCL) line for a clock signal, and the processing circuit samples a flag over each clock period of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line, as described in Clause 7 or Clause 8 of the controller.

[0064] Clause 10. A controller according to any one of Clauses 7 to 9, wherein the processing circuit samples a flag over each clock period of a reference clock, and the threshold number of consecutive samples of the monitored samples of the flag is represented by a predetermined number of clock periods set to be equal to a predetermined period.

[0065] Clause 11. A controller according to any one of Clauses 1 to 10, which includes a processing circuit for generating a stack SDA status or interrupt indicating a stack SDA state.

[0066] Clause 12. A controller according to any one of Clauses 1 to 11, comprising processing circuitry for performing at least one operation to recover from a stacked SDA state.

[0067] A method comprising sampling a serial data (SDA) line of a wired shared serial data bus to obtain a sample of the voltage level on the SDA line; monitoring the sample; detecting a predetermined number of consecutive samples from the monitored sample that are at a low voltage level with no low-to-high transition in the voltage level; and indicating a stacked SDA state based on the detected predetermined number of consecutive samples from the monitored sample.

[0068] The method according to Clause 13, comprising filtering out noise in the voltage level on the SDA line, wherein the SDA line is sampled from the filtered voltage level.

[0069] The method according to Clause 15. Monitoring a sample includes monitoring adjacent samples among the samples, detecting a high-to-low transition in the voltage level of the monitored adjacent samples among the samples, and setting a flag based on the detected high-to-low transition, wherein a predetermined number of consecutive samples among the monitored samples that are at a low voltage level and have no low-to-high transition in voltage are detected based on the flag.

[0070] Clause 16. The method according to Clause 15, which includes maintaining a set flag for consecutive samples that are at a low voltage level among the monitored samples.

[0071] Clause 17. The method of Clause 15 or Clause 16, wherein monitoring a sample includes detecting a low-to-high transition in the voltage level of an adjacent sample among the samples being monitored, and unflacking based on the detected low-to-high transition.

[0072] Clause 18. The method of Clause 17, which includes keeping a flag unset for consecutive samples among the monitored samples that are at a high voltage level.

[0073] Clause 19. The method according to any one of Clauses 15 to 18, wherein detecting a predetermined number of consecutive samples from monitored samples that are at a low voltage level without a low-to-high transition includes sampling a flag to obtain a sample of the flag, monitoring a sample of the flag, and detecting a threshold number of consecutive samples from monitored samples of the flag that are set, where the threshold number of consecutive samples from monitored samples of the flag corresponds to a predetermined number of consecutive samples from monitored samples of the voltage level on the SDA line.

[0074] The method according to Clause 20.2, wherein a wired shared serial data bus includes a serial clock (SCL) line for a clock signal, and the flag is sampled over each clock period of a reference clock having a frequency greater than or equal to the frequency of the clock signal on the SCL line.

[0075] The method of Clause 21.2, wherein a wired shared serial data bus includes a serial clock (SCL) line for a clock signal, and the flag is sampled over each clock period of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line.

[0076] Clause 22. The method according to any one of Clauses 19 to 21, wherein the flag is sampled over each clock period of a reference clock, and the threshold number of consecutive samples among the monitored samples of the flag is represented by a predetermined number of clock periods set to be equal to a predetermined period.

[0077] Clause 23. The method according to any one of Clauses 13 to 22, wherein indicating a stack SDA state includes generating a stack SDA status or interrupt to indicate a stack SDA state.

[0078] Clause 24. The method of any one of Clauses 13 to 23, which includes performing at least one action to recover from a stacked SDA state.

[0079] Many modifications and other implementations of the Disclosure described herein will be conceived by those skilled in the art who are interested in the teachings presented in the foregoing description and the accompanying figures. Therefore, it should be understood that the Disclosure should not be limited to the specific implementations disclosed, and that modifications and other implementations are intended to be included within the scope of the appended claims. Furthermore, while the foregoing description and the accompanying figures illustrate exemplary implementations in the context of specific exemplary combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative implementations without departing from the scope of the appended claims. In this regard, different combinations of elements and / or functions than those expressly described above are also contemplated, for example, as may be described in part of the appended claims. Specific terms are used herein, but they are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. It is a controller, An SDA line interface for connecting the controller to the serial data (SDA) line of a two-wire shared serial data bus, A processing circuit is provided, and the processing circuit comprises at least, The SDA line is sampled to obtain a sample of the voltage level on the SDA line. The aforementioned sample is monitored, A predetermined number of consecutive samples from the monitored samples are detected that are at a low voltage level without any transition from low to high voltage level. A controller that indicates the stack SDA state based on a predetermined number of consecutive samples detected from the monitored samples.

2. The controller according to claim 1, comprising the processing circuit for filtering out noise at the voltage level on the SDA line, wherein the SDA line is sampled from the filtered voltage level.

3. The processing circuit for monitoring the sample is Monitor adjacent samples among the aforementioned samples, The high-to-low transition in the voltage level of the monitored adjacent sample among the aforementioned samples is detected. The circuit includes a processing circuit for setting a flag based on the detected high-to-low transition, The controller according to claim 1, wherein a predetermined number of consecutive samples from the monitored samples that are at the low voltage level without a transition of the voltage from low to high are detected based on the flag.

4. The controller according to claim 3, wherein the processing circuit holds the flag set for consecutive samples at the low voltage level among the monitored samples.

5. The processing circuit for monitoring the sample is The transition from low to high in the voltage level of the monitored adjacent sample among the aforementioned samples is detected. The controller according to claim 3, further comprising a processing circuit for desetting the flag based on the detected transition from low to high.

6. The controller according to claim 5, wherein the processing circuit holds the flag in an unset state for consecutive samples among the monitored samples that are at the high voltage level.

7. The processing circuit for detecting a predetermined number of consecutive samples from the monitored samples that are at the low voltage level without a transition from low to high is: Sample the aforementioned flag to obtain a sample of the flag, The sample of the aforementioned flag is monitored, The controller according to claim 3, comprising a processing circuit for detecting a threshold number of consecutive samples of the monitored samples of the flag for which the flag is set, wherein the threshold number of consecutive samples of the monitored samples of the flag corresponds to a predetermined number of consecutive samples of the voltage level on the SDA line.

8. The controller according to claim 7, wherein the two-wire shared serial data bus includes a serial clock (SCL) line for a clock signal, and the processing circuit samples the flag over each clock period of a reference clock having a frequency greater than or equal to the frequency of the clock signal on the SCL line.

9. The controller according to claim 7, wherein the two-wire shared serial data bus includes a serial clock (SCL) line for a clock signal, and the processing circuit samples the flag over each clock period of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line.

10. The controller according to claim 7, wherein the processing circuit samples the flag over each clock period of a reference clock, and the threshold number of consecutive samples of the monitored samples of the flag is represented by a predetermined number of clock periods set to be equal to a predetermined period.

11. The controller according to claim 1, wherein the processing circuit indicating the stack SDA state includes the processing circuit for generating a stack SDA status or interrupt indicating the stack SDA state.

12. The controller according to claim 1, further comprising the processing circuit for performing at least one operation to recover from the stacked SDA state.

13. This involves sampling the serial data (SDA) line of a two-wire shared serial data bus to obtain a sample of the voltage level on the SDA line, Monitoring the aforementioned sample, To detect a predetermined number of consecutive samples from the monitored samples that are at a low voltage level without any transition from low to high voltage level, A method comprising indicating a stacked SDA state based on a predetermined number of consecutive samples detected from the monitored samples.

14. The method according to claim 13, comprising filtering out noise at the voltage level on the SDA line, wherein the SDA line is sampled from the filtered voltage level.

15. Monitoring the aforementioned sample means Monitoring adjacent samples among the aforementioned samples, To detect the transition from high to low in the voltage level of the monitored adjacent sample among the aforementioned samples, This includes setting a flag based on the detected high-to-low transition, The method according to claim 13, wherein a predetermined number of consecutive samples of the monitored samples that are at the low voltage level without a transition of the voltage from low to high are detected based on the flag.

16. The method according to claim 15, further comprising maintaining the flag set for consecutive samples at the low voltage level among the monitored samples.

17. Monitoring the aforementioned sample means To detect the transition from low to high in the voltage level of the monitored adjacent sample among the aforementioned samples, The method according to claim 15, comprising desetting the flag based on the detected transition from low to high.

18. The method according to claim 17, comprising keeping the flag in a de-set state for consecutive samples among the monitored samples that are at the high voltage level.

19. Detecting a predetermined number of consecutive samples from the monitored samples that are at the low voltage level without a transition from low to high is: To sample the aforementioned flag and obtain a sample of the aforementioned flag, Monitoring the aforementioned sample of the aforementioned flag, The method according to claim 15, comprising detecting a threshold number of consecutive samples of the monitored samples of the flag for which the flag is set, wherein the threshold number of consecutive samples of the monitored samples of the flag corresponds to a predetermined number of consecutive samples of the voltage level on the SDA line.

20. The method according to claim 19, wherein the two-wire shared serial data bus includes a serial clock (SCL) line for a clock signal, and the flag is sampled over each clock period of a reference clock having a frequency greater than or equal to the frequency of the clock signal on the SCL line.

21. The method according to claim 19, wherein the two-wire shared serial data bus includes a serial clock (SCL) line for a clock signal, and the flag is sampled over each clock period of a reference clock having a frequency lower than the frequency of the clock signal on the SCL line.

22. The method according to claim 19, wherein the flag is sampled over each clock period of a reference clock, and the threshold number of consecutive samples of the monitored samples of the flag is represented by a predetermined number of clock periods set to be equal to a predetermined period.

23. The method according to claim 13, wherein indicating the stack SDA state includes generating a stack SDA status or interrupt to indicate the stack SDA state.

24. The method according to claim 13, comprising performing at least one operation to recover from the stack SDA state.

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