Detection and recovery from error conditions on a serial data bus.

Abstract

A target is provided that includes an SDA line interface for connecting the target to the serial data (SDA) line of a two-wire shared serial data bus. The target includes processing circuitry for transferring output data to the SDA line and monitoring the data on the SDA line. The processing circuitry compares the data on the SDA line with the output data to detect error conditions when the data on the SDA line differs from the output data. The processing circuitry then performs at least one action to recover from the detected error condition, which includes at least one of disabling the output SDA pad buffer of the target that transfers the output data to the SDA line, or asserting a stop condition on the data bus.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority to Indian Patent Application No. 202341041195, filed on June 16, 2024, entitled "Detection and Recovery from a Read - Write Data Conflict on a Serial Data Bus", and U.S. Patent Application No. 18 / 514,759, filed on November 20, 2023, entitled "Detection and Recovery from an Error Condition on a Serial Data Bus", the contents of which are hereby incorporated by reference in their entirety.

[0002] (Field of the Invention) This disclosure generally relates to serial communication, and more particularly to the detection of error conditions on a serial data bus and recovery from error conditions.

Background Art

[0003] Serial communication has played an important role in facilitating communication between chips within an electronic system. This involves transmitting data sequentially bit - by - bit over a communication link between devices. This approach offers advantages such as simplicity, fewer pins, and the ability to transmit data over longer distances compared to parallel communication.

[0004] One common serial communication protocol is Inter-Integrated Circuit (I2C), developed in the early 1980s by Philips Semiconductor (now NXP Semiconductors). I2C is a two-wire bus protocol that enables multiple devices to communicate with each other using shared serial data (SDA) and serial clock (SCL) lines. It supports a controller-target (master-slave) architecture, where a controller device initiates and controls communication, and target devices respond to commands or requests from the controller. I2C is commonly used to connect various devices in embedded systems, consumer electronics, and computer peripherals.

[0005] As technology advances and the need for higher data transfer rates, increased flexibility, and improved power efficiency arises, the MIPI Alliance has developed Improved Inter-Integrated Circuit (I3C). Introduced in 2017, I3C builds on the strengths of I2C while offering enhanced and additional features. I3C is backward compatible with I2C, allowing I2C devices to coexist on the same data bus, resulting in higher data transfer rates, increased flexibility for connecting multiple devices, multi-controller support, hot-join capabilities, dynamic address assignment, in-band interrupts, and other improvements. I3C has gained popularity in applications such as smartphones, tablets, Internet of Things (IoT) devices, and automotive systems.

[0006] Serial communication protocols such as I2C and I3C have become essential for inter-chip communication within electronic systems. They enable devices to exchange data, commands, and control signals efficiently and reliably. These protocols are widely adopted and standardized, enabling interoperability between devices from different manufacturers and simplifying the integration of various components within electronic systems. The continuous evolution and development of serial communication protocols contribute to advancements in inter-chip communication and the seamless operation of modern electronic devices. [Overview of the Initiative]

[0007] In I3C, a controller can request read or write transactions with a target. However, in some cases, an error can occur if the controller attempts to initiate a write transaction but believes the target is responding to a read transaction. When this occurs, data written on the data bus from the controller may collide with data read from the target. In I3C, this is referred to as error type TE6, and the target should stop sending, allowing the controller to terminate the data transfer, and then wait for a stop or restart condition. However, it can take several bytes for the stop / restart condition to appear.

[0008] Therefore, exemplary implementations of this disclosure relate to the detection and recovery from TE6 error conditions, which may be completed earlier than specified in I3C. This disclosure includes, but is not limited to, the following exemplary implementations:

[0009] Some exemplary implementations provide a target comprising an SDA line interface for connecting the target to the serial data (SDA) line of a two-wire shared serial data bus, and a processing circuit, the processing circuit performing at least: transferring output data onto the SDA line; monitoring the data on the SDA line; comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data; and performing at least one action to recover from a detected error condition, which includes the processing circuit disabling the output SDA pad buffer of the target on which the output data is transferred onto the SDA line, or asserting a stop condition on the data bus.

[0010] Some exemplary implementations provide a method that includes transferring output data onto a serial data (SDA) line of a two-wire shared serial data bus; monitoring the data on the SDA line; and performing at least one action to recover from a detected error condition, which includes, when the monitored data on the SDA line differs from the output data, comparing the monitored data on the SDA line with the output data to detect an error condition, and disabling the output SDA pad buffer of the target transferring the output data onto the SDA line, or asserting a stop condition on the data bus.

[0011] These and other features, aspects, and advantages of the Disclosure will become apparent from reading the following detailed description together with the accompanying drawings, which are briefly described below. The Disclosure includes any combination of two, three, four, or more features or elements described herein, whether such features or elements are expressly combined or otherwise enumerated in the specific exemplary implementations described herein. The Disclosure is intended to be read holistically so that any separable feature or element of the Disclosure should be considered combinable in any aspect or exemplary implementation unless the context of the Disclosure expressly indicates otherwise.

[0012] Therefore, it will be understood that this “Summary of the Invention” is provided solely for the purpose of summarizing some exemplary implementations in order to provide a basic understanding of some aspects of the present disclosure. Accordingly, it will be understood that the above-described exemplary implementations are merely examples and should not be interpreted in any way as narrowing the scope or spirit of the present disclosure. Other exemplary implementations, aspects, and advantages will become apparent from understanding the following detailed description in conjunction with the accompanying diagrams illustrating the principles of some of the described exemplary implementations.

[0013] While the exemplary implementations of this disclosure have been described above using general terminology, we now refer to the attached drawings, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0014] [Figure 1] This disclosure shows some exemplary implementations of targets. [Figure 2] The system, including the target shown in Figure 1, is shown in several exemplary implementation configurations. [Figure 3] This document illustrates a system that can correspond to the system shown in Figure 2, including multiple controllers and targets, in several exemplary implementation configurations. [Figure 4A]Figure 2 or Figure 3 shows the timing diagrams of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and restart conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 4B] Figure 2 or Figure 3 shows the timing diagrams of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and restart conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 4C] Figure 2 or Figure 3 shows the timing diagrams of signals on the data bus lines for a transaction on the data bus, including specifying start, stop, and restart conditions (Figure 4A), address headers (Figure 4B), and data words (Figure 4C) in several exemplary implementations. [Figure 5] Figure 1 shows a functional block diagram of the target, with several exemplary implementation configurations. [Figure 6A] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6B] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6C] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6D] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6E] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6F] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6G] This is a flowchart showing the various steps in different exemplary implementations of the method. [Figure 6H]A flowchart showing various steps in a method according to various exemplary implementations. [Figure 6I] A flowchart showing various steps in a method according to various exemplary implementations.

Embodiments for Carrying out the Invention

[0015] Some embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. In fact, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout, like reference numerals refer to like elements.

[0016] Unless otherwise specified or clear from the context, references to first, second, etc. should not be construed as meaning a particular order. Features described as being above another feature (unless otherwise specified or clear from the context) may, instead, be below it, and vice versa. Similarly, features described as being to the left of another feature may, instead, be to the right of it, and vice versa. Also, although this specification may refer to quantitative measures, values, geometric relationships, etc., unless otherwise specified, all or any one or more of these may be approximations to account for possible acceptable variations, such as those resulting from engineering tolerances, etc.

[0017] As used herein, unless otherwise specified or clear from the context, "or" of a set of operands is an "inclusive logical disjunction", whereby it is true only when one or more of the operands are true, in contrast to an "exclusive logical disjunction" which is false when all of the operands are true. Thus, for example, "[A] or [B]" is true when [A] is true, or [B] is true, or both [A] and [B] are true. Further, the articles "a" and "an" mean "one or more" unless otherwise specified or clear from the context that the singular form is intended. Further, it should be understood that unless otherwise specified, the terms "data", "content", "digital content", "information", and similar terms may sometimes be used interchangeably.

[0018] Further, although this specification may refer to terms specific to a particular system or architecture, it should be understood that the exemplary implementations of the present disclosure may be equally applicable to any of several systems and architectures. In this regard, some exemplary implementations may be described in the context of serial communication standards for inter-chip communication such as I3C and its predecessor I2C. However, it should be understood that the exemplary implementations may be equally applicable to other serial communication standards as well.

[0019] Exemplary implementations of the present disclosure generally relate to serial communication, and more particularly, to the detection of read / write data collisions on a serial data bus and recovery therefrom.

[0020] Figure 1 shows a target 100 in several exemplary implementations of the present disclosure. The target may be an electronic device such as an integrated circuit (IC). The target may include, but is not limited to, a processing circuit 102 such as a general-purpose or dedicated processor, microprocessor, controller, or microcontroller. The target may also include one or more interfaces for connecting the target to a data bus 104 from which the target can communicate with other electronic devices. In the context of serial communication standards such as I2C and I3C, the data bus may be a two-wire shared serial data bus 104. In this regard, the data bus may include serial data (SDA) lines 104A used to transmit and receive data between electronic devices connected to the data bus. The target may include an SDA line interface 106 for connecting the target to the SDA lines, and the SDA line interface may include an output SDA pad buffer 108 for driving output data 110 on the SDA lines.

[0021] Figure 2 shows a system 200 including a target 100 in some exemplary implementations of the present disclosure. As shown, the system includes several electronic devices 202, such as ICs, connected to a data bus 104. In addition to the SDA line 104A, the data bus may include an SCL line 204B that provides a clock signal used to synchronize data transfers between the electronic devices 202. In some examples, the target 100 may also include an SCL line interface for connecting the target to the SCL line.

[0022] System 200 can operate according to a controller-target architecture in which an electronic device 202 can function as a controller 206 that initiates and controls communication (timing and data) on the data bus 104, and another electronic device can function as a target 100 that responds to commands or requests from the controller. In some examples, the system can support multiple controllers and targets.

[0023] Figure 3 shows a system 300 that may correspond to system 200 in Figure 2, including multiple controllers and targets in several exemplary implementation forms. As shown, for example, system 300 may include a primary controller 206A and one or more secondary controllers 206B, one of which may be the active controller currently controlling the data bus 104. Primary controller 206A can initialize the data bus 104 and perform configuration of target 100. In its initial state, primary controller 206A acts as the authority for the data bus 104, and once the data bus is configured, it may become the first active controller. Secondary controller 206B may initially function as a target, but secondary controller 206B can accept controllership from the active controller and become the new active controller. In the context of I3C, the system may include an I3C primary controller and one or more I3C secondary controllers.

[0024] System 300 may similarly include one or more targets 100. The system may also include one or more legacy targets 304 from previous communication standards to which System 300 may conform. In this case as well, in the context of I3C, the system may include one or more I3C targets, and the system may include one or more I2C targets.

[0025] Returning to Figure 2, the system 200 may support multiple data transfer modes, allowing electronic devices 202 to communicate at different speeds based on their capabilities. The modes may include single data rate (SDR) mode and several high data rate (HDR) modes, along with increasing data transfer rates and corresponding signal integrity requirements. In particular, SDR mode may be used for several purposes, such as performing private messaging from controller 206 to target 100, and for entering other modes and states (e.g., HDR mode). In the context of I3C, SDR mode may be used to implement built-in I3C features such as common command code (CCC), in-band interrupt (IBI), and hot join. SDR mode may also be used to transition from I2C to I3C through dynamic address assignment, and for executing legacy I2C transactions on data bus 104.

[0026] The electronic device 202 can operate in various output modes to drive signals on the data bus 104. Examples of appropriate modes include open-drain mode and push-pull mode, which define how the electronic device 202 controls the voltage levels on the SDA line 104A and the SCL line 204B. In open-drain mode, the electronic device 202 may be configured as open-drain or open-collector at its output. In open-drain mode, the electronic device 202 can pull a signal line (SDA or SCL) to a low voltage level (logic 0) by actively sinking current, but it does not have an active element to pull the signal line to a high voltage level (logic 1); instead, an externally present pull-up resistor may be used to pull the line to a high voltage level (logic 1). In push-pull mode, the electronic device 202 may be configured as a push-pull driver at its output. In push-pull mode, the electronic device can actively drive both high (logic 1) and low (logic 0) voltage levels on the signal line.

[0027] Figures 4A, 4B, and 4C are timing diagrams of signals on the SDA line 104A and SCL line 204B for read / write transactions on the data bus 104, in several exemplary implementations. As shown in Figure 4A, a read / write transaction on the data bus can start with an initiation state, which can be implemented as a high-to-low transition on the SDA line while asserted by the controller 206 and the SCL line is held constant high by the controller 206. Similarly, a read / write transaction on the data bus can end with a termination condition asserted by the controller 206. The termination condition can be implemented as a low-to-high transition on the SDA line while the SCL line is held constant high by the controller 206. As an alternative to termination conditions, restart conditions may allow multiple messages to be sent within the same frame without the need to send stop and start signals between messages. Restart conditions may look similar to initiation conditions on the data bus.

[0028] Following the start / restart conditions, a read / write transaction on the data bus 104 may include an address header that may contain the destination address, indicate the read or write transaction, and provide an acknowledgment. The address header may be transmitted on the SDA line 104A during the period when the SCL line 204B is transitioning from low to high (rising edge) or high to low (falling edge). Figure 4B shows the timing diagrams of the SDA and SCL lines for the address header (in push-pull mode) in several exemplary implementations. In the context of I2C and I3C, the address header may include seven address bits, one read / write (R / W) bit, and one acknowledgment (ACK) / non-acknowledgment (NACK) bit. In the context of I3C, the R / W bit may be referred to as the R / W bit or RnW bit. In some examples, the controller 206 may transmit the address and the R / W bit. The controller 206 can address the target 100 using the address bit, and the controller can specify write mode (the controller 206 writes data to the target 100) or read mode (the controller 206 reads data from the target 100) using the R / W bit. In this regard, the controller 206 may transmit a low signal (R / W bit = 0) on the SDA line 104A to indicate write mode, or a high signal (R / W bit = 1) on the SDA line to indicate read mode.

[0029] Once controller 206 transmits the address and R / W bits of the address header on data bus 104, the controller can wait for target 100 to acknowledge (or not acknowledge) the request. This can be done through the ACK / NACK bits in the address header. The target may pull SDA line 104A low (ACK / NACK bits = 0) to respond with an acknowledgment (ACK), or release the SDA line high (ACK / NACK bits = 1) to respond with a negation (NACK).

[0030] As shown in Figure 4C, one or more data words may follow the address header. Similar to the address header, data words may be transmitted on the SDA line 104A during the period when the SCL line 204B is transitioning from low to high (rising edge) or high to low (falling edge). In the context of I3C, a data word may be 9 bits wide, containing 8 bits of data and a ninth transition bit (T bit). When the controller 206 is writing data to the target 100, the T bit of each data word may be a parity bit calculated using odd parity, which helps in detecting errors caused by noise on the data bus 104. Conversely, when the controller 206 is reading data returned from the target 100, the T bit of each data word may represent a data end bit. In this regard, the target 100 can use the T bit to control the number of data words the target returns. The T bit can also cause the controller 206 to abort the read prematurely. To terminate a message, the target 100 can return the T bit as "O". To continue the message, the target can monitor the SDA line by returning the T bit as "1". If the SDA line remains high on the next falling SCL edge, the target can continue sending the next data value. If the SDA line is low on the next falling SCL edge (restart), the controller 206 has stopped the data transfer, and the target will not send the next data.

[0031] The electronic device 202 may implement one or more error detection and recovery methods to handle various error conditions during read / write transactions on the data bus 104. In this regard, in the context of I3C, if an error occurs in the R / W bit of the address header, target 100 may believe that target 100 is responding to a read transaction when controller 206 actually attempts to initiate a write transaction. When this occurs, write data on the data bus from the controller may collide with read data from the target. In the MIPI I3C® standard published by the Mobile Industry Processor Interface (MIPI) Alliance, this error condition is referred to as error type TE6. As specified, target 100 should monitor the data that target 100 transmits on the SDA line 104A of data bus 104 for read transactions, thereby enabling target 100 to detect the TE6 error condition when the monitored data differs from the data that the target intended to transmit.

[0032] According to the MIPI I3C® standard, when target 100 detects a TE6 error condition during an attempted private write transaction with controller 206 (i.e., when target 100 is functioning as if responding to a private read transaction while the controller is attempting to execute a private write transaction), target 100 can stop transmitting, allowing controller 206 to terminate the data transfer, and then wait for a stop or resume state. However, several bytes, possibly up to 68 bytes, may be required before the stop / resume condition appears on SDA line 104A. Therefore, exemplary implementations of this disclosure provide an improved error detection and recovery method for TE6 error conditions, which can avoid long-term conflicting data on data bus 104 and reduce power consumption.

[0033] According to some exemplary implementations of this disclosure, target 100 (e.g., processing circuit 102) can operate in a read state and execute a read transaction to transfer output data 110 to data bus 104. While target is in a read state, target can monitor data on SDA line 104A, compare the data on SDA line 104A with output data 110, and detect an error condition if the data on SDA line 104A and output data 110 are different. To recover from the error condition, target can disable the internal output SDA pad buffer 108 that drives output data 110 on the SDA line until a stop / restart state appears on the SDA line indicating that the transfer of data from controller 206 that is competing with and interfering with output data 110 has been completed. Additionally or alternatively, in some examples, target 100 can assert a stop on data bus 104, which controller 206 can detect and terminate the transfer from controller 206 to the SDA line.

[0034] As shown in Figure 1, for example, the processing circuit 102 of target 100 can transfer output data 110 to SDA line 104A and monitor data 112 on the SDA line. In some examples, the processing circuit 102 can filter noise in the data on the SDA line to generate filtered data, and the monitored data may be filtered data. In some examples, the processing circuit 102 can detect an address header in the data on the SDA line (Figure 4B) and monitor one or more data words following the address header in the data on the SDA line (Figure 4C).

[0035] The processing circuit 102 can compare data 112 on SDA line 104A with output data 110 to detect an error condition when the data on the SDA line and the output data 110 are different. In some examples, the processing circuit can perform a bitwise comparison of one or more data words of data 112 on the SDA line with one or more data words of output data 110. When the bitwise comparison indicates that one or more data words of data 112 on the SDA line and one or more data words of output data 110 are different, the processing circuit can set a flag to indicate that a detected error condition has been detected.

[0036] The processing circuit 102 can perform at least one action to recover from a detected error condition, such as when a flag is set. In this regard, the processing circuit can disable the output SDA pad buffer 108 of the target 100 that transfers the output data 110 onto the SDA line 104A. In this regard, in some examples, the output SDA pad buffer 108 is a three-state buffer having an enable / disable input through which the output SDA pad buffer 108 is disabled.

[0037] In addition to, or instead of, disabling the SDA pad buffer 108, in some examples, the processing circuit 102 may assert a stop condition on the data bus 104. In some examples, where data 112 on the SDA line 104A is corrupted by the controller 206 competing with and interfering with output data 110, the processing circuit 102 may assert a stop condition on the data bus 104 to cause the controller 206 to terminate the transfer of data onto the SDA line 104A. In some examples, the processing circuit 102 may count the bit positions of the current data word of output data 110 to identify the transition bit positions of the current data word of output data 102. Then, when the transition bit positions of the current data word of output data 110 have been identified, the processing circuit 102 may assert a stop condition on the data bus. In some examples where the data bus 104 also includes the SCL line 204B, to assert a stop condition, the processing circuit may cause a low-to-high transition in the voltage level on the SDA line 204B while the voltage level on the SCL line 104A remains consistently high.

[0038] To further illustrate some exemplary implementations of the present disclosure, Figure 5 is a functional block diagram of target 100 in some exemplary implementations. In an example where target 100 is an electronic device 202 such as an IC, target 100 may include several blocks that are functional units or modules that perform the respective functions of target 100. As shown, target 100 may include a semiconductor intellectual property core (IP block) 502 to enable the target to support serial communication on data bus 104. The target may include an input SDA pad buffer 504 for receiving input data (SDA_IN) on SDA line 104A. In some examples, the input SDA pad buffer 504 may include a glitch filter (sometimes referred to as a spike filter) for filtering unwanted noise in the input data on SDA line 104A, such as by suppressing extreme changes in voltage levels on SDA line 104A.

[0039] The target 100 may also include an output SDA pad buffer 108 for driving output data (SDA_OUT) on the SDA line 104A. In some examples, the output SDA pad buffer 108 may be a three-state buffer, and the IP block 502 may allow the output SDA pad buffer 108 to drive output data when the target is in a read state.

[0040] As shown in the figure, target 100 also includes a state machine 508 and a detector 510. The state machine 508 can monitor the IP block 502 to determine when target 100 is in a read state. In the read state, the IP block 502 can cause the output SDA pad buffer 108 to drive output data (SDA_OUT) to the SDA line 104A, thereby executing a read transaction. The state machine 508 can detect an address header in the data on the SDA line 104A (SDA_IN). The state machine 508 can then enable the detector 510 to monitor one or more data words following the address header and detect a TE6 state on the SDA line.

[0041] In some examples, the detector 510 includes an XOR (exclusive OR) gate 512, a multiplexer 514, and a D flip-flop 516. The XOR gate 512 compares one or more data words of data (SDA_IN) on the SDA line 104A with one or more output data words of output data (SDA_OUT) bit by bit and can generate a high gate output (logic 1) when one or more input data words and one or more output data words are different. The multiplexer 514 may pass the output of the XOR gate 512 to the D input of the D flip-flop 516 in response to an asserted enable signal (EN) from the state machine 508, the D flip-flop 516 is clocked by a signal which may be the SCL clock, a synchronous SCL clock, or a faster clock signal, and the D flip-flop may then latch the output of the XOR gate 512. Therefore, if one or more input data words differ from one or more output data words, the D flip-flop latches a high output as a TE6_Error signal (sometimes referred to as the TE6 error flag), which can be provided to the state machine 508 to indicate that a TE6 condition has been encountered. Depending on the set TE6 error flag, the state machine 508 may deassert an enable signal to the multiplexer 514, thereby latching the TE6 error flag. In other examples, the multiplexer 514 and the D flip-flop 516 are not required, and the state machine 508 responds to the TE6 error flag without requiring the TE6 error flag to be latched. Similarly, the state machine 508 may clear the D flip-flop when the detector is not in use or when the target exits the read state, thereby clearing the TE6 error flag.

[0042] The state machine 508 may detect that the TE6 error flag is set and implement a recovery method to recover. In some examples, the target 100 includes a 2:1 multiplexer 518 and a pad buffer control block 520. The 2:1 multiplexer 518 may include an output line coupled to the enable pin of the output SDA pad buffer 108 and a first input line coupled to each output of the IP block 502 to allow the IP block 502 to enable the output SDA pad buffer when the target is in a read state.

[0043] The 2:1 multiplexer 518 may also include a second input line connected to ground (logic 0) and a selection line connected to the pad buffer control block 520, allowing the pad buffer control block to select one of the first or second input lines of the 2:1 multiplexer 518. The pad buffer control block 520 may select the first input line to allow the IP block 502 to enable the output SDA pad buffer 108 in read state. However, if the state machine detects the TE6 error flag, the state machine 508 may control the pad buffer control block to select the second input line of the 2:1 multiplexer, thereby connecting the enable pin of the output SDA pad buffer to ground to disable the output SDA pad. Thus, the state machine 508 and detector 510 can detect the TE6 error condition and implement a recovery method outside of the IP block 502 without interrupting the IP block 502.

[0044] In some examples, target 100 may include a counter block 522 coupled to state machine 508. In some of these examples, the state machine can use the counter block to count the bit positions of one or more output data words of output data (SDA OUT). The state machine can identify the current T bit position of one or more output data words when the output SDA pad buffer 108 is disabled. The state machine can cause the target to issue a stop on SDA line 104A and SCL line 204B, and the controller 206 can detect and terminate the transfer of data onto the SDA line where the data was competing with and interfering with output data 110. The state machine 508 then asserts an enable signal to multiplexer 514, clears D flip-flop 516, and signals pad buffer control block 520 to re-select the first input of 2:1 multiplexer 518, allowing IP block 502 to re-enable output SDA pad buffer 108. In an example where controller 206 does not support receiving stop bits generated by target 100, and therefore controller 206 continues to transmit data, state machine 508 and pad buffer control block 520 can keep output SDA pad buffer 108 disabled and wait for stop or restart conditions from controller 206.

[0045] Figures 6A to 6I are flowcharts showing various steps of Method 600 in various exemplary implementations. The Method includes transferring output data to a serial data (SDA) line of a two-wire shared serial data bus, as shown in block 602 of Figure 6A. The Method includes monitoring data on the SDA line, as shown in block 604. The Method includes comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line differs from the output data, as shown in block 606. The Method then includes performing at least one action to recover from the detected error condition, which includes at least one of disabling the target output SDA pad buffer that transfers output data onto the SDA line, or asserting a stop condition on the data bus, as shown in block 608.

[0046] In some examples, method 600 includes filtering and removing noise in the data on the SDA line to generate filtered data, as shown in block 610 of Figure 6B. In some of these examples, the monitored data is the filtered data.

[0047] In some examples, monitoring data on the SDA line in block 604 involves detecting the address header in the data on the SDA line, as shown in block 612 of Figure 6C. In some of these examples, monitoring the data also involves monitoring one or more data words following an address header in the data on the SDA line, as shown in block 614.

[0048] In some examples, comparing the monitored data on the SDA line with the output data in block 606 involves performing a bitwise comparison of one or more data words of the monitored data on the SDA line with one or more data words of the output data, as shown in block 616 of Figure 6D. In some of these examples, method 600 includes setting a flag to indicate that an error condition has been detected when the bitwise comparison shows that one or more data words of the monitored data on the SDA line are different from one or more data words of the output data, as shown in block 618. Then, in block 608, when the flag is set, at least one action is performed to recover from the detected error condition.

[0049] In some examples, performing at least one operation in block 608 includes disabling the target output SDA pad buffer that transfers output data onto the SDA line, as shown in block 620 in Figure 6E.

[0050] In some examples, the output SDA pad buffer is a three-state buffer with an enable / disable input through which the output SDA pad buffer is disabled in block 620.

[0051] In some cases, monitored data on the SDA line conflicts with transferred output data and is corrupted by the interfering controller. In some of these cases, performing at least one action in block 608 includes disabling the target output SDA pad buffer and asserting a stop condition on the data bus to cause the controller to terminate the transfer of data onto the SDA line, as shown in blocks 622 and 624 of Figure 6F.

[0052] In some cases where data on the SDA line conflicts with transferred output data and is corrupted by an interfering controller, performing at least one action in block 608 includes asserting a stop condition on the data bus to cause the controller to terminate the transfer of data onto the SDA line, as shown in block 626 of Figure 6G.

[0053] In some examples, asserting the stop condition in block 626 involves counting the bit position of the current data word of the output data and identifying the current data word of the output data, as shown in block 628 of Figure 6H. The method then involves asserting the stop condition on the data bus when the transition bit position of the current data word of the output data is identified, as shown in block 630.

[0054] In some examples, the data bus includes an SDA line and a serial clock (SCL) line. In some of these examples, asserting a stop condition on the data bus in block 626 involves causing a low-to-high transition in the voltage level on the SDA line while the voltage level on the SCL line remains constant high, as shown in block 632 of Figure 6I.

[0055] As described above and repeated below, this disclosure includes, without limitation, the following exemplary implementations.

[0056] Clause 1. A target comprising an SDA line interface for connecting the target to a serial data (SDA) line of a two-wire shared serial data bus, and a processing circuit, wherein the processing circuit performs at least: transferring output data onto the SDA line; monitoring the data on the SDA line; comparing the monitored data on the SDA line with the output data to detect an error condition when the monitored data on the SDA line is different from the output data; and performing at least one action to recover from a detected error condition, which includes the processing circuit disabling the output SDA pad buffer of the target on which the output data is transferred onto the SDA line, or asserting a stop condition on the data bus.

[0057] Clause 2. The target described in Clause 1, comprising a processing circuit for filtering noise in the data on the SDA line in order to generate filtered data, wherein the monitored data is filtered data.

[0058] Clause 3. A target according to Clause 1 or Clause 2, comprising a processing circuit for monitoring data on an SDA line, which includes a processing circuit that detects an address header in the data on an SDA line and monitors one or more data words following the address header in the data on an SDA line.

[0059] Clause 4. A processing circuit for comparing monitored data on an SDA line with output data comprises: performing a bitwise comparison of one or more data words of the monitored data on an SDA line with one or more data words of the output data; and setting a flag to indicate that a detected error condition has been detected when the bitwise comparison indicates that one or more data words of the monitored data on an SDA line and one or more data words of the output data are different, wherein at least one operation is performed to recover from a detected error condition when the flag is set, as described in any one of Clauses 1 to 3.

[0060] Clause 5. A target as described in any one of Clauses 1 to 4, comprising a processing circuit for performing at least one operation, the processing circuit for disabling the target's output SDA pad buffer for transferring output data onto the SDA line.

[0061] Clause 6. The output SDA pad buffer is a three-state buffer having an enable / disable input through which the output SDA pad buffer is disabled, as described in Clause 5.

[0062] Clause 7. The target as described in Clause 5 or 6, wherein monitored data on the SDA line is corrupted by a controller that conflicts with and interferes with transferred output data, and the processing circuitry for performing at least one action includes disabling the target's output SDA pad buffer and asserting a stop condition on the data bus to cause the controller to terminate the transfer of data onto the SDA line.

[0063] Clause 8. The target described in any one of Clauses 1 to 7, wherein the monitored data on the SDA line is corrupted by a controller that is in conflict with and interfering with the transferred output data, and the processing circuit for performing at least one action includes a processing circuit for asserting a stop condition on the data bus to cause the controller to terminate the transfer of data to the SDA line.

[0064] The target described in Clause 9, comprising a processing circuit for asserting a stop condition, which includes a processing circuit that counts the bit position of the current data word of the output data to identify the current data word of the output data, and when the transition bit position of the current data word of the output data is identified, asserts a stop condition on the data bus.

[0065] Clause 10. The target as described in Clause 8 or Clause 9, wherein the data bus includes an SDA line and a serial clock (SCL) line, and the processing circuit for asserting a stop condition on the data bus includes a processing circuit for causing a low-to-high transition of the voltage level on the SDA line while the voltage level on the SCL line is constant high.

[0066] Clause 11. A method comprising: transferring output data onto a serial data (SDA) line of a two-wire shared serial data bus; monitoring data on the SDA line; and performing at least one action to recover from a detected error condition, which includes, when the monitored data on the SDA line differs from the output data, comparing the monitored data on the SDA line with the output data to detect an error condition; disabling the output SDA pad buffer of a target that transfers output data onto the SDA line; or asserting a stop condition on the data bus.

[0067] Clause 12. The method according to Clause 11, which includes filtering out noise in the data on the SDA line in order to generate filtered data, wherein the monitored data is filtered data.

[0068] Clause 13. Monitoring data on an SDA line is the method of Clause 11 or Clause 12, which includes detecting an address header in the data on an SDA line and monitoring one or more data words following the address header in the data on an SDA line.

[0069] Clause 14. The method according to any one of Clauses 11 to 13, wherein comparing monitored data on an SDA line with output data includes performing a bitwise comparison of one or more data words of monitored data on an SDA line with one or more data words of output data, and setting a flag to indicate that a detected error condition has been detected when the bitwise comparison indicates that one or more data words of monitored data on an SDA line and one or more data words of output data are different, and at least one action is performed to recover from the detected error condition when the flag is set.

[0070] Clause 15. The method described in any one of Clauses 11-14, wherein performing at least one action includes disabling the target output SDA pad buffer that transfers output data onto the SDA line.

[0071] Clause 16. The method according to Clause 15, wherein the output SDA pad buffer is a three-state buffer having an enable / disable input through which the output SDA pad buffer is disabled.

[0072] Clause 17. The method of Clause 15 or Clause 16, wherein monitored data on an SDA line is corrupted by a controller that conflicts with and interferes with transferred output data, and the method of performing at least one action includes disabling the target output SDA pad buffer and asserting a stop condition on the data bus to cause the controller to terminate the transfer of data onto the SDA line.

[0073] Clause 18. The method described in any one of Clauses 11 to 17, wherein monitored data on the SDA line is corrupted by a controller that is in conflict with and interfering with transferred output data, and the controller performs at least one action, which includes asserting a stop condition on the data bus to cause the controller to terminate the transfer of data to the SDA line.

[0074] The method of Clause 18, wherein asserting a stop condition includes counting the bit position of the current data word of the output data to identify the current data word of the output data, and asserting a stop condition on the data bus when the transition bit position of the current data word of the output data has been identified.

[0075] Clause 20. The method of Clause 18 or Clause 19, wherein the data bus includes an SDA line and a serial clock (SCL) line, and asserting a stop condition on the data bus causes a transition from low to high voltage level on the SDA line while the voltage level on the SCL line is constant high.

[0076] Many modifications and other implementations of the Disclosure described herein will be recalled by those skilled in the art to whom the Disclosure relates, who are of interest in the teachings presented in the above description and associated figures. Therefore, it should be understood that the Disclosure should not be limited to the specific implementations disclosed, and that modifications and other implementations are intended to be included within the scope of the appended claims. Furthermore, while the above description and associated figures illustrate exemplary implementations in the context of specific exemplary combinations of elements and / or functions, it should be understood that different combinations of elements and / or functions may be provided by alternative implementations without departing from the scope of the appended claims. In this regard, different combinations of elements and / or functions than those explicitly described above are also contemplated, for example, as may be described in part of the appended claims. Specific terms are used herein, but they are used in a general and descriptive sense only and are not intended to be limiting.

Claims

1. The target, An SDA line interface for connecting the target to the serial data (SDA) line of a two-wire shared serial data bus, A processing circuit is provided, and the processing circuit comprises at least, Transferring output data onto the SDA line, Monitoring the data on the aforementioned SDA line, When the monitored data on the SDA line and the output data are different, in order to detect an error condition, the monitored data on the SDA line and the output data are compared, A target that performs at least one operation to recover from the detected error condition, which includes the processing circuit performing at least one of the following: disabling the output SDA pad buffer of the target that transfers the output data onto the SDA line, or asserting a stop condition on the data bus.

2. The target according to claim 1, comprising the processing circuit for filtering noise in the data on the SDA line in order to generate filtered data, wherein the monitored data is the filtered data.

3. The processing circuit for monitoring the data on the SDA line is: To detect the address header in the data on the SDA line, The target according to claim 1, further comprising the processing circuit that monitors one or more data words following the address header in the data on the SDA line.

4. The processing circuit for comparing the monitored data on the SDA line with the output data is: Perform a bitwise comparison between one or more data words of the monitored data on the SDA line and one or more data words of the output data. The processing circuit includes, when the bitwise comparison indicates that one or more data words of the monitored data on the SDA line are different from one or more data words of the output data, setting a flag to indicate that the detected error condition has been detected. The target according to claim 1, wherein the at least one operation is performed to recover from the detected error condition when the flag is set.

5. The target according to claim 1, wherein the processing circuit for performing the at least one operation comprises the processing circuit for disabling the output SDA pad buffer of the target that transfers the output data onto the SDA line.

6. The target according to claim 5, wherein the output SDA pad buffer is a three-state buffer having an enable / disable input through which the output SDA pad buffer is disabled.

7. The target according to claim 5, wherein the monitored data on the SDA line is corrupted by a controller that conflicts with and interferes with the transferred output data, and the processing circuit for performing the at least one operation comprises the processing circuit for disabling the output SDA pad buffer of the target and asserting the stop condition on the data bus to cause the controller to terminate the transfer of the data onto the SDA line.

8. The target according to claim 1, wherein the monitored data on the SDA line is corrupted by a controller that conflicts with and interferes with the transferred output data, and the processing circuit for performing the at least one operation comprises the processing circuit for asserting the stop condition on the data bus to cause the controller to terminate the transfer of the data onto the SDA line.

9. The processing circuit for asserting the aforementioned stop condition is: The bit position of the current data word in the output data is counted to identify the transition bit position of the current data word in the output data, The target according to claim 8, further comprising a processing circuit that, when the transition bit position of the current data word of the output data is identified, asserts the stop condition on the data bus.

10. The data bus includes the SDA line and the serial clock (SCL) line, The target according to claim 8, wherein the processing circuit for asserting the stop condition on the data bus comprises the processing circuit for causing a transition from low to high voltage level on the SDA line while the voltage level on the SCL line is at a constant high.

11. It is a method, The steps include transferring output data onto the serial data (SDA) line of a two-wire shared serial data bus, The steps include monitoring the data on the aforementioned SDA line, A method comprising: comparing the monitored data on the SDA line with the output data in order to detect an error condition when the monitored data on the SDA line is different from the output data; and performing at least one action to recover from the detected error condition, which includes at least one of the following steps: disabling the target output SDA pad buffer that transfers the output data onto the SDA line; or asserting a stop condition on the data bus.

12. The method according to claim 11, comprising the step of filtering noise in the data on the SDA line in order to generate filtered data, wherein the monitored data is the filtered data.

13. The step of monitoring the data on the SDA line is: The steps include detecting the address header in the data on the SDA line, The method according to claim 11, comprising the step of monitoring one or more data words following the address header in the data on the SDA line.

14. The step of comparing the monitored data on the SDA line with the output data is: The steps include performing a bitwise comparison between one or more data words of the monitored data on the SDA line and one or more data words of the output data, The step of setting a flag to indicate that the detected error condition has been detected when the bitwise comparison indicates that one or more data words of the monitored data on the SDA line are different from one or more data words of the output data, The method according to claim 11, wherein the at least one operation is performed to recover from the detected error condition when the flag is set.

15. The method according to claim 11, wherein the step of performing at least one of the operations includes disabling the output SDA pad buffer of the target that transfers the output data onto the SDA line.

16. The method according to claim 15, wherein the output SDA pad buffer is a three-state buffer having an enable / disable input through which the output SDA pad buffer is disabled.

17. The method according to claim 15, wherein the monitored data on the SDA line is corrupted by a controller that conflicts with and interferes with the transferred output data, and the step of performing at least one action includes disabling the output SDA pad buffer of the target and asserting the stop condition on the data bus to cause the controller to terminate the transfer of the data onto the SDA line.

18. The method according to claim 11, wherein the monitored data on the SDA line is corrupted by a controller that conflicts with and interferes with the transferred output data, and the step of performing the at least one action includes asserting the stop condition on the data bus to cause the controller to terminate the transfer of the data onto the SDA line.

19. The step of asserting the aforementioned stop condition is: The steps include counting the bit position of the current data word in the output data and identifying the transition bit position of the current data word in the output data, The method according to claim 18, comprising the step of asserting the stop condition on the data bus when the transition bit position of the current data word of the output data is identified.

20. The data bus includes the SDA line and the serial clock (SCL) line, The method according to claim 18, wherein the step of asserting the stop condition on the data bus includes causing a transition from low to high voltage level on the SDA line while the voltage level on the SCL line is constant high.

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