Method and apparatus for detection of shared events across streams - Patents.com

Abstract

This study identifies shared events across spiking neural network data streams with significant stochastic content. The data streams are first subjected to cross-correlation. If two data streams are perfectly uncorrelated, the occurrence rate of inter-stream spike pairs will be approximately uniform, r_ind, across all inter-event times. Any shared events generate a gradient, and for any TBE, identification time, r_ind increases up to a rate, r_shr. Searching for the actual TOD can be accomplished using the estimated TOD. TOD_c is tested against an exponential decay with the rate set to the estimated r_ind. If r_ind_c = actual r_ind, equal ranges of exponential decay values ​​represent equal probabilities. Values ​​for TOD_c and r_ind are generated until a combination is found where probabilistically equal regions receive a statistically equal number of inter-stream events. This is then known as TOD_a and TOD_c.

Description

[Technical field]

[0001] This patent claims the benefit of the filing date of the following U.S. patent applications, which are incorporated herein by reference in their entireties: U.S. patent application Ser. No. 62 / 856,142, filed June 2, 2019, entitled “Method and Apparatus for Shared Cross-Stream Event Detection,” inventor David Carl Barton.

[0002] This patent incorporates by reference in its entirety: U.S. patent application Ser. No. 62 / 819,590, entitled “Method and Apparatus for Cross Correlation,” filed March 17, 2019, inventor David Carl Barton; and PCT International Patent Application No. PCT / US2020 / 022869, entitled “Method and Apparatus for Cross Correlation,” filed March 15, 2020, with the inventor being David Carl Barton.

[0003] Technical Field The present invention relates generally to detection of shared events occurring across multiple data streams, and more particularly to shared event detection across data streams having significant probabilistic content. [Background technology]

[0004] Background technology The importance of achieving synchronization (or cross-correlation) between signal (or data) streams is well understood in many technical domains, including but not limited to signal processing and computer networking. For example, in signal processing, cross-correlation is often used to find the relative delay between signal streams in various applications. After two signal streams have been subjected to cross-correlation, it can be useful to have an indication of their degree of synchronization.

[0005] Therefore, a better measure of the correlation between signal streams is needed.

[0006] BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention. [Brief description of the drawings]

[0007] [Figure 1] 1 illustrates an exemplary application scenario of a multi-stream cross-correlator in the domain of spiking neural networks. [Diagram 2] FIG. 2 is a functional block diagram of an example internal structure for each CCU in FIG. 1. [Diagram 3] We present a functional implementation of the Learn Delay using each pair of spikes present at the FORd input as a frame of reference for analyzing spikes occurring at the Other input of the Learn Delay. [Figure 4] 1 illustrates an example pseudo-code implementation of a lazy learner based on the Python programming language. [Diagram 5] 1 illustrates an exemplary electrical implementation of a delay learner. [Figure 6] 1 illustrates an exemplary electrical implementation of a delay learner. [Figure 7] 1 illustrates an exemplary electrical implementation of a delay learner. [Figure 8]This is a functional block diagram of the CCU in FIG. 2, but differs in that a Resolve Conflicts block has been added to the memoryless version of the Produce Delay. [Figure 9] 1 shows an example of an implementation of a delay generator by combining an exponential decay curve with threshold detection. [Figure 10] Regarding the functional block 0220, a circuit for implementing the function of the delay generator described in relation to FIG. 8 is presented. [Figure 11] It shows the same CCU as shown in FIG. 8, except for the addition of a "Rate All Learner" (or LRA) functional block 0223. [Figure 12] 13 shows an exemplary distribution of spikes when the actual MEAALL is known. [Figure 13] An exemplary distribution of spikes is shown when the guess for the value of MEAALL (called MEAguess) is too high. [Figure 14] An exemplary distribution of spikes is shown when the guess for the value of MEAALL (called MEAguess) is too low. [Figure 15] Rather than solving for the point where Equation 1 yields half of its full range (e.g., P=0.5), we present an equality testing scheme for finding the MEA. [Figure 16] We present a circuit implementation of the Rate All learning part based on the equality testing method. [Figure 17] We present the same circuit implementation of the delay learning part shown in Fig. 6, except that hardware for the rALL input has been added. [Figure 18] We present the same circuit implementation of the delay learning part shown in Fig. 7, except that hardware for the rALL input has been added. [Figure 19] We present the same circuit implementation of the delay generator shown in Fig. 10, except that hardware for the rALL input has been added. [Figure 20]1 shows a block diagram for using a Learn TOD Unit using the output of the Cross-Correlation Unit (or CCU). [Figure 21] Shown are snippets of two spike streams that may appear after correlation has been performed. [Figure 22] The same spike stream as in Figure 21, except that an example of two types of random interspike delays is highlighted. [Figure 23] Only two CSSP TBEs are shown in order to highlight the central problem of the present invention, namely, determining the "Time Of Discernment" or TOD. [Figure 24] A simulation is presented showing how two instances of the TOD learning unit implementation of FIG. 26, when incorporated into the design of FIG. 20, might perform on a spike stream. [Figure 25A] FIG. 1 is intended to illustrate the behavior of a CS spike-pair stream with only stochastic content. [Figure 25B] This is intended to show the additional rate at which shared spikes (if any) are added to r_ind for time separations less than or equal to TOD. [Figure 26] 21 illustrates an exemplary division of implementations of each of the TOD learning units of FIG. 20 that is particularly suited to hardware. [Figure 27A] A functional diagram of an implementation using TOD_c and r_ind_c is shown. [Figure 27B] A functional diagram of an implementation using TOD_c and r_ind_c is shown. [Figure 28A] We provide example pseudocode implementations of each of the TOD learning units in Figure 20. [Figure 28B] We provide example pseudocode implementations of each of the TOD learning units in Figure 20. [Figure 29] An example of implementation at the electrical circuit level according to the hardware division in FIG. 26 is shown below. [Figure 30A]Corresponding to FIG. 27A, but different, is that FIG. 30A shows an example of dividing the time range after TOD_c into quarters as well as halves. [Figure 30B] Corresponding to FIG. 27B, but different, is that FIG. 30B shows an example of dividing the time range after TOD_c into quarters as well as halves. [Diagram 31] An example of an electrical circuit level implementation of the multi-scale (quarter and half) and multi-sample (Q4 / Q3 and Q2 / Q1) schemes of FIGS. 30A-B is shown. [Figure 32A] Figure 20 shows an example of a multi-scale, multi-sample pseudocode implementation of each of the TOD learning units in Figure 20. [Figure 32B] Figure 20 shows an example of a multi-scale, multi-sample pseudocode implementation of each of the TOD learning units in Figure 20. [Figure 32C] Figure 20 shows an example of a multi-scale, multi-sample pseudocode implementation of each of the TOD learning units in Figure 20. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Modes for carrying out the invention Reference will now be made in detail to various embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

[0009] Please see Chapter 7 (Glossary of Selected Terms) for definitions of selected terms used below.

[0010] Table of contents for detailed description 1. Overview 2. Exemplary Embodiments 3. Split embodiment 3.1 Overview 3.2 Generalization 3.3 Electrical Circuit Implementation 4. Pseudocode Implementation 5 Multi-scale, multi-sample 5.1 Overview 5.2 Illustrative Embodiments 5.3 Electrical implementation example 5.4 Pseudocode Implementation 6 Further variations 7 Glossary of selected terms 8 Computing equipment 9. Appendix

[0011] 1. Overview This patent is based directly on the following U.S. provisional patent applications: U.S. Provisional Patent Application No. 62 / 856,142, filed June 2, 2019, entitled “Method and Apparatus for Shared Cross-Stream Event Detection,” inventor David Carl Barton (hereinafter referred to as the ‘142 application).

[0012] The '142 application is itself based on the following U.S. provisional patent applications: U.S. Provisional Patent Application No. 62 / 819,590, entitled “Method and Apparatus for Cross Correlation,” filed March 17, 2019, inventor David Carl Barton (hereinafter referred to as the ‘590 application).

[0013] The '590 application is incorporated in its entirety as an appendix to the '142 application. Essentially, the '590 application is incorporated herein in its entirety as an appendix. As noted above, the '590 application is incorporated herein by reference in its entirety.

[0014] The '590 application presents a method and apparatus for cross-correlation between data streams that have significant stochastic content (such as may occur in spiking neural networks).

[0015] Because the '590 application contains figures numbered 1 through 19, Figures 1 through 19 of this patent are addressed in an appendix (i.e., Chapter 9) incorporated herein.

[0016] The figure numbering of the '142 application, and the discussion of detection of shared events across streams in this patent, begins with FIG.

[0017] The description presented herein focuses on the application of the present invention to spiking neural networks. However, as explained in the glossary below, the term "spike" as used herein can refer to a much broader range of signal discontinuities. To emphasize the broadness of the term "spike," at various points in this specification, this term may be replaced with the terms "event" or "occurrence."

[0018] Figure 21 shows snippets of two spike streams 2001 and 2002 as they might appear after being correlated using the invention of the '590 application. Thus, the spikes in streams 2001 and 2002 can be expected to be randomly distributed (or said to have roughly random content), with the exception of certain spike pairs that are determined to be correlated across the two streams. Randomness arises both when considering each spike stream by itself individually, and when examining spikes across two or more streams.

[0019] As can be seen, for purposes of discussion, each spike in stream 2001 is assigned a label from a1 through j1, and each spike in stream 2002 is assigned a label from a2 through f2.

[0020] Figure 22 shows the same spike stream as Figure 21, except that an example of two types of random inter-spike delays is highlighted.

[0021] Figure 22 highlights two Intra-Stream (IS) spike pairs in stream 2001: ● An IS spike pair consisting of spikes a1 and b1, and • IS spike pair consisting of spikes b1 and c1.

[0022] Figure 22 also highlights two Cross-Stream (CS) spike pairs for streams 2001 and 2002: ● A CS spike pair consisting of spikes a2 and b1, and ●CS spike pair of spikes b2 and d1.

[0023] The time interval between two consecutive spikes (where the spikes occur in the same stream or in separate streams) is sometimes referred to as the Time Between the Events (TBE) of a spike pair. (In the '590 application, the TBE of an IS spike pair is called the Inter-Spike Gap or ISG.) In this patent, we primarily consider the TBE of CS spike pairs. CS spike pairs are sometimes referred to herein as CSSPs, and IS spike pairs are sometimes referred to herein as ISSPs. Consecutive CSSPs, such as those resulting from the selection of two spike streams, are sometimes referred to as a CS spike pair stream (or CSSP stream).

[0024] Figure 22 highlights the following two TBEs of the IS spike pair: ● TBE2210 with spikes a1 and b1, and ●TBE2211 for spikes b1 and c1.

[0025] Figure 22 also highlights two TBEs from the CSSP: ● TBE2220 between spikes a2 and b1, and ●TBE2221 between spikes b2 and d1.

[0026] Unless otherwise constrained, the time range of the TBE can be virtually any value, from an arbitrarily close to 0 to an arbitrarily close to infinity.

[0027] As mentioned above, within each ISSP or CSSP stream, the time intervals are expected to be random, with the exception of CS spike pairs where correlations are found. The random distribution of ISSP or CSSP streams is likely to be Poisson distributed. Although random, each ISSP or CSSP stream may be expected to have a relatively constant average time interval. This average time interval may be expressed as the average rate of spike pair occurrence, or r_avg.

[0028] As mentioned above, in addition to stochastic content, a stream of CSSPs may have non-random content, and the present invention is directed to detecting non-random CSSPs. When non-random CSSPs occur, the spikes that make up the CSSPs may be expected to have a fixed temporal relationship (subject to constraints present in any realistic signal system, such as jitter).

[0029] While having a fixed temporal relationship, such spikes (due to reasons other than jitter and inherent to the operation of systems such as spiking neural networks) may generally be expected to occur at different times. Furthermore, cases may arise where one or both spikes that are part of a non-random CSSP do not reliably appear in their respective spike streams (although such spikes are expected to have a fixed temporal relationship with respect to each other when they occur). A non-random CS spike pair is sometimes referred to as a "shared" CS spike pair, since it represents multiple spikes that share an indication of some underlying event. The occurring spike of a shared CS spike pair is sometimes referred to as a "shared" CS spike (or simply a shared spike).

[0030] In contrast to shared CS spike pairs, random CS spike pairs represent spike pairs in which the occurrence of one spike is independent of the occurrence of the other. Thus, spikes in random CS spike pairs are sometimes called "independent" CS spikes (or simply independent spikes). The average occurrence rate of these independent spikes is sometimes denoted as r_ind (rather than r_avg).

[0031] After applying the correlation invention of the '590 application, shared CS spike pairs can be expected to have a time separation (i.e., TBE) close to zero. The present invention seeks to determine a maximum time distance, referred to herein as the "Time Of Discernment" (i.e., TOD). CS spike pairs with a TBE less than or equal to the TOD are classified as consisting of a shared spike, while CS spike pairs with a TBE greater than the TOD are considered independent.

[0032] The determination of TOD is based on an understanding of how independent and shared spikes interact once correlations are found. This is illustrated with the help of Figures 25A-B, each of which shows a type of graph showing the relationship between rate (vertical axis) and time separation (horizontal axis, labeled "TBE") for a particular CS spike pair stream. The particular values ​​on the TBE axis are for illustrative purposes only.

[0033] Figure 25A is intended to illustrate the behavior of a CS spike-pair stream with only stochastic content: the figure shows that across all time separations, CSSPs are expected to exhibit a roughly uniform average occurrence rate, i.e., r_ind (as discussed above).

[0034] In contrast, however, Figure 25B is intended to show the additional rate of shared spikes (if any) that are added to r_ind for time separations less than or equal to TOD 2510. This combined rate, labeled 2530 in Figure 25b, shall be referred to as the shared rate, or r_shr. Thus, a TOD such as 2510 can be determined by finding a time separation that has the following characteristics: For every larger TBE, the rate of CSSP becomes smaller (e.g., in FIG. 25B, it drops to r_ind2521), and ●For anything less than the time separation (relative to TOD), the rate of TBE will be higher (e.g., increased to r_shr2530).

[0035] Figure 25B also shows that even within a range of time separations that are equal to or less than the TOD, there is still a background random CSSP occurrence rate (shown as 2520 in Figure 25B). This background rate is added to the rate of shared CSSPs, resulting in a combined level of r_shr. The background rate of r_ind indicates that a certain number of false positives can be expected.

[0036] 23 shows only two CSSP TBEs in order to highlight the central problem of the present invention, namely, determining the "Time Of Discernment" or TOD. For illustrative purposes, TBE2221 will be considered to be larger than TOD and therefore spikes b2 and d1 will be considered to be unshared. TBE2222 will be considered to be small enough so that c2 and e1 are considered to be shared spikes.

[0037] 2. Exemplary Embodiments In order to present the exemplary embodiments, it may be useful to introduce additional terminology. In particular, it is useful to distinguish between two types of TOD: ● TOD_a: The actual TBE time separation, after which the CSSP rate drops from r_shr to r_ind. ● TOD_c: For embodiments seeking to determine TOD_a, TOD_c represents the current estimated value.

[0038] Although embodiments of the present invention cannot directly detect TOD_a, they can detect the gradient that separates TOD_c from TOD_a, thereby searching for a progressively more accurate estimate of TOD_a.

[0039] Similarly, it is useful to distinguish between two kinds of r_ind: ● r_ind_a: The actual rate of the CSSP for time intervals greater than TOD_a. r_ind_c: For embodiments seeking to determine r_ind_a, r_ind_c represents the current estimated value based on CSSP>TOD_c.

[0040] Again, embodiments of the present invention cannot directly find r_ind_a, but can find the gradient that separates r_ind_c from r_ind_a, and thereby search for a value of r_ind_c that represents a more accurate estimate.

[0041] 27A-B show a functional diagram of an implementation using TOD_c and r_ind_c. In particular, each of FIGs. 27A-B shows one of two main modes of operation: ● Figure 27A: Shows the situation where TOD_a≦TOD_c, which will be called "first mode" or "mode 1." In the illustrated example, TOD_a is shown to be 0.05s, and TOD_c is 0.10s. ● Figure 27B: shows a situation where TOD_a>TOD_c, which shall be called the "second mode" or "mode 2." In the illustrated example, TOD_a is shown to be 0.51 s and TOD_c is 0.10 s.

[0042] As can be seen, Figure 27A is composed of two main subparts: ●Graph 2700:e -rt 27 shows an exponential decay curve 2710 of the form: ##EQU00001## The horizontal axis represents the time distance between the first and second spikes of the CSSP (i.e., TBE). We assume that the exponential decay rate ("r") is equal to the actual average rate (r_ind_a) of the independent (or randomly spaced) CSSPs. Each value along the vertical TBE_P axis then represents the probability that: 1. If the first spike of an independent CSSP has just occurred, then for each time along the horizontal TBE axis, the value of TBE_P represents the probability that a second spike will occur at time TBE or later. Thus, for example, for a first spike at TBE time 0s, the probability that a second spike will occur at 0s or any time later is 1 or 100% (according to the TBE_P axis). Graph 2701: Shows essentially the same type of graph as previously discussed with respect to FIG. 25B, except that TOD_a in FIG. 27A is shown to be at 0.05s.

[0043] Graph 2700 is also based on the use of two threshold detectors: ● A first threshold detector is set to a threshold th_c, where th_c, when projected onto the time axis (i.e., projected onto the TBE axis) by the exponential decay 2710, identifies TOD_c. This threshold detector therefore identifies a time range from TOD_c to infinity. In Fig. 27A, an exemplary value is th_c=0.74, with a corresponding TOD_c=0.10s. ● The second threshold detector is set to th_c / 2. In FIG. 27A, for example purposes, th_c / 2=0.37. When projected onto the time axis, the second threshold detector determines the Median Estimated Time of Arrival (MEA) time for the time range from TOD_c to infinity. In the example of FIG. 27A, the MEA time is 0.33s. Therefore, th_c / 2 can be used to divide the time range from TOD_c to infinity in half, as follows: ○ The first half, called H2, where: TOD_c < H2 ≤ MEA. In the case of Figure 27A, the exemplary range is: 0.10s < H2 ≤ 0.33s. ○ The second half, called H1, where: MEA < H1 ≤ ∞. In the case of Figure 27A, the exemplary range is: 0.33s < H2 ≤ ∞s.

[0044] Although an example of dividing into halves is used, other unit divisions (such as dividing the range into quarters) can be used to initially introduce the division of the time range from TOD_c to infinity. Therefore, each unit of division may also be referred to as a "Region". Figure 27A shows the use of two regions, each region being half of the time range.

[0045] Using the division into halves, r_ind_c can be converged to r_ind_a as follows: ● For each independent CS spike pair, the second spike (referred to as spike_2) is regarded as the negative proxy of r_ind_a. ● Regardless of which half side spike_2 is included in, adjust r_ind_c so that the possibility of a spike occurring within the opposite half in the future increases. For example, Figure 27A shows an exemplary spike_2 at 0.51s within H1. Therefore, decreasing r_ind_c by a certain amount of change (according to the desired learning rate) is also because this tends to shift the spike towards H2 in the future. Generally, the adjustment rule of r_ind_c is as follows: ○ When the second spike of the CS spike pair occurs within H1: Decrease r_ind_c by a certain amount of change so that the subsequent spike is more likely to occur within H2. ○ When the second spike of the CS spike pair occurs within H2: Increase r_ind_c by a certain amount of change so that the subsequent spike is more likely to occur within H1. ●For now, ignoring the influence of TOD_a (i.e., assuming that the time range in which r_ind_a is searched has exactly a uniform rate r_ind_a), we can understand how this method statistically converges r_ind_c towards r_ind_a. ○As time passes, if H1 receives more second spikes of the CS spike pair than H2, it can be seen that r_ind_c is too high by some unknown amount (i.e., it can be seen that r_ind_c > r_ind_a). Therefore, the gradient of the search space indicates that r_ind_a is somewhere below r_ind_c, and in order to reduce the difference, r_ind_c should be decreased. ○As time passes, if H2 receives more second spikes of the CS spike pair than H1, it can be seen that r_ind_c is too low by some unknown amount (i.e., it can be seen that r_ind_c < r_ind_a). Therefore, the gradient of the search space indicates that r_ind_a is somewhere above r_ind_c, and in order to reduce the difference, r_ind_c should be increased. ●A certain amount of change that decreases or increases r_ind_c determines the learning rate, and this amount shall be called R_LR.

[0046] According to these rules, if the optimization process happens to start with r_ind_c lower than r_ind_a, more spikes will occur at H2 than at H1, causing a net increase in r_ind_c. As r_ind_c increases, the time-axis projection of th_c will be reduced (i.e., it will cause a decrease in TOD_c). For the purpose of explanation, assume that the decrease in TOD_c is not sufficient to the extent of exiting mode 1 (i.e., TOD_c will not be below TOD_a). If r_ind_c starts higher than r_ind_a, adjusting (i.e., reducing) r_ind_c cannot exit mode 1 (because this will increase the amount by which TOD_c exceeds TOD_a).

[0047] Thus, for this first mode of operation, equilibrium can be reached simply when r_ind_c is equal to r_ind_a and TOD_a is less than TOD_c, without any additional mechanisms (discussed below). In that situation, an equal number of spikes will still occur in H2 and H1, implying a net dynamic equilibrium.

[0048] Figure 27B illustrates the second primary mode of operation, in which TOD_a is greater than TOD_c. Like Figure 27A, Figure 27B is composed of upper and lower subgraphs. The upper subgraph of Figure 27B is the same as the upper subgraph of Figure 27A (hence they are both labeled 2700). The lower subgraph of Figure 27B (labeled 2702) differs from the lower subgraph of Figure 27A (labeled 2701) only in that TOD_a is greater than TOD_c.

[0049] It is observed that in the mode 2 situation, since r_shr always extends at least some amount into the H2 region (with the assumption that TOD_a>TOD_c), and since r_shr always extends less (if at all) into the H1 region, the net spiking rate of H2 will always be higher than the net spiking rate of H1. This observation can be used to adjust TOD_c towards TOD_a as follows: If the second spike of a CS spike pair occurs in H2: Assume this is the result of TOD_a extending beyond TOD_c by at least some unknown amount. Act to reduce the rate of imbalance (between H2 and H1) by increasing TOD_c by a constant amount towards TOD_a (by decreasing th_c by a constant amount). While this assumption is not necessarily true when dealing with individual spike pairs, statistically, across a large number of spike pairs there will always be more second spikes in H2 than in H1 (as long as TOD_a extends beyond TOD_c by at least some amount). If the second spike of the CS spike pair occurs in H1: assume this is the result of balanced rates between H2 and H1, and therefore decrease TOD_c by a constant amount (by increasing th_c by a constant amount). Although such a decrease serves to slow the approach of TOD_c towards TOD_a (if TOD_c is in fact less than TOD_a), it is necessary in case the TOD learning device eventually achieves the first mode of operation (i.e., achieves TOD_c being equal to or greater than TOD_a). In that first mode, once r_ind_c is equal to r_ind_a, not only are the changes in r_ind_c balanced, but so are the changes in TOD_c, resulting in a net dynamic equilibrium in TOD_c.

[0050] The constant amount of change by which TOD_c is lowered or increased (through adjustment of th_c) determines the learning rate, and this amount will be referred to as TH_LR.

[0051] Note that in mode 2, the greater tendency for spikes to occur in H2 than in H1 also causes an increase in r_ind_c (because an increase is needed if the TOD learning device is actually in mode 1, and it is assumed that the device does not know whether it is actually in mode 1 or mode 2). As noted above, such an increase in rate tends to reduce TOD_c, thus acting to offset a constant increase in TOD_c.

[0052] Eventually, however, r_ind_c is increased to a high enough rate that each quantified increase in rate (by R_LR) reduces TOD_c by less than the increase in TOD_c (caused by the reduction in th_c by TH_LR). Furthermore, as TOD_c approaches TOD_a, rate increases occur less frequently (as the average rate across H2 drops toward the average rate across H1). Eventually, TOD_c will be equal to or greater than TOD_a, resulting in the first mode of operation, where an equal number of spikes (on average) occur in H2 or H1. Thus, in the first mode of operation, quantified changes in th_c are balanced and have no effect on the position of TOD_c.

[0053] As already mentioned above, in relation to FIG. 27A, it is understood that under equilibrium conditions in the first mode, without further mechanisms, TOD_c may remain greater than TOD_a and not necessarily equal to TOD_a. This problem can be addressed by adding an additional mechanism to reduce TOD_c. In particular, th_c can always be increased by a small constant increment each time a spike pair is detected, regardless of whether the spike pair is in the H2 or H1 half. To prevent a constant (or domain-independent) increase in th_c from having a significant effect on the accuracy of the result (the result being a value of TOD_c that is an accurate estimate of TOD_a), the value used can be a small fraction of TH_LR. For example, a value of TH_LR / 10 or less can be used.

[0054] 3. Split embodiment 3.1 Overview Figure 20 corresponds to Figure 1 of the '590 application. The main difference is that the "soma" 0121 of Figure 1 has been replaced with TOD learning units 2021 and 2022. Each TOD learning unit has an identical internal structure, the only difference being their connections to spike streams 2001 and 2002. Each TOD learning unit is designed to learn TOD from CS spike pairs, where the first spike of each pair considered appears at the "Other" input and the second spike appears at the "Me" input. As can be seen, this results in TOD units 2021 and 2022 operating as follows: ●TOD learning unit 2021 learns TOD from CS spike pairs, where the first spike is from stream 2002 (via CCU 2012) and the second spike is from stream 2001 (via CCU 2010). ●TOD learning unit 2022 learns TOD from CS spike pairs, where the first spike is from stream 2001 (via CCU 2010) and the second spike is from stream 2002 (via CCU 2012).

[0055] Thus, when combined, TOD learning units 2021 and 2022 can recognize either direction of inter-stream spike pairs occurring across streams 2001 and 2002, with the output of one TOD learning unit or the other driving the “Shared Event” output of OR gate 2015.

[0056] The operation of the two TOD learning units, with respect to learning to recognize CS spike pairs, can be understood with reference to FIGS.

[0057] 3.2 Generalization Figure 26 shows an exemplary partitioning of the respective implementations of the TOD learning units 2021 and 2022 that is particularly suitable for hardware. Although Figure 26 is partitioned for a hardware-centric implementation, it is also relatively generalized with respect to the implementation of the particular technology selected.

[0058] As can be seen, for each TOD learning unit, the "Me", "Other", and "Other Shared" inputs are directed to a state machine 2610 called the "Pair Detector".

[0059] The purpose of the pair detector 2610 is to detect whenever a pair of consecutive spikes occurs, where (among other potential requirements) the first spike occurs at the Other input and the immediately following consecutive spike occurs at the Me input. Upon a wake-up signal or reset, the pair detector 2610 may be designed to start in state #0.

[0060] The directed edge from state #0 to state #1 of the pair detector 2610 indicates that when a spike is received at the Other input, it outputs a pulse at the "Start or Restart" (SR) output while transitioning to state #1. The SR pulse triggers the exponential decay block 2620, which generates an exponentially decayed value at the "P" (or "Probability") output. As described above with respect to Figures 27A-B, the exponential decay (where the rate of r_ind_c is a good approximation of r_ind_a) represents a probability value that starts at 1 and decays towards 0. If the exponential decay block 2620 is already undergoing exponential decay, the arrival of another SR trigger pulse restarts the decay process (at 1). According to one exemplary scheme for implementation, the value at the "P" output may be represented by a voltage.

[0061] As the decay process progresses, the value of "P" is evaluated by comparators 2640 and 2641 using references 2630 and 2631, respectively. Specifically, reference 2630 provides a signal (usually a voltage) representative of th_c, while 2631 outputs th_c divided by two. Comparator 2640 asserts its output line when P falls below th_c. Thus, in terms of time, comparator 2640 asserts its output only after TOD_c has elapsed. Similarly, comparator 2641 asserts its output line when P falls below th_c / 2. Thus, in terms of time, comparator 2641 asserts its output only after an MEA time (in the time domain from TOD_c to infinity) has elapsed.

[0062] If a spike is received at the "Me" input while already in state #1, the pair detector 2610 transitions from state #1 to state #2. This transition to state #2 causes the state machine 2610 to output a pulse at its event pair detect (EPD) output. The EPD is applied to AND gates 2650-2652, which decode the output of the comparator: • As can be seen, AND gate 2652 asserts its output (which becomes the Shared Event output of the TOD learning unit) if P is not below th_c at time EPD. • AND gate 2651 identifies whether P is within H2 (of Figures 27A-27B) by determining that P is below th_c but not below th_c / 2. • AND gate 2650 identifies whether P is within H1 by determining that P is below th_c / 2.

[0063] If the transition from state #1 to state #2 causes the first TOD learning unit to assert its Shared Event output, that output will appear as the "Other Shared" (OS) input in the second TOD learning unit (per FIG. 20). Assertion of the OS input forces the pair detector 2610 of the second TOD learning unit into state #0 (if not already in state #0). The return to state #0 ensures that the same spike that caused the first TOD learning unit to recognize a shared CS spike pair cannot serve as the first spike of another spike pair in the second TOD learning unit.

[0064] As previously discussed with respect to Figures 27A-B, the estimated rate of an independent CS spike pair (r_ind_c) is made to approach the actual rate of such spike pair (r_ind_a) by adjusting the rate based on whether the second spike of the CS spike pair is in region H2 or H1. The learning rate of such adjustment was described by the variable R_LR. As can be seen in Figure 26, the exponential decay unit 2620 is shown as having two rate adjustment inputs, one of which is labeled +R_LR (a pulse at this input increases the decay rate by R_LR) and the other is labeled -R_LR (a pulse decreases the decay rate by R_LR). As can be seen, a spike determined (by AND 2651) to be in H2 causes a pulse at the +R_LR input, and a spike determined (by AND 2650) to be in H1 causes a pulse at the -R_LR input.

[0065] Similarly, Figures 27A-B were considered with respect to adjusting th_c towards th_a (or TOD_c towards TOD_a, respectively) based on whether the second spike of a CS spike pair is in region H2 or H1. The learning rate of such adjustment was described by the variable TH_LR. As can be seen in Figure 26, the reference standard 2630 is shown as having two level adjustment inputs, one of which is labeled +TH_LR (a pulse at this input decreases TOD_c by increasing th_c) and the other is labeled -TH_LR (a pulse at this input increases TOD_c by decreasing th_c). As can be seen, a spike determined to be in H1 causes a pulse at the +TH_LR input, and a spike determined to be in H2 causes a pulse at the -TH_LR input. Adjusting the output of 2630 automatically adjusts the output of 2631 since 2631 acts to divide the current signal output of 2630 by two.

[0066] Figure 24 shows a simulation of how two instances of the TOD learning unit implementation of Figure 26 might be performed for spike streams 2001 and 2002 when incorporated into the design of Figure 20. The simulation is for spikes a1-i1 in stream 2001 and spikes a2-d2 in stream 2002. A total of eight CS spike pairs have been identified between these spikes, all of which are independent, with the exception of spike pair c2 and e1 (which can also be expressed as (c2, e1)). This independent spike pair ends up in stream 2001 (i.e., its second element is within stream 2001), so it is recognized by the TOD learning unit 2021.

[0067] To reduce the space taken up by the graph, Figure 24 uses the following abbreviations: ●TOD Learning Unit 2021 is “LU1” and TOD Learning Unit 2022 is “LU2”. ● "pr" and "sp" are "pair" (meaning a pair of spikes) and "spike", respectively. So, for example, "pr1" means the first spike pair recognized in a stream of spike pairs, and "sp1" means that the first spike of a pair was recognized. ● "ipair" means that an independent inter-stream pair was recognized, and "spair" means that a shared inter-stream pair was found. ●NOP means that "No Operation" will be performed as a result of the spike. SKIP means that the spike is skipped from consideration of whether it is part of a spike pair.

[0068] A spike-by-spike simulation of the behavior of LU1 and LU2 (both assumed to start in state #0) can be described as follows: ● a1 (see also note box 2410) o LU1: Applied to the Me input, executes a NOP and the state machine 2610 simply returns to state #0. LU2: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #0 to state #1. Thus, LU2 has recognized the first spike of potentially the first spike pair to be recognized. The assertion of SR starts a timing operation. ● a2 (see also note box 2411) LU1: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #0 to state #1. Thus, LU1 has recognized the first spike of potentially the first spike pair to be recognized. The assertion of SR starts a timing operation. LU2: Assert the "EPD" or "Event Pair Detect" signal while transitioning state machine 2610 from state #1 to state #2. For illustrative purposes, assume that the time separation of spikes a1 and a2 is >TOD_c. Thus, an independent inter-stream pair has been recognized by LU2 (indicated by note box 2430). ● b1 (see also note box 2412) LU1: Asserts the "EPD" or "Event Pair Detected" signal while transitioning state machine 2610 from state #1 to state #2. For purposes of illustration, assume that the time separation of spikes a2 and b1 is >TOD_c. Thus, an independent inter-stream pair has been recognized by LU1 (indicated by note box 2431). LU2: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #2 to state #1. Thus, LU2 has recognized the first spike of a potentially second spike pair to be recognized. The assertion of SR starts a timing operation. ● c1 (see also note box 2413) LU1: Causes the state machine 2610 to perform a NOP, in which case the state machine transitions recursively from state #2 back to state #2 and does not assert any output signals. LU2: A complete repeat of the actions described above occurs when spike b1 is applied to the Other input, the only difference being that the timing starts from the time of spike c1 instead of b1. ● b2 (see also note box 2414) LU1: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #2 to state #1. Thus, LU1 has recognized the first spike of a potentially second spike pair to be recognized. The assertion of SR starts a timing operation. LU2: Asserts the "EPD" or "Event Pair Detected" signal while transitioning state machine 2610 from state #1 to state #2. For purposes of illustration, assume that the time separation of spikes c1 and b2 is >TOD_c. Thus, another independent inter-stream pair has been recognized by LU2 (indicated by note box 2432). ● d1 (see also note box 2415) LU1: Asserts the "EPD" or "Event Pair Detected" signal while transitioning state machine 2610 from state #1 to state #2. For purposes of illustration, assume that the time separation of spikes b2 and d1 is >TOD_c. Thus, an independent inter-stream pair has been recognized by LU1 (indicated by note box 2433). LU2: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #2 to state #1. Thus, LU2 has recognized the first spike of a potentially third spike pair to be recognized. The assertion of SR starts a timing operation. ● c2 (see also note box 2416) LU1: Asserts the "SR" or "Start or Restart" signal applied to its Other input, transitioning state machine 2610 from state #2 to state #1. Thus, LU1 has recognized the first spike of a potentially third spike pair to be recognized. The assertion of SR starts a timing operation. LU2: Asserts the "EPD" or "Event Pair Detected" signal while transitioning state machine 2610 from state #1 to state #2. For purposes of illustration, assume that the time separation of spikes d1 and c2 is >TOD_c. Thus, another independent inter-stream pair has been recognized by LU2 (indicated by note box 2434). ● e1 (see also note box 2417) LU1: Asserts the "EPD" or "Event Pair Detected" signal while transitioning state machine 2610 from state #1 to state #2. For purposes of illustration, assume that the time separation of spikes c2 and e1 is ≦TOD_c. Thus, the first shared inter-stream pair has been recognized by LU1 (indicated by note box 2435). Immediately after asserting EPD, the "Shared Event" output of LU1 is asynchronously asserted and applied to the "Other Shared" (OS) input of LU2. LU2: Rather than transitioning from state #2 to state #1, and rather than recognizing the first spike of a potentially fourth spike pair to be recognized, the OS input to LU2 is asserted. The assertion of OS causes LU2's state machine to transition from state #2 to state #0. This prevents spike e1 from becoming part of another CS spike pair, since e1 is already part of a shared CS spike pair. Spike e1 is therefore skipped from consideration by LU2. f1, g1, and h1 (see also note box 2418) ○ LU1: f1, f1, and h1 applied to the Me inputs cause LU1 to execute a NOP and the state machine 2610 simply returns to state #2 (similar to the behavior of LU1 for spike a1). ○LU2: Applied to the Other input, f1 asserts the "SR" or "Start or Restart" signal, transitioning state machine 2610 from state #0 to state #1. At each of g1 and h1, it simply reasserts the SR signal each time, returning to state #1. Thus, LU2 recognizes three times, the first spike of a potentially fourth spike pair to be recognized. Each time SR is asserted, a timing run is started or restarted, with the final timing run beginning at time h1. ● d2 (see also note box 2419): The actions taken by LU1 and LU2 are substantially the same as those described above upon receipt of spikes a2, b2, or c2. ● i1 (see also note box 2420): The actions taken by LU1 and LU2 are substantially the same as those described above upon receipt of spikes b1, c1, or d1.

[0069] 3.3 Electrical Circuit Implementation Figure 29 shows an example of an electrical circuit level implementation according to the hardware division in Figure 26. The correspondence between Figure 26 and Figure 29 is as follows: • External input interface 2600 (external to the TOD learning unit) in FIG. 26 corresponds to 2900 in FIG. The external output interface 2601 in FIG. 26 corresponds to 2901 in FIG. ● State machine 2610 of Figure 26 corresponds to outline 2910 of Figure 29. Like state machine 2610, 2910 has three inputs (Me, Other, and Other Shared) and two outputs (SR and EPD). A detailed description of state machine 2910 is provided below. ● Unit 2920 corresponds to the exponential decay unit 2620. As can be seen, the exponential decay of 2920 is achieved by an RC combination of a variable resistor 2924 and a capacitor 2923. The inputs to increase or decrease the decay rate of 2620 (+R_LR and -R_LR, respectively) are implemented within 2920 by decreasing or increasing the resistance of 2924, respectively. Asserting the SR input of 2920 causes a switch 2921 to recharge a capacitor 2923 using a unitary voltage source 2922. ● Reference 2630 corresponds to a variable voltage source 2930 with a maximum output of 1 volt. The inputs for increasing or decreasing the thresholds generated by 2630 (+TH_LR and -TH_LR, respectively) are implemented in 2930 by increasing or decreasing the voltage of 2924, respectively. To ensure convergence of TOD_c towards TOD_a, the EPD output of 2910 provides a region-independent signal to 2930 if TOD_c happens to be >TOD_a (meaning that equilibrium can be reached based on an appropriate value of r_ind_c). As discussed above with respect to the generalized hardware implementation, the adjustment of th_c with each EPD pulse can be much smaller (e.g., an order of magnitude or less) than the region-dependent adjustment. The division of th_c by 2631 is most conveniently implemented in Figure 29 by a voltage divider 2931. 2931 is simply two equal value resistors connected between th_c and ground. 26 correspond to the op-amp comparators 2940 and 2941, respectively, of FIG. *AND gates 2650 to 2652 in FIG. 26 correspond to AND gates 2950 to 2952 in FIG. 29, respectively. A detailed description of the operation of the state machine 2910 is as follows: ○The state is held by two flip-flops: a set-reset flip-flop 2911 and a negative-edge triggered flip-flop 2912. Both flip-flops are reset at power-up (i.e., Q is low). ○One shot 2913 and 2914 each generate a short pulse, EPD and SR respectively, at their output upon a positive edge at their trigger input. o In most cases, the TOD learning unit may expect to receive independent CS spike pairs. In this case, the state machine 2910 spends most of its time bouncing between states represented as #1 and #2 in Figure 26. These states are maintained by the SR flip-flop 2911. When flip-flop 2912 is in the reset state,

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[0070] 4. Pseudocode Implementation As an alternative to the hardware-centric approach of Chapter 3, the TOD learning units may also be implemented in software (or by a suitable combination of software and hardware as dictated by the constraints of the particular application environment).

[0071] 28A-B show a pseudocode procedure called Learn_TOD_H2H1 as an example of the software-centric approach, which is based on the Python programming language.

[0072] Each execution instance of the pseudocode in FIGS. 28A-28B corresponds to either TOD learning unit 2021 or 2022 in FIG.

[0073] Lines 5-13 of FIG. 28A introduce certain global variables, while lines 15-26 introduce internal variables that are local to each instance of Learn_TOD_H2H1.

[0074] Lines 28 to 34 of FIG. 28A deal with the case where a spike is applied to the Other input of the TOD learning unit.

[0075] If the "elif" on line 36 (Figure 28A) tests positive, then we know that a new CS spike pair has been identified, where the current spike is applied to the Me input and the previous spike is applied to the Other input of the TOD learning unit. All the remaining pseudocode deals with the case where line 36 tests positive.

[0076] Line 38 determines the time interval between spikes in the current CS spike pair.

[0077] Line 39 converts this time interval into a probability by applying exponential decay to the unit value (and by assuming that r_ind_c is an accurate estimate of r_ind_a).

[0078] Line 43 sets an indicator that a previous event was applied to the Me input for the next invocation of this instance of Learn_TOD_H2H1.

[0079] We need to ensure that, although a CS spike pair is found as a result of the current spike being applied to the Me input, the spike earlier than the current CS spike is not found to be part of a shared CS spike pair, since under our model of shared events this will at best appear as a single spike per stream. This is ensured by testing the "lastEventWasShared" variable in line 1 of FIG. 28B. If this variable tests TRUE, processing jumps directly to line 50 of FIG. 28B. Since only the previous spike was found to be part of a previously identified shared CS spike pair, line 50 sets the value of lastEventWasShared so that the current spike can be paired in a subsequent call. However, if lastEventWasShared tests FALSE (the more likely test outcome), then lines 4-46 are potential targets for execution. Lines 4-46 are the subject of the remaining discussion of Learn_TOD_H2H1.

[0080] Line 4 introduces a region-independent tendency towards reducing TOD_c for the situation where TOD_c happens to be > TOD_a and the region-based adjustment can be stabilized simply by adjusting r_ind_c close enough to r_ind_a.

[0081] Line 8 tests the possibility that this most recent CS spike pair does in fact reflect an underlying shared event. If so, lines 10 and 14 are executed: ● Line 10 represents the assertion of the “Shared Event” output of the external interface 2601 with reference to FIG. • Now that the current spike is found to be part of a shared CS spike pair, line 14 ensures that the current spike cannot be found as part of a subsequent spike pair.

[0082] If line 8 is evaluated negatively, then we know that an independent CS spike pair has been found. The task then becomes one of adjusting th_c and r_ind_c appropriately based on the current TBE (lines 17-44 in Figure 28B), where the current TBE is used as a negative proxy for TOD_a. Specifically, the current TBE is used as a negative proxy for values ​​that are not TOD_a.

[0083] Since the current spike is not known to be part of a shared CS spike pair, line 20 allows the current spike to be part of a subsequent spike pair.

[0084] Line 23 performs the function of 2631 in Figure 26, i.e., splitting the time range from TOD_c to infinity in MEA times. Specifically, the time range from TOD_c to infinity is split into halves, with H2 being the earlier half (i.e., before MEA times) and H1 being the later half.

[0085] The test whether H2 or H1 is true is done in line 30: Lines 33-36 are executed if the TBE of the current CS spike pair is found to be within H2. As a negative proxy for TOD_a, adjustments are made to th_c and r_ind_c so that future CS spike pairs are more likely to be within the time range of H1. Lines 41-44 are executed if the TBE of the current CS spike pair is found to be within H1. As a negative proxy for TOD_a, adjustments are made to th_c and r_ind_c so that future CS spike pairs are more likely to be within the time range of H2.

[0086] Regardless of whether the CS spike pair just processed is shared or independent, line 46 ensures that th_c is always within the proper range of probability.

[0087] 5 Multi-scale, multi-sample 5.1 Overview Since the search space formed by TOD_c and r_ind_c is convex with no local minima, the procedure presented herein converges towards a solution (i.e., TOD_c=TOD_a and r_ind_c=r_ind_a). However, as described above with respect to Mode 2, temporary situations may occur where optimizing one variable works against optimizing the other variable. For example, as described above with respect to Mode 2, the main goal is to increase TOD_c to get closer to TOD_a (i.e., TOD_c=TOD_a, where the current state is TOD_a>TOD_c). However, because TOD_a>TOD_c, region H2 will have a higher spike rate than H1, which will increase r_ind_c. For a given value of th_c, increasing r_ind_c will tend to make TOD_c smaller (i.e., the difference between TOD_c and TOD_a will increase).

[0088] Also, poor selection of initial values ​​for r_ind_c, TOD_c, or both may increase convergence time.

[0089] Therefore, for practical efficiency purposes (depending on the real-world application and its constraints), the multi-scale and multi-sample techniques of this chapter may be useful.

[0090] 5.2 Illustrative Embodiments Other time scales are possible other than dividing the time range from TOD_c to infinity by 2. For example, Figures 30A-B show an example of dividing the time range after TOD_c into quarters.

[0091] Figure 30A corresponds to Figure 27A in that Figure 30A also shows what is called Mode 1 (or first mode), where TOD_c>TOD_a. Similarly, Figure 30B corresponds to Figure 27B in that Figure 30B also shows what is called Mode 2 (or second mode), where TOD_a>TOD_c.

[0092] Along the probability axis (TBE_P), two additional division points (in addition to FIGS. 27A-B) are identified (in each of FIGS. 30A-B: ● Midpoint of the range from th_c / 2 to th_c: When projected onto the time axis, (3 / 4)th_c identifies the location of this upper half of the MEA. This value of MEA can be distinguished as MEA_H2, since it divides the time range of H2. In the example of Figures 30A-B, (3 / 4)th_c = 0.555 and MEA_H2 = 0.20s. ● Midpoint of the range from 0 to th_c / 2: When projected onto the time axis, (1 / 4)th_c identifies the location of this lower half of the MEA. This value of MEA can be distinguished as MEA_H1, since it divides the time range of H1. In the example of Figures 30A-B, (1 / 4)th_c = 0.185 and MEA_H2 = 0.565s.

[0093] Substantially the same logic described above for utilizing H2 and H1 to adjust th_c towards th_a and r_ind_c towards r_ind_a can be used for either or both of the following two quarter pairs: Q4 and Q3 (also referred to as Q4 / Q3) or Q2 and Q1 (also referred to as Q2 / Q1). As shown in the brackets for H1 and H2 at the top of each of Figures 30A-B, the basic logic is that independent CS spike pairs in H2 cause an increase (hence the "+" sign). This increase is for rate and TOD_c. Conversely, independent CS spike pairs in H1 cause a decrease (hence the "-" sign). This decrease is for rate and TOD_c.

[0094] As shown in the brackets for Q4 and Q3 at the top of each of Figures 30A-B, independent CS spike pairs in Q4 cause an increase (hence the "+" sign), while independent CS spike pairs in Q3 cause a decrease (hence the "-" sign). The same annotation applies to the brackets for Q2 and Q1 at the top of each of Figures 30A-B: independent CS spike pairs in Q2 cause an increase, while independent CS spike pairs in Q1 cause a decrease.

[0095] If both Q4 / Q3 and Q2 / Q1 are utilized simultaneously, this can be called an example of a multi-sample scheme, since the time range after TOD_c is actually sampled at two different locations.

[0096] If both Q4 / Q3 and Q2 / Q1 are utilized simultaneously, and also H2 / H1, this can be called an example of a multi-scale scheme (and is still multi-sample, for reasons explained immediately above). This is because the time range after TOD_c is actually utilized in two different time scales, a time scale based on a quarter and a second time scale based on a half. It is interesting to note that this particular multi-scale and multi-sample scheme simplifies to simply utilizing Q4 and Q1. This is easily understood by examining the plus and minus signs in the parentheses at the top of each of Figures 30A-B: ●When H2 overlaps with Q3, H2 and Q3 cancel each other out and only Q4 is active. ●When H1 overlaps with Q2, H1 and Q2 cancel each other out and only Q1 is effective.

[0097] 5.3 Electrical implementation example Figure 31 shows an example of a circuit-level implementation of the multi-scale (quarter and half) and multi-sample (Q4 / Q3 and Q2 / Q1) scheme described above. The circuit in Figure 31 follows a similar hardware partitioning as already discussed with respect to Figures 26 and 29. The correspondence between Figures 29 and 31 is as follows: - The external input interfaces 2900 and 2901 of FIG. 29 remain the same in FIG. • The state machine 2910 of Figure 29 remains the same in Figure 31 (although only the outline shapes are shown in Figure 31). - The exponential decay unit 2920 of FIG. 29 remains the same in FIG. - The variable voltage source 2930 of FIG. 29 remains the same in FIG. • Opamp comparators 2940 and 2941 of Figure 29 remain the same in Figure 31. Opamp comparators 3120 and 3121 are new to Figure 31 for testing (3 / 4)th_c and (1 / 4)th_c respectively. *AND gates 2950-2952 in Figure 29 remain the same in Figure 31. AND gates 3130-3133 for decoding Q1-Q4 respectively are new to Figure 31.

[0098] OR gates 3140 and 3141 implement the multi-scale and multi-sample scheme described above. 3140 decodes for increases in (r_ind_c, TOD_c, or both), while 3141 decodes for decreases in (r_ind_c, TOD_c, or both). It has also been shown that this multi-scale and multi-sample scheme can be simplified to simply Q4 meaning an increase and Q1 meaning a decrease.

[0099] 5.4 Pseudocode Implementation 32A-32C show a multi-scale, multi-sample approach to the TOD learning unit, an alternative to the hardware-centric approach of Section 5.3.

[0100] 32A-32C show a pseudocode procedure called Learn_TOD_MSMS, which is based on the Python programming language.

[0101] Each execution instance of the pseudocode in FIGS. 32A-32C corresponds to either TOD learning unit 2021 or 2022 in FIG.

[0102] The TOD learning unit may also be implemented by any suitable combination of software and hardware, as dictated by the constraints of a particular application environment. The trade-offs are similar to those discussed above in Chapter 4 ("Pseudocode Implementation") in connection with the pseudocode procedure Learn_TOD_H2H1.

[0103] Learn_TOD_H2H1 is shown in Figures 28A-B. All the pseudocode for Learn_TOD_H2H1 is included in Learn_TOD_MSMS. The only functional difference between Learn_TOD_H2H1 and Learn_TOD_MSMS is that the code in Figure 28B, lines 30-43, has been expanded. The same functionality as lines 30-43 of Figure 28B has been maintained, but additional functionality has been added. Thus, lines 30-43 of Figure 28B correspond to the following portions of Figure 32: lines 26 of Figure 32B to line 20 of Figure 32C. A more detailed comparison of Figures 28A-B and Figures 32A-C continues now.

[0104] Lines 30-35 of Figure 28B handle the case when TBE is within H2. If the second spike of a CS spike pair is within this region, the logic is to increase both the lower bound of H2 (i.e., see line 32) and the rate r_ind_c (i.e., see line 34). Lines 26-32 of Figure 32B implement the same logic as lines 30-35 of Figure 28B.

[0105] Similarly, lines 37-43 of Figure 28B handle the case when TBE is within H1. If the second spike of a CS spike pair is within this region, the logic is to decrease both the lower bound of H2 (i.e., see line 39) and the rate r_ind_c (i.e., see line 42). Lines 1-8 of Figure 32C implement the same logic as lines 37-43 of Figure 28B.

[0106] However, to implement the additional scale of quarters, lines 34-44 of FIG. 32B add the ability to process quarters Q4 / Q3 if the TBE tests to be in H2. Line 36 tests whether the second spike of the CS spike pair is in Q4 or Q3. If the spike is in Q4, the same increase logic is performed (lines 38-39 of FIG. 32B) as described above for H2 (lines 28-30 of FIG. 32B). Similarly, if the spike is in Q3, the same decrease logic is performed (lines 42-43 of FIG. 32B) as described above for H1 (lines 3-6 of FIG. 32C).

[0107] To handle the quarter Q2 / Q1, lines 10-20 of FIG. 32C were added when the TBE tests to be in H1. Line 12 tests whether the second spike of the CS spike pair is in Q2 or Q1. If the spike is in Q2, the same increase logic is performed (lines 14-15 of FIG. 32C) as described above for H2 (lines 28-30 of FIG. 32B). Similarly, if the spike is in Q1, the same decrease logic is performed (lines 18-19 of FIG. 32C) as described above for H1 (lines 3-6 of FIG. 32C).

[0108] It is interesting to note that, as mentioned above in Section 5.3 (Example Electrical Implementation), the combination of all the multi-scale, multi-sample logic (from line 23 in Figure 32B to line 20 in Figure 32C) becomes simple and only the following logic is required: - If TBE is within Q4 (tested by lines 26 and 36 of FIG. 32B), perform the increase logic described above for Q4 (lines 38-39 of FIG. 32B). - If TBE is in Q1 (tested by lines 1 and 16 of FIG. 32C), perform the decrease logic described above for Q1 (lines 18-19 of FIG. 32C).

[0109] 6 Further Variations Section 5.2 above ("Exemplary Embodiments") discussed the use of Q4 / Q3 and Q2 / Q1 as an exemplary multi-sample scheme (at a quarter scale of the range). It is worth noting that while Section 5.2 discusses the simultaneous use of Q4 / Q3 and Q2 / Q1, this is not necessarily on an individual spike (or "per spike") basis. For example, for an individual spike n, only Q4 / Q3 may be active. For a spike that occurs i spikes after spike n (i.e., for the later spike n+i), only Q2 / Q1 may be active.

[0110] Furthermore, Q4 / Q3 and Q2 / Q1 each need not be active for the same number of spikes: for example, as part of the sampling process, Q4 / Q3 may be active for spike set x and Q2 / Q1 may be active for spike set y, where the number of elements in set x is not equal to the number of elements in set y (symbolically, |x|≠|y|).

[0111] In Figures 30A-B, each scale (either half the range or quarter the range) is shown as having two properties: 1.These regions occupy the entire range of the TBE_P axis, from 0 to th_c. 2. The regions are spaced evenly so that an integer number of regions can occupy the entire range of the TBE_P axis from 0 to th_c.

[0112] Neither of these two properties is required.

[0113] With regard to the first of the above properties, for example, there may be cases where only Q4 / Q3 are used (or "covered") at a scale of one-quarter of the range. With regard to the discussion immediately above, where Q4 / Q3 are described as being active for spike set x and Q2 / Q1 are described as being active for spike set y, this can be considered equivalent to the situation where y={} and x≠{} (i.e., only Q4 / Q3 are active, and are active for spike set x).

[0114] A drawback of covering only a portion of the TBE_P axis at a particular scale (also called "partial coverage") is that there may be values ​​(of TOD_a, r_ind_a, or both) for which convergence cannot be achieved (at least not without additional gradient detection at other scales). Also, each additional range will introduce some additional complexity, at least with respect to the design of the TOD learning units (such as 2021 and 2022 in FIG. 20), and may also add implementation (or physical realization) complexity.

[0115] Advantages of partial coverage include: Within the operating range, partial coverage can act to speed up convergence, increase stability approaching convergence, or both. Outside the operating range, partial coverage is unlikely to significantly slow convergence, and it does not decrease the stability of convergence.

[0116] As an example of the second property given above, each of Q1-Q4 is shown (in Figures 30A-B) as covering one quarter of the TBE_P axis from 0 to th_c. In the case of partial covers, this is not necessarily the case. If Q4 / Q3 were to be used as partial covers, then each might be positioned (for example) with respect to the TBE_P axis as follows: ●Q4: Instead of placing them in the range from (0.75)th_c to (1.00)th_c, place them in the range from (0.59)th_c to (0.84)th_c. ●Q3: Instead of placing them in the range from (0.50)th_c to (0.75)th_c, place them in the range from (0.34)th_c to (0.59)th_c.

[0117] Note that the use of the quarter range scale as an example is arbitrary. Without loss of generality, the same technique can be applied to any other fractional quantities. Furthermore, the use of 0.59 as the division point between Q4 and Q3 is also arbitrary. Without loss of generality, the same technique can be applied to place other division points between quarters of the range or other fractional quantities.

[0118] Also, the regions utilized as part of searching TOD_a and r_ind_a do not need to be contiguous. For example, with reference to FIGS. 30A-B, it is noteworthy that a fully functional embodiment can be realized utilizing only Q4 and Q1. (Section 5.2 notes that utilizing only Q4 and Q1 results in a simplified net result when the following multi-scale and multi-sample approach is used: H2 / H1, in conjunction with Q4 / Q3 and Q2 / Q1.) A potential drawback of not utilizing Q3 or Q2 is that spikes that are within those time domains will not function to converge toward TOD_a and r_ind_a. A potential advantage of not utilizing Q3 or Q2 is that the process by which such convergence proceeds will be more stable.

[0119] Furthermore, it is not necessary to use an even number of regions as part of searching TOD_a and r_ind_a. For example, referring to Figures 30A-B, a fully functional embodiment can be realized utilizing the following three regions: Q4, Q3, and H1. The main requirement is probabilistic symmetry. In this example, let us denote the portions of the TBE_P axis for Q4, Q3, and H1, respectively, as P(Q4), P(Q3), and P(H1) (respectively). The main requirement is that the net probability of a region increasing by a constant amount (or "+") is equal to the net probability of a region decreasing by a constant amount (or "-"). (As discussed above in Section 5.2, "Illustrative Embodiments," a constant increasing region will increase r_ind_c and TOD_c when each spike falls within its range, while a constant decreasing region will decrease r_ind_c and TOD_c when each spike falls within its range.) In this example, we know that P(Q4)+P(Q3)=P(H1). Thus, the only change required between these three regions from what is shown in Figures 30A-B is to change Q3 to a constant increasing region like Q4.

[0120] The TOD learning unit may generate useful outputs other than whether a sharing event was detected. For example, the estimated discrimination threshold (i.e., th_c) may be a useful signal. In the example hardware implementation of FIGS. 29 and 31, this is reflected in the setting (in either analog or digital form) of the variable voltage source (2930). Similarly, the average rate of occurrence of independent inter-stream spike pairs (independent CSSPs) may also be a useful output. In the example hardware implementation of FIGS. 29 and 31, this is reflected in the setting of the variable resistor (2924).

[0121] 7 Glossary of selected terms Summing Amplifier: It outputs a voltage that is the sum of the voltages present at its inputs at any given time. Event: Any kind of discrete discontinuity when considering the time domain behavior of a signal. one shot: has an input trigger and one output. When a trigger signal is received it generates a pulse at the output. Region: A range of values ​​along either the probability (i.e., TBE_P) or time (i.e., TBE) axis. For example, a probability range from 0 to th_c, or a time range from infinity to TOD_c, respectively, may be divided so that each region is one half or one quarter of the total range. Spike: As used herein, a spike may refer to any event in a signal that, when considered in the time domain, can be considered as at least one discrete, discontinuous transition between two distinct levels. As an example, a spike as used herein may refer to a spike as understood to occur in the field of spiking neural networks. As another example, in the field of digital logic, a spike may refer to an abrupt transition (also called an "edge") of a signal from a first level to a second level. Subtracting Amplifier: At any given time, it outputs the voltage obtained by subtracting the voltage present at its first input from the voltage present at its second input. TBE: Sometimes used herein to refer to the second spike of a CS spike pair (because TBE is the time distance between a pair of spikes). Two shot: has an input trigger and two outputs. Upon receiving a trigger signal, it generates a pulse sequentially at each of the two outputs.

[0122] 8 Computing equipment In accordance with what is generally known to those skilled in the art, the methods, procedures, or techniques of the present invention described herein can be implemented by using any suitable computing hardware, electronic hardware, or a combination of both. Suitable computing hardware may include the use of one or more general-purpose computers or processors. Hardware implementation techniques may include the use of various types of integrated circuits, including digital, analog, or a combination of both (e.g., mixed signal). Digital hardware may include programmable memory (volatile or non-volatile).

[0123] Such hardware, whether in the form of an integrated circuit or otherwise, is typically based on the use of transistors (field effect, bipolar, or both), but may include other types of components (including capacitors, resistors, or inductors). A variety of component technologies may be used, including optical, microelectromechanical, magnetic, or any combination of the foregoing.

[0124] All computing hardware has the property that it consumes energy, requires some time to change state, and occupies some physical space.

[0125] Programmable memory is often implemented in the form of integrated circuits and is subject to the same physical constraints as those mentioned above for computing hardware. Programmable memory is intended to include devices that use any type of physically based effect or property to store information in at least a non-transient manner for a reasonable length of time. The types of physical effects used to implement such storage include, but are not limited to, maintaining a particular state through a feedback signal, charge storage, changing the optical properties of a material, magnetic changes, or chemical changes (reversible or irreversible).

[0126] Unless specifically noted, the terms computing hardware, programmable memory, computer readable medium, system, and subsystem do not include a person or mental steps that a person may undertake.

[0127] Any of the methods, procedures, or techniques described above may also be described as a computer program product, provided that they are implemented by programming a computer or other data processing system. The computer program product may be embodied on any suitable computer readable medium or programmable memory. Information of the type described herein (e.g., data and / or instructions, etc.) on the computer readable medium and / or programmable memory may be stored on a computer readable code device in which it is embodied. The computer readable code device may represent a portion of a memory capable of storing a defined unit of information (e.g., a bit), a memory from which a defined unit of information can be read, or both.

[0128] 9. Appendix This appendix is ​​substantially the entirety of U.S. patent application Ser. No. 62 / 819,590, entitled “Method and Apparatus for Cross Correlation,” filed Mar. 17, 2019, by David Carl Barton, which is hereby incorporated by reference in its entirety.

[0129] Application No. 62 / 819,590 is substantially identical to PCT International Patent Application No. PCT / US2020 / 022869, entitled “Method and Apparatus for Cross Correlation,” filed on March 15, 2020, with David Carl Barton as an inventor, which is also incorporated by reference in its entirety herein.

[0130] 9.1 Introduction Cross-correlation is known to have many important applications. Among these, in the area of spiking neural networks, cross-correlation is predicted to continue to increase in importance, where relative spike timing can be important for proper operation.

[0131] Figure 1 shows an exemplary application scenario in the area of spiking neural networks. The left input is three streams of spikes, S1, S2, and S3. Each spike stream is predicted to contain significant random (or probabilistic) content.

[0132] Regarding the probabilistic content, the temporal size of the inter-spike gap (or ISG) is assumed to have a random distribution (often Poisson), and each ISG i is within the following range: 0 seconds < i < ∞ seconds

[0133] For the entire time range of i, the average spike rate of the spike stream is denoted as r ALL (because this is the rate that includes all spikes that can occur).

[0134] Such content is probabilistic with respect to the stream in which the content occurs and with respect to other streams. However, it is also predicted that non-random events will occur that manifest across two or more input streams. (In the following description, non-random events are often simply referred to as "events".)

[0135] Each stream S1, S2, and S3 is respectively coupled to the F.O.R. inputs of cross-correlation units (or CCUs) 0110, 0112, and 0114. Each CCU has an output labeled "FOR d " As can be seen, each FOR dThe outputs connect to the inputs of "Soma" 0121. At its most basic functional level, Soma can be designed to act as a kind of coincidence detector, generating an output spike every time a spike appears simultaneously on each of its inputs.

[0136] In the following discussion, three input streams have been chosen for convenience of explanation. It will be readily appreciated that a system such as that of FIG. 1 can be applied to any number of inputs without changing the principles of operation. A minimum of two input streams is required. Overall, a system such as that of FIG. 1 can be viewed as a biologically inspired model of a neuron. While biologically inspired, from an engineering (and non-biological) perspective, FIG. 1 can be understood to represent a multi-stream cross-correlator or "MCC."

[0137] When an event occurs in two or more input streams of an MCC, its occurrence in each input stream is expected to have a certain temporal relationship to its occurrence in the other spike streams. Although the multi-stream occurrences of an event are expected to have certain temporal relationships to each other, such occurrences are also expected not to occur simultaneously.

[0138] Any other spike (i.e., any non-event spike) is expected to have a random relationship to all other non-event spikes, both when considered within the input stream in which it occurs and in relation to other input streams. Any such non-event spike is referred to as a "random spike."

[0139] The job of each CCU, 0110, 0112, and 0114, is to determine a delay or time offset so that as many event occurrences as possible across multiple streams occur simultaneously at the output of the CCU (and therefore simultaneously at the input to Soma 0121).

[0140] More specifically, each CCU in FIG. 01 can be viewed as having two inputs: FOR, and ●Other.

[0141] "FOR" (alternatively, "FOR") means "frame of reference" (unless otherwise specified, the use of the terms "FOR" or "FOR" herein refers to a "frame of reference" and not to the preposition "for"). The spike stream presented to the CCU's FOR input, after any modifications, is the CCU's FOR d By inserting a delay, the CCU can determine whether a spike at the FOR input is d The “Other” input of each CCU can change the output stream of other CCUs (i.e., other CCUs connected to the same Soma). d It is intended to be the union of the spikes that appear in the output.

[0142] As can be seen, the Other input of each CCU is determined as follows: First, the output spikes of all CCUs are combined together by an OR gate 0120 to form a single combined spike stream. The output of this OR gate is labeled "ANY", because the FOR input of any CCU can be d This is because as long as a spike occurs at the output, a spike is expected to occur at the output of that OR gate.

[0143] Each CCU 0110, 0112, and 0114 comprises, respectively, an AND gate 0111, 0113, and 0115. As can be seen, each AND gate filters (i.e., removes) the spike stream received by the Other input of that CCU. In particular, spikes contributed by that AND gate's CCU are removed.

[0144] 9.2 Cross-correlation unit 9.2.1 General Considerations In contrast to conventional correlation and cross-correlation techniques, the MCC of the present invention relies on the presence of a large number (eg, hundreds or thousands) of random spikes.

[0145] MCC works by having each CCU operate essentially independently of the other CCUs. An exception to independent operation is that each CCU may not receive the FOR inputs of other CCUs (e.g., rather than a union of spike streams as presented to the FOR inputs of the other CCUs). d This means that you receive the union of the outputs (in the Other input).

[0146] FIG. 2 is a functional block diagram of an exemplary internal structure for each CCU of FIG.

[0147] As can be seen, the CCU consists of two main units: A delay generator (block 0225), and ● Delay learning unit (block 0226).

[0148] The delay generator accepts an input spike stream (at its FOR input) and outputs d The FOR input of the delay generator is coupled to the FOR input of the CCU (labeled 0211), and the FOR d The output is the FOR d is coupled to the output.

[0149] The delay learning unit receives the CCU's Other spike stream (from the CCU's Other input 0210) and the delay generation unit FOR d Output (FOR delay learning part d The delay learning part accepts FOR d Each pair of spikes present in the inputs is used as a frame of reference for analyzing spikes occurring at the Other input of the delayed learner.

[0150] If the delay generator has sufficient memory, it will generate a spike stream that is identical to the spike stream at the FOR input, except for the possible delay. d At the output, we can regenerate the delay, which can be called a lossless version of the delay generator.

[0151] Depending on the application, the delay generator memory can be implemented using analog or digital devices. In a digital implementation, the delay generator may include a FIFO (first-in, first-out) queue or buffer, for example, implemented using semiconductor random access memory (RAM). In an analog implementation, the delay generator may include any suitable signal or waveguide, such as an electrical cable or a free space wave propagation cavity.

[0152] In general, however, a lossless version of the delay generator may require an infinite (or unlimited) amount of memory.

[0153] Another important aspect of the present invention is to exploit the stochastic nature of the spike stream presented to the CCU's FOR input to generate a lossy version of the FOR at the output of the delay generator. d In fact, the delay generator's memory for only one spike (at a time) is d Sometimes this is enough to generate a useful correlated stream of spikes at the output. With storage for only one spike, the delay generator can be thought of as a kind of "timer". When a spike appears at the FOR input, the timer can be started. At the end of the delay period, the timer is d Generates spikes for output. The use of a single spike memory is discussed below in Section 9.2.3 ("Delay Generation").

[0154] 9.2.2 Lazy learning section 9.2.2.1 Functional Description As mentioned above, the delay learning part isd Each pair of spikes present in the inputs is used as a frame of reference for analyzing spikes occurring at the Other input of the delay learner. Figure 3 shows an exemplary situation of this kind.

[0155] As can be seen, Figure 3 contains two axes: ● The horizontal time axis, where 0.00 s ≤ t ≤ 0.60 s. • A vertical axis (described further below) used to assign a weight to each Other spike, where 0.00≦weight≦1.00.

[0156] Other spikes serve as a framework for evaluating the delay learning part d Let successive pairs of spikes in the input be called n and n+1. The vertical line at time t=0.00 (in addition to representing the weight axis) indicates spike n (this spike is also labeled 0310). Conversely, spike n+1 is shown at t=0.60 (this spike is also labeled 0311). The magnitudes of the n and n+1 spikes along the vertical axis are not relevant and have been chosen merely for purposes of graphical presentation.

[0157] The weight axis is associated with curves 0320 and 0321. As can be seen, 0320 is -rt where r is the rate, t is time, and r is equal to 3 (for example purposes). Conversely, 0321 is an exponential decay curve of the form -r(m-t) where r and t are the same as 0320 and m (the "max" time) is equal to 0.60 seconds. For reasons explained below, curves 0320 and 0321 are also referred to as "Post" and "Pre", respectively.

[0158] FOR dEach Other spike occurring between spikes n and n+1 is assigned both a Post and a Pre value. If the Post value is greater than the Pre value, the Other spike is characterized more as being "post" (or later) spike n than as being "pre" (or earlier) spike n+1. Conversely, if the Pre value is greater than the Post value, the spike is characterized more as being "pre" (or earlier) spike n+1 than as being "post" (or later) spike n.

[0159] FIG. 3 shows two exemplary Other spikes with the following values: ●Other spike 1: ○t=0.065 seconds ○Post value = 0.723 ○Pre value = 0.05 ●Other spikes 2: ○t=0.44 seconds ○Post value = 0.112 ○Pre value = 0.446

[0160] As can be seen, each Other spike is given two weights depending on where it intersects with the Post and Pre weighting curves.

[0161] A pair of FOR d Across multiple Other spikes that may occur between spikes n and n+1, the final tendency towards being "post" or "pre" can be determined and corrected as follows: Accumulate the sum of all Post values ​​(also called "postAcc"), and Accumulate the sum of all Pre values ​​(also called "preAcc"). ●If postAcc>preAcc: ○Other spike streams, after all, FOR d This is considered to have occurred after the spike in d It also means the stream is faster. o A Delay Learner (eg, Delay Learner block 0226 in FIG. 2) can try to correct this early by issuing a command (such as a pulse) at the "more d" output. In response to the "more d" command, the delay generator (see, for example, delay generator block 0225) d The delay between the input and the output can be increased by fixed incremental amounts. ●If preAcc>postAcc: ○Other spike streams, after all, FOR d This is, after all, the FOR d It also means the stream is slow. The delay learner can try to compensate for this slowness by issuing a command (such as a pulse) at the "less d" output. In response, the delay generator receives the FOR input and d The delay between the input and the output can be reduced by fixed incremental amounts.

[0162] The increment by which the delay of the Delay Learner changes (in response to a "more d" or "less d" command) may be selected based on the particular application and its speed vs. accuracy requirements. In general, the smaller the increment (also called a slower learning rate), the more time it takes for the CCU to find the delay value that provides the best synchronization with the Event and Other streams. However, smaller increments have the advantage that they lead to a more accurate determination of the required delay value.

[0163] Although both decreasing and increasing exponential curves have been shown, a variety of functions may be suitable for the purposes of Post and Pre weighting. The main criteria for a suitable function are: ●Pre function is the symmetric and opposite of Post function. • Post and Pre functions that reach their maximum values ​​at spikes n and n+1, respectively. ●Post and Pre functions that decrease monotonically from a maximum value.

[0164] 9.2.2.2 Sequential Operation and Pseudocode Implementation The discussion in the previous sub-chapter has described the operation of the delay learner in a manner that is adapted to the following spikes being simultaneously available: ●FOR d Input spikes n and n+1, and ●nF.OR d Spike and n+1F.OR d Any spikes present at the Other input of the delay learning unit during the time interval between spikes.

[0165] In actual operation, the CCU (and the MCC of which it is a part) is expected to operate on a spike-by-spike basis. For example, each spike, which we can call spike n, is a FOR d When present in the input, we can expect the lazy learner to perform two main actions: If there is n-1 spike, try to complete the cross-correlation analysis that started with spike n-1. In other words, complete the cross-correlation analysis with spikes n-1 and n as the reference frames. When spike n+1 arrives, it starts a new cross-correlation analysis that will be completed in the future. In other words, it starts a new cross-correlation analysis, where spikes n and n+1 serve as reference frames.

[0166] Depending on the particular application, it may be desirable to implement the delay learner as a computer program, or as electrical hardware, or as a hybrid combination of the two approaches.

[0167] Figure 4 shows an exemplary pseudocode implementation of a lazy learner based on the Python programming language. Boldface text corresponds closely to Python syntax and symbolic semantics. Comments have been inserted according to Python syntax. Line numbers have been added to the left to aid in explanation. The main departure from Python syntax and symbolic semantics is in lines 5-17, to the right of the assignment operator. Also, passing of parameters or other data to and from procedures is treated informally.

[0168] The procedure in Figure 4 is called “Learn_Delay_PC”, where the suffix “PC” indicates pseudocode. Line 1.

[0169] Learn_Delay_PC is FOR d It is called whenever a spike occurs in either the Input or Other input.

[0170] Several important values ​​and variables are assigned across lines 5-17, but these will be covered as part of examining the pseudocode that makes use of these variables across lines 22-44.

[0171] Line 22 updates the Pre accumulator "preAcc" by exponentially decaying the contents of the Pre accumulator based on the amount of time (i.e., T-TLO) since the last Other spike called Learn_Delay_PC (where T and TLO are defined in lines 8-9 of FIG. 4). As explained further below, this exponential decay of preAcc is combined with adding a unit value to preAcc every time an Other spike occurs.

[0172] Add a unit value to preAcc at the time of each Other spike, and set preAcc to (FOR d The exponential decay (until the time of the Other spike) is mathematically equivalent to the preAcc accumulation method described above with respect to FIG. 3. That is, as each Other spike occurs, preAcc is increased by a value e-r(m-t) where m is the maximum value of t, and having a non-decaying preAcc.

[0173] Decaying preAcc exponentially may seem like an unnecessarily indirect way to accumulate Pre values. However, as we will see in the next subchapter, e -r(m-t) e -rt is a relatively complex function to implement in electronic hardware.

[0174] Following an update to preAcc, the current spike is of type FOR d A test is performed as to whether the condition is FOR or Other. Line 25. d A spike is considered to "belong" to the currently executing delay learner unit, because its origin is from a delay generator unit that belongs to the same CCU. Thus, if the IS_MINE variable is false, it indicates that an Other spike has been received, and lines 26-33 are executed. Otherwise, the current spike is of type FOR d and lines 35 to 45 are executed.

[0175] Assuming IS_MINE is false, the following steps are performed: - A unit value is added to preAcc to take into account that the current spike is of type Other. Line 26. The value added to postAcc is the last FOR d A simple exponential decay of unity after the spike. Line 30. ● The time of the last Other spike is updated in preparation for the next call to Learn_Delay_PC. Line 32.

[0176] Assuming IS_MINE is true, the following steps are performed: ● Previous FOR dAs part of completing an ongoing cross-correlation analysis that was started by a spike, a test is first performed to determine whether an Other spike has occurred. Line 35. ●Assuming that at least one Other spike has occurred, the preAcc value is compared with the postAcc value. Line 38. ○If preAcc>postAcc, then FOR d The spike is considered slow compared to the Other spikes. The delay from the delay generator, represented by the variable D, is reduced. The amount of reduction, which controls the learning rate, is represented by "-D_LR" on line 38. ○If postAcc>preAcc, then FOR d The spike is considered early compared to the Other spikes. The delay from the delay generator, represented by variable D, is increased. The amount of increase, which controls the learning rate, is represented by "D_LR" on line 38. • Checks can be carried out to ensure that D remains within acceptable limits. Line 40. As part of initiating a new cross-correlation analysis, the following steps will be performed: ○preAcc and postAcc are reset to zero. Line 42. ○The last FOR d The spike time is updated to the current time. Line 44.

[0177] 9.2.2.3 Electrical implementation 5-7 show exemplary electrical implementations of the delay learner.

[0178] Figure 5 shows the top level control and interface of the Delay Learner module, Figure 6 focuses on the circuitry associated with storing the postAcc value, and Figure 7 focuses on the circuitry associated with storing the preAcc value.

[0179] Contour line 0510 in FIG. 5 indicates the external interface of the delay learner, with each connection corresponding to an input or output of the delay learner function block 0221, as described above in relation to FIG.

[0180] Contour 0520 indicates the delay learn unit's internal interface to the postAcc circuit of FIG. 6 and the preAcc circuit of FIG.

[0181] Continuing with the consideration of the external interface 0510.

[0182] FOR d Each spike presented to the input triggers a "two shot" 0530. First, the out1 of the two shot completes the current reference frame by reading the comparison amplifier 0540. Second, out2 resets the postAcc and preAcc circuits so that accumulation over the next reference frame can begin.

[0183] out1 reads comparator 0540 by enabling AND gates 0541 and 0542. When the output of comparator 0540 is a logical 0, these AND gates are enabled, causing AND gate 0542 to present a trigger signal to one shot 0532, which when triggered generates a pulse at its "less d" output (of interface 0510). Conversely, when the output of comparator 0540 is a logical 1, AND gate 0541 presents a trigger signal to one shot 0531, which when triggered generates a pulse at its "more d" output (of interface 0510).

[0184] The comparator 0540 compares two signals: a signal representing preAcc (called "preAcc") and a signal representing postAcc (called "postAcc"). The postAcc signal is generated by the circuit of FIG. 6, while the preAcc signal is accumulated by the circuit of FIG. 7. The preAcc and postAcc signals are each analog, with voltage levels representing accumulated values. If the voltage of the preAcc signal is higher than the postAcc, the comparator 0540 outputs a signal representing a logical 0. As mentioned above, a logical 0 (as read by out1 of the two shot 0530) causes a pulse from the "less d" output. Conversely, if postAcc>preAcc, the comparator 0540 outputs a logical 1. As mentioned above, a logical 1 (as read by out1 of the two shot 0530) causes a pulse from the "more d" output.

[0185] The final connection to consider for the external interface 0510 is the Other input. d As with the input, a spike on Other also triggers a two shot, which in this case is two shot 0533. As explained further below, out1 of two shot 0533 causes (among other actions) a sampling of the current voltage levels of each of the postAcc and preAcc accumulators. Secondly, out2 causes each of the postAcc and preAcc accumulators to charge to a new voltage level.

[0186] With reference to Figure 6, capacitor 0650 maintains the voltage of the postAcc signal (or node). As described above with reference to Figure 3, with respect to the Post n function 0320, it is determined by the combination of capacitor 0640 and resistor 0641. The Post n function is available in Figure 6 at the attenuation variable node.

[0187] As mentioned above, as part of initiating a new reference frame, two shot0530 asserts (at its out2 output) a "reset (FOR)" signal. With reference to Figure 6, it can be seen that the reset (FOR) signal causes the resetting of the following capacitors: - Switch 0660 couples the postAcc node to ground, resetting the accumulated postAcc value to zero. The Post n function 0320 is reset to a new period of exponential decay by switches S1 and S2 of the switching unit 0643. Specifically, for the duration of the reset (FOR) pulse: ○ S1 couples the capacitor 0640 to a unit value voltage source 0642, and ○S2 ensures that the decay variable node maintains the correct initial value to restart the exponential decay while the capacitor 0640 is being recharged. At the appropriate time, capacitor 0632 is used to hold a sample of the voltage at the attenuation variable node. Capacitor 0632 is reset by switch 0662 coupling capacitor 0632 to ground. At the appropriate time, capacitor 0622 is used to hold a sample of the voltage at the postAcc node. Capacitor 0622 is reset by switch 0661 coupling capacitor 0622 to ground.

[0188] Once the reset (FOR) signal is terminated, the combination of capacitor 0640 and resistor 0641 begins the exponential decay and the Post n function becomes available at the Decay variable node.

[0189] If other spikes occur, (FOR d Following the reset of the postAcc node (due to the spike), two shot0533 is triggered. With reference to Figure 6, it can be seen that the assertion of the "Other" signal causes the following: • Sampling of the current voltage at the damping variable node by closing switch 0631. • Sampling the current voltage at the postAcc node by closing switch 0621.

[0190] Following assertion of the "Other" signal, the following occurs: ● Switch 0631 is opened and the sampled voltage of the attenuation variable node is held by capacitor 0632. ● Switch 0621 opens and the sampled voltage at the postAcc node is held by capacitor 0622. • The voltages held by capacitors 0632 and 0622 are summed by summing amplifier 0610.

[0191] Two shot 0533 then asserts the "Charge Acc(Other)" signal, which closes switch 0611 in FIG. 6. This causes comparator 0612 to compare the voltage at the postAcc node with the output of summing amplifier 0611. The voltage from the summing amplifier will be greater than the voltage at the postAcc node by the amount sampled at the attenuation variable node. Comparator 0612 therefore causes switch 0613 to close and remain closed until the postAcc node is charged to a voltage substantially equal to the output of the summing amplifier.

[0192] As can be seen, the net effect of the sequential assertion of the "Sample(Other)" and "Charge(Other)" signals is as follows: At the time of each Other spike, the voltage on the postAcc node increases by an amount equal to the then-current voltage on the Attenuation Variable Node.

[0193] With reference to Figure 7, capacitor 0720 maintains the voltage of the preAcc signal (or node). However, as described above with respect to the Learn_Delay_PC pseudocode of Figure 4, the preAcc node is designed to decay due to combination with resistor 0721. As described above, the combination of a decaying preAcc node and the addition of a unit voltage for each Other spike is mathematically equivalent to determining the Pre n+1 function 0321 (of Figure 3) and adding that value to the undampened Pre accumulator. The relative simplicity of the decaying preAcc node approach from a circuit implementation standpoint can be seen in Figure 7.

[0194] As mentioned above, as part of initiating a new reference frame, two shot0530 asserts (at its out2 output) a "reset (FOR)" signal. With reference to Figure 7, it can be seen that the reset (FOR) signal causes the resetting of the following capacitors: - Switch 0741 couples the preAcc node to ground, resetting the accumulated preAcc value to zero. At the appropriate time, capacitor 0732 is used to hold a sample of the voltage at the postAcc node. Capacitor 0732 is reset by switch 0740 coupling capacitor 0732 to ground.

[0195] If other spikes occur, (FOR d Following the reset of the preAcc node (due to the spike), two shot 0533 is triggered. With reference to Figure 7, it can be seen that asserting the "Sample (Other)" signal causes a sampling of the current voltage at the preAcc node by closing switch 0731.

[0196] Following assertion of the "Other" signal, the following occurs: ● Switch 0731 opens and the sampled voltage at the preAcc node is held by capacitor 0732. • The voltage held by capacitor 0732 is summed with a unit voltage from voltage source 0714 by summing amplifier 0710 .

[0197] Two shot 0533 then asserts the "Charge Acc(Other)" signal, which closes switch 0711 in FIG. 7. This causes comparator 0712 to compare the voltage at the preAcc node with the output of summing amplifier 0710. The voltage from the summing amplifier is greater than the voltage at the preAcc node by an amount provided by unit voltage source 0714. Comparator 0712 therefore causes switch 0713 to close and remain closed until the preAcc node is charged to a voltage substantially equal to the output of the summing amplifier.

[0198] As can be seen, the net effect of the sequential assertion of the "Sample" and "Charge" signals is as follows: At the time of each Other spike, the voltage at the preAcc node increases by an amount equal to the unit voltage of the voltage source 0714. Following this increase, the preAcc node resumes its exponential decay until one of the following occurs: ●FOR d Upon occurrence of the spike, the current reference frame ends. ●Another Other spike occurs.

[0199] 9.2.3 Delay Generation - Lossy Version 9.2.3.1 Conflict Resolution As mentioned above, in section 9.2.1 ("General Considerations"), another important aspect of the present invention is the inclusion of a lossy version of the delay generator at the output of the delay generator. d It is an option to exploit the stochastic nature of the spike streams presented to the FOR input of each CCU to generate

[0200] The memory of only one spike (at a time) by the delay generator (e.g., by function block 0225 of FIG. 2) is stored in the CCU FOR dSometimes this is enough to produce a useful, correlated stream of spikes at the output. In this case, the delay generator can be thought of as a kind of "timer". When a spike appears at the delay generator's FOR input, a timer can be started. At the end of the delay period, the timer d Generates spikes for output. Use of a single spike memory is explained below.

[0201] We call the lossy version "memoryless" because its delay generator requires much less memory (only one spike) than the lossless version, whose memory would potentially need to be infinite.

[0202] A key issue in implementing a memoryless scheme is what is called the "contention resolution" problem. The contention resolution problem can arise whenever the delay generator has a delay greater than 0 seconds. Due to the stochastic nature of the spike stream input to each CCU, whenever the delay generator is in the middle of timing a delay period d due to a FOR spike x, there is always a chance that the next FOR spike x+1 will arrive. There are then two options: Ignore spike x+1 and continue timing spike x until the delay period d is complete. This is called the "keep the oldest" option. Restart the timer so that the delay period d begins on spike x+1. We call this the “keep the most recent” option.

[0203] If either of these two policies is applied consistently, then they may be applied an infinite number of times in succession. For example: Keep the oldest: While a delay d is being timed for a spike x, an infinite number of subsequent FOR d Spikes may arrive, they are all ignored. ● Keep it most recent: If spike x+1 restarts the delay d of spike x, then spike x+2 can restart the period of spike x+1, and spike x+3 can restart the period of spike x+2. Restarts of delay periods can continue to occur a potentially infinite number of times.

[0204] If either of these two options is exclusively applied as a conflict resolution policy, FOR d The problem is that the comparison of the spike streams with other spike streams introduces a time bias. Specifically: ● Keep the oldest: FOR d This has the effect of making the spike stream appear earlier than it actually is relative to the other spike streams, so that the delay generated by the delay generator becomes too large. This effect can be seen from the fact that the keep-the-oldest policy causes later spikes (i.e. spikes after spike x) to be discarded. ●Keep the newest: FOR d This has the effect of making the spike stream appear later than it actually is relative to the other spike streams, so that the delays generated by the delay generator are too small. This effect can be seen from the fact that the keep-latest policy causes earlier spikes (e.g. spike x earlier than spike x+1) to be ignored.

[0205] The time bias problem can be solved by any technique that selects the keep-oldest and keep-youngest policies on average equally many times. The main difference between FIG. 8 and FIG. 2 is the introduction of a conflict resolution block 0224, inside which the proposed implementation can be seen. Function block 0220 (Delay Generator) of FIG. 8 contains an additional "Delay Done" output that is not present in function block 225 of FIG. 2. Delay Done is a logical 0 when the Delay Generator is timing the delay period, and a logical 1 otherwise. Whenever Delay Done is a logical 1, AND gate 0230 allows a spike at the FOR input 0211 to start the delay operation. This makes sense since under such conditions there is no conflict with the existing delay period.

[0206] Conversely, if a FOR spike arrives at input 0211 and the delayed completion is a logical 0, then a race condition is known to exist. This condition is resolved by AND 0233 in the race resolution block 0224. The AND gate 0233, which produces a logical 1, will cause one of two actions to occur, depending on the existing state of flip-flop 0234: If flip-flop 0234 happens to already be generating a logical 1 at its Q output, then that Q output, in concert with the logical 1 from AND 0233, will cause AND 0232 (via OR gate 0231) to generate a signal that causes the delay generator to restart timing. As can be seen, this is an implementation of the "keep the newest" policy. Conversely, if flip-flop 0234 happens to generate a logical 0 at its Q output, that logical 0 will prevent AND 0232 from generating a signal that would cause the delay generator to restart timing. This is an implementation of the "keep the oldest" policy.

[0207] Every time a logical 1 is produced by AND 0233, flip-flop 0234 is triggered to change state, regardless of whether flip-flop 0234 happens to already be producing a logical 1. The end result is that every time a conflict situation is detected, conflict resolution block 0224 implements a policy based on the current state of flip-flop 0234, and then changes the state of flip-flop 0234 so that the opposite policy will be executed next time.

[0208] 9.2.3.2 Electrical implementation 9-10 deal with an exemplary electrical implementation of the delay generation unit.

[0209] Figure 9 shows the exponential decay curve (i.e., 0910 is e -rt 9 shows an example of an implementation of the delay generator by combining the delay detection (horizontal line 0911) with threshold detection (horizontal line 0912). In the example of FIG. 9, the rate of decay r is equal to 3 and the threshold to be detected (th d The threshold (called "d") is equal to 0.1. As can be seen, under these conditions, the delay period (called "d") produced is 0.77 seconds. As will be appreciated, the delay can be increased or decreased by lowering or increasing the threshold, respectively.

[0210] FIG. 10 shows a circuit for implementing the function of the delay generator shown in FIG. 8 for the functional block 0220.

[0211] Contour line 1010 in FIG. 10 indicates the external interface of the delay generator, with each connection corresponding to an input or output of the delay generator functional block 0220 .

[0212] The exponential decay that forms the basis of the delay generator's timing function is generated by the combination of a capacitor 1040 and a resistor 1041. The delay occurs at the "decay" node, which is applied to the negative input of the comparison amplifier 1030. dThe voltage output by 1031 (called "more d") is set by an adjustable voltage source 1031, which is applied to the positive input of the comparator. The voltage output by 1031 can be adjusted in steps lower or higher by pulses applied to the "more d" or "less d" inputs, respectively, to interface 1010. At any one time, the state of voltage source 1031 (i.e. the voltage it is currently set to output) may be held by a capacitor (not shown).

[0213] Each spike at the start / restart input triggers one shot 1020. One shot 1020 generates a pulse which, while asserted, primes capacitor 1040 to generate a new period of exponential decay via switches S1 and S2 of switching unit 1043. Specifically, for the duration of the one shot pulse: S1 couples the capacitor 1040 to a unit value voltage source 1042; and - S2 ensures that the decay node maintains the correct initial value to restart the exponential decay while the capacitor 1040 is being recharged.

[0214] Once the one shot 1020 signal ends, the combination of capacitor 1040 and resistor 1041 begins the exponential decay. When the voltage at the decay node becomes lower than the voltage output by voltage source 1031, the output of comparator 1030 produces a logical 1. A logical 1 causes both of the following: ● The "Delayed Done" output on interface 1010 is asserted. ●One shot 1021 is triggered and the pulse is sent to the FOR d Configure the spike output at the output.

[0215] 9.2.4 Rate All Learning Section As mentioned above, both the Delay Generator and Delay Learner functional blocks (e.g., blocks 0220 and 0226 in FIG. 8) function through the use of exponential decay curves. The decay rate r of those functions can be selected based on the expected spike frequency of a particular application.

[0216] However, the mean spike rate (r ALL It may be useful to include a function block within the CCU that can discover the ALL is a suitable value to use as r for the decay functions of the delay generator and delay learner.

[0217] For example, for the delay generator shown in FIG. ALL can be used for the Post and Pre functions. Using this value for r tends to ensure that the Other spikes are located in regions where the functions are changing relatively quickly, and therefore easier to measure. The delay rate at which the delay generator measures the delay (see, for example, function 0910 in FIG. 9) can be set to r ALL Similar advantages are realized by using

[0218] Figure 11 shows the same CCU as Figure 8, with the following differences: ● A “Rate All Learning Unit” (or LRA) function block 0223 has been added. As can be seen, the LRA 0223 accepts the FOR spikes as input and ALL Output. ●r ALL The inputs are added to the delay generator and delay learner, respectively (hence the label numbers have been changed from 0220 and 0226 in FIG. 8 to 0227 and 0228 in FIG. 11). ALL The input is LRA0223 r ALL Driven by the output.

[0219] The Rate All learning unit is based on the following properties of a stochastic spike stream s:ALL If the values ​​for are correct, then the following formula gives the probability of the next spike occurring at time t or any time thereafter:

number

[0220] This also means that if an exponential decay is generated according to Equation 1, the time when P=0.5 is the median expected (or MEA) time of arrival of the next spike in stream s. ALL Also called the , it has the following special properties: Special characteristics 1: s Multiple spikes occur across the MEA ALL The number of spikes occurring before the MEA ALL can be predicted to be equal to the number of spikes that occur after

[0221] In the case of Figure 12, the actual MEA ALL is r ALL For , it is assumed to be 0.23 seconds. As can be seen (for the sake of clarity of illustration), spikes a-d are ALL are chosen to be evenly distributed on both sides of the

[0222] Special Feature 1 has the following meaning: ●MEA ALL Estimated value of (MEA guess (called MEA) is too high (i.e., in practice, guess >MEA ALL ), over the many spikes that occur in s, guess MEA than after guess An extreme example of this is shown in Figure 13, where the MEA guess The time is 0.345 seconds (when r = 2), and spikes a to d (labeled a' to d' with respect to their locations when r = 2) are all located within the MEA guess It will be before. ●MEA ALL Estimated value of (MEAguess (called MEA) is too low (i.e., in practice, guess <MEA ALL ), over the many spikes that occur in s, guess MEA than before guess After this, more spikes will occur. An extreme example of this is shown in Figure 14, where the MEA guess is 0.115 s (for r = 6), and the same spikes a-d (labeled a''-d'' here for r = 6) are all MEA guess It comes after.

[0223] Special Feature 1, together with its meaning, is the MEA ALL This provides the basis for a search procedure capable of discovering the 1.MEA guess Choose a reasonable initial value for: ○MEA guess The selection of the initial value of MEA may be limited, for example, to be within a range of possible values ​​based on the particular system design and intended application. guess The value of MEA guess We can determine the initial value of r by guessing the value of r guess It can also be determined by the MEA. guess The corresponding time for P = 0.5 and r = r can be determined from Equation 1. guess , then Equation 1 becomes:

number

[0224] In the search procedure outlined above, MEA guess For each of the above assumptions about whether is too high or too low, the following possibilities exist: ●MEA guess If is actually too high, across many spikes, this will guess is determined by the occurrence of more comparisons indicating that the MEA is too high rather than too low. guess The value of (r guess ) and ultimately decreases. ●MEA guess If is actually too low, across many spikes, this will guess is determined by the occurrence of more comparisons indicating that the MEA is too low rather than too high. guess The value of (r guess ) and ultimately increases. ●MEA guess is factually correct (i.e., MEA guess =MEA ALLand r guess =r ALL Ultimate dynamic stability is achieved only if

[0225] Therefore, over a sufficient number of spikes, r ALL is r ALL The convergence rate (also called the "learning rate") to the determined r ALL Select Δr to provide an appropriate tradeoff between the accuracy of the value and is determined as: • Larger values ​​of Δr increase the learning rate but reduce the accuracy of the results. A smaller value of Δr will reduce the learning rate but will produce more accurate results.

[0226] 15 shows an alternative way to find the MEA other than solving for the point where Equation 1 yields half of its full range (e.g., P=0.5). This alternative approach is to solve for the time at which Equation 1 and Equation 3 below are equal (Equation 3 defines a cumulative probability distribution).

number

[0227] As can be seen from FIG. 15, each of the MEAs previously described with respect to FIGS. 12-14 can be found by searching for points of equal value.

[0228] This equality testing scheme is the basis for the hardware implementation of FIG. 16 and can be explained as follows.

[0229] Contour line 1610 in FIG. 16 indicates the external interface of the LRA, with each connection corresponding to an input or output of the LRA function block 0223 in FIG.

[0230] The exponential decay of Equation 1 is implemented in Figure 16 by the combination of capacitor 1630 and variable resistor 1631. The decay value is available at "decay" node 1641. Equation 3 (exponential increase) is implemented by subtracting amplifier 1621 as follows: • A unit voltage is applied to the ‘A’ input of the amplifier. • Attenuation node 1641 (i.e., Equation 1) is applied to the 'B' input. Therefore, the output of the subtraction amplifier 1621, available at node 1640, is the voltage level representation of Equation 3.

[0231] The equality test between Equation 1 and Equation 3 is performed by a comparison amplifier 1622, and the result (MEA in the above description) guess ) is available at node 1642.

[0232] Each time there is a spike n, two shot 1620 is triggered at the FOR input of interface 1610. The first step, initiated by out1 of two shot, is to complete the MEA measurement that began with the last FOR spike n-1. out1 accomplishes this by enabling AND gates 1623 and 1624 to read the output of comparator 1622.

[0233] The output of comparator 1622 can be interpreted as follows: The comparator 1622 compares the period between spikes n-1 and n to determine whether the period is longer than the current MEA. guess , it outputs a logical 1 if it indicates that exponential decay node 1641 is less than The comparator 1622 compares the period between spikes n-1 and n to determine whether the period is longer than the current MEA. guess If exponential increase node 1640 drives the - input of the comparator, it outputs a logical 0 if exponential increase node 1640 indicates that exponential increase is greater than -.

[0234] The current measurement by comparator 1622 isguess If the voltage at node 1642 indicates that the voltage is too high, then a logical 1 at node 1642 enables AND gate 1623 and an out1 pulse is applied to the R-input of variable resistor 1631. As will be appreciated, reducing the resistance will speed up the rate of decay at "decay" node 1641, decreasing the MEA guess is adjusted downwards.

[0235] Conversely, the current measurement by comparator 1622 is guess If the voltage at node 1642 indicates that the output voltage is too low, a logical 0 at node 1642 enables AND gate 1624 and an out1 pulse is applied to the R+ input of variable resistor 1631. As will be appreciated, increasing the resistance will slow the rate of decay at "decay" node 1641, increasing the MEA guess is adjusted upwards.

[0236] Factors such as the duration of the out1 pulse and the particular configuration of variable resistor 1631 determine r guess The magnitude of each such increment of change is referred to above as the "learning rate," Δr.

[0237] The state of the variable resistor 1631 (i.e., the current resistance level) may be held by an internal state capacitor (not shown). The voltage on this capacitor may, for example, increase with each pulse to the R- input and decrease with each pulse to the R+ input. Furthermore, the voltage on the internal state capacitor may be made available via a voltage tracking amplifier (also not shown), which is connected to the r ALL Drive the output.

[0238] As described above with reference to FIG. 11, the LRA 0223 calculates the delay time of each of the delay generation unit 0227 and the delay learning unit 0228. ALL Enter LRA0223 r ALL An output can be provided.

[0239] r ALLA portion of the circuit implementation of the delay learner 0226, modified by adding an input, is shown in Figures 6 and 7. For the circuit implementation of the delay learner 0228, Figures 6 and 7 are replaced by Figures 17 and 18, respectively. Figures 17 and 18 differ from Figures 6 and 7 as follows: The fixed resistor 0641 (Figure 6) is r ALL It has been replaced with a variable resistor 0644 (FIG. 17) which accepts an input 0601. The fixed resistor 0721 (Figure 7) is r ALL The input 0701 is replaced by a variable resistor 0722 (FIG. 18) which accepts the input 0701.

[0240] For the circuit implementation of the delay generator 0227, FIG. 10 is replaced by FIG. 19. FIG. 19 differs from FIG. 10 in the following ways: the fixed resistor 1041 (FIG. 10) is replaced by r ALL It is replaced with a variable resistor 1044 (FIG. 19) that accepts an input.

[0241] LRA's r ALL The voltage at the output is found by the LRA0223 ALL To generate an exponential decay curve (for the delay generator 0227 and the delay learner 0228) with r equal to ●Capacitors 0640 (see the postAcc implementation in Figure 17), 0720 (see the preAcc implementation in Figure 18), and 1040 (see the delay generation unit implementation in Figure 19) can be made to have the same capacitance as LRA capacitor 1630 (see Figure 16). Variable resistors 0644 (see the implementation of postAcc in FIG. 17), 0722 (see the implementation of preAcc in FIG. 18), and 1044 (see the implementation of the delay generator in FIG. 19) can be the same as LRA's variable resistor 1631 (see FIG. 16), except that instead of maintaining an internal state, each of 0644, 0722, and 1044 is connected to an external interface r ALL A voltage follower is used, driven by the input.

[0242] 9.3 Overview A multi-stream cross-correlator for spiking neural networks is provided, where each stream contains significant stochastic content. At least one event occurs that has a constant temporal relationship across at least two streams. Each stream is treated as a reference frame (FOR) and is given an adjustable delay based on a comparison with the Other stream. For each spike in the FOR, a timing analysis is completed for the last and current FOR spike by comparing the Post and Pre accumulators. A new timing analysis is also started with the current FOR spike by restarting the generation of the Post and Pre weighting functions, and the values ​​of these functions are accumulated every time an Other spike occurs until the next FOR spike. If a time-neutral conflict resolution is used, a unit that delays one spike can be used. The average spike rate of the FOR is determined and can be used for the Post and Pre weighting functions.

[0243] While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, and variations will become apparent in light of the foregoing description. Accordingly, the present invention is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and scope of the appended claims and equivalents thereof.

Claims

1. 1. A method for identifying pairs of spikes that share an underlying event, comprising: receiving a first spike stream having significant stochastic content except for a first subset of spikes, each spike of the first subset sharing underlying events with spikes of a second subset of spikes of a second spike stream, the first spike stream comprising significant stochastic content except for a first subset of spikes of the first spike stream, the first subset sharing underlying events with spikes of a second subset of spikes of the second spike stream; receiving the second spike stream, the second spike stream including significant stochastic content except for the second subset, the second spike stream being at least partially performed using an electronic hardware configuration; identifying a first inter-stream spike pair, the first spike from the first spike stream and a second spike from the second spike stream, performed at least in part using an electronic hardware configuration; initiating a first exponential decay unit with a first decaying output upon receipt of said first spike, said first exponential decay unit being at least partially effected using an arrangement of electronic hardware; deactivating the first exponential decay unit upon receipt of the second spike, performed at least in part using an electronic hardware configuration; outputting a first signal, performed at least in part using an electronic hardware configuration, indicating the first spike and the second spike as both caused by a shared underlying event if the first decay output is not less than a first threshold at the time of the stopping of the first exponential decay unit; setting a second threshold as a first fraction of the first threshold, performed at least in part using electronic hardware configuration; if, at the time of the stopping of the first exponential decay unit, the first decay output is less than the first threshold and not less than the second threshold, increasing a first decay rate of the first exponential decay unit and decreasing the first threshold, performed at least in part using an electronic hardware configuration; and if, at the time of the stopping of the first exponential decay unit, the first decay output is less than the first threshold and less than the second threshold, decreasing a first decay rate of the first exponential decay unit and increasing the first threshold, performed at least in part using an electronic hardware configuration.

2. 1. A method for identifying pairs of spikes that share an underlying event, comprising: receiving a first spike stream having significant stochastic content except for a first subset of spikes, each spike of the first subset sharing underlying events with spikes of a second subset of spikes of a second spike stream, the first spike stream comprising significant stochastic content except for a first subset of spikes of the first spike stream, the first subset sharing underlying events with spikes of a second subset of spikes of the second spike stream; receiving the second spike stream, the second spike stream including significant stochastic content except for the second subset, the second spike stream being at least partially performed using an electronic hardware configuration; identifying a first inter-stream spike pair, the first spike from the first spike stream and a second spike from the second spike stream, performed at least in part using an electronic hardware configuration; initiating a first exponential decay unit with a first decaying output upon receipt of said first spike, said first exponential decay unit being at least partially effected using an arrangement of electronic hardware; comparing, upon receipt of the second spike, the first attenuated output to a decision threshold, a first threshold for a first region, and a second threshold for the first region, performed at least in part using an electronic hardware configuration, the decision threshold being at least equal to the first threshold for the first region, and the first threshold for the first region being greater than the second threshold for the first region; if, at the time of said comparison, said first attenuated output is not less than said discrimination threshold, outputting a first signal, performed at least in part using an electronic hardware configuration, indicating said first spike and said second spike as both caused by a shared underlying event; increasing a first decay rate of the first exponential decay unit and decreasing the decision threshold, performed at least in part using an electronic hardware configuration, if the first decay output is less than the first threshold in the first region and not less than the second threshold in the first region at the time of the comparison; identifying a second inter-stream spike pair including a third spike from the first spike stream and a fourth spike from the second spike stream, performed at least in part using an electronic hardware configuration; initiating the first exponential decay unit with the first decaying output upon receipt of the third spike, performed at least in part using an electronic hardware configuration; comparing, at least in part, with an electronic hardware configuration, upon receipt of the fourth spike, the first attenuated output to a discrimination threshold, a first threshold for a second region, and a second threshold for the second region, wherein the second threshold for the first region is at least equal to the first threshold for the second region, and the first threshold for the second region is greater than the second threshold for the second region; if, at the time of said comparison, the first attenuated output is not less than the discrimination threshold, outputting a second signal, performed at least in part using an electronic hardware configuration, indicating the third spike and the fourth spike as both caused by a shared underlying event; and decreasing a first decay rate of the first exponential decay unit and increasing the decision threshold, performed at least in part using an electronic hardware configuration, if, at the time of the comparison, the first decay output is less than the first threshold in the second region and not less than the second threshold in the second region.

3. 3. The method of claim 2, wherein the first spike of the first inter-stream spike pair is the same as the third spike of the second inter-stream spike pair and the second spike of the first inter-stream spike pair is the same as the fourth spike of the second inter-stream spike pair.

4. 3. The method of claim 2, wherein the first spike and the second spike of the first inter-stream spike pair are different from the third spike and the fourth spike of the second inter-stream spike pair.

5. The method of claim 2 , wherein the second threshold of the first region is the same as the first threshold of the second region.

6. The method of claim 2 , wherein the decision threshold is the same as the first threshold of the first region.

7. The method of claim 6 , wherein the second threshold value for the second region is zero.

8. 8. The method of claim 7, wherein a first difference between the first threshold of the first region and the second threshold of the first region is approximately equal to a second difference between the first threshold of the second region and the second threshold of the second region.

9. The second threshold value of the first region is equal to the first threshold value of the second region. Item 9. The method according to item 8.

10. 3. The method of claim 2, wherein a first difference between the first threshold of the first region and the second threshold of the first region is approximately equal to a second difference between the first threshold of the second region and the second threshold of the second region.

11. The method of claim 10 , wherein the first difference and the second difference are each approximately the same and approximately constant fraction of the difference between a decision threshold and zero.

12. The method of claim 2 further comprising the step of correlating the first spike stream and the second spike stream.

13. receiving a first non-delayed spike stream containing significant stochastic content except for a first subset of non-delayed spikes, each spike in the first subset of non-delayed spikes sharing underlying events with spikes in a second subset of non-delayed spikes in a second non-delayed spike stream; inputting the first undelayed spike stream into a first delay unit to generate the first spike stream with a first delay, the first delay having a lower bound of zero seconds; inputting the second undelayed spike stream into a first delay unit to generate the second spike stream with a second delay, the second delay having a lower bound of zero seconds; upon receiving a first delayed spike from the first spike stream, comparing a first accumulated value with a second accumulated value to generate a first comparison result; increasing the first delay if the first comparison result indicates that the first accumulation value is greater than the second accumulation value; decreasing the first delay if the first comparison result indicates that the first accumulation value is less than the second accumulation value; resetting the first accumulation value and the second accumulation value after the first comparison result is generated; after the first comparison result is generated, restarting the first process for generating a first weighting function and a second weighting function, the first weighting function being monotonically decreasing and the second weighting function being monotonically increasing and symmetrically opposite to the first weighting function; accumulating a first weight value in a first accumulator according to the first weighting function upon receiving a spike with a second delay from the second spike stream; 13. The method of claim 12, further comprising: upon receiving a spike with the same second delay from the second spike stream, accumulating a second weight value in a second accumulator according to the second weighting function.

14. 1. A method for identifying pairs of spikes that share an underlying event, comprising: receiving a first spike stream having significant stochastic content except for a first subset of spikes, each spike of the first subset sharing underlying events with spikes of a second subset of spikes of a second spike stream, the first spike stream comprising significant stochastic content except for a first subset of spikes of the first spike stream, the first subset sharing underlying events with spikes of a second subset of spikes of the second spike stream; receiving the second spike stream, the second spike stream including significant stochastic content except for the second subset, the second spike stream being at least partially performed using an electronic hardware configuration; identifying a first inter-stream spike pair, the first spike from the first spike stream and a second spike from the second spike stream, performed at least in part using an electronic hardware configuration; initiating a first exponential decay unit with a first decaying output upon receipt of said first spike, said first exponential decay unit being at least partially effected using an arrangement of electronic hardware; comparing, at least in part, using an electronic hardware configuration, upon receipt of the second spike, the first attenuated output to a decision threshold, a first threshold of a first constant increment region, and a second threshold of the first constant increment region, the decision threshold being at least equal to the first threshold of the first constant increment region, and the first threshold of the first constant increment region being greater than the second threshold of the first constant increment region; if, at the time of said comparison, said first attenuated output is not less than said discrimination threshold, outputting a first signal, performed at least in part using an electronic hardware configuration, indicating said first spike and said second spike as both caused by a shared underlying event; if, at the time of the comparison, the first decay output is less than the first threshold of the first constant increment region and not less than the second threshold of the first constant increment region, increasing a first decay rate of the first exponential decay unit and decreasing the decision threshold, performed at least in part using an electronic hardware configuration; identifying a second inter-stream spike pair including a third spike from the first spike stream and a fourth spike from the second spike stream, performed at least in part using an electronic hardware configuration; initiating a second exponential decay unit with a second decaying output upon receipt of said third spike, performed at least in part using an electronic hardware configuration; comparing, upon receipt of the fourth spike, the second decay output to a discrimination threshold, a first constant rate region first threshold, and a second constant rate region second threshold, performed at least in part using an electronic hardware configuration, wherein the first constant rate region first threshold is greater than the second constant rate region second threshold; if, at the time of said comparison, said second attenuated output is not less than said discrimination threshold, outputting a second signal, performed at least in part using an electronic hardware configuration, indicating said third spike and said fourth spike as both caused by a shared underlying event; and decreasing a first decay rate of the second exponential decay unit and increasing the decision threshold, performed at least in part using an electronic hardware configuration, if, at the time of the comparison, the second decay output is less than the first threshold of the first constant rate region and is not less than the second threshold of the first constant rate region.

15. 15. The method of claim 14, wherein the second threshold of the first constant increasing region is at least equal to the first threshold of the first constant decreasing region.

16. The method of claim 14 , wherein the same exponential decay unit functions as both the first exponential decay unit and the second exponential decay unit.

17. The method of claim 14 , wherein the first constant incremental increase region and the first constant incremental decrease region have stochastic symmetry.

18. The region where the value increases by the first constant amount of change and the region where the value decreases by the first constant amount of change are The method of claim 14 further comprising operating at the same scale.

19. 20. The method of claim 18, further comprising operating the first constant increment region and the first constant increment region on different samples.

20. 15. The method of claim 14, further comprising operating the first constant incremental region at a first scale and operating the first constant incremental region at a second scale, the first scale being different from the second scale.

21. 21. The method of claim 20, further comprising operating the first constant increment region and the first constant increment region on different samples.

22. operating a first set of one or more additional incremental regions according to at least one threshold different from the first and second thresholds of the first incremental region; operating a second set of one or more additional incremental regions according to at least one threshold different from the first and second thresholds of the first incremental region; operating said first set of incrementally increasing regions according to the same procedure as said first incrementally increasing regions; operating said second set of additional steadily decreasing regions according to the same procedure as said first steadily decreasing region; 15. The method of claim 14, further comprising operating the first set of the first steadily increasing regions and steadily increasing additional regions in a state of stochastic symmetry with respect to the second set of the first steadily decreasing regions and steadily decreasing additional regions.

23. 15. The method of claim 14, wherein the first spike of the first inter-stream spike pair is the same as the third spike of the second inter-stream spike pair and the second spike of the first inter-stream spike pair is the same as the fourth spike of the second inter-stream spike pair.

24. 15. The method of claim 14, wherein the first spike and the second spike of the first inter-stream spike pair are different from the third spike and the fourth spike of the second inter-stream spike pair.

25. 1. A system for identifying pairs of spikes that share an underlying event, comprising: a first subsystem, using at least in part an electronic hardware configuration, to receive a first spike stream having significant stochastic content except for a first subset of spikes, each spike of the first subset sharing underlying events with spikes of a second subset of spikes of a second spike stream; a second subsystem, using at least in part an electronic hardware configuration, for receiving the second spike stream, with all but the second subset having significant stochastic content; a third subsystem that, at least in part using electronic hardware configurations, identifies a first inter-stream spike pair, the first spike pair including a first spike from the first spike stream and a second spike from the second spike stream; At least in part using electronic hardware configurations, upon receipt of the first spike a fourth subsystem for initiating a first exponential decay unit with a first decay output at a fifth subsystem, at least in part using an electronic hardware configuration, for comparing, upon receipt of the second spike, the first attenuated output to a decision threshold, a first threshold of a first constant increment region, and a second threshold of the first constant increment region, the decision threshold being at least equal to the first threshold of the first constant increment region, and the first threshold of the first constant increment region being greater than the second threshold of the first constant increment region; a sixth subsystem, using at least in part an electronic hardware configuration, to output a first signal indicating the first spike and the second spike as both caused by a shared underlying event if, upon the comparison by the fifth subsystem, the first attenuated output is not less than the discrimination threshold; and a seventh subsystem, using at least in part an electronic hardware configuration, to increase a first decay rate of the first exponential decay unit and to decrease the decision threshold if, upon the comparison by the fifth subsystem, the first decay output is less than the first threshold of the first constant increment region and is not less than the second threshold of the first constant increment region; an eighth subsystem that identifies, at least in part using electronic hardware configurations, a second inter-stream spike pair including a third spike from the first spike stream and a fourth spike from the second spike stream; and a ninth subsystem, employing at least in part an electronic hardware configuration, initiating a second exponential decay unit with a second decaying output upon receipt of the third spike; a tenth subsystem, using at least in part an electronic hardware configuration, for comparing, upon receipt of the fourth spike, the second decay output to a decision threshold, a first constant rate region first threshold, and a second constant rate region second threshold, wherein the first constant rate region first threshold is greater than the second constant rate region second threshold; an eleventh subsystem, using at least in part an electronic hardware configuration, to output a second signal indicating the third spike and the fourth spike as both caused by a shared underlying event if, upon the comparison by the tenth subsystem, the second attenuated output is not less than the discrimination threshold; and a twelfth subsystem that, at the time of the comparison by the tenth subsystem, decreases a first decay rate of the second exponential decay unit and increases the decision threshold if the second decay output is less than the first threshold of the first constant rate region and is not less than the second threshold of the first constant rate region.

26. increasing the first delay by increasing a length of a first queue constituting the first delay unit; The method of claim 13 , further comprising: reducing the first delay by reducing a first queue length.

27. clocking a duration equal to the first delay when a first non-delayed spike from the first spike stream is input to the first delay unit if timing by the first delay unit has not already begun; outputting a spike upon completion of any timing of the first delay; determining a first state of a first decision variable and a second non-delayed spike during a duration of the previous non-delayed spike based on the first state of the first decision variable and receipt of a second non-delayed spike during the duration of the previous non-delayed spike; determining to continue said duration of the orgasm; determining to restart timing the first delay by the first delay unit based on a second state of the first decision variable and receipt of the second undelayed spike during the duration of the previous undelayed spike; 14. The method of claim 13, further comprising: ensuring, across multiple instances, receipt of the second non-delayed spike during the duration of the previous non-delayed spike for the first decision variable an approximately equal number of occurrences of the first and second states.

28. if a first exponential decrease function is greater than a first exponential increase function upon receiving a first undelayed spike from the first spike stream, increasing a first average spike rate to produce both the first exponential decrease function and the first exponential increase function; decreasing a first average spike rate to produce both the first exponential decrease function and the first exponential increase function when receiving the first undelayed spike from the first spike stream and if the first exponential decrease function is less than the first exponential increase function; 14. The method of claim 13, further comprising: using the first average spike rate to generate the first and second weighting functions.

29. if a first exponential decrease function is greater than a first exponential increase function upon receiving a first undelayed spike from the first spike stream, increasing a first average spike rate to produce both the first exponential decrease function and the first exponential increase function; decreasing a first average spike rate to produce both the first exponential decrease function and the first exponential increase function when receiving the first undelayed spike from the first spike stream and if the first exponential decrease function is less than the first exponential increase function; 28. The method of claim 27, further comprising: using the first average spike rate to time the first delay.

30. a thirteenth subsystem for receiving a first non-delayed spike stream, the first non-delayed spike stream including significant stochastic content except for a first subset of non-delayed spikes, each spike of the first subset of non-delayed spikes sharing underlying events with spikes of a second subset of non-delayed spikes of a second non-delayed spike stream; a fourteenth subsystem that inputs the first undelayed spike stream into a first delay unit to generate the first spike stream with a first delay, the first delay having a lower bound of zero seconds; a fifteenth subsystem that inputs the second undelayed spike stream into a first delay unit to generate the second spike stream with a second delay, the second delay having a lower bound of zero seconds; a sixteenth subsystem for comparing the first accumulated value with the second accumulated value upon receiving a first delayed spike from the first spike stream to generate a first comparison result; a seventeenth subsystem that increases the first delay if the first comparison result indicates that the first accumulated value is greater than the second accumulated value; an eighteenth subsystem that decreases the first delay if the first comparison result indicates that the first accumulated value is less than the second accumulated value; After the first comparison result is generated, the first accumulation value and the second accumulation value are reset. a nineteenth subsystem for controlling the a twentieth subsystem for initiating again the first process for generating a first weighting function and a second weighting function after the first comparison result is generated, the first weighting function being monotonically decreasing and the second weighting function being monotonically increasing and symmetrically opposite to the first weighting function; a twenty-first subsystem that accumulates a first weight value in a first accumulator according to the first weighting function upon receiving a second delayed spike from the second spike stream; and a twenty-second subsystem that accumulates a second weighting value in a second accumulator according to the second weighting function upon receiving a spike with the same second delay from the second spike stream.

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