Power Conversion Equipment

Abstract

To provide a highly efficient and small power conversion apparatus being compatible with a single phase three-wire self-supported output.SOLUTION: A flying capacitor type multi-level inverter 10 converts a DC voltage supplied from a DC power supply 2 into an AC voltage, and outputs the converted AC voltage to a single phase three-wire distribution line. A balancing circuit 20 includes: a first switch part SW1 and a second switch part SW2, which are connected in series between both ends of the DC power supply 2; and a reactor L1 connected between a connection point between the first switch part SW1 and the second switch part SW2, and a midpoint of the multi-level inverter 10 connected to a neutral line of the single phase three-wire distribution line. A control part 30 controls the first switch part SW1 and the second switch part SW2 so that the voltage of the midpoint of the multi-level inverter 10 becomes 1 / 2 of voltage of the DC power supply 2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device that converts DC power into AC power. [Background technology]

[0002] Single-phase power conditioners, which are connected between a DC power source such as a solar cell, a stationary storage battery, or an on-board storage battery and a power grid, are generally equipped with an independent operation mode that functions during a grid blackout. There are two types of independent output for single-phase power conditioners: single-phase two-wire and single-phase three-wire. With the single-phase two-wire type, only 100V equipment can be used, while with the single-phase three-wire type, 100V equipment can be connected between UO, 100V equipment between WO, and 200V equipment between UW.

[0003] In recent years, it has become desirable to adopt single-phase three-wire system for isolated output as well, so that power can be supplied to all in-house loads connected to the distribution board regardless of whether there is a power outage or not. To achieve single-phase three-wire system for isolated output, a function is required to adjust the phase voltage to 100V / line voltage to 200V when there is a load imbalance between the UO phase and the WO phase. Without this voltage adjustment function, there is a possibility that the power conditioner will stop operating or the load equipment will break down due to overvoltage or undervoltage of the phase voltage when the load is unbalanced.

[0004] There are two methods for achieving a voltage adjustment function: a commercial transformer method and a balance circuit method. The commercial transformer method is a method that adds an autotransformer or a transformer composed of a single-phase two-wire primary winding and a single-phase three-wire secondary winding. Both transformers operate at commercial frequencies. The balance circuit method is a method that adds a circuit to the O phase that balances the UO phase voltage and the WO phase voltage (see, for example, Patent Document 1). Comparing the commercial transformer method and the balance circuit method, the balance circuit method is superior in terms of size, weight, and cost. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2015-27178 A Summary of the Invention [Problem to be solved by the invention]

[0006] While there is a demand for power conditioners that are highly efficient and compact, there is also a demand for them to be equipped with single-phase three-wire independent output.

[0007] The present disclosure has been made in consideration of these circumstances, and has an object to provide a highly efficient and compact power conversion device that is compatible with single-phase three-wire independent output. [Means for solving the problem]

[0008] In order to solve the above problems, a power conversion device according to an embodiment of the present disclosure includes: a flying capacitor type multilevel inverter that converts a DC voltage supplied from a DC power source into an AC voltage and outputs the converted AC voltage to a single-phase three-wire distribution line; a balancing circuit having a first switch unit and a second switch unit connected in series between both ends of the DC power source; and a reactor connected between a connection point between the first switch unit and the second switch unit and a midpoint of the multilevel inverter that is connected to a neutral line of the single-phase three-wire distribution line; and a control unit that controls the first switch unit and the second switch unit so that a voltage at the midpoint of the multilevel inverter becomes 1 / 2 of the voltage of the DC power source. Effect of the Invention

[0009] According to the present disclosure, it is possible to realize a highly efficient and compact power conversion device that is compatible with single-phase three-wire independent output. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram for explaining the configuration of a power conversion device according to the first embodiment. [Diagram 2]1. FIG. 4 is a diagram showing a summary of switching patterns of a first switching element to a twenty-fourth switching element in the power conversion device of FIG. 1 in a grid-connected mode. [Diagram 3] 3(a)-(d) are circuit diagrams showing switching patterns of the positive half cycle of the switching pattern shown in FIG. [Figure 4] 4(a)-(d) are circuit diagrams showing switching patterns for the negative half cycle of the switching pattern shown in FIG. [Diagram 5] FIG. 1 is a diagram showing a pseudo-sine wave generated by a voltage of five levels (+E, +1 / 2E, 0, -1 / 2E, -E). [Figure 6] 6 is a diagram showing a summary of the output voltage Vinv_uw between U and W, the output voltage Vinv_uo between U and O, and the output voltage Vinv_wo between W and O of the multilevel inverter in each section of the pseudo sine wave shown in FIG. 5. [Figure 7] FIG. 11 is a diagram showing simulation waveforms of the output voltage Vout of the power conversion device, the output voltage Vinv of the multilevel inverter, and the output current Iout of the power conversion device when the first load (U-phase load) and the second load (W-phase load) are balanced. [Figure 8] FIG. 11 is a diagram showing simulation waveforms of the output voltage Vout of the power conversion device, the output voltage Vinv of the multilevel inverter, and the output current Iout of the power conversion device when the first load (U-phase load) and the second load (W-phase load) are not balanced. [Figure 9] 9(a) to 9(c) are diagrams illustrating configuration examples of flying capacitor circuits. [Figure 10] FIG. 1 is a diagram showing an N-stage flying capacitor circuit. [Figure 11] This figure shows a pseudo-sine wave generated with seven voltage levels (+E, +2 / 3E, +1 / 3E, 0, -1 / 3E, -2 / 3E, -E) by a multilevel inverter using a two-stage flying capacitor circuit. [Figure 12]12 is a diagram summarizing the output voltage Vinv_uw between U and W, the output voltage Vinv_uo between U and O, and the output voltage Vinv_wo between W and O of the multilevel inverter in each section of the pseudo sine wave shown in FIG. [Figure 13] FIG. 11 is a diagram for explaining the configuration of a power conversion device according to a second embodiment. [Figure 14] FIG. 11 is a diagram for explaining the configuration of a power conversion device according to a third embodiment. [Figure 15] FIG. 11 is a diagram for explaining a configuration of a power conversion device according to a modification of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Fig. 1 is a diagram for explaining the configuration of a power conversion device 1 according to a first embodiment. The power conversion device 1 converts DC power supplied from a DC power source 2 into AC power, and outputs the converted AC power to a power grid 3. The DC power source 2 is configured, for example, by a distributed power source (such as a solar cell, a storage battery, or a fuel cell) and a DC / DC converter (not shown) capable of controlling the output of the distributed power source. The DC / DC converter and the power conversion device 1 are connected by a DC bus. Note that the DC power source 2 may be configured by connecting a plurality of pairs of a distributed power source and a DC / DC converter in parallel.

[0012] The power conversion device 1 includes a multilevel inverter 10, a balancing circuit 20, and a control unit 30. The multilevel inverter 10 converts the DC voltage supplied from the DC power source 2 into an AC voltage by generating a pseudo sine wave having a multilevel voltage (five levels in the circuit configuration of FIG. 1) based on the DC voltage supplied from the DC power source 2.

[0013] The multilevel inverter 10 has a multilevel output section (in FIG. 1, composed of a first switching element Q1 to a sixteenth switching element Q16 and a first flying capacitor C1 to a fourth flying capacitor C4) that includes a plurality of flying capacitor circuits and can output five or more levels of potential, and a polarity switching section (in FIG. 1, composed of a seventeenth switching element Q17 to a twenty-fourth switching element Q24) that controls the direction of a current flowing between two points of the multilevel output section. In the example shown in FIG. 1, the multilevel output section includes a first flying capacitor circuit 11, a second flying capacitor circuit 12, a third flying capacitor circuit 13, and a fourth flying capacitor circuit 14. The polarity switching section includes a first output circuit 15 and a second output circuit 16.

[0014] The first flying capacitor circuit 11 and the second flying capacitor circuit 12 are connected in series between both ends of the DC power supply 2. The third flying capacitor circuit 13 and the fourth flying capacitor circuit 14 are connected in series between both ends of the DC power supply 2. An intermediate wiring Lm connects the connection point between the first flying capacitor circuit 11 and the second flying capacitor circuit 12 and the connection point between the third flying capacitor circuit 13 and the fourth flying capacitor circuit 14. The intermediate wiring Lm is connected to the neutral line (O phase line) of the single-phase three-wire distribution line.

[0015] The first flying capacitor circuit 11 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, a fourth switching element Q4, and a first flying capacitor C1. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series and connected between the positive side bus of the DC power supply 2 and the intermediate wiring Lm. The first flying capacitor C1 is connected between the connection point between the first switching element Q1 and the second switching element Q2 and the connection point between the third switching element Q3 and the fourth switching element Q4, and is charged and discharged by the first switching element Q1-the fourth switching element Q4.

[0016] The second flying capacitor circuit 12 includes a fifth switching element Q5, a sixth switching element Q6, a seventh switching element Q7, an eighth switching element Q8, and a second flying capacitor C2. The fifth switching element Q5, the sixth switching element Q6, the seventh switching element Q7, and the eighth switching element Q8 are connected in series and are connected between the intermediate wiring Lm and the negative bus of the DC power supply 2. The second flying capacitor C2 is connected between the connection point between the fifth switching element Q5 and the sixth switching element Q6 and the connection point between the seventh switching element Q7 and the eighth switching element Q8, and is charged and discharged by the fifth switching element Q5-the eighth switching element Q8.

[0017] The third flying capacitor circuit 13 includes a ninth switching element Q9, a tenth switching element Q10, an eleventh switching element Q11, a twelfth switching element Q12, and a third flying capacitor C3. The ninth switching element Q9, the tenth switching element Q10, the eleventh switching element Q11, and the twelfth switching element Q12 are connected in series and are connected between the positive side bus of the DC power supply 2 and the intermediate wiring Lm. The third flying capacitor C3 is connected between the connection point between the ninth switching element Q9 and the tenth switching element Q10 and the connection point between the eleventh switching element Q11 and the twelfth switching element Q12, and is charged and discharged by the ninth switching element Q9-the twelfth switching element Q12.

[0018] The fourth flying capacitor circuit 14 includes a thirteenth switching element Q13, a fourteenth switching element Q14, a fifteenth switching element Q15, a sixteenth switching element Q16, and a fourth flying capacitor C4. The thirteenth switching element Q13, the fourteenth switching element Q14, the fifteenth switching element Q15, and the sixteenth switching element Q16 are connected in series and are connected between the intermediate wiring Lm and the negative bus of the DC power supply 2. The fourth flying capacitor C4 is connected between the connection point between the thirteenth switching element Q13 and the fourteenth switching element Q14 and the connection point between the fifteenth switching element Q15 and the sixteenth switching element Q16, and is charged and discharged by the thirteenth switching element Q13-the sixteenth switching element Q16.

[0019] The first output circuit 15 is connected between a midpoint of the first flying capacitor circuit 11 (specifically, a connection point between the second switching element Q2 and the third switching element Q3) and a midpoint of the second flying capacitor circuit 12 (specifically, a connection point between the sixth switching element Q6 and the seventh switching element Q7). The first output circuit 15 includes a seventeenth switching element Q17, an eighteenth switching element Q18, a nineteenth switching element Q19, and a twentieth switching element Q20 connected in series. The midpoint of the first output circuit 15 (specifically, a connection point between the eighteenth switching element Q18 and the nineteenth switching element Q19) is connected to a first voltage line (U-phase line) of a single-phase three-wire power distribution line.

[0020] The second output circuit 16 is connected between the midpoint of the third flying capacitor circuit 13 (specifically, the connection point between the tenth switching element Q10 and the eleventh switching element Q11) and the midpoint of the fourth flying capacitor circuit 14 (specifically, the connection point between the fourteenth switching element Q14 and the fifteenth switching element Q15). The second output circuit 16 includes a twenty-first switching element Q21, a twenty-second switching element Q22, a twenty-third switching element Q23, and a twenty-fourth switching element Q24 connected in series. The midpoint of the second output circuit 16 (specifically, the connection point between the twenty-second switching element Q22 and the twenty-third switching element Q23) is connected to a second voltage line (W-phase line) of a single-phase three-wire distribution line.

[0021] A potential in the range between E [V] applied to the upper terminal of the first switching element Q1 and 1 / 2E [V] applied to the lower terminal of the fourth switching element Q4 is output from the midpoint of the first flying capacitor circuit 11. The first flying capacitor C1 is initially charged (precharged) to a voltage of 1 / 4E [V], and charging and discharging are repeated with the voltage of 1 / 4E [V] at the center. Therefore, the first flying capacitor circuit 11 outputs approximately three levels of potential: E [V], 3 / 4E [V], and 1 / 2E [V].

[0022] A potential in the range between 1 / 2E [V] applied to the upper terminal of the fifth switching element Q5 and 0 [V] applied to the lower terminal of the eighth switching element Q8 is output from the midpoint of the second flying capacitor circuit 12. The second flying capacitor C2 is initially charged to a voltage of 1 / 4E [V], and charging and discharging are repeated with the voltage of 1 / 4E [V] at the center. Therefore, the second flying capacitor circuit 12 outputs approximately three levels of potential: 1 / 2E [V], 1 / 4E [V], and 0 [V].

[0023] A potential in the range between E [V] applied to the upper terminal of the ninth switching element Q9 and 1 / 2E [V] applied to the lower terminal of the twelfth switching element Q12 is output from the midpoint of the third flying capacitor circuit 13. The third flying capacitor C3 is initially charged to a voltage of 1 / 4E [V], and charging and discharging are repeated with the voltage of 1 / 4E [V] at the center. Therefore, the third flying capacitor circuit 13 outputs three levels of potential, roughly E [V], 3 / 4E [V], and 1 / 2E [V].

[0024] A potential in the range between 1 / 2E [V] applied to the upper terminal of the 13th switching element Q13 and 0 [V] applied to the lower terminal of the 16th switching element Q16 is output from the midpoint of the fourth flying capacitor circuit 14. The fourth flying capacitor C4 is initially charged to a voltage of 1 / 4E [V], and charging and discharging are repeated with the voltage of 1 / 4E [V] at the center. Therefore, the fourth flying capacitor circuit 14 outputs approximately three levels of potential: 1 / 2E [V], 1 / 4E [V], and 0 [V].

[0025] A diode is formed or connected in anti-parallel to each of the first switching element Q1 to the 24th switching element Q24. In the following embodiment, an example is assumed in which an N-channel MOSFET with a withstand voltage of 150 V is used for each of the first switching element Q1 to the 24th switching element Q24. In the N-channel MOSFET, a parasitic diode is formed from the source to the drain.

[0026] Note that an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor may be used for the first switching element Q1 to the 24th switching element Q24. In this case, no parasitic diode is formed in the first switching element Q1 to the 24th switching element Q24, and an external diode is connected in anti-parallel to each of the first switching element Q1 to the 24th switching element Q24.

[0027] In addition, the first switching element Q1 to the twenty-fourth switching element Q24 may be switching elements made of wide band gap semiconductors using silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or the like.

[0028] A multi-level voltage (a voltage of five levels in the circuit configuration of FIG. 1) is output from the midpoint of the first output circuit 15 (specifically, the connection point between the eighteenth switching element Q18 and the nineteenth switching element Q19) and the midpoint of the second output circuit 16 (specifically, the connection point between the twenty-second switching element Q22 and the twenty-third switching element Q23) to an output filter (configured by the first output reactor L2, the second output reactor L3, the first output capacitor C7, and the second output capacitor C8 in FIG. 1). The greater the number of levels, the closer the pseudo-sine wave is to a regular sine wave. In this embodiment, U-phase power is output from the midpoint of the first output circuit 15, and W-phase power is output from the midpoint of the second output circuit 16.

[0029] The output filter attenuates harmonic components of the voltage and current output from the first output circuit 15 and the second output circuit 16 to bring them closer to a sine wave synchronized with the sine wave of the power system 3. The output filter includes a first output reactor L2, a second output reactor L3, a first output capacitor C7, and a second output capacitor C8. The first output reactor L2 is inserted in a first voltage line (U-phase line) of a single-phase three-wire distribution line. The second output reactor L3 is inserted in a second voltage line (W-phase line) of the single-phase three-wire distribution line. The first output capacitor C7 is connected between the first voltage line and a neutral line of the single-phase three-wire distribution line. The second output capacitor C8 is connected between the second voltage line and a neutral line of the single-phase three-wire distribution line.

[0030] A first relay RY1 is inserted in the distribution line between the output filter and a single-phase three-wire power system 3. A second relay RY2 is inserted in the distribution line between the output filter and a single-phase three-wire independent output terminal.

[0031] A first load R1 (U-phase load) is connected between the independent output terminals of the first voltage line and neutral line of the single-phase three-wire system. A second load R2 (W-phase load) is connected between the independent output terminals of the second voltage line and neutral line of the single-phase three-wire system. A third load R3 (line load) is connected between the independent output terminals of the first voltage line and second voltage line of the single-phase three-wire system. A 200V device (e.g., an induction cooking heater, an electric water heater, etc.) can be connected as the third load R3. The first load R1, the second load R2, and the third load R3 are specific loads that can receive power supply preferentially in the event of a grid power outage.

[0032] The first voltage sensor 41 measures the output voltage Vout_uo between U and O of the power conversion device 1 and outputs it to the control unit 30. The second voltage sensor 42 measures the output voltage Vout_wo between W and O of the power conversion device 1 and outputs it to the control unit 30. The third voltage sensor 43 measures the output voltage Vout_uw between U and W of the power conversion device 1 and outputs it to the control unit 30.

[0033] The first voltage sensor 41 to the third voltage sensor 43 are disposed in a stage subsequent to the output filter. Each of the first voltage sensor 41 to the third voltage sensor 43 includes, for example, a voltage dividing resistor and an error amplifier.

[0034] The first current sensor 51 measures an output current Iout_U flowing through a first voltage line of the single-phase three-wire distribution line and outputs it to the control unit 30. The second current sensor 52 measures an output current Iout_W flowing through a second voltage line of the single-phase three-wire distribution line and outputs it to the control unit 30. The third current sensor 53 measures an output current Iout_O flowing through a neutral line of the single-phase three-wire distribution line and outputs it to the control unit 30. The fourth current sensor 54 measures a reactor current IL_U flowing through the first output reactor L2 and outputs it to the control unit 30. The fifth current sensor 55 measures a reactor current IL_W flowing through the second output reactor L3 and outputs it to the control unit 30. Each of the first current sensor 51 to the fifth current sensor 55 includes, for example, a CT sensor or a Hall sensor.

[0035] The balancing circuit 20 is connected between the positive bus and the negative bus of the DC power supply 2, and has a function of maintaining the midpoint voltage of the multilevel inverter 10 at 1 / 2E. The balancing circuit 20 includes a first switch section SW1, a second switch section SW2, a reactor L1, a first dividing capacitor C5, and a second dividing capacitor C6.

[0036] Each of the first switch section SW1 and the second switch section SW2 may be composed of one switching element (for example, MOSFET), or may be composed of a plurality of switching elements connected in series or in parallel.

[0037] A first switch section SW1 and a second switch section SW2 are connected in series between the positive bus and the negative bus of the DC power supply 2. A first dividing capacitor C5 and a second dividing capacitor C6 are connected in series between the positive bus and the negative bus of the DC power supply 2. A reactor L1 is connected between a first connection point between the first switch section SW1 and the second switch section SW2 and a second connection point between the first dividing capacitor C5 and the second dividing capacitor C6. A neutral line of a single-phase three-wire distribution line is further connected to the second connection point, and a midpoint of a multilevel inverter 10 is connected to the neutral line.

[0038] The control unit 30 performs overall control of the power conversion device 1. The control unit 30 can be realized by a combination of hardware resources and software resources, or by hardware resources alone. Analog elements, microcontrollers, DSPs, ROMs, RAMs, FPGAs, ASICs, and other LSIs can be used as hardware resources. Programs such as firmware can be used as software resources.

[0039] In this embodiment, the control unit 30 controls the on / off of the first switching element Q1 to the twenty-fourth switching element Q24 of the multilevel inverter 10, the first switch section SW1, the second switch section SW2, the first relay RY1, and the second relay RY2 of the balancing circuit 20.

[0040] FIG. 2 is a diagram showing switching patterns of the first switching element Q1 to the twenty-fourth switching element Q24 in the power conversion device 1 of FIG. 1 in the grid interconnection mode.

[0041] 2, a group of the first switching element Q1, the fifth switching element Q5, the twelfth switching element Q12, and the sixteenth switching element Q16 is complementary to a group of the fourth switching element Q4, the eighth switching element Q8, the ninth switching element Q9, and the thirteenth switching element Q13. A group of the second switching element Q2, the sixth switching element Q6, the eleventh switching element Q11, and the fifteenth switching element Q15 is complementary to a group of the third switching element Q3, the seventh switching element Q7, the tenth switching element Q10, and the fourteenth switching element Q14.

[0042] In addition, the group consisting of the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 is always on during the positive half cycle of the fundamental wave and always off during the negative half cycle. The group consisting of the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 is always on during the negative half cycle of the fundamental wave and always off during the positive half cycle. In Japan, the fundamental wave is a sine wave of 50 Hz / 60 Hz.

[0043] Figures 3(a)-(d) are circuit diagrams showing a switching pattern of a positive half cycle of the switching pattern shown in Figure 2. Figures 4(a)-(d) are circuit diagrams showing a switching pattern of a negative half cycle of the switching pattern shown in Figure 2. Note that, to simplify the drawings, MOSFETs are depicted with simple switch symbols.

[0044] As shown in FIG. 3(a), when +0 is output from the multilevel inverter 10, the control unit 30 controls the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the on state, and controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the off state.

[0045] As shown in FIG. 3(b), in the case where +1 / 2E is output from the multilevel inverter 10 while the first flying capacitor C1 and the fourth flying capacitor C4 are charged from the DC power supply 2, the control unit 30 controls the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the eighteenth switching element Q20, the eighteenth switching element Q22, the eighteenth switching element Q24, the eighteenth switching element Q26, the eighteenth switching element Q28, the eighteenth switching element Q29, the eighteenth switching element Q30, the eighteenth switching element Q31, the eighteenth switching element Q32, the eighteenth switching element Q33, the eighteenth switching element Q34, the eighteenth switching element Q35, the eighteenth switching element Q36, the eighteenth switching element Q37, the eighteenth switching element Q38, the eighteenth switching element Q39, the eighteenth switching element Q40, the eighteenth switching element Q41, the eighteenth switching element Q42, the eighteenth switching element Q43, the eighteenth switching element Q44, the eighteenth switching element Q45, the eighteenth switching element Q46, the eighteenth switching element Q47, the eighteenth switching element Q48, the eighteenth switching element Q49, the eighteenth switching element Q50, the eighteenth switching element Q51, the eighteenth switching element Q52, the eighteenth switching element Q53, the eighteenth switching element Q54, the eighteenth switching element Q55, the eighteenth switching element Q56, the eighteenth switching element Q57, the eighteenth switching element Q58, the eighteenth switching element Q59, the The element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 are controlled to the on state, and the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 are controlled to the off state.

[0046] As shown in FIG. 3( c), in the case where +½E is output from the multilevel inverter 10 while discharging from the first flying capacitor C1 and the fourth flying capacitor C4 to the power grid 3, the control unit 30 controls the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q18, the eighteenth switching element Q19, the eighteenth switching element Q20, the fourth switching element Q40, the sixth switching element Q60, the eighth switching element Q80, the ninth switching element Q90, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q20, the eighteenth switching element Q21, the eighteenth switching element Q22, the fourth switching element Q40, the sixth switching element Q60, the eighth switching element Q80, the ninth switching element Q90, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q21, the eighteenth switching element Q22, the eighteenth switching element Q23, the eighteenth switching element Q24, the eighteenth switching element Q25, the eighteenth switching element Q26, the eighteenth switching element Q27, the eighteenth switching element Q28, the eighteenth switching element Q29, the eighteenth switching element Q30, the eighteenth switching element Q31, the eighteenth switching element Q32, the eighteenth switching element Q33, the eighteenth switching element Q34, the eighteenth switching element Q35, the eight The first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 are controlled to the off state.

[0047] The control unit 30 can cause the multilevel inverter 10 to output +1 / 2E by alternately repeating the switching pattern shown in FIG. 3(b) and the switching pattern shown in FIG. 3(c).

[0048] As shown in FIG. 3(d), when +E is output from the multilevel inverter 10, the control unit 30 controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the ON state, and controls the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the OFF state.

[0049] As shown in FIG. 4(a), when −0 is output from the multilevel inverter 10, the control unit 30 controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and controls the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0050] As shown in FIG. 4(b), in the case where −½E is output from the multilevel inverter 10 while the second flying capacitor C2 and the third flying capacitor C3 are being charged from the DC power supply 2, the control unit 30 controls the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the nineteenth switching element Q19, the twentieth ...2 The first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 are controlled to the off state.

[0051] As shown in FIG. 4(c), in the case where −1 / 2E is output from the multilevel inverter 10 while discharging from the second flying capacitor C2 and the third flying capacitor C3 to the power grid 3, the control unit 30 controls the first switching element Q1, the third switching element Q3, the fifth switching element Q5, the seventh switching element Q7, the tenth switching element Q10, the twelfth switching element Q12, the fourteenth switching element Q14, the sixteenth switching element Q16, the nineteenth switching element Q19, the twentieth switching element Q20, the tenth switching element Q22, the tenth switching element Q24, the tenth switching element Q26, the nineteenth switching element Q28, the tenth switching element Q29, the tenth switching element Q30, the tenth switching element Q32, the tenth switching element Q34, the tenth switching element Q36, the tenth switching element Q38, the tenth switching element Q36, the tenth switching element Q38, the tenth switching element Q39, the tenth switching element Q40, the tenth switching element Q41, the tenth switching element Q42, the tenth switching element Q43, the tenth switching element Q44, the tenth switching element Q45, the tenth switching element Q46, the tenth switching element Q47, the tenth switching element Q48, the tenth switching element Q49, the tenth switching element Q50, the tenth switching element Q52, the tenth switching element Q54, the tenth switching element Q56, the tenth switching element Q58, the tenth switching element Q56, the tenth switching element Q58, the tenth switching element Q59, the tenth switching element Q60, the tenth switching element Q60, the tenth switching element Q61, the tenth switching element Q62, the tenth switching element Q63, the tenth switching element Q64, the tenth switching element Q65, the tenth switching element Q66, the tenth switching element Q6 The element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 are controlled to the on state, and the second switching element Q2, the fourth switching element Q4, the sixth switching element Q6, the eighth switching element Q8, the ninth switching element Q9, the eleventh switching element Q11, the thirteenth switching element Q13, the fifteenth switching element Q15, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 are controlled to the off state.

[0052] The control unit 30 can cause the multilevel inverter 10 to output −1 / 2E by alternately repeating the switching pattern shown in FIG. 4(b) and the switching pattern shown in FIG. 4(c).

[0053] As shown in FIG. 4(d), when −E is output from the multilevel inverter 10, the control unit 30 controls the third switching element Q3, the fourth switching element Q4, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the thirteenth switching element Q13, the fourteenth switching element Q14, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 to the ON state, and controls the first switching element Q1, the second switching element Q2, the fifth switching element Q5, the sixth switching element Q6, the eleventh switching element Q11, the twelfth switching element Q12, the fifteenth switching element Q15, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the twenty-third switching element Q23, and the twenty-fourth switching element Q24 to the OFF state.

[0054] Fig. 5 is a diagram showing a pseudo sine wave generated by a voltage of five levels (+E, +1 / 2E, 0, -1 / 2E, -E). Fig. 6 is a diagram showing the output voltage Vinv_uw between U and W, the output voltage Vinv_uo between U and O, and the output voltage Vinv_wo between W and O of the multilevel inverter 10 in each section of the pseudo sine wave shown in Fig. 5.

[0055] In section (a), +1 / 2E and 0 are alternately output from the multilevel inverter 10 as the output voltage Vinv_uw between U and W, +1 / 4E and 0 are alternately output as the output voltage Vinv_uo between U and O, and -1 / 4E and 0 are alternately output as the output voltage Vinv_wo between W and O. In section (b), +E and +1 / 2E are alternately output from the multilevel inverter 10 as the output voltage Vinv_uw between U and W, +1 / 2E and +1 / 4E are alternately output as the output voltage Vinv_uo between U and O, and -1 / 2E and -1 / 4E are alternately output as the output voltage Vinv_wo between W and O. In section (c), the multilevel inverter 10 alternately outputs +1 / 2 and 0 as the output voltage Vinv_uw between U and W, alternates between +1 / 4E and 0 as the output voltage Vinv_uo between U and O, and alternates between -1 / 4E and 0 as the output voltage Vinv_wo between W and O.

[0056] In section (d), the multilevel inverter 10 alternately outputs -1 / 2 and 0 as the output voltage Vinv_uw between U and W, alternates between -1 / 4E and 0 as the output voltage Vinv_uo between U and O, and alternates between +1 / 4E and 0 as the output voltage Vinv_wo between W and O. In section (e), the multilevel inverter 10 alternately outputs -E and -1 / 2E as the output voltage Vinv_uw between U and W, alternates between -1 / 2E and -1 / 4E as the output voltage Vinv_uo between U and O, and alternates between +1 / 2E and +1 / 4E as the output voltage Vinv_wo between W and O. In section (f), the multilevel inverter 10 alternately outputs -1 / 2E and 0 as the output voltage Vinv_uw between U and W, alternates between -1 / 4E and 0 as the output voltage Vinv_uo between U and O, and alternates between +1 / 4E and 0 as the output voltage Vinv_wo between W and O.

[0057] In either section, the absolute values ​​of the output voltage Vinv_uo between U and O and the output voltage Vinv_wo between W and O are 1 / 2 the output voltage Vinv_uw between U and W. In this way, the multilevel inverter 10 outputs any of +1 / 2E, +1 / 4E, 0, -1 / 4E, -1 / 2E between the first voltage line and neutral line of the single-phase three-wire distribution line, outputs any of +1 / 2E, +1 / 4E, 0, -1 / 4E, -1 / 2E between the second voltage line and neutral line, and outputs any of +E, +1 / 2E, 0, -1 / 2E, -E between the first voltage line and second voltage line.

[0058] When the power conversion device 1 is operated in the grid-connected mode, the control unit 30 controls the first relay RY1 to be in an ON state and the second relay RY2 to be in an OFF state. The control unit 30 controls the first switching element Q1 to the 24th switching element Q24 so that the current flowing through the first output reactor L2 measured by the fourth current sensor 54 or the current flowing through the second output reactor L3 measured by the fifth current sensor 55 maintains a target current value. More specifically, the control unit 30 controls the first switching element Q1 to the 16th switching element Q16 by PWM (Pulse Width Modulation) so that the measured current value maintains the target current value.

[0059] In the grid-connected mode, the control unit 30 stops the operation of the first switch unit SW1 and the second switch unit SW2. In the grid-connected mode, since no current flows through the O phase of the output current from the multilevel inverter 10, the voltage division balance between the first dividing capacitor C5 and the second dividing capacitor C6 is basically not lost, and there is no need to operate the balance circuit 20.

[0060] When the power conversion device 1 is operated in the isolated operation mode, the control unit 30 controls the first relay RY1 to be in the off state and the second relay RY2 to be in the on state. In the isolated operation mode, the power conversion device 1 is disconnected from the power grid 3, so that the voltages of the first load R1 to the third load R3 need to be regulated by the power conversion device 1.

[0061] In the independent operation mode, the control unit 30 PWM-controls the first switching element Q1-eighth switching element Q8 and the seventeenth switching element Q17-twentieth switching element Q20 of the U phase of the multilevel inverter 10 so that the UO output voltage Vout_uo of the power conversion device 1 measured by the first voltage sensor 41 becomes 1 / 2 of the UW output voltage Vout_uw measured by the third voltage sensor 43. At the same time, the control unit 30 PWM-controls the ninth switching element Q9-sixteenth switching element Q16 and the twenty-first switching element Q21-twentieth switching element Q24 of the W phase of the multilevel inverter 10 so that the WO output voltage Vout_uo measured by the second voltage sensor 42 becomes 1 / 2 of the UW output voltage Vout_uw measured by the third voltage sensor 43.

[0062] In the independent operation mode, the control unit 30 controls the first switch unit SW1 and the second switch unit SW2 so that the midpoint voltage of the multilevel inverter 10 (= the midpoint voltage of the first dividing capacitor C5 and the second dividing capacitor C6) becomes 1 / 2E. The control unit 30 measures the midpoint voltage of the multilevel inverter 10 based on a voltage measured by at least one of a voltage sensor (not shown) connected in parallel to the first dividing capacitor C5 and a voltage sensor (not shown) connected in parallel to the second dividing capacitor C6.

[0063] When the midpoint voltage of the multilevel inverter 10 is higher than 1 / 2E, the control unit 30 increases the period during which the first switch unit SW1 is in the OFF state and the second switch unit SW2 is in the ON state, thereby decreasing the midpoint voltage of the multilevel inverter 10. Conversely, when the midpoint voltage of the multilevel inverter 10 is lower than 1 / 2E, the control unit 30 increases the period during which the first switch unit SW1 is in the ON state and the second switch unit SW2 is in the OFF state, thereby increasing the midpoint voltage of the multilevel inverter 10.

[0064] When the power consumption of a first load R1 (U-phase load) connected between a first voltage line and a neutral line differs from the power consumption of a second load R2 (W-phase load) connected between a second voltage line and a neutral line, a difference current between a current flowing through the first voltage line and a current flowing through the second voltage line flows through the neutral line to the multilevel inverter 10 and the balance circuit 20. Specifically, the difference current is divided into a current flowing through the neutral line to the U-phase leg or W-phase leg of the multilevel inverter 10, a current flowing through the first dividing capacitor C5 and the second dividing capacitor C6, and a current flowing through the reactor L1.

[0065] 7 is a diagram showing simulation waveforms of the output voltage Vout of the power conversion device 1, the output voltage Vinv of the multilevel inverter 10, and the output current Iout of the power conversion device 1 when the first load R1 (U-phase load) and the second load R2 (W-phase load) are balanced. In the example shown in Fig. 7, the power consumption of the first load R1 (U-phase load) is 3 kW, the power consumption of the second load R2 (W-phase load) is 3 kW, the third load R3 (line load) is not connected, and the bus voltage Vbus of the DC power supply 2 is 400 V.

[0066] In this case, the output voltage Vout_uo between U and O of the power conversion device 1 is 100 Vrms, the output voltage Vout_wo between W and O is 100 Vrms, the output voltage Vout_uw between U and W is 200 Vms, the output current Iout_U of the U phase is 30 Arms, the output current Iout_W of the W phase is 30 Arms, and the output current Iout_o of the O phase is 0 Arms.

[0067] 8 is a diagram showing simulation waveforms of the output voltage Vout of the power conversion device 1, the output voltage Vinv of the multilevel inverter 10, and the output current Iout of the power conversion device 1 when the first load R1 (U-phase load) and the second load R2 (W-phase load) are not balanced. In the example shown in Fig. 8, the power consumption of the first load R1 (U-phase load) is 3 kW, the power consumption of the second load R2 (W-phase load) is 1 kW, the third load R3 (line load) is not connected, and the bus voltage Vbus of the DC power supply 2 is 400 V.

[0068] In this case, the output voltage Vout_uo between U and O of the power conversion device 1 is 100 Vrms, the output voltage Vout_wo between W and O is 100 Vrms, the output voltage Vout_uw between U and W is 200 Vms, the output current Iout_U between U and W is 30 Arms, the output current Iout_W between W and W is 10 Arms, and the output current Iout_o between O and O is 20 Arms.

[0069] In both cases when the first load R1 (U-phase load) and the second load R2 (W-phase load) shown in FIG. 7 are balanced and when the first load R1 (U-phase load) and the second load R2 (W-phase load) shown in FIG. 8 are unbalanced, the balance circuit 20 controls the midpoint voltage Vmid of the multilevel inverter 10 to 200 V.

[0070] 9(a)-(c) are diagrams showing configuration examples of a flying capacitor circuit. FIG. 9(a) shows a one-stage flying capacitor circuit. The flying capacitor circuit shown in FIG. 9(a) includes four switching elements Q2a, Q1a, Q1b, and Q2b connected in series, and one capacitor Ca1. Capacitor Ca1 is connected between the connection point between switching elements Q2a and Q1a and the connection point between switching elements Q1b and Q2b. Capacitor Ca1 is charged with a voltage of 1 / 4E.

[0071] FIG. 9(b) shows a two-stage flying capacitor circuit. The two-stage flying capacitor circuit includes six switching elements Q3a, Q2a, Q1a, Q1b, Q2b, and Q3b connected in series, and two capacitors Ca1 and Ca2. Capacitor Ca1 is connected between the connection point between switching elements Q2a and Q1a and the connection point between switching elements Q1b and Q2b. Capacitor Ca1 is charged with a voltage of 1 / 6E. Capacitor Ca2 is connected between the connection point between switching elements Q3a and Q2a and the connection point between switching elements Q2b and Q3b. Capacitor Ca2 is charged with a voltage of 2 / 6E.

[0072] FIG. 9(c) shows a three-stage flying capacitor circuit. The three-stage flying capacitor circuit includes eight switching elements Q4a, Q3a, Q2a, Q1a, Q1b, Q2b, Q3b, and Q4b connected in series, and three capacitors Ca1, Ca2, and Ca3. Capacitor Ca1 is connected between the connection point between switching elements Q2a and Q1a and the connection point between switching elements Q1b and Q2b. Capacitor Ca1 is charged with a voltage of 1 / 8E. Capacitor Ca2 is connected between the connection point between switching elements Q3a and Q2a and the connection point between switching elements Q2b and Q3b. Capacitor Ca2 is charged with a voltage of 2 / 8E. Capacitor Ca3 is connected between the connection point between switching elements Q4a and Q3a and the connection point between switching elements Q3b and Q4b. Capacitor Ca3 is charged with a voltage of 3 / 8E.

[0073] FIG. 10 shows an N-stage flying capacitor circuit. The N-stage flying capacitor circuit includes (2N+2) switching elements Q(n+1)a, Qna, . . ., Q4a, Q3a, Q2a, Q1a, Q1b, Q2b, Q3b, Q4b, . . ., Qnb, and Q(n+1)b connected in series, and N capacitors Ca1, Ca2, Ca3, . . ., and Can. The capacitor Ca1 is connected between the connection point between the switching elements Q2a and Q1a and the connection point between the switching elements Q1b and Q2b. The capacitor Ca1 is charged with a voltage of 1 / (2N+2)E. The capacitor Ca2 is connected between the connection point between the switching elements Q3a and Q2a and the connection point between the switching elements Q2b and Q3b. The capacitor Ca2 is charged with a voltage of 2 / (2N+2)E. Capacitor Ca3 is connected between the connection point between switching elements Q4a, Q3a and the connection point between switching elements Q3b, Q4b. A voltage of 3 / (2N+2)E is charged to capacitor Ca3. Capacitor Can is connected between the connection point between switching elements Q(n+1)a, Qna and the connection point between switching elements Qnb, Q(n+1)b. A voltage of N / (2N+2)E is charged to capacitor Can.

[0074] The multilevel inverter 10 shown in Fig. 1 uses a one-stage flying capacitor circuit shown in Fig. 9(a). When a one-stage flying capacitor circuit is used, the multilevel inverter 10 can output voltages of five levels (+E, +1 / 2E, 0, -1 / 2E, -E).

[0075] When the two-stage flying capacitor circuit shown in FIG. 9(b) is used, seven voltage levels (+E, +2 / 3E, +1 / 3E, 0, -1 / 3E, -2 / 3E, -E) can be output from the multilevel inverter 10. When the three-stage flying capacitor circuit shown in FIG. 9(c) is used, nine voltage levels (+E, +3 / 4E, +2 / 4E, +1 / 4E, 0, -1 / 4E, -2 / 4E, -3 / 4E, -E) can be output from the multilevel inverter 10. When the N-stage flying capacitor circuit shown in FIG. 10 is used, (2N+3) types of voltages can be output from the multilevel inverter 10.

[0076] Fig. 11 is a diagram showing a pseudo sine wave generated by a multilevel inverter 10 using a two-stage flying capacitor circuit with seven voltage levels (+E, +2 / 3E, +1 / 3E, 0, -1 / 3E, -2 / 3E, -E). Fig. 12 is a diagram showing the output voltage Vinv_uw between U and W, the output voltage Vinv_uo between U and O, and the output voltage Vinv_wo between W and O of the multilevel inverter 10 in each section of the pseudo sine wave shown in Fig. 11.

[0077] In section (a), +1 / 3E and 0 are alternately output from the multilevel inverter 10 as the output voltage Vinv_uw between U and W, +1 / 6E and 0 are alternately output as the output voltage Vinv_uo between U and O, and -1 / 6E and 0 are alternately output as the output voltage Vinv_wo between W and O. In section (b), +2 / 3E and +1 / 3E are alternately output from the multilevel inverter 10 as the output voltage Vinv_uw between U and W, +1 / 3E and +1 / 6E are alternately output as the output voltage Vinv_uo between U and O, and -1 / 3E and -1 / 6E are alternately output as the output voltage Vinv_wo between W and O. In section (c), +E and +2 / 3E are alternately output as the output voltage Vinv_uw between U and W, +1 / 2E and +1 / 3E are alternately output as the output voltage Vinv_uo between U and O, and -1 / 2E and -1 / 3E are alternately output as the output voltage Vinv_wo between W and O. In section (d), +2 / 3E and +1 / 3E are alternately output as the output voltage Vinv_uw between U and W, +1 / 3E and +1 / 6E are alternately output as the output voltage Vinv_uo between U and O, and -1 / 3E and -1 / 6E are alternately output as the output voltage Vinv_wo between W and O. In section (e), the multilevel inverter 10 alternately outputs +1 / 3E and 0 as the output voltage Vinv_uw between U and W, alternates between +1 / 6E and 0 as the output voltage Vinv_uo between U and O, and alternates between -1 / 6E and 0 as the output voltage Vinv_wo between W and O.

[0078] In section (f), the multilevel inverter 10 alternately outputs -1 / 3E and 0 as the output voltage Vinv_uw between U and W, alternates between -1 / 6E and 0 as the output voltage Vinv_uo between U and O, and alternates between +1 / 6E and 0 as the output voltage Vinv_wo between W and O. In section (g), the multilevel inverter 10 alternately outputs -2 / 3E and -1 / 3E as the output voltage Vinv_uw between U and W, alternates between -1 / 3E and -1 / 6E as the output voltage Vinv_uo between U and O, and alternates between +1 / 3E and +1 / 6E as the output voltage Vinv_wo between W and O. In section (h), the multilevel inverter 10 alternately outputs -E and -2 / 3E as the output voltage Vinv_uw between U and W, alternately outputs -1 / 2E and -1 / 3E as the output voltage Vinv_uo between U and O, and alternately outputs +1 / 2E and +1 / 3E as the output voltage Vinv_wo between W and O. In section (i), the multilevel inverter 10 alternately outputs -2 / 3E and -1 / 3E as the output voltage Vinv_uw between U and W, alternately outputs -1 / 3E and -1 / 6E as the output voltage Vinv_uo between U and O, and alternately outputs +1 / 3E and +1 / 6E as the output voltage Vinv_wo between W and O. In section (j), the multilevel inverter 10 alternately outputs -1 / 3E and 0 as the output voltage Vinv_uw between U and W, alternates between -1 / 6E and 0 as the output voltage Vinv_uo between U and O, and alternates between +1 / 6E and 0 as the output voltage Vinv_wo between W and O.

[0079] In either section, the output voltage Vinv_uo between U and O and the output voltage Vinv_wo between W and O are 1 / 2 of the output voltage Vinv_uw between U and W. In this way, the multilevel inverter 10 using the two-stage flying capacitor circuit outputs any one of +1 / 2E, +1 / 3E, +1 / 6E, 0, -1 / 6E, -1 / 3E, -1 / 2E between the first voltage line and the neutral line of the single-phase three-wire distribution line, outputs any one of +1 / 2E, +1 / 3E, +1 / 6E, 0, -1 / 6E, -1 / 3E, -1 / 2E between the second voltage line and the neutral line, and outputs any one of +E, +2 / 3E, +1 / 3E, 0, -1 / 3E, -2 / 3E, -E between the first voltage line and the second voltage line.

[0080] As described above, the multilevel inverter 10 using one stage of flying capacitor circuit outputs any of +1 / 2E, +1 / 4E, 0, -1 / 4E, -1 / 2E between the first voltage line and neutral line of a single-phase three-wire distribution line, outputs any of +1 / 2E, +1 / 4E, 0, -1 / 4E, -1 / 2E between the second voltage line and neutral line, and outputs any of +E, +1 / 2E, 0, -1 / 2E, -E between the first voltage line and second voltage line.

[0081] A multilevel inverter 10 using N (N is a natural number) stages of flying capacitor circuits outputs (2N+3) types of voltages in the range of +1 / 2E to -1 / 2E between a first voltage line and a neutral line of a single-phase three-wire distribution line, outputs (2N+3) types of voltages in the range of +1 / 2E to -1 / 2E between the second voltage line and the neutral line, and outputs (2N+3) types of voltages in the range of +E to -E between the first voltage line and the second voltage line.

[0082] As described above, according to the first embodiment, by combining the multilevel inverter 10 and the balancing circuit 20, it is possible to realize a highly efficient and small-sized power conversion device 1 while supporting single-phase three-wire isolated output. Therefore, both 100V devices and 200V devices can be used during a grid power outage. Furthermore, by controlling the UO voltage to 100V, the WO voltage to 100V, and the UW voltage to 200V with the balancing circuit 20, it is possible to realize a smaller size, lighter weight, and lower cost compared to a case where control is performed using a commercial transformer method.

[0083] Moreover, in the first embodiment, it is possible to reduce the withstand voltage of the first switching element Q1 to the 24th switching element Q24. In a normal inverter with an H-bridge configuration, IGBTs with a withstand voltage of 600V are often used for the four switching elements. In contrast, in the multilevel inverter 10 with five-level output shown in FIG. 1, MOSFETs with a withstand voltage of 150V can be used for the first switching element Q1 to the 24th switching element Q24. This makes it possible to reduce the on-resistance and increase the switching speed tr / tf, thereby enabling the loss of the switching elements to be reduced. In this case, both the conduction loss and switching loss of the switching elements can be reduced.

[0084] By increasing the switching speed tr / tf, it is possible to increase the switching frequency. For example, if a 600V withstand voltage IGBT is replaced with a 150V withstand voltage MOSFET, the frequency can be increased three times, from 20kHz to 60kHz. This makes it possible to reduce loss, size, weight, and cost of passive components, especially the AC reactors (first output reactor L2 and second output reactor L3). Both copper loss and iron loss in the AC reactor can be reduced.

[0085] Reducing the loss of the switching elements allows for smaller, lighter, and less costly cooling components (e.g., heat sinks). Alternatively, eliminating the need for a fan allows for smaller, lighter, less costly components with longer life. This allows for a smaller, lighter, and less costly housing for the power conversion device 1.

[0086] By reducing the loss of the switching elements and increasing the switching speed tr / tf, it is possible to reduce the power conversion loss, making it possible to increase the self-consumption or sale of the power generated by the solar cell. This allows for economic benefits such as reduced electricity charges or increased electricity sales charges. In addition, since the power conversion loss can be reduced when charging the storage battery from the power system 3 or discharging from the storage battery to a home load, it is also possible to enjoy the economic benefit of reduced electricity charges.

[0087] Fig. 13 is a diagram for explaining the configuration of the power conversion device 1 according to the embodiment 2. The power conversion device 1 according to the embodiment 2 is different from the power conversion device 1 according to the embodiment 1 shown in Fig. 1 in the configuration of the multilevel inverter 10.

[0088] Compared to the multilevel inverter 10 according to the first embodiment, the multilevel inverter 10 according to the second embodiment has a configuration in which the third flying capacitor circuit 13, the fourth flying capacitor circuit 14, the first output circuit 15 and the second output circuit 16 are omitted and an H-bridge circuit 17 is added.

[0089] The H-bridge circuit 17 includes a ninth switching element Q9, a tenth switching element Q10, an eleventh switching element Q11, and a twelfth switching element Q12. Between the midpoint of the first flying capacitor circuit 11 and the midpoint of the second flying capacitor circuit 12, the ninth switching element Q9 and the tenth switching element Q10 are connected in series, and further, the eleventh switching element Q11 and the twelfth switching element Q12 are connected in series. A connection point between the ninth switching element Q9 and the tenth switching element Q10 is connected to a first voltage line (U-phase line) of a single-phase three-wire power distribution line, and a connection point between the eleventh switching element Q11 and the twelfth switching element Q12 is connected to a second voltage line (W-phase line) of the single-phase three-wire power distribution line. The H-bridge circuit 17 can switch the output polarity of the multilevel inverter 10.

[0090] The ninth switching element Q9 and the twelfth switching element Q12 are always on during the positive half cycle of the fundamental wave and always off during the negative half cycle. The tenth switching element Q10 and the eleventh switching element Q11 are always off during the positive half cycle of the fundamental wave and always on during the negative half cycle.

[0091] The multilevel inverter 10 according to the second embodiment shown in FIG. 13 can also output voltages of five levels (+E, +1 / 2E, 0, -1 / 2E, -E) in the same manner as the multilevel inverter 10 according to the first embodiment shown in FIG.

[0092] As described above, according to the second embodiment, the same effects as those of the first embodiment are achieved.

[0093] Fig. 14 is a diagram for explaining the configuration of the power conversion device 1 according to the embodiment 3. The power conversion device 1 according to the embodiment 3 also differs from the power conversion device 1 according to the embodiment 1 shown in Fig. 1 in the configuration of the multilevel inverter 10.

[0094] In the multilevel inverter 10 according to the third embodiment, the third switching element Q3, the fourth switching element Q4, the fifth switching element Q5, the sixth switching element Q6, and the first flying capacitor C1 constitute a first stage of a first flying capacitor circuit. Similarly, the eleventh switching element Q11, the twelfth switching element Q12, the thirteenth switching element Q13, the fourteenth switching element Q14, and the second flying capacitor C2 constitute a second stage of a second flying capacitor circuit.

[0095] The output polarity of the multilevel inverter 10 can be switched by the first switching element Q1, the second switching element Q2, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, the fifteenth switching element Q15, the sixteenth switching element Q16, the seventeenth switching element Q17, the eighteenth switching element Q18, the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, the twenty-second switching element Q22, the twenty-third switching element Q23 and the twenty-fourth switching element Q24.

[0096] The group of the first switching element Q1 and the second switching element Q2 connected to the upper side of the first flying capacitor circuit, the fifteenth switching element Q15 and the sixteenth switching element Q16 connected to the lower side of the second flying capacitor circuit, and the nineteenth switching element Q19, the twentieth switching element Q20, the twenty-first switching element Q21, and the twenty-second switching element Q22 inserted in the path connecting the lower side of the first flying capacitor circuit and the upper side of the second flying capacitor circuit is always on during the positive half cycle of the fundamental wave and always off during the negative half cycle.

[0097] The group of the seventh switching element Q7 and eighth switching element Q8 connected to the lower side of the first flying capacitor circuit, the ninth switching element Q9 and tenth switching element Q10 connected to the upper side of the second flying capacitor circuit, and the seventeenth switching element Q17, eighteenth switching element Q18, twenty-third switching element Q23, and twenty-fourth switching element Q24 inserted in the path connecting the upper side of the first flying capacitor circuit and the lower side of the second flying capacitor circuit are always off during the positive half cycle of the fundamental wave and always on during the negative half cycle.

[0098] The multilevel inverter 10 according to the third embodiment shown in FIG. 14 can also output voltages of five levels (+E, +1 / 2E, 0, -1 / 2E, -E) in the same manner as the multilevel inverter 10 according to the first embodiment shown in FIG.

[0099] As described above, according to the third embodiment, the same effects as those of the first embodiment are achieved.

[0100] The present disclosure has been described above based on the embodiments. The embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of each component and each processing step, and that such modifications are also within the scope of the present disclosure.

[0101] Fig. 15 is a diagram for explaining the configuration of a power conversion device 1 according to a modification of embodiment 1. The power conversion device 1 according to the modification of embodiment 1 is configured such that the first dividing capacitor C5 and the second dividing capacitor C6 are omitted, compared to the power conversion device 1 according to the basic example of embodiment 1 shown in Fig. 1. When the first dividing capacitor C5 and the second dividing capacitor C6 are omitted, the current flowing through the reactor L1 increases out of the current flowing through the O phase.

[0102] In this modified example, the first dividing capacitor C5 and the second dividing capacitor C6 can be omitted, but the current flowing through the reactor L1 increases, so the loss in the reactor L1, the first switch section SW1, and the second switch section SW2 increases. This requires the cooling components (e.g., heat sinks) of the balancing circuit 20 to be larger. On the other hand, in the basic example shown in FIG. 1, the first dividing capacitor C5 and the second dividing capacitor C6 cannot be omitted, but the loss in the reactor L1, the first switch section SW1, and the second switch section SW2 can be reduced, and the cooling components of the balancing circuit 20 can be made smaller.

[0103] In the above-mentioned second and third embodiments, an example in which a single-stage flying capacitor circuit is used has been described, but two or more stages of flying capacitors may be used as in the above-mentioned first embodiment. Also, a flying capacitor type multilevel inverter 10 having a circuit configuration other than those shown in the above-mentioned first to third embodiments may be used.

[0104] The embodiment may be specified by the following items.

[0105] [Item 1] A flying capacitor type multilevel inverter (10) that converts a DC voltage supplied from a DC power source (2) into an AC voltage and outputs the converted AC voltage to a single-phase three-wire distribution line; a first switch section (SW1) and a second switch section (SW2) connected in series between both ends of the DC power supply (2); a reactor (L1) connected between a connection point between the first switch unit (SW1) and the second switch unit (SW2) and a midpoint of the multilevel inverter (10) connected to a neutral line of the single-phase three-wire power distribution line; A balance circuit (20) having a control unit (30) that controls the first switch unit (SW1) and the second switch unit (SW2) so that a voltage at a midpoint of the multilevel inverter (10) becomes half the voltage of the DC power source (2); A power conversion device (1) comprising: This makes it possible to realize a highly efficient and compact power conversion device (1) that is compatible with single-phase three-wire independent output. [Item 2] The balance circuit (20) includes: The power supply further includes a first capacitor (C5) and a second capacitor (C6) connected in series between both ends of the DC power supply (2), The power conversion device (1) described in item 1, characterized in that a connection point between the first capacitor (C5) and the second capacitor (C6) is connected to a midpoint of the multilevel inverter (10) that is connected to a neutral line of the single-phase three-wire distribution line. This makes it possible to reduce the current flowing through the reactor (L1), thereby reducing the loss in the balancing circuit (20). [Item 3] When the voltage of the DC power source (2) is E, The multilevel inverter (10) comprises: Outputting a voltage of five or more levels in a range of +1 / 2E to -1 / 2E between a first voltage line and the neutral line of the single-phase three-wire distribution line; Outputting a voltage of five or more levels in the range of +1 / 2E to -1 / 2E between the second voltage line and the neutral line of the single-phase three-wire distribution line; 3. The power conversion device (1) according to item 1 or 2, characterized in that it outputs voltages of five or more levels in a range from +E to -E between the first voltage line and the second voltage line of the single-phase three-wire distribution line. This makes it possible to reduce the withstand voltage of the switching elements included in the multilevel inverter (10) and to improve the switching speed, thereby contributing to high efficiency and miniaturization of the power conversion device (1). [Item 4] The multilevel inverter (10) comprises: outputting any one of +1 / 2E, +1 / 4E, 0, -1 / 4E, and -1 / 2E between the first voltage line and the neutral line; outputting any one of +1 / 2E, +1 / 4E, 0, -1 / 4E, and -1 / 2E between the second voltage line and the neutral line; 4. The power conversion device (1) according to item 3, wherein any one of +E, +1 / 2E, 0, -1 / 2E, and -E is output between the first voltage line and the second voltage line. According to this, by using a multilevel inverter (10) with five output levels, it is possible to realize high efficiency and miniaturization of the power conversion device (1) while reducing the number of switching elements. [Item 5] The power conversion device (1) has a grid-connected mode and an isolated operation mode, In the independent operation mode, The power conversion device (1) described in item 3 or 4, characterized in that when the power consumption of a load (R1) connected between the first voltage line and the neutral line is different from the power consumption of a load (R2) connected between the second voltage line and the neutral line, a differential current between a current flowing in the first voltage line and a current flowing in the second voltage line flows to the multilevel inverter (10) and the balancing circuit (20) via the neutral line. This makes it possible to switch between a single-phase three-wire grid-connected mode and a single-phase three-wire isolated operation mode. [Item 6] The multilevel inverter (10) has a first leg including a plurality of switching elements (Q1-Q8) and a second leg including a plurality of switching elements (Q9-Q16), In the independent operation mode, the control unit (30) controls a plurality of switching elements (Q1-Q8) included in the first leg so that a voltage between the first voltage line and the neutral line becomes half of a voltage between the first voltage line and the second voltage line; The power conversion device (1) described in item 5, characterized in that a plurality of switching elements (Q9-Q16) included in the second leg are controlled so that a voltage between the second voltage line and the neutral line becomes half of a voltage between the first voltage line and the second voltage line. With this, even if there is an imbalance between the load connected between the first voltage line and the neutral line and the load connected between the second voltage line and the neutral line, a stable voltage can be supplied to each of the loads. [Item 7] In the grid-connected mode, 7. The power conversion device (1) according to item 5 or 6, wherein the control unit (30) controls a plurality of switching elements (Q1-Q24) included in the multilevel inverter (10) so that an output current of the power conversion device (1) maintains a target current value. This makes it possible to provide a stable reverse power flow to the power grid. [Item 8] In the independent operation mode, the control unit (30) controls the first switch unit (SW1) and the second switch unit (SW2) included in the balance circuit (20) so that a voltage at a midpoint of the multilevel inverter (10) becomes half a voltage of the DC power supply (2); In the grid-connected mode, The power conversion device (1) according to any one of items 5 to 7, wherein the control unit (30) stops operations of the first switch unit (SW1) and the second switch unit (SW2). This makes it possible to supply a stable voltage to the load in the isolated operation mode, and to reduce unnecessary loss in the balancing circuit (20) in the grid-connected mode. [Explanation of symbols]

[0106] REFERENCE SIGNS LIST 1 power conversion device, 2 DC power supply, 3 power system, 10 multilevel inverter, 11-14 flying capacitor circuit, 15-16 output circuit, 17 H-bridge circuit, 20 balancing circuit, 30 control unit, 41-43 voltage sensors, 51-55 current sensors, R1-R3 load, Q1-Q24 switching elements, C1-C8 capacitors, L1-L3 reactor, SW1-SW2 switch unit, RY1-RY2 relay.

Claims

1. A flying capacitor type multilevel inverter that converts a DC voltage supplied from a DC power source into an AC voltage and outputs the converted AC voltage to a single-phase three-wire distribution line; a first switch unit and a second switch unit connected in series between both ends of the DC power supply; a reactor connected between a connection point between the first switch unit and the second switch unit and a midpoint of the multilevel inverter connected to a neutral line of the single-phase three-wire power distribution line; A balancing circuit having a control unit that controls the first switch unit and the second switch unit so that a voltage at a midpoint of the multilevel inverter becomes half a voltage of the DC power supply; Equipped with When the voltage of the DC power supply is E, The multilevel inverter comprises: Outputting a voltage of five or more levels in a range of +1 / 2E to -1 / 2E between a first voltage line and the neutral line of the single-phase three-wire distribution line; Outputting a voltage of five or more levels in a range of +1 / 2E to -1 / 2E between a second voltage line and the neutral line of the single-phase three-wire distribution line; A voltage of five or more levels in a range from +E to −E is output between the first voltage line and the second voltage line of the single-phase three-wire distribution line; The multilevel inverter has a first leg including a plurality of switching elements and a second leg including a plurality of switching elements, This power conversion device has a grid-connected mode and an isolated operation mode. In the independent operation mode, the control unit controls a plurality of switching elements included in the first leg so that a voltage between the first voltage line and the neutral line becomes half of a voltage between the first voltage line and the second voltage line; controlling a plurality of switching elements included in the second leg so that a voltage between the second voltage line and the neutral line becomes half of a voltage between the first voltage line and the second voltage line; A power conversion device characterized in that, when the power consumption of a load connected between the first voltage line and the neutral line is different from the power consumption of a load connected between the second voltage line and the neutral line, a differential current between a current flowing in the first voltage line and a current flowing in the second voltage line flows to the multilevel inverter and the balancing circuit via the neutral line.

2. The balance circuit includes: a first capacitor and a second capacitor connected in series across the DC power supply; 2. The power conversion device according to claim 1, wherein a connection point between the first capacitor and the second capacitor is connected to a midpoint of the multilevel inverter that is connected to a neutral line of the single-phase three-wire distribution line.

3. The multilevel inverter comprises: outputting any one of +1 / 2E, +1 / 4E, 0, -1 / 4E, and -1 / 2E between the first voltage line and the neutral line; outputting any one of +1 / 2E, +1 / 4E, 0, -1 / 4E, and -1 / 2E between the second voltage line and the neutral line; 2. The power conversion device according to claim 1, wherein any one of +E, +1 / 2E, 0, -1 / 2E, and -E is output between the first voltage line and the second voltage line.

4. In the grid-connected mode, The power conversion device according to claim 1 , wherein the control unit controls a plurality of switching elements included in the multilevel inverter so that an output current of the power conversion device maintains a target current value.

5. In the independent operation mode, the control unit controls the first switch unit and the second switch unit included in the balancing circuit so that a voltage at a midpoint of the multilevel inverter becomes half a voltage of the DC power supply; In the grid-connected mode, The power conversion device according to claim 1 , wherein the control unit stops operations of the first switch unit and the second switch unit.

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