Imaging device, control method and program thereof

Abstract

To provide a technique to perform correction of an image with high accuracy even in high-frame rate photography.SOLUTION: An imaging apparatus has an image pick-up device, a correction circuit that has a first memory and a second memory in which while one is in a writing mode through transfer, the other is in a reading mode, and based on a set of correction values read out from the memory set to the reading mode, corrects pieces of pixel data in image data obtained through the imaging performed by the image pick-up device, and a storage unit that stores the plurality of sets of correction values used in the correction circuit. When a drive period for obtaining a plurality of images picked up by the image pick-up device is shorter than the time for a transfer unit to transfer the sets of correction values, the imaging apparatus maintains the state of reading and writing of the first memory and second memory in a period until the transfer of a set of new correction values is completed, and at the timing of the drive period immediately after the completion of the transfer, switches the memory in which storage of the set of new correction values is completed to one for reading, and the other to one for writing.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a technique for correcting an image captured by an imaging device. [Background technology]

[0002] As imaging devices become more sophisticated, image capture is becoming increasingly faster in frame rate. In such high frame rate capture, exposure control different from conventional methods may be required from various standpoints, and various techniques have been proposed so far.

[0003] For example, Patent Document 1 discloses a method for switching the tracking speed of exposure control depending on the frame rate at which a high frame rate moving image is played back when continuous images are captured for the moving image. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-156886 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, in recent years, imaging devices have become more sophisticated, making it possible to shoot at higher frame rates. A higher frame rate means that the processing time per frame becomes shorter. As a result, various processes that were previously performed within one frame no longer fit into the time of one frame. In particular, since it takes time to transmit correction values ​​used in image correction circuits to improve image quality, the time required for transmission can sometimes be longer than the period of the shooting frame rate. In such cases, a mismatch can occur between the correction values ​​and the readout settings of the imaging device, resulting in degradation of image quality.

[0006] The present invention has been made in consideration of such problems, and aims to provide a technique that enables image correction with high precision even in high frame rate shooting. [Means for solving the problem]

[0007] In order to solve this problem, for example, an imaging device according to the present invention has the following configuration. An image sensor that converts an optical image of a subject into an electrical signal; Multiple correction values but memory was done A memory circuit; Based on the correction value One frame read from the image sensor a correction circuit for correcting the captured image data; a first memory and a second memory built in the correction circuit; The correction value stored in the memory circuit The correction value is read out. a transfer circuit for transferring the signal to the correction circuit; a write circuit that writes the correction value transferred by the transfer circuit into either the first memory or the second memory; The transfer circuit From the memory circuit to the correction circuit The transfer time of the correction value is 1 frame. One frame period for reading out photographed image data from the image sensor and performing correction processing by the correction circuit. If it is longer than 1. Multiple Frames Mu period In between Leave, The write circuit The second correction value read from the memory circuit First memo To As you write, The correction circuit Stored in No. 1 Read out the correction value of The first correction value is used to correct the first frame of the plurality of frames read out from the image sensor during each frame period of the first plurality of frame periods. Correcting the captured image data Control, In a second multiple frame period following the first multiple frame period, the writing circuit writes the third correction value read from the storage circuit into the second memory, and the correction circuit reads out the second correction value stored in the first memory and corrects the captured image data of the multiple frames read out from the image sensor in each frame period of the second multiple frame period using the read second correction value. and a control unit that controls the Effect of the Invention

[0008] According to the present invention, it is possible to perform image correction with high precision even in high frame rate shooting. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram showing the configuration of an imaging apparatus according to an embodiment. [Diagram 2] FIG. 2 is a block diagram of an image sensor according to an embodiment. [Diagram 3] FIG. 2 is a block diagram of an image correction circuit according to the embodiment. [Figure 4] 4 is a timing chart showing a shooting operation and a correction operation in the image sensor of the embodiment. [Diagram 5] FIG. 11 is a block diagram showing the configuration of an imaging apparatus according to a modified example. [Figure 6] 5 is a flowchart showing a process for switching an operation mode in the embodiment. [Figure 7] 11 is a flowchart showing a setting process for switching between image processing for a plurality of images. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] [First embodiment] Fig. 1 is a block diagram of an imaging device according to a first embodiment. In Fig. 1, a first lens 100 is disposed at the tip of an imaging optical system 104. An aperture 101 adjusts the aperture diameter to adjust the amount of light during imaging. A second lens 102 and a third lens 103 are driven by a focus actuator 119 (described later) and move forward and backward in the optical axis direction to adjust the focus of the imaging optical system 104.

[0012] The focal plane shutter 105 has a function of adjusting the exposure time when capturing a still image. However, when an electronic shutter using slit rolling readout of the image sensor 107 is used to adjust the exposure time, the exposure time is not adjusted. The optical low-pass filter 106 is used to reduce false colors and moire in the captured image. The image sensor 107 photoelectrically converts the optical image of the subject formed by the image capturing optical system 104 into an electrical signal. The image sensor 107 also has an electronic shutter function and can capture images using slit rolling readout.

[0013] The DSP 108 receives an image signal and processes the image. In addition to image processing, the DSP 108 also performs calculations of information used to drive the focus lenses (second lens 102, third lens 103) based on information from the image sensor 107. The data transfer circuit 109 is a circuit that transfers correction values ​​stored in the RAM 110 to the image sensor 107 under the control of a CPU 111 (described later).

[0014] The RAM 110 functions as an image data storage means for storing image data processed by the DSP 108, as a correction value storage means for transfer by the data transfer circuit 109, and further as a work memory when the CPU 111 described below operates. Note that when one frame's worth of correction values ​​is one set, the RAM 110 stores multiple sets of correction values.

[0015] In this embodiment, these functions are realized using the RAM 110, but other types of memory may be used as long as the access speed is fast enough to cause no operational problems. In this embodiment, the RAM 110 is disposed outside the DSP 108 and the CPU 111, but some or all of the functions may be built into the DSP 108 and the CPU 111.

[0016] The CPU 111 performs overall control of the operation of the imaging device. To this end, the CPU 111 executes a program stored in a ROM 116 in order to control each unit of the imaging device. The CPU 111 can control reading from the imaging element 107 by making various settings to the imaging element. The parameters that the CPU 111 can change by setting the imaging element 107 include at least settings related to ISO sensitivity and settings related to accumulation time.

[0017] Furthermore, the CPU 111 communicates with a timing pulse generating circuit 112 and controls the generation timing of various timing pulses for controlling the operation of the image sensor 107. The timing pulse generating circuit 112 supplies the generated synchronization signal to the image sensor 107. This controls the operation timing of the image sensor 107.

[0018] The CPU 111 also has a function of controlling a focus actuator 119 using the calculation results output from the DSP 108, thereby adjusting the focus of the photographing optical system 104. The CPU 111 also has a function of controlling an aperture actuator 121 via an aperture drive circuit 120, thereby adjusting the aperture diameter of the photographing optical system 104. The CPU 111 can perform control related to ISO sensitivity settings and accumulation time for the image sensor 107 described above, and can perform control related to the adjustment of the aperture diameter for the photographing optical system 104. In this way, the CPU 111 is in charge of controlling the exposure of the imaging device.

[0019] The display unit 113 displays still images and moving images processed by the DSP 108, as well as various menus. By using the displayed moving image as a viewfinder, the user can perform framing to adjust the shooting range for still image shooting and moving image shooting. In addition to a rear display, an electronic viewfinder (EVF) is known as the display unit 113. Note that, although FIG. 1 shows one display unit 113 as a display configuration, a configuration equipped with both a device rear display and an EVF may also be used.

[0020] The operation unit 114 is an operation member such as a button or a lever. The operation unit 114 may also include a touch panel. The user gives various instructions to the CPU 111 through the operation unit 114. Naturally, these instructions include the user's settings of imaging conditions and shooting instructions. The CPU 111 performs control according to the instructions from the user.

[0021] The recording medium 115 is a removable recording medium for recording still image data and video data. The recording medium 115 is typically a removable storage medium such as an SD memory card, but may be a recording medium fixed to the device. The ROM 116 stores programs that the CPU 111 loads and executes to control the operation of each unit.

[0022] A shutter driving circuit 117 drives and controls the focal plane shutter 105. A focus driving circuit 118 functions as a focal position changing means for changing the focal position of the photographing optical system 104, and controls a focus actuator 119 based on the output of the CPU 111 to drive the focus lenses (second lens 102, third lens 103) forward and backward in the optical axis direction to perform focus adjustment. An aperture driving circuit 120 controls an aperture actuator 121 to control the degree of opening (F value) of the aperture 101.

[0023] The image sensor 107 of this embodiment will be described with reference to FIGS.

[0024] First, Fig. 2(a) shows the circuit configuration of a unit pixel 206. A photodiode 200 (hereinafter, PD200) is an element that constitutes the unit pixel 206 under a microlens, and constitutes a photoelectric conversion section. A transfer switch 201 is a switch controlled by a signal φtx. By setting the value of the signal φtx to High (hereinafter, H), the photocharge accumulated in the PD200 can be transferred to a floating diffusion section (FD202).

[0025] The reset switch 203 is a switch controlled by a signal φres to initialize the FD 202. The pixel reset operation is realized by setting both the signal φtx and the signal φres to H, thereby setting both the PD 200 and the FD 202 to the power supply voltage (VDD). The pixel amplifier transistor 204 is connected to a constant current source 209 (described later) via a select switch 205 and a vertical output line 208 (described later).

[0026] When the value of the input signal φsel of the select switch 205 becomes H, the pixel amplifier transistor 204 is connected to a constant current source 209 to form a pixel amplifier. Since the FD 202 is connected to this pixel amplifier, the charge transferred from the PD 200 to the FD 202 is converted by the pixel amplifier into a voltage value according to the amount of charge, and is output as a pixel signal to a vertical output line 208 (see FIG. 2(b)).

[0027] Next, a circuit block diagram of the image sensor 107 will be described with reference to Fig. 2(b). The pixel array 207 has a structure in which a plurality of unit pixels 206 are arranged in a matrix. Specifically, (m+1) unit pixels 206 are arranged in the horizontal direction and (n+1) unit pixels 206 are arranged in the vertical direction. Here, both m and n are natural numbers.

[0028] The drive pulse generation circuit 210 generates pulses for performing reset operations and read operations of the unit pixels 206. The generated pulses are supplied to a pixel drive circuit 212. The row selection circuit 211 selects a pixel row to which the pulses generated by the drive pulse generation circuit 210 are supplied, and sets the selected pixel row in the pixel drive circuit 212. The pixel drive circuit 212 supplies the pulses generated by the drive pulse generation circuit 210 to the pixel row set by the row selection circuit 211.

[0029] The pixel signals are output to the vertical output lines 208 for each pixel row in response to pulses supplied from the pixel drive circuit 212. The constant current source 209 forms a source follower circuit in combination with the pixel amplifier transistor 204. The AD conversion circuit (hereinafter, ADC 213) converts the analog output output to the vertical output line 208 into a digital value corresponding to the output.

[0030] The ADC213 is manufactured with AD conversion circuits that are identical in circuit configuration for each column. However, even circuits with the same circuit configuration have different characteristics due to manufacturing variations in transistors. This variation in characteristics for each pixel column appears in the image as column offset variation. In addition, this column offset variation changes depending on the state in which AD conversion is performed, so the state changes when the ISO sensitivity is changed.

[0031] In order to correct this variation in column offset, the pixel signals converted into digital values ​​by the ADC 213 are selected in order by the horizontal scanning circuit 214 and transferred to an image correction circuit 215. The image correction circuit 215 receives the column offset correction values ​​stored in the RAM 110 via the data transfer circuit 109, and performs a correction process on the pixel signals using the correction values.

[0032] Such correction of pixel signals reduces the effect on the image of variations in column offset caused by manufacturing variations in transistors, making it possible to acquire images with good image quality. Details of image correction circuit 215 will be described in detail with reference to Fig. 3. The pixel signals processed by image correction circuit 215 are output to the outside of image sensor 107 via output unit 216.

[0033] In this embodiment, the pixel driving circuit 212, the ADC 213, and the image correction circuit 215 are built into the image sensor 107, but they may be provided on a chip separate from the image sensor 107. In this embodiment, the correction values ​​are set to ISO sensitivity-specific correction values ​​for correcting variations in column offset, but the types of correction values ​​are not limited to this. For example, correction values ​​for correcting variations in column gain or any other correction values ​​may be used.

[0034] Here, it is assumed that the transfer time of the column offset correction value for one frame (all lines) by the data transfer circuit 109 from the RAM 110 to the image correction circuit 215 of the image sensor 107 is 4.9 ms (depending on the specifications of the transfer bus, the resolution of the image sensor, etc.). Also, it is assumed that the user selects a mode for shooting at 240p (240 frames per second) as a representative example of a high frame rate via the operation unit 114. In this case, the drive period for shooting is 1 / 240 seconds, so the time required for correction processing for one frame is 4.17 ms (=1 / 240 seconds).

[0035] Now, assume that a user has changed the ISO sensitivity, or the ISO sensitivity has been changed in the automatic exposure determination process, and thus it becomes necessary to transfer a new correction value. In this case, the transfer of the correction value will not be in time for the correction process. In this embodiment, even in such a case where "the time required for the transfer of the correction value is greater than the time required for the correction process of one frame", it is possible to switch the correction process appropriately. For this reason, in the embodiment, the correction value is transferred over a plurality of frames, and once the transfer is completed, it is possible to start the correction process using the corrected correction value.

[0036] In order to realize the above processing, the image correction circuit 215 will be described in detail with reference to Fig. 3. Note that the same reference numerals are used for the components already described in other drawings, and the description thereof will be omitted.

[0037] The image correction circuit 215 has a data receiving circuit 300 that receives the column offset correction value (data indicating a positive or negative signed value) transmitted from the data transfer circuit 109. The data receiving circuit 300 stores the received column offset correction value in either the first RAM 302 or the second RAM 303 through a router 301. This router 301 is controlled by the CPU 111, and can switch the write target at any timing.

[0038] Both the first RAM 302 and the second RAM 303 have a capacity capable of storing column offset correction values ​​for one frame (all lines), and when one is in a write mode, the other is in a read mode.

[0039] The selector 304 is connected to both the first RAM 302 and the second RAM 303, and can connect either of the two RAMs to the correction processing circuit 305. The correction processing circuit 305 reads out a column offset correction value from either the first RAM 302 or the second RAM 303 selected by the selector 304, and uses the column offset correction value to correct column offset variations in pixel signals.

[0040] Since the column offset variation is the offset variation for each pixel column, correction is performed for each pixel column. When certain pixel data is input to the correction processing circuit 305 from the AD conversion circuit 213, the correction processing circuit 305 reads the corresponding column offset correction value from the RAM selected by the selector 304, and performs addition and subtraction processing on the pixel data.

[0041] Next, the shooting operation and correction operation in the image sensor 107, as well as the timing of transmission of the column offset correction value, will be explained using the timing chart in Fig. 4. In the image sensor 107, the shooting operation is started upon receiving a shooting instruction issued by, for example, a user pressing a shooting start button on the operation unit 114. Note that the diagonal lines in the figure represent readout from the image sensor.

[0042] At timing t400, when the timing pulse generation circuit 112 asserts the vertical synchronization signal (VD), the image sensor 107 starts reading out pixel signals. At the same time as starting to read out the pixel signals, the image correction circuit 215 starts correcting the pixel data. At this time, the selector 304 selects the first RAM 302. Therefore, the correction processing circuit 305 corrects the pixel data using the column offset correction value already stored in the first RAM 302.

[0043] At timing t401, the data transfer circuit 109 reads out the column offset correction values ​​from the RAM 110 and starts transmitting them to the data receiving circuit 300 of the image correction circuit 215. At this time, the router 301 selects the second RAM 303. Therefore, the column offset correction values ​​received by the data receiving circuit 300 are stored in the second RAM 303.

[0044] In this way, a configuration can be adopted in which a RAM that stores the column offset correction values ​​used for correction and a RAM that rewrites the stored data with the column offset correction values ​​from the data receiving circuit are separated, allowing the data receiving circuit 300 to receive the column offset correction values ​​without destroying the column offset correction values ​​used for image correction.

[0045] At timing t402, the image correction circuit 215 performs communication for the operation of the image sensor 107 for the next frame. When the timing pulse generation circuit 112 asserts VD at t403, the image sensor 107 starts reading out pixel signals for the next frame. At this time, the column offset correction value that started to be transmitted at timing t401 has not yet been transmitted. Therefore, the selector 304 continues to select the first RAM 302.

[0046] The correction processing circuit 305 corrects the pixel signal using the column offset correction value stored in the first RAM 302. When controlled in this manner, only the column offset correction value stored in the first RAM 302 can be applied to the readout started at timing t403. Therefore, if the ISO sensitivity corresponding to the column offset correction value stored in the first RAM 302 and the ISO sensitivity of the readout started at timing t403 do not correspond correctly, the image cannot be corrected correctly. Therefore, the ISO sensitivity is not changed in communication with the image sensor 107 performed at timing t402.

[0047] At timing t403, CPU 111 changes various parameters of image sensor 107. This setting is not effective at the time of setting, but is set to be effective at timing t406 when VD is next asserted. Reception of the column offset correction value is completed at timing t405, which is the time before VD is next asserted. Then, it becomes possible to correct the image with the column offset correction value stored in second RAM 303.

[0048] The CPU 111 changes the ISO sensitivity so that the setting value set at timing t404 corresponds to the column offset correction value stored in the second RAM 303 from timing t401 to t405. Furthermore, the CPU 111 switches the router 301 from the second RAM 303 to the first RAM 302 at timing t406. Also, at this timing t406, the CPU 111 switches the selector 304 from the first RAM 302 to the second RAM 303. As a result, the write / read modes of the first RAM 302 and the second RAM 303 are switched.

[0049] By controlling in this manner, it becomes possible to switch the parameters of the image sensor 107 from the frame read out from timing t406 without causing a mismatch between the ISO sensitivity corresponding to the column offset correction value and the ISO sensitivity setting set in the image sensor 107.

[0050] Also, with regard to the storage of the column offset correction value, the column offset correction value that starts to be received from the following timing t407 is switched to be stored in the first RAM 302. Therefore, it is possible to continue receiving data without destroying the correction value being used. Similarly, the column offset correction value that starts to be transmitted from timing t407 can be reflected from timing t409.

[0051] The correction value may be switched only when it is necessary to switch the correction value, but the control may be simplified by periodically switching the correction value even when it is not necessary to switch the correction value. In this case, the correction value is updated in a second cycle from timing t401 to t407, which is longer than the time interval from timing t400 to t403, which is the imaging cycle. In addition, the setting in the imaging element 107 can also be performed in the second cycle, which is the time interval from timing t404 to t408. In order not to destroy the correction value being transmitted, the second cycle is controlled to be longer than the time from timing t401 to t405, which is the time required to transmit the correction value.

[0052] In this embodiment, a change in the ISO sensitivity setting affects the image correction value type, but does not affect the image correction value types of the accumulation time and the aperture diameter. However, in order to control the exposure, it is necessary to appropriately control these three parameters simultaneously. Therefore, the accumulation time and the aperture diameter are controlled so that they are changed only when the ISO sensitivity setting is changed.

[0053] As described above, according to this embodiment, when the imaging interval is shorter than the transfer time of the correction value for one frame, it is possible to appropriately maintain and switch between writing of correction values ​​to two memories (first RAM and second RAM) and reading of correction values ​​basically at a timing based on the vertical synchronization signal. As a result, even when the frame rate is high, the correction values ​​are appropriately read in the correction process, and a high-quality image can be obtained.

[0054] In the above embodiment, an example in which the image correction circuit 215 is built in the imaging element 107 has been described, but the image correction circuit 215 may be provided outside the imaging element 107. FIG. 5 is a block diagram showing a case in which a circuit equivalent to the image correction circuit 215 is provided outside the imaging element 107. In FIG. 5, the image correction circuit 215 is configured to be built in the DSP 500. In this case, the data transfer circuit 109 is connected to the DSP 500. The DSP 500 also has the function of the DSP 108 in the first embodiment.

[0055] In the above embodiment, for ease of understanding, the specific imaging conditions are described as follows: the time required to transfer correction values ​​for one frame is 4.9 ms, and the frame rate during shooting is 240 fps. In other words, under these conditions, the correction values ​​are transferred using a period of two frames, and the router 301 and the selector 304 are switched according to the vertical synchronization signal immediately after the transfer is completed.

[0056] During the two-frame period (=4.17×2 ms) during which the correction values ​​are transferred, the write / read mode of the first RAM 302 and the second RAM 303 is maintained, and the write / read mode is switched based on the vertical synchronization signal immediately after the transfer is completed.

[0057] The time required to transfer correction values ​​for one frame is defined as "T" (seconds), and the frame rate set by the user is defined as "F" (fps). In this case, the CPU 111 obtains the smallest natural number n that satisfies the following formula. T < n / F Then, the CPU 111 maintains the write / read mode of the first RAM 302 and the second RAM 303 for a period of n frames (=n / F) and transfers (writes) the correction value to the RAM in the write mode. Then, the CPU 111 switches the router 301 and the selector 304 and switches the write / read mode of the first RAM 302 and the second RAM 303 in accordance with the vertical synchronization signal immediately after the transfer is completed, and sets the imaging conditions for the imaging element 107.

[0058] [Second embodiment] In the first embodiment, a method for controlling the readout image and the correction value to match each other even when an image is captured at a high frame rate is shown. However, according to this method, the frame rate for tracking the luminance change is lower than the image capture frame rate.

[0059] If the shooting frame rate is sufficiently high, it is still possible to adequately track changes in the brightness of the subject, but even at a general shooting frame rate such as 30 fps, if the method shown in the first embodiment is applied, it will not be possible to track changes in the brightness of the subject. Therefore, in the second embodiment, a method of switching the operation of the imaging device depending on the frame rate is disclosed.

[0060] In addition, for the multiple images obtained in this manner, several types of image data can be generated by changing the image processing method in the DSP 108. Therefore, in this embodiment, switching between the image processing of multiple images will also be introduced.

[0061] FIG. 6 is a flowchart showing a method for switching the operation mode in accordance with the frame rate setting.

[0062] In S600, the CPU 111 starts setting the shooting mode. In S601, the CPU 111 accepts a frame rate setting made by the user via the operation unit 114.

[0063] In S602, the CPU 111 determines whether the image capturing period (the reciprocal of the frame rate) at the set frame rate is shorter than the time required for transmitting the correction value. Note that, before reaching this step, the time required for transmitting the correction value and the image capturing period for each frame rate may be calculated.

[0064] In this case, in S602, the CPU 111 determines whether the set frame rate is equal to or higher than a predetermined frame rate, and performs control so that if the set frame rate is equal to or higher than the predetermined frame rate, the result transitions to Yes, and if the set frame rate is lower than the predetermined frame rate, the result transitions to No.

[0065] In S602, if the CPU 111 determines that the image capturing cycle at the set frame rate is shorter than the time required for transmitting the correction values, the CPU 111 transitions the process to S603.

[0066] In S603, the CPU 111 loads a program for performing the operations shown in the first embodiment, and transitions to completion of the shooting mode setting in S605.

[0067] On the other hand, if the CPU 111 determines in S602 that the image capturing cycle at the set frame rate is longer than the time required for transmitting the correction values, the CPU 111 transitions the process to S604.

[0068] In S604, the CPU 111 loads a program for performing a normal operation different from the operation shown in the first embodiment. The normal operation here is an operation in which the ISO sensitivity setting of the image sensor is changed for each frame. When the program loading is completed, the process proceeds to completion of the shooting mode setting in S605.

[0069] FIG. 7 is a flow chart showing the setting process when a plurality of images are captured in succession.

[0070] In S700, the CPU 111 starts setting the shooting mode.

[0071] In S701, the CPU 111 accepts a mode setting made by the user via the operation unit 114.

[0072] In S702, CPU 111 determines whether the mode set by the user is the still image mode. If CPU 111 determines that the mode set by the user is the still image mode, CPU 111 transitions the process to S703. If not (if the mode is the moving image mode), CPU 111 transitions the process to S706.

[0073] When the process moves to S703, the CPU 111 judges whether or not the continuous shooting mode is set. When it is judged that the continuous shooting mode is set, the CPU 111 moves the process to S704. When it is not set (when the combination mode is set), the CPU 111 moves the process to S705.

[0074] When the process transitions to S704, the CPU 111 loads a program for a continuous shooting mode that stores the obtained images of multiple frames as multiple still images as they are, and transitions to the completion of the shooting mode setting in S707. Note that in the continuous shooting mode, the control is performed so that the above-mentioned correction value can be changed even during continuous shooting. However, depending on the relationship between the continuous shooting speed (frame rate) and the time required to transfer the correction value, the control is performed so that the correction value is not changed.

[0075] When the process moves to S705, the CPU 111 loads a program for a synthesis mode that generates one synthetic image from the obtained images of the multiple frames, and moves to completion of the shooting mode setting in S707. Note that in this synthesis mode, control is performed so that the above-mentioned correction value is not changed during the period in which the multiple still images to be synthesized are captured.

[0076] Also, when the process transitions to S706, the CPU 111 loads a program for a moving image mode that handles the obtained images of multiple frames as a moving image, and transitions to completion of shooting mode setting in S707. Note that in the moving image mode, control is performed so that the above-mentioned correction value can be changed, and control is performed so that the correction value is not changed depending on the relationship between the frame rate and the time required for transferring the correction value.

[0077] As described above, according to the second embodiment, by following the flowchart in Fig. 6, it is possible to switch the ISO sensitivity setting every several frames at a high frame rate and to switch the correction value and the image sensor setting appropriately. Also, at a low frame rate, it is possible to switch the ISO sensitivity setting every frame and make the ISO sensitivity setting follow the change in the brightness of the subject.

[0078] Furthermore, by following the flow chart of FIG. 7, it becomes possible to process a plurality of images acquired by the method shown in the first embodiment as desired by the user.

[0079] (Other Examples) The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0080] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0081] 107: image sensor, 109: data transfer circuit, 111: CPU, 110: RAM, 215: correction circuit

Claims

1. An image sensor that converts an optical image of a subject into an electrical signal; a memory circuit in which a plurality of correction values ​​are stored; a correction circuit that corrects one frame of photographed image data read from the image sensor based on the correction value; a first memory and a second memory built in the correction circuit; a transfer circuit that reads out the correction value stored in the memory circuit and transfers the read correction value to the correction circuit; a write circuit that writes the correction value transferred by the transfer circuit into either the first memory or the second memory; When a time required for the transfer circuit to transfer the correction value from the memory circuit to the correction circuit is longer than a one-frame period required for reading out one frame of photographed image data from the image sensor and performing a correction process by the correction circuit, during a first plurality of frame periods, the write circuit writes the second correction value read from the storage circuit into the first memory, and the correction circuit reads the first correction value stored in the second memory, and controls the correction circuit to correct the captured image data of the plurality of frames read from the image sensor during each frame period of the first plurality of frame periods using the read first correction value; and a control unit that controls the writing circuit to write a third correction value read from the memory circuit into the second memory during a second multiple frame period following the first multiple frame period, and the correction circuit to read the second correction value stored in the first memory and to correct the captured image data of multiple frames read from the imaging element during each frame period of the second multiple frame period using the read second correction value.

2. The image pickup apparatus according to claim 1 , wherein the plurality of correction values ​​stored in the memory circuit correspond to different ISO sensitivities.

3. 2. The imaging apparatus according to claim 1, wherein the correction circuit is incorporated in an imaging element.

4. 4. The imaging device according to claim 1, wherein the control unit performs the control when a moving image is acquired.

5. 4. The imaging apparatus according to claim 1, wherein the control unit performs the control when acquiring images in a continuous shooting mode.

6. 4. The imaging device according to claim 1, wherein the control unit does not perform the above control when acquiring images of a plurality of frames used to generate one composite image.

7. An image sensor that converts an optical image of a subject into an electrical signal; a memory circuit in which a plurality of correction values ​​are stored; a correction circuit that corrects one frame of photographed image data read from the image sensor based on the correction value; a first memory and a second memory built in the correction circuit; a transfer circuit that reads out the correction value stored in the memory circuit and transfers the read correction value to the correction circuit; a writing circuit that writes the correction value transferred by the transfer circuit into either the first memory or the second memory, When a time required for the transfer circuit to transfer the correction value from the memory circuit to the correction circuit is longer than a one-frame period required for reading out one frame of photographed image data from the image sensor and performing a correction process by the correction circuit, during a first plurality of frame periods, the write circuit writes the second correction value read from the storage circuit into the first memory, and the correction circuit reads the first correction value stored in the second memory, and controls the correction circuit to correct the captured image data of the plurality of frames read from the image sensor during each frame period of the first plurality of frame periods using the read first correction value; In a second multiple frame period following the first multiple frame period, the writing circuit writes the third correction value read from the storage circuit into the second memory, and the correction circuit reads the second correction value stored in the first memory and corrects the captured image data of the multiple frames read from the image sensor in each frame period of the second multiple frame period using the read second correction value.

23. A method for controlling an imaging apparatus comprising the steps of:

8. A program for causing a computer to execute the imaging apparatus control method according to claim 7 by reading and executing the program.

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