APPARATUS AND METHOD FOR REAL-TIME GRAPHICS PROCESSING USING LOCAL AND CLOUD-BASED GRAPHICS PROCESSING RESOURCES - Patent application

Abstract

To provide an apparatus and method for scheduling threads on local and remote processing resources.SOLUTION: A scheduler identifies a first subset of the threads for execution on a local graphics processor and a second subset of the threads for execution on a virtualized representation of a local processor, and schedules the first subset of threads on the local graphics processor and the second subset of the threads by transmitting the threads or a representation thereof to cloud-based processing resources associated with the virtualized representation of the local processor. The local graphics processor combines first results of executing the first subset of threads on the local graphics processor with second results of executing the second subset of threads on the cloud-based processing resources to render an image frame.SELECTED DRAWING: None

Description

[Technical field]

[0001] The present invention relates generally to the field of graphics processing, and more particularly to an apparatus and method for real-time graphics processing using local and cloud-based graphics processing resources. [Background technology]

[0002] Although remote graphics servers can render image frames much faster than a typical user's gaming device, there are other challenges that can affect the real-time gaming user experience, such as network-induced latency and quality variations due to data compression. Certain types of games, such as augmented reality (AR) and virtual reality (VR) games, require high-performance networking platforms to achieve the necessary latency.

[0003] [Brief description of the drawings]

[0004] A better understanding of the present invention can be obtained from the following detailed description taken in conjunction with the following drawings.

[0005] [Figure 1] FIG. 1 is a block diagram of one embodiment of a computer system including a processor having one or more processor cores and a graphics processor.

[0006] [Figure 2A] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2B] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2C]FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor. [Figure 2D] FIG. 1 is a block diagram of one embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0007] [Figure 3A] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. [Figure 3B] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. [Figure 3C] FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0008] [Figure 4] FIG. 2 is a block diagram of one embodiment of a graphics processing engine of a graphics processor.

[0009] [Figure 5A] FIG. 2 is a block diagram of another embodiment of a graphics processor. [Figure 5B] FIG. 2 is a block diagram of another embodiment of a graphics processor.

[0010] [Figure 6] FIG. 2 is a block diagram of thread execution logic including an array of processing elements.

[0011] [Figure 7] 1 illustrates a graphics processor execution unit instruction format according to one embodiment.

[0012] [Figure 8] FIG. 2 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a renderer output pipeline.

[0013] [Figure 9A] FIG. 2 is a block diagram illustrating a graphics processor command format according to one embodiment.

[0014] [Figure 9B] FIG. 2 is a block diagram illustrating a graphics processor command sequence according to one embodiment.

[0015] [Figure 10] 1 illustrates an exemplary graphics software architecture for a data processing system according to one embodiment.

[0016] [Figure 11A] 1 illustrates an exemplary IP core development system that may be used to manufacture integrated circuits for performing operations according to one embodiment. [Figure 11B] 1 illustrates an exemplary IP core development system that may be used to manufacture integrated circuits for performing operations according to one embodiment. [Figure 11C] 1 illustrates an exemplary IP core development system that may be used to manufacture integrated circuits for performing operations according to one embodiment. [Figure 11D] 1 illustrates an exemplary IP core development system that may be used to manufacture integrated circuits for performing operations according to one embodiment.

[0017] [Figure 12] 1 illustrates an exemplary system-on-chip integrated circuit that can be manufactured using one or more IP cores, according to one embodiment.

[0018] [Figure 13]1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores.

[0019] [Figure 14] 1 illustrates an additional exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores.

[0020] [Figure 15A] 1 illustrates an embodiment of an architecture that includes a virtualized or "ghost" GPU. [Figure 15B] 1 illustrates an embodiment of an architecture that includes a virtualized or "ghost" GPU.

[0021] [Figure 16] 1 illustrates another embodiment of an architecture that includes a virtualized or "ghost" GPU.

[0022] [Figure 17] Timings associated with a run using three ghost GPUs and one physical GPU are shown.

[0023] [Figure 18] 1 illustrates one embodiment for creating ghost GPUs and enumerating ghost GPUs.

[0024] [Figure 19] 1 illustrates a method according to one embodiment of the present invention.

[0025] [Figure 20A] The configurations of Ghost and Physical GPUs and xPUs are shown. [Figure 20B] The configurations of Ghost and Physical GPUs and xPUs are shown.

[0026] [Figure 21] 1 illustrates one embodiment of an architecture for performing initial training of a machine learning architecture.

[0027] [Figure 22] 1 illustrates an embodiment in which a machine learning engine is continuously trained and updated during runtime.

[0028] [Figure 23] 1 illustrates another embodiment in which a machine learning engine is continuously trained and updated during runtime.

[0029] [Figure 24A] 1 illustrates an embodiment in which machine learning data is shared over a network. [Figure 24B] 1 illustrates an embodiment in which machine learning data is shared over a network.

[0030] [Diagram 25] 1 illustrates one embodiment of a method for training a machine learning engine.

[0031] [Figure 26] 1 illustrates an embodiment in which nodes exchange ghost region data to perform a distributed denoising operation.

[0032] [Figure 27] 1 illustrates an embodiment of an architecture in which image rendering and denoising operations are distributed across multiple nodes.

[0033] [Figure 28] We present additional details of an architecture for distributed rendering and denoising.

[0034] [Figure 29] 1 illustrates a method according to one embodiment of the present invention.

[0035] [Diagram 30] 1 illustrates one embodiment of a machine learning method.

[0036] [Diagram 31]1 shows multiple interconnected general-purpose graphics processors.

[0037] [Diagram 32] We present a set of convolutional and fully connected layers for a machine learning implementation.

[0038] [Diagram 33] 1 illustrates one embodiment of a convolutional layer.

[0039] [Diagram 34] 1 illustrates an example of a set of interconnected nodes in a machine learning implementation.

[0040] [Diagram 35] 1 illustrates one embodiment of a training framework in which a neural network learns using a training dataset.

[0041] [Figure 36A] An example of model parallelism and data parallelism will be given.

[0042] [Figure 36B] An example of a system on chip (SoC) is shown.

[0043] [Figure 37] 1 illustrates an example of a processing architecture including a ray tracing core and a tensor core.

[0044] [Figure 38] 1 shows an example of a beam.

[0045] [Figure 39] 1 illustrates an embodiment of an apparatus for performing beam tracking.

[0046] [Diagram 40] 1 shows an example of a beam hierarchy.

[0047] [Diagram 41]A method for performing beam tracing is shown.

[0048] [Diagram 42] 1 illustrates an example of a distributed ray tracing engine.

[0049] [Diagram 43] 1 shows an example of compression performed in a ray tracing system. [Diagram 44] 1 shows an example of compression performed in a ray tracing system.

[0050] [Diagram 45] 1 illustrates a method according to one embodiment of the present invention.

[0051] [Figure 46] 1 illustrates an exemplary hybrid ray tracing apparatus.

[0052] [Figure 47] 1 shows an example of a stack used for a ray tracing operation.

[0053] [Figure 48] 1 illustrates additional details of one embodiment of a hybrid ray tracing apparatus.

[0054] [Figure 49] 1 illustrates an example of a bounding volume hierarchy.

[0055] [Figure 50] 1 shows an example of a call stack and traversal state storage.

[0056] [Figure 51] 1 illustrates one embodiment of a method for traversal and intersection.

[0057] [Figure 52A] 1 illustrates an embodiment in which multiple dispatch cycles are required to execute a particular shader. [Figure 52B]1 illustrates an embodiment in which multiple dispatch cycles are required to execute a particular shader.

[0058] [Diagram 53] 1 illustrates an embodiment in which a single dispatch cycle executes multiple shaders.

[0059] [Figure 54] 1 illustrates another embodiment in which a single dispatch cycle executes multiple shaders.

[0060] [Figure 55] 1 illustrates one embodiment of an architecture for executing ray tracing instructions.

[0061] [Figure 56] 1 illustrates one embodiment of a method for executing ray tracing instructions within a thread.

[0062] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0063] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present invention described below. However, it will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of the embodiments of the present invention. Exemplary Graphics Processor Architecture and Data Types <System Overview>

[0064] 1 is a block diagram of a processing system 100 according to one embodiment. System 100 may be used in a single processor desktop system, a multiprocessor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform integrated into a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices, such as in the Internet of Things (IoT) with wired or wireless connections to local or wide area networks.

[0065] In one embodiment, system 100 may include, be coupled to, or be integrated into a server-based gaming platform, a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, system 100 is part of a mobile Internet-connected device, such as a mobile phone, a smart phone, a tablet computing device, or a laptop with low internal storage capacity. Processing system 100 may also include, be coupled to, or be integrated into a wearable device, such as a smart watch wearable device, smart glasses or clothing, other augmented reality (AR) device, or other virtual reality (VR) device, augmented with augmented reality (AR) or virtual reality (VR) capabilities that provide visual, auditory, or haptic output to augment a real-world visual, auditory, or haptic experience, or to provide text, audio, graphics, video, holographic images or video, or haptic feedback. In some embodiments, processing system 100 includes or is part of a television or a set-top box. In one embodiment, system 100 may include, be coupled to, or integrated within an autonomous vehicle, such as a bus, a tractor, a trailer, an automobile, a motor or electric bicycle, an airplane, or a glider (or any combination thereof), which may use system 100 to process the sensed environment around the vehicle.

[0066] In some embodiments, the one or more processors 102 each include one or more processor cores 107 that process instructions that, when executed, perform operations for system or user software. In some embodiments, at least one of the one or more processor cores 107 is configured to process a specific instruction set 109. In some embodiments, the instruction set 109 may implement Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW) computations. One or more processor cores 107 may process different instruction sets 109 that may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may also include other processing devices, such as a Digital Signal Processor (DSP).

[0067] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level 3 (L3) cache or Last Level Cache (LLC) (not shown)) that may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 may additionally be included in the processor 102 and may include different types of registers for storing different data types (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general purpose registers and other registers may be specific to the design of the processor 102.

[0068] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 for transmitting communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. The interface bus 110, in one embodiment, may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller bus (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0069] The memory device 120 may be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, a flash memory device, a phase-change memory device, or any other memory device with suitable performance to function as a process memory. In one embodiment, the memory device 120 operates as a system memory for the system 100 and may store data 122 and memory 121 for use when the one or more processors 102 execute applications or processes. The memory controller 116 also couples to an optional external graphics processor 118 that may communicate with one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, graphics, media, and / or computation operations may be assisted by an accelerator 112, which is a co-processor that may be configured to perform a dedicated set of graphics, media, or computation operations. For example, in one embodiment, the accelerator 112 is a matrix multiplication accelerator used to optimize machine learning or computation operations. In one embodiment, accelerator 112 is a ray tracing accelerator that may be used to perform ray tracing operations in conjunction with graphics processor 108. In one embodiment, external accelerator 119 may be used instead of or in conjunction with accelerator 112n.

[0070] In some embodiments, a display device 111 can be connected to the processor 102. The display device 111 can be one or more of an internal display device, such as in a mobile electronic or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 can be a head mounted display (HMD), such as a stereoscopic display for use in virtual reality (VR) or augmented reality (AR) applications.

[0071] In some embodiments, the platform control hub 130 allows peripherals to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio control 146, a network control 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., non-volatile memory, volatile memory, hard disk drive, flash memory, NAND, 3D NAND, 3D XPoint, etc.). The data storage device 124 can be connected via a storage interface (e.g., SATA) or via a peripheral bus such as a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, 5G, or LTE (Long-Term Evolution) transceiver. Firmware interface 128 allows for communication with system firmware and may be, for example, unified extensible firmware interface (UEFI). Network controller 134 may allow for network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. Audio controller 146, in one embodiment, is a multi-channel high resolution audio controller. In some embodiments, system 100 includes an optical legacy I / O controller 140 that couples legacy (e.g., Personal System 2 (PS / 2)) input devices to the system. Platform control hub 130 may also connect to one or more Universal Serial Bus (USB) controller 142 connected input devices, such as a keyboard and mouse 143 coupling, a camera 144, or other USB input devices.

[0072] It is understood that system 100 is shown by way of example and not limitation, and that other types of data processing systems configured in different ways may be used. For example, instances of memory controller 116 and platform control hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 118. In one embodiment, platform control hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include external memory controller 116 and platform control hub 130, which may be configured as memory control hub and peripheral control units within a system chipset that communicates with processor 102.

[0073] For example, the circuit boards ("sleds") on which components such as CPUs, memory, and other components are located are designed for improved thermal performance. In some examples, processing components such as processors are located on the top side of the sled, and nearby memory such as DIMMs are located on the bottom side of the sled. As a result of the improved airflow provided by this design, the components can operate at higher frequencies and higher power levels than standard systems, thereby improving performance. Additionally, the sleds are configured to blindly mate with power and data communication cables in the rack, thereby improving their ability to be quickly removed, upgraded, reinstalled, and / or replaced. Similarly, the individual components located on the sleds, such as the processors, accelerators, memory, and data storage drives, are configured to be easily upgraded by being spaced farther apart from one another. In an illustrative embodiment, the components further include hardware attestation capabilities to attest to their authenticity.

[0074] Data centers can utilize a single network architecture ("fabric") that supports multiple other network architectures, including Ethernet and Omni-Path. Threads can be coupled to switches via optical fiber, which provides higher bandwidth and lower latency than standard twisted-pair cable (e.g., Cat 5, Cat 5e, Cat 6, etc.). The high bandwidth, low latency interconnect and network architecture allows data centers to pool resources such as memory, accelerators (e.g., GPUs, graphics accelerators, FPGAs, ASICs, neural network and / or artificial intelligence accelerators, etc.), and physically disaggregated data storage drives, when in use, and provide them to computing resources (e.g., processors) as needed, allowing the computing resources to access the pooled resources as if they were local.

[0075] A power supply or source can provide voltage and / or current to system 100 or any component or system described herein. In one example, the power source includes an AC-DC (alternating current to direct current) adapter for plugging into a wall outlet. Such AC power can be a sustainable energy (e.g., solar power) source. In one example, the power source includes a DC source, such as an external AC-DC converter. In one example, the power supply or source includes wireless charging hardware that charges via a nearby charging field. In one example, the power source can include an internal battery, an AC source, a motion-based power source, a solar cell, or a fuel cell.

[0076] 2A-2D illustrate a computing system and graphics processor provided in accordance with embodiments described herein. Elements of FIGs. 2A-2D having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including, but not limited to, such.

[0077] FIG. 2A is a block diagram of one embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. Processor 200 may include additional cores up to and including additional core 202N, represented by a dashed box. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206. The internal cache units 204A-204N and the shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared intermediate cache, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, where the highest level cache before external memory is classified as an LLC. In some embodiments, cache coherency logic maintains coherency among the various cache units 206 and 204A-204N.

[0078] In some embodiments, processor 200 may also include a set of one or more bus control units 216 and a system agent core 210. The one or more bus control units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage various external memory devices (not shown).

[0079] In some embodiments, one or more of the processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, the system agent core 210 includes components for coordinating and operating the cores 202A-202N during multithreaded processing. The system agent core 210 may further include a power control unit (PCU) that includes logic and components for coordinating the power state of the processor cores 202A-202N and the graphics processor 208.

[0080] In some embodiments, processor 200 further includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 couples to a set of shared cache units 206 and a system agent core 210 that includes one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 for driving graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may also include a separate module coupled to the graphics processor via at least one interconnect or may be integrated within graphics processor 208.

[0081] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units may be used, such as a point-to-point interconnect, a switched interconnect, or other technologies, including those well known in the art. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0082] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including a package I / O interconnect that facilitates communication between various processor components and a high performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 can use the embedded memory module 218 as a shared Last Level Cache.

[0083] In some embodiments, the processor cores 202A-202N are homogenous cores that execute the same instruction set architecture. In another embodiment, the processor cores 202A-202N are heterogeneous in terms of instruction set architecture, where one or more of the processor cores 202A-202N execute a first instruction set while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of microarchitecture, where one or more cores have a relatively high power consumption binding and one or more power cores have a lower power consumption. In one embodiment, the processor cores 202A-202N are heterogeneous in terms of computational capabilities. Additionally, the processor 200 can be implemented on one or more chips or as a SoC integrated circuit having the illustrated components in addition to other components.

[0084] FIG. 2B is a block diagram of hardware logic of a graphics processor core 219 according to some embodiments described herein. Elements of FIG. 2B having the same reference numbers (or names) as elements of any other figures herein may operate or function in any manner similar to that described elsewhere herein, including but not limited to such. The graphics processor core 219, sometimes referred to as a core slice, may be one or more graphics cores in a modular graphics processor. The graphics processor core 219 is an example of one graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 219 may include a fixed function block 230 coupled to multiple sub-cores 221A-221F, also referred to as sub-slices, that include modular blocks of general purpose and fixed function logic.

[0085] In some embodiments, fixed function block 230 includes a geometry / fixed function pipeline 231 that may be shared by all sub-cores in graphics processor core 219, for example in a lower performance and / or power graphics processor implementation. In various embodiments, geometry / fixed function pipeline 231 includes a 3D fixed function pipeline (e.g., 3D pipeline 312, as in Figures 3 and 4, described below), a video front end unit, a thread spawner and dispatcher, and a unified return buffer manager that manages a unified return buffer (e.g., unified return buffer 418, Figure 4, described below).

[0086] In one embodiment, the fixed function block 230 also includes a graphics SoC interface 232, a graphics microcontroller 233, and a media pipeline 234. The graphics SoC interface 232 provides an interface between the graphics processor core 219 and other processor cores in the system-on-chip integrated circuit. The graphics microcontroller 233 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 219, including thread dispatching, scheduling, and pre-emption. The media pipeline 234 (e.g., media pipeline 316 of FIGS. 3 and 4) includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 234 performs media operations upon requests to computation or sampling logic in the sub-cores 221A-221F.

[0087] In one embodiment, the SoC interface 232 enables the graphics processor core 219 to communicate with other components in the SoC, including general purpose application processor cores (e.g., CPUs) and / or memory hierarchy elements including shared last level cache memory, system RAM, and / or integrated on-chip or on-package DRAM. The SoC interface 232 also enables communication with fixed function devices in the SoC, such as a camera image pipeline, and enables the use and / or implementation of global memory atomics that may be shared between the graphics processor core 219 and CPUs in the SoC. The SoC interface 232 may also implement power management controls for the graphics processor core 219, and enables an interface between the clock domain of the graphics core 219 and other clock domains in the SoC. In one embodiment, the SoC interface 232 enables the receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions may be dispatched to the media pipeline 234 when media operations are performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 231, geometry and fixed function pipelines 237) when graphics processing operations are performed.

[0088] Graphics microcontroller 233 may be configured to perform various scheduling and management tasks for graphics processor core 219. In one embodiment, graphics microcontroller 233 may perform graphics and / or compute workload scheduling for various graphics parallel engines in execution unit (EU) arrays 221A-221F, 224A-224F in sub-cores 221A-221F. In this scheduling model, host software executing on a CPU core of an SoC including graphics processor core 219 may submit a workload to one of multiple graphics processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting the workload to a command streamer, pre-empting existing workloads running on the engines, monitoring the progress of the workload, and notifying the host software when the workload is completed. In one embodiment, the graphics microcontroller 233 can also facilitate low power or idle states for the graphics processor core 219, providing the graphics processor core 219 with the ability to conserve and restore registers within the graphics processor core 219 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0089] Graphics processor core 219 may have up to N modular sub-cores, more or less than the illustrated sub-cores 221A-221F. For each set of N sub-cores, graphics processor core 219 may also include shared function logic 235, shared and / or cache memory 236, geometry / fixed function pipeline 237, and additional fixed function logic 238 for accelerating various graphics and computational processing operations. Shared function logic 235 may include logic associated with shared function logic 420 of FIG. 4 (e.g., sampler, arithmetic, and / or inter-thread communication logic) that is shareable by each of the N sub-cores in graphics processor core 219. Shared and / or cache memory 236 may be a last level cache for the set of N sub-cores 221A-221F in graphics processor core 219 and may also function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 237 is included in place of geometry / fixed function pipeline 231 in fixed function block 230 and may include the same or similar logic units.

[0090] In one embodiment, graphics processor core 219 includes additional fixed function logic 238, which may include various fixed function acceleration logic for use by graphics processor core 219. In one embodiment, additional fixed function logic 238 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are two geometry pipelines: a complete geometry pipeline in geometry / fixed function pipeline 238, 231, and a cull pipeline, which is an additional geometry pipeline that may be included in additional fixed function logic 238. In one embodiment, the cull pipeline is a fragmented version of the complete geometry pipeline. The complete pipeline and the cull pipeline can run different instances of the same application, with each instance having a separate context. Position-only shading can hide long cull runs of discarded triangles, completing shading faster than in some instances. For example, in one embodiment, the cull pipeline logic in additional fixed function logic 238 can run position shaders in parallel with the main application, typically producing significant results faster than the complete pipeline. This is because the cull pipeline only fetches and shades the position attributes of vertices, without performing pixel rasterization and rendering to the frame buffer. The cull pipeline can use the generated material results to calculate visibility information for all triangles, regardless of whether they are culled or not. The full pipeline (which may be called the reconstructed pipeline in this example) can consume the visibility information, skip the culled triangles, and shade only the visible triangles that are eventually passed to the rasterization stage.

[0091] In one embodiment, the additional process function logic 238 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations involving machine learning training or estimation optimization.

[0092] Within each graphics sub-core 221A-221F is a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests by a graphics pipeline, a media pipeline, or a shader program. The graphics sub-cores 221A-221F include a number of EU arrays 222A-222F, 224A-224F, thread dispatch and inter-thread communication (TD / IC) logic 223A-223F, 3D (e.g., texture) samplers 225A-225F, media samplers 206A-206F, shader processors 227A-227F, and shared local memory (SLM) 228A-228F. Each of the EU arrays 222A-222F, 224A-224F includes a number of execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations in the service of graphics, media, or compute operations, including graphics, media, or compute shader programs. The TD / IC logic 223A-223F performs local thread dispatch and thread control operations for the execution units in the sub-cores and facilitates communication between threads executing on the execution units of the sub-cores. The 3D samplers 225A-225F can read textures or other 3D graphics related data into memory. The 3D samplers can read texture data in different ways based on the configured sample state and the texture format associated with a given texture. The media samplers 206A-206F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each of the graphics sub-cores 221A-221F can alternatively include an integrated 3D and media sampler. Threads executing on execution units within each of the sub-cores 221A-221F can utilize shared local memory 228A-228F within each sub-core, allowing threads executing within a thread group to execute using a common pool of on-chip memory.

[0093] 2C illustrates a graphics processing unit (GPU) 239 that includes a dedicated set of graphics processing resources organized into multi-core groups 240A-240N. Details of only a single multi-core group 240A are provided, it being understood that the other multi-core groups 240B-240N may be equipped with the same or similar sets of graphics processing resources.

[0094] As shown, multi-core group 240A may include a set of graphics cores 243, a set of tensor cores 244, and a set of ray tracing cores 245. Scheduler / dispatcher 241 schedules and dispatches graphics threads for execution on the various cores 243, 244, 245. A set of register files 242 stores operand values ​​used by cores 243, 244, 245 when executing graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0095] One or more combined level 1 (L1) cache and shared memory units 247 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. locally within each multicore group 240A. One or more texture units 247 may also be used to perform texture operations such as texture mapping and sampling. A level 2 (L2) cache 253, shared by all or a subset of the multicore groups 240A-240N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 253 may be shared across multiple multicore groups 240A-240N. One or more memory controllers 248 couple the GPU 239 to memory 249, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0096] Input / output (I / O) circuitry 250 couples GPU 239 to one or more I / O devices 252, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O devices 252 to GPU 239 and memory 249. One or more I / O memory management units (IOMMUs) 251 of I / O circuitry 250 directly couple I / O devices 252 to system memory 249. In one embodiment, IOMMU 251 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 249. In this embodiment, I / O devices 252, CPU 246, and GPU 239 may share the same virtual address space.

[0097] In one implementation, IOMMU 251 supports virtualization. In this case, IOMMU 251 may manage a first set of page tables that map guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables that map guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 249). The base addresses of each of the first and second page table sets may be stored in control registers and swapped out on a context switch (e.g., so that a new context is provided access to the associated page table set). Although not shown in FIG. 2C, each of cores 243, 244, 245 and / or multicore groups 240A-240N may include a translation lookaside buffer (TLB) that caches guest virtual translations to guest physical translations, guest physical translations to host physical translations, and guest virtual translations to host physical translations.

[0098] In one embodiment, CPU 246, GPU 239, and I / O devices 252 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 249 may be integrated into the same chip or may be coupled to memory controller 248 via an off-chip interface. In one implementation, memory 249 includes GDDR6 memory that shares the same virtual address space as other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0099] In one embodiment, tensor cores 244 include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and estimation. Tensor cores 244 may perform matrix operations using a variety of operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and half byte (4 bits). In one embodiment, the neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0100] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on tensor cores 244. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process the inner product formulation of an N×N×N matrix multiplication, tensor cores 244 may include at least N dot product processing elements. Before starting the matrix multiplication, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded in each of the N cycles. In each cycle, there are N dot products to be processed.

[0101] Matrix elements may be stored with different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for tensor cores 244 to ensure that the most efficient precision is used for different workloads (e.g., estimated workloads that can tolerate quantization to bytes and half-bytes).

[0102] In one embodiment, ray tracing core 245 accelerates ray tracing operations for both real-time and non-real-time ray tracing implementations. In particular, ray tracing core 245 includes ray traverse / intersection circuitry to perform ray traversal using a bounding volume hierarchy (BVH) and identify intersections between rays and primitives confined within the BVH volume. Ray tracing core 245 may also include circuitry to perform depth testing and culling (e.g., using a Z-buffer or similar construct). In one embodiment, ray tracing core 245 performs traversal and intersection operations in conjunction with image denoising techniques described herein, which may be performed at least in part on tensor core 244. For example, in one embodiment, tensor core 244 implements a deep learning neural network to perform denoising of frames generated by ray tracing core 245. However, the CPU 246, the graphics core 243, and / or the ray tracing core 245 may implement all or part of the denoising and / or deep learning algorithms.

[0103] Additionally, as discussed above, a distributed approach to denoising may be utilized, where the GPU 239 is in a computing device that is coupled to other computing devices via a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0104] In one embodiment, ray tracing core 245 handles all BVH traversals and ray primitive intersections to prevent graphics core 243 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 245 includes a first set of dedicated circuitry to perform bounding box tests (e.g., for traverse operations) and a second set of dedicated circuitry to perform ray triangle intersection tests (e.g., intersecting traversed rays). Thus, in one embodiment, multi-core group 240A can simply issue ray probes, and ray tracing core 245 independently performs ray traversals and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 243, 244 are freed to perform other graphics or computational work while ray tracing core 245 performs traverse and intersection operations.

[0105] In one embodiment, each ray tracing core 245 includes a traverse unit for performing BVH test operations and an intersection unit for performing ray primitive intersection tests. The intersection unit generates and provides a "hit", "no hit", or "multiple hit" response to the appropriate thread. During traverse and intersection operations, the execution resources of other cores (e.g., graphics core 243 and tensor core 244) are freed to perform other types of graphics work.

[0106] In one particular embodiment, described below, a hybrid rasterization / ray tracing approach is used, with work distributed between the graphics core 243 and the ray tracing core 245.

[0107] In one embodiment, the ray tracing core 245 (and / or other cores 243, 244) includes hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR), which includes a DispatchRays command and ray generation, nearest hit, any hit, and miss shaders, allowing assignment of a unique set of shaders and textures per object. Another ray tracing platform that may be supported by the ray tracing core 245, graphics core 243, and tensor core 244 is Vulkan 1.1.85. However, it is noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0108] In general, the various cores 245, 244, 243 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, any hit, ray primitive intersection, per-primitive and substructure bounding box construction, miss, visit, and exception. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

[0109] Ray Generation: Ray generation instructions may be executed per pixel, sample, or other user-defined work allocation.

[0110] Closest Hit: The Closest Hit instruction may be executed to locate the closest intersection point of a ray with a primitive in a scene.

[0111] Any Hit: The Any Hit command identifies multiple intersections between a ray and primitives in the scene, and potentially identifies a new nearest intersection point.

[0112] Intersection: The intersection command performs a ray-primitive intersection test and outputs the result.

[0113] Per-primitive Bounding box Construction: This instruction constructs a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0114] Miss: Indicates that the ray misses all geometry in the scene or a particular area of ​​the scene.

[0115] Visit: Indicates the child volume that the ray will traverse.

[0116] Exceptions: Includes various kinds of exception handling (eg, invoked for various error conditions).

[0117] 2D is a block diagram of a general purpose graphics processing unit (GPGPU) 270 that may be configured as a graphics processor and / or computational accelerator according to embodiments described herein. GPGPU 270 may be interconnected with a host processor (e.g., one or more CPUs 246) and memories 271, 272 via one or more system and / or memory buses. In one embodiment, memory 271 is a system memory that may be shared by one or more CPUs 246, and memory 272 is a device memory dedicated to GPGPU 270. In one embodiment, components within GPGPU 270 and device memory 272 may be mapped to memory addresses accessible by one or more CPUs 246. Access to memories 271 and 272 may be facilitated by memory controller 268. In one embodiment, memory controller 268 may include an internal direct memory access (DMA) controller 269 or may include logic to perform operations that may otherwise be performed by a DMA controller.

[0118] GPGPU 270 includes multiple cache memories, including L2 cache 253, L1 cache 254, instruction cache 255, and shared memory 256, at least a portion of which may be partitioned as cache memories. GPGPU 270 also includes multiple compute units 260A-260N. Each compute unit 260A-260N includes a set of vector registers 261, scalar registers 262, a vector logic unit 263, and a scalar logic unit 264. Compute units 260A-260N may also include local shared memory 256 and program counter 266. Compute units 260A-260N may be coupled to a constant cache 267 that may be used to store constant data that does not change during execution of a kernel or shader program executing on GPGPU 270. In one embodiment, constant cache 267 is a scalar data cache, and cached data may be fetched directly into scalar registers 262.

[0119] During operation, one or more CPUs 246 can write commands that are mapped into an accessible address space to registers or memory within GPGPU 270. Command processor 257 can read commands from registers or memory and determine how these commands are processed within GPGPU 270. Thread dispatcher 258 can then be used to dispatch threads to computation units 260A-260N for execution of these commands. Each computation unit 260A-260N can execute threads independently of the other computation units. Additionally, each computation unit 260A-260N can be independently configured to perform conditional computations and can conditionally output computation results to memory. Command processor 257 can interrupt one or more CPUs 246 upon completion of a submitted command.

[0120] 3A-3C show block diagrams of additional graphics processors and computational accelerators provided by embodiments described herein. Elements of FIGs. 3A-3C having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

[0121] 3A is a block diagram of a graphics processor 300, which may be a discrete graphics processing unit or may be a graphics processor integrated with multiple processing cores or other semiconductor devices such as, but not limited to, memory devices or network interfaces. In some embodiments, the graphics processor communicates with registers on the graphics processor and with commands placed in the processor memory via a memory-mapped I / O interface. In some embodiments, the graphics processor 300 includes a memory interface 314 to access memory. The memory interface 314 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0122] In some embodiments, the graphics processor 300 also includes a display control 302 that drives display output data to a display device 318. The display control 302 includes hardware for one or more overlay planes for display and for compositing multiple layers of video or user interface elements. The display device 318 can be an internal or external display device. In one embodiment, the display device 318 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 for encoding, decoding, or converting media to, to, or between one or more media coding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, H.265 / HEVC, Alliance for Open Media (AOMedia) VP8, VP9, ​​and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

[0123] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterization operations, including, for example, bit-boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a computation engine for performing graphics operations, including three-dimensional (3D) graphics and media operations.

[0124] In some embodiments, GPE 310 includes a 3D pipeline 312 that performs 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the elements and / or generate execution threads for 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media operations such as video post-processing and image enhancement.

[0125] In some embodiments, the media pipeline 316 includes fixed function or programmable logic units that perform one or more specific media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, instead of or on behalf of the video codec engine 306. In some embodiments, the media pipeline 316 further includes a thread generation unit that generates threads for execution on the 3D / media subsystem 315. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0126] In some embodiments, the 3D / Media subsystem 315 includes logic to execute threads created by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315. The 3D / Media subsystem 315 includes thread dispatch logic to arbitrate and dispatch the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, for sharing data between threads and for storing output data.

[0127] FIG. 3B illustrates a graphics processor 320 having a tile architecture according to an embodiment described herein. In one embodiment, the graphics processor 320 includes a graphics processing engine cluster 322 having multiple instances of the graphics processing engine 310 of FIG. 3A in graphics engine tiles 310A-310D. Each of the graphics engine tiles 310A-310D can be interconnected via a set of tile interconnects 323A-323F. Each of the graphics engine tiles 310A-310D can also be connected to memory modules or memory devices 326A-326D via memory interconnects 325A-325D. The memory devices 326A-326D can use any graphics memory technology. For example, the memory devices 326A-326D can be graphics double data rate (GDDR) memories. Memory devices 326A-326D, in one embodiment, are high-bandwidth memory (HBM) modules on the die with their respective graphics engine tiles 310A-310D. In one embodiment, memory devices 326A-326D are stacked memory devices that may be stacked on top of their respective graphics engine tiles 310A-310D. In one embodiment, each graphics engine tile 310A-310D and associated memory 326A-326D resides on an individual chiplet that is coupled to a base die or base substrate as detailed in Figures 11B-11D.

[0128] The graphics processing engine cluster 322 can be connected to an on-chip or on-package fabric interconnect 324. The fabric interconnect 324 enables communication between the graphics engine tiles 310A-310D and components such as the video codec 306 and one or more copy engines 304. The copy engine 304 can be used to move data to / from / between the memory devices 326A-326D and memory external to the graphics processor 320 (e.g., system memory). The fabric interconnect 324 can also be used to interconnect the graphics engine tiles 310A-310D. The graphics processor 320 can optionally include a display controller 302 to enable connection to an external display device 318. The graphics processor can be configured as a graphics or computation accelerator. In an accelerator configuration, the display controller 302 and the display device 318 can be omitted.

[0129] Graphics processor 320 may be connected to a host system via host interface 328. Host interface 328 may enable communication between graphics processor 320, system memory, and / or other system components. Host interface 328 may be, for example, a PCI Express bus or another type of host system interface.

[0130] FIG. 3C illustrates a computation accelerator 330 according to an embodiment described herein. The computation accelerator 330 includes architectural similarities to the graphics processor 320 of FIG. 3B and is optimized for computation acceleration. The computation engine cluster 332 may include a set of computation engine tiles 340A-340D that include execution logic optimized for general-purpose computation operations based on parallel or vectors. In some embodiments, the computation engine tiles 340A-340D do not include fixed-function graphics processing logic, but in one embodiment, one or more of the computation engine tiles 340A-340D may include logic for performing media acceleration. The computation engine tiles 340A-340D may be connected to memories 326A-326D via memory interconnects 325A-325D. The memories 326A-326D and memory interconnects 325A-325D may be of similar technology as in the graphics processor 320, or may be different. Graphics computation engine tiles 340A-340D may also be interconnected via tile interconnects 323A-323F, which may be connected to and / or interconnected by fabric interconnect 324. In one embodiment, computation accelerator 330 includes a large L3 cache 336, which may be configured as a device-wide cache. Computation accelerator 330 may also be connected to a host processor and memory via host interface 328, in a manner similar to graphics processor 320 of FIG. 3B.

[0131] <Graphics processing engine>

[0132] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3A and may represent the graphics engine tiles 310A-310D of FIG. 3B. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and media pipeline 316 of FIG. 3A are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, separate media and / or image processors are coupled to the GPE 410.

[0133] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be one or more of a system memory or an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are instructions fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may further include a batch command buffer that stores a batch of multiple commands. Commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media subsystem 316 process commands and data by executing operations through logic within the respective pipelines, and by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B). Each block includes one or more graphics cores. Each graphics core includes a set of graphics execution resources, including general purpose and graphics dedicated execution logic to perform graphics and computation operations, as well as fixed function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0134] In various embodiments, the 3D pipeline 312 may include fixed function and programmable logic that processes one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides an integrated block of execution resources for use in processing these shader programs. General purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads associated with multiple shaders.

[0135] In some embodiments, graphics core array 414 includes execution logic to perform media functions such as video and / or image processing. In one embodiment, the execution units include general purpose logic to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel with or in conjunction with general purpose logic in processor core 107 of FIG. 1 or cores 202A-202N as in FIG. 2A.

[0136] Output data generated by threads executing on the graphics core array 414 may output data to memory in unified return buffers (URBs) 418. The URBs 418 can store data for multiple threads. In some embodiments, the URBs 418 may be used to transmit data between different threads executing on the graphics core array 414. In some embodiments, the URBs 418 may also be used for synchronization between threads on the graphics core array and fixed function logic in the shared function logic 420.

[0137] In some embodiments, graphics core array 414 is scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 410. In one embodiment, execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

[0138] The graphics core array 414 couples to shared function logic 420, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functions in the shared function logic 420 are hardware logic units that provide dedicated complementary functions to the graphics core array 414. In various embodiments, the shared function logic 420 includes, but is not limited to, sampler 421, arithmetic 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared function logic 420.

[0139] Shared functionality is implemented at least when a given dedicated functionality is insufficient for inclusion within the graphics core array 414. Instead, a single instantiation of this dedicated functionality is implemented as a standalone entity within the shared functionality logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functionality included within the graphics core array 414 that is shared among the graphics core array 414 varies depending on the embodiment. In some embodiments, certain shared functionality within the shared functionality logic 420 that is used extensively by the graphics core array 414 may be included in the shared functionality logic 416 within the graphics core array 414. In various embodiments, the shared functionality logic 416 within the graphics core array 414 may include some or all of the logic within the shared functionality logic 420. In one embodiment, all of the logical elements within the shared functionality logic 420 may be duplicated within the shared functionality logic 416 of the graphics core array 414. In one embodiment, the shared functionality logic 420 is removed in favor of the shared functionality logic 416 within the graphics core array 414.

[0140] <Execution unit>

[0141] 5A-5B illustrate thread execution logic 500 including an array of processing elements utilized in a graphics processor core according to embodiments described herein. Elements of FIG. 5A-5B having the same reference numbers (or names) as elements of any other figures herein may operate or function in any manner similar to that described elsewhere herein, including but not limited to such. FIG. 5A-5B illustrates a schematic of thread execution logic 500 that may represent the hardware logic shown with each of sub-cores 221A-221F of FIG. 2B. FIG. 5A illustrates an execution unit in a general-purpose graphics processor, and FIG. 5B illustrates an execution unit that may be used in a computational accelerator.

[0142] As shown in FIG. 5A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 508A-508N, a sampler 510, a shared local memory 511, a data cache 512, and a data port 514. In one embodiment, the scalable execution unit array is dynamically scalable by enabling or disabling one or more execution units (e.g., any of execution units 508A, 508B, 508C, 508D-508N-1, and 508N) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect fabric that links each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to a memory, such as a system memory or a cache memory, through one or more of the instruction cache 506, the data port 514, the sampler 510, and the execution units 508A-508N. In some embodiments, each execution unit (e.g., 508A) is a self-contained programmable general-purpose computational unit capable of executing multiple simultaneous hardware threads, processing multiple data elements in parallel with each thread. In various embodiments, the array of execution units 508A-508N is scalable to include any number of individual execution units.

[0143] In some embodiments, execution units 508A-508N are primarily used to execute shader programs. Shader processor 502 processes various shader programs and dispatches execution threads associated with the shader programs via thread dispatcher 504. In one embodiment, the thread dispatcher includes logic for arbitrating thread initiation requests from the graphics and media pipelines and instantiating the requested threads on one or more execution units within execution units 508A-508N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, thread dispatcher 504 can also handle run-time thread creation requests from executing shader programs.

[0144] In some embodiments, the execution units 508A-508N support an instruction set that includes native support for many standard 3D graphics shader instructions. As a result, shader programs from graphics libraries (e.g., Direct 3D and OpenGL) execute with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of the execution units 508A-508N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation allows for an efficient execution environment despite higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multi-issue per clock for a pipeline capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and a wide variety of other operations. While waiting for data from memory or one of the shared functions, subordinate logic within the execution units 508A-508N puts the waiting thread to sleep until the required data is returned. While the waiting thread is sleeping, hardware resources may be dedicated to other threads in process. For example, during a delay associated with a vertex shader operation, the execution unit may execute operations for another type of shader program, including a pixel shader, a fragment shader, or a different vertex shader. Various embodiments may be applied to use execution using Single Instruction Multiple Threads (SIMT) as an alternative to or in addition to using SIMD. Reference to a SIMD core or operation may also apply to SIMT or to SIMD in combination with SIMT.

[0145] Each execution unit in execution units 508A-508N operates on an array of data elements. The number of data elements is the "execution size" or number of channels of the instruction. An execution channel is a logical execution unit of data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) of a particular graphics processor. In some embodiments, execution units 508A-508N support integer and floating point data types.

[0146] The execution unit instruction set includes SIMD instructions. The various data elements can be stored in registers as packed data types, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 54-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double-Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit packed data elements (Byte (B) size data elements). However, different vector widths and register sizes are possible.

[0147] In one embodiment, one or more execution units can be coupled to a combined execution unit 509A-509N having thread control logic (507A-507N) that is common to the combined EUs. Multiple EUs can be coupled to an EU group. Each EU in a combined EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a combined EU group can vary depending on the embodiment. Furthermore, various SIMD widths can be executed per EU, including, but not limited to, SIMD8, SIMD16, and SIMD32. Each combined graphics execution unit 509A-509N includes at least two execution units. For example, combined execution unit 509A includes a first EU 508A, a second EU 508B, and a third thread control logic 507A that is common to the first EU 508A and the second EU 508B. The thread execution logic 507A controls the threads executing on the combined graphic execution unit 509A so that each EU in the combined execution units 509A-509N can execute using a common instruction pointer register.

[0148] One or more internal instruction caches (e.g., 506) are included in the thread execution logic 500 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 512) are included for caching thread data during thread execution. Threads executing on the execution logic 500 can also store explicitly managed data in shared local memory 511. In some embodiments, a sampler 510 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 510 includes dedicated texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0149] During execution, the graphics and media pipeline sends thread start requests to the thread execution logic 500 via thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) in the shader processor 502 is invoked to further compute output information and write the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader or fragment shader computes values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel processor logic in the shader program 502 then executes pixel or fragment shader programs provided by an application programming interface (API). To execute the shader programs, the shader processor 502 dispatches threads to execution units (e.g., 508A) via the thread dispatcher 504. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 510 to access texture data in texture maps stored in memory. Texturizers and arithmetic operations on the input geometry data compute pixel color data for each geometry fragment or discard one or more pixels from further processing.

[0150] In some embodiments, the data port 514 provides a memory access mechanism for the thread execution logic 500 to output processed data to memory for future processing on the graphics processor output pipeline. In some embodiments, the data port 514 includes or couples to one or more cache memories (e.g., data cache 512) to cache data for memory access by the data port.

[0151] In one embodiment, the execution logic 500 may also include a ray tracer 505 that may provide ray tracing acceleration functionality. The ray tracer 505 may support a ray tracing instruction set that includes instructions / functions for ray generation. The ray tracing instruction set may be similar to or different from the ray tracing instruction set supported by the ray tracing core 245 of FIG. 2C.

[0152] 5B illustrates exemplary internal details of an execution unit 508, according to an embodiment. The graphics execution unit 508 may include an instruction fetch unit 537, a general register file array (GRF) 524, an architectural register file array (ARF) 526, a thread arbiter 522, a send unit 530, a branch unit 532, a SIMD floating point unit (FPU) 534, and, in one embodiment, a set of special purpose registers SIMD ALU 535. The GRF 524 and ARF 526 include a general purpose register file and a set of architectural register files associated with each concurrent hardware thread that may be active in the graphics execution unit 508. In one embodiment, a per thread architectural state is maintained in the ARF 256, while data used during thread execution is stored in the GRF 524. The execution state of each thread, including each thread's instruction pointer, may be held in thread-specific registers within the ARF 256.

[0153] In one embodiment, the graphics execution unit 508 has an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). The architecture has a modular configuration that can be tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where the execution unit resources are divided across the logic used to execute multiple simultaneous threads. The number of logical threads that can be executed by the graphics execution unit 508 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.

[0154] In one embodiment, the graphics execution unit 508 can co-issue multiple instructions, each of which may be a different instruction. The thread arbiter 522 of the graphics execution unit thread 508 can dispatch the instruction to one of the send unit 530, the branch unit 532, or the SIMD FPU 534 for execution. Each execution thread has access to 128 general purpose registers in the GRF 524, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4K bytes in the GRF 524, although embodiments are not so limited and other embodiments may be provided with more or less register resources. In one embodiment, the graphics execution unit 508 is partitioned into seven hardware threads that can independently perform computational operations. However, the number of threads per execution unit may also vary according to the embodiment, for example, in one embodiment, up to 16 hardware threads are supported. In one embodiment, 7 threads may access 4K bytes, allowing GRF 524 to store a total of 28K bytes. 16 threads may access 4K bytes, allowing GRF 524 to store a total of 64K bytes. Flexible addressing modes can allow registers to be addressed together to efficiently build wide registers or to represent strided rectangular block data structures.

[0155] In one embodiment, memory operations, sampler operations, and other longer latency system communications are dispatched by "send" instructions executed by a message passing send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 532 to expedite SIMD divergence and final convergence.

[0156] In one embodiment, the graphics execution unit 508 includes one or more SIMD floating point units (FPUs) 534 to perform floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 534 can SIMD execute up to M 32-bit floating point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended computational capabilities to support high-throughput transcendental math functions and double precision 54-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized to perform operations associated with machine learning calculations.

[0157] In some embodiments, an array of multiple instances of the graphics execution unit 508 can be instantiated within a graphics subcore group (e.g., a subslice). For scalability, the product architecture can select the exact number of execution units per subcore group value. In one embodiment, the execution unit 508 can execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 508 executes on a different channel.

[0158] FIG. 6 illustrates an additional execution unit 600 according to one embodiment. The execution unit 600 may be, for example, but not limited to, a compute-optimized execution unit for use in the compute engine tiles 340A-340D of FIG. 3C. Variations of the execution unit 600 may be used in the graphics engine tiles 310A-310D of FIG. 3B. In one embodiment, the execution unit 600 includes a thread control unit 601, a thread state unit 602, an instruction fetch / prefetch unit 603, and an instruction decode unit 604. The execution unit 600 further includes a register file 606 that stores registers that can be allocated to hardware threads within the execution unit. The execution unit 600 further includes a send unit 607 and a branch unit 608. In one embodiment, the send unit 607 and the branch unit 608 may operate similarly to the send unit 530 and the branch unit 532 of the graphics execution unit 508 of FIG. 5B.

[0159] Execution unit 600 also includes a computation unit 610 that includes multiple different types of functional units. In one embodiment, computation unit 610 includes an ALU unit 611 that includes an array of arithmetic logic units. ALU unit 611 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating point operations. The integer and floating point operations may be performed simultaneously. Computation unit 610 may also include a systolic array 612 and an arithmetic unit 613. Systolic array 612 includes a W-wide and D-deep network of data processing units that can be used to perform vector or other data parallel operations in a systolic manner. In one embodiment, systolic array 612 can be configured to perform matrix operations such as matrix dot product operations. In one embodiment, systolic array 612 supports 16-bit floating point operations, and 8-bit and 4-bit integer operations. In one embodiment, systolic array 612 can be configured to accelerate machine learning operations. In such an embodiment, systolic array 612 may be configured to support bfloat 16-bit floating point format. In one embodiment, arithmetic unit 613 may be included to perform a unique subset of arithmetic operations in a more efficient and lower power manner than ALU unit 611. Arithmetic unit 613 may include a variation of arithmetic logic found in the shared function logic of the graphics processing engine provided by other embodiments. In one embodiment, arithmetic unit 613 may be configured to perform 32-bit and 64-bit floating point operations.

[0160] The thread control unit 601 includes logic for controlling the execution of threads in the execution units. The thread control unit 601 may include thread arbitration logic for starting, stopping, and preempting the execution of threads in the execution units 600. The thread state unit 602 may be used to store thread states for threads assigned to execute on the execution units 600. Storing thread states in the execution units 600 allows for fast preemption of threads when these threads become blocked or idle. The instruction fetch / prefetch unit 603 may fetch instructions from higher level execution logic (e.g., instruction cache 506 of FIG. 5A). The instruction fetch / prefetch unit 603 may also issue prefetch requests for instructions to be loaded into the instruction cache based on analysis of currently executing threads. The instruction decode unit 604 may be used to decode instructions to be executed by the compute units. In one embodiment, the instruction decode unit 604 may be used as a secondary decoder to decode complex instructions into component micro operations.

[0161] Execution unit 600 further includes a register file 606 that can be used by hardware threads executing on execution unit 600. The registers in register file 606 can be divided across logic used to execute multiple simultaneous threads in the compute units 610 of execution unit 600. The number of logical threads that can be executed by graphics execution unit 600 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of register file 606 can vary depending on the embodiment based on the number of hardware threads supported. In one embodiment, register renaming can be used to dynamically assign registers to hardware threads.

[0162] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid lined boxes indicate components that are typically included in the execution unit instructions, while the dashed lines include components that are included in any or only a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated are macro-instructions, in that they are the instructions that are supplied to the execution units as the instructions are processed, as opposed to micro-operations that result from instruction decoding.

[0163] In some embodiments, the graphics processor execution units natively support instructions in 128-bit instruction format 710. A 64-bit compact instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction format 710 provides access to all instruction options, and some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, instructions are compacted in part using a set of index values ​​in index file 713. The execution unit hardware looks up a set of compaction tables based on the index value and uses the output of the compaction tables to reconstruct the native instruction in the 128-bit instruction format 710. Instructions of other sizes and formats can be used.

[0164] For each format, the instruction opcode 712 defines the operation that the execution unit is to perform. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture or picture element. By default, the execution unit executes each instruction across all data channels of an operand. In some embodiments, the instruction control field 714 enables control over certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, the exec-size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the exec-size field 716 is not available for use with the 64-bit compact instruction format 730.

[0165] Some execution unit instructions have up to three operands, including two source operands, src0 720, src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implicit. Data manipulation instructions can have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an intermediate (e.g., hard-coded) value passed along with the instruction.

[0166] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether direct register address mode or indirect register address mode is used. When direct register address mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0167] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment of the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0168] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction should use direct or indirect addressing. When the direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When the indirect register addressing mode is used, the register address of one or more operands may be calculated based on an address register value and an address intermediate field in the instruction.

[0169] In some embodiments, instructions are grouped based on a bit field of the opcode 712 to simplify the opcode decoder 740. In an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The detailed opcode grouping shown is merely an example. In some embodiments, the move and logic opcode group 724 includes data movement and logic instructions (e.g., mov, comp). In some embodiments, the move and logic group 742 share the five most significant bits (MSBs), with move instructions being of the form 0000xxxxb and logic instructions being of the form 0001xxxxb. The flow control instruction group 744 (e.g., call, jmp) includes instructions of the form 0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes synchronization instructions (e.g., wait, send) in the format of 0011xxxxb (e.g., 0x30). A parallel arithmetic instruction group 748 includes component-related computation instructions (e.g., add, multiply (mul)) in the format of 0100xxxxb (e.g., 0x40). The parallel arithmetic group 748 performs computation operations in parallel across data channels. A vector arithmetic group 750 includes computation instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). The vector arithmetic group performs computations such as dot product calculations on vector operands. The illustrated opcode decode 740 can be used in one embodiment to determine which portion of the execution unit is used to execute the decoded instruction. For example, some instructions may be designed as systolic instructions executed by a systolic array. Other instructions, such as ray tracing instructions (not shown), can be routed to a ray tracing core or ray tracing logic within a slice or partition of the execution unit.

[0170] <Graphics Pipeline>

[0171] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, including but not limited to such.

[0172] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or by commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803 that provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0173] In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to a vertex shader 807, which performs coordinate space transformations and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute the vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0174] In some embodiments, the execution units 852A-852B are an array of vector processors with an instruction set for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an associated L1 cache 851 that is dedicated to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0175] In some embodiments, the geometry pipeline 820 includes a tessellation component that performs hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 performs the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellator 813 operates under the direction of the hull shader 811 and includes dedicated logic to generate a set of detailed geometry objects based on a coarse geometry model provided as input to the geometry pipeline 820. In some embodiments, if tessellation is not used, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) can be bypassed.

[0176] In some embodiments, a complete geometry object can be processed by geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to clipper 829. In some embodiments, the geometry shader operates on entire geometry objects, rather than vertices or patches of vertices as in previous stages of the geometry pipeline. If tessellation is disabled, geometry shader 819 receives input from vertex shader 807. In some embodiments, geometry shader 819 is programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

[0177] Prior to rasterization, a clipper 829 processes the vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper with clipping and geometry functions. In some embodiments, a rasterizer and depth test component 873 in the render output pipeline 870 dispatches pixel shaders to convert geometry objects into per-pixel representations. In some embodiments, pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via the stream output unit 823.

[0178] Graphics processor 800 has an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed between major components of the processor. In some embodiments, execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the processor's render output pipeline. In some embodiments, sampler 854, caches 851, 858, and execution units 852A-852B each have a separate memory access path. In one embodiment, texture cache 858 may also be configured as a sampler cache.

[0179] In some embodiments, the render output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower / masker unit to perform fixed function triangle and line rasterization. An associated render cache 878 and depth cache 879 are also available in some embodiments. A pixel operations component 877 performs pixel-based operations on the data. However, in some instances, pixel operations associated with 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or substituted at display time by the display controller 843 using an overlay display surface. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing sharing of data without the use of main system memory.

[0180] In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from a command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread spawning function that spawns threads for dispatch to thread execution logic 850 via a thread dispatcher 831.

[0181] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802, or some other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes dedicated logic operable independently of the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown). The display device may be a system built-in display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0182] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and computation APIs, all of which are provided by the Khronos Group. In some embodiments, support may also be provided for Microsoft Corporation's Direct3D library. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines may also be supported, provided that a mapping can be made from the existing API's pipeline to the graphics processor's pipeline.

[0183] <Graphics Pipeline Programming>

[0184] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to one embodiment. The solid lined boxes in Figure 9A indicate components that are typically included in a graphics command, while the dashed lines include components that are optional or that are only included in a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields to identify a client 902, a command operation code (opcode) 904, and data for the command 906. Sub-opcodes 905 and command size 908 are also included in some commands.

[0185] In some embodiments, the client 902 specifies which client units of the graphics device will process the command data. In some embodiments, the graphics processor command parser examines the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned by multiples of double words. Other command formats can be used.

[0186] The flow diagram of FIG. 9B illustrates an exemplary graphics processor command sequence. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The exemplary command sequence is shown and described for illustrative purposes only, and embodiments are not limited to these particular commands or to this command sequence. Furthermore, commands may be issued as a batch of commands in a command sequence. As a result, the graphics processor processes the sequence of commands at least partially concurrently.

[0187] In some embodiments, the graphics processor command sequence 910 may begin with a pipeline flush command 912, causing any active graphics pipelines to complete any commands currently pending in the pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. The pipeline flush is performed to cause the active graphics pipelines to complete any pending commands. In response to the pipeline flush, the command parser for the graphics processor pauses command processing until the active drawing engines complete pending operations and the associated read caches are invalidated. Optionally, any data in the render cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0188] In some embodiments, the pipeline select command 913 is used when a command sequence requests the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is requested only once within an execution context before issuing a pipeline command unless the context should issue commands for both pipelines. In some embodiments, a pipeline flush command 912 is requested immediately before a pipeline switch via the pipeline select command 913.

[0189] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operation and to program the 3D pipeline and media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state of an active pipeline. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in an active pipeline before processing a batch of commands.

[0190] In some embodiments, the return buffer state command 916 is used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor uses one or more return buffers to store output data and also to perform inter-thread communication. In some embodiments, the return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0191] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline decision 902, the command sequence is tailored to the 3D pipeline 922, starting at the 3D pipeline state 930, or the media pipeline 924, starting at the media pipeline state 940.

[0192] Commands for configuring the 3D pipeline state 930 include set 3D state commands that set commands for vertex buffer states, row element states, constant color states, depth buffer states, and other state variables that are to be configured before 3D primitive commands are processed. The values ​​of these commands are determined, at least in part, based on the particular 3D API being used. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if those elements are not being used.

[0193] In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitive via a vertex shader. To process the vertex shader, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0194] In some embodiments, the 3D pipeline 922 is triggered by an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered by a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush command sequences through the graphics pipeline. The 3D pipeline performs geometry operations on 3D primitives. Once the operations are complete, the resulting geometry objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel backend operations may also be included for these operations.

[0195] In some embodiments, the graphics processor command sequence 910 follows the media pipeline 924 when performing media operations. In general, the specific use and programming method of the media pipeline 924 depends on the media or computational operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may be bypassed and media decode may be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operation, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to rendering graphics primitives.

[0196] In some embodiments, the media pipeline 924 is configured in a similar manner to the 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched and placed in the command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 contain data to configure the media pipeline elements used to process the media object. This includes data to configure the video decoding and video encoding logic in the media pipeline, such as the encoding or decoding format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0197] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. A media object includes a memory buffer containing the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or an equivalent execute event (e.g., a register write). The output from the media pipeline 924 may then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed similarly to media operations.

[0198] <Graphics Software Architecture>

[0199] 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute within the system memory 1050 of the data processing system.

[0200] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language such as Direct3D's High-Level Shader Language (HLSL), OpenGL Shader Language (GLSL), etc. The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0201] In some embodiments, the operating system 1020 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX®-like operating system, or an open source UNIX-like operating system that uses a variant of the Linux® kernel. The operating system 1020 can support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is used, the operating system 1020 uses a front-end compiler 1024 to compile any shader instructions 1012 in HLSL into a low-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform shader precompilation. In some embodiments, the high-level shaders are compiled into low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0202] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 communicates with a kernel mode graphics driver 1029 using operating system kernel mode functions 1028. In some embodiments, the kernel mode graphics driver 1029 communicates with a graphics processor 1032 to dispatch commands and instructions.

[0203] <IP Core Implementation>

[0204] One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions that represent various logic within the processor. When read by a machine, the instructions may cause the machine to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible machine-readable medium, such as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities that load the hardware model onto manufacturing machines that fabricate the integrated circuit. The integrated circuit may be fabricated to perform the operations described in connection with any of the embodiments described herein.

[0205] FIG. 11A is a block diagram illustrating an example IP core development system 1100 that may be used to fabricate an integrated circuit for performing operations according to one embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 may be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be generated or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers with associated logic that is implemented using the modeled digital signals. In addition to the RTL design 1115, a logic level or transistor level low level design may also be generated, designed, or synthesized, and therefore the specific details of the initial design and simulation may vary.

[0206] The RTL design 1115 or equivalent may be further synthesized by the design facility into a hardware model 1120. The hardware model 1120 may be a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for distribution to a third party manufacturing facility 1165. Alternatively, the IP core design may be transmitted via a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0207] 11B illustrates a side cross-sectional view of an integrated circuit package component 1170 according to some embodiments described herein. The integrated circuit package component 1170 illustrates one implementation of one or more processors or accelerator devices as described herein. The package component 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be implemented at least in part in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include interconnect structures such as, but not limited to, bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is a resin-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package component 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0208] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides routes for the electrical signals. The bridge 1182 may include a bridge substrate made of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0209] Although one logic unit 1172, 1174 and bridge 1182 are shown, the embodiments described herein may include more or less logic units on one or more dies. One or more dies may be connected by zero or more bridges, and bridge 1182 may be eliminated when the logic is contained on a single die. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

[0210] FIG. 11C illustrates a package component 1190 that includes multiple units of hardware logic chiplets connected to a substrate 1180 (e.g., a base die). Graphics processing units, parallel processors, and / or computational accelerators as described herein may be composed of multiple silicon chiplets that are manufactured individually. In this context, a chiplet is an at least partially packaged integrated circuit that includes individual logic units that can be assembled into a larger package with other chiplets. Multiple sets of chiplets with different IP core logic can be assembled into a single device. Furthermore, chiplets can be combined into a base die or base chiplet using active interposer technology. The concepts described herein allow interconnection and communication between different types of IP within a GPU. IP cores can be manufactured using different process technologies and can be configured during manufacturing. This avoids the complexity of combining multiple IPs in the same manufacturing process, especially on a large SoC with several types of IP. Enabling the use of multiple process technologies improves time to market and provides a cost-effective way to generate multiple product SKUs. Additionally, decentralized IP can be further modified to be independently power controlled, so that components not being used in a given workload can be powered off, reducing overall power consumption.

[0211] The hardware logic chiplets may include dedicated hardware logic chiplets 1172, logic or I / O chiplets 1174, and / or memory chiplets 1175. The hardware logic chiplets 1172 and logic or I / O chiplets 1174 may be implemented at least in part in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor cores, graphics processors, parallel processors, or other accelerator devices described herein. The memory chiplets 1175 may be DRAM (e.g., GDDR, HBM) memory or cache (SRAM) memory.

[0212] Each chiplet may be fabricated as an individual semiconductor die and coupled to substrate 1180 via interconnect structures 1173. Interconnect structures 1173 may be configured to route electrical signals between the various chiplets and logic within substrate 1180. Interconnect structures 1173 may include interconnects such as, but not limited to, bumps or pillars. In some embodiments, interconnect structures 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with operation of the logic, I / O, and memory chiplets.

[0213] In some embodiments, the substrate 1180 is a resin-based laminate substrate. The substrate 1180 may include other suitable types of substrates in other embodiments. The package components 1190 may be connected to other electrical devices via package interconnects 1183. The package interconnects 1183 may be coupled to a surface of the substrate 1180 for routing electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0214] In some embodiments, the logic or I / O chiplets 1174 and the memory chiplets 1175 may be electrically coupled via a bridge 1187 configured to route electrical signals between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may be a high density interconnect structure that provides a route for the electrical signals. The bridge 1187 may include a bridge substrate made of glass or a suitable semiconductor material. Electrical routing features may be formed on the bridge substrate to provide inter-chip connections between the logic or I / O chiplets 1174 and the memory chiplets 1175. The bridge 1187 may also be referred to as a silicon bridge or an interconnect bridge. For example, the bridge 1187 is an Embedded Multi-die Interconnect Bridge (EMIB) in some embodiments. In some embodiments, the bridge 1187 may simply be a direct connection from one chiplet to another.

[0215] Substrate 1180 may include hardware components for I / O 1191, cache memory 1192, and other hardware logic 1193. Fabric 1185 may be embedded within substrate 1180 to enable communication between the various logic chiplets and logic 1191, 1193 within substrate 1180. In one embodiment, I / O 1191, fabric 1185, cache, bridges, and other hardware logic 1193 may be integrated into a base die stacked on top of substrate 1180.

[0216] In various embodiments, package part 1190 may include fewer or more components and chiplets interconnected by fabric 1185 or one or more bridges 1187. Chiplets in package part 1190 may be arranged in a 3D or 2.5D configuration. Typically, bridge structures 1187 may be used to facilitate point-to-point interconnections between, for example, logic or I / O chiplets and memory chiplets. Fabric 1185 may be used to interconnect various logic and / or I / O chiplets (e.g., chiplets 1172, 1174, 1191, 1193) with other logic and / or I / O chiplets. In one embodiment, cache memory 1192 in the substrate may operate as a global cache for package part 1190, a portion of a distributed global cache, or a dedicated cache for fabric 1185.

[0217] 11D illustrates a package component 1194 including interconnectable chiplets 1195, according to one embodiment. The interconnectable chiplets 1195 can be assembled into standardized slots on one or more base chiplets 1196, 1198. The base chiplets 1196, 1198 can be coupled via a bridge interconnect 1197, which can be, for example, an EMIB, similar to other bridge interconnects described herein. Memory chiplets can also be connected to logic or I / O chiplets via a bridge interconnect. I / O and logic chiplets can communicate via an interconnect fabric. The base chiplets can each support one or more slots in a standardized format for one of logic or I / O or memory / cache.

[0218] In one embodiment, the SRAM and power distribution circuitry may be fabricated in one or more of the base chiplets 1196, 1198, which may be fabricated using a different process technology than the interconnectable chiplets 1195 stacked on top of the base chiplets. For example, the base chiplets 1196, 1198 may be fabricated using a larger process technology, while the interconnectable chiplets may be fabricated using a smaller process technology. One or more of the interconnectable chiplets 1195 may be memory (e.g., DRAM) chiplets. Different memory densities may be selected for the package parts 1194 based on the power and / or performance targeted for the product using the package parts 1194. Furthermore, logic chiplets with different numbers of base unit types may be selected at assembly time based on the power and / or performance targeted for the product. Furthermore, chiplets containing different types of IP logic cores may be inserted into the interconnectable chiplet slots, enabling hybrid processor designs that can mix and match IP blocks of different technologies.

[0219] Exemplary System-on-Chip Integrated Circuits

[0220] 12-13 illustrate an example integrated circuit and associated graphics processor that may be manufactured using one or more IP cores according to various embodiments described herein. In addition to what is shown, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface processors / cores, or general purpose processor cores.

[0221] 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that may be manufactured using one or more IP cores, according to one embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPU), at least one graphics processor 1210, and may further include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, a UART controller 1230, a SPI / SDIO controller 1235, and an I2S / I2C controller 1240. Additionally, the integrated circuit includes a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 that includes a flash memory and a flash memory controller. A memory interface may be provided by memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits further include an embedded security engine 1270.

[0222] 13-14 are block diagrams illustrating an example graphics processor for use in an SoC, according to embodiments described herein. FIG. 13 illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to one embodiment. FIG. 14 illustrates an additional example graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores, according to one embodiment. The graphics processor 1310 of FIG. 13 is an example of a low-power graphics processor core. The graphics processor 1340 of FIG. 14 is an example of a high-power graphics processor core. Each of the graphics processors 1310, 1340 may be a variation of the graphics processor 1210 of FIG. 12.

[0223] As shown in FIG. 13, the graphics processor 1310 includes a vertex processor 1305 and one or more graph processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D-1315N-1, 1315N). The graphics processor 1310 can execute different shader programs with separate logic. As a result, the vertex processor 1305 is optimized to execute the operations of a vertex shader program, while one or more fragment processors 1315A-1315N execute the fragment (e.g., pixel) shading operations of a fragment or pixel shader program. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, fragment processors 1315A-1315N are optimized to execute fragment shader programs, such as those provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs, such as those provided in the Direct3D API.

[0224] The graphics processor 1310 further includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mapping to the graphics processor 1310, including the vertex processor 1305 and / or fragment processors 1315A-1315N, which may reference vertices or image / texture data stored in memory in addition to vertices or image / texture data stored in the one or more caches 1325A-1325B. In one embodiment, the one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1205, image processor 1215, and / or video processor 1220 of FIG. 12. As a result, each processor 1205-1220 can participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interact with other IP cores in the SoC via the SoC's internal bus or via direct connections, depending on the embodiment.

[0225] As shown in FIG. 14, the graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of the graphics processor 1310 of FIG. 13A. The graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F-1355N-1, 1355N) that provide a unified shader core architecture in which a single core or type or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. Additionally, graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N, and a tiling unit 1358 that accelerates tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, e.g., to exploit local spatial coherence within the scene or to optimize the use of internal caches. Apparatus and method for real-time graphics processing using local and cloud-based graphics processing resources

[0226] Although remote graphics servers can render image frames much faster than a typical user's gaming device, there are other challenges that can affect the real-time gaming user experience, such as network-induced latency and quality variations due to data compression. Certain types of games, such as augmented reality (AR) and virtual reality (VR) games, require high-performance networking platforms to achieve the necessary latency.

[0227] Embodiments of the present invention improve latency by separating the workload between a local GPU (e.g., for low-latency compute operations) and offloading other work to remote processing resources without requiring the graphics application to manage remote connections.

[0228] In one embodiment, remote GPU support is presented as a virtual graphics adapter within the operating system (e.g., as one or more "ghost" GPUs). Because of this integration, applications can use current graphics and compute APIs to access the ghost GPUs in the same way as they would a physical GPU. The local GPU is fully available when sufficient local compute is available, while in one embodiment, additional "ghost" GPUs are enabled when additional compute is required.

[0229] FIG. 15A illustrates one particular implementation in which the graphic processing resource 1500 includes multiple local physical GPUs 1505-1506 and multiple ghost GPUs 1515-1517 that couple the client 1502 to the remote processing resource 1525 via a network 1592. The ghost GPU 1560 may represent various types of pipelines, including, but not limited to, a rasterization pipeline, a machine learning pipeline, a ray tracing pipeline, a media pipeline, a copy pipeline, and a compute pipeline. Thus, the particular description below focuses on particular types of pipelines, but the underlying principles of the invention are not limited to any particular graphic processing resource. Additionally, the remote processing resource 1525 may include general-purpose processing resources such as CPUs (e.g., Xeon CPU, Core i7 CPU, etc.) and application-specific accelerators. For example, the ghost GPUs 1517-1515 may represent processing capabilities that the physical GPUs 1505-1506 do not natively support (e.g., ray tracing capabilities).

[0230] In one implementation, both the ghost GPUs 1515-1517 and the physical GPUs 1505-1506 are exposed to the application 1505 and / or the ghost GPU-aware scheduler 1510. In one embodiment, the application 1505: So Each may contain work for a different thread. Multiple The ghost GPU-aware scheduler 1510 manages multiple command buffers. The ghost GPU-aware scheduler 1510 (which may be a separate component shared by multiple applications rather than integrated into one application as shown in FIG. 15) intelligently schedules graphics work across the physical GPUs 1505-1506 and the ghost GPUs 1515-1517 based on the graphics processing capabilities and characteristics of the ghost and physical GPUs (e.g., differences in latency, graphics processing bandwidth, etc.). For example, if the physical GPUs 1505-1506 have sufficient graphics processing resources to adequately perform the requested graphics work, the ghost GPU-aware scheduler may send all work to the physical GPUs 1505-1506.

[0231] In one embodiment, at least a portion of the scheduling may be performed by remote processing resources (RPR) 1525. As shown in Figure 15B, local scheduler 1510 sends a work request including a batch of different types of work to ghost GPU 1560, which forwards the work to remote processing resources 1525. In one embodiment, the request includes a set of parameters and / or requirements for the work, such as minimum acceptable latency, resolution, accuracy, etc.

[0232] Resource manager 1550 sends an acknowledgment to ghost GPU 1560 indicating (1) that it will process all of the work according to the specified parameters / requirements, (2) that it will process part of the work according to the specified parameters / requirements, or (3) that it cannot process any of the work according to the parameters / requirements. For accepted work, resource manager 1550 schedules the work across the appropriate set of processing pipelines 1551-1556 (i.e., based on the type of work requested) and returns the results to ghost GPU 1560 upon completion. In the example shown in FIG. 15B, the processing pipelines include a rasterization pipeline 1551 that performs rasterization and / or related operations of graphical objects, a machine learning pipeline 1552 that performs machine learning operations (e.g., mixed precision fused multiply-add), a ray tracing pipeline 1553 that performs ray tracing operations (e.g., ray traversal, intersection, global illumination, etc.), a media pipeline 1554 for media processing (e.g., video encoding / decoding), a compute pipeline 1555 for general-purpose parallel computing operations, and a copy pipeline 1556 that performs bit block transfers and other copy operations.

[0233] Thus, in the embodiment shown in Figure 15B, at least a portion of the work scheduling is performed on the RPR 1525. Although only a single ghost GPU 1560 is shown in Figure 15B, multiple such ghost GPUs and associated remote processing resources may be used. For example, each of the ghost GPUs 1515-15157 of Figure 15A may be associated with a different set of processing resources on a different (or the same) cloud service that provides the RPR.

[0234] Returning to Figure 15A, in an environment where the physical GPUs 1505-1506 cannot adequately handle the graphics work, the ghost GPU-aware scheduler 1510 offloads some graphics work 1561 to the ghost GPU. In this case, the scheduler 1510 may subdivide the graphics work, scheduling latency-sensitive work 1560 to the physical GPU 1560 (because they are local and have no network-induced latency) and scheduling other graphics work to the ghost GPUs 1515-1516.

[0235] In one embodiment, the ghost GPUs 1515-1517 are made visible to the scheduler 1510 / application 1505 during the device enumeration phase. The scheduler 1510 / application 1505 then associates device instances with the ghost GPUs 1515-1517 and offload work 1561 is submitted to these instances. Thus, the "cloud" complexity of the ghost GPUs 1515-1517 is abstracted away from the application.

[0236] New advances in graphics processing technology enable more seamless integration of multiple GPUs. For example, new APIs such as DX12 and Vulkan expose multiple GPUs at the API level, providing applications 1505 with the flexibility to divide the workload at a much finer granularity. Additionally, the new APIs provide ways for applications 1505 to more efficiently manage command buffers, including asynchronous command buffer creation, command buffer recording / playback, and bundling. These features help reduce redundant command buffer creation in the previous API model.

[0237] 16 illustrates additional details of an embodiment in which application 1505 manages multiple threads. Each of the multiple threads is associated with one of multiple command buffers 1611A-D. Ghost GPU-aware scheduler 1510 assigns commands from command buffers 1611A-D to command queues 1615-1617 of ghost GPUs 1515-1517, respectively, and to command queue 1605 of physical GPU 1505 installed in client 1502. As discussed above, ghost GPU-aware scheduler 1510 attempts to send latency sensitive work to command queue 1605 of physical GPU 1505. In one embodiment, work sent to ghost GPU command queues 1615-1617, respectively, is sent by ghost GPUs 1515-1517 to a remote processing resource where the workload can be executed by an array of GPUs, CPUs and / or FPGAs. The results are returned to the application 1505 and / or physical GPU 1505 via ghost GPUs 1515-1517 on the client side. The results are then used to compose the final rendered frame in a frame buffer on the physical GPU 1505, and once complete, the physical GPU 1505 is instructed to display the frame on the local display 1590.

[0238] In one embodiment, the application 1505 is provided with full visibility of all GPUs, including virtual or "ghost" GPUs, during the GPU enumeration phase. The application can then create device objects on these ghost GPUs and access them as normal GPUs. In one embodiment, the application evaluates the overall latency by sending a workload to the ghost GPU instances and querying the execution time. Based on the measured latency, the application can split the workload across different GPUs and compose the final frame using the local GPU 1505. The results generated by the cloud-based graphics processing resource 1525 are returned to the virtual adapter associated with the ghost GPU. The application 1505 combines the results with the results generated by the local GPU 1505 on which the final frame was composed.

[0239] Alternatively, in one embodiment, the application 1505 is unaware of the disparate capabilities of the physical and virtual GPUs, and a ghost GPU-aware scheduler performs thread scheduling on behalf of the application.

[0240] Regardless of which entity performs the scheduling, in one embodiment, certain types of delay-tolerant tasks / threads may be offloaded to a ghost GPU, while delay-sensitive tasks / threads are queued for execution on the physical GPU. These delay-tolerant tasks / threads include (but are not limited to) those that are not updated every frame. One example is using remote processing resources to render dynamic reflection mapping (e.g., stereo map rendering from scratch of an object), which a game engine does not typically update every frame, but where the local GPU renders the remainder of the path to compose the final frame.

[0241] Below are examples of rendering techniques that are latency tolerant and therefore may be offloaded to a ghost GPU, according to embodiments of the present invention. Dynamic Environment Mapping (Reflection / Refraction) Indirect / global lighting (e.g. fixed light scenarios) Traditional game physics (corrosion, particle simulation, smoke, cloth simulation, hair simulation) Hybrid Ray Tracing AI-based approaches (e.g. character animation, game physics through reasoning) AI-based texture generation, model generation, terrain / map generation Precise spatial audio processing AI-based type conversion (e.g. one GPU is used for rendering and the other for type conversion) Fake rendering.

[0242] The graph in Figure 17 illustrates a scenario in which command buffers 1611A-D are submitted separately in parallel to each GPU 1515-1517, 1505 and synchronized by the local GPU 1505. The resulting frame time 1700 for generating the final frame using the results from the ghost GPUs 1515-1517 is also shown.

[0243] The ghost GPU described herein can be used by existing applications, deep learning frameworks, and rendering applications to take advantage of remote GPU capabilities by submitting GPU workloads to the ghost GPU's virtual graphics adapter.

[0244] In one embodiment, a profile is created by specifying the requirements and capabilities of a "ghost GPU," which may include latency values ​​(e.g., min / max latency values), bandwidth, computation, cost, and power. Once the profile is set, the ghost GPU-aware scheduler 1510 can send work to the edge / cloud-based "ghost GPU" in view of the capabilities and limitations of these GPUs.

[0245] While a 1:1 relationship of ghost GPU:cloud GPU may be appropriate for many workloads and programming models, cloud-side task distribution may perform a different allocation to schedule work across available machines and resources in the cloud. The allocation may be performed dynamically based on the characteristics of the work to be performed. Thus, in some embodiments, a 1:N (ghost GPU:cloud GPU) relationship may exist where N is any value, including fractional values ​​(to allocate the virtualized portion of the GPU).

[0246] In one embodiment, applications feed dependency graphs to ghost GPU command queues, or indirect execution kernels to generate cloud-side command buffers that can be submitted to the cloud queue. These techniques enable vendor-specific distribution (based on tiling, split rendering, alternate frame rendering, etc.) or user-guided submission schemes that produce and consume work in the cloud.

[0247] FIG. 18 illustrates one embodiment for the creation and use of ghost GPUs on a client machine. A GPU configuration and control module or application 1801 (e.g., a ghost GPU creation application) allows a user to specify ghost GPUs to a ghost GPU generator 1802. The ghost GPU generator 1802 communicates with an operating system 1803 to register three ghost GPUs in the system. In one embodiment, each ghost GPU includes a link to a cloud service. However, the registered ghost GPUs are treated as separate physical GPUs by the client's device manager 1810. In this example, three ghost GPU adapters 1811 are shown in the device manager 1810.

[0248] When an application 1505 requests access to graphics processing resources, the application can examine all available GPUs, including ghost GPUs 1811, during the GPU enumeration stage 1804. The application 1505 can then create device objects on these ghost GPUs 1811 and access them as normal GPUs. The application can evaluate the overall latency by sending workloads to the ghost GPU instances and querying the execution times.

[0249] A method according to one embodiment of the present invention is illustrated in Figure 19. The method may be implemented within the context of the architecture described above, but is not limited to any particular form or architecture.

[0250] At 1901, one or more ghost GPUs are registered and configured on a system that includes one or more physical GPUs. As described above, this may include installing virtual adapters or drivers associated with the ghost GPUs so that they appear as real GPUs in the system.

[0251] At 1902, ghost GPUs and physical GPUs are enumerated in the system (e.g., in response to an application). An application having multiple graphics threads is executed at 1903. As mentioned above, in some implementations, each graphics thread may be assigned its own command queue, which may be assigned to a particular GPU.

[0252] At 1904, performance parameters of the graphics thread are evaluated in terms of performance metrics associated with the ghost GPU. For example, the performance parameters may include an indication of a maximum latency and / or bandwidth requirement of the graphics thread, and the ghost GPU metrics may also include latency and / or bandwidth related data (e.g., Average delay / bandwidth, Based on current network conditions Current delay / bandwidth, etc.

[0253] Based on this evaluation, certain graphics threads are scheduled for execution on the ghost GPU at 1905. For example, if the ghost GPU can produce the results of the threads with acceptable latency, those threads may be scheduled to the ghost GPU, offloading work from the physical GPU. The remaining threads are scheduled on the physical GPU.

[0254] At 1906, the ghost GPU thread is offloaded to the specified cloud service where it is executed by graphics processing resources on the cloud service. As mentioned above, the graphics processing resources may include specialized hardware (e.g., ray traversal / intersection hardware, tensor execution hardware, global illumination hardware, etc.) and may include a CPU, a GPU, and / or an FPGA. The results are provided by the cloud service to the ghost GPU, which forwards the results to the application and / or the physical GPU. At 1907, the physical GPU uses the results to generate a final frame. The final frame is displayed on a local display device.

[0255] One advantage provided by these embodiments is that some tasks, such as ray tracing, which may sometimes be finely divided across computing resources, have a logical entity located on the cloud to facilitate load balancing. In a split rendering scenario, the application does not need to be aware of remote rendering support. Rather, the application only needs to know that a ghost GPU is present and understand the capabilities of the ghost GPU (e.g., processing metrics associated with various types of graphics processing, including latency).

[0256] In one embodiment of the present invention, an application utilizes a multi-GPU aware API, such as DX12 or Vulkan, to asynchronously generate command buffers and submit them to each GPU (either the local physical GPU or a ghost GPU).

[0257] As shown in FIG. 20A, a multi-layer architecture of ghost GPUs may be implemented. In particular, the client 2010 accesses processing resources of the edge service 2020 based on the ghost GPU configuration as described above. In this example, the client 2010 may include a local GPU and a ghost GPU, or may include only a ghost GPU (i.e., no local GPU hardware). As used herein, an "edge" service includes a remote service that is closest to the client 2010 in terms of network latency (e.g., hosted directly in the client's Internet Service Provider network or in the case of a cellular provider, a 5G network). In this embodiment, the edge service 2020 includes a physical GPU, but may also include ghost GPUs associated with remote processing resources in one or more cloud services 2030. With this architecture, a resource manager in the edge service 2020 may evaluate client requests to determine whether to perform processing itself or offload processing to processing resources in the cloud service 2030.

[0258] In any of the above-described embodiments, a "ghost GPU" or physical GPU may be a ghost or physical xPU. An xPU designates any type of processor (e.g., CPU, digital signal processing unit, tensor processing unit, ray processing unit, vector processing unit, etc.) for processing or offloading any type of data processing work to a remote processor. FIG. 20B illustrates an embodiment in which a client 2050 may be equipped with one or more ghost xPUs for offloading work and optionally one or more local xPUs (i.e., the client may or may not have a physical to perform processing work). Similarly, edge services 2060 may include local and ghost xPUs, and further up the hierarchy, cloud services 2070 may include local and ghost xPUs. For example, in one embodiment, a vector processing unit (VPU) on client 2010 allocates additional ghost xPUs to perform computational work similar to the VPU.

[0259] In one implementation, the resource manager makes this determination based on parameters and / or latency requirements associated with the client request. For example, if the edge service 2020 can process the request according to the specified parameters within the specified latency, it will offload the request to the cloud service 2030 if the latency would be exceeded. However, certain types of work where higher latency is tolerable and / or a dedicated platform (e.g., a quantized computing platform) is required may be offloaded to the cloud service 2030 via a ghost GPU configured on the edge service. In this manner, multiple tiers of processing resources and ghost GPUs may be configured to process work locally and to offload work that can be offloaded.

[0260] Further, additional tiers may be configured within the user's home. For example, a powerful server within the user's home may serve multiple clients. This server may include one or more ghost GPUs to offload work to the user's network provider. The network provider may perform all or part of the work and offload certain work to cloud services via its own ghost GPUs. Finally, each cloud service may itself include ghost GPUs to offload work to other cloud services.

[0261] Various parameters may be associated with each offload request. For example, the cost of using a remote processing resource may be evaluated in combination with delay and / or performance. For example, a request may specify a maximum delay, a minimum performance, and a maximum allowable cost value. A scheduler on the client 2010 or edge service 2020 may then determine how to distribute the work to meet the delay and performance requirements while minimizing cost.

[0262] As mentioned above, in addition to graphics tasks, embodiments of the present invention may offload other types of tasks, including (but not limited to) ray tracing operations and machine learning operations. The remainder of this patent application provides specific examples of these additional types of tasks. <Ray tracing using machine learning>

[0263] As mentioned above, ray tracing is a graphics processing technique in which light transport is simulated through physically based rendering. One of the main operations in ray tracing is processing visibility queries that require traversal and intersection testing of nodes in a bounding volume hierarchy (BVH).

[0264] Ray and path tracing based techniques compute images by tracing rays and paths through each pixel and using random sampling to compute advanced effects such as shadows, gloss, indirect lighting, etc. Using only a small number of samples is fast but produces noisy images, while using a large number of samples produces high quality images but is cost prohibitive.

[0265] Machine learning includes any circuitry, program code, or combination thereof that is capable of progressively improving the performance of a specified task or progressively rendering a more accurate prediction or decision. Some machine learning engines can perform tasks or render predictions / decisions without being explicitly programmed to perform these tasks or render these predictions / decisions. There are a variety of machine learning techniques, including (but not limited to) supervised and semi-supervised learning, unsupervised learning, and reinforcement learning.

[0266] In recent years, a breakthrough solution for ray / path tracing for real-time use has emerged in the form of "denoising", a process that uses image processing techniques to generate high-quality filtered / denoised images from noisy, low-sample inputs. The most efficient denoising techniques rely on machine learning techniques, where the machine learning engine learns what the noisy image is likely to look like if it were computed with more samples. In one particular implementation, the machine learning is performed by a convolutional neural network (CNN), although the underlying principles of the invention are not limited to CNN implementations. In one such implementation, training data is generated with low-sample inputs and a ground-truth. The CNN is trained to predict converged pixels from a neighborhood of noisy pixel inputs around the pixel in question.

[0267] While not perfect, this AI-based denoising technique has proven surprisingly effective. Note, however, that good training data is required, as otherwise the network may predict erroneous results. For example, if an animation movie studio trains a denoising CNN on past movies with land scenes, and then tries to use the trained CNN to denoise frames from a new movie set on water, the denoising operation will not perform optimally.

[0268] To solve this problem, an embodiment of the present invention continuously trains a machine learning engine such as a CNN based on currently running data while dynamically collecting and rendering training data, thus continuously improving the machine learning engine for near future tasks. The embodiment may still perform a training phase before runtime, but continues to adjust the machine learning weights as needed during runtime. Furthermore, the embodiment avoids the high cost of computing reference data required for training by limiting the generation of training data to a sub-region of the image every frame or every N frames. In particular, a noisy input of a frame is generated to denoise the complete frame by the current network. Furthermore, as described below, a small region of reference pixels is generated and used for successive training.

[0269] Although a CNN implementation is described with respect to a particular embodiment, any type of machine learning engine may be used, including, without limitation, systems that perform supervised learning (e.g., building a mathematical model of a dataset that includes both the input and the desired output), unsupervised learning (e.g., evaluating input data for a particular type of structure), and / or a combination of supervised and unsupervised learning.

[0270] Existing denoising implementations operate in a training phase and a runtime phase. During the training phase, a network topology is defined that receives an NxN pixel region with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive ID, and reflectance, and generates the final pixel color. A set of "representative" training data is generated using a frame's worth of low sample count inputs, and with a reference to a "desired" pixel color calculated with a very high sample count. The network is trained towards these inputs, generating a set of "ideal" weights for the network. In these implementations, the reference data is used to train the network weights to most closely match the network's output to the desired result.

[0271] At runtime, given pre-computed ideal network weights are loaded and the network is initialized. For each frame, a low-sample image of the denoised input (i.e., the same one used for training) is generated. For each pixel, a given neighborhood of the pixel's input is run through the network to predict the "denoised" pixel color, producing a denoised frame.

[0272] Figure 21 illustrates one embodiment of an initial training implementation. A machine learning engine 2100 (e.g., a CNN) receives an NxN pixel region as high sample count image data 1702 with various per-pixel data channels such as pixel color, depth, normal, normal deviation, primitive ID, and reflectance, and generates the final pixel color. Representative training data is generated using one frame's worth of low sample count inputs 2101. The network is trained on these inputs to generate a set of "ideal" weights 2105 that the machine learning engine 2100 later uses to denoise the low sample count image at runtime.

[0273] To improve upon the above technique, an embodiment of the present invention enhances the denoising stage to generate new training data for every frame or subset of frames (e.g., every N frames, where N=2, 3, 4, 10, 25, etc.). In particular, as shown in FIG. 22, the embodiment selects one or more regions in each frame, referred to herein as "new reference regions" 2202. These are rendered at a high sample count into a separate high sample count buffer 2204. The low sample count buffer 1603 stores the low sample count input frame 2201 (including the low sample count regions 2204 that correspond to the new reference regions 2202).

[0274] In one embodiment, the position of the new reference region 2202 is selected randomly, or alternatively, the position of the new reference region 2202 may be adjusted in a pre-specified manner for each new frame (e.g., with a pre-defined movement of the region between frames, confined to a designated region in the center of the frame, etc.).

[0275] Regardless of how a new reference region is selected, it is used by the machine learning engine 2200 to continuously refine and update the trained weights 2205 used for denoising. In particular, the reference pixel color from each new reference region 2202 and the noisy reference pixel from the corresponding low sample count region 2207 are rendered. Then, in the machine learning engine 2200, additional training is performed using the high sample count reference region 2202 and the corresponding low sample count region 2207. In contrast to the initial training, this training is performed continuously for each new reference region 2202 during runtime, thereby ensuring that the machine learning engine 2200 is trained accurately. For example, per-pixel data channels (e.g., pixel color, depth, normal, normal deviation, etc.) that the machine learning engine 2200 uses to make adjustments to the trained weights 2205 may be evaluated. As in the training case (FIG. 21), the machine learning engine 2200 is trained towards a set of ideal weights 2205 for removing noise from low-sample count input frames 2201 to produce denoised frames 2220. However, in this embodiment, the trained weights 2205 are continually updated based on new image characteristics of new types of low-sample count input frames 2201.

[0276] In one embodiment, the retraining operations performed by the machine learning engine 2200 are executed simultaneously in a background process on a graphics processor unit (GPU) or host processor. A render loop, which may be implemented as a driver component and / or a GPU hardware component, continuously generates new training data (e.g., in the form of new reference regions 2202) that it places in a queue. A background training process running on the GPU or host processor continuously reads new training data from this queue and retrains the machine learning engine 2200, updating it with new weights 2205 at appropriate intervals.

[0277] 23 illustrates an example of one implementation in which the background training process 2300 is implemented by the host CPU 1710. In particular, in this embodiment, the background training process 2300 uses new reference regions 2202 with high sample counts and corresponding low sample regions 2204 to continuously update the trained weights 2205, thereby updating the machine learning engine 2200.

[0278] As shown in FIG. 24A, in one implementation, such as in a multi-player online game, different host machines 2420-2422 individually generate reference regions that background training processes 1700A-C send to a server 2400 (e.g., a game server). The server 2400 then uses the new reference regions received from each of the hosts 2421-2422 to train the machine learning engine 2410 and update the weights 2405 as described above. The server 2400 sends the weights 2405 to the host machine 2420 which stores the weights 2205A-C, thereby updating each individual machine learning engine (not shown). The server 2400 can be provisioned with a large number of reference regions in a short period of time, allowing it to efficiently and accurately update the weights for any given application (e.g., an online game) being run by a user.

[0279] As shown in FIG. 24B, different host machines may generate new trained weights (e.g., based on training / reference domain 2202 as described above) and share the new trained weights with server 2400 (e.g., game server), or alternatively, use a peer-to-peer sharing protocol. A machine learning management component 2410 on the server generates a set of combining weights 2405 using the new weights received from each of the host machines. The combining weights 2405 may be, for example, an average generated from the new weights and may be continuously updated as described herein. Once generated, copies of combining weights 2205A-C may be transmitted and stored to each of the host machines 2420-2421. The host machines 2420-2421 may then use the combining weights to perform denoising operations, as described herein.

[0280] In one embodiment, this semi-closed loop update mechanism can be used by hardware manufacturers. For example, the reference network may be included as part of a driver distributed by the hardware manufacturer. As the driver generates new training data using the techniques described herein and continuously submits them to the hardware manufacturer, the hardware manufacturer uses this information to continue improving its machine learning implementation for the next driver update.

[0281] In one implementation (e.g., rendering a batch of movies on a render farm), the renderer sends newly generated training regions to a dedicated server or database (within the studio's render farm) that collects this data from multiple render nodes over time. A separate process on a separate machine continuously improves the studio's dedicated denoising network, and new render jobs always use the most recently trained network.

[0282] A method according to one embodiment of the present invention is illustrated in Figure 25. The method may be implemented on the architectures described herein, but is not limited to any particular system or graphics processing architecture.

[0283] At 2501, as part of an initial training stage, low and high sample count image data are generated for a number of image frames. At 2502, a machine learning denoising engine is trained using the high / low sample count image data. In one embodiment, for example, a set of convolutional neural network weights associated with pixel features may be updated following the training. However, any machine learning architecture may be used.

[0284] At runtime, at 2503, the low sample count image frames are generated along with at least one reference region having a high sample count. At 2504, the high sample count reference regions are used by the machine learning engine and / or separate training logic (e.g., background training module 2300) to continually refine the training of the machine learning engine. For example, in one embodiment, the high sample count reference regions are used in combination with corresponding portions of the low sample count image to continue to teach the machine learning engine 1904 how to most efficiently perform denoising. In a CNN implementation, for example, this may include updating weights associated with the CNN.

[0285] Variations of the above-described embodiments may be implemented, such as the manner in which the feedback loop to the machine learning engine is configured, the entity that generates the training data, the manner in which the training data is fed back to the training engine, and the manner in which the improved network is provided to the rendering engine. Furthermore, while the above-described embodiment performs continuous training using a single reference region, multiple reference regions may be used. Furthermore, as mentioned above, the reference regions may be of different sizes, may be used on different numbers of image frames, and may be positioned at different locations within the image frames using different techniques (e.g., randomly, according to a predetermined pattern, etc.).

[0286] Furthermore, although a convolutional neural network (CNN) has been described as an example of the machine learning engine 2200, the underlying principles of the present invention may be implemented using any type of machine learning engine capable of continuously refining its results with new training data. By way of example, and not limitation, other machine learning implementations include group method of data handling (GMDH), long short-term memory, deep reservoir computation, deep belief network (DBN), tensor deep stacked network, and deep predictive coding network (Deep PredNet), to name a few. <Apparatus and method for efficient dispersion noise removal>

[0287] As mentioned above, denoising has become real-time ray tracing with smooth, low noise images being a key feature. Rendering can be done across a distributed system of multiple devices, but to date, existing denoising frameworks all run on a single instance on a single machine. When rendering is done across multiple devices, they may not have all the rendered pixels accessible to compute the denoised portion of the image.

[0288] One embodiment of the present invention includes a distributed denoising algorithm that works with both artificial intelligence (AI) and non-AI based denoising techniques. Regions of an image are either already distributed across nodes from a distributed rendering operation, or are split and distributed from a single frame buffer. Ghost regions of neighboring regions needed to compute sufficient denoising are collected from neighboring nodes when necessary, and the resulting tiles are composited into the final image. <Distributed processing>

[0289] Figure 26 illustrates one embodiment of the present invention in which multiple nodes 2621-2623 perform rendering. Although only three nodes are shown for simplicity, the underlying principles of the present invention are not limited to any number of nodes. In fact, a single node may be used to implement a particular embodiment of the present invention.

[0290] Each of the nodes 2621-2623 renders a portion of the image, resulting in regions 2611-2613 in this example. Although rectangular regions 2611-2613 are shown in FIG. 26, regions of any shape may be used and any device may process any number of regions. The regions required by a node to perform a sufficiently smooth denoising operation are called ghost regions 2611-2613. In other words, the ghost regions 2601-2603 represent the total data required to perform denoising at a specified level of quality. A decrease in the quality level reduces the size of the ghost regions and therefore the amount of data required, while an increase in the quality level increases the ghost regions and the corresponding required data.

[0291] In one embodiment, if a node, such as node 2621, has a local copy of the portion of ghost region 2601 necessary to denoise its region 2611 at a specified level of quality, the node reads the necessary data from one or more "neighboring" nodes, such as node 2622, which also owns the portion of ghost region 2601 as shown. Similarly, if node 2622 has a local copy of the portion of ghost region 2602 necessary to denoise its region 2612 at a specified level of quality, node 2622 reads the necessary ghost region data 2632 from node 2621. The read may be performed over a bus, interconnect, high-speed memory fabric, network (e.g., fast Ethernet), or even an on-chip interconnect in a multi-core chip that can distribute the rendering network among multiple cores (e.g., used to render very high resolution or large time-varying images). In one embodiment, each node 2621-2623 includes an individual execution unit or a designated set of execution units within the graphics processor.

[0292] The particular amount of data to be transmitted depends on the denoising technique being used. Additionally, the data from the ghost regions may include any data necessary to improve the denoising of each region. In one embodiment, for example, the ghost region data includes image color / wavelength, intensity / alpha data, and / or normals. However, the underlying principles of the present invention are not limited to any particular ghost region data set. Additional Details of an Embodiment

[0293] For slow networks or interconnects, existing general purpose lossless or lossy compression can be used to compress this data. Examples include, but are not limited to, zlib, gzip, and LZMA (Lempel-Ziv-Markov chain algorithm). Content-specific compression may also be used, noting that when the delta in ray hit information between frames becomes very coarse and a node already has a delta collected from a previous frame, only samples that contribute to the delta need to be sent. These can be selectively pushed to node i that collects those samples, or node i can request samples from other nodes. In one embodiment, lossless compression is used for certain types of data and program code, while lossy compression is used for other types of data.

[0294] 27 illustrates additional details of the interactions between the nodes 2621-2622, according to one embodiment of the present invention. Each node 2621-2622 includes ray tracing rendering circuitry 2681-2682 that renders the respective image regions 2611-2612 and ghost regions 2601-2602. The denoisers 2700-2711 perform denoising operations on the regions 2611-2012 that each node 2621-2622 is responsible for rendering and denoising. The denoisers 2621-2622 may include, for example, circuitry, software, or any combination thereof, to generate the respective denoised regions 2721-2722. As described above, when generating denoised regions, denoisers 2621-2622 may need to rely on data in ghost regions owned by different nodes (e.g., denoiser 2700 may need data from ghost region 2602 owned by node 2622).

[0295] Thus, in one embodiment, the denoisers 2700-2711 generate denoised regions 2721-2722, respectively, using data from the regions 2611-2612 and the ghost regions 2601-2602, at least some of which may be received from other nodes. The region data managers 2701-2702 manage the transfer of data from the ghost regions 2601-2602, as described herein. In one embodiment, the compression / decompression units 2731-2732 perform compression and decompression of ghost region data exchanged between the nodes 2621-2622, respectively.

[0296] For example, region data manager 2701 of node 2621 may send data from ghost region 2601 to compressor / decompressor 2731 upon request from node 2622. Compressor / decompressor 2731 compresses the data to generate compressed data 2706 for transmission to node 2622, thereby reducing bandwidth on the interconnect, network, bus, or other data communication link. Compressor / decompressor 2732 of node 2622 then decompresses compressed data 2706, and denoiser 2711 uses the decompressed ghost data to generate a higher quality denoised region 2612 than would be possible with only the data from region 2612. Region data manager 2702 stores the decompressed data from ghost region 2601 in a cache, memory, register file, or other storage device to make it available to denoiser 2711 when generating denoised region 2722. A similar set of operations may be performed to provide data from ghost region 2602 to a denoiser 2700 on node 2621, which uses that data along with data from region 2011 to produce a higher quality denoised region 2721. <grab data or render>

[0297] If the connections between devices such as nodes 2621-2622 are slow (i.e., below a threshold latency and / or threshold bandwidth), it may be faster to render the ghost region locally rather than requesting results from other devices. This can be determined at run-time by tracking the network transaction rate and the linear estimated rendering time for the ghost region size. If it is faster to render the entire ghost region, then the subject devices may end up rendering the same portion of the image. The resolution of the rendered portion of the ghost region may be adjusted based on the variance of the fundamental region and the determined degree of blurring. <Load balance>

[0298] In one embodiment, static and / or dynamic load balancing schemes may be used to distribute the processing load among the various nodes 2621-2623. In dynamic load balancing, the variance determined by the denoising filter drives the amount of samples used to render certain regions of the scene, with low variance and blurry regions of the image requiring more time for denoising but fewer samples. The particular regions assigned to a particular node may be dynamically adjusted based on data from previous frames, or dynamically communicated between devices so that all devices have the same amount of work as they render.

[0299] 28 illustrates an embodiment in which monitors 2801-2802 running on each node 2621-2622 collect performance metric data including, but not limited to, the time consumed to transmit data over network interfaces 2811-2812, the time consumed in denoising the regions (with and without ghost region data), and the time consumed to render each region / ghost region. The monitors 2801-2802 report these performance metrics to a manager or load balancing node 2801. The manager or load balancing node 2801 analyzes the data to identify the current workload of each node 2621-2622 and possibly determine a more efficient mode of processing the various denoised regions 2721-2722. The manager node 2801 then distributes new workload for new regions to the nodes 2621-2622 according to the detected load. For example, manager node 2801 may send more work to nodes that are less heavily loaded and / or reallocate work from overloaded nodes. Additionally, load balancing node 2801 may send reconfiguration commands to adjust the particular way in which rendering and / or denoising is performed by each of the nodes (some examples are described above). <Ghost area determination>

[0300] In one embodiment, the size and shape of the ghost regions 2601-2602 are determined based on a denoising algorithm implemented by the denoising units 2700-2711. Their individual sizes may then be dynamically changed based on the detected variance of the samples being denoised. A learning algorithm used for the AI ​​denoising itself may be used to determine the appropriate region size, or in other cases, such as bidirectional blur, a predefined filter width determines the size of the ghost regions 2601-2602. In an implementation using a learning algorithm, a machine learning engine may run on the manager node 2801 and / or parts of the machine learning may run on each of the individual nodes 2621-2623 (see, for example, FIGS. 24A-B and related discussion above). <Collecting the final image>

[0301] In one embodiment, the final image does not require ghost regions or normals and is assembled by collecting the rendered denoised regions from each of the nodes 2621-2623. In FIG. 28, for example, the denoised regions 2721-2722 are sent to the region processor 2680 of the manager node 2601. The region processor 2680 combines the regions to generate the final denoised image 2690. The image 2690 is then displayed on the display 2890. The region processor 2280 may combine the regions using various 2D compositing techniques. Although shown as separate components, the region processor 2680 and the denoised image 2690 may be integrated into the display 2890. In this embodiment, the various nodes 2621-2622 may transmit the denoised regions 2721-2722 using direct transmission techniques, possibly using various lossy or lossless compression of the region data.

[0302] AI denoising remains a costly operation as games move to the cloud. Thus, distributing the processing of denoising across multiple nodes 2621-2622 may be necessary to achieve real-time frame rates for traditional games or virtual reality (VR) that demand higher frame rates. Movie studios also render on large render farms that can take advantage of faster denoising.

[0303] One embodiment of a method for performing distributed rendering and denoising is shown in Figure 29. The method may be implemented within the context of the system architectures described above, but is not limited to any particular system architecture.

[0304] At 2901, graphics work is dispatched to multiple nodes that perform ray tracing operations to render regions of an image frame. In one embodiment, each node may already have the necessary data to perform the operations in memory. For example, two or more nodes may share a common memory, or the local memory of a node may already store data from a previous ray tracing operation. Alternatively or additionally, specific data may be sent to each node.

[0305] At 2902, a "ghost region" required for a specified level of noise reduction (i.e., an acceptable performance level) is determined. The ghost region includes any data required to perform the specified level of noise reduction, including data owned by one or more other nodes.

[0306] Data relating to the ghost regions (or portions thereof) is exchanged between the nodes at 2903. At 2904, each node performs denoising on its respective region (e.g., using the exchanged data), and at 2905 the results are combined to generate a final denoised image frame.

[0307] In one embodiment, a manager node or primary node, such as that shown in FIG. 28, dispatches work to the nodes and then combines the work performed by the nodes to generate the final image frame. In another embodiment, a peer-based architecture is used, where the nodes are peers that exchange data for rendering and denoising the final image frame.

[0308] The nodes described herein (e.g., nodes 2621-2623) may be graphic processing computing systems interconnected via a high speed network. Alternatively, the nodes may be individual processing nodes coupled to a high speed memory fabric. In this embodiment, all of the nodes may share a shared virtual memory space and / or a shared physical memory. In another embodiment, the nodes may be a combination of a CPU and a GPU. For example, the manager node 2801 described above may be a CPU and / or software running on the CPU, and the nodes 2621-2622 may be a GPU and / or software running on the GPU. A variety of different types of nodes may be used while still adhering to the basic principles of the present invention. <Example Neural Network Implementation>

[0309] Although there are many types of neural networks, a simple type of neural network is a feedforward network. A feedforward network may be implemented as an acyclic graph with nodes organized into layers. Typically, a feedforward network topology includes an input layer and an output layer separated by at least one hidden layer. The hidden layer converts the inputs received by the input layer into a representation that is useful for generating outputs at the output layer. The network nodes are fully connected to the nodes in adjacent layers via edges, but there are no edges between the nodes within each layer. Data received at the nodes in the input layer of a feedforward network is propagated to the nodes in the output layer (i.e., "forward propagation") through an activation function that calculates the state of the nodes in each successive layer in the network based on the coefficients ("weights") associated with each of the edges connecting the layers. Depending on the particular model being represented by the algorithm being executed, the output from a neural network algorithm may take a variety of forms.

[0310] Before a machine learning algorithm can be used to model a particular problem, the algorithm is trained using a training dataset. Training a neural network involves selecting a network topology, using a training dataset that represents the problem to be modeled by the network, and adjusting weights until the network model performs with minimal error for all instances of the training dataset. For example, during a supervised learning training process for a neural network, outputs generated by the network in response to inputs representing instances in the training dataset are compared with "correctly" labeled outputs of the instances, an error signal representing the difference between the outputs and the labeled outputs is calculated, and weights associated with the connections are adjusted to minimize the error when the error signal is backpropagated through the layers of the network. The network is considered "trained" when the error is minimized for each output generated from an instance of the training dataset.

[0311] The accuracy of machine learning algorithms can be greatly affected by the quality of the data set used to train the algorithm. The training process is computationally intensive and can require a significant amount of time in traditional general-purpose processors. Therefore, parallel processing hardware is used to train many types of machine learning algorithms. This is particularly useful for optimizing the training of neural networks, since the calculations performed in adjusting the coefficients in the neural network are themselves suitable for parallel implementation. In particular, many machine learning algorithms and software applications are adapted to take advantage of parallel processing hardware in general-purpose graphics processing units.

[0312] 30 is a generalized diagram of a machine learning software stack 3400. A machine learning application 3402 can be configured to train a neural network using a training dataset or to implement machine intelligence using a trained deep neural network. The machine learning application 3402 may include training and inference functions for the neural network and / or specialized software that can be used to train the neural network before deployment. The machine learning application 3402 can implement any type of machine intelligence, including, but not limited to, image recognition, mapping and localization, automated navigation, speech synthesis, medical imaging, or language translation.

[0313] Hardware acceleration for machine learning applications 3402 can be enabled by the machine learning framework 3404. The machine learning framework 3404 can provide a library of machine learning primitives. Machine learning primitives are basic operations typically performed by machine learning algorithms. Without the machine learning framework 3404, developers of machine learning algorithms would need to generate and optimize the main computation logic associated with the machine learning algorithm, and then re-optimize the computation logic as new parallel processors are developed. In contrast, machine learning applications can be configured to perform the required computations using primitives provided by the machine learning framework 3404. Exemplary primitives include tensor convolution, activation functions, and pooling, which are computational operations performed while training a convolutional neural network (CNN). The machine learning framework 3404 can also provide primitives for implementing basic linear algebra subprograms performed by many machine learning algorithms, such as matrix and vector operations.

[0314] The machine Kush framework 3404 can process the input data received from the machine learning application 3402 and generate an appropriate input to the computing framework 3404. The computing framework 3406 abstracts the basic instructions provided to the GPGPU driver 3408 so that the machine learning framework 3404 can utilize hardware acceleration via the GPGPU hardware 3410, and the machine learning framework 3404 does not need to have detailed knowledge of the GPGPU hardware 3410. Further, the computing framework 3406 can enable hardware acceleration of the machine learning framework 3404 and generation of the GPGPU hardware 3410 across various types.

[0315] <GPGPU Machine Learning Acceleration>

[0316] FIG. 31 illustrates a multi-GPU computing system 3100 according to one embodiment. The multi-GPU computing system 3100 may include a processor 3102 coupled to a plurality of GPGPUs 3106A-D via a host interface switch 3104. The host interface switch 3104, in one embodiment, is a PCI Express switch device that couples the processor 3102 to a PCI Express bus. Through the PCI Express bus, the processor 3102 may communicate with a set of GPGPUs 3106A-D. Each of the plurality of GPGPUs 3106A-D may be an instance of a GPGPU as described above. The GPGPUs 3106A-D may be interconnected via a set 3116 of high speed point-to-point inter-GPU links. The high speed inter-GPU links may be connected to each of the GPGPUs 3106A-D via dedicated GPU links. The P2P GPU link 3116 allows direct communication between each of the GPGPUs 3106A-D, without requiring communication through the host interface bus to which the processor 3102 is connected. Because inter-GPU traffic is directed to the P2P GPU link, the host interface bus remains available for system memory access or for communicating with other instances of the multi-GPU computing system 3100, for example, via one or more network devices. In the illustrated embodiment, the GPGPUs 3106A-D connect to the processor 3102 through the host interface switch 3104, although in one embodiment, the processor 3102 includes direct support for the P2P GPU link 3116 and can connect directly to the GPGPUs 3106A-D.

[0317] <Implementation of machine learning neural network>

[0318] The computing architecture provided by the embodiments described herein can be configured to perform a type of parallel processing that is particularly suitable for training and deploying neural networks for machine learning. A neural network can be generalized as a network of functions with graph relationships. As is well known in the art, various types of neural network implementations are used in machine learning. One exemplary neural network is the feedforward network described above.

[0319] A second exemplary type of neural network is the Convolutional Neural Network (CNN). A CNN is a forward-propagation neural network dedicated to processing data with a known grid-like topology, such as image data. Thus, CNNs are commonly used for computer vision and image recognition applications, but may also be used for other types of pattern recognition, such as speech and language processing. The nodes in the CNN input layer are organized into a set of "filters" (feature detectors inspired by receptive fields in the retina), and the output of each filter set is propagated to nodes in successive layers of the network. Computation for a CNN involves applying a convolution arithmetic operation to each filter to generate the filter's output. Convolution is a special type of arithmetic operation performed by two functions to generate a third function that is a modified version of one of the two original functions. In convolutional network terminology, the first function to the convolution may be called the input, and the second function may be called the convolution kernel. The output may be called a feature map. For example, the input to a convolutional layer may be a multidimensional array of data that defines the various color components of the input image. A convolution kernel is a multidimensional array of parameters, which are adapted through the training process of the neural network.

[0320] Recurrent neural networks (RNNs) are a family of feed-forward neural networks that contain feedback connections between layers. RNNs allow for the modeling of sequential data by sharing parameter data across different parts of the neural network. The architecture for RNNs includes cycles. At least a portion of the output data from the RNN is used as feedback to process later inputs in the sequence, so the cycles represent the influence of a variable's current value on the future value of that variable. This feature makes RNNs particularly useful for language processing due to the changing nature in which language data can be structured.

[0321] The figures described below show exemplary feedforward CNN and RNN networks and explain the general process of training and deploying each of these types of networks, respectively, with the understanding that these illustrations are examples and are not limited to any particular embodiment described herein, and that the illustrated concepts are generally applicable to deep neural networks and machine learning techniques.

[0322] The exemplary neural network described above can be used to perform deep learning. Deep learning is machine learning using deep neural networks. In contrast to shallow neural networks that contain only a single hidden layer, deep neural networks used in deep learning are artificial neural networks with multiple hidden layers. Deeper neural networks are usually more computationally intensive to train. However, the additional hidden layers of the network allow for multiple steps of pattern recognition, which results in reduced output errors compared to shallow machine learning techniques.

[0323] A deep neural network used in deep learning typically includes a front-end network for performing feature recognition coupled to a back-end network representing a mathematical model that can perform an action (e.g., object classification, speech recognition, etc.) based on the feature representations provided to the model. Deep learning allows machine learning to be performed without requiring hand-crafted feature engineering to be performed for the model. Instead, deep neural networks can learn features based on statistical structures or correlations in the input data. The learned features can be provided to a mathematical model that can map detected features to an output. The mathematical model used by the network is typically dedicated to the particular task to be performed, and different models are used to perform different tasks.

[0324] Once a neural network is constructed, a learning model can be applied to the network to train it to perform a particular task. The learning model describes how to adjust the weights in the model to reduce the network's output error. Backpropagation of errors is a common method used to train neural networks. An input vector is presented to the network for processing. The output of the network is compared to the desired output using a loss function, and an error value is calculated for each of the neurons in the output layer. The error values ​​are then backpropagated until each neuron has an associated error value that roughly represents its contribution to the original output. The network can then learn from these errors using algorithms such as a stochastic gradient descent algorithm to update the neural network weights.

[0325] 32-33 show an exemplary convolutional neural network. FIG. 32 shows various layers in a CNN. As shown in FIG. 32, an exemplary CNN used to model image processing can receive an input 3202 describing the red, green, and blue (RGB) components of an input image. The input 3202 can be processed by multiple convolutional layers (e.g., convolutional layer 3204, convolutional layer 3206). The output from the multiple convolutional layers can optionally be processed by a set of fully connected layers 3208. Neurons in a fully connected layer have full connections to all activations in the previous layer, as described above for feedforward networks. The output from the fully connected layer 3208 can be used to generate an output result from the network. The activations in the fully connected layer 3208 can be calculated using matrix multiplication instead of convolutions. Not all CNN implementations utilize fully connected layers. For example, in some implementations, the convolutional layer 3206 can generate the output of the CNN.

[0326] Convolutional layers are loosely connected. This differs from traditional neural network configurations found in the fully connected layer 3208. Traditional neural network layers are fully connected, so that every output unit interacts with every input unit. However, as shown, convolutional layers are loosely connected because the output of the convolution of the field is the input to the nodes of the subsequent layer (instead of the respective state values ​​of each of the nodes in the field). The kernels associated with the convolutional layers perform the convolution operation, and the output is sent to the next layer. The dimensionality reduction performed in the convolutional layers is one aspect that allows CNNs to scale to process large images.

[0327] FIG. 33 shows exemplary computational steps in a convolutional layer of a CNN. The input to the convolutional layer 3312 of the CNN can be processed in three stages in the convolutional layer 3314. The three stages can include a convolution stage 3316, a detection stage 3318, and a pooling stage 3320. The convolutional layer 3314 can then output data to a successive convolutional layer. The final convolutional layer of the network generates output feature map data or provides input to a fully connected layer to generate classification values, for example, for input to the CNN.

[0328] In the convolution stage 3316, multiple convolutions run in parallel to generate a set of linear activations. The convolution stage 3316 may include an affine transformation, which is any transformation that can be specified as a linear transformation and a translation. Affine transformations include rotation, translation, scaling, and combinations of these transformations. The convolution stage calculates the output of a function (e.g., a neuron) that is connected to a particular region in the input, which may be determined as a local region associated with the neuron. The neuron calculates a dot product between the neuron's weight and the region in the local input to which the neuron is connected. The output from the convolution stage 3316 defines a set of linear activations that are processed by successive stages of the convolution layer 3314.

[0329] The linear activations can be processed by a detection stage 3318. In the detection stage 3318, each linear activation is processed by a nonlinear activation function. The nonlinear activation function increases the nonlinear characteristics of the entire network without affecting the receptive fields of the convolutional layers. Several types of nonlinear activation functions may be used. One particular type is the rectified linear unit (ReLU), which uses an activation function defined as f(x)=max(0,x). As a result, the activations are thresholded to 0.

[0330] The pooling stage 3320 uses a pooling function that replaces the output of the convolutional layer 3306 with the summary statistics of nearby outputs. The pooling function can be used to introduce translation invariance into the neural network, so that small translations to the input do not change the pooled output. Invariance to local translations can be useful in scenarios where the presence of a feature in the input data is more important than the exact location of the feature. Various types of pooling functions can be used during the pooling stage 3320, including max pooling, average pooling, and L2 norm pooling. Furthermore, some CNN implementations do not include a pooling stage. Instead, such implementations are an alternative additional convolution stage with an increased stride compared to the previous convolutional layer.

[0331] The output from the convolutional layer 3314 may then be processed by the next layer 3322, which may be an additional convolutional layer or one of the fully connected layers 3208. For example, the first convolutional layer 3314 in Figure 33 may output to a second convolutional layer 3322, which may output to the first of the fully connected layers 3208.

[0332] FIG. 34 illustrates an exemplary recurrent neural network 3400. In a recurrent neural network (RNN), the previous state of the network influences the output of the current state of the network. RNNs can be constructed in a variety of ways using a variety of functions. The use of RNNs typically uses mathematical models in a recursive manner to predict the future based on previous input sequences. For example, RNNs may be used to perform statistical language modeling to predict words that will appear given previous word sequences. The illustrated RNN 3400 can be described as having an input layer 3402 that receives input vectors, a hidden layer 404 that implements a recursive equation, a feedback mechanism 3405 that allows for "memory" of previous states, and an output layer 3406 that outputs the results. The RNN 3400 operates on a time-step basis. The state of the RNN at a given time step is influenced based on the previous time step via the feedback mechanism 3405. For a given time step, the state of the hidden layer 3404 is determined by the previous state and the input at the current time step. An initial input (x1) at a first time step may be processed by the hidden layer 3404. A second input (x2) may be processed by the hidden layer 3404 using state information determined during processing of the initial input (x1). A given state may be calculated as s_t=f(Ux_t+Ws_(t-1)), where U and W are parameter matrices. The function f is typically nonlinear and may be a hyperbolic tangent function (Tanh) or a rectifier function f(x)=max(0,x). However, the particular mathematical function used in the hidden layer 3404 may vary depending on the particular implementation details of the RNN 3400.

[0333] In addition to the basic CNN and RNN networks described, variations on these networks may be possible. One exemplary RNN variation is the long short term memory (LSTM) RNN. LSTM RNNs can learn long-term dependencies that may be necessary to process longer language sequences. A variation on CNN is the convolutional deep belief network, which has a similar structure to CNNs and is trained in a similar manner to deep belief networks. Deep Belief Networks (DBNs) are generative neural networks that consist of multiple layers of random (random) variables. DBNs can be trained layer-by-layer using greedy unsupervised learning. The learned weights of the DBN can then be used to provide a pre-trained neural network by determining an optimal initial set of weights for the neural network.

[0334] FIG. 35 illustrates the training and deployment of deep neural networks. Once a network is constructed for a given task, the neural network is trained using a training dataset 3502. Various training frameworks 3504 have been developed to allow hardware acceleration of the training process. For example, the machine learning frameworks described above may be configured as training frameworks. The training framework 3504 may connect to an untrained neural network 3506 and train the untrained neural network using the parallel processing resources described herein to generate a trained neural network 3508.

[0335] To start the training process, initial weights may be selected randomly or by pre-training with a deep Belief network. Training cycles are then performed in a supervised or unsupervised manner.

[0336] Supervised learning is a learning method where training is performed as an interventional action, for example when a training data set 3502 includes inputs paired with desired outputs for the inputs, or where the training data set has known outputs and the output of the neural network is manually evaluated. The network processes the inputs and compares the resulting output against an expected or desired set of outputs. Errors are then back-propagated through the system. The training framework 3504 can be adjusted to adjust the weights that control the untrained neural network 3506. The training framework 3504 can provide tools to monitor how well the untrained neural network 3506 is converging towards a model suitable for generating the correct answer based on known input data. The training process occurs iteratively as the network weights are adjusted to refine the output generated by the neural network. The training process can continue until the neural network reaches a desired statistical accuracy associated with the trained network 3508. The trained neural network 3508 can then be deployed to perform any number of machine learning operations.

[0337] Unsupervised learning is a learning method in which a network attempts to train itself with unlabeled data. Thus, in unsupervised learning, the training dataset 3502 includes input data without any associated output data. The untrained neural network 3506 can learn groupings among the unlabeled inputs and determine how individual inputs relate to the entire dataset. Unsupervised training can be used to generate self-organizing maps, a type of trained neural network 3507 that can perform operations useful for reducing the dimensionality of data. Unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the input dataset that deviate from normal patterns of data.

[0338] Variations on supervised and unsupervised training may also be used. Semi-supervised learning is a technique in which the training dataset 3502 contains a mixture of labeled and unlabeled data of the same variance. Incremental learning is a variation of supervised learning in which input data is successively used to further train the model. Incremental learning allows the trained neural network 3508 to adapt to new datasets without forgetting the knowledge injected into the network during initial training.

[0339] The training process, especially for deep neural networks, whether supervised or unsupervised, can be very computationally intensive for a single computing node. Instead of using a single computing node, a distributed network of computing nodes can be used to accelerate the training process.

[0340] 36A is a block diagram illustrating distributed learning. Distributed learning is a training model that uses multiple distributed computing nodes, such as those described above, to perform supervised or unsupervised training of a neural network. The distributed computing nodes may each include one or more host processors and one or more general-purpose processing nodes, such as highly parallel general-purpose graphics processing units. As shown, distributed learning can be performed with model parallelism 3602, data parallelism 3604, or a combination of model and data parallelism.

[0341] In model parallelism 3602, different computational nodes in a distributed system can perform training computations for different parts of a single network. For example, each layer of a neural network can be trained by a different processing node of the distributed system. Benefits of model parallelism include the ability to scale, especially for large models. Splitting up the computations associated with different layers of a neural network enables the training of very large neural networks where the weights of all layers do not fit into the memory of a single computational node. In some examples, model parallelism is particularly useful in performing unsupervised training of large neural networks.

[0342] In data parallelism 3604, different nodes of the distributed network have a complete instance of the model, with each node receiving a different portion of the data. The results from the different nodes are then combined. Different approaches to data parallelism are possible, but all data parallel training approaches require techniques to combine the results and synchronize the model parameters between each node. Exemplary approaches to combining data include parameter averaging and data parallelism based updates. Parameter averaging trains each node on a subset of the training dataset and sets the global parameters (e.g., weights, biases) to the average of the parameters from each node. Parameter averaging uses a central parameter server that maintains the parameter data. Data parallelism based updates are similar to parameter averaging, except that instead of forwarding parameters from the nodes to the parameter server, updates to the model are forwarded. Additionally, data parallelism based updates can be performed in a decentralized manner, with updates compressed and forwarded between nodes.

[0343] The combined model and data parallelism 3606 can be implemented, for example, in a distributed system where each compute node contains multiple CPUs. Each node can have a complete instance of the model where individual GPUs in each node are used to train different parts of the model.

[0344] Distributed training has increased overhead compared to training on a single machine, however, the parallel processors and GPGPUs described herein can each implement various techniques to reduce the overhead of distributed training, including techniques to enable high-bandwidth inter-GPU data transfers and accelerated remote data synchronization. <Example machine learning application>

[0345] Machine learning can be applied to solve a variety of technical problems, including, but not limited to, computer vision, autonomous driving and navigation, speech recognition, and language processing. Computer vision has traditionally been one of the most active research areas for machine learning applications. Applications of computer vision range widely from replicating human visual capabilities, such as face recognition, to creating new categories of visual capabilities. For example, computer vision applications can be configured to recognize sound waves from vibrations that occur within an object seen in a video. Parallel processor-accelerated machine learning allows computer vision applications to be trained with significantly larger training datasets than was previously feasible, allowing estimation systems to be deployed using low-power parallel processors.

[0346] Parallel processor accelerated machine learning has applications in autonomous driving including lane and road sign recognition, obstacle avoidance, navigation, and cruise control. Accelerated machine learning techniques can be used to train driving models based on data sets that define appropriate responses to specific training inputs. The parallel processors described herein can enable fast training of increasingly complex neural networks used for autonomous driving solutions, and enable the deployment of low-power estimation processors in mobile platforms suitable for integration into autonomous vehicles.

[0347] Parallel processor accelerated deep neural networks have enabled a machine learning approach to automatic speech recognition (ASR). ASR involves the generation of a function that computes the most likely language sequence given an input acoustic sequence. Accelerated machine learning using deep neural networks has enabled the replacement of the hidden Markov model (HMM) and Gaussian mixture model (GMM) previously used for ASR.

[0348] Parallel processor-accelerated machine learning can also be used to accelerate natural language processing. Automated learning procedures utilize statistical inference algorithms to generate models that are robust to erroneous or unfamiliar input. Exemplary natural language processor applications include automatic machine translation between human languages.

[0349] Parallel processing platforms used for machine learning are divided into training platforms and deployment platforms. Training platforms are typically highly parallelized and include optimizations to accelerate multi-GPU single-node training and multi-node multi-GPU training. Exemplary parallel processors suitable for training include the highly parallel general-purpose graphic processing units and / or multi-GPU computing systems described herein. In contrast, deployed machine learning platforms typically include low-power parallel processors suitable for use in products such as cameras, autonomous robots, and autonomous vehicles.

[0350] FIG. 36B illustrates an exemplary estimation system-on-chip (SOC) 3100 suitable for performing estimation using a trained model. The SOC 3100 can integrate processing components including a media processor 3602, a vision processor 3604, a GPGPU 3106, and a multi-core processor 3608. The SOC 3100 can further include an on-chip memory 3605 that enables a shared on-chip data pool accessible by each of the processing components. The processing components can be optimized for low-power operation to be deployed in a variety of machine learning platforms, including autonomous vehicles and autonomous robots. For example, an implementation of the SOC 3100 can be used as part of a master control system for an autonomous vehicle. When the SOC 3100 is configured for use in an autonomous vehicle, the SOC is designed and configured to comply with the relevant functional safety standards of the jurisdiction of deployment.

[0351] In operation, the media processor 3602 and the vision processor 3604 can work together to accelerate computer vision operations. The media processor 3602 can enable low latency decoding of multiple high resolution (e.g., 4K, 8K) video streams. The decoded video streams can be written to a buffer in the on-chip memory 3605. The vision processor 3604 then parses the decoded video and performs pre-processing operations on frames of the decoded video in preparation for processing the frames using a trained image recognition model. For example, the vision processor 3604 can accelerate the convolution operations of a CNN used to perform image recognition on high resolution video data. Meanwhile, the back-end model computations are performed by the GPGPU 3106.

[0352] The multicore processor 3608 may include control logic to assist in sequencing and synchronization of data transfer and shared memory operations performed by the media processor 3602 and the vision processor 3604. The multicore processor 3608 may also function as an application processor to execute software applications that can utilize the estimated computational power of the GPGPU 3106. For example, at least a portion of the navigation and navigation logic may be implemented in software that executes on the multicore processor 3608. Such software may issue computational workloads directly to the GPGPU 3106. Alternatively, computational workloads may be issued to the multicore processor 3608, which may offload at least a portion of these operations to the GPGPU 3106.

[0353] The GPGPU3106 may include a computation cluster such as the computation clusters DPLAB06A-DPLAB06H in a low-power configuration within the highly parallel general-purpose graphic processing unit DPLAB00. The computation clusters within the GPGPU3106 may support instructions specifically optimized for performing inference calculations on trained neural networks. For example, the GPGPU3106 may support instructions for performing low-precision calculations such as 8-bit and 4-bit integer vector operations. <Ray tracing architecture>

[0354] In one implementation, the graphics processor includes circuitry and / or program code for performing real-time ray tracing. In some embodiments, a dedicated set of ray tracing cores is included in the graphics processor to perform various ray tracing operations described herein, including ray traverse / ray intersection operations. In addition to the ray tracing cores, one embodiment includes multiple sets of graphics processing cores for performing programmable shading operations, and multiple sets of tensor cores for performing matrix operations on tensor data.

[0355] 37 shows an example portion of one such graphics processing unit (GPU) 3705 including dedicated sets of graphics processing resources organized into multi-core groups 3700A-N. Details of only a single multi-core group 3700A are provided, it being understood that the other multi-core groups 3700B-N may be equipped with the same or similar sets of graphics processing resources.

[0356] As shown, multi-core group 3700A may include a set of graphics cores 3730, a set of tensor cores 3740, and a set of ray tracing cores 3750. A scheduler / dispatcher 3710 schedules and dispatches graphics threads for execution on the various cores 3730, 3740, 3750. A set of register files 3720 stores operand values ​​used by the cores 3730, 3740, 3750 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0357] One or more associated level 1 (L1) caches and texture units 3760 store graphics data locally within each multicore group 3700A, such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. A level 2 (L2) cache 3780, shared by all or a subset of the multicore groups 3700A-N, stores graphics data and / or instructions for multiple simultaneous graphics threads. As shown, the L2 cache 3780 may be shared across multiple multicore groups 3700A-N. One or more memory controllers 3770 couple the GPU 3705 to memory 3798, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0358] Input / output (I / O) circuitry 3795 couples GPU 3705 to one or more I / O devices 3790, such as a digital signal processor (DSP), a network controller, or a user input device. On-chip interconnects may be used to couple I / O devices 3790 to GPU 3705 and memory 3798. One or more I / O memory management units (IOMMUs) 3770 of I / O circuitry 3795 directly couple I / O devices 3790 to system memory 3798. In one embodiment, IOMMU 3770 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 3798. In this embodiment, I / O devices 3790, CPU 3799, and GPU 3705 may share the same virtual address space.

[0359] In one implementation, the IOMMU 3770 supports virtualization. In this case, the IOMMU 3770 may manage a first set of page tables that map guest / graphics virtual addresses to guest / graphics physical addresses, and a second set of page tables that map guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 3798). The base addresses of each of the first and second page table sets may be stored in control registers and swapped out on a context switch (e.g., so that a new context is provided access to the associated page table set). Although not shown in FIG. 37, each of the cores 3730, 3740, 3750 and / or multicore groups 3700A-N may include a translation lookaside buffer (TLB) that caches guest virtual translations to guest physical translations, guest physical translations to host physical translations, and guest virtual translations to host physical translations.

[0360] In one embodiment, the CPU 3799, GPU 3705, and I / O devices 3790 are integrated into a single semiconductor chip and / or chip package. The illustrated memory 3798 may be integrated into the same chip or may be coupled to the memory controller 3770 via an off-chip interface. In one implementation, the memory 3798 includes GDDR6 memory that shares the same virtual address space as other physical system level memory, although the underlying principles of the invention are not limited to this particular implementation.

[0361] In one embodiment, tensor cores 3740 include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and estimation. Tensor cores 3740 may perform matrix processing using a variety of operand precisions, including single precision floating point (e.g., 32 bits), half precision floating point (e.g., 16 bits), integer word (16 bits), byte (8 bits), and half byte (4 bits). In one embodiment, the neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to compose a high-quality final image.

[0362] In a deep learning implementation, parallel matrix multiplication operations may be scheduled for execution on the tensor cores 3740. Training neural networks, in particular, requires a significant number of matrix dot product operations. To process the inner product formulation of an N×N×N matrix multiplication, the tensor cores 3740 may include at least N dot product processing elements. Before starting the matrix multiplication, an entire matrix is ​​loaded into a tile register, and at least one column of a second matrix is ​​loaded in each of the N cycles. In each cycle, there are N dot products to be processed.

[0363] Matrix elements may be stored with different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8), and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for tensor cores 3740 to ensure that the most efficient precision is used for different workloads (e.g., estimated workloads that can tolerate quantization to bytes and half-bytes).

[0364] In one embodiment, the ray tracing core 3750 accelerates ray tracing operations for both real-time and non-real-time ray tracing implementations. In particular, the ray tracing core 3750 includes ray traverse / intersection circuitry to perform ray traversal using a bounding volume hierarchy (BVH) and identify intersections between rays and primitives confined within the BVH volume. The ray tracing core 3750 may also include circuitry to perform depth testing and culling (e.g., using a Z-buffer or similar construct). In one embodiment, the ray tracing core 3750 performs the traverse and intersection operations in conjunction with image denoising techniques described herein, which may be performed at least in part on the tensor core 3740. For example, in one embodiment, the tensor core 3740 implements a deep learning neural network to perform denoising of frames generated by the ray tracing core 3750. However, the CPU 3799, graphics core 3730, and / or ray tracing core 3750 may implement all or part of the denoising and / or deep learning algorithms.

[0365] Additionally, as discussed above, a distributed approach to denoising may be utilized, where the GPU 3705 is in a computing device that is coupled to other computing devices via a network or high speed interconnect. In this embodiment, the interconnected computing devices share neural network learning / training data to improve the speed at which the entire system learns to perform denoising for different types of image frames and / or different graphics applications.

[0366] In one embodiment, the ray tracing core 3750 handles all BVH traversals and ray primitive intersections to prevent the graphics core 3730 from being overloaded with thousands of instructions per ray. In one embodiment, each ray tracing core 3750 includes a first set of dedicated circuitry to perform bounding box tests (e.g., for traverse operations) and a second set of dedicated circuitry to perform ray triangle intersection tests (e.g., intersecting traversed rays). Thus, in one embodiment, the multi-core group 3700A can simply issue ray probes, and the ray tracing core 3750 independently performs ray traversals and intersections and returns hit data (e.g., hit, no hit, multiple hits, etc.) to the thread context. The other cores 3730, 3740 are freed to perform other graphics or computational work while the ray tracing core 3750 performs the traverse and intersection operations.

[0367] In one embodiment, each ray tracing core 3750 includes a traverse unit for performing BVH test operations and an intersection unit for performing ray primitive intersection tests. The intersection unit generates and provides a "hit", "no hit", or "multiple hits" response to the appropriate thread. During traverse and intersection operations, the execution resources of other cores (e.g., graphics core 3730 and tensor core 3740) are freed to perform other forms of graphics work.

[0368] In one particular embodiment, described below, a hybrid rasterization / ray tracing approach is used, with work distributed between the graphics core 3730 and the ray tracing core 3750.

[0369] In one embodiment, the ray tracing core 3150 (and / or other cores 3730, 3740) includes hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR), which includes a DispatchRays command and ray generation, nearest hit, any hit, and miss shaders, allowing for the assignment of a unique set of shaders and textures per object. Another ray tracing platform that may be supported by the ray tracing core 3750, graphics core 3730, and tensor core 3740 is Vulkan 1.1.85. However, it is noted that the underlying principles of the present invention are not limited to any particular ray tracing ISA.

[0370] In general, the various cores 3750, 3740, 3730 may support a ray tracing instruction set that includes instructions / functions for ray generation, nearest hit, any hit, ray primitive intersection, per-primitive and substructure bounding box construction, miss, visit, and exception. More specifically, one embodiment includes ray tracing instructions to perform the following functions:

[0371] Ray Generation: Ray generation instructions may be executed per pixel, sample, or other user-defined work allocation.

[0372] Closest Hit: The Closest Hit instruction may be executed to locate the closest intersection point of a ray with a primitive in a scene.

[0373] Any Hit: The Any Hit command identifies multiple intersections between a ray and primitives in the scene, and potentially identifies a new nearest intersection point.

[0374] Intersection: The intersection command performs a ray-primitive intersection test and outputs the result.

[0375] Per-primitive Bounding box Construction: This instruction constructs a bounding box around a given primitive or group of primitives (e.g., when building a new BVH or other acceleration data structure).

[0376] Miss: Indicates that the ray misses all geometry in the scene or a particular area of ​​the scene.

[0377] Visit: Indicates the child volume that the ray will traverse.

[0378] Exceptions: Includes various kinds of exception handling (eg, invoked for various error conditions). <Hierarchical beam tracing>

[0379] Bounding volume hierarchies are commonly used to improve the efficiency with which operations are performed on graphic primitives and other graphic objects. A BVH is a hierarchical tree structure built on a set of geometric objects. At the top of the tree is a root node that contains all of the geometric objects in a given scene. Individual geometric objects are enveloped in bounding volumes that form the leaf nodes of the tree. These nodes are then grouped into smaller sets and contained within larger bounding volumes. These in turn are recursively grouped and contained within other larger bounding volumes, ultimately resulting in a tree structure with a single bounding volume represented by the root node at the top of the tree. Bounding volume hierarchies are used to efficiently support various operations on geometric objects, such as collision detection, primitive culling, and ray traverse / intersection operations used in ray tracing.

[0380] In a ray tracing architecture, rays are traversed through the BVH to determine ray primitive intersections. For example, if a ray does not pass through the root node of the BVH, the ray does not intersect any of the primitives contained by the BVH, and no further processing is required for the ray with respect to this set of primitives. If a ray passes through the first child node of a BVH but not through the second child node, the ray does not need to be tested against any primitives contained by the second child node. In this way, the BVH provides an efficient mechanism for testing for ray primitive intersections.

[0381] In one embodiment of the present invention, a group of consecutive rays is called a "beam" and is tested against the BVH rather than individual rays. Figure 38 shows an exemplary beam 3801 outlined by different rays. Any rays that intersect a patch 3800 defined by four rays are considered to be in the same beam. Although the beam 3801 in Figure 38 is defined by a rectangular configuration of rays, the beam may be defined in a variety of other ways (e.g., circular, elliptical, etc.) while still adhering to the basic principles of the present invention.

[0382] FIG. 39 illustrates an exemplary embodiment in which the ray tracing engine 3910 of the GPU 3920 implements the beam tracing techniques described herein. In particular, the ray generation circuitry 3904 generates a number of rays on which traversal and intersection operations are to be performed. However, rather than performing the traversal and intersection operations on individual rays, the illustrated embodiment performs the traversal and intersection using a hierarchy of beams 3907 generated by the beam hierarchy construction circuitry 3905. In one embodiment, the beam hierarchy is similar to a bounding volume hierarchy (BVH). For example, FIG. 40 provides an example of a first order beam 4000 that may be subdivided into a number of different components. In particular, the first order beam 4000 may be divided into four quadrants 4001-4004. Each quadrant may itself be divided into sub-quadrants, such as sub-quadrants A-D within quadrant 4004. The first order beam may be subdivided in a variety of ways. For example, in one embodiment, the primary beam may be divided into halves (rather than quarters), each half may be divided into halves, etc. Regardless of how the subdivision is done, in one embodiment, a hierarchical structure is created in a manner similar to a BVH, e.g., with a root node representing the primary beam 4000, first level child nodes each represented by a quadrant 4001-4004, second level child nodes for each sub-quadrant A-D, etc.

[0383] In one embodiment, once the beam hierarchy 3907 is constructed, the traverse / intersection circuit 3906 performs traverse / intersection operations using the beam hierarchy 3907 and the BVH 3908. In particular, the beam may be tested against the BVH and portions of the beam that do not intersect any portion of the BVH may be culled. Using the data shown in Figure 40, for example, if the sub-beams associated with sub-regions 4002 and 4003 do not intersect the BVH or a particular branch of the BVH, they may be culled with respect to the BVH or branch. The remaining portions 4001, 4004 may be tested against the BVH by performing a depth-first search, or other search algorithm.

[0384] A method according to one embodiment of the present invention is illustrated in Figure 41. The method may be implemented within the context of the graphics processing architectures mentioned above, but is not limited to any particular architecture.

[0385] At 4100, a primary beam is constructed that includes multiple rays. At 4101, the beam is subdivided and a hierarchy data structure is generated to generate a beam hierarchy. In one embodiment, operations 4100-4101 are performed as a single, integrated operation to construct a beam hierarchy from multiple rays. At 4102, the beam hierarchy is used with the BVH to cull rays (from the beam hierarchy) and / or nodes / primitives from the BVH. At 4103, ray-primitive intersections are determined for the remaining rays and primitives. <Lossiness and Lossless Packet Compression in Distributed Ray Tracing Systems>

[0386] In one embodiment, ray tracing operations are distributed across multiple computational nodes that are coupled together via a network. Figure 42, for example, illustrates a ray tracing cluster 4200 that includes multiple ray tracing nodes 4210-4213 that perform ray tracing operations in parallel and possibly combine the results at one of the nodes. In the illustrated architecture, the ray tracing nodes 4210-4213 are communicatively coupled to a client-side ray tracing application 4230 via a gateway.

[0387] One of the difficulties with a distributed architecture is that large amounts of packet data must be transmitted between each of the ray tracing nodes 4210-4213. In one embodiment, both lossless and lossy compression techniques are used to reduce the data transmitted between the ray tracing nodes 4210-4213.

[0388] To implement lossless compression, rather than sending packets filled with the results of a particular type of operation, data or commands are sent that allow the receiving node to reconstruct the results. For example, stochastically sampled area illumination and ambient occlusion (AO) operations do not necessarily require direction. As a result, in one embodiment, the sending node simply sends a random seed that is used by the receiving node to perform random sampling. For example, if a scene is distributed across nodes 4210-4212, to sample light 1 at points p1-p3, only the light ID and origin need to be sent to nodes 4210-4212. Each of the nodes may then stochastically sample the light independently. In one embodiment, the random seed is generated by the receiving node. Similarly, ambient occlusion (AO) and soft shadow sampling can be calculated at nodes 4210-4212 for primary ray hit points without waiting for the original point for successive frames. Additionally, if a set of rays is known to go to the same point light source, a command identifying the light source may be sent to the receiving node, which applies it to the set of rays. As another example, if there are N ambient occlusions that have been sent a single point, a command may be sent to generate N samples from this point.

[0389] Various additional techniques may be applied for lossy compression. For example, in one embodiment, a quantization factor may be utilized to quantize all coordinate values ​​associated with BVH, primitives, and rays. Additionally, 32-bit floating point values ​​used for data such as BVH nodes and primitives may be converted to 8-bit integer values. In one particular implementation, bundles of ray packets are stored with full precision, but individual ray points P1-P3 are transmitted as indexed offsets into the bundle. Similarly, multiple local coordinate systems may be generated that use 8-bit integer values ​​as local coordinates. The location of the origin of each of these local coordinate systems may be encoded using full precision (e.g., 32-bit floating point) values, effectively connecting the global and local coordinate systems.

[0390] Below is an example of lossless compression used in one embodiment of the present invention: An example of a ray data format used within a ray tracing program is as follows:

number

[0391] Instead of sending the raw data for each and every generated node, this data can be compressed by grouping values ​​and, where possible, generating implicit rays with appropriate metadata.

[0392] <Bundling and grouping of ray data>

number

[0393] All ray data is packetized, except that only a single origin is stored across all rays. RayPacket.flags is set to RAYPACKET_COMMON_ORIGIN. When a ray packet is received and depacketized, the origin is filled from the single origin value. <The origin is shared only among some rays>

[0394] All ray data is packetized, except for rays that share an origin. For each group of unique shared origins, an operator is packed that identifies the operation (shared origin), stores the origin, and masks which rays share information. Such operations can be done on any value that is shared between nodes, such as material IDs, primitive IDs, origins, directions, normals, etc.

number

[0395] Often, ray data can be derived at the receiving end with minimal meta-information used to generate the ray data. A very common example is generating multiple secondary rays to probabilistically sample an area. Instead of the sender generating a secondary ray, sending it, and the receiver acting on it, the sender can send a command that a ray needs to be generated with any dependent information, and the ray is generated at the receiving end. If a ray needs to be generated initially by the sender to determine which receiver to send the ray to, the ray can be generated and a random seed can be sent to regenerate the exact same ray.

[0396] For example, to sample a hit point with 64 shadow rays sampling an area light source, all 64 rays intersect the area from the same calculation N4. A RayPacket with a common origin and normal is generated. More data can be sent if we want the receiver to shade the resulting pixel contribution. However, in this example, we assume we only want to return whether the ray hits another node data. A RayOperation assigns the lightID values ​​and random seed to be generated and sampled for the generate shadow ray operation. When N4 receives the ray packet, it generates fully filled ray data for all rays by filling them with the shared origin data and setting the direction based on the lightID probabilistically sampled by the random seed, generating the same rays as the original sender generated. When the results are returned, only the binary results of all rays need to be returned, which can be handled by a mask on the rays.

[0397] Sending the original 64 rays in this example would use 104 bytes x 64 rays = 6656 bytes. If the return rays were sent in their raw form, this would double again to 13312 bytes. Using lossless compression to send only the ray generation operations with the common ray origin, normal, and seed and ID, with 8 bytes for the intersection mask, only 29 bytes are sent. This results in a compression ratio of approximately 360:1 for the data that needs to be sent over the network. This does not include the overhead for processing the message itself, which may need to be identified in some way but is left to the implementation. Other operations may be performed to recalculate the ray origin and direction from the pixel ID (pixelD) of the primary ray, to recalculate the pixel ID based on the range in the ray packet, and for many other possible implementations of value recalculation. Similar operations can be used for any single or group of rays sent, including shadows, reflections, refractions, ambient occlusion, intersections, volume intersections, shading, bouncing reflections in the path to be traced, etc.

[0398] FIG. 43 shows additional details of two ray tracing nodes 4310-4311 that perform compression and decompression of ray tracing packets. In particular, in one embodiment, when the first ray tracing engine 4330 is ready to send data to the second ray tracing engine 4331, the ray compression circuit 4320 performs lossy and / or lossless compression of the ray tracing data as described herein (e.g., converting 32-bit values ​​to 8-bit values, replacing raw data with instructions to reconstruct the data, etc.). The compressed ray packet 4301 is transmitted from the network interface 4325 over a local network (e.g., a 10 Gb / s, 100 Gb / s Ethernet network) to the network interface 4326. The ray decompression circuit then decompresses the ray packet when appropriate. For example, the ray decompression circuit may execute commands to reconstruct the ray tracing data (e.g., using a random seed to perform random sampling for lighting operations). The ray tracing engine 4331 then performs ray tracing operations using the received data.

[0399] In the reverse direction, the ray compression circuitry 4341 compresses the ray data, the network interface 4326 transmits the compressed ray data over the network (e.g., using techniques described herein), the ray decompression circuitry 4340 decompresses the ray data if necessary, and the ray tracing engine 4330 uses the data in its ray tracing operations. Although shown as separate units in Figure 43, the ray decompression circuits 4340-4341 may be integrated within the ray tracing engines 4330-4331, respectively. For example, to the extent the compressed ray data includes commands for reconstructing the ray data, these commands may be executed by the respective ray tracing engines 4330-4331.

[0400] 44, the beam compression circuit 3720 may include a lossy compression circuit 4401 that performs the lossy compression techniques described herein (e.g., converting 32-bit floating point coordinates to 8-bit integer coordinates), and a lossless compression circuit 4403 that performs the lossless compression techniques (e.g., sending commands and data to enable the beam decompression circuit 3721 to reconstruct the data). The beam decompression circuit 3721 includes a lossy decompression circuit 4402, and a lossless decompression circuit 4404 that performs lossless decompression.

[0401] A method according to one embodiment is illustrated in Figure 45. The method may be implemented on any ray tracing architecture described herein, but is not limited to any particular architecture.

[0402] At 4500, ray data is received from a first ray tracing node to be transmitted to a second ray tracing node. At 4501, a lossy compression circuit performs lossy compression at the first ray tracing node, and at 4502, a lossless compression circuit performs lossless compression at the second ray tracing node. At 4503, the compressed ray tracing data is transmitted to the second ray tracing node. At 4504, a lossy / lossless decompression circuit performs lossy / lossless decompression of the ray tracing data. At 4505, the second ray tracing node performs a ray tracing operation using the decompressed data. <Graphics processor with hardware accelerated hybrid ray tracing>

[0403] One embodiment of the present invention includes a hybrid rendering pipeline that performs rasterization on the graphics core 3730 and ray tracing operations on the ray tracing core 3750, the graphics core 3730, and / or the CPU 3799 core. For example, rasterization and depth testing may be performed on the graphics core 3730 instead of the primary ray casting stage. The ray tracing core 3750 may then generate secondary rays for reflection, refraction, and shadows. Additionally, certain embodiments may select certain regions of a scene on which the ray tracing core 3750 performs ray tracing operations (e.g., based on material property thresholds such as high reflectivity levels), while other regions of the scene are rendered by rasterization on the graphics core 3730. In one embodiment, this hybrid implementation is used for real-time ray tracing applications where latency is a key issue.

[0404] One embodiment of the ray traversal architecture described below performs programmable shading and ray tracing control using existing SIMD (single instruction multiple data) and / or SIMT (single instruction multiple thread) graphics processors while accelerating critical functions such as BVH traversal and / or intersection using dedicated hardware. In this embodiment, non-coherent path SIMD occupational space is improved by regrouping shaders generated at specific points during traversal and before shading. This is achieved using dedicated hardware that dynamically sorts shaders on-chip. Iterations are managed by splitting functions into successive ones that are executed upon returning and regrouping the successive ones before executing the improved SIMD occupational space.

[0405] Programmable control of ray traversal / intersection is achieved by decomposing the traverse functionality into an inner traverse that can be implemented as fixed-function hardware, and an outer traverse that runs on the GPU processor, allowing programmable control through user-defined traverse shaders. The cost of transferring traverse context between hardware and software is reduced by traditionally truncating the inner traverse state during the transition between inner and outer traverses.

[0406] Programmable control of ray tracing can be expressed through different shader types, listed below in Table A. There are multiple shaders within each type. For example, each material can have a different hit shader. Table A [Table 1]

[0407] In one embodiment, recursive ray tracing is initiated by an API function that instructs the graphics processor to start an intersection circuit that can generate a set of primary shaders or ray-scene intersections of primary rays. This in turn generates other shaders, such as traverse, hit, or miss shaders. A shader that generates a child shader can receive return values ​​from the child shader. A callable shader is a generic function that can be generated directly by another shader and can also return values ​​to the calling shader.

[0408] Figure 46 illustrates one embodiment of a graphics processing architecture including shader execution circuitry 4600 and fixed function circuitry 4610. The general purpose execution hardware subsystem includes multiple SIMD (single instruction multiple data) and / or SIMT (single instructions multiple threads) cores / execution units (EUs) 4601 (i.e., each core may include multiple execution units), one or more samplers 4602, a level 1 (L1) cache 4603, or other forms of local memory. The fixed function hardware subsystem 4610 includes a message unit 4604, a scheduler 4607, a ray BVH traverse / intersection circuitry 4605, a sorting circuitry 4608, and a local L1 cache 4606.

[0409] In operation, the primary dispatcher 4609 dispatches a set of primary rays to the scheduler 4607, which schedules work to shaders executing on the SIMD / SIMT core / EU 4601. The SIMD core / EU 4601 may be the ray tracing core 3750 and / or the graphics core 3730 described above. The execution of the primary shaders generates additional work to be performed (e.g., to be performed by one or more child shaders and / or fixed function hardware). The message unit 4604 distributes the work generated by the SIMD core / EU 4601 to the scheduler 4607, which accesses the free stack pool as needed, the sorting circuit 4608, or the ray BVH intersection circuit 4605. If the additional work is sent to the scheduler 4607, it is scheduled for execution on the SIMD / SIMT core / EU 4601. Prior to scheduling, sorting circuitry 4608 may sort rays into groups or bins as described herein (e.g., grouping rays with similar characteristics). Ray BVH intersection circuitry 4605 performs intersection tests of rays with BVH volumes. For example, ray BVH intersection circuitry 4605 may compare ray coordinates with each level of the BVH to identify volumes intersected by the ray.

[0410] Shaders can be referenced using a shader record, a user-allocated structure that contains a pointer to an entry function, vendor-specific metadata, and global arguments to the shader executed by the SIMD core / EU4601. Each execution instance of a shader is associated with a call stack that may be used to store arguments passed between parent and child shaders. The call stack also stores a reference to a continuation function that is executed when the call returns.

[0411] Figure 47 shows an example set of allocated stacks 4701 including a primary shader stack, a hit shader stack, a traverse shader stack, a continuation function stack, and a ray BVH intersection stack (which may be implemented by fixed function hardware 4610, as described above). New shader invocations may implement new shaders from a free stack pool 4702. The call stacks may be cached in local L1 caches 4603, 4606 to reduce access latency.

[0412] In one embodiment, there are a finite number of call stacks, each with a fixed maximum size "Sstack" that is allocated in a contiguous region of memory. Therefore, the base address of the stack can be calculated directly from the stack index (SID): base address = SID * Sstack. In one embodiment, stack IDs are allocated and deallocated by the scheduler 4607 when scheduling work to a SIMD core / EU 4601.

[0413] In one embodiment, the primary dispatcher 4609 includes a graphics processor command processor that dispatches primary shaders in response to dispatch commands from the host (e.g., CPU). The shaders 4607 receive these dispatch requests and start the primary shaders on the SIMD processor threads if they can allocate a stack ID for each SIMD lane. The stack IDs are allocated from the free stack pool 4702, which is initialized at the beginning of the dispatch command.

[0414] An executing shader can spawn a child shader by sending a create message to message unit 4604. This command contains the stack ID associated with the shader and also contains pointers to the child shader records for each active SIMD lane. A parent shader can only issue this message once per active lane. In one embodiment, after sending the create message for all relevant lanes, the parent shader terminates.

[0415] Shaders executing on the SIMD core / EU 4601 can also generate fixed function tasks such as ray BVH intersection using generate messages with shader record pointers reserved for the fixed function hardware. As described above, the message unit 4604 sends generated ray BVH intersection work to the fixed function ray BVH intersection circuit 4005 and callable shaders directly to the sort circuit 4608. In one embodiment, the sort circuit groups shaders by shader record pointers to derive rSIMD batches with similar properties. Thus, stack IDs from different parent shaders can be grouped into the same batch by the sort circuit 4608. The sort circuit 4608 sends the grouped batches to the scheduler 4607, which accesses shader records from the graphics memory 2511 or the last level cache (LLC) 4620 and dispatches the shaders onto the processor threads.

[0416] In one embodiment, continuations are treated as callable shaders and may also be referenced through a shader record. When a child shader is created and returns a value to a parent shader, a pointer to the continuation shader record is pushed onto the call stack as shown in Figure 47. When the child shader returns, the continuation shader record is popped from the call stack 4701 and the continuation shader is created. The created continuation passes through the sort unit just like a callable shader and is launched onto a processor thread.

[0417] As shown in FIG. 48, one embodiment of the sorting circuit 4608 groups tasks generated by shader record pointers 4801A, 4801B, 4801n to generate SIMD batches for shading. The stack IDs or context IDs in the sorted batches may be grouped from different dispatches and different input SIMD lanes. In one embodiment, the grouping circuit 4810 performs the sorting using a content addressable memory (CAM) structure 4801 having multiple entries, each entry identified by a tag 4801. As mentioned above, in one embodiment, the tag 4801 is the corresponding shader record pointer 4801A, 4801B, 4801n. In one embodiment, the CAM structure 4801 stores a limited number of tags (e.g., 32, 64, 128, etc.) associated with incomplete SIMD batches, each of which corresponds to a shader record pointer.

[0418] For an incoming generate command, each SIMD lane has a corresponding stack ID (shown as one of 16 context IDs 0-15 in each CAM entry) and shader record pointer 4801A,B,...,n (which acts as a tag value). In one embodiment, grouping circuit 4810 compares each lane's shader record pointer to tags 4801 in CAM structure 4801 to find a matching batch. If a matching batch is found, the stack ID / context ID is added to the batch. Otherwise, a new entry with a new shader record pointer tag is created, possibly evicting an old entry with an incomplete batch.

[0419] An executing shader can deallocate its call stack when it becomes empty by sending a deallocate message to the message unit, which is relayed to the scheduler, which returns the stack ID / context ID of the active SIMD lane to the free pool.

[0420] One embodiment of the present invention implements a hybrid approach for ray traversal operations using a combination of fixed-function and software ray traversal. It therefore provides the flexibility of software traversal while maintaining the efficiency of fixed-function traversal. Figure 49 shows an acceleration structure that can be used for hybrid traversal. It is a two-level tree, with a single top-level BVH 4900 and several bottom-level BVHs 4901 and 4902. On the right side, graphical elements are shown to show the inner traversal path 4903, the outer traversal path 4904, the traversal nodes 4905, and the leaf nodes 4907 with custom primitives.

[0421] A leaf node 4906 with a triangle in the top level BVH 4900 can reference a triangle, intersection shader record, or traverse shader record for custom primitives. A leaf node 4906 with a triangle in the bottom level BVH 4901-4902 can only reference triangle and intersection shader records for custom primitives. The type of reference is encoded in the leaf node 4306. An internal traversal 4303 references a traversal within each BVH 490-4902. An internal traversal operation involves the calculation of ray BVH intersections, and a traversal across the BVH structures 4900-4902 is known as an external traversal. An internal traversal operation can be implemented efficiently in fixed function hardware, while an external traversal operation can be performed with acceptable performance by programmable shaders. Thus, one embodiment of the present invention performs internal traverse operations using fixed function circuitry 4610 and performs external traverse operations using shader execution circuitry 4600, which includes a SIMD / SIMT core / EU 4601 that executes programmable shaders.

[0422] Note that the SIMD / SIMT core / EU 4601 may be referred to herein, for simplicity, simply as the "core," "SIMD core," "EU," or "SIMD processor." Similarly, the ray traverse / intersection circuit 4605 may be referred to herein simply as the "traverse unit," "traverse / intersection unit," or "traverse / intersection circuit." Alternative terminology may be used, and the particular names used to designate the respective circuits / logic do not change the basic function that the circuits / logic perform as described herein.

[0423] Additionally, although shown as a single component in FIG. 46, the traverse / intersection unit 4605 may include a separate traverse unit and a separate intersection unit, each of which may be implemented in circuitry and / or logic as described herein.

[0424] In one embodiment, when a ray intersects a traverse node during an internal traversal, a traverse shader is generated. As shown in FIG. 48, the sorting circuit 4608 groups these shaders by shader record pointers 4801A,B,n to generate a SIMD batch. The SIMD batch is submitted by the shader 4607 to the graphics SIMD core / EU 4001 for SIMD execution. The traverse shader can be modified in several ways to enable a variety of applications. For example, the traverse shader may select a BVH at a coarse level of detail (LOD) or transform the ray to enable rigid body transformation. The traverse shader then generates an internal traversal for the selected BVH.

[0425] The internal traversal computes ray BVH intersections by traversing the BVH and computing ray boxes and ray triangle intersections. The internal traversal is generated in the same manner as a shader, by sending messages to the messaging circuit 4604 which relays corresponding generate messages to the ray BVH intersection circuit 4605 which computes the ray BVH intersections.

[0426] In one embodiment, the stack of the inner traversal is stored locally in the fixed function circuitry 4610 (e.g., in the L1 cache 4606). When the ray intersects with a leaf node corresponding to a traverse or intersection shader, the inner traversal is terminated and the inner stack is truncated. The truncated stack, together with the ray and a pointer to the BVH, is written to memory at the location specified by the calling shader, and then the corresponding traverse or intersection shader is generated. If the ray intersects with any triangle during the inner traversal, the corresponding hit information is provided to these shaders as input arguments, as shown in the code below. These generated shaders are grouped by the sorting circuitry 4608 to generate a SIMD batch for execution.

number

[0427] Truncating the internal traversal stack reduces the cost of splitting it into memory. One embodiment of the present invention uses the approach described in Restart Trail for Stackless BVH Traversal, High Performance Graphics (2010), pp. 107-111 to truncate the stack to a small number of entries at the top of the stack, a 42-bit restart trail, and a 6-bit depth value. The restart trail indicates the branches that have already been taken inside the BVH, and the depth value indicates the traversal depth corresponding to the last stack entry. This is enough information to resume the internal traversal at a later time.

[0428] The inner traversal is complete when the inner stack is empty and there are no BVH nodes to test, in which case an outer stack handler is created that pops the top of the outer stack and resumes the traversal if the outer stack is not empty.

[0429] In one embodiment, the outer traversal executes a main traversal state machine and is implemented in program code executed by the shader execution circuitry 4600. The outer traversal generates inner traversal queries under the following conditions: (1) when a new ray is generated by a hit shader or a primary shader, (2) when a traversal shader selects a BVH for traversal, and (3) when the outer stack handler resumes inner traversal of a BVH.

[0430] Figure 50 shows that before the internal traversal is generated, space is allocated in the call stack 5005 of the fixed function circuitry 4610 to store a truncated internal stack 5010. The call stack and offsets 5003-5004 to the top of the internal stack are maintained in a traverse state 5000, which is also stored in memory. The traverse state 5000 also contains hit information for rays in world closure 5001 and object space 5002, as well as the nearest intersecting primitive.

[0431] The traverse shaders, intersection shaders, and external stack handlers are all generated by the ray BVH intersection circuit 4605. The traverse shaders are allocated on the call stack 5005 before starting a new inner traversal of the second level BVH. The external stack handlers are the shaders responsible for updating the hit information and resuming any pending inner traversal tasks. The external stack handlers are also responsible for generating hit or miss shaders when the traversal is complete. A traversal is complete when there are no pending inner traverse queries to be generated. When the traversal is complete and no intersection was found, a hit shader is generated, otherwise a miss shader is generated.

[0432] Although the hybrid traversal scheme described above uses a two-level BVH hierarchy, embodiments of the invention described herein may use any number of BVH levels, with corresponding modifications to the outer traversal implementation.

[0433] Additionally, although the fixed function circuitry 4610 has been described in the above embodiments to perform ray BVH intersection, other system components may also be implemented in the fixed function circuitry. For example, the external stack handlers described above may be internal (user invisible) shaders that may potentially be implemented in the fixed function BVH traverse / intersection circuitry 4605. This implementation may be used to reduce the number of shader stages dispatched and round trips between the fixed function intersection hardware 4605 and the processor.

[0434] The embodiments of the invention described herein enable programmable shading and ray traversal control using user-defined functions that can be executed with great SIMD efficiency on existing and future GPU processors. Programmable control of the ray traversal enables several important features such as procedural instantiation, probabilistic level-of-detail selection, custom primitive intersections, and lazy BVH updates.

[0435] One embodiment of the present invention has a programmable MIMD (multiple instruction multiple data) ray tracing architecture that supports speculative execution of hit and intersection shaders. In particular, it focuses on reducing the scheduling and communication overhead between the programmable SIMD / SIMT core / execution unit 4001 described above with respect to FIG. 46 and the fixed function MIMD traverse / intersection unit 4605 in a hybrid ray tracing architecture. Described below is a scheme for speculative execution of multiple hit and intersection shaders that can be dispatched in a single batch from the traverse hardware and avoid multiple traverse and shading round trips. One embodiment includes dedicated circuitry for implementing these techniques.

[0436] Embodiments of the present invention are particularly advantageous when required by ray traversal queries where the execution of multiple hit or intersection shaders imposes significant overhead when implemented without dedicated hardware support. These include, but are not limited to, nearest k hit queries (which launch a hit shader for the k nearest intersections) and multiple programmable intersection shaders.

[0437] The techniques described herein are implemented as extensions to the architecture shown in Figure 46 (and described with respect to Figures 46-50). In particular, the present embodiment of the invention builds upon this architecture with improvements to improve performance for the use cases described above.

[0438] The performance limitation of the hybrid ray traversal architecture is the overhead of launching traverse queries from the execution units and invoking programmable shaders from the ray tracing hardware. When multiple hit or intersection shaders are invoked during the traversal of the same ray, this overhead generates an "execution round trip" between the programmable core 4601 and the traverse / intersection unit 4605. This puts additional pressure on the sort unit 4608, which must extract SIMD / SIMT coherence from the individual shader invocations.

[0439] Several aspects of ray tracing require programmable control that can be expressed through different shader types (i.e., Primary, Hit, Any Hit, Miss, Intersection, Traversal, Callable) listed in Table A above. There are multiple shaders in each type. For example, each material may have a different hit shader. Several of these shader types are defined in the current Microsoft® ray tracing API.

[0440] In summary, recursive ray tracing begins with an API function that instructs the GPU to emit a primary shader that can generate a ray-scene intersection (implemented in hardware and / or software) for a primary ray, which in turn can generate other shaders such as traverse, hit, or miss shaders. A shader that generates a child shader can also receive return values ​​from the shader. A callable shader is a generic function that can be generated directly by another shader and can also return values ​​to the calling shader.

[0441] Ray traversal computes ray-scene intersections by traversing and intersecting nodes in a bounding volume hierarchy (BVH). Recent research has shown that the efficiency of computing ray-scene intersections can be improved by orders of magnitude using techniques that are better suited to fixed-function hardware, such as low-precision arithmetic, BVH compression, per-ray state machines, dedicated intersection pipelines, and custom caches.

[0442] The architecture shown in Figure 46 includes such a system in which an array of SIMD / SIMT cores / execution units 4601 interact with a fixed function ray tracing / intersection unit 4605 to perform programmable ray tracing. Programmable shaders are mapped to SIMD / SIMT threads on the execution units / cores 4601, where SIMD / SIMT utilization, execution, and data coherence are important for optimal performance. Ray queries can disrupt coherence for a variety of reasons, including: · Traversal Differences: The duration of BVH traversal varies significantly between rays that support asynchronous ray processing. Execution divergence: Rays generated from different lanes of the same SIMD / SIMT thread may result in different shader invocations. Data access differences: For example, rays hitting different faces sample different BVH nodes, primitives and shaders access different textures, and various other scenarios can cause data access issues.

[0443] In one embodiment, the fixed function ray tracing / intersection unit 4005 overcomes the first two problems by processing each ray individually and out of order. This, however, collapses the SIMD / SIMT groups. The sort unit 4608 is now responsible for forming new coherent SIMD / SIMT groups of shader invocations to be re-dispatched to the execution units.

[0444] It is easy to see the advantages of such an architecture compared to a purely software-based ray tracing implementation on a SIMD / SIMT processor. However, there is overhead associated with messaging between the SIMD / SIMT core / execution unit 4601 (sometimes referred to herein simply as a SIMD / SIMT processor or core / EU) and the MIMD traverse / intersection unit 4605. Furthermore, the sort unit 4608 may not abstract full SIMD / SIMT utilization from non-coherent shader invocations.

[0445] One embodiment of the present invention identifies a use case where shader invocations may be particularly frequent during traversal. Extensions for hybrid MIMD ray tracing processors are described to significantly reduce communication overhead between the Core / EU 4601 and the Traverse / Intersection Unit 4605. This embodiment may be particularly advantageous when finding k-nearest intersections and in the implementation of programmable intersection shaders. However, it is noted that the techniques described herein are not limited to any particular processing scenario.

[0446] A high-level cost summary of the ray tracing context switches between the Core / EU 4601 and the Fixed Function Traverse / Intersection Unit 4605 is provided below. Most of the performance overhead is caused by these two context switches every time a shader invocation is required during a single ray traverse.

[0447] Each SIMD / SIMT lane that launches a ray generates a create message to the traverse / intersection unit 4005 associated with the BVH to be traversed. The data (ray traverse context) is relayed to the traverse / intersection unit 4605 via the create message and (cached) memory. When the traverse / intersection unit 4605 is ready to allocate a new hardware thread for the create message, it loads the traverse state and performs the traverse on the BVH. There is also setup cost that needs to be performed before the first traversal step can be performed on the BVH.

[0448] Figure 51 illustrates the operational flow of a programmable ray tracing pipeline, according to one embodiment of the present invention. In the illustrated embodiment, the shaded elements such as traversal 5102 and intersection 5103 are implemented in fixed function circuitry, while the remaining elements are implemented by programmable cores / execution units.

[0449] The primary ray shader 5101 sends work to the traversal circuit (5102), which traverses the current ray through the BVH (or other acceleration structure). When a leaf node is reached, the traversal circuit calls the intersection circuit (5103), which, upon identifying a ray triangle intersection, calls an optional shader (5104) (optional shaders may return results to the traversal circuit as shown).

[0450] Alternatively, the traversal may terminate before a leaf node is reached and the nearest hit shader (5107) (if a hit is recorded) or the miss shader (5106) (in the case of a miss) is called.

[0451] As shown at 5105, the intersection shader may be called when the traversal circuitry reaches a custom primitive leaf node. The custom primitive may be any non-triangular primitive, such as a polygon or polyhedron (e.g., a tetrahedron, voxel, hexahedron, wedge, pyramid, or other "unstructured volume"). The intersection shader 5105 identifies any intersection between the ray and the custom primitive and passes it to an optional hit shader 5104, which implements any hit processing.

[0452] In one embodiment, when hardware traversal 5102 reaches a programmable stage, traverse / intersection unit 5105 generates a shader dispatch message to associated shader 5105-5107, which corresponds to a single SIMD lane of the execution unit used to execute the shader. Because dispatches occur in arbitrary ray order and differ in the programs that are invoked, one embodiment of sort unit 4608n accumulates multiple dispatches to extract a coherent SIMD batch. The updated traverse state and optional shader arguments may be written to memory 2511 by traverse / intersection unit 4605.

[0453] For the k-nearest intersection problem, the nearest hit shader 5107 is executed for the first k intersections. In the traditional approach, this means finding the nearest intersection, invoking the hit shader, and generating a new ray from the hit shader to terminate the ray traversal upon finding the new nearest intersection (with a ray origin offset so the same intersection does not occur again). It is easy to see that this implementation requires k ray generation for a single ray. Another implementation uses an insertion sort operation to work with an optional hit shader 5104 that is called for every intersection and maintains a global list of nearest intersections. The main problem with this approach is that there is no upper bound on any hit shader invocation.

[0454] As mentioned above, the intersection shader 5105 may be invoked on non-triangle (custom) primitives. Depending on the outcome of the intersection test and the traversal state (pending tuple and primitive intersections), traversal of the same ray may continue after execution of the intersection shader 5105. Thus, finding the closest intersection may require several round trips to the execution unit.

[0455] One embodiment of the present invention focuses on reducing SIMD-MIMD context switching for intersection shaders 5105 and hit shaders 5104, 5107 through modifications to the traversal hardware and shader scheduling model. First, the ray traversal circuitry 4605 defers shader invocations by accumulating multiple possible invocations and dispatching them into larger batches. Additionally, certain invocations that are found to be unnecessary may be culled at this stage. Additionally, one embodiment of the shader scheduler 4607 aggregates multiple shader invocations from the same traversal context into a single SIMD batch. This results in a single ray generation message. In one embodiment, the traversal hardware 4605 pauses the traversal thread to wait for the results of multiple shader invocations. This mode of operation is referred to herein as "speculative" shader execution, since it allows for the invocation of multiple shaders, some of which may not be invoked when using sequential invocations.

[0456] FIG. 52A shows an example where a traversal operation encounters multiple custom primitives 5250 in a subtree. FIG. 52B shows how this can be resolved with three cross dispatch cycles C1-C3. In particular, the scheduler 4607 of this embodiment requires three cycles to submit work to the SIMD processor 4601, and the traverse circuitry 4605 requires three cycles to provide the results to the sort unit 4608. The traversal state 5201 required by the traverse circuitry 4605 is stored in a memory such as a local cache (e.g., an L1 cache and / or an L2 cache). A. Deferred ray-traced shader invocation

[0457] One embodiment of the present invention modifies the hardware traversal state 5201 to be managed to allow for accumulation in a list of multiple possible intersections or hit invocations. At a given time during the traversal, each entry in the list may be used to generate a shader invocation. For example, the k-closest intersections may be accumulated on the traversal hardware 4605 and / or in the traversal state 5201 in memory, and when the traversal is complete, a hit shader can be called for each element. In the hit shader, multiple possible intersections may be accumulated for subtrees in the BVH.

[0458] In the k-nearest use case, the advantage of this approach is that instead of k-1 round trips to the SIMD core / EU 4601 and k-1 new ray generation messages, all hit shaders are invoked on the traverse circuitry 4605 from the same traverse thread during a single traverse operation. A possible implementation challenge is that it is not easy to guarantee the order of execution of hit shaders (a standard "round trip" approach guarantees that the hit shader of the nearest intersection is executed first, etc.). In one embodiment, this is solved by relaxing the order or synchronization of hit shaders.

[0459] In the intersection shader use case, the traversal circuit 4605 does not know in advance whether a given shader will return a positive intersection test. However, multiple intersection shaders can be speculatively executed, and if at least one returns a positive hit result, it is merged into a global nearest neighbor list. A particular implementation needs to find an optimal number of delayed intersection tests to reduce the number of dispatch calls but avoid too many calls of redundant intersection shaders. B. Aggregation of shader calls from traversal circuits

[0460] When dispatching multiple shaders for the same ray generated on the traversal circuit, one embodiment creates a branch in the flow of the ray traversal algorithm. This can be problematic for intersection shaders because the remaining BVH traversal depends on all dispatched intersection tests. This means that synchronous operations are required to wait for the results of the shader invocations, which can be a challenge on asynchronous hardware.

[0461] One embodiment of the present invention relies on two points for fusing the results of shader invocations: the SIMD processor 4601 and the traversal circuitry 4605. With respect to the SIMD processor 4601, multiple shaders can be synchronized and their results aggregated using standard programming models. One relatively simple way to do this is to use a global atomic and aggregate the results into a shared data structure in memory where the intersection results of multiple shaders can be stored. The last shader then resolves the data structure and calls back to the traversal circuitry 4605 to continue the traversal.

[0462] One embodiment of the present invention implements a more efficient approach that restricts execution of multiple shader invocations to the same SIMD lane on SIMD processor 4601. Intersection tests are then reduced locally using SIMD / SIMT reduce operations (rather than relying on global atomics). This embodiment may rely on new circuitry in sort unit 4608 to keep small batches of shader invocations within the same SIMD branch.

[0463] One embodiment of the present invention pauses execution of the traverse thread on the traverse circuitry 4605. With a traditional execution model, once a shader is dispatched to a traverse thread, the traverse thread is terminated and the ray traverse state is saved to memory to allow other ray generation commands to execute while the execution unit 4601 processes the shader. If the traverse thread were simply paused, the traverse state would not need to be stored and each shader result could be awaited individually. This embodiment may include circuitry to avoid deadlocks and provide good hardware utilization.

[0464] 53-54 show an embodiment of a deferred model invoking a single shader invocation on a SIMD core / execution unit 4601 with three shaders. When saved, all intersection tests are evaluated within the same SIMD / SIMT group. Therefore, the nearest intersection can also be calculated on the programmable core / execution unit 4601.

[0465] As discussed above, all or part of the shader aggregation and / or deferral may be performed by the traverse / intersection circuitry 4605 and / or the core / EU scheduler 4607. Figure 53 illustrates an embodiment in which the shader deferral / aggregation circuitry 5306 in the scheduler 4007 delays the scheduling of shaders associated with a particular SIMD / SIMT thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the scheduler 4007 dispatches the multiple aggregated shaders to the core / EU 4001 in a SIMD / SIMT batch.

[0466] 54 illustrates an embodiment in which a shader delay / aggregation circuit 5405 in the traverse / intersection circuit 4005 delays the scheduling of shaders associated with a particular SIMD thread / lane until a specified trigger event occurs. Upon detecting the trigger event, the traverse / intersection circuit 4005 submits the aggregated shaders to the sort unit 4008 in a single SIMD / SIMT batch.

[0467] However, note that the shader latency and aggregation techniques may be implemented within various other components such as the sort unit 4008, or may be distributed across multiple components. For example, the traversal / intersection circuit 405 may perform a first set of shader aggregation operations, the scheduler 4007 may perform a second set of shader aggregation operations, ensuring that the shaders of the SIMD threads are efficiently scheduled on the cores / EUs 4001.

[0468] The "trigger event" for dispatching the aggregated shaders to the cores / EUs may be a processing event such as a specific number of accumulated shaders or the minimum latency associated with a particular shader. Alternatively or additionally, the trigger event may be a timing event such as a specific period from the latency of the first shader or a specific number of processor cycles. Other variables such as the current workload on the cores / EUs 4001 and the traversal / intersection unit 4005 may also be evaluated by the scheduler 4007 to determine when to dispatch the SIMD / SIMT batches of shaders.

[0469] Different embodiments of the present invention may be implemented using different combinations of the approaches described above, depending on the specific system architecture and application requirements being used. <Ray Tracing instruction>

[0470] The ray tracing instructions described below are included in an instruction set architecture (ISA) supported by one embodiment of the CPU 3799 and / or GPU 3705. When executed by the CPU, single instruction multiple data (SIMD) instructions may utilize vector / packed source and destination registers to perform the described operations and may be decoded and executed by a CPU core. When executed by the GPU 3705, the instructions may be executed by the graphics core 3730. For example, any of the execution units (EUs) 4601 described above may execute the instructions. Alternatively or additionally, the instructions may be executed by execution circuitry on the ray tracing core 3150 and / or tensor core 3740.

[0471] Figure 55 illustrates one embodiment of an architecture for executing ray tracing instructions, described below. The illustrated architecture may be integrated into one or more of the above-mentioned cores 3730, 3740, 3750 (see Figure 37 and related discussion) that may be included in different processor architectures.

[0472] In operation, the instruction fetch unit 5503 fetches ray tracing instructions from memory and the decoder 5595 decodes the instructions. In one embodiment, the decoder 5595 decodes the instructions to generate executable operations (e.g., micro-operations, or uops in a microcode core). Alternatively, some or all of the ray tracing instructions 5500 may be executed without decoding, e.g., no decoder 5504 is required.

[0473] In either implementation, scheduler / dispatcher 5505 schedules and dispatches instructions (or operations) across a set of functional units (FUs) 5510-5512. The illustrated embodiment includes a vector FU 5510 that executes SIMD instructions that operate simultaneously on multiple packed data elements stored in vector registers 5515, and a scalar FU 5511 that operates on scalar values ​​stored in one or more scalar registers 5516. An optional ray trace FU 5512 may operate on the packed data values ​​stored in vector registers 5515 and / or the scalar values ​​stored in scalar registers 5516. In one embodiment, without a dedicated FU 5512, the vector FU 5510 and possibly scalar FU 5511 execute ray trace instructions, described below.

[0474] The various FUs 5510 5510-5512 access ray tracing data 5502 (e.g., traverse / intersection data) required to execute the ray tracing instructions 550 from vector registers 5515, scalar registers 5516, and / or a local cache subsystem 5508 (e.g., an L1 cache). In one embodiment, the FUs 5510-5512 may also perform accesses to memory 3198 via load and store operations, and the cache subsystem 5508 may operate independently to cache data locally.

[0475] While the ray tracing instructions are used to improve the performance of ray traverse / intersection and BVH construction, they may also be applicable to other areas such as high performance computing (HPC) and general purpose GPU (GPGPU) implementations.

[0476] In the following description, the term "doubleword" may be abbreviated as dw, and unsigned byte is abbreviated as ub. Additionally, the source and destination registers referred to below (e.g., src0, src1, dest, etc.) may represent vector registers 5515 or in some cases a combination of vector registers 5515 and scalar registers 5516. Typically, when a source or destination value used by an instruction contains packed data elements (e.g., when the source or destination stores N data elements), vector registers 5515 are used. Other values ​​may use scalar registers 5516 or vector registers 5515. <dequantize>

[0477] One embodiment of the Dequantize instruction "dequantizes" a previously quantized value. As an example, in a ray tracing implementation a particular BVH subtree may be quantized to reduce storage and bandwidth requirements. One embodiment of the Dequantize instruction takes the form dequantize dest src0 src1 src2, where source register src0 stores N unsigned bytes, source register src1 stores one unsigned byte each, source register src2 stores one floating point value, and destination register dest stores N floating point values. All of these registers may be vector registers 5515. Alternatively, src0 and dest may be vector registers 5515 and src1 and src2 may be scalar registers 5516.

[0478] The following code sequence defines one particular implementation of the inverse quantization instruction.

number

[0479] One embodiment of the selective min or max instruction performs a per-lane min or max operation (i.e., returns the min or max of a set of values) as indicated by the bits in a bit mask. The bit mask may utilize vector register 5515, scalar register 5516, or a separate set of mask registers (not shown). The following code sequence defines one particular implementation of the min / max instruction. sel_min_max dest src0 src1 src2, where src0 stores N doublewords, src1 stores N doublewords, src2 supplies one doubleword per service, and the destination register stores N doublewords.

[0480] The following code sequence defines one particular implementation of the selective min / max instruction.

Number

[0481] One embodiment of the shuffle index instruction can copy any set of input lanes to output lanes. At 32-bit SIMD width, this instruction may be executed with lower throughput. This embodiment takes the form shuffle_index dest src0 sorc1 <optional flag>, where src0 stores N doublewords, src1 stores N unsigned bytes (i.e., index values), and dest stores N doublewords.

[0482] The following code sequence defines one specific implementation of the shuffle index instruction.

Number

[0483] In the above code, the index in src1 identifies the current lane. If the i-th value in the execution mask is set to 1, a check is performed to ensure that the source lane is within the range of 0 to the SIMD width. If it is within the range, a flag is set (srcLaneMod), and the destination data element i is set equal to the data element i of src0. If the lane is within the range (i.e., valid), the index value from src1 (srcLane0) is used as the index into src0 (dst[i]=src0[srcLane]). <Immediate Shuffle Up / Dn / XOR Instruction>

[0484] In one embodiment, the immediate shuffle Up / Dn / XOR instruction shuffles the input data elements / lanes based on the immediate value of the instruction. In one implementation, the immediate value specifies that the input lanes are shifted by 1, 2, 4, 8, or 16 positions based on the value of the immediate. Optionally, an additional scalar source register can be specified as the fill value. When the source lane index is invalid, the fill value (if provided) is stored in the data element value in the destination. If no fill value is provided, all data element positions are set to 0.

[0485] In one embodiment, a flag register is used as the source mask. When the flag bit of the source lane is set to 1, the source lane is marked as invalid and the instruction proceeds.

[0486] The following are examples of different implementations of the immediate shuffle instruction.

Number

[0487] The following code sequence defines one specific implementation of the immediate shuffle instruction.

Number

[0488] Here, the input data elements / lanes are shifted by only 1, 2, 4, 8, or 16 positions based on the value of an immediate. Register src1 is an additional scalar source register used as the fill value to be stored in the data element position in the destination when the source lane index is invalid. If no fill value is provided and the source lane index is invalid, the data element position in the destination is set to 0. A flag register (FLAG) is used as the source mask. If the flag bit of a source lane is set to 1, the source lane is marked as invalid and the instruction proceeds as described above. <Indirect Shuffle Up / Dn / XOR Instruction>

[0489] The indirect shuffle instruction has a source operand (src1) that controls the mapping from source lanes to destination lanes. One embodiment of the indirect shuffle instruction takes the following form.

Number

[0490] The following code sequence defines one specific implementation of the indirect shuffle instruction.

Number

[0491] Therefore, the indirect shuffle instruction operates in the same manner as the immediate shuffle instruction described above, except that the mapping from the source lane to the destination lane is controlled by the source register src1 rather than being immediate. <Cross Lane Min / Max Instruction>

[0492] Embodiments of the cross lane minimum / maximum instruction are supported for floating point and integer data types. The cross lane minimum instruction takes the form lane_min dest src0, and the cross lane maximum instruction takes the form lane_max dest src0. Here, src0 stores N double words and dest stores 1 double word.

[0493] As an example, the following code sequence defines one particular implementation of the cross lane minimum.

Number

[0494] Embodiments of the cross lane minimum index instruction m take the form lane_min_index dest src0, and the cross lane maximum index instruction takes the form lane_max_index dest src0. Here, src0 stores N double words and dest stores 1 double word.

[0495] As an example, the following code sequence defines one particular implementation of the cross lane minimum index instruction.

Number

[0496] In one embodiment, a cross-lane sorting network instruction sorts all N input elements in ascending (sortnet_min) or descending (sortnet_max) order using an N-wide (stable) sorting network. The minimum / maximum versions of the instruction take the form sortnet_min dest src0 and sortnet_max dest src0, respectively. In one implementation, src0 and dest store N doublewords. The minimum (min) / maximum (max) sort can be performed on the N doublewords of src0, and the elements sorted in ascending (for min) or descending (for max) order are stored in dest in their respective sorted order. An example of the code sequence defining the instruction is dest = apply_N_wide_sorting_network_min / max(src0). <Cross Lane Sorting Network Index instruction>

[0497] In one embodiment, the cross-lane sorting network index instruction sorts all N input elements in ascending (sortnet_min) or descending (sortnet_max) order using an N-wide (stable) sorting network and returns an ordering (permute) index. Min / max versions of the instruction take the form sortnet_min_index dest src0 and sortnet_max_index dest src0, where src0 and dest each store N double words. An example of a code sequence defining the instruction is dest=apply_N_wide_sorting_network_min / max_index(src0).

[0498] One embodiment of a method for executing any of the instructions described above is illustrated in Figure 56. The method may be implemented on the specific processor architectures described above, but is not limited to any particular processor or system architecture.

[0499] At 5601, instructions of the primary graphics thread are executed on a processor core, which may include, for example, any of the cores described above (e.g., graphics core 3730). Once ray tracing work arrives in the primary graphics thread, at 5602, the ray tracing instructions are offloaded to a ray tracing execution circuit, which may be in the form of a functional unit (FU) as described above with respect to FIG. 55, or which may be a dedicated ray tracing core 3150 as described with respect to FIG. 37.

[0500] At 5603, the ray tracing instructions are fetched from memory and decoded. At 5606, the instructions are decoded into executable operations (in embodiments requiring a decoder). At 5604, the ray tracing instructions are scheduled and dispatched for execution by the ray tracing circuitry. At 5605, the ray tracing instructions are executed by the ray tracing circuitry. For example, the instructions may be dispatched to and executed by the FUs mentioned above (e.g., FU 5510, ray tracing FU 4912, etc.) and / or the graphics core 3730 or the ray tracing core 3750.

[0501] Once execution is complete for the ray tracing instructions, the results are stored (e.g., stored in memory 3798) at 5606. The primary graphics thread is notified at 5607. At 5608, the ray tracing results are processed (e.g., read from memory and integrated into the graphics rendering results) within the context of the primary thread.

[0502] In the above embodiments, the terms "engine" or "module" or "logic" may represent, be part of, or include an application specific integrated circuit (ASIC), electronic circuitry, processor (shared, dedicated, or group), and / or memory (shared, dedicated, or group), coupled logic circuitry, and / or other suitable components that execute one or more software or firmware programs, and / or provide the described functionality. In embodiments, the engine, module, or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware, and software.

[0503] An embodiment of the present invention may include various steps as described above. The steps may be implemented in machine-executable instructions that may be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by dedicated hardware components that contain hardwired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0504] As described herein, instructions may represent a particular configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform a particular operation or having a predetermined functionality, or software instructions stored in a memory embodied in a non-transitory computer readable medium. Thus, the techniques illustrated in the figures may be implemented using code and data stored in and executed by one or more electronic devices (e.g., end stations, network elements, etc.). Such electronic devices store and communicate (internally and / or with other electronic devices over a network) code and data using computer readable media such as non-transitory computer machine readable storage media (e.g., magnetic disks, optical disks, random access memory, read only memory, flash memory devices, phase change memory) and transient computer machine readable communication media (e.g., electrical, optical, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.).

[0505] Furthermore, such electronic devices typically include one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of the set of processors and other components is typically via one or more buses and bridges (also referred to as bus controllers). The signals carrying the storage devices and network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage devices of a given electronic device typically store code and / or data for execution on the set of one or more processors of the electronic device. Of course, one or more portions of an embodiment of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout the detailed description, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. In certain instances, well-known structures and functions have not been described in detail in order to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the invention should be judged in terms of the following claims. [Explanation of symbols]

[0506] 102 processors 104 Cache 106 Register File 107 processor cores 108 Graphics Processor 109 Instruction Set 110 Interface Bus 111 Display device 112 Accelerator 116 Memory control unit 118 External Graphics Processor 119 External Accelerators 120 Memory Device 121 Command 122 Data 124 Data storage device 125 Touch Sensor 126 Radio Transceiver 128 Firmware Interface 130 Platform Control Hub 134 Network Control Unit 140 Legacy I / O Control Unit 142 USB control unit 143 Keyboard / Mouse 144 Camera 146 Audio control section< / dequantize>

Claims

1. running an application having multiple threads; identifying a first subset of threads for execution on a local graphics processor and a second subset of threads for execution on a virtualized representation of the local processor; scheduling the first subset of threads on the local graphics processor; scheduling the second subset of threads by sending the threads or representations of the threads to a cloud-based processing resource associated with the virtualized representation of the local processor; combining a first result of executing the first subset of threads on the local graphics processor with a second result of executing the second subset of threads on the cloud-based processing resource to render an image frame; Including, a first command associated with a first graphics thread in the first thread subset is stored in a first command buffer and a second command associated with a second graphics thread in the second thread subset is stored in a second command buffer, the first command buffer and the second command buffer being on the local graphics processor.

2. The method of claim 1 , further comprising: evaluating the plurality of threads to identify the first and second subsets of threads.

3. 3. The method of claim 2, wherein evaluating the plurality of threads further comprises evaluating execution requirements associated with the plurality of threads in terms of metrics associated with execution on the virtualized representation of the local processor.

4. 4. The method of claim 3, wherein the execution requirements include latency and / or bandwidth thresholds, and the metrics include average or current latency and / or bandwidth based on network conditions between the local graphics processor and the cloud-based processing resource associated with execution on the virtualized representation of the local processor.

5. The method of claim 1 or 4, further comprising the step of installing and / or enumerating the local graphics processor and the virtualized representation of the local processor.

6. 6. The method of claim 1 or 5, further comprising: scheduling the first graphics thread on the local graphics processor by transferring the first command to a first command queue of the local graphics processor, the local graphics processor processing the first command from the first command queue.

7. 7. The method of claim 6, further comprising: scheduling the second graphics thread on a virtualized representation of a second local graphics processor by forwarding the second command to a second command queue, wherein the cloud-based graphics execution resource processes the second command from the second command queue.

8. The method of claim 1 or 7, wherein the first subset of threads is assigned delay-tolerant tasks and the second subset of threads is assigned delay-sensitive tasks.

9. A machine-readable medium having stored thereon program code that, when executed by a machine, causes the machine to perform operations, the operations including: running an application having multiple threads; identifying a first subset of threads for execution on a local graphics processor and a second subset of threads for execution on a virtualized representation of the local processor; scheduling the first subset of threads on the local graphics processor; scheduling the second subset of threads by sending the threads or representations of the threads to a cloud-based processing resource associated with the virtualized representation of the local processor; combining a first result of executing the first subset of threads on the local graphics processor with a second result of executing the second subset of threads on the cloud-based processing resource to render an image frame; Including, a first command associated with a first graphics thread in the first thread subset is stored in a first command buffer and a second command associated with a second graphics thread in the second thread subset is stored in a second command buffer, the first command buffer and the second command buffer being present on the local graphics processor.

10. evaluating the plurality of threads to identify the first and second subsets of threads; 10. The machine readable medium of claim 9, further comprising program code for causing the machine to perform operations including:

11. 11. The machine-readable medium of claim 10, wherein evaluating the plurality of threads further comprises evaluating execution requirements associated with the plurality of threads in terms of metrics associated with execution on the virtualized representation of the local processor.

12. 12. The machine-readable medium of claim 11, wherein the execution requirements include latency and / or bandwidth thresholds and the metrics include average or current latency and / or bandwidth based on network conditions between the local graphics processor and the cloud-based processing resource associated with execution on the virtualized representation of the local processor.

13. 13. The machine-readable medium of claim 9 or 12, further comprising program code for causing the machine to perform operations including installing and / or enumerating the local graphics processor and the virtualized representation of the local processor.

14. 14. The machine-readable medium of claim 9 or 13, further comprising program code for causing the machine to perform operations including: scheduling the first graphics thread on the local graphics processor by transferring the first command to a first command queue of the local graphics processor, the local graphics processor processing the first command from the first command queue.

15. 15. The machine-readable medium of claim 14, further comprising program code for causing the machine to perform operations including: scheduling the second graphics thread on a virtualized representation of a second local graphics processor by forwarding the second command to a second command queue, wherein the cloud-based graphics execution resource processes the second command from the second command queue.

16. 16. The machine-readable medium of claim 9 or 15, wherein the first subset of threads is assigned delay-tolerant tasks and the second subset of threads is assigned delay-sensitive tasks.

17. a local graphics processor that runs multiple threads of an application; a graphics processor virtualization circuit and / or logic for generating a virtualized representation of the local processor; a scheduler that identifies a first subset of threads for execution on a local graphics processor and a second subset of threads for execution on a virtualized representation of the local processor; Including, the scheduler schedules the first subset of threads on the local graphics processor and the second subset of threads by sending the threads or representations of the threads to a cloud-based processing resource associated with the virtualized representation of the local processor; the local graphics processor combines a first result of executing the first subset of threads on the local graphics processor with a second result of executing the second subset of threads on the cloud-based processing resource to render an image frame; a first command associated with a first graphics thread in the first thread subset is stored in a first command buffer and a second command associated with a second graphics thread in the second thread subset is stored in a second command buffer, the first command buffer and the second command buffer being on the local graphics processor.

18. 20. The apparatus of claim 17, wherein the scheduler includes evaluation circuitry / logic to evaluate the plurality of threads to identify the first and second subsets of threads.

19. 20. The apparatus of claim 18, wherein evaluating the plurality of threads further comprises evaluating execution requirements associated with the plurality of threads in terms of metrics associated with execution on the virtualized representation of the local processor.

20. 20. The apparatus of claim 19, wherein the execution requirements include latency and / or bandwidth thresholds, and the metrics include average or current latency and / or bandwidth based on network conditions between the local graphics processor and the cloud-based processing resource associated with execution on the virtualized representation of the local processor.

21. 21. An apparatus as claimed in claim 17 or 20, further comprising circuitry and / or logic for installing and / or enumerating the virtualised representation of the local graphics processor and the local processor.

22. 22. The apparatus of claim 17 or 21, wherein the scheduler schedules the first graphics thread on the local graphics processor by transferring the first command to a first command queue of the local graphics processor, and the local graphics processor processes the first command from the first command queue.

Images