Signal Synthesizer

Abstract

In some aspects, the receiver includes first amplifiers, each having an input and an output. The receiver also includes second amplifiers, each having an input and an output, the output of the second amplifiers coupled to the combining node. The receiver also includes transmission lines, each coupled between an output of a respective one of the first amplifiers and an input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node and receiver elements, each having an input and an output, the output of each of the receiver elements coupled to the input of a respective one of the first amplifiers.

Description

Claiming priority

[0001]

[0001] This patent application claims priority to U.S. Non-Provisional Application No. 16 / 557,961, entitled "SIGNAL COMBINER," filed on August 30, 2019, assigned to the assignee of the present application, and expressly incorporated herein by reference. [Technical field]

[0002] Aspects of the present disclosure relate generally to wireless communications, and more particularly, to signal combiners for use in phased array receivers. [Background technology]

[0003]

[0003] Phased antenna arrays are used in wireless communication systems (e.g., fifth generation (5G) communication systems) operating in the millimeter wave (mmWave) band (e.g., tens of gigahertz). Phased antenna arrays enable wireless devices to transmit and / or receive signals with high directionality for increased range. Summary of the Invention

[0004]

[0004] The following presents a simplified summary of one or more implementations in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, nor is it intended to identify key or critical elements of all implementations or to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that is presented later.

[0005]

[0005] A first aspect relates to a receiver. The receiver includes a first amplifier(s), each of the first amplifiers having an input and an output. The receiver also includes a second amplifier(s), each of the second amplifiers having an input and an output, the output of the second amplifiers being coupled to a combining node. The receiver also includes a transmission line, each of the transmission lines being coupled between an output of a respective one of the first amplifiers and an input of a respective one of the second amplifiers. The receiver further includes a load coupled to the combining node, and a receiver element(s), each of the receiver elements having an input and an output, the output of each of the receiver elements being coupled to an input of a respective one of the first amplifiers.

[0006]

[0006] A second aspect relates to a method for signal combining, the method including receiving signals from receiver elements, amplifying the signals from the receiver elements into a first amplified signal, and driving a transmission line with the first amplified signal. The method also includes receiving the first amplified signal from the transmission line, amplifying the first amplified signal from the transmission line into a second amplified signal, and combining the second amplified signal into a combined signal.

[0007]

[0007] To the accomplishment of the foregoing and related ends, the one or more implementations comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the one or more implementations. These aspects are indicative, however, of but a few of the various ways in which the principles of the various implementations may be employed, and the described implementations are intended to include all such aspects and their equivalents. [Brief description of the drawings]

[0008] [Figure 1]

[0008] FIG. 2 illustrates an example of steering the receive direction of a phased antenna array using a phase shifter in accordance with some aspects of the present disclosure. [Diagram 2]

[0009] FIG. 1 illustrates an example of a phased antenna array in accordance with some aspects of the present disclosure. [Diagram 3]

[0010] FIG. 1 illustrates an example of a phased array receiver in accordance with certain aspects of the present disclosure. [Figure 4]

[0011] FIG. 1 illustrates another example of a phased array receiver in accordance with certain aspects of the present disclosure. [Diagram 5]

[0012] FIG. 1 illustrates yet another example of a phased array receiver in accordance with certain aspects of the present disclosure. [Figure 6]

[0013] FIG. 1 illustrates an example of a dual-band phased array receiver in accordance with certain aspects of the present disclosure. [Figure 7]

[0014] FIG. 2 illustrates an example of a combiner according to some aspects of the present disclosure. [Figure 8]

[0015] 1 illustrates an example in which inputs of a combiner are coupled to respective receiver elements in accordance with some aspects of the present disclosure. [Figure 9]

[0016] FIG. 2 illustrates an example implementation of a current amplifier in accordance with certain aspects of the present disclosure. [Figure 10]

[0017] FIG. 2 illustrates an example implementation of a current amplifier with adjustable current gain in accordance with certain aspects of the present disclosure. [Figure 11]

[0018] FIG. 2 illustrates an example of a combiner including a current amplifier, in accordance with some aspects of the present disclosure. [Figure 12]

[0019] FIG. 2 illustrates an example of a combiner including a common gate amplifier in accordance with some aspects of the present disclosure. [Figure 13]

[0020] FIG. 2 illustrates an example of a combiner including a common-gate amplifier with adjustable channel width in accordance with some aspects of the present disclosure. [Figure 14A]

[0021] FIG. 2 illustrates an example implementation of a common gate amplifier with adjustable channel width in accordance with some aspects of the present disclosure. [Figure 14B]

[0022] FIG. 1 illustrates another example implementation of a common-gate amplifier with adjustable channel width in accordance with some aspects of the present disclosure. [Figure 15]

[0023] FIG. 2 illustrates an example of a combiner including a current amplifier and a common-gate amplifier in accordance with some aspects of the present disclosure. [Figure 16]

[0024] FIG. 2 illustrates an example of a combiner including a matching network in accordance with some aspects of the present disclosure. [Figure 17A]

[0025] FIG. 1 illustrates an example implementation of a matching network in accordance with certain aspects of the present disclosure. [Figure 17B]

[0026] FIG. 1 illustrates another example implementation of a matching network in accordance with certain aspects of the present disclosure. [Figure 18]

[0027] FIG. 2 illustrates an example of an inter-chip combiner in accordance with some aspects of the present disclosure. [Figure 19]

[0028] FIG. 2 illustrates an example of multiple combiners coupled in a tree configuration in accordance with some aspects of the present disclosure. [Figure 20]

[0029] FIG. 2 illustrates an example of multiple combiners coupled in a chain configuration, in accordance with some aspects of the present disclosure. [Figure 21]

[0030] 1 is a flowchart illustrating a method for signal synthesis in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009]

[0031] The detailed description set forth below with reference to the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0010]

[0032] Operating a wireless communication system (e.g., a 5G communication system) in the mmWave band enables the wireless communication system to transmit signals at a wider bandwidth for higher data rates. However, wireless communication systems operating in the mmWave band may suffer from high signal attenuation. To compensate for high signal attenuation, wireless devices operating in the mmWave band include phased antenna arrays that enable the wireless device to receive and / or transmit signals with high directionality for improved range.

[0011]

[0033] The receive direction of a phased antenna array may be electronically steered by shifting the phase of signals received by antennas in the phased antenna array. An example of this is shown in FIG. 1, which shows an example of two adjacent antennas 110-1 and 110-2 in a phased antenna array. The antennas 110-1 to 110-2 are coupled to adjustable (i.e., tunable) phase shifters 115-1 to 115-2, respectively. Each phase shifter 115-1 and 115-2 is configured to shift the phase of signals received by its respective antenna 110-1 and 110-2.

[0012]

[0034] In this example, the distance (i.e., spacing) between antennas 110-1 and 110-2 is d, and the wavefront of a radio signal received by the phased antenna array arrives at an angle θ relative to the antenna boresight. In this example, the wavefront of the radio signal must travel an additional distance of d·sinθ relative to antenna 110-1 to reach antenna 110-2. This additional distance translates into a time delay of:

[0013]

number

[0014] where Δt is the time delay and c is the propagation speed of the radio signal. The time delay Δt can be expressed as a phase shift for a given frequency f as follows:

[0015]

number

[0016] where Δφ is the phase shift between antennas 110-1 and 110-2. Equations (1) and (2) can be combined to express the phase shift as:

[0017]

number

[0018] where λ is the wavelength of the radio signal and is given by c / f. To set the receive direction of the phased antenna array to angle θ, phase shifters 115-1 and 115-2 may be adjusted to provide a phase shift between antennas 110(1) and 110(2) that cancels the phase shift Δφ in equation (3). By canceling the phase shift Δφ, phase shifters 115-2 and 115-2 align the signals received by antennas 110-1 and 110-2 at angle θ, allowing the signals to combine constructively. While FIG. 1 shows an example of two antennas 110-1 and 110-2 for ease of explanation, it should be appreciated that the principles illustrated in FIG. 1 may be extended to the entire phased antenna array or subsections of a phased antenna array to receive signals in a desired direction.

[0019]

[0035] FIG. 2 illustrates an example of a phased antenna array 205 including multiple antennas 210-1-210-k. In FIG. 2, each antenna 210-1-210-k is represented by a small square. Each antenna 210-1-210-k in the phased antenna array 205 may be referred to as an antenna element or another term. In this example, the antennas 210-1-210-k are arranged in a two-dimensional array, but it should be appreciated that the antennas 210-1-210-k may also be arranged in a one-dimensional array or a three-dimensional array. Each of the antennas 210-1-210-k may be implemented by a patch antenna or another type of antenna. In the example illustrated in FIG. 2, the phased antenna array 205 includes 64 antennas 210-1-210-k. However, it should be appreciated that the phased antenna array 205 may include a different number of antennas 210-1-210-k. The phased antenna array 205 may include tens to hundreds of antennas.

[0020]

[0036] The phased antenna array 205 may be incorporated into a wireless device (e.g., a 5G wireless device) to enable the wireless device to receive and / or transmit signals with high directionality. The receive direction of the phased antenna array 205 may be electronically steered (e.g., based on equation (3)) using a phase shifter. For example, the receive direction of the phased antenna array 205 may be set to point toward another wireless device that transmits a signal to the wireless device.

[0021]

[0037] An advantage of operating a wireless device in the mmWave band is that the mmWave band enables the use of small antennas (e.g., in the millimeter range). The small size of antennas 210-1 through 210-k in the mmWave band significantly reduces the area of ​​phased antenna array 205. This allows phased antenna array 205 to be incorporated into a handset, a small base station (e.g., customer premises equipment (CPE)), or another wireless device.

[0022]

[0038] 3 illustrates an example of a phased array receiver 310 for receiving signals from antennas in a phased antenna array (e.g., phased antenna array 205). The phased array receiver 310 includes a number of receiver elements 315-1 to 315-n, each of which is coupled to a respective antenna in the phased antenna array via a respective input 312-1 to 312-n. In one example, the number of receiver elements 315-1 to 315-n is equal to the number of antennas 210-1 to 210-k in the phased antenna array 205, where n is equal to k. In another example, the number of receiver elements 315-1 to 315-n is less than the number of antennas 210-1 to 210-k in the phased antenna array 205. In this example, each of the receiver elements 315-1 through 315-n may be coupled to a respective one of n antennas 210-1 through 210-k in the phased antenna array 205.

[0023]

[0039] Each of the receiver elements 315-1 to 315-n includes a respective low noise amplifier (LNA) 320-1 to 320-n and a respective phase shifter 325-1 to 325-n. Each of the LNAs 320-1 to 320-n is configured to amplify a signal from its respective antenna (e.g., a respective one of the antennas 210-1 to 210-k) and may have a variable gain.

[0024]

[0040] Each of the phase shifters 325-1 to 325-n is configured to shift the phase of its respective signal by a respective phase shift. The phase shifters 325-1 to 325-n are used to set the receive direction of the phased antenna array (e.g., toward a transmitting device). In this regard, the phase shift controller 355 sets the phase shifts of the phase shifters 325-1 to 325-n such that the phase shifters 325-1 to 325-n align the phase of the signals received by the antenna with the desired receive direction. This allows the signals received by the antenna in the desired receive direction to be constructively combined, as will be further described below. For ease of illustration, the individual connections between the phase shift controller 355 and the phase shifters 325-1 to 325-n are not explicitly shown in FIG. 3.

[0025]

[0041] The phased array receiver 310 also includes a plurality of transmission lines 330-1 through 330-n and a combiner 340. Each of the transmission lines 330-1 through 330-n is coupled between an output 327-1 through 327-n of a respective one of the receiver elements 315-1 through 315-n and the combiner 340. The receiver elements 315-1 through 315-n may be spaced apart from one another by the transmission lines 330-1 through 330-n, which route output signals of the receiver elements 315-1 through 315-n to the combiner 340.

[0026]

[0042] The combiner 340 receives the output signals of the receiver elements 315-315-n via their respective transmission lines 330-1-330-n, combines the output signals into a combined signal, and outputs the combined signal at an output 350 of the combiner 340. As explained above, the phase shifters 325-1-325-n align the phases of the signals received by the antennas to the desired receiving direction. As a result, the combiner 340 constructively combines the signals corresponding to the desired receiving direction to generate a combined signal. The combiner 340 may output the combined signal to a receiving circuit (not shown) for further processing (e.g., frequency down-conversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or output the combined signal to another combiner (not shown) for a subsequent combining stage.

[0027]

[0043] 4 illustrates another example of a phased array receiver 410 for receiving signals from antennas in a phased antenna array (e.g., phased antenna array 205). The phased array receiver 410 includes a plurality of receiver elements 415-1 to 415-n, each of which is coupled to a respective antenna in the phased antenna array via a respective input 412-1 to 412-n. In one example, the number of receiver elements 415-1 to 415-n is equal to the number of antennas 210-1 to 210-k in the phased antenna array 205, where n is equal to k. In another example, the number of receiver elements 415-1 to 415-n is less than the number of antennas 210-1 to 210-k in the phased antenna array 205. In this example, each of the receiver elements 415-1 through 415-n may be coupled to a respective one of n antennas 210-1 through 210-k in the phased antenna array 205.

[0028]

[0044] Each of the receiver elements 415-1 through 415-n includes a respective low noise amplifier (LNA) 420-1 through 420-n, a respective phase shifter 424-1 through 424-n, and a respective mixer 426-1 through 426-n. Each of the LNAs 420-1 through 420-n is configured to amplify a signal from its respective antenna (e.g., a respective one of the antennas 210-1 through 210-k) and may have a variable gain.

[0029]

[0045] Each of the phase shifters 424-1 through 424-n is configured to shift the phase of its respective signal by a respective phase shift. The phase shifters 424-1 through 424-n are used to set the receive direction of the phased antenna array (e.g., toward a transmitting device). In this regard, the phase shift controller 455 sets the phase shifts of the phase shifters 424-1 through 424-n such that the phase shifters 424-1 through 424-n align the phase of the signals received by the antenna with the desired receive direction. This allows the signals received by the antenna in the desired receive direction to be constructively combined, as described further below. For ease of illustration, the individual connections between the phase shift controller 455 and the phase shifters 425-1 through 425-n are not explicitly shown in FIG. 4.

[0030]

[0046] Each of the mixers 426-1 to 426-n is configured to receive an LO signal from a local oscillator (LO) 435 and mix the signal from its respective phase shifter 424-1 to 424-n with the LO signal to frequency downconvert the signal from its respective phase shifter 424-1 to 424-n. The frequency downconversion may be from a radio frequency (RF) to an intermediate frequency (IF). Thus, in this example, the frequency downconversion is performed in the receiver elements 415-1 to 415-n prior to signal combination.

[0031]

[0047] The phased array receiver 410 also includes a plurality of transmission lines 430-1 through 430-n and a combiner 440. Each of the transmission lines 430-1 through 430-n is coupled between a respective one of the outputs 428-1 through 428-n of the receiver elements 415-1 through 415-n and the combiner 440. The receiver elements 415-1 through 415-n may be spaced apart from one another by the transmission lines 430-1 through 430-n, which route output signals of the receiver elements 415-1 through 415-n to the combiner 440.

[0032]

[0048] The combiner 440 receives the output signals of the receiver elements 415-415-n via the respective transmission lines 430-1-430-n, combines the output signals into a combined signal, and outputs the combined signal at an output 450 of the combiner 440. As explained above, the phase shifters 424-1-424-n align the phases of the signals received by the antennas to the desired receiving direction. As a result, the combiner 440 constructively combines the signals corresponding to the desired receiving direction to generate a combined signal. The combiner 440 may output the combined signal to a receiving circuit (not shown) for further processing (e.g., frequency down-conversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or output the combined signal to another combiner (not shown) for a subsequent combining stage.

[0033]

[0049] In the example of Fig. 4, combiner 440 combines signals in the IF domain. This is because frequency down-conversion from RF to IF is performed in mixers 426-1 to 426-n in receiver elements 415-1 to 415-n. As a result, the output signals of receiver elements 415-1 to 415-n (combined by combiner 440) are IF signals. In contrast, combiner 340 in Fig. 3 combines signals in the RF domain. In the example of Fig. 3, frequency down-conversion is performed after signal combination.

[0034]

[0050] The phased array receiver 410 of FIG. 4 may include more hardware than the phased array receiver 310 of FIG. 3. This is because the phased array receiver 410 includes mixers 426-1-426-n in the receiver elements 415-1-415-n to frequency downconvert the RF signals from the antennas to IF signals before signal combining by the combiner 440. In contrast, the combined signal of FIG. 3 may be frequency downconverted from RF to IF using one mixer (not shown in FIG. 3). Although the phased array receiver 410 may require more hardware, combining IF signals in the combiner 440 has the benefit of lowering the operating frequency of the combiner 440 compared to combining RF signals. A lower frequency in the combiner 440 may result in lower signal loss due to parasitics (e.g., parasitic capacitance) in the combiner 440, improving the performance of the combiner 440. Thus, the additional hardware cost associated with including mixers 426-1 through 426-n in receiver elements 415-1 through 415-n may be offset by lower signal loss due to parasitics in combiner 440.

[0035]

[0051] 5 illustrates another example of a phased array receiver 510 for receiving signals from antennas in a phased antenna array (e.g., phased antenna array 205). The phased array receiver 510 includes a plurality of receiver elements 515-1 to 515-n, each of which is coupled to a respective antenna in the phased antenna array via a respective input 512-1 to 512-n. In one example, the number of receiver elements 515-1 to 515-n is equal to the number of antennas 210-1 to 210-k in the phased antenna array 205, where n is equal to k. In another example, the number of receiver elements 515-1 to 515-n is less than the number of antennas 210-1 to 210-k in the phased antenna array 205. In this example, each of the receiver elements 515-1 through 515-n may be coupled to a respective one of n antennas 210-1 through 210-k in the phased antenna array 205.

[0036]

[0052] Each of the receiver elements 515-1 through 515-n includes a respective low noise amplifier (LNA) 520-1 through 520-n, a respective phase shifter 522-1 through 522-n, and a respective mixer 525-1 through 525-n. Each of the LNAs 520-1 through 520-n is configured to amplify a signal from its respective antenna (e.g., a respective one of the antennas 210-1 through 210-k) and may have a variable gain.

[0037]

[0053] Each of the phase shifters 522-1 through 522-n is configured to receive a local oscillator (LO) signal from LO 535 and shift the phase of the received LO signal by a respective phase shift to generate a respective phase-shifted LO signal. Each of the phase shifters 522-1 through 522-n outputs its respective phase-shifted LO signal to its respective mixer 525-1 through 525-n.

[0038]

[0054] Each of the mixers 525-1 to 525-n is configured to mix the signal from its respective LNA 520-1 to 520-n with the phase-shifted LO signal from its respective phase shifter 522-1 to 522-n to generate a frequency downconverted and phase-shifted version of the signal from its respective LNA 520-1 to 520-n. The frequency downconversion may be from a radio frequency (RF) to an intermediate frequency (IF). In this case, the signal received by the receiver elements 515-1 to 515-n is an RF signal, and the output signal of the mixers 525-1 to 525-n is an IF signal. Thus, in this example, the frequency downconversion and phase shifting are performed in the receiver elements 515-1 to 515-n.

[0039]

[0055] In some aspects, the phase shift controller 555 sets the phase shift of the phase shifters 522-1-522-n according to a desired receiving direction (e.g., a direction toward a transmitting device). In this regard, the phase shift controller 555 may set the phase shift of the phase shifters 522-1-522-n such that the output signals of the mixers 525-1-525-n corresponding to the desired receiving directions are approximately in phase. This allows the signals corresponding to the desired receiving directions to be constructively combined, as described further below. For ease of illustration, the individual connections between the phase shift controller 555 and the phase shifters 522-1-522-n are not explicitly shown in FIG. 5.

[0040]

[0056] The phased array receiver 510 also includes a plurality of transmission lines 530-1 through 530-n and a combiner 540. Each of the transmission lines 530-1 through 530-n is coupled between a respective one of the outputs 527-1 through 527-n of the receiver elements 515-1 through 515-n and the combiner 540. The receiver elements 515-1 through 515-n may be spaced apart from one another by the transmission lines 530-1 through 530-n, which route output signals of the receiver elements 515-1 through 515-n to the combiner 540.

[0041]

[0057] The combiner 540 receives the output signals of the receiver elements 515-1 to 515-n via their respective transmission lines 530-1 to 530-n, combines the output signals into a combined signal, and outputs the combined signal at an output 550 of the combiner 540. As explained above, the output signals of the mixers 525-1 to 525-n corresponding to the desired receiving directions are nearly in phase. As a result, the combiner 540 constructively combines the signals corresponding to the desired receiving directions to generate a combined signal. The combiner 540 may output the combined signal to a receiving circuit (not shown) for further processing (e.g., frequency down-conversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or may output the combined signal to another combiner (not shown) for a subsequent combining stage.

[0042]

[0058] FIG. 6 illustrates an example of a dual band phased array receiver 605 according to some aspects of the disclosure. The dual band phased array receiver 605 includes a low band (LB) receiver 610 and a high band (HB) receiver 640. The LB receiver 610 is used to receive signals from antennas of the phased antenna array at LB, and the HB receiver 640 is used to receive signals from antennas of the phased antenna array at HB. In one example, the LB may be in a frequency range of 24-33 GHz, and the HB may be in a frequency range of 37-43 GHz. It should be appreciated that the LB and HB are not limited to the exemplary frequency ranges given above. In general, the LB may be in a first frequency range, and the HB may be in a second frequency range, the first frequency range being lower than the second frequency range. The LB receiver 610 and the HB receiver 640 may receive signals from the same phased antenna array or from different phased antenna arrays.

[0043]

[0059] The LB receiver 610 includes a plurality of receiver elements 615-1 to 615-n, each of which is coupled to a respective antenna of a phased antenna array (e.g., phased antenna array 205) via a respective input 612-1 to 612-n. Each of the receiver elements 615-1 to 615-n includes a respective low noise amplifier (LNA) 620-1 to 620-n and a respective phase shifter 625-1 to 625-n. Each of the LNAs 620-1 to 620-n is configured to amplify a signal from its respective antenna and may have a variable gain. Each of the phase shifters 625-1 to 625-n is configured to shift the phase of its respective signal by a respective phase shift according to a desired receiving direction with respect to the LB, as further described below.

[0044]

[0060] The LB receiver 610 also includes a plurality of transmission lines 630-1 to 630-n and a first combiner 635. Each of the transmission lines 630-1 to 630-n is coupled between one output 618-1 to 618-n of a respective one of the receiver elements 615-1 to 615-n and the first combiner 635.

[0045]

[0061] The first combiner 635 receives the output signals of the receiver elements 615-1 to 615-n via respective transmission lines 630-1 to 630-n, combines the LB output signals into a combined signal, and outputs the LB combined signal at an output 638 of the first combiner 635.

[0046]

[0062] The HB receiver 640 includes multiple receiver elements 645-1 through 645-m, each of which is coupled to a respective antenna of a phased antenna array (e.g., phased antenna array 205) via a respective input 642-1 through 642-m. The phased antenna array coupled to the HB receiver 640 may be the same phased antenna array coupled to the LB receiver 610 or a different phased antenna array. The number of receiver elements 645-1 through 645-m in the HB receiver 640 may be the same as or different from the number of receiver elements 615-1 through 615-n in the LB receiver 610.

[0047]

[0063] Each of the receiver elements 645-1 to 645-m includes a respective low noise amplifier (LNA) 650-1 to 650-m and a respective phase shifter 655-1 to 655-m. Each of the LNAs 650-1 to 650-m is configured to amplify a signal from its respective antenna and may have a variable gain. Each of the phase shifters 655-1 to 655-m is configured to shift the phase of its respective signal by a respective phase shift according to a desired receiving direction with respect to the HB, as described further below.

[0048]

[0064] The HB receiver 640 also includes a plurality of transmission lines 660-1 to 660-m and a second combiner 665. Each of the transmission lines 660-1 to 660-m is coupled between a respective output 648-1 to 648-m of the receiver elements 645-1 to 645-m and the second combiner 665.

[0049]

[0065] The second combiner 665 receives the output signals of the receiver elements 645-1 to 645-m via their respective transmission lines 660-1 to 660-m, combines the HB output signals into a combined signal, and outputs the HB combined signal at an output 668 of the second combiner 665.

[0050]

[0066] The dual-band phased array receiver 605 also includes a third combiner 675. The third combiner 675 is coupled to an output 638 of the first combiner 635 via a transmission line 670-1 and to an output 668 of the second combiner 665 via a transmission line 670-2. The third combiner 675 is configured to combine the LB combined signal from the first combiner 635 and the HB combined signal from the second combiner 665 into a dual-band combined signal and output the dual-band combined signal at an output 678 of the third combiner 675. The third combiner 675 may output the dual-band combined signal to a receiver circuit (not shown) for further processing (e.g., frequency down-conversion, filtering, demodulation, analog-to-digital conversion, baseband processing, etc.) or output the dual-band combined signal to another combiner (not shown) in a subsequent combining stage.

[0051]

[0067] In some embodiments, the phase shifts of the phase shifters 625-1 through 625-n and 655-1 through 655-m are controlled by a phase shift controller 680. For ease of illustration, the individual connections between the phase shift controller 680 and the phase shifters 625-1 through 625-n and 655-1 through 655-m are not explicitly shown in FIG.

[0052]

[0068] The phase shift controller 680 sets the phase shift of the phase shifters 625-1 to 625-n in the LB receiver 610 according to a desired receive direction relative to the LB (e.g., toward a device transmitting at the LB). In this regard, the phase shift controller 680 sets the phase shift of the phase shifters 625-1 to 625-n such that the phase shifters 625-1 to 625-n align the phase of signals corresponding to the desired receive direction relative to the LB. This enables the first combiner 635 to constructively combine signals corresponding to the desired receive direction relative to the LB.

[0053]

[0069] The phase shift controller 680 also sets the phase shift of the phase shifters 655-1-655-m in the HB receiver 640 according to a desired receive direction with respect to HB (e.g., toward a device transmitting at HB). In this regard, the phase shift controller 680 sets the phase shift of the phase shifters 655-1-655-m such that the phase shifters 655-1-655-m align the phase of signals corresponding to the desired receive direction with respect to HB. This enables the second combiner 665 to constructively combine signals corresponding to the desired receive direction with respect to HB. The desired receive direction with respect to HB may be different from the desired direction with respect to LB.

[0054]

[0070] 7 illustrates an example combiner 710 according to some aspects of the present disclosure. The combiner 710 includes a number of inputs 712-1 through 712-n ("In1" through "In nThe combiner 710 has three inputs 712-1 through 712-n (labeled "in") and one output 750 (labeled "out"). The combiner 710 is configured to receive signals at inputs 712-1 through 712-n, combine the received signals into a combined signal, and output the combined signal at output 750. The signals input to the combiner 710 may come from receiver elements (e.g., receiver elements 315-1 through 315-n, 415-1 through 415-n, 515-1 through 515-n, 615-1 through 615-n, or 645-1 through 645-m). In this case, each of the inputs 712-1 through 712-n of the combiner 710 is coupled to a respective one output of the receiver elements. The combiner 710 may output the combined signal to a receiver circuit (not shown) for further processing (e.g., frequency downconversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or may output the combined signal to another combiner (not shown) for a subsequent combining stage.

[0055]

[0071] The combiner 710 includes a plurality of first amplifiers 720-1 to 720-n, a plurality of transmission lines 725-1 to 725-n, a plurality of second amplifiers 730-1 to 730-n, and a load 740. The transmission lines 725-1 to 725-n are used to route signals that are combined by the combiner 710, as described further below.

[0056]

[0072] Each of the first amplifiers 720-1 to 720-n has an input 722-1 to 722-n coupled to a respective one of the inputs 712-1 to 712-n of the combiner 710 and an output 724-1 to 724-n coupled to a first end of a respective one of the transmission lines 725-1 to 725-n. In an example in which each of the inputs 712-1 to 712-n of the combiner 710 is coupled to an output of a respective receiver element, the input of each of the first amplifiers 720-1 to 720-n receives the output signal of the respective receiver element. Each of the first amplifiers 720-1 to 720-n is configured to amplify the signal at its respective input 722-1 to 722-n and output the resulting amplified signal to a respective transmission line 725-1 to 725-n. Each of the first amplifiers 720-1 to 720-n may be implemented by a current amplifier, a transconductance amplifier, a voltage amplifier, or another type of amplifier.

[0057]

[0073] Each of the second amplifiers 730-1 to 730-n has an input 732-1 to 732-n coupled to a second end of a respective one of the transmission lines 725-1 to 725-n and an output 734-1 to 734-n coupled to a combining node 735. As shown in Figure 7, each of the transmission lines 725-1 to 725-n is coupled between an output 724-1 to 724-n of a respective first amplifier 720-1 to 720-n and an input 732-1 to 732-n of a respective second amplifier 730-1 to 730-n to route a signal from the respective first amplifier 720-1 to 720-n to the respective second amplifier 730-1 to 730-n. The transmission lines 725-1 through 725-n may include metal traces on one or more chips (i.e., dies), metal traces on a printed circuit board, cables (e.g., coaxial cables), or any combination thereof. It should be appreciated that although the transmission lines 725-1 through 725-n are shown as straight in FIG. 7, this need not be the case. For example, one or more of the transmission lines 725-1 through 725-n may follow a non-straight path (e.g., depending on the layout of the first amplifiers 720-1 through 720-n and the second amplifiers 730-1 through 730-n).

[0058]

[0074] A load 740 is coupled between the voltage supply rail and the combination node 735 and provides an output load for the second amplifiers 730-1 through 730-n. The load 740 may be implemented by an inductor, a choke, a bias T network, a resonator, or another type of load, as described further below.

[0059]

[0075] Each of the second amplifiers 730-1-730-n may be configured to amplify the signal from its respective transmission line 725-1-725-n and / or act as a buffer amplifier (e.g., to provide high load isolation between the load 740 and the respective transmission line 725-1-725-n). The output signals of the second amplifiers 730-1-730-n are combined at a combining node 735 to generate a combined signal. In one example, the output signals of the second amplifiers 730-1-730-n are currents that are combined into a combined current at the combining node 735. In this example, the combined current flows through the load 740 to generate a voltage that provides the combined signal of the combiner 710. The combined signal is output at an output 750 of the combiner 710. The combiner 710 may output the combined signal to a receiving circuit (not shown) for further processing or to another combiner (not shown) in a subsequent combining stage.

[0060]

[0076] As discussed above, each of the inputs 712-1 through 712-n of the combiner 710 may be coupled to an output of a respective receiver element. In this regard, FIG. 8 illustrates an example of receiver elements 815-1 through 815-n coupled to respective inputs 712-1 through 712-n of the combiner 710. In this example, the receiver elements 815-1 through 815-n may be implemented by the example receiver elements 315-1 through 315-n of FIG. 3, the example receiver elements 415-1 through 415-n of FIG. 4, the example receiver elements 515-1 through 515-n of FIG. 5, the example receiver elements 615-1 through 615-n of FIG. 6, or the example receiver elements 645-1 through 645-m of FIG. 6.

[0061]

[0077] Each of the receiver elements 815-1 to 815-n has a respective input 822-1 to 822-n coupled to a respective antenna 810-1 to 810-n and a respective output 824-1 to 824-n coupled to a respective input 712-1 to 712-n of the combiner 710. The antennas 810-1 to 810-n may be antennas in a phased antenna array (e.g., two or more of the antennas 210-1 to 210-k in the phased antenna array 205). Each of the receiver elements 815-1 to 815-n is configured to receive a respective signal (e.g., a respective RF signal) from a respective antenna 810-1 to 810-n via a respective input 822-1 to 822-n and process the respective signal. For example, each of receiver elements 815-1 through 815-n may shift the phase of a respective signal by a respective phase shift to set a receive direction of the phased antenna array, as described above. In this example, each of receiver elements 815-1 through 815-n may include a respective phase shifter (e.g., a respective one of phase shifters 325-1 through 325-n, 424-1 through 424-n, 522-1 through 522-n, 625-1 through 625-n, or 655-1 through 655-m) to shift the phase of the respective signal. The phase settings of the phase shifters of receiver elements 815-1 through 815-n may be the same or different.

[0062]

[0078] Each of receiver elements 815-1 through 815-n may also be configured to amplify a respective signal. In this example, each of receiver elements 815-1 through 815-n may include a respective LNA (e.g., a respective one of LNAs 320-1 through 320-n, 420-1 through 420-n, 520-1 through 520-n, 620-1 through 620-n, or 650-1 through 650-m) for amplifying the respective signal.

[0063]

[0079] Each of receiver elements 815-1 through 815-n may also be configured to frequency downconvert (e.g., from RF to IF) its respective signal. In this example, each of receiver elements 815-1 through 815-n may include a respective mixer (e.g., a respective one of mixers 426-1 through 426-n or 525-1 through 525-n) for frequency downconverting its respective signal.

[0064]

[0080] Each of receiver elements 815-1 through 815-n outputs a respective processed signal (e.g., an amplified, phase shifted, and / or frequency downconverted signal) at a respective output 824-1 through 824-n. The processed signals output at outputs 824-1 through 824-n of receiver elements 815-1 through 815-n provide output signals for receiver elements 815-1 through 815-n.

[0065]

[0081] 7, combines the received output signals into a combined signal, and outputs the combined signal at output 750. The combiner 710 may output the combined signal to a receiver circuit (not shown) for further processing (e.g., frequency downconversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or may output the combined signal to another combiner (not shown) for a subsequent combining stage.

[0066]

[0082] In an example in which receiver elements 815-1 to 815-n are implemented by exemplary receiver elements 315-1 to 315-n of FIG. 3, input sections 822-1 to 822-n correspond to input sections 312-1 to 312-n of FIG. 3, and output sections 824-1 to 824-n correspond to output sections 327-1 to 327-n of FIG. 3.

[0067]

[0083] In an example in which receiver elements 815-1 to 815-n are implemented by exemplary receiver elements 415-1 to 415-n of FIG. 4, input sections 822-1 to 822-n correspond to input sections 412-1 to 412-n of FIG. 4, and output sections 824-1 to 824-n correspond to output sections 428-1 to 428-n of FIG. 4.

[0068]

[0084] In an example in which receiver elements 815-1 to 815-n are implemented by exemplary receiver elements 515-1 to 515-n of FIG. 5, input sections 822-1 to 822-n correspond to input sections 512-1 to 512-n of FIG. 5, and output sections 824-1 to 824-n correspond to output sections 527-1 to 527-n of FIG. 5.

[0069]

[0085] In an example in which receiver elements 815-1 to 815-n are implemented by exemplary receiver elements 615-1 to 615-n of FIG. 6, input sections 822-1 to 822-n correspond to input sections 612-1 to 612-n of FIG. 6, and output sections 824-1 to 824-n correspond to output sections 618-1 to 618-n of FIG. 6.

[0070]

[0086] In an example where receiver elements 815-1 through 815-n are implemented by example receiver elements 645-1 through 645-m of Figure 6, inputs 822-1 through 822-n correspond to inputs 642-1 through 642-m of Figure 6, and outputs 824-1 through 824-n correspond to outputs 648-1 through 648-m of Figure 6. In this example, "n" in Figure 8 (indicating the number of receiver elements 815-1 through 815-n) is not necessarily equal to "n" in Figure 6 (indicating the number of receiver elements 615-1 through 615-n in LB receiver 610).

[0071]

[0087] It should be appreciated that the combiner 710 is not limited to combining signals from the receiver elements. For example, the combiner 710 may also be used to combine signals from two or more combiners in a previous combining stage. In one example, the combiner 710 may be used to combine the LB combined signal and the HB combined signal of FIG. 6 into a dual-band combined signal. In this example, a first one of the inputs 712-1 to 712-n of the combiner 710 is coupled to the output 638 of the first combiner 635, and a second one of the inputs 712-1 to 712-n of the combiner 710 is coupled to the output 668 of the second combiner 665. The combiner 710 combines the output signals of the first and second combiners 635 and 668 into a dual-band combined signal and outputs the dual-band combined signal at an output 750 (corresponding to the output 678 of the third combiner 675 of FIG. 6).

[0072]

[0088] In some aspects, each of the first amplifiers 720-1-720-n is configured to drive a respective transmission line 725-1-725-n with a respective output current. In one example, each of the first amplifiers 720-1-720-n is implemented with a current amplifier configured to receive a respective input current (e.g., from an output of each of the receiver elements 815-1-815-n), amplify the respective input current to generate a respective output current, and drive a respective transmission line with the respective output current. In another example, each of the first amplifiers 720-1-720-n is implemented with a transconductance amplifier configured to receive a respective input voltage (e.g., from an output of each of the receiver elements 815-1-815-n), convert the respective input voltage to a respective output current, and drive a respective transmission line with the respective output current.

[0073]

[0089] Driving the transmission lines 725-1 through 725-n with currents may improve signal integrity compared to driving the transmission lines 725-1 through 725-n with voltages, as described further below.

[0074]

[0090] In one example, the receiver elements 815-1 through 815-n may be widely spaced apart from one another. For example, each of the receiver elements 815-1 through 815-n may be located near its respective antenna 810-1 through 810-n in a phased antenna array (e.g., phased antenna array 205). In this example, the antennas 810-1 through 810-n in the phased antenna array may be widely spaced apart, causing the receiver elements 815-1 through 815-n to also be widely spaced apart.

[0075]

[0091] In the above example, each of the first amplifiers 720-1-720-n may be located near its respective receiver element 815-1-815-n. This may be done to reduce signal loss between the first amplifiers 720-1-720-n and the respective receiver element 815-1-815-n. In this example, since the receiver elements 815-1-815-n are widely spaced apart, the first amplifiers 720-1-720-n may also be widely spaced apart. The second amplifiers 730-1-730-n may be located side-by-side near the combining node 735 to reduce signal loss between the second amplifiers 730-1-730-n and the combining node 735. As a result, the first amplifiers 720-1-720-n may be widely spaced apart from the second amplifiers 730-1-730-n. Thus, in this example, the lengths of the transmission lines 725-1 to 725-n may need to be relatively long to route signals from the outputs 724-1 to 724-n of the first amplifiers 720-1 to 720-n to the inputs 732-1 to 732-n of the second amplifiers 730-1 to 730-n.

[0076]

[0092] In the above example, driving the transmission lines 725-1-725-n with a voltage may result in a large amount of signal loss between the first amplifiers 720-1-720-n and the second amplifiers 730-1-730-n. This is because the resistance of each transmission line 725-1-725-n increases with increasing length, which increases the IR voltage drop across each transmission line 725-1-725-n. Thus, the relatively long length of the transmission lines 725-1-725-n in this example results in an increased IR voltage drop across the transmission lines 725-1-725-n. The increased IR voltage drop across the transmission lines 725-1-725-n may significantly reduce the voltage reaching the inputs 732-1-732-n of the second amplifiers 730-1-730-n.

[0077]

[0093] Driving the transmission lines 725-1-725-n with currents may significantly reduce signal loss between the first amplifiers 720-1-720-n and the second amplifiers 730-1-730-n. This is because the current flowing through the transmission lines 725-1-725-n is not reduced by the IR voltage drop across the transmission lines 725-1-725-n. Thus, unlike voltages, currents do not suffer significant loss due to IR voltage drops across the transmission lines 725-1-725-n. The reduced signal loss facilitates signal routing over long distances (e.g., when the first amplifiers 720-1-720-n are spread out and the second amplifiers 730-1-730-n are located close to each other near the combined node 735).

[0078]

[0094] In some aspects, each of the first amplifiers 720-1-720-n has a high output impedance so that the output of each of the first amplifiers 720-1-720-n approaches an ideal current source (having infinite output impedance). This helps ensure that a majority of the output current generated by each of the first amplifiers 720-1-720-n flows through the respective transmission line 725-1-725-n. In these aspects, each of the first amplifiers 720-1-720-n may be implemented by a current amplifier or a transconductance amplifier.

[0079]

[0095] Each of the second amplifiers 730-1 to 730-n may have a low input impedance, which helps ensure that the majority of the current flowing through each of the transmission lines 725-1 to 725-n flows through one input 732-1 to 732-n of each of the second amplifiers 730-1 to 730-n.

[0080]

[0096] Thus, the first amplifiers 720-1-720-n may have a high output impedance and the second amplifiers 730-1-730-m may have a low input impedance. This helps ensure that a majority of the output current generated by the first amplifiers 720-1-720-n flows through the inputs 732-1-723-n of the second amplifiers 730-1-730-m for high efficiency. In one example, the output impedance of each of the first amplifiers 720-1-720-n is at least 10 times greater than the input impedance of each one of the second amplifiers 730-1-730-n.

[0081]

[0097] As described above, each of the first amplifiers 720-1 to 720-n may be implemented by a current amplifier. In this regard, FIG. 9 illustrates an example implementation of a current amplifier 905 according to some aspects of the present disclosure. Each of the first amplifiers 720-1 to 720-n may be implemented by the current amplifier 905 shown in FIG. 9 (i.e., each of the first amplifiers 720-1 to 720-n may be a separate instance of the current amplifier 905 shown in FIG. 9).

[0082]

[0098] Current amplifier 905 has inputs 922 coupled to respective ones of inputs 712-1 to 712-n of combiner 710 (shown in FIG. 7) and outputs 924 coupled to respective ones of transmission lines 725-1 to 725-n (shown in FIG. 7). Current amplifier 905 includes a current mirror 910, a current source 915, and an alternating current (AC) coupling capacitor 955. Current mirror 910 has an input 945 and an output 950. AC coupling capacitor 955 is coupled between input 922 of current amplifier 905 and input 945 of current mirror 910. Output 950 of current mirror 910 is coupled to output 924 of current amplifier 905.

[0083]

[0099] In operation, AC coupling capacitor 955 AC couples an input current at input 922 of current amplifier 905 to input 945 of current mirror 910. Current mirror 910 amplifies the input current to produce an output current at output 924 of current amplifier 905. Because output 924 of current amplifier 905 is coupled to a respective one of transmission lines 725-1 through 725-n (shown in FIG. 7), current amplifier 905 drives a respective one of transmission lines 725-1 through 725-n with its output current.

[0084]

[0100] 9, current mirror 910 includes an input transistor 920 (e.g., an NFET) and an output transistor 925 (e.g., an NFET). The drain of the input transistor 920 is coupled to an input 945 of the current mirror 910, the source of the input transistor 920 is coupled to ground, and the gate of the input transistor 920 is connected to the drain of the input transistor 920. The drain of the output transistor 925 is coupled to an output 950 of the current mirror 910, the gate of the output transistor 925 is coupled to the gate of the input transistor 920, and the source of the output transistor 925 is coupled to ground. In operation, current mirror 910 produces an output current at the output 950 of the current mirror 910 that is approximately equal to the current at the input 945 of the current mirror 910 multiplied by the current mirror ratio. The current mirror ratio of current mirror 910 is given by the following equation:

[0085]

number

[0086] where current_mirror_ratio is the current mirror ratio of the current mirror 910 and Channel_Width out is the channel width of the output transistor 925, and Gate_Length out is the gate length of the output transistor 925, and Channel_Width in is the channel width of the input transistor 920, and Gate_Length in is the gate length of input transistor 920. In this example, the current gain of current amplifier 905 is approximately equal to the current mirror ratio of current mirror 910. Thus, in this example, the current gain of current amplifier 905 is given by:

[0087]

number

[0088] where current_gain is the current gain of current amplifier 905. If the gate length of output transistor 925 is approximately equal to the gate length of input transistor 920, then equation 5 may be simplified to:

[0089]

number

[0090]

[0101] The current amplifier 905 also includes a current source 915 coupled to an input 945 of the current mirror 910. The current source 915 may be a direct current (DC) current source. The current source 915 is configured to provide a DC bias current (labeled "Ibias") to the input 945 of the current mirror 910 to bias the current mirror 910. The current mirror 910 generates a bias current at an output 950 of the current mirror 910 that is approximately equal to the bias current at the input 945 of the current mirror 910 multiplied by a current mirror ratio. The bias current at the output 950 provides a current bias to each one of the second amplifiers 730-1 through 730-n (shown in FIG. 7). The current source 915 may be implemented by a transistor (e.g., a PFET) whose gate is biased based on a reference current to generate the bias current Ibias. Note that AC coupling capacitor 955 blocks the DC bias current Ibias from input 922 of current amplifier 905. AC coupling capacitor 955 also blocks any DC current at input 922 from entering current amplifier 905. In this sense, AC coupling capacitor 955 is sometimes referred to as a DC blocking capacitor.

[0091]

[0102] Thus, current amplifier 905 is configured to receive an input current at an input 922 of current amplifier 905 and amplify the input current by a current gain of current amplifier 905 to generate an output current at output 950 of current amplifier 905. In an example where input 922 is coupled to an output of each of receiver elements 815-1 through 815-n, the input current may come from an output of each of receiver elements 815-1 through 815-n. If each of receiver elements 815-1 through 815-n outputs a voltage, the output of each of receiver elements 815-1 through 815-n may be coupled to input 922 of current amplifier 905 via a transconductance amplifier (not shown) configured to convert the voltage at the output of the respective receiver element to an input current.

[0092]

[0103] In the example of Figure 9, the input 945 of the current mirror 910 has a low input impedance because the input transistor 920 is diode connected, creating a low input impedance approximately equal to 1 / gm, where gm is the transconductance of the input transistor 920. The low input impedance of the current mirror 910 helps ensure that the current input to the current amplifier 905 flows through the input 945 of the current mirror 910. Note that the current source 915 has a much higher impedance than the input 945 of the current mirror 910. As a result, very little of the current input to the current amplifier 905 flows in the current source 915.

[0093]

[0104] 9, the output 950 of the current mirror 910 has a high output impedance because of the high impedance looking into the drain of the output transistor 925. The high output impedance allows the current amplifier 905 to efficiently drive the respective transmission line with the output current.

[0094]

[0105] In some embodiments, the channel width of the input transistor 920 is electronically adjustable and the channel width of the output transistor 925 is electronically adjustable. This is indicated by the arrows through the input transistor 920 and the output transistor 925 in FIG. 9. In these embodiments, the current gain of the current amplifier 905 may be adjusted by adjusting the channel width of the input transistor 920 and / or adjusting the channel width of the output transistor 925 to achieve a desired current gain (e.g., based on equation (5)).

[0095]

[0106] 10 illustrates an example implementation of input transistor 920 and output transistor 925, where the channel width of input transistor 920 is electronically adjustable and the channel width of output transistor 925 is electronically adjustable. In this example, the channel width of input transistor 920 is adjusted according to a respective multi-bit control signal Cm inand the channel width of the output transistor 925 is controlled by a respective multi-bit control signal Cm out The control signal Cm in and Cm out is generated and output by control circuitry 1070, as described further below.

[0096]

[0107] In this example, the input transistor 920 includes multiple parallel branches 1010-1 to 1010-m, each of which is coupled between an input 945 of the current mirror 910 and ground. Each of the branches 1010-1 to 1010-m includes a respective transistor 1015-1 to 1015-m (e.g., an NFET) and a respective switch 1020-1 to 1020-m coupled in series. The gates of the transistors 1015-1 to 1015-m are coupled to the input 945 of the current mirror 910. It should be noted that "m" in FIG. 10 (indicating the number of branches 1010-1 to 1010-m in the input transistor 920) is not necessarily equal to "m" in FIG. 6 (indicating the number of receiver elements 645-1 to 645-m in the HB receiver 640).

[0097]

[0108] In this example, each multi-bit control signal Cm in is m control bits Cm in <1> ~Cm in <m>where each of the control bits corresponds to a respective one of the branches 1010-1 to 1010-m. Each of the control bits controls whether a switch 1020-1 to 1020-m of a respective branch 1010-1 to 1010-m is turned on (i.e., closed) or off (i.e., open). When a switch 1020-1 to 1020-m is turned on (i.e., closed), the respective branch 1010-1 to 1010-m is enabled, in which case the channel width of the respective transistor 1015-1 to 1015-m contributes to the channel width of the input transistor 920. When a switch 1020-1 to 1020-m is turned off (i.e., open), the respective branch 1010-1 to 1010-m is disabled, in which case the channel width of the respective transistor 1015-1 to 1015-m does not contribute to the channel width of the input transistor 920. In this example, the channel width of the input transistor 920 is the sum of the channel widths of the transistors 1015-1 to 1015-m in the enabled branches 1010-1 to 1010-m. Thus, in this example, the multi-bit control signal Cm in controls the number of enabled branches 1010-1 to 1010-m, thereby controlling the channel width of the input transistor 920. The more enabled branches 1010-1 to 1010-m, the wider the channel width.

[0098]

[0109] The output transistor 925 includes a plurality of parallel branches 1050-1 through 1050-p, each of which is coupled between the output 950 of the current mirror 910 and ground. Each of the branches 1050-1 through 1050-p includes a respective transistor 1055-1 through 1055-p (e.g., an NFET) and a respective switch 1060-1 through 1060-p coupled in series. The gates of the transistors 1055-1 through 1055-p are coupled to the gates of the transistors 1015-1 through 1015-m.

[0099]

[0110] In this example, each multi-bit control signal Cm out is p control bits Cm out <1>~Cm out where each of the control bits corresponds to a respective one of the branches 1050-1 to 1050-p. Each of the control bits controls whether a switch 1060-1 to 1060-p of a respective branch 1050-1 to 1050-p is turned on (i.e., closed) or off (i.e., open). When a switch 1060-1 to 1060-p is turned on (i.e., closed), the respective branch 1050-1 to 1050-p is enabled, in which case the channel width of the respective transistor 1055-1 to 1055-p contributes to the channel width of the output transistor 925. When a switch 1060-1 to 1060-p is turned off (i.e., open), the respective branch 1050-1 to 1050-p is disabled, in which case the channel width of the respective transistor 1055-1 to 1055-p does not contribute to the channel width of the output transistor 925. In this example, the channel width of the output transistor 925 is the sum of the channel widths of the transistors 1055-1 to 1055-p in the enabled branches 1050-1 to 1050-p. Thus, in this example, the multi-bit control signal Cm out controls the number of enabled branches 1050-1 to 1050-p, thereby controlling the channel width of the output transistor 925. The more enabled branches 1050-1 to 1050-p, the wider the channel width.

[0100]

[0111] Therefore, in this example, the control circuit 1070 outputs the control signal Cm in is used to set the channel width of the input transistor 920, and the control signal Cm out can be used to set the channel width of output transistor 925. This allows control circuit 1070 to set the current mirror ratio of current mirror 910 (e.g., based on equation (4)) and therefore the current gain of current amplifier 905 (e.g., based on equation (5)). Note that for ease of illustration, the individual connections between control circuit 1070 and switches 1020-1 through 1020-m and 1060-1 through 1060-p are not shown in FIG.

[0101]

[0112] In one example, the control circuit 1070 sets the current gain of the current amplifier 905 according to a current gain value stored in the register 1080. In this example, the current gain value indicates the current gain of the current amplifier 905. To set the current gain, the control circuit 1070 sets the current mirror ratio of the current mirror 910 to a current mirror ratio that corresponds to the current gain indicated by the current gain value (e.g., based on equation (5)). The control circuit 1070 controls the control signal Cm in 920 and sets the channel width of the input transistor 920 accordingly (e.g., based on equation (4)) out 1080. The current gain of current amplifier 905 may be programmed by programming (e.g., writing) a current gain value stored in register 1080.

[0102]

[0113] 10, both the input transistor 920 and the output transistor 925 have adjustable channel widths. However, it should be appreciated that the present disclosure is not limited to this example. For example, the channel width of the input transistor 920 may be fixed, while the channel width of the output transistor 925 is adjustable. In this example, the control circuit 1070 controls the control signal Cm out The current mirror ratio of the current mirror 910 can be adjusted (and therefore the current gain of the current amplifier 905) by adjusting the channel width of the output transistor 925 using the control signal Cm in By adjusting the channel width of the input transistor 920 using the MOSFET 914, the current mirror ratio of the current mirror 910 (and therefore the current gain of the current amplifier 905) can be adjusted.

[0103]

[0114] FIG. 11 illustrates an example in which each of the first amplifiers 720-1 to 720-n is implemented by the example current amplifier 905 illustrated in FIG. 10 (i.e., each of the first amplifiers 720-1 to 720-n is a separate example of the current amplifier 905 illustrated in FIG. 10). For ease of illustration, FIG. 11 illustrates details of only one of the first amplifiers 720-1 to 720-n (i.e., the first amplifier 720-1). In this example, each of the first amplifiers 720-1 to 720-n receives a respective input current from a respective input 712-1 to 712-n of the combiner 710 and amplifies the respective input current by a respective current gain to generate a respective output current. Each of the first amplifiers 720-1 to 720-n drives a respective transmission line 725-1 to 725-n with a respective output current.

[0104]

[0115] In one example, the current gains of the first amplifiers 720-1 through 720-n may be independently controlled. In this example, the control circuit 1150 may independently set the current gain of each of the first amplifiers 720-1 through 720-n. For each of the first amplifiers 720-1 through 720-n, the control circuit 1150 may generate a respective control signal ("Cm in_1 " ~ "Cm in_n ") and the respective control signals ("Cm out_1 " ~ "Cm out_n For each of the first amplifiers 720-1 to 720-n, the control circuit 1070 outputs a control signal Cm in_1 ~Cm in_n and the control signal Cm out_1 ~Cm out_n For ease of illustration, the individual connections between control circuit 1150 and first amplifiers 720-1 to 720-n are not shown in FIG.

[0105]

[0116] In this example, register 1160 may store a plurality of current gain values, where each of the current gain values ​​indicates a current gain of a respective one of first amplifiers 720-1 through 720-n. As used herein, a "register" may be implemented by a plurality of registers for storing a plurality of values. Control circuit 1150 sets the current gain of each of first amplifiers 720-1 through 720-n to the current gain indicated by the respective current gain value in register 1160. More specifically, for each of first amplifiers 720-1 through 720-n, control circuit 1150 controls control signal Cm to set the current mirror ratio of the respective current mirror to the current mirror ratio corresponding to the current gain indicated by the respective current gain value (e.g., based on equation (5)). in_1 ~Cm in_n to set the channel width of each input transistor, and the control signal Cm out_1 ~Cm out_n Each of the first amplifiers 720-1 through 720-n may be programmed by programming (e.g., writing) a current gain value stored in a register 1160.

[0106]

[0117] Thus, the first amplifiers 720-1 to 720-n may be implemented by current amplifiers with programmable current gain. The current gains of the first amplifiers 720-1 to 720-n may be programmed, for example, so that the amplitudes of the currents at the inputs 732-1 to 732-n of the second amplifiers 730-1 to 730-n are approximately the same. This helps to ensure that the signals combined at the combining node 735 have approximately the same amplitude, which may help to narrow the beam pattern of the phased array receiver. A narrower beam pattern increases the directivity of the phased array receiver.

[0107]

[0118] In one example, the length of the transmission lines 725-1-725-n may vary depending on the layout of the first amplifiers 720-1-720-n and the second amplifiers 730-1-730-n. In this example, the length of one of the transmission lines 725-1-725-n may be at least 20 percent longer than the length of another one of the transmission lines 725-1-725-n. Variations in the length of the transmission lines 725-1-725-n may cause variations in signal loss in the transmission lines 725-1-725-n. Variations in signal loss in the transmission lines 725-1-725-n may lead to variations in the amplitude of the current at the inputs 732-1-732-n of the second amplifiers 730-1-730-n. To correct for this, the current gain of the first amplifiers 720-1-720-n may be programmed to compensate for variations in signal loss in the transmission lines 725-1-725-n. For example, if a transmission line coupled to a first one of the first amplifiers 720-1-720-n experiences higher signal loss than a transmission line coupled to a second one of the first amplifiers 720-1-720-n, the current gain of the first one of the first amplifiers 720-1-720-n may be programmed to be higher than the current gain of the second one of the first amplifiers 720-1-720-n to compensate for the higher signal loss. In this example, the register 1150 may store different current gain values ​​for the first one of the first amplifiers 720-1-720-n and the second one of the first amplifiers 720-1-720-n. It should be appreciated that the current gain of first amplifiers 720-1 through 720-n may also be programmed based on other factors, examples of which are described below.

[0108]

[0119] In the above example, the variation in length of the transmission lines 725-1-725-n may also cause a phase offset between the currents at the inputs 732-1-732-n of the second amplifiers 730-1-730-n. To correct for this, the phase shift of the phase shifter (e.g., 325-1-325-n, 424-1-424-n, 522-1-522-n, 625-1-625-n, or 655-1-655-m) in the receiver elements 815-1-815-n may include a phase shift component that compensates for the phase offset due to the variation in length of the transmission lines 725-1-725-n. Thus, in this example, the phase shift of each phase shifter may include a phase shift component to set the receive direction of the phased antenna array (e.g., based on equation (3)) and a phase shift component to compensate for phase offsets due to length variations of the transmission lines 725-1 through 725-n. This helps to ensure that the currents at the inputs 732-1 through 732-n of the second amplifiers 730-1 through 730-n are in phase for constructive combining at the combining node 735.

[0109]

[0120] FIG. 12 illustrates that each of the second amplifiers 730-1 to 730-n has a drain (labeled “D”) coupled to a combination node 735 and a respective bias voltage Vg1 to Vg n 12 shows an example implemented by a common gate amplifier including respective transistors 1230-1 to 1230-n having a gate (labeled "G") biased by a bias current (V) and a source (labeled "S") coupled to respective transmission lines 725-1 to 725-n. In this example, the output 734-1 to 734-n of each of the second amplifiers 730-1 to 730-n is located at the drain of the respective transistor 1230-1 to 1230-n, and the input 732-1 to 732-n of each of the second amplifiers 730-1 to 730-n is located at the source of the respective transistor 1230-1 to 1230-n. In the example of FIG. 12, each of the transistors 1230-1 to 1230-n is an n-type field effect transistor (NFET). However, it should be appreciated that transistors 1230-1 through 1230-n may be implemented with other types of transistors (eg, p-type field effect transistors (PFETs)).

[0110]

[0121] The advantage of implementing each of the second amplifiers 730-1 to 730-n with a common gate amplifier is that the common gate amplifier can be small. This allows the second amplifiers 730-1 to 730-n to be located close to each other. The close proximity of the second amplifiers 730-1 to 730-n reduces signal loss between the outputs 734-1 to 734-n of the second amplifiers 730-1 to 730-n and the combining node 735, improving the quality of the signal combining at the combining node 735.

[0111]

[0122] 12, each of the second amplifiers 730-1 through 730-n has a low input impedance approximately equal to 1 / gm, where gm is the transconductance of the respective transistor 1230-1 through 1230-n. The low input impedance of each of the second amplifiers 730-1 through 730-n may be approximately matched to the characteristic impedance (e.g., 40-50 ohms) of the respective transmission line 725-1 through 725-n to provide a good impedance match between the input of the second amplifier and the respective transmission line 725-1 through 725-n, as described further below.

[0112]

[0123] In the example of FIG. 12, the input impedance of each of the second amplifiers 730-1 to 730-n is determined by the gate bias voltages Vg1 to Vg n (That is, the gate bias voltages Vg1 to Vg n For example, the input impedance of each of the second amplifiers 730-1 to 730-n is a function of the gate bias voltages Vg1 to Vg n This is because the input impedance of each of the second amplifiers 730-1 to 730-n is approximately equal to 1 / gm of the respective transistors 1230-1 to 1230-n, and the gm of each of the transistors 1230-1 to 1230-n is approximately inversely proportional to the gate bias voltages Vg1 to Vg n Therefore, the input impedance of each of the second amplifiers 730-1 to 730-n can be adjusted (i.e., tuned) by adjusting the respective gate bias voltages, as described further below.

[0113]

[0124] In one example, the gate bias voltages Vg1 to Vg n may be set such that the input impedance of the second amplifiers approximately matches the characteristic impedance of each transmission line 725-1 to 725-n. Good impedance matching between the inputs of each of the second amplifiers 730-1 to 730-n and the respective transmission lines increases the power transfer between the transmission lines 725-1 to 725-n and the inputs 732-1 to 732-n of the second amplifiers 730-1 to 730-n.

[0114]

[0125] In one example, the gate bias circuit 1260 controls the gate bias voltages Vg1 to Vg n For ease of explanation, the individual connections between the gate bias circuit 1260 and the second amplifiers 730-1 to 730-n are not explicitly shown in FIG.

[0115]

[0126] In this example, a plurality of gate bias voltage values ​​are stored in a register 1250 coupled to a gate bias circuit 1260, where each of the gate bias voltage values ​​represents a gate bias voltage of a respective one of the second amplifiers 730-1 to 730-n (i.e., Vg1 to Vg n 1250, one for each of the second amplifiers 730-1 to 730-n). The "register" described above may be implemented by multiple registers for storing multiple values. In this example, the gate bias circuit 1260 retrieves the gate bias voltage value of each of the second amplifiers 730-1 to 730-n from the register 1250 and sets the gate bias voltage of each of the second amplifiers 730-1 to 730-n based on the respective gate bias voltage values. The gate bias circuit 1260 may independently set the gate bias voltage of each of the second amplifiers 730-1 to 730-n based on the respective gate bias voltage values. The gate bias voltage of each of the second amplifiers 730-1 to 730-n may be programmed by programming (e.g., writing) the corresponding gate bias voltage value stored in the register 1250.

[0116]

[0127] In the above example, each of the gate bias voltage values ​​in the register 1250 may indicate a gate bias voltage that approximately matches the input impedance of each one of the second amplifiers 730-1-730-n to the characteristic impedance of the respective transmission line 725-1-725-n for good impedance matching. The gate bias voltage that provides good impedance matching between the inputs 732-1-732-n of the second amplifiers 730-1-730-n and the transmission lines 725-1-725-n may be determined based on a computer simulation of the combiner 710 and / or tests performed on the combiner 710.

[0117]

[0128] In some aspects, one or more of the second amplifiers 730-1-730-n each have an electronically adjustable channel width. An example of this is shown in FIG. 13, where an arrow through each of the second amplifiers 730-1-730-n indicates that the channel width of the second amplifiers 730-1-730-n is adjustable. In the example shown in FIG. 13, all of the second amplifiers 730-1-730-n have an adjustable channel width, but it should be appreciated that this is not required. In this example, the input impedance of each of the second amplifiers 730-1-730-n is a function of the respective channel width. The larger the channel width, the larger the transconductance gm (and thus the smaller the input impedance, which is approximately equal to 1 / gm). Thus, the input impedance of each of the second amplifiers 730-1-730-n may be adjusted (i.e., tuned) by adjusting the respective channel width. In one example, the channel width of each of the second amplifiers 730-1 to 730-n may be set such that the input impedance of the second amplifier approximately matches the characteristic impedance of the respective transmission line 725-1 to 725-n, as described further below.

[0118]

[0129] In one example, the channel width of each of the second amplifiers 730-1 to 730-n is determined by the respective control signals Cw1 to Cw n In this example, the control circuit 1360 is controlled by the control signals Cw1 to Cw n and outputs the control signals Cw1 to Cw n 13 to set the channel width of each of the second amplifiers 730-1 to 730-n. For ease of illustration, the individual connections between the control circuit 1360 and the second amplifiers 730-1 to 730-n are not explicitly shown in FIG.

[0119]

[0130] In this example, a plurality of channel width values ​​are stored in a register 1350 coupled to the control circuitry 1360, each of the channel width values ​​indicating a channel width of a respective one of the second amplifiers 730-1-730-n. The "register" described above may be implemented by a plurality of registers for storing a plurality of values. In this example, the control circuitry 1360 retrieves the channel width value of each of the second amplifiers 730-1-730-n from the register 1350 and sets the channel width of each of the second amplifiers 730-1-730-n based on the respective channel width value using the respective channel width control signal. The control circuitry 1360 may independently set the channel width of each of the second amplifiers 730-1-730-n based on the respective channel width value. The channel width of each of the second amplifiers 730-1-730-n may be programmed by programming (e.g., writing) the corresponding channel width value stored in the register 1350.

[0120]

[0131] In the above example, each of the channel width values ​​in the register 1350 may indicate a channel width that approximately matches the input impedance of one of the second amplifiers 730-1-730-n to the characteristic impedance of the respective transmission line 725-1-725-n for good impedance matching. The channel width that provides good impedance matching between the inputs 732-1-732-n of the second amplifiers 730-1-730-n and the transmission lines 725-1-725-n may be determined based on a computer simulation of the combiner 710 and / or tests performed on the combiner 710.

[0121]

[0132] FIG. 14A illustrates an example implementation of a common gate amplifier 1430, which is configured to receive respective control signals (e.g., control signals Cw1-Cw n Each of the second amplifiers 730-1 through 730-n shown in FIG. 13 may be implemented by the common gate amplifier 1430 shown in FIG. 14A (i.e., each of the second amplifiers 730-1 through 730-n may be a separate instance of the common gate amplifier 1430 shown in FIG. 14A).

[0122]

[0133] In the example shown in FIG. 14A, the common gate amplifier 1430 includes a plurality of parallel branches 1410-1 through 1410-k, each of which is coupled between an output 1434 and an input 1432 of the common gate amplifier 1430. The output 1434 is coupled to a combination node 735 (shown in FIG. 13), and the input 1432 is coupled to a respective transmission line 725-1 through 725-n (shown in FIG. 13). Each of the branches 1410-1 through 1410-k includes a respective transistor 1415-1 through 1415-k (e.g., an NFET) and a respective switch 1420-1 through 1420-k coupled in series. The gates of the transistors 1415-1 through 1415-k are coupled to a gate bias voltage Vg (e.g., the gate bias voltages Vg1 through Vg2 of FIG. 13). n 2 (respective ones of the branches 1410-1 through 1410-k). Note that "k" in FIG. 14A (indicating the number of branches 1410-1 through 1410-k) is not necessarily equal to "k" in FIG. 2 (indicating the number of antennas 210-1 through 210-k in phased antenna array 205).

[0123]

[0134] In this example, each control signal is represented by k control bits Cw <1> ~Cw <k>, where each of the control bits corresponds to a respective one of the branches 1410-1 through 1410-k. Each of the control bits controls whether a switch 1420-1 through 1420-k of a respective branch 1410-1 through 1410-k is turned on (i.e., closed) or off (i.e., open). When a switch 1420-1 through 1420-k is turned on (i.e., closed), the respective branch 1410-1 through 1410-k is enabled, in which case the channel width of the respective transistor 1415-1 through 1415-k contributes to the channel width of the common gate amplifier 1430. When a switch 1420-1-1420-k is turned off (i.e., open), the respective branch 1410-1-1410-k is disabled, in which case the channel width of the respective transistor 1415-1-1415-k does not contribute to the channel width of the common gate amplifier 1430. In this example, the channel width of the common gate amplifier 1430 is the sum of the channel widths of the transistors 1415-1-1415-k in the enabled branches 1410-1-1410-k. Thus, in this example, the respective control signal controls the channel width of the common gate amplifier 1430 by controlling the number of enabled branches 1410-1-1410-k. The more enabled branches 1410-1-1410-k, the wider the channel width. Note that in the example where each of the second amplifiers 730-1 to 730-n is implemented by a common gate amplifier 1430 of FIG. 14A, the branches 1410-1 to 1410-k shown in FIG. 14A implement respective transistors 1230-1 to 1230-n.

[0124]

[0135] FIG. 14B illustrates another exemplary implementation of a common gate amplifier 1480, in which the common gate amplifier 1480 is configured to receive respective control signals (e.g., control signals Cw1-Cw n Each of the second amplifiers 730-1 through 730-n shown in FIG. 13 may be implemented by the common gate amplifier 1480 shown in FIG. 14B (i.e., each of the second amplifiers 730-1 through 730-n may be a separate instance of the common gate amplifier 1480 shown in FIG. 14B).

[0125]

[0136] 14B, common gate amplifier 1480 includes a plurality of parallel branches 1460-1 through 1460-k, each of which is coupled between an output 1484 and an input 1482 of common gate amplifier 1480. Output 1484 is coupled to summing node 735 (shown in FIG. 13), and input 1482 is coupled to a respective transmission line 725-1 through 725-n (shown in FIG. 13). Each of branches 1460-1 through 1460-k includes a respective transistor 1465-1 through 1465-k (e.g., an NFET) having a drain coupled to output 1484 and a source coupled to input 1482 of common gate amplifier 1480. Each of the branches 1460-1 through 1460-k also includes a respective switch 1470-1 through 1470-k coupled to the gate of a respective transistor 1465-1 through 1465-k. Each switch 1470-1 through 1470-k couples the gate of the respective transistor 1465-1 through 1465-k to a gate bias voltage Vg (e.g., gate bias voltages Vg1 through Vg2 of FIG. 13 ), as described further below. n Each switch 1470-1 through 1470-k may be implemented by a single-pole-two-throw (SP2T) switch or another type of switch.

[0126]

[0137] In this example, each control signal is represented by k control bits Cw <1> ~Cw <k>, where each of the control bits corresponds to a respective one of the branches 1460-1 through 1460-k. Each of the control bits controls whether the switch 1470-1 through 1470-k of the respective branch 1460-1 through 1460-k couples the gate of the respective transistor 1465-1 through 1465-k to the gate bias voltage Vg or to ground. In this regard, each of the control bits may configure the switch 1470-1 through 1470-k of the respective branch 1460-1 through 1460-k to couple the gate of the respective transistor 1465-1 through 1465-k to the gate bias voltage Vg or to ground. In one example, switches 1460-1 to 1460-k may be configured to couple the gates of respective transistors 1465-1 to 1465-k to a gate bias voltage Vg when the respective control bit has a first logical value, and to couple the gates of respective transistors 1465-1 to 1465-k to ground when the respective control bit has a second logical value.

[0127]

[0138] A respective branch 1460-1 to 1460-k is enabled when a switch 1460-1 to 1460-k couples the gate of a respective transistor 1465-1 to 1465-k to a gate bias voltage Vg, in which case the gate of the respective transistor 1465-1 to 1465-k is coupled to the gate voltage of the common gate amplifier (e.g., gate bias voltages Vg1 to Vg2 in FIG. 13 ). n Each branch 1460-1 through 1460-k is biased by a respective one of the control signals 1460-1 through 1460-k. When the switch 1470-1 through 1470-k couples the gate of the respective transistor 1465-1 through 1465-k to ground, the respective branch 1460-1 through 1460-k is disabled, in which case the respective transistor 1465-1 through 1465-k is turned off. In this example, the channel width of the common gate amplifier 1480 is the sum of the channel widths of the transistors 1465-1 through 1465-k in the enabled branches 1460-1 through 1460-k. Thus, in this example, the respective control signal controls the channel width of the common gate amplifier 1480 by controlling the number of enabled branches 1460-1 through 1460-k. The more enabled branches 1460-1 through 1460-k, the wider the channel width. Note that in the example where each of the second amplifiers 730-1 to 730-n is implemented by a common gate amplifier 1480 of FIG. 14B, the branches 1460-1 to 1460-k shown in FIG. 14B implement the respective transistors 1230-1 to 1230-n.

[0128]

[0139] Thus, the input impedance of each of the second amplifiers 730-1-730-n may be adjusted (i.e., tuned) by adjusting the respective gate bias voltage or the respective channel width. In some aspects, both the gate bias voltage and the channel width of each of the second amplifiers 730-1-730-n may be adjusted (i.e., tuned) to set the respective input impedance. In other words, the gate bias voltage and the channel width of each of the second amplifiers 730-1-730-n provide two degrees of freedom for setting the respective input impedance. For each of the second amplifiers 730-1-730-n, the respective gate bias voltage value and the respective channel width value may be programmed in combination such that the respective gate bias voltage value and the respective channel width value set the respective input impedance to a desired impedance (e.g., an impedance that matches the characteristic impedance of the respective transmission line). In operation, the gate bias circuit 1260 adjusts the gate bias voltages Vg1 to Vgn of the second amplifiers 730-1 to 730-n based on the respective gate bias voltage values ​​stored in the register 1350. n , and the control circuit 1360 sets the channel widths of the second amplifiers 730-1 to 730-n based on the respective channel width values ​​stored in the register 1250.

[0129]

[0140] In some embodiments, the characteristic impedance of the transmission lines 725-1-725-n may vary. For example, the characteristic impedance of the transmission lines may be frequency dependent. In this example, two transmission lines carrying signals in different frequency bands (e.g., HB and LB) may have different characteristic impedances. In another example, the characteristic impedance of the transmission lines 725-1-725-n may differ due to process variations and / or differences in the design of the transmission lines 725-1-725-n (i.e., one transmission line may be integrated on-chip while another is an off-chip transmission line). In these embodiments, the input impedance of each of the second amplifiers 730-1-730-n may be programmed by setting the respective gate bias voltages and / or setting the respective channel widths such that the respective input impedances approximately match the characteristic impedances of the respective transmission lines. Therefore, the input impedance of the second amplifiers 730-1 to 730-n can be individually programmed to approximately match the characteristic impedance of the respective transmission lines 725-1 to 725-n.

[0130]

[0141] In one example, a first one of the second amplifiers 730-1-730-n is coupled to a first one of the transmission lines 725-1-725-n and a second one of the second amplifiers 730-1-730-n is coupled to a second one of the transmission lines 725-1-725-n, and the first and second ones of the transmission lines 725-1-725-n have different characteristic impedances (e.g., for any one of the reasons described above). In this example, the input impedance of the first one of the second amplifiers 730-1-730-n may be programmed to approximately match the characteristic impedance of the first one of the transmission lines 725-1-725-n and the input impedance of the second one of the second amplifiers 730-1-730-n may be programmed to approximately match the characteristic impedance of the second one of the transmission lines 725-1-725-n. In this example, because the first and second ones of the transmission lines 725-1 through 725-n have different characteristic impedances, the first and second ones of the second amplifiers 730-1 through 730-n may be programmed to have different input impedances.

[0131]

[0142] In the above example, the first and second ones of the second amplifiers 730-1-730-n may be programmed to have different input impedances by biasing the first and second ones of the second amplifiers 730-1-730-n with different gate bias voltages. In this example, the register 1250 may store different gate bias voltage values ​​for the first and second ones of the second amplifiers 730-1-730-n. In another example, the first and second ones of the second amplifiers 730-1-730-n may be programmed to have different input impedances by setting the channel widths of the first and second ones of the second amplifiers 730-1-730-n to different widths. In this example, the register 1360 may store different channel width values ​​for the first and second ones of the second amplifiers 730-1-730-n. In another example, a first and second one of the second amplifiers 730-1 through 730-n can be programmed to have different input impedances by both biasing the first and second one of the second amplifiers 730-1 through 730-n with different gate bias voltages and setting the channel widths of the first and second one of the second amplifiers 730-1 through 730-n to different widths.

[0132]

[0143] FIG. 15 illustrates an example of a combiner 710, where the first amplifiers 720-1 to 720-n are current amplifiers and the second amplifiers 730-1 to 730-n are common gate amplifiers. In this example, each of the first amplifiers 720-1 to 720-n may be implemented by the example current amplifier 905 illustrated in FIG. 9. For ease of illustration, FIG. 15 illustrates details of only one of the first amplifiers (i.e., the first amplifier 720-1). The second amplifiers 730-1 to 730-n may be implemented by the common gate amplifiers illustrated in FIG.

[0133]

[0144] In this example, first amplifiers 720-1 through 720-n have programmable current gains, and the current gains of each of first amplifiers 720-1 through 720-n may be independently set by control circuit 1150 (shown in FIG. 11). Second amplifiers 730-1 through 730-n have programmable input impedances. The input impedances of each of second amplifiers 730-1 through 730-n may be set by gate bias circuit 1260 (shown in FIG. 12) and / or control circuit 1360 (shown in FIG. 13), as described above.

[0134]

[0145] In this example, each of the first amplifiers 720-1-720-n is configured to receive a respective input current (e.g., from an output of a respective one of the receiver elements 815-1-815-n), amplify the respective input current to generate a respective output current, and drive a respective transmission line 725-1-725-n with the respective output current. Each of the second amplifiers 730-1-730-n receives the output current of a respective one of the first amplifiers 720-1-720-n via a respective transmission line 725-1-725-n.

[0135]

[0146] In the example of FIG. 15, each of the first amplifiers 720-1 to 720-n has a high output impedance. This is because, as explained above, the impedance looking into the drain of each of the output transistors 925-1 to 925-n is high. The high output impedance of each of the first amplifiers 720-1 to 720-n enables each of the amplifiers 720-1 to 720-n to efficiently drive the respective transmission lines 725-1 to 725-n with a current. Each of the second amplifiers 730-1 to 730-n has a low input impedance (e.g., approximately equal to 1 / gm of each of the transistors 1230-1 to 1230-n).

[0136]

[0147] In the example of FIG. 15, each of the second amplifiers 730-1 to 730-n has a current gain of approximately unity. As a result, the output currents of the second amplifiers 730-1 to 730-n are approximately equal to the currents at the inputs 732-1 to 732-n of the second amplifiers 730-1 to 730-n. The output currents of the second amplifiers 730-1 to 730-n are combined into a combined current at a combining node 735. A load 740 converts the combined currents into a voltage that provides the combined signal of the combiner 710. The second amplifiers 730-1 to 730-n have a high output impedance, which helps to isolate the combined signal from the inputs 732-1 to 732-n of the second amplifiers 730-1 to 730-n.

[0137]

[0148] The output voltage swing of the composite signal depends on the impedance of the load 740. In some aspects, the impedance of the load 740 may be selected such that the composite signal has a desired output voltage swing. The desired output voltage swing may be high enough to provide a good signal-to-noise ratio (SNR), but not too high (which may put a large burden on the output of the second amplifiers 730-1 to 730-n and / or cause nonlinear distortion). FIG. 15 shows an example in which the load 740 is an inductive load including an inductor 1510. However, it should be appreciated that the disclosure is not limited to this example and the load 740 may be implemented by a choke, a bias T network, a resonator, or another type of load.

[0138]

[0149] The output voltage swing of the combined signal of the combiner 710 may be adjusted (i.e., tuned) by tuning the impedance of the load 740 (e.g., tuning the impedance of the load 740 at the center frequency of the signals being combined). The higher the impedance of the load 740, the larger the output voltage swing of the combined signal. In this example, the impedance of the load 740 may be adjusted by adjusting the inductance of an inductor in the load 740 and / or by adjusting the capacitance of a capacitor in the load 740. The load 740 may be implemented by a T network, a Pi network, an inductor-capacitor (LC) tank, etc.

[0139]

[0150] In another example, the output voltage swing may be adjusted (i.e., tuned) by adjusting the current gain of the first amplifiers 720-1 through 720-n. The higher the current gain, the higher the combined current at the combined node 735 and therefore the higher the output voltage swing for a given load impedance. The output voltage swing may also be adjusted by adjusting both the impedance of the load 740 and the current gain of the first amplifiers 720-1 through 720-n.

[0140]

[0151] As described above, the combiner 710 may be used as a single-band combiner or a dual-band combiner. In the case of a single-band combiner, the combiner 710 may combine signals within a frequency band. In this example, the load 740 may be configured to resonate at a resonant frequency within the frequency band such that the load 740 has a high impedance within the frequency band. The high impedance helps provide a high output voltage swing for the combined signal within the frequency band. In this example, the center frequency of the signals being combined may be located at or near the resonant frequency of the load 740.

[0141]

[0152] In the case of a dual-band combiner 710, the combiner 710 may combine one or more signals in a first frequency band with one or more signals in a second frequency band. In this example, the load 740 may be a dual-resonant load resonantly configured at a first resonant frequency in the first frequency band and a second resonant frequency in the second frequency band. As a result, the load 740 has a high impedance in the first frequency band and a high impedance in the second frequency band. The high impedance in the first frequency band provides a high output voltage swing in the first frequency band, and the high impedance in the second frequency band provides a high output voltage swing in the second frequency band.

[0142]

[0153] In an alternative implementation, the load 740 may be a wideband load that is tuned to a wide frequency band to provide high impedance (and high gain) over the wide frequency band. In this example, the wide frequency band includes (i.e., covers) the first and second frequency bands described above.

[0143]

[0154] 16 illustrates an example in which the combiner 710 includes multiple impedance matching networks 1615-1 to 1615-n (hereinafter simply referred to as matching networks). In this example, each of the matching networks 1615-1 to 1615-n is coupled between a respective one of the inputs 722-1 to 722-n of the first amplifiers 720-1 to 720-n and a respective one of the inputs 712-1 to 712-n of the combiner 710. In an example in which each of the inputs 712-1 to 712-n of the combiner 710 is coupled to a respective one of the outputs of the receiver elements 815-1 to 815-n, each of the matching networks 1615-1 to 1615-n is configured to provide impedance matching between a respective one of the inputs of the first amplifiers 720-1 to 720-n and a respective one of the outputs of the receiver elements 815-1 to 815-n. The impedance matching increases the power transfer between the outputs of the receiver elements 815-1 to 815-n and the inputs of the first amplifiers 720-1 to 720-n.

[0144]

[0155] Each of the matching networks 1615-1 to 1615-n may be implemented by an inductor, a transformer, a T-network, a π-network, an L-network, or another type of impedance matching network. Each of the matching networks 1615-1 to 1615-n may include reactive elements (e.g., inductors and / or capacitors) to reduce power losses in the matching networks 1615-1 to 1615-n.

[0145]

[0156] FIG. 17A illustrates an exemplary implementation of a matching network 1710. Each of the matching networks 1615-1 to 1615-n may be implemented by the exemplary matching network 1710 illustrated in FIG. 17A (i.e., each of the matching networks 1615-1 to 1615-n may be a separate instance of the matching network 1710 of FIG. 17A). The matching network 1710 is an example of an L-network. The matching network 1710 includes an inductor 1715 coupled between an input 1722 of the matching network 1710 and ground, and a capacitor 1720 coupled between the input 1722 and an output 1724 of the matching network 1710. The input 1722 is coupled to a respective input 712-1 to 712-n of the combiner 710, and the output 1724 is coupled to a respective one of the inputs 722-1 to 722-n of the first amplifiers 720-1 to 720-n. The inductance of inductor 1715 and the capacitance of capacitor 1720 may be selected to provide impedance matching between an input of each of first amplifiers 720-1 to 720-n and an output of each of receiver elements 815-1 to 815-n.

[0146]

[0157] 17B illustrates another exemplary implementation of a matching network 1750. Each of the matching networks 1615-1 through 1615-n may be implemented by the exemplary matching network 1750 illustrated in FIG. 17B (i.e., each of the matching networks 1615-1 through 1615-n may be a separate instance of the matching network 1750 of FIG. 17B). The matching network 1750 is an example of a π network. The matching network 1750 includes a first shunt capacitor 1760, a second shunt capacitor 1765, and an inductor 1755 coupled between the first shunt capacitor 1760 and the second shunt capacitor 1765. A first shunt capacitor 1760 is coupled between an input 1772 of matching network 1750 and ground, a second shunt capacitor 1765 is coupled between an output 1774 of matching network 1750 and ground, and an inductor 1755 is coupled between the input 1772 and the output 1774 of matching network 1750. The inductance of inductor 1755 and the capacitances of first and second shunt capacitors 1760 and 1765 may be selected to provide impedance matching between an input of each of first amplifiers 720-1 through 720-n and an output of each of receiver elements 815-1 through 815-n.

[0147]

[0158] In examples in which the combiner 710 is a dual-band combiner, one or more of the matching networks 1615-1 to 1615-n may be configured to provide impedance matching within a first frequency band (e.g., LB) to receive signals in the first frequency band, and one or more others of the matching networks 1615-1 to 1615-n may be configured to provide impedance matching within a second frequency band (e.g., HB) to receive signals in a second frequency band.

[0148]

[0159] A matching network (e.g., one of matching networks 1615-1 through 1615-n) used for a first frequency band (e.g., LB) may include one or more inductors and one or more capacitors disposed within the network. In this example, the inductance of one or more inductors (e.g., inductor 1715 or inductor 1755) and / or the capacitance of one or more capacitors (e.g., capacitor 1720 or capacitors 1760 and 1765) within the matching network may be selected such that the matching network provides impedance matching at a first frequency within the first frequency band. The first frequency may be approximately equal to a center frequency of a signal input to a respective one of first amplifiers 720-1 through 720-n, where the center frequency of the signal is within the first frequency band.

[0149]

[0160] A matching network (e.g., one of the matching networks 1615-1-1615-n) used for a second frequency band (e.g., HB) may include one or more inductors and one or more capacitors disposed within the network. In this example, the inductance of one or more inductors (e.g., inductor 1715 or inductor 1755) and / or the capacitance of one or more capacitors (e.g., capacitor 1720 or capacitors 1760 and 1765) within the matching network may be selected such that the matching network provides impedance matching at a second frequency within the second frequency band. The second frequency may be approximately equal to a center frequency of a signal input to each one of the first amplifiers 720-1-720-n, the center frequency of the signal being within the second frequency band. The first frequency and the second frequency may be spaced apart by at least 1 gigahertz (e.g., in an example where the first frequency band is LB and the second frequency band is HB).

[0150]

[0161] In the above examples, the matching network for the first frequency band and the matching network for the second frequency band may be implemented using the same type of network (e.g., a network, an L network, a π network, etc.) or different types of networks. The inductors and / or capacitors in the matching network for the first frequency band may have different inductances and / or capacitances than the inductors and / or capacitors in the matching network for the second frequency band, even if the same type of matching network is used for both frequency bands. This is because the matching networks are tuned to provide impedance matching at different frequencies (i.e., the first and second frequencies).

[0151]

[0162] The matching networks 1615-1-1615-n may be omitted in some implementations. For example, the matching networks 1615-1-1615-n may be omitted if the first amplifiers 720-1-720-n are current amplifiers and the inputs 722-1-722-n of the first amplifiers 720-1-720-n are driven by currents by the respective receiver elements 815-1-815-n. In this example, each of the receiver elements 815-1-815-n may have a high output impedance such that the outputs of the receiver elements approach an ideal current source (having infinite output impedance). This allows each of the receiver elements 815-1-815-n to efficiently drive the inputs 712-1-712-n of the respective first amplifiers 720-1-720-n by currents.

[0152]

[0163] In some aspects, the combiner 710 may be used for inter-chip signal combining, where the combiner 710 combines signals from two or more chips (i.e., dies). In this regard, FIG. 18 illustrates an example in which the combiner 710 combines signals from a first chip 1810 (labeled "IC1") and a second chip 1820 (labeled "IC2"). The first chip 1810 and the second chip 1820 may be mounted on a common substrate (e.g., a printed circuit board (PCB)). In the example illustrated in FIG. 18, a first one of the first amplifiers 720-1 is integrated on the first chip 1810, and a second one of the first amplifiers 720-2 is integrated on the second chip 1820. Also, the second amplifiers 730-1-730-2 and the load 740 are integrated on the second chip 1820.

[0153]

[0164] In this example, a first one of the first amplifiers 720-1 can receive a signal from a receiver element (e.g., a respective one of receiver elements 815-1 through 815-n) or a previous combining stage (e.g., a respective one of first combiner 635 and second combiner 665) and may or may not be integrated on the first chip 1810. Also, a second one of the first amplifiers 720-2 can receive a signal from a receiver element (e.g., a respective one of receiver elements 815-1 through 815-n) or a previous combining stage (e.g., a respective one of first combiner 635 and second combiner 665) and may or may not be integrated on the second chip 1820.

[0154]

[0165] In this example, at least a portion of the transmission line 725-1 that couples a first one of the first amplifiers 720-1 to a corresponding second amplifier 730-1 is external to the first chip 1810 and the second chip 1820. The external portion of the transmission line 725-1 may include a cable, a waveguide, or another type of transmission line that can carry an RF or IF signal. In an example in which the first chip 1810 and the second chip 1820 are implemented on a common substrate (e.g., a PCB), the external portion of the transmission line 725-1 may be formed on the substrate (e.g., including one or more metal traces on the substrate). Note that FIG. 18 illustrates the entire transmission line 725-1 as being external to the first and second chips 1810 and 1820 for ease of illustration. However, it should be appreciated that the transmission line 725-1 may include a first portion (e.g., a metal line) on the first chip 1810 and a second portion (e.g., a metal line) on the second chip 1820. The transmission line 725-2 coupling a second one of the first amplifiers 720-2 to a corresponding second amplifier 730-2 may be integrated on the second chip 1820, as shown in FIG.

[0155]

[0166] The combined signal at output 750 of the combiner 710 may be output to a receiving circuit (not shown) for further processing (e.g., frequency downconversion, filtering, demodulation, analog-to-digital conversion, baseband processing, etc.), or may be output to another combiner (not shown) in a subsequent combining stage to be combined with other signals (e.g., from other chips).

[0156]

[0167] 18, the combiner 710 may be a single-band combiner or a dual-band combiner. In a dual-band example, the signal input to a first one of the first amplifiers 720-1 is in a first frequency band (e.g., LB) and the signal input to a second one of the first amplifiers 720-2 is in a second frequency band (e.g., HB). In this example, the load 740 may be a dual-resonant load or a wideband load, as described above.

[0157]

[0168] Although FIG. 18 shows an example in which the combiner 710 combines signals from two chips (i.e., a first chip 1810 and a second chip 1820), it should be appreciated that the combiner 710 may combine signals from three or more chips.

[0158]

[0169] In some aspects, multiple combiners may be coupled together to form a larger combiner configured to combine signals from a large number of antennas (e.g., 64 or 128 antennas) in a phased antenna array (e.g., phased antenna array 205). An advantage of combining signals from a large number of antennas in a phased antenna array is that the large number of antennas allows the receive beam pattern to be very narrow (i.e., focused) for high receive directivity. In these aspects, each of the multiple combiners in the larger combiner may be implemented by combiner 710 (e.g., each of the multiple combiners may be a separate instance of combiner 710). The multiple combiners may be coupled in a tree configuration, a chain configuration, or another configuration to form the larger combiner.

[0159]

[0170] In one example, the number of receiver elements that may be combined into a single combiner (e.g., combiner 710) may be limited (e.g., due to parasitic and / or other limitations). In this example, combining multiple combiners together to form a larger combiner overcomes the limited number of receiver elements that may be combined into a single combiner, allowing signals from a much larger number of receiver elements to be combined.

[0160]

[0171] FIG. 19 illustrates an example of multiple combiners 1910-1 through 1910-4 and 1920 coupled together in a tree configuration to form a large combiner 1905. Each of the combiners 1910-1 through 1910-4 and 1920 may be implemented by the combiner 710 illustrated in FIG. 7, FIG. 8, FIG. 11, FIG. 12, FIG. 13, FIG. 15, or FIG. 16 (e.g., each of the combiners 1910-1 through 1910-4 and 1920 may be a separate example of the combiner 710). In the example illustrated in FIG. 19, each of the combiners 1910-1 through 1910-4 and 1920 is a 4-to-1 combiner, although it should be appreciated that the present disclosure is not limited to this example. The inputs of each of the combiners 1910-1 through 1910-4 are coupled to a respective set of four receiver elements 1915-1 through 1915-4. Each receiver element may receive a signal from a respective antenna in the phased antenna array (e.g., a respective one of antennas 210-1 through 210-k). The inputs of combiner 1920 are coupled to the outputs of combiners 1910-1 through 1910-4. The output of combiner 1920 provides an output (labeled “Out”) of large combiner 1905.

[0161]

[0172] In operation, each of the combiners 1910-1 through 1910-4 combines signals from a respective set of four receiver elements 1915-1 through 1915-4 into a respective combined signal and outputs the respective combined signal to the combiner 1920. The combiner 1920 combines the combined signals from the combiners 1910-1 through 1910-4 into a single combined signal and outputs the single combined signal at an output of the large combiner 1905. The single combined signal may be output to a receiver circuit (not shown) for further processing (e.g., frequency downconversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or may be output to another combiner (not shown) in a subsequent combining stage to be combined with other signals.

[0162]

[0173] The combiners 1910-1 to 1910-4 and 1920 may be formed on multiple chips, with the combiners 1910-1 to 1910-4 and 1920 including external transmission lines coupled between the chips. It should be appreciated that although FIG. 19 shows an example in which multiple 4 to 1 combiners are combined to form a 16 to 1 combiner, the disclosure is not limited to this example. For example, a larger number of combiners may be coupled together in a tree configuration to form more combiners (e.g., a 64 to 1 combiner or a 128 to 1 combiner).

[0163]

[0174] In one example, the first amplifiers 720-1 through 720-n of the combiner 1920 may be current amplifiers. In this example, if the output of each of the combiners 1910-1 through 1910-4 is a voltage, the output of each of the combiners 1910-1 through 1910-4 may be coupled to a respective input of the combiner 1920 via a transconductance amplifier (not shown) configured to convert the respective voltages to respective currents.

[0164]

[0175] FIG. 20 illustrates an example of multiple combiners 2010-1-2010-4 coupled together in a chain configuration to form a larger combiner 2005. Each of the combiners 2010-1-2010-4 may be implemented by the combiner 710 illustrated in FIG. 7, FIG. 8, FIG. 11, FIG. 12, FIG. 13, FIG. 15, or FIG. 16 (e.g., each of the combiners 2010-1-2010-4 may be a separate example of the combiner 710). An input of a first combiner 2010-1 in the chain is coupled to a respective set of receiver elements 2015-1. An input of a second combiner 2010-2 in the chain is coupled to a respective set of receiver elements 2015-2 and to an output of the first combiner 2010-1. The inputs of the third combiner 2010-3 in the chain are coupled to a respective set of receiver elements 2015-3 and to an output of the second combiner 2010-2. The inputs of the fourth combiner 2010-4 in the chain are coupled to a respective set of receiver elements 2015-4 and to an output of the third combiner 2010-3. The output of the fourth combiner 2010-4 provides an output (labeled "Out") of the large combiner 2005. Each receiver element may receive a signal from a respective antenna (e.g., a respective one of the antennas 210-1 through 210-k) in the phased antenna array.

[0165]

[0176] In operation, the first combiner 2010-1 combines signals from each set of receiver elements 2015-1 into a respective combined signal and outputs each combined signal to the second combiner 2010-2. The second combiner 2010-2 combines signals from each set of receiver elements 2015-2 with the combined signal from the first combiner 2010-1 into a respective combined signal and outputs each combined signal to the third combiner 2010-3. The third combiner 2010-3 combines signals from each set of receiver elements 2015-3 with the combined signal from the second combiner 2010-2 into a respective combined signal and outputs each combined signal to the fourth combiner 2010-4. The fourth combiner 2010-4 combines the signals from each set of receiver elements 2015-4 with the combined signal from the third combiner 2010-3 into a respective combined signal and outputs the respective combined signal as a combined signal for the large combiner 2005. The combined signal may be output to a receiving circuit (not shown) for further processing (e.g., frequency downconversion, filtering, analog-to-digital conversion, demodulation, baseband processing, etc.) or may be output to another combiner (not shown) in a subsequent combining stage to be combined with other signals.

[0166]

[0177] The combiners 2010-1 to 2010-4 may be formed on multiple chips, and the combiners 2010-1 to 2010-4 include external transmission lines coupled between the chips.

[0167]

[0178] It should be appreciated that the present disclosure is not limited to the example configurations shown in Figures 19 and 20. For example, multiple combiners may be combined in a hybrid configuration in which the combiners are divided into groups. In this example, the combiners within a group may be combined in a chain configuration, while groups of combiners may be combined in a tree configuration, or vice versa.

[0168]

[0179] FIG. 21 illustrates a method 2100 for signal combining according to some aspects of the disclosure.

[0169]

[0180] At block 2110, a signal is received from a receiver element. The receiver element may correspond to receiver elements 315-1 through 315-n, 415-1 through 415-n, 515-1 through 515-n, 615-1 through 615-n, or 645-1 through 645-m.

[0170]

[0181] In block 2120, the signals from the receiver elements are amplified to first amplified signals. The signals from the receiver elements may be amplified using current amplifiers (e.g., current amplifiers 720-1 through 720-n of FIG. 11) or transconductance amplifiers. In some aspects, first ones of the signals from the receiver elements are amplified by a first gain and second ones of the signals from the receiver elements are amplified by a second gain, where the first gain and the second gain are different.

[0171]

[0182] In block 2130, a transmission line is driven by the first amplified signal. The transmission line may correspond to transmission lines 725-1 through 725-n.

[0172]

[0183] A first amplified signal is received from a transmission line at block 2140. In some aspects, the transmission line is driven by the first amplified signal at a first end of the transmission line, and the first amplified signal is received at a second end of the transmission line.

[0173]

[0184] In block 2150, the first amplified signal from the transmission line is amplified to a second amplified signal. The first amplified signal from the transmission line may be amplified using a common gate amplifier (e.g., common gate amplifiers 734-1 through 734-n of FIG. 12). In one example, each of the first and second ones of the common gate amplifiers has an adjustable channel width. In this example, the channel width of the first one of the common gate amplifiers may be set to a first channel width and the channel width of the second one of the common gate amplifiers may be set to a second channel width, but the first channel width is different from the second channel width. In one example, the gate of the first one of the common gate amplifiers may be biased by a first gate bias voltage and the gate of the second one of the common gate amplifiers may be biased by a second gate bias voltage, but the first gate bias voltage is different from the second gate bias voltage.

[0174]

[0185] The second amplified signals are combined into a combined signal at block 2160. In examples in which the first amplified signals are amplified into a second amplified signal using a common gate amplifier, the second amplified signals may be combined at a combining node (e.g., combining node 735) coupled to an output of the common gate amplifier.

[0175]

[0186] As used herein, the term "receiver" may refer to a device that processes one or more signals received from one or more antennas (e.g., in a phased antenna array). A "receiver" does not have to process one or more signals all the way to a baseband signal. For example, a "receiver" may process one or more signals to an intermediate signal (e.g., a composite signal), which is further processed by subsequent receive circuitry to a baseband signal.

[0176]

[0187] As used herein, the term "electronically adjustable" means adjustable by an electrical signal such as a voltage or current.

[0177]

[0188] It should be appreciated that any of the transmission lines described above may include one or more metal traces on a chip (die), one or more metal traces on a printed circuit board, one or more cables (e.g., one or more coaxial cables), a waveguide, or any combination thereof.

[0178]

[0189] It should be appreciated that the present disclosure is not limited to the example terminology used above to describe aspects of the present disclosure. For example, the term "signal combining" may be referred to as "power combining." In another example, the term "impedance matching" may be referred to as "power matching." In another example, the term "receiver element" may be referred to as a "receiver chain." In examples where a "receiver element" outputs an RF signal, the "receiver element" may be referred to as an "RF chain."

[0179]

[0190] The above-described phase shift controllers 355, 455, 555 and 680, the control circuit 1070, the control circuit 1150, the gate bias circuit 1260 and the control circuit 1360 may each be implemented by a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof designed to perform the functions described herein. The processor may perform the functions by executing software comprising codes for performing the functions described herein. The software may be stored in a computer-readable storage medium, such as a RAM, a ROM, an EEPROM, an optical disk, and / or a magnetic disk.

[0180]

[0191] References herein to elements using designations such as "first," "second," etc. are not intended to generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, references to a first and a second element do not imply that only two elements may be utilized or that the first element must precede the second element.

[0181]

[0192] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to a direct or indirect coupling between two structures.

[0182]

[0193] The above description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. The invention as described in the claims of the original application is set forth below. [C1] first amplifiers, each of said first amplifiers having an input and an output; second amplifiers, each of the second amplifiers having an input and an output, the output of the second amplifiers being coupled to a combining node; transmission lines, each of said transmission lines being coupled between said output of a respective one of said first amplifiers and said input of a respective one of said second amplifiers; a load coupled to the combining node; receiver elements, each of said receiver elements having an input and an output, said output of each of said receiver elements being coupled to said input of a respective one of said first amplifiers; A receiver comprising: [C2] Further comprising an antenna; The receiver of C1, wherein the input of each of the receiver elements is coupled to a respective one of the antennas. [C3] Each of the receiver elements comprises a phase shifter, the phase shifter comprising: receiving a signal from said respective one of said antennas; shifting the phase of the signal from said respective one of said antennas by a respective phase shift; 3. The receiver according to claim 2, configured to: [C4] A phase shift controller is further included, 4. The receiver of claim 3, wherein the antenna is part of a phased antenna array, and for each of the receiver elements, the phase shift controller is configured to set the respective phase shift based on a receive direction of the phased antenna array. [C5] a local oscillator configured to generate a local oscillator signal; Each of the receiver elements further comprises a mixer, the mixer comprising: receiving the phase shifted signals from the respective phase shifters; mixing the phase shifted signals from each of the phase shifters with the local oscillator signal; 4. The receiver of claim 3, configured to: [C6] a local oscillator configured to generate a local oscillator signal; Each of the receiver elements comprises a mixer, the mixer comprising: receiving a signal from said respective one of said antennas; mixing the signal from said respective one of said antennas with said local oscillator signal; 3. The receiver according to claim 2, configured to: [C7] a local oscillator configured to generate a local oscillator signal; Each of the receiver elements comprises: a phase shifter configured to receive the local oscillator signal and to shift the phase of the local oscillator signal by a respective phase shift; a mixer configured to receive a signal from said respective one of said antennas and mix said signal from said respective one of said antennas with said respective phase shifted local oscillator signal; The receiver according to C2, comprising: [C8] The receiver of claim C1, wherein each of the second amplifiers is a common gate amplifier. [C9] Receiver according to C8, wherein each of the second amplifiers comprises a transistor having a drain coupled to the combination node, a gate, and a source coupled to the respective one of the transmission lines. [C10] Further comprising a gate bias circuit; 9. The receiver of claim 8, wherein for each of the second amplifiers, the gate bias circuit is configured to bias the gate of the respective transistor. [C11] The gate bias circuit includes: biasing the gate of the transistor of a first one of the second amplifiers at a first gate bias voltage; biasing the gate of the transistor of a second one of the second amplifiers at a second gate bias voltage, where the first gate bias voltage and the second gate bias voltage are different; 4. The receiver of claim 3, further comprising: [C12] a register configured to store a respective gate bias voltage value for each of the second amplifiers; 13. The receiver of claim 10, wherein, for each of the second amplifiers, the gate bias circuit is configured to bias the gate of the respective transistor based on the respective gate bias voltage value in the resistor. [C13] The receiver of claim 12, wherein the gate bias voltage value of a first one of the second amplifiers is different from the gate bias voltage value of a second one of the second amplifiers. [C14] The receiver of C8, wherein each of the second amplifiers has an electronically adjustable channel width. [C15] Each of the second amplifiers comprises: a plurality of branches coupled between the combined node and the respective ones of the transmission lines; each of the plurality of branches comprises a transistor and a switch coupled in series, each of the plurality of branches being enabled by closing the respective switch; the receiver further comprises a control circuit configured to set the channel width of each of the second amplifiers by controlling a number of the respective branches that are enabled. A receiver as described in C14. [C16] Each of the second amplifiers comprises: a plurality of branches coupled between the combined node and the respective ones of the transmission lines; each of the plurality of branches comprises a transistor and a switch configured to selectively couple a gate of the transistor to a gate bias voltage or to ground, each of the plurality of branches being enabled by setting the respective switch to couple the gate of the respective transistor to the gate bias voltage; The receiver of claim 14, further comprising a control circuit configured to set the channel width of each of the second amplifiers by controlling a number of the respective branches that are enabled. [C17] The receiver of C16, wherein the switch in each of the plurality of branches comprises a respective single-pole, double-throw switch. [C18] a register configured to store, for each of the second amplifiers, a respective channel width value; a control circuit configured to set the channel width of each of the second amplifiers based on the respective channel width value in the register; The receiver of claim 14, further comprising: [C19] The receiver of claim 18, wherein the channel width value of a first one of the second amplifiers is different from the channel width value of a second one of the second amplifiers. [C20] The receiver of claim 1, wherein each of the first amplifiers is a current amplifier. [C21] Each of the first amplifiers comprises: A current source; a current mirror having an input and an output, wherein the input of the current mirror is coupled to the current source and the input of the first amplifier, and the output of the current mirror is coupled to the respective one of the transmission lines; The receiver according to C20, comprising: [C22] The receiver of C21, wherein the current mirror of each of the first amplifiers has an electronically adjustable current mirror ratio. [C23] a register configured to store, for each of the first amplifiers, a respective current gain value; a control circuit configured to set the current mirror ratio of the current mirror of each of the first amplifiers based on the respective current gain value in the register; 23. The receiver of claim 22, further comprising: [C24] The receiver of C23, wherein the current gain value of a first one of the first amplifiers is different from the current gain value of a second one of the first amplifiers. [C25] The current mirror of each of the first amplifiers comprises: an input transistor having a drain coupled to the input of the current mirror, a gate coupled to the input of the current mirror, and a source coupled to ground; an output transistor having a drain coupled to the output of the current mirror, a gate coupled to the gate of the input transistor, and a source coupled to the ground; Receiver according to C21, comprising: [C26] The receiver of C25, wherein for each of the first amplifiers, the input transistor of the respective current mirror has an electronically adjustable channel width. [C27] The receiver of C25, wherein for each of the first amplifiers, the output transistor of the respective current mirror has an electronically adjustable channel width. [C28] 2. The receiver of claim 1, wherein a first one of the transmission lines has a length that is at least 20 percent greater than a length of a second one of the transmission lines. [C29] The receiver of C1, wherein the load comprises at least one of an inductor, a choke, or a resonator. [C30] a first one of the first amplifiers is integrated on a first chip; a second one of the first amplifiers is integrated on a second chip; a first and a second one of the second amplifiers are integrated on the second chip; a first one of the transmission lines is coupled between the output of the first one of the first amplifiers and the input of the first one of the second amplifiers; at least a portion of the first of the transmission lines is external to both the first chip and the second chip; A receiver as described in C1. [C31] a second one of the transmission lines is integrated on the second chip; the second one of the transmission lines is coupled between the output of the second one of the first amplifiers and the input of the second one of the second amplifiers. A receiver as described in C30. [C32] the first and second chips are mounted on a substrate; the at least a portion of the first one of the transmission lines is formed on the substrate. A receiver as described in C30. [C33] a first matching network coupled between the input of a first one of the first amplifiers and the output of a first one of the receiver elements; a second matching network coupled between the input of a second one of the first amplifiers and the output of a second one of the receiver elements; Further equipped with the first matching network is configured to provide an impedance match between the input of the first one of the first amplifiers and the output of the first one of the receiver elements at a first frequency; the second matching network is configured to provide an impedance match between the input of the second one of the first amplifiers and the output of the second one of the receiver elements at a second frequency. A receiver as described in C1. [C34] The receiver of C33, wherein the load is tuned to a wide frequency band, the wide frequency band including the first frequency and the second frequency. [C35] The receiver of claim 33, wherein the load comprises a dual resonant load. [C36] The receiver of C33, wherein the first frequency and the second frequency are spaced apart by at least 1 gigahertz. [C37] 1. A method for signal synthesis, comprising: Receiving a signal from a receiver element; amplifying the signal from the receiver element into a first amplified signal; Driving a transmission line with the first amplified signal; receiving the first amplified signal from the transmission line; amplifying the first amplified signal from the transmission line to obtain a second amplified signal; combining the second amplified signals into a combined signal; A method comprising: [C38] Amplifying the signal from the receiver element comprises: amplifying a first one of the signals from the receiver element by a first gain to obtain a first one of the first amplified signals; amplifying a second one of the signals from the receiver element by a second gain to become a second one of the first amplified signals; Equipped with The method of C37, wherein the first gain and the second gain are different. [C39] Driving the transmission line comprises: driving a first one of the transmission lines with the first one of the first amplified signals; driving a second one of the transmission lines with the second one of the first amplified signals; Equipped with The method of C38, wherein the first one of the transmission lines has a length that is at least 20 percent greater than a length of the second one of the transmission lines. [C40] amplifying the first ones of the signals from the receiver elements comprises amplifying the first ones of the signals from the receiver elements on a first chip; combining the second amplified signals comprises combining the second amplified signals on a second chip; driving the transmission lines comprises driving a first one of the transmission lines with the first one of the first amplified signals; at least a portion of the first of the transmission lines is external to both the first chip and the second chip; The method described in C38. [C41] driving the transmission lines comprises driving a second one of the transmission lines with the second one of the first amplified signals; The method of C40, wherein the second one of the transmission lines is integrated on the second chip. [C42] the second amplified signal comprises a current; combining the second amplified signals comprises combining the currents into a combined current and conducting the combined current through a load to generate the combined signal. The method described in C37. [C43] The method of C42, wherein the load comprises at least one of an inductor, a choke, or a resonator. [C44] a first one of the signals from the receiver element has a first frequency; a second one of the signals from the receiver element has a second frequency; the load comprises a broadband load tuned to a wide frequency band including the first frequency and the second frequency, or the load comprises a dual resonant load. The method described in C42. [C45] The method of claim 44, wherein the first frequency and the second frequency are spaced apart by at least 1 gigahertz. [C46] the first amplified signal comprises a current; driving the transmission lines with the first amplified signal comprises conducting each of the currents through a respective one of the transmission lines. The method described in C37. [C47] The method of C37, wherein amplifying the first amplified signal from the transmission line comprises amplifying the first amplified signal from the transmission line using a common gate amplifier. [C48] each of the first and second of the common gate amplifiers having an adjustable channel width; The method comprises: setting the channel width of the first one of the common gate amplifiers to a first channel width and setting the channel width of the second one of the common gate amplifiers to a second channel width; the first channel width is different from the second channel width; The method described in C47. [C49] biasing a gate of a first one of the common gate amplifiers with a first gate bias voltage and biasing a gate of a second one of the common gate amplifiers with a second gate bias voltage; the gate bias voltage is different from the second gate bias voltage; The method described in C47. < / k> < / k> < / m>

Claims

1. A receiver comprising: receiver elements for generating receiver element signals, each of said receiver elements having an input and an output; antennas, wherein the input of each of the receiver elements is coupled to a respective one of the antennas; a first amplifier, each of said first amplifiers having an input and an output, a receiver element signal output from said output of each of said receiver elements being input to said input of a respective one of said first amplifiers; second amplifiers, each of the second amplifiers having an input and an output, the output of the second amplifiers coupled to a combining node; transmission lines, each of said transmission lines being coupled between said output of a respective one of said first amplifiers and said input of a respective one of said second amplifiers; a load coupled to the combining node; a local oscillator configured to generate a local oscillator signal; Equipped with Each of the receiver elements comprises a mixer, the mixer comprising: receiving a signal from said respective one of said antennas; mixing the signal from the respective one of the antennas with the local oscillator signal or a signal based on the local oscillator signal to generate the receiver element signal; A receiver configured to:

2. Each of the receiver elements comprises a phase shifter, the phase shifter comprising: receiving a signal from said respective one of said antennas; shifting the phase of the signal from said respective one of said antennas by a respective phase shift to generate a phase shifted signal; 2. The receiver of claim 1, configured to:

3. A phase shift controller is further included, the antenna is part of a phased antenna array, and for each of the receiver elements, the phase shift controller is configured to set the respective phase shift based on a receive direction of the phased antenna array; or Each mixer is receiving the phase shifted signals from the respective phase shifters; mixing the phase shifted signals from each of the phase shifters with the local oscillator signal; 3. The receiver of claim 2, configured to:

4. Each of the receiver elements comprises: a phase shifter configured to receive the local oscillator signal and shift the phase of the local oscillator signal by a respective phase shift to generate a respective phase-shifted local oscillator signal; Each mixer is receiving a signal from said respective one of said antennas; 2. The receiver of claim 1 configured to mix the signal from said respective one of said antennas with said respective phase-shifted local oscillator signal.

5. a first one of the transmission lines has a length that is at least 20 percent greater than a length of a second one of the transmission lines; or The receiver of claim 1 , wherein the load comprises at least one of an inductor, a choke, or a resonator.

6. a first one of the first amplifiers is integrated on a first chip; a second one of the first amplifiers is integrated on a second chip; a first and a second one of the second amplifiers are integrated on the second chip; a first one of the transmission lines is coupled between the output of the first one of the first amplifiers and the input of the first one of the second amplifiers; at least a portion of the first one of the transmission lines is external to both the first chip and the second chip; 2. The receiver of claim 1.

7. A receiver comprising: receiver elements for generating receiver element signals, each of said receiver elements having an input and an output; a first amplifier, each of said first amplifiers having an input and an output, said receiver element signal output from said output of each of said receiver elements being input to said input of a respective one of said first amplifiers; second amplifiers, each of the second amplifiers having an input and an output, the output of the second amplifiers coupled to a combining node; transmission lines, each of said transmission lines being coupled between said output of a respective one of said first amplifiers and said input of a respective one of said second amplifiers; a load coupled to the combining node; Equipped with each of the second amplifiers is a common gate amplifier; each of the second amplifiers comprises a transistor having a drain coupled to the combination node, a gate, and a source coupled to the respective one of the transmission lines; A receiver comprising:

8. and a gate bias circuit configured to bias the gate of the respective transistor for each of the second amplifiers; The gate bias circuit includes: biasing the gate of the transistor of a first one of the second amplifiers at a first gate bias voltage; biasing the gate of the transistor of a second one of the second amplifiers at a second gate bias voltage, where the first gate bias voltage and the second gate bias voltage are different; or a register configured to store a respective gate bias voltage value for each of the second amplifiers; 8. The receiver of claim 7, wherein for each of the second amplifiers, the gate bias circuit is configured to bias the gate of the respective transistor based on the respective gate bias voltage value in the resistor.

9. The receiver of claim 7, wherein each of the second amplifiers has an electronically adjustable channel width.

10. Each of the second amplifiers comprises: a plurality of branches coupled between the combining node and said respective ones of the transmission lines; each of the plurality of branches comprises a transistor and a switch coupled in series, each of the plurality of branches being enabled by closing the respective switch; the receiver further comprising a control circuit configured to set the channel width of each of the second amplifiers by controlling a number of the respective branches that are enabled.

10. The receiver of claim 9.

11. Each of the second amplifiers comprises: a plurality of branches coupled between the combining node and said respective ones of the transmission lines; each of the plurality of branches comprises a transistor and a switch configured to selectively couple a gate of the transistor to a gate bias voltage or to ground, each of the plurality of branches being enabled by setting the respective switch to couple the gate of the respective transistor to the gate bias voltage; the receiver further comprises a control circuit configured to set the channel width of each of the second amplifiers by controlling a number of the respective branches that are enabled; 10. The receiver of claim 9, wherein the switches in each of the plurality of branches comprise respective single-pole, double-throw switches.

12. A method for controlling a channel width of a first amplifier comprising: a control circuit configured to set the channel width of each of the second amplifiers based on the respective channel width value in the register; Further equipped with 10. The receiver of claim 9, wherein the channel width value of a first one of the second amplifiers is different from the channel width value of a second one of the second amplifiers.

13. 1. A method for signal synthesis, comprising: receiving, by a receiver element, an antenna signal from an antenna; mixing, by the receiver element, the antenna signal with a local oscillator signal generated by or based on a local oscillator signal into a receiver element signal; receiving, by a first amplifier, the receiver element signal from the receiver element; amplifying, with the first amplifier, the receiver element signal from the receiver element into a first amplified signal; driving a transmission line with the first amplified signal; receiving, by a second amplifier, the first amplified signal from the transmission line; amplifying the first amplified signal from the transmission line by the second amplifier to obtain a second amplified signal; combining the second amplified signals into a combined signal; A method comprising:

14. 1. A method for signal synthesis, comprising: receiving a signal from a receiver element by a first amplifier; amplifying, with the first amplifier, the signal from the receiver element into a first amplified signal; driving a transmission line with the first amplified signal; receiving, by a second amplifier, the first amplified signal from the transmission line; amplifying the first amplified signal from the transmission line by the second amplifier to obtain a second amplified signal; combining the second amplified signals into a combined signal; wherein amplifying the first amplified signal from the transmission line comprises amplifying the first amplified signal from the transmission line using a common gate amplifier. A method comprising:

15. each of the first and second of the common gate amplifiers having an adjustable channel width; The method comprises: setting the channel width of the first one of the common gate amplifiers to a first channel width and setting the channel width of the second one of the common gate amplifiers to a second channel width; the first channel width is different from the second channel width; or The method comprises: biasing a gate of a first one of the common gate amplifiers with a first gate bias voltage and biasing a gate of a second one of the common gate amplifiers with a second gate bias voltage; the first gate bias voltage is different from the second gate bias voltage; The method of claim 14.

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