Pixel circuit, driving method thereof, and display panel

Abstract

The embodiments of the present application disclose a pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a driving module, a data writing module, a compensation module, a leakage suppression module, and a first storage module. A first end of the compensation module is electrically connected to a second end of the driving module, a first light-emitting control signal is accessed at a control end of the compensation module, a first end of the leakage suppression module is electrically connected to the control end of the driving module, a second end of the leakage suppression module is electrically connected to the second end of the compensation module, a first light-emitting control signal is accessed at a control end of the leakage suppression module, a first end of the first storage module is electrically connected to the second end of the compensation module, a reference voltage signal is accessed at the second end of the first storage module, and the first storage module is configured to maintain the voltage difference unchanged when a voltage difference is formed between the first end of the first storage module and the second end of the first storage module.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application bearing application number 202111100960.1, filed with the China Patent Office on September 18, 2021, the entire contents of which are incorporated herein by reference.

[0002] The embodiments of the present application relate to the field of display technology, for example, a pixel circuit and a driving method thereof, and a display panel. [Background technology]

[0003] With the continuous development of display technology, people's requirements for display panels are also increasing, and display panels are developing in the direction of high display quality, multiple frame rate modes and low power consumption. The power consumption of a display panel is mainly due to pixel circuits and light emitting elements. As for the pixel circuit, the power consumption can be reduced by lowering the frame rate, but when the refresh rate of the display panel is low, there is a problem of leakage current in the pixel circuit, which causes the phenomenon of flicker on the display screen, which affects the display quality of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel for improving the leakage current problem of the pixel circuit at a low refresh rate and achieving both low power consumption and high display quality. [Means for solving the problem]

[0005] The embodiment of the present application is a drive module having a control end, a first end and a second end; a data writing module, the data writing module having a scanning control end through which a first scanning signal is accessed, a first end electrically connected to the first end of the driving module, and a second end through which a data signal is accessed; a compensation module having a control end through which a first light emission control signal is accessed, a first end electrically connected to the second end of the driving module, and a second end; a leakage current suppression module, the leakage current suppression module having a control end through which the first light emission control signal is accessed, a first end electrically connected to the control end of the driving module, and a second end electrically connected to the second end of the compensation module, the leakage current suppression module being electrically connected to the compensation module during an initialization phase and a data writing phase; A technical solution for a pixel circuit is provided, comprising: a first memory module having a first end electrically connected to the second end of the compensation module and a second end through which a reference voltage signal is accessed, and configured to maintain a voltage difference unchanged when a voltage difference is formed between the first end of the first memory module and the second end of the first memory module during the data writing phase and the light emitting phase.

[0006] The present application further provides a display panel comprising the pixel circuit according to any of the embodiments of the present application.

[0007] The present application, In the initialization stage, the first light emission control signal is different from the first end of the driving module and the second end of the driving module. Electrical Signal When the access is made, control the compensation module and the leakage current suppression module to be conductive so as to initialize the driving module; In a data writing step, the first light emitting control signal controls the compensation module and the leakage suppression module to be conductive, the first scanning signal controls the data writing module to be conductive, so as to write the data signal into the control end of the driving module, the potentials of the first end of the first storage module and the control end of the driving module are equal, and a voltage difference is formed between the first end of the first storage module and the second end of the first storage module; In a light emitting stage, the first light emitting control signal controls the compensation module and the leakage current suppression module to be turned off, the first scanning signal controls the data writing module to be turned off, and the first memory module maintains a voltage difference between the first end of the first memory module and the second end of the first memory module unchanged, so as to make the potentials of the first end of the leakage current suppression module and the second end of the leakage current suppression module equal, and further provides a driving method for a pixel circuit applicable to a pixel circuit relating to any embodiment of the present application. Effect of the Invention

[0008] In the embodiment of the present application, the leakage suppression module is arranged between the control end of the driving module and the second end of the compensation module, and the first storage module is arranged between the reference voltage signal and the second end of the compensation module. In this way, the control end of the driving module is provided with only one leakage current path, which connects the control end of the driving module and the second end of the driving module, and the path is composed of the leakage suppression module and the compensation module controlled by the first light emission control signal. Only after the potential of the second end of the compensation module has drifted significantly, the leakage suppression module generates a large leakage current and the potential of the control end of the driving module drifts. And in the embodiment of the present application, since the potential of the control end of the driving module is close to the potential of the second end of the compensation module, the leakage current of the leakage suppression module is small, and the magnitude of the leakage current of this only leakage path is reduced, so that the potential of the control end of the driving module is more stable, a high current holding rate is realized, and the flicker phenomenon of the display panel is improved.

[0009] The embodiments of the present application make a breakthrough improvement in the reset path and reset method of the control end of the driving module, and combine the first memory module with the leakage current suppression module to effectively suppress the leakage current of the control end of the driving module, which is advantageous for realizing high-quality display at a low frame rate, and is advantageous for realizing the effect of achieving both low power consumption and high display quality.

[0010] At the same time, the pixel circuit according to the embodiment of the present application provides different inputs to the first end of the driving module and the second end of the driving module during the initialization stage. Electrical Signal When the control end of the driving module is accessed, for example, when a first power supply signal is accessed at the first end and a second power supply signal is accessed at the second end, the driving module is turned on and a large current can flow, which is beneficial to initializing the control end of the driving module and at the same time improving the bias state of the driving module, and is beneficial to improving the problem of image retention. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a schematic circuit diagram of one pixel circuit. [Diagram 2] FIG. 2 is a schematic diagram of the layout of the pixel circuit shown in FIG. [Diagram 3] FIG. 11 is a circuit schematic diagram of another pixel circuit. [Figure 4] FIG. 4 is a schematic diagram of the layout of the pixel circuit shown in FIG. [Diagram 5] FIG. 2 is a structural schematic diagram of one pixel circuit according to an embodiment of the present application. [Figure 6] FIG. 4 is a structural schematic diagram of another pixel circuit according to an embodiment of the present application. [Figure 7] FIG. 13 is a structural schematic diagram of yet another pixel circuit according to an embodiment of the present application. [Figure 8] FIG. 8 is a schematic diagram of the layout of the pixel circuit shown in FIG. [Figure 9] FIG. 4 is a schematic diagram showing a flow of a method for driving one pixel circuit according to an embodiment of the present application. [Figure 10] FIG. 4 is a schematic diagram of a time sequence of driving one pixel circuit according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present application will be described with reference to the drawings and examples. It is understood that the specific examples described here are merely for the purpose of interpreting the present application and do not limit the present application. In addition, in order to facilitate the description, the drawings show only parts related to the present application, not all structures.

[0013] 1 and 2, the pixel circuit has a 7T1C structure. The pixel circuit includes a transistor M1', a transistor M2', a transistor M3', a transistor M4', a transistor M5', a transistor M6', a transistor M7', and a capacitor Cst'. Exemplarily, all the transistors are P-type transistors and are fabricated using a low temperature polysilicon (LTPS) process. The LTPS transistor has the advantages of high mobility, strong driving capability, and low process cost, and is widely used in pixel circuits, but has the disadvantage that the driving current generated in the pixel circuit fluctuates greatly due to a large leakage current. This is because the transistor M1' is a driving transistor, and the voltage of the gate electrode G' of the transistor M1' is stored by the capacitor Cst', but there are two leakage paths in the gate electrode G', namely, leakage through the transistor M3' and the transistor M4'. Generally, current leaks in from the drain electrode D' via the transistor M3', and current leaks out from the reference voltage signal Vref via the transistor M4'. This is limited by the difference in potential between multiple nodes, and it is difficult for one input and one output of the leakage current of the gate electrode G' to be completely offset, so a large fluctuation appears in the potential of the gate electrode G', which causes a large fluctuation in the drive current of the transistor M1'.

[0014] In order to solve the technical problem, still referring to FIG. 1, the first improvement scheme is to change the two leakage path transistors into dual gate transistors. The transistor M3' is equivalent to the transistor M3-1' and the transistor M3-2' connected in series, and the transistor M4' is equivalent to the transistor M4-1' and the transistor M4-2' connected in series. Compared with the single gate transistor, the dual gate transistor has a lower leakage current, which can reduce the potential fluctuation of the gate electrode G' to a certain extent, but the improvement of the leakage effect of this scheme is not satisfactory.

[0015] The second improvement is to change the transistors of the two leakage paths to low temperature polycrystalline oxide (LTPO) transistors. Compared with LTPS transistors, LTPO transistors have the advantage of having a smaller leakage current, which can effectively solve the problem caused by the leakage current of the gate electrode G'. However, this method adds the process of oxide thin film transistors to the manufacturing process of the display panel, which significantly increases the process cost.

[0016] 3 and 4, the third improvement plan is to add a transistor M8' to the 7T1C circuit to obtain an 8T1C circuit. Compared with the first improvement plan, this plan further improves the leakage problem of the gate electrode G'. However, as can be seen from the comparison of FIG. 2 and FIG. 4, this plan needs to add the light emission control signal EMB' based on the circuit layout of the 7T1C, which makes the layout arrangement of this plan complicated.

[0017] For the above reasons, the pixel circuit cannot simultaneously take into consideration a number of effects, such as low power consumption, low leakage current, low cost, and simplified layout arrangement.

[0018] An embodiment of the present application provides a pixel circuit. Referring to FIG. 5, the pixel circuit includes a driving module 100, a data writing module 200, a compensation module 300, a leakage suppression module 400 and a first storage module 500. The driving module 100 includes a control end, a first end and a second end. Preferably, the driving module 100 includes a driving transistor MD. Taking the driving transistor MD as a P-type transistor as an example, the gate electrode G of the driving transistor MD is the control end of the driving module 100, the source electrode S of the driving transistor MD is the second node N2, i.e. the first end of the driving module 100, and the drain electrode D of the driving transistor MD is the third node N3, i.e. the second end of the driving module 100. If the gate electrode G and the drain electrode D of the driving transistor MD are conductive, the driving transistor MD is a diode-connected mode, and when the source electrode S is at a high level and the drain electrode D is at a low level, the driving transistor MD is conductive to generate a driving current.

[0019] The data writing module 200 has a scanning control end, a first end and a second end, the first end of the data writing module 200 is electrically connected to the first end of the driving module 100, the second end of the data writing module 200 is accessed by the data signal Data, and the scanning control end of the data writing module 200 is accessed by the first scanning signal S1. The compensation module 300 has a control end, a first end and a second end, the first end of the compensation module 300 is electrically connected to the second end of the driving module 100, the second end of the compensation module 300 is a first node N1, and the control end of the compensation module 300 is accessed by the first emission control signal EMB. The leakage suppression module 400 has a control end, a first end and a second end, the first end of the leakage suppression module 400 is electrically connected to the control end (gate electrode G) of the driving module 100, the second end of the leakage suppression module 400 is electrically connected to the second end (first node N1) of the compensation module 300, and the control end of the leakage suppression module 400 is accessed by the first light emission control signal EMB. The first storage module 500 has a first end and a second end, the first end of the first storage module 500 is electrically connected to the second end (first node N1) of the compensation module 300, and the second end of the first storage module 500 is accessed by the reference voltage signal Vref.

[0020] The driving process of the pixel circuit shown in FIG. 5 includes an initialization stage, a data writing stage, and a light emitting stage. The leakage suppression module 400 and the compensation module 300 are both accessed by the first light emitting control signal EMB, so that the open / close states of both are the same. The first light emitting control signal EMB controls the leakage suppression module 400 and the compensation module 300 to be conductive in the initialization stage and the data writing stage. The first storage module 500 is configured to maintain a voltage difference between the first end of the first storage module 500 and the second end of the first storage module 500 unchanged when the voltage difference is formed between the first end of the first storage module 500 and the second end of the first storage module 500 in the data writing stage and the light emitting stage.

[0021] In the initialization stage, the leakage current suppression module 400 and the compensation module 300 are conductive, and the second end of the driving module 100 and the control end (gate electrode G) of the driving module 100 are conductive. The driving module 100 is in a diode connection mode, and different currents are respectively connected to the first end of the driving module 100 and the second end of the driving module 100. Electrical Signal When the control end (gate electrode G) of the driving module 100 is accessed, for example, when a first power supply signal is accessed to the first end of the driving module 100 and a second power supply signal is accessed to the second end of the driving module 100, the driving module 100 is turned on and a large current flows, which initializes the control end (gate electrode G) of the driving module 100 and at the same time is beneficial to improving the bias state of the driving module 100 and is beneficial to improving the problem of image retention.

[0022] In the data writing stage, the data writing module 200, the leakage suppression module 400 and the compensation module 300 are all conductive, and the data signal Data is written to the control end (gate electrode G) of the driving module 100 through the data writing module 200, the conductive driving module 100, the compensation module 300 and the leakage suppression module 400. Since the leakage suppression module 400 is in a conductive state, the potentials of the control end (gate electrode G) of the driving module 100 and the first node N1 are equal and change synchronously. At the same time, a voltage difference is formed between the first end of the first storage module 500 and the second end of the first storage module 500, the second end of the first storage module 500 is a constant reference voltage signal Vref, and the first end of the first storage module 500 stores the potential of the first node N1. When the potential of the control end (gate electrode G) of the driving module 100 is constant, the potential of the first node N1 also does not change, and a fixed voltage difference is formed between the first end and the second end of the first storage module 500.

[0023] In the light emitting stage, the data writing module 200, the leakage suppression module 400 and the compensation module 300 are all turned off, and the first storage module 500 maintains the voltage difference between the first end of the first storage module 500 and the second end of the first storage module 500 unchanged. And the reference voltage signal Vref with a constant potential is accessed to the second end of the first storage module 500, so the potential of the first end of the first storage module 500 (i.e. the first node N1) is maintained at the potential during the data writing stage. The control end (gate electrode G) of the driving module 100 is also maintained at the potential during the data writing stage, so that the potential of the first end of the leakage suppression module 400 and the potential of the second end of the leakage suppression module 400 are maintained to be equal, and the leakage current of the leakage suppression module 400 is reduced, and the leakage of the control end (gate electrode G) of the driving module 100 is suppressed.

[0024] As can be seen from the above analysis, the embodiment of the present application provides a leakage suppression module 400 between the control end (gate electrode G) of the driving module 100 and the second end (first node N1) of the compensation module 300, and provides a first storage module 500 between the reference voltage signal Vref and the second end (first node N1) of the compensation module 300. In this way, only one leakage current path is provided in the control end (gate electrode G) of the driving module 100, which connects the control end of the driving module 100 and the second end of the driving module 100, and the path is composed of the leakage suppression module 400 and the compensation module 300 controlled by the first light emission control signal. Only after the potential of the second end (first node N1) of the compensation module 300 has drifted significantly, the leakage suppression module 400 generates a large leakage current and the potential of the control end (gate electrode G) of the driving module 100 drifts. In addition, in the embodiment of the present application, since the potential of the control end (gate electrode G) of the driving module 100 is close to the potential of the second end (first node N1) of the compensation module 300, the leakage current of the leakage suppression module 400 is small, and the magnitude of the leakage current of this only leakage path is reduced, so that the potential of the control end (gate electrode G) of the driving module 100 is more stable, a high current holding rate is achieved, and the flicker phenomenon of the display panel is improved.

[0025] The embodiment of the present application makes a breakthrough improvement in the reset path and reset method of the control end (gate electrode G) of the driving module 100, adopts a first memory module 500 instead of a dual-gate transistor to reset the control end (gate electrode G) of the driving module 100, and combines the first memory module 500 with a leakage suppression module 400 to effectively suppress the leakage of the control end (gate electrode G) of the driving module 100, which is advantageous for realizing high-quality display at a low frame rate and for realizing the effect of achieving both low power consumption and high display quality.

[0026] In addition to achieving the above effects, the pixel circuit according to the embodiment of the present application may provide different inputs to the first end of the driving module 100 and the second end of the driving module 100 during the initialization stage. Electrical Signal When the control end (gate electrode G) of the driving module 100 is accessed, for example, when a first power supply signal is accessed at the first end and a second power supply signal is accessed at the second end, the driving module 100 is turned on and a large current can flow, which is beneficial to initializing the control end (gate electrode G) of the driving module 100 and at the same time improving the bias state of the driving module 100, and is beneficial to improving the problem of image retention.

[0027] Hereinafter, the first end and the second end of the driving module 100 are respectively different. Electrical Signal is accessed and the driving module 100 generates a large current.

[0028] 5, in view of the above embodiment, preferably, the pixel circuit further includes a first light-emitting control module 700, a second light-emitting control module 800 and an initialization module 900. The first light-emitting control module 700 includes a control end, a first end and a second end, the first end of the first light-emitting control module 700 is electrically connected to the first end (second node N2) of the driving module 100, the second end of the first light-emitting control module 700 is accessed by a first power supply signal VDD, and the control end of the first light-emitting control module 700 is accessed by a second light-emitting control signal EM. The second light-emitting control module 800 has a control end, a first end and a second end, the control end of the second light-emitting control module 800 is accessed by a second light-emitting control signal EM, the first end of the second light-emitting control module 800 is electrically connected to the second end (third node N3) of the driving module 100, and the second end of the second light-emitting control module 800 is electrically connected to the light-emitting element OLED. The light-emitting element OLED has an anode and a cathode. Exemplarily, the second end of the second light-emitting control module 800 is electrically connected to the anode of the light-emitting element OLED, and the cathode of the light-emitting element OLED is accessed by a second power signal VSS.

[0029] The initialization module 900 has a control end, a first end and a second end, the control end of the initialization module 900 receives the second scanning signal S2, the first end of the initialization module 900 is electrically connected to the second end of the second light-emitting control module 800, and the second end of the initialization module 900 receives the initialization signal S2. Preferably, the reference voltage signal Vref is also used as the initialization signal.

[0030] In the initialization stage, the leakage suppression module 400 and the compensation module 300 are conductive, and the driving module 100 is in a diode-connected manner. And the first light-emitting control module 700, the second light-emitting control module 800 and the initialization module 900 are simultaneously conductive. The first power signal VDD is written to the first end (second node N2) of the driving module 100 through the first light-emitting control module 700, and the second power signal VSS is written to the second end (third node N3) of the driving module 100 through the second light-emitting control module 800, so that the driving module 100 is conductive and generates a large current. The current flows out through the initialization module 900 and does not flow through the light-emitting element OLED, which can initialize the anode of the light-emitting element OLED and also avoids the light-emitting element OLED from being conductive during the initialization stage.

[0031] As can be seen from this, the pixel circuit according to the embodiment of the present application controls the driving module to generate a large current in the initialization stage, and enables the generated large current to flow through the initialization module 900, which initializes the control end (gate electrode G) of the driving module 100 and the anode of the light-emitting element OLED, and is also beneficial to improving the bias state of the driving module 100 and improving the problem of image retention.

[0032] Continuing to refer to FIG. 5, in view of the above embodiment, preferably, the pixel circuit further includes a second storage module 600. The second storage module 600 includes a first end and a second end, the first end of the second storage module 600 is electrically connected to the control end (gate electrode G) of the driving module 100, and the second end of the second storage module 600 is accessed by a first power supply signal VDD. The second storage module 600 has a function of storing an electric potential, and is configured to keep the electric potential of the control end of the driving module 100 unchanged in the light-emitting stage. In this way, the first memory module 500 and the second memory module 600 work together, the first memory module 500 maintains the potential of the first node N1 unchanged, and the second memory module 600 maintains the potential of the control end (gate electrode G) of the driving module 100 unchanged, thereby maintaining the potentials of the first node N1 and the gate electrode G to be equal, which is more advantageous in reducing the leakage current of the control end (gate electrode G) of the driving module 100, achieving a high current retention rate, and improving the flicker phenomenon of the display panel.

[0033] With reference to FIG. 6 and based on the above embodiment, the embodiment of the present application will describe a method of installing transistors in multiple modules.

[0034] In one embodiment of the present application, the compensation module 300 preferably includes a first transistor M1. A first pole of the first transistor M1 is electrically connected to the second end (third node N3) of the driving module 100, a second pole of the first transistor M1 is electrically connected to the second end (first node N1) of the leakage suppression module 400, and a first light emission control signal EMB is accessed to the gate electrode of the first transistor M1. The embodiment of the present application provides the compensation module 300 with only one transistor, and the circuit structure is simple and easy to implement.

[0035] Continuing to refer to FIG. 6, in one embodiment of the present application, the leakage suppression module 400 preferably includes a second transistor M2. A first pole of the second transistor M2 is electrically connected to the control end (gate electrode G) of the driving module 100, a second pole of the second transistor M2 is electrically connected to the second end (first node N1) of the compensation module 300, and the gate electrode of the second transistor M2 is accessed by the first light emission control signal EMB. In the embodiment of the present application, the leakage suppression module 400 is configured to include only one transistor, and the circuit structure is simple and easy to realize.

[0036] Continuing to refer to FIG. 6, in one embodiment of the present application, the data writing module 200 preferably includes a third transistor M3. The first pole of the third transistor M3 is electrically connected to the first end (second node N2) of the driving module 100, the second pole of the third transistor M3 is accessed by the data signal Data, and the gate electrode of the third transistor M3 is accessed by the first scanning signal S1. The embodiment of the present application provides the data writing module 200 with only one transistor, so that the number of transistors required for the pixel circuit is small.

[0037] Continuing to refer to FIG. 6, in one embodiment of the present application, the first light-emitting control module 700 preferably includes a fifth transistor M5. The first pole of the fifth transistor M5 is electrically connected to the first end (second node N2) of the driving module 100, the second pole of the fifth transistor M5 is accessed by the first power signal VDD, and the gate electrode of the fifth transistor M5 is accessed by the second light-emitting control signal EM. In the embodiment of the present application, the first light-emitting control module 700 is configured to include only one transistor, and the circuit structure is simple and easy to implement.

[0038] Continuing to refer to FIG. 6, in one embodiment of the present application, the second light-emitting control module 800 preferably includes a sixth transistor M6. The first pole of the sixth transistor M6 is electrically connected to the second end of the driving module 100, the second pole of the sixth transistor M6 is electrically connected to the light-emitting element OLED, and the gate electrode of the sixth transistor M6 is accessed by the second light-emitting control signal EM. In the embodiment of the present application, the second light-emitting control module 800 is configured to include only one transistor, and the circuit structure is simple and easy to implement.

[0039] Continuing to refer to FIG. 6, in one embodiment of the present application, the initialization module 900 preferably includes a seventh transistor M7. The first pole of the seventh transistor M7 is electrically connected to the second end of the second light-emitting control module 800, the second pole of the seventh transistor M7 is accessed by the initialization signal, and the gate electrode of the seventh transistor M7 is accessed by the second scanning signal S2. In the embodiment of the present application, the initialization module 900 is configured to include only one transistor, and the circuit structure is simple and easy to implement.

[0040] 6, in one embodiment of the present application, the first storage module 500 preferably comprises a first capacitor C1. The first pole of the first capacitor C1 is electrically connected to the second end (first node N1) of the compensation module 300, and the second pole of the first capacitor C1 is accessed by the reference voltage signal Vref. The embodiment of the present application provides the first storage module 500 with only one capacitor, so that the circuit structure is simple and easy to implement.

[0041] Continuing to refer to FIG. 6, in one embodiment of the present application, the second storage module 600 preferably includes a second capacitor C2. The first pole of the second capacitor C2 is electrically connected to the control end (gate electrode G) of the driving module 100, and the second pole of the second capacitor C2 is accessed by the first power supply signal VDD. The embodiment of the present application provides the second storage module 600 with only one capacitor, and the circuit structure is simple and easy to implement.

[0042] 6 shows an example in which all the transistors in the pixel circuit are P-type transistors and are manufactured by an LTPS process, but this is not intended to limit the present application. In other embodiments, some or all of the transistors in the pixel circuit may be N-type transistors, and may be set as required in practical applications.

[0043] 6 shows the first transistor M1 and the second transistor M2 as single-gate transistors for illustrative purposes only and is not intended to be limiting of the present application, in other embodiments, the first transistor M1 and / or the second transistor M2 may be provided as dual-gate transistors.

[0044] 7, the difference from the above embodiment is that the data writing module 200 further includes a synchronous control end, to which the first light emitting control signal EMB is accessed, and the data writing module 200 transmits the data signal Data under the joint control of the first scanning signal S1 and the first light emitting control signal EMB. Preferably, the data writing module 200 further includes a fourth transistor M4. The gate electrode of the fourth transistor M4 is accessed by the first light emitting control signal EMB, and the fourth transistor M4 is connected in series between the first pole of the third transistor M3 and the first end (second node N2) of the driving module 100. The embodiment of the present application is provided in this manner in order to reduce the number of via holes in the layout, without affecting other functions of the pixel circuit.

[0045] 7 and 8, the layout of the pixel circuit includes a first scanning line, a first light-emitting control signal line, a second light-emitting control signal line and a second scanning line extending along a first direction X and located in a first metal layer. The first scanning line transmits a first scanning signal S1, the first light-emitting control signal line transmits a first light-emitting control signal EMB, the second light-emitting control signal line transmits a second light-emitting control signal EM, and the second scanning line transmits a second scanning signal S2.

[0046] The pixel circuit layout further comprises a reference voltage signal line extending along the first direction X and located in the second metal layer, the reference voltage signal line carrying a reference voltage signal Vref.

[0047] The pixel circuit layout further includes a data line and a first power signal line extending along the second direction Y and located in a third metal layer, the data line transmitting a data signal Data, and the first power signal line transmitting a first power signal VDD.

[0048] The pixel circuit layout further includes a semiconductor pattern located in the active layer, where transistors are formed at locations where the semiconductor pattern intersects with a plurality of signal lines located in the first metal layer, and an S-shaped portion of the semiconductor pattern intersects with the first metal layer to form a drive transistor MD.

[0049] A third transistor M3 is formed at the intersection of the semiconductor pattern and the first scan line. The intersection of the first scan line and the semiconductor pattern is the gate electrode of the third transistor M3, i.e., the gate electrode of the third transistor M3 is electrically connected to the first scan line. The portions of the semiconductor pattern located on both sides of the first scan line are the first pole and the second pole of the third transistor M3, the second pole of the third transistor M3 is connected to the data line by the via hole 110, and the first pole of the third transistor M3 is electrically connected to the second pole of the fourth transistor M4.

[0050] At the intersection of the semiconductor pattern and the first light emission control signal line, a fourth transistor M4, a second transistor M2, and a first transistor M1 are formed. The gate electrode of the fourth transistor M4 is electrically connected to the first light emission control signal line, the first electrode of the fourth transistor M4 is electrically connected to the first electrode of the driving transistor MD, and the second electrode of the fourth transistor M4 is electrically connected to the first electrode of the third transistor M3. The gate electrode of the first transistor M1 is electrically connected to the first light emission control signal line, the first electrode of the first transistor M1 is electrically connected to the second electrode of the driving transistor MD, and the second electrode of the first transistor M1 is electrically connected to the second electrode of the second transistor M2. The gate electrode of the second transistor M2 is electrically connected to the first light emission control signal line, the first electrode of the second transistor M2 is connected to the gate electrode of the driving transistor MD through a via hole 110 and a connecting line 120, and the second electrode of the second transistor M2 is electrically connected to the second electrode of the first transistor M1. Exemplarily, the connecting line 120 is located in the third metal layer.

[0051] A fifth transistor M5 and a sixth transistor M6 are formed at a position where the semiconductor pattern intersects with the second light emission control signal line. The gate electrode of the fifth transistor M5 is electrically connected to the second light emission control signal line, the first electrode of the fifth transistor M5 is electrically connected to the first electrode of the driving transistor MD, and the second electrode of the fifth transistor M5 is connected to the first power supply signal line by a via hole 110. The gate electrode of the sixth transistor M6 is electrically connected to the second light emission control signal line, the first electrode of the sixth transistor M6 is electrically connected to the second electrode of the driving transistor MD, and the second electrode of the sixth transistor M6 is electrically connected to the anode 130 of the light emitting element by the via hole 110.

[0052] A seventh transistor M7 is formed at the intersection of the semiconductor pattern and the second scan line. The gate electrode of the seventh transistor M7 is electrically connected to the second scan line, the first electrode of the seventh transistor M7 is electrically connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the reference voltage signal line through a via hole 110 and a connection line 120.

[0053] The gate electrode of the drive transistor MD is the first electrode plate of the second capacitor C2, and the second electrode plate of the second capacitor C2 may be provided on the third metal layer and directly connected to the first power supply signal line, or may be provided on the second metal layer and electrically connected to the first power supply signal line by providing a via hole 110.

[0054] The plate of the first pole of the first capacitor C1 is located on the second metal layer and is connected to the second pole of the first transistor M1 by a via hole 110 and a connection line 120. The plate of the second pole of the first capacitor C1 is located on the third metal layer and is connected to the reference voltage signal line by a via hole 110 and a connection line 120. Alternatively, the plate of the first pole of the first capacitor C1 is located on the third metal layer and is connected to the second pole of the first transistor M1 by a via hole 110 and a connection line 120. The plate of the second pole of the first capacitor C1 is located on the second metal layer and is directly connected to the reference voltage signal line.

[0055] Therefore, from the layout shown in FIG. 8, it can be seen that under the third transistor M3, the semiconductor pattern and the first light emission control signal line naturally form the fourth transistor M4, and the presence of the fourth transistor M4 does not affect the function of the pixel circuit. However, if M4 is not provided, it is necessary to interrupt the semiconductor pattern to provide a via hole and a connection line so that the semiconductor pattern straddles the first light emission control signal line, or to interrupt the first light emission control signal line to provide a via hole and a connection line so that the first light emission control signal line straddles the semiconductor pattern. Therefore, the embodiment of the present application realizes a reduction in the number of via holes in the layout by adding the fourth transistor M4 to the pixel circuit, on the premise that it does not affect other functions of the pixel circuit.

[0056] As can be seen, the embodiment of the present application provides a pixel circuit with an 8T2C structure, and in terms of layout, comparing Fig. 2 with Fig. 8, compared with the 7T1C pixel circuit of the related art, the 8T2C pixel circuit of the embodiment of the present application does not add any new signal lines. Comparing Fig. 4 with Fig. 8, compared with the 8T1C circuit of the related art, the 8T2C pixel circuit of the embodiment of the present application has a reduced number of signal lines extending along one first direction X, so that the embodiment of the present application is advantageous in saving wiring space and improving the design of the number of pixels per inch (PPI).

[0057] In view of the above, the embodiments of the present application include at least the following effects.

[0058] First, a high current holding ratio is achieved, which improves the flicker phenomenon in the display panel and is advantageous for achieving high-quality display at low frame rates, thereby achieving the effect of achieving both low power consumption and high display quality.

[0059] Secondly, it is advantageous for improving the bias state of the drive transistor MD while initializing the gate electrode G of the drive transistor MD, and is advantageous for improving the problem of residual images.

[0060] Third, it is advantageous for saving wiring space and for realizing a high PPI design.

[0061] The embodiments of the present application further provide a display panel, which includes a pixel circuit according to any embodiment of the present application and has corresponding effects, which will not be described again.

[0062] The embodiments of the present application further provide a driving method for a pixel circuit, which can be applied to the pixel circuit according to any embodiment of the present application and has corresponding effects. Referring to Figures 7 and 9, the driving method for a pixel circuit includes:

[0063] In S110, in the initialization stage, the first light emission control signal EMB is respectively provided to the first end of the driving module 100 and the second end of the driving module 100. Electrical Signal When accessed, it controls the compensation module 300 and the leakage current suppression module 400 to be conductive so as to initialize the driving module 100 by making it conductive.

[0064] In S120, in the data writing stage, the first light emitting control signal EMB controls the compensation module 300 and the leakage suppression module 400 to be conductive, the first scanning signal S1 controls the data writing module 200 to be conductive so as to write the data signal Data to the control end of the driving module 100, the potentials of the first end of the first memory module 500 and the control end of the driving module 100 are equal, and a voltage difference is formed between the first end of the first memory module 500 and the second end of the first memory module 500.

[0065] In S130, in the light emitting stage, the first light emitting control signal EMB controls the compensation module 300 and the leakage current suppression module 400 to be turned off, the first scanning signal S1 controls the data writing module 200 to be turned off, and the first memory module 500 maintains the voltage difference between the first end of the first memory module 500 and the second end of the first memory module 500 unchanged, so as to make the potentials of the first end and the second end of the leakage current suppression module 400 equal.

[0066] In light of the above embodiment, preferably, the initialization stage includes a first initialization sub-stage and a second initialization sub-stage.

[0067] In the first initialization sub-phase, the first emission control signal EMB controls the compensation module 300 and the leakage suppression module 400 to be conductive, the second emission control signal EM controls the first emission control module 700 and the second emission control module 800 to be conductive, and the second scanning signal S2 controls the initialization module 900 to be conductive so as to make the driving module 100 conductive, and the generated driving current flows out through the initialization module 900. The driving module 100 is made conductive, and a large current flows, which initializes the control end (gate electrode G) of the driving module 100 and is at the same time beneficial to improving the bias state of the driving module 100 and beneficial to improving the problem of image retention.

[0068] In the second initialization sub-stage, the second light-emitting control signal EM controls the first light-emitting control module 700 and the second light-emitting control module 800 to be turned off, and the reference voltage signal Vref continues to initialize the anode of the light-emitting element OLED.

[0069] 10 is a schematic diagram of a time sequence of driving one pixel circuit according to an embodiment of the present application. The driving process of the pixel circuit will be described below with reference to FIGS.

[0070] In the first initialization sub-stage t11, the second scanning signal S2, the first emission control signal EMB and the second emission control signal EM are at low level, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are conductive, the gate electrode G of the driving transistor MD and the anode of the light-emitting element OLED are reset simultaneously, and the reference voltage signal Vref is written to the gate electrode G of the driving transistor MD. At this time, a large current flows through the driving transistor MD, which is advantageous to improve the bias state of the driving transistor MD and improve the problem of image retention.

[0071] The second initialization sub-stage t12 is different from the first initialization stage t11 in that the second light emission control signal EM changes from low level to high level, the fifth transistor M5 and the sixth transistor M6 are turned off, and the driving transistor MD does not generate a large current. The potential of the gate electrode G is held by the first capacitor C1, and the reference voltage signal Vref continues to initialize the anode of the light emitting element OLED.

[0072] In the data write stage t2, the second scanning signal S2 is at a high level, and the seventh transistor M7 is turned off. The first scanning signal S1 and the first light emission control signal EMB are at a low level, the third transistor M3, the fourth transistor M4, the first transistor M1, and the second transistor M2 are conductive, and the data signal Data is written to the gate electrode G and the first node N1 through the third transistor M3, the fourth transistor M4, the driving transistor MD, the first transistor M1, and the second transistor M2, that is, written to the first capacitor C1 and the second capacitor C2. Since the reference voltage signal Vref is lower than the voltage of the data signal Data, the potential of the gate electrode G gradually rises in the data write stage t2.

[0073] In the light-emitting stage t3, the first scanning signal S1 and the first light-emitting control signal EMB are at high level, and the third transistor M3, the fourth transistor M4, the first transistor M1 and the second transistor M2 are turned off. The second light-emitting control signal EM is at low level, and the fifth transistor M5 and the sixth transistor M6 are turned on, and the light-emitting element OLED is turned on. Meanwhile, the first capacitor C1 and the second capacitor C2 latch the potentials of the first node N1 and the gate electrode G. Since the potentials of the first node N1 and the gate electrode G are very close, the leakage current of the second transistor M2 is very small, so that the potential of the gate electrode G is more stable, and the flicker problem of the display panel is improved.

[0074] Still referring to FIG. 10, stage t0 is the initial state and is considered to be the emission stage of the previous frame.

[0075] 10 exemplarily shows that a first transition step is further included between the second initialization sub-step t12 and the data writing step t2. In the first transition step, the second scanning signal S2 changes from a low level to a high level, and the first light emission control signal EMB changes from a low level to a high level, which is not a limitation of the present application. In another embodiment, the first transition step may not be provided, the second scanning signal S2 changes from a low level to a high level in the data writing step t2, and the first light emission control signal EMB may be held at a low level in the initialization step and the data writing step t2.

[0076] 10 exemplarily illustrates that a second transition step is further included between the data writing step t2 and the light emitting step t3. In the second transition step, the first scanning signal S1 and the first light emitting control signal EMB change from a low level to a high level, which is not a limitation of the present application. In other embodiments, the second transition step is not provided, and the first scanning signal S1 and the first light emitting control signal EMB may change from a low level to a high level in the light emitting step t3.

Claims

1. a drive module having a control end, a first end and a second end; a data writing module, the data writing module having a scanning control end through which a first scanning signal is accessed, a first end electrically connected to the first end of the driving module, and a second end through which a data signal is accessed; a compensation module having a control end through which a first light emission control signal is accessed, a first end electrically connected to the second end of the driving module, and a second end; a leakage current suppression module, the leakage current suppression module having a control end through which the first light emission control signal is accessed, a first end electrically connected to the control end of the driving module, and a second end electrically connected to the second end of the compensation module, the leakage current suppression module being electrically connected to the compensation module during an initialization phase and a data writing phase; a first storage module having a first end electrically connected to the second end of the compensation module and a second end through which a reference voltage signal is accessed, the first storage module being configured to maintain a voltage difference unchanged when a voltage difference is formed between the first end of the first storage module and the second end of the first storage module during the data writing phase and the light emitting phase; A pixel circuit comprising: The data writing module includes: a synchronous control terminal through which the first light emission control signal is accessed; a third transistor having a second pole connected to the data signal and a gate electrode connected to the first scanning signal; a fourth transistor, the first pole of which is electrically connected to the first end of the driving module, the second pole of which is electrically connected to the first pole of the third transistor, and the gate electrode of which is accessed by the first light emission control signal; Further equipped with The data signal is transmitted under joint control of the first scanning signal and the first light emission control signal; Pixel circuit.

2. The compensation module includes: a first transistor, the first pole of which is electrically connected to the second end of the driving module, the second pole of which is electrically connected to the second end of the leakage current suppression module, and the first light emission control signal is accessed at a gate electrode of the first transistor; and / or The leakage current suppression module includes: a second transistor, the first pole of which is electrically connected to the control end of the driving module, the second pole of which is electrically connected to the second end of the compensation module, and the gate electrode of which is accessed by the first light emission control signal; The pixel circuit of claim 1 .

3. The first storage module includes: a first capacitor having a first pole electrically connected to the second end of the compensation module and a second pole to which the reference voltage signal is applied; and / or The data writing module includes: a third transistor, the third transistor having a first pole electrically connected to the first end of the driving module, a second pole to which the data signal is applied, and a gate electrode to which the first scanning signal is applied; The pixel circuit of claim 1 .

4. a second storage module having a first end electrically connected to the control end of the driving module, a second end to which a first power supply signal is accessed, and a second capacitor having a first pole electrically connected to the control end of the driving module and a second pole to which the first power supply signal is accessed, the second storage module being configured to keep the potential of the control end of the driving module unchanged during the light emission phase; The pixel circuit of claim 1 .

5. a first light-emitting control module, the first light-emitting control module having a control end through which a second light-emitting control signal is accessed, a first end electrically connected to the first end of the driving module, and a second end through which a first power supply signal is accessed; a second light-emitting control module, the second light-emitting control module having a control end through which the second light-emitting control signal is accessed, a first end electrically connected to the second end of the driving module, and a second end electrically connected to a light-emitting element; an initialization module having a control end through which a second scanning signal is accessed, a first end electrically connected to the second end of the second light-emitting control module, and a second end through which an initialization signal is accessed; Further equipped with The first light-emitting control module, the second light-emitting control module and the initialization module are simultaneously conducted during the initialization stage; The first light emission control module includes: a fifth transistor, the fifth transistor having a first pole electrically connected to the first end of the driving module, a second pole to which the first power supply signal is connected, and a gate electrode to which the second light emission control signal is connected; and / or The second light-emitting control module includes a sixth transistor, the first pole of which is electrically connected to the second end of the driving module, the second pole of which is electrically connected to the light-emitting element, and the gate electrode of which is accessed by the second light-emitting control signal; and / or The initialization module includes: a seventh transistor, the first pole of which is electrically connected to the second end of the second light-emitting control module, the second pole of which is connected to the initialization signal, and the gate electrode of which is connected to the second scanning signal; and / or The light-emitting element has an anode electrically connected to the second end of the second light-emitting control module, and a cathode to which a second power signal is accessed; The pixel circuit of claim 1 .

6. The reference voltage signal is also used as the initialization signal. The pixel circuit of claim 5.

7. A pixel circuit according to any one of claims 1 to 6, Display panel.

8. A driving method for a pixel circuit, comprising: a driving module, a leakage suppression module, a data writing module, a compensation module, and a first storage module, wherein the data writing module has a first end electrically connected to a first end of the driving module, a second end to which a data signal is accessed, and a control end to which a first scanning signal is accessed; the compensation module has a first end electrically connected to a second end of the driving module, and a first light-emitting control signal is accessed at the control end; the leakage suppression module has a first end electrically connected to the control end of the driving module, a second end electrically connected to the second end of the compensation module, and the first light-emitting control signal is accessed at the control end; and the first storage module has a first end electrically connected to the second end of the compensation module, and a reference voltage signal is accessed at the second end, In an initialization stage, when the first end of the driving module and the second end of the driving module are accessed with different electrical signals, the first light emission control signal controls the compensation module and the leakage current suppression module to be conductive, so as to make the driving module conductive and initialize it; In a data writing step, the first light emitting control signal controls the compensation module and the leakage current suppression module to be conductive, the first scanning signal controls the data writing module to be conductive, so as to write the data signal into the control end of the driving module, the potentials of the first end of the first storage module and the control end of the driving module are equal, and a voltage difference is formed between the first end of the first storage module and the second end of the first storage module; In a light emitting stage, the first light emitting control signal controls the compensation module and the leakage current suppression module to be turned off, the first scanning signal controls the data writing module to be turned off, and the first storage module maintains a voltage difference between the first end of the first storage module and the second end of the first storage module unchanged, so as to make the potential of the first end of the leakage current suppression module and the second end of the leakage current suppression module equal; Including, The pixel circuit further includes: a first light-emitting control module, the first end of which is electrically connected to the first end of the driving module, the second end of which is connected to a first power supply signal, and the control end of which is connected to a second light-emitting control signal; a second light-emitting control module, the first end of which is electrically connected to the second end of the driving module, the second end of which is electrically connected to a light-emitting element, and the control end of which is connected to the second light-emitting control signal; and an initialization module, the first end of which is electrically connected to the second end of the second light-emitting control module, the second end of which is connected to an initialization signal, and the control end of which is connected to a second scanning signal; The initialization step includes a first initialization sub-step and a second initialization sub-step, in which in the first initialization sub-step, the first emission control signal controls the compensation module and the leakage suppression module to be conductive, the second emission control signal controls the first emission control module and the second emission control module to be conductive, the second scanning signal controls the initialization module to be conductive, the reference voltage signal initializes the gate electrode of the driving transistor and the anode of the light-emitting element, in the second initialization sub-step, the second emission control signal controls the first emission control module and the second emission control module to be off, and the reference voltage signal initializes the anode of the light-emitting element; The driving method includes: In the data writing step, the second scanning signal controls the initialization module to be turned off, and the first scanning signal controls the data writing module to be conductive; In the light emitting step, the first scanning signal controls the data writing module to be turned off, the first light emitting control signal controls the compensation module and the leakage suppression module to be turned off, and the second light emitting control signal controls the first light emitting control module and the second light emitting control module to be conductive; a first transitional phase is further included between the second initialization subphase and the data writing phase; The driving method includes: In the first transition phase, the second scanning signal controls the initialization module to be turned off, and the first light emission control signal controls the compensation module and the leakage current suppression module to be turned off; and / or a second transition step is included between the data writing step and the light emitting step; The driving method includes: In the second transition phase, the first scanning signal controls the data writing module to be turned off, and the first light emission control signal controls the compensation module and the leakage current suppression module to be turned off. A method for driving a pixel circuit.

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