Interrupt simulation device, interrupt simulation method, and interrupt simulation program

Abstract

An interruption simulation device (10) is provided with an accumulative addition unit (14) and a branch addition unit (15). The accumulative addition unit (14) uses, as a target basic block, each of a plurality of basic blocks obtained by dividing a target program (20) being a computer program, to add an accumulative addition process of adding a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program (20) when the target basic block is executed in the target program (20). The branch addition unit (15) adds, to the target program (20), a conditional branch process to be executed when the value of the counter variable satisfies a trigger condition.

Description

[Technical field]

[0001] The present disclosure relates to an interrupt simulation device, an interrupt simulation method, and an interrupt simulation program. [Background technology]

[0002] In the development of embedded programs, there are cases where the development of the embedded program is carried out in a situation where the actual device that will be the operating environment of the embedded program cannot be prepared at hand. In addition, since real-time performance is often required for embedded programs, it is important to estimate the execution time of the embedded program from the early development stage. When the actual device cannot be prepared at the early development stage, it is common to estimate the execution time of the embedded program using an emulator or simulator. However, when an emulator or simulator is used, there is a problem that it takes a long time to estimate the execution time of an embedded program because of the execution time overhead caused by the emulation or simulation. As a method for solving this problem, Patent Document 1 presents a method for estimating the execution time of an embedded program without using an emulator or simulator by using a program analysis technique by a compiler. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2010 / 001766 Brochure Summary of the Invention [Problem to be solved by the invention]

[0004] Some embedded programs use interrupts. An interrupt is a mechanism that executes a pre-specified process when an interrupt event occurs. An interrupt event is an external event such as a timer firing. Here, the method presented in Patent Document 1 has a problem that it is not possible to estimate the execution time of a program that handles interrupts because it does not have a mechanism for simulating an interrupt event. When using this method to estimate the execution time of an embedded program that handles interrupts, a problem occurs in the branch history information generation process shown in FIG. 3 of Patent Document 1. As a specific example, consider a case where the value of variable X is changed when a timer fires, and the main process waits until the value of variable X changes. In this case, the branch history information generation process cannot simulate the timer firing event, so the main process does not execute the processes after the wait process. Therefore, in this case, the expected execution time estimate cannot be obtained. The present disclosure aims to realize simulation of a timer interrupt event without using an emulator or simulator by utilizing a program analysis technique using a compiler. Here, a timer interrupt event is an interrupt event triggered by firing of a timer. [Means for solving the problem]

[0005] The interrupt simulator according to the present disclosure comprises: an accumulation adding unit which, when a target program which is a computer program is divided into a plurality of basic blocks, treats each basic block of the plurality of basic blocks as a target basic block, and adds an accumulation addition process which adds a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program when the target basic block is executed in the target program; a branch addition unit that adds a conditional branch process to the target program, the conditional branch process being executed when the value of the counter variable satisfies an ignition criteria condition; Equipped with. Effect of the Invention

[0006] When a target program processed according to the present disclosure is executed, the cumulative execution time of the target program is managed using a counter variable, and a conditional branch process is executed when the value of the counter variable satisfies an ignition criterion condition. Here, the conditional branch process corresponds to a timer interrupt event, and the cumulative execution time is the cumulative estimated execution time of each basic block. Each basic block may be divided by utilizing a program analysis technique by a compiler. Therefore, according to the present disclosure, by utilizing the program analysis technique by a compiler, it is possible to simulate a timer interrupt event without using an emulator or a simulator. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram showing an example of the configuration of an interrupt simulator 10 according to a first embodiment. [Diagram 2] FIG. 4 is a diagram for explaining a processed program 29 according to the first embodiment. [Diagram 3] 1 is a diagram showing an example of a hardware configuration of an interrupt simulator 10 according to a first embodiment. [Figure 4] 4 is a flowchart showing the operation of a definition adding unit 13 according to the first embodiment. [Diagram 5] FIG. 2 is a diagram for explaining a target program 21 according to the first embodiment. [Figure 6] 4 is a flowchart showing the operation of a storage adding unit 14 according to the first embodiment. [Figure 7] 4 is a flowchart showing the operation of the branch adding unit 15 according to the first embodiment. [Figure 8] 3 is a diagram for explaining a setting file 28 and a processed program 29 according to the first embodiment. FIG. [Figure 9] FIG. 13 is a diagram showing an example of a hardware configuration of an interrupt simulator 10 according to a modification of the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the description of the embodiments and the drawings, the same elements and corresponding elements are given the same reference numerals. Descriptions of elements given the same reference numerals are omitted or simplified as appropriate. Arrows in the drawings primarily indicate data flow or processing flow. In addition, "part" may be read as "circuit," "step," "procedure," "processing," or "circuitry" as appropriate.

[0009] Embodiment 1 Hereinafter, the present embodiment will be described in detail with reference to the drawings.

[0010] ***Configuration Description*** 1 shows an example of a software configuration of an interrupt simulator 10. As shown in FIG. 1, the interrupt simulator 10 includes a division unit 11, an estimation unit 12, a definition addition unit 13, an accumulation addition unit 14, and a branch addition unit 15. The division unit 11 and the estimation unit 12 execute a static estimation process to statically estimate the execution time of each basic block included in the target program 20. The target program 20 is a computer program. In this specification, a computer program will be simply referred to as a "program". The definition adding unit 13, the accumulation adding unit 14, and the branch adding unit 15 add a process for simulating a timer interrupt event to the target program 20 based on the result of the static estimation process and the setting file 28. The setting file 28 is, as a specific example, a file created by the user.

[0011] The division unit 11 is a software module that receives a target program 20 as input, divides the received target program 20 into a plurality of basic blocks, and outputs a basic block set consisting of the plurality of divided basic blocks. The target program 20 is a program whose execution time is to be measured, and as a specific example, is an embedded program. The division unit 11 divides the target program 20 into a plurality of basic blocks using a known algorithm. As a specific example, the algorithm is provided as a function of the open source compiler platform LLVM (Low Level Virtual Machine).

[0012] The estimation unit 12 is a software module that receives a set of basic blocks as input, estimates the execution time for each element of the received set of basic blocks, and outputs the estimated execution time. A specific example of an algorithm for estimating execution time is disclosed in Patent Document 1.

[0013] The definition adding unit 13 is a software module that adds a counter variable to the target program 20. Here, the counter variable is a variable that corresponds to the accumulated execution time of the target program 20, and is a global variable that holds the accumulated value of the current estimated execution time during the execution of the target program 20.

[0014] The accumulation addition unit 14 is a software module that adds an accumulation addition process to a counter variable on a basic block basis. That is, when a target program is divided into a plurality of basic blocks, the accumulation addition unit 14 sets each basic block of the plurality of basic blocks as a target basic block, and adds an accumulation addition process corresponding to the target basic block in the target program. The accumulation addition process is a process of adding a value corresponding to the estimated execution time of the target basic block to the counter variable when the target basic block is executed. The accumulation addition process accumulates a cumulative value of the current estimated execution time required to simulate the firing of a timer. The target program is a collective term for the target program 20, the target program 21, and the target program 22. The target program 22 is the target program 21 to which the accumulation addition process has been added by the accumulation addition unit 14. The target program 21 is the target program 20 to which the definition of the counter variable has been added by the definition addition unit 13. The accumulation adding unit 14 may add an accumulation addition process corresponding to the target basic block to the end of the target basic block.

[0015] The branch addition unit 15 is a software module that adds a conditional branch process for simulating a timer interrupt event based on the configuration file 28. The conditional branch process may be a process that is executed when the value of a counter variable satisfies a firing criterion condition. The firing criterion condition may be any condition. The firing criterion condition may be a condition indicated by the configuration file 28, that is, a condition that is set externally. The branch addition unit 15 also outputs a program in which the conditional branch process has been added to the target program as a processed program 29. The branch addition unit 15 may add a conditional branch processing to the end of a basic block corresponding to the conditional branch processing. A timer interrupt event can be simulated by executing the modified program 29 on a computer having the hardware configuration shown in Fig. 3. In the modified program 29, a basic block is a partial instruction sequence of a program having only one branch instruction at the end. In the modified program 29, an estimated execution time of each basic block passed during execution of the target program 20 is accumulated, thereby making it possible to simulate a timer interrupt event based on the estimated execution time.

[0016] FIG. 2 is a diagram for explaining the processed program 29. As shown in FIG. 2 does not have a mechanism for simulating a timer interrupt event. Therefore, even if the target program 20 is executed on a computer, the process after the while statement corresponding to waiting for completion of TimerHandler is not executed. On the other hand, the interrupt simulator 10 processes the target program 20 to generate a processed program 29 in which a simulation process of a timer interrupt event based on the configuration file 28 is added to the target program 20. When the processed program 29 is executed on a computer, the process following the while statement corresponding to waiting for completion of the TimerHandler is also executed.

[0017] 3 is a diagram showing an example of a hardware configuration of the interrupt simulator 10. The interrupt simulator 10 is a computer, and includes a processor 51, a memory 52, a secondary storage device 53, an input device 54, an output device 55, and a bus 59 as hardware components. The processor 51 is a hardware unit that performs calculations and control based on instructions written in a program, and is, for example, a CPU (Central Processing Unit). The interrupt simulator 10 may include multiple processors that replace the processor 51. The multiple processors share the role of the processor 51. The memory 52 is a volatile storage device, and is a hardware unit that stores programs and data. A specific example of the memory 52 is a random access memory (RAM). The secondary storage device 53 is a non-volatile storage device, and is a hardware unit that stores the interrupt simulation program and the setting file 28. Specific examples of the secondary storage device 53 include a hard disk drive (HDD) and a solid state drive (SSD). The input device 54 is a hardware unit for a user to input to the system, and is exemplified by a keyboard and a mouse. The output device 55 is a hardware unit for transmitting the processing result from the system to a user. A specific example of the output device 55 is a display. These hardware units are interconnected via a bus 59 .

[0018] The secondary storage device 53 stores an interrupt simulation program. The interrupt simulation program is a program that causes a computer to realize the functions of each unit of the interrupt simulation device 10. The functions of each unit of the interrupt simulation device 10 are realized by software. The interrupt simulation program may be recorded on a non-volatile recording medium that is readable by a computer. Specific examples of the non-volatile recording medium include an optical disk or a flash memory. The interrupt simulation program may be provided as a program product. Processor 51 reads out the interrupt simulation program stored in memory 52, and executes calculations, control, etc. according to the instructions written in the interrupt simulation program. If the instruction is a memory read / write instruction, processor 51 executes reading / writing of data from / to the corresponding area of ​​memory 52. ​​If the instruction is a file read / write instruction, processor 51 executes reading / writing of a file from / to the corresponding area of ​​secondary storage device 53. If the instruction is an input instruction, processor 51 acquires data from input device 54, and writes the acquired data to memory 52. ​​If the instruction is an output instruction, processor 51 acquires data to be output from memory 52, and outputs the acquired data to be output to output device 55.

[0019] ***Explanation of Operation*** The operation procedure of the interrupt simulator 10 corresponds to an interrupt simulator method, and the program that realizes the operation of the interrupt simulator 10 corresponds to an interrupt simulator program.

[0020] 4 is a flowchart showing an example of the process of the definition adding unit 13. The process of the definition adding unit 13 will be described with reference to FIG.

[0021] (Step S101) The definition adding unit 13 receives the target program 20 as an input, and adds a definition of a counter variable to the global variable area of ​​the received target program 20. Definition adding unit 13 adds the definition of the counter variable in a format that conforms to the grammar of the language of target program 20. As a specific example, when target program 20 is written in C language, a definition statement of a global variable CurrentTime is added as the definition of the counter variable, as shown in Fig. 5. Also, 0 is set as the initial value of the counter variable.

[0022] Fig. 6 is a flowchart showing an example of the processing of the accumulation adding unit 14. The processing of the accumulation adding unit 14 will be described with reference to Fig. 6. Note that in this flowchart, it is assumed that the processing of the division unit 11, the processing of the estimation unit 12, and the processing of the definition adding unit 13 have already been executed.

[0023] (Step S111) This step is a loop for adding an accumulation addition process to each element of the basic block set. The accumulation and addition unit 14 receives as input the output of the estimation unit 12 and the output of the definition addition unit 13. In addition, the accumulation and addition unit 14 selects one element of the basic block set as a target basic block in each iteration of the loop, where "BB" indicates the target basic block.

[0024] (Step S112) The accumulation adding unit 14 acquires the estimated execution time corresponding to the target basic block as the target execution time.

[0025] (Step S113) The accumulation adding unit 14 adds an accumulation addition process to the target basic block. As a specific example, the accumulation adding unit 14 adds a process of accumulating and adding a value corresponding to the target execution time to a counter variable at the end of the target basic block.

[0026] 7 is a flowchart showing an example of the process of the branch adding unit 15. The process of the branch adding unit 15 will be described with reference to FIG. In this flowchart, the branch addition unit 15 receives the output of the accumulation addition unit 14 and the setting file 28 as input, and adds a conditional branch to the target program 22 for simulating an interrupt event based on the setting file 28.

[0027] (Step S121) This step is a loop for adding a conditional branch to each element of the basic block set. The accumulation adding unit 14 selects one element of the basic block set as a target basic block in each iteration of the loop.

[0028] (Step S122) This step is a loop for adding a conditional branch corresponding to each entry indicated by the configuration file 28. In each iteration of the loop, the branch addition unit 15 selects one entry indicated by the setting file 28 as a target entry.

[0029] (Step S123) The branch addition unit 15 adds a conditional branch corresponding to the target entry to the end of the target basic block. As a specific example, the branch addition unit 15 acquires a conditional expression and processing content for a conditional branch from the configuration file 28. Here, a counter variable and a global variable included in the target program 22 can be described in the conditional expression. A call of a function included in the target program 22 can be described in the processing content.

[0030] Fig. 8 shows a specific example of a configuration file 28 and a modified program 29. In Fig. 8, the first entry simulates a timer interrupt event, that is, simulates the firing of a timer. The description of the first entry causes the TimerHandler function to be called when the current estimated execution time exceeds 1000. In addition, the value of FlagTimerHandler is set by calling the TimerHandler function, and therefore the wait for TimerHandler completion in the main function is released. Also, like the second and third entries shown in FIG. 8, a global variable defined in the target program 20 can be written in the conditional expression.

[0031] ***Explanation of the Effects of the First Embodiment*** As described above, according to this embodiment, in simulating a timer interrupt event, neither a real machine that is the operating environment of the program nor an emulator or simulator having an interrupt model is necessary. Therefore, according to this embodiment, even in the early development stage when a real machine or the like cannot be prepared, it is possible to simulate a timer interrupt event based on the elapsed time during program execution. Furthermore, according to this embodiment, since no execution time overhead due to emulation or simulation occurs in simulating a timer interrupt event, the simulation of the timer interrupt event is accelerated.

[0032] ***Other configurations*** <Variation 1> FIG. 9 shows an example of the hardware configuration of the interrupt simulator 10 according to this modified example. The interrupt simulator 10 includes a processing circuit 58 in place of the processor 51 , the processor 51 and a memory 52 , the processor 51 and a secondary storage device 53 , or the processor 51 , the memory 52 , and the secondary storage device 53 . The processing circuit 58 is hardware that realizes at least a part of each unit included in the interrupt simulator 10 . The processing circuitry 58 may be dedicated hardware, or may be a processor that executes programs stored in the memory 52 .

[0033] When processing circuitry 58 is dedicated hardware, processing circuitry 58 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The interrupt simulator 10 may include a plurality of processing circuits that replace the processing circuit 58. The plurality of processing circuits share the role of the processing circuit 58.

[0034] In the interrupt simulator 10, some of the functions may be realized by dedicated hardware, and the remaining functions may be realized by software or firmware.

[0035] Processing circuitry 58 is illustratively implemented in hardware, software, firmware, or a combination thereof. The processor 51, memory 52, secondary storage device 53, and processing circuit 58 are collectively referred to as "processing circuitry." In other words, the functions of the functional components of the interrupt simulator 10 are realized by the processing circuitry.

[0036] ***Other embodiments*** Although the first embodiment has been described, it is possible to combine a plurality of parts of the present embodiment. Alternatively, it is possible to partially implement the present embodiment. In addition, the present embodiment may be modified in various ways as necessary, and may be implemented in any combination, either as a whole or in part. The above-described embodiment is essentially a preferred example, and is not intended to limit the scope of the present disclosure, its applications, and uses. The procedures described using the flowcharts and the like may be modified as appropriate. [Explanation of symbols]

[0037] 10 interrupt simulator, 11 division unit, 12 estimation unit, 13 definition addition unit, 14 accumulation addition unit, 15 branch addition unit, 20, 21, 22 target program, 28 setting file, 29 processed program, 51 processor, 52 memory, 53 secondary storage device, 54 input device, 55 output device, 58 processing circuit, 59 bus.

Claims

1. an accumulation adding unit which, when a target program which is a computer program is divided into a plurality of basic blocks, treats each basic block of the plurality of basic blocks as a target basic block, and adds an accumulation addition process which adds a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program when the target basic block is executed in the target program; a branch addition unit that adds a conditional branch process to the target program, the conditional branch process being executed when the value of the counter variable satisfies an ignition criteria condition; An interrupt simulation device comprising:

2. 2. The interrupt simulator according to claim 1, wherein the target program is an embedded program.

3. the accumulation addition unit adds an accumulation addition process corresponding to the target basic block to an end of the target basic block; 3. The interrupt simulator according to claim 1, wherein the branch addition unit adds the conditional branch processing to an end of a basic block corresponding to the conditional branch processing.

4. 3. The interrupt simulator according to claim 1, wherein the ignition criteria are conditions specified in a setting file.

5. 3. The interrupt simulator according to claim 1, wherein the counter variable is a global variable.

6. a computer adds an accumulative addition process for, when a target program, which is a computer program, is divided into a plurality of basic blocks, treating each basic block of the plurality of basic blocks as a target basic block, and, when a target basic block is executed in the target program, adding a value corresponding to an estimated execution time of the target basic block to a counter variable corresponding to an accumulated execution time of the target program; The interrupt simulation method, in which the computer adds, to the target program, a conditional branch process that is executed when the value of the counter variable satisfies an ignition reference condition.

7. an accumulation addition process for adding an accumulation addition process for adding a value corresponding to an estimated execution time of a target basic block to a counter variable corresponding to an accumulated execution time of the target program when the target program is divided into a plurality of basic blocks and each basic block of the plurality of basic blocks is set as a target basic block and the target basic block is executed in the target program; a branch addition process for adding a conditional branch process to the target program, the conditional branch process being executed when the value of the counter variable satisfies an ignition criterion condition; An interrupt simulation program that causes an interrupt simulation device, which is a computer, to execute the above.

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