Information processing device, information processing method, and information processing program

Abstract

To provide an information processing apparatus, an information processing method, and an information processing program configured to effectively complete learning of embedding of a graph structure in a realistic time.SOLUTION: An information processing apparatus includes a sub-graph extraction unit, a path extraction unit, and a learning unit. The sub-graph extraction unit is configured to extract a sub-graph that is a graph structure operating independently from data of an input graph structure including a plurality of nodes and an edge connecting the nodes. The path extraction unit is configured to extract a path from the extracted sub-graph. The learning unit is configured to perform learning of an embedding model using the extracted path, the embedding model performing embedding on data of the graph structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present embodiment relates to an information processing device, an information processing method, and an information processing program. [Background technology]

[0002] The source code of a program can be converted into a graph structure by regarding each processing unit as a node and each processing transition as an edge. Similarly, the design diagram of an electric circuit can be converted into a graph structure by regarding each circuit part as a node and each wiring between the circuit parts as an edge. By analyzing these graph structures, the characteristics of the source code and the design diagram, or each line of the source code or the parts included in the design diagram, can be quantified. This type of quantification is called graph embedding, etc. When graph embedding is performed by a machine learning model, a method of machine learning for the machine learning model using paths cut out from the graph structure has been established. Path extraction is a method often used in natural language processing. Here, compared to natural language, which has a structure in which words are arranged in a straight line, a graph structure contains many nodes to which multiple edges are connected. A node to which multiple edges are connected becomes a branch point in the path extraction process, and the number of paths increases due to the branch point. For example, if two nodes to which five edges are connected are connected by an edge, there are 16 paths including these two nodes. The number of paths increases exponentially every time three or four nodes connected to multiple edges are connected to each other. In this way, the number of paths tends to increase in a graph structure. For this reason, if machine learning is performed using all the paths, learning may not be completed within a realistic time. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] B. Perozzi, R. Al-Rfou, and S. Skiena, “Deepwalk: Online learning of social representations,” in KDD, 2014, pp. 701-710. Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment provides an information processing device, an information processing method, and an information processing program that can effectively complete learning of embeddings of a graph structure in a realistic amount of time. [Means for solving the problem]

[0005] According to one aspect of the present invention, an information processing apparatus includes a subgraph extraction unit, a path extraction unit, and a learning unit. The subgraph extraction unit extracts a subgraph from input graph structure data having a plurality of nodes and edges connecting the nodes. Only the extracted nodes and edges Operation Complete A subgraph having a graph structure is extracted. A path extraction unit extracts paths from the extracted subgraph. A learning unit uses the extracted paths to learn an embedding model that performs embedding on data of the graph structure. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing a configuration of an information processing device according to an embodiment. [Diagram 2] FIG. 2 is a diagram illustrating an example of a hardware configuration of an information processing device. [Diagram 3] FIG. 3 is a flowchart showing an information processing method performed by the information processing device. [Figure 4A] FIG. 4A is a diagram showing an example of data of a graph-structured design diagram of an electric circuit input to an information processing device. [Figure 4B] FIG. 4B is a diagram showing an example of a subgraph extracted from the graph structure data of FIG. 4A. [Figure 5A] FIG. 5A is a diagram showing an example of data of a graph-structured program source code input to an information processing device. [Figure 5B] FIG. 5B is a diagram showing an example of a subgraph extracted from the graph structure data of FIG. 5A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. Fig. 1 is a block diagram showing a configuration of an information processing device according to an embodiment. The information processing device 1 has an input unit 11, a subgraph extraction unit 12, a path extraction unit 13, and a learning unit 14.

[0008] The input unit 11 accepts input of data of an input graph structure. A graph structure represents the association between multiple things as a combination of nodes and edges. A node is a vertex in the graph structure. An edge is a line connecting nodes. Each node includes information on an index number assigned to each node, parameters held by each node, and index numbers of connected edges. Each edge includes information on an index number assigned to each edge and index numbers of connected nodes. An edge may be a valid edge that includes directional information, or an undirected edge that does not include directional information.

[0009] Here, the data of the input graph structure may be input in advance by a user. The data of the input graph structure in the embodiment includes, for example, data of a graph structure generated by regarding a unit of processing of a program as a node and a transition of processing as an edge. The data of the input graph structure in the embodiment also includes data of a graph structure generated by regarding a circuit part of an electric circuit as a node and a wiring between the circuit parts as an edge.

[0010] The subgraph extraction unit 12 receives data of the input graph structure from the input unit 11. Then, the subgraph extraction unit 12 extracts a subgraph from the data of the input graph structure. In the embodiment, the subgraph extraction unit 12 extracts a subgraph composed of nodes and edges that operate independently. "Operating independently" means that the operation is completed by only the combination of the extracted nodes and edges.

[0011] The behaviors defined by the combinations of nodes and edges contained in graph-structured data may not actually work effectively. For example, the source code of a program may contain many branching processes. However, it is rare that all combinations resulting from the branching processes work effectively. Also, in the case of a design drawing of an electric circuit, a closed circuit that includes circuit parts that can act as a motive force is highly reusable, and the closed circuit itself often has a role. On the other hand, when closed circuits are connected to each other, they are often only connected to share motive force. For this reason, the combination of edges that cross closed circuits is only connected for the convenience of implementation, and it is difficult to express the role or characteristics of the electric circuit.

[0012] Taking these factors into consideration, if the graph-structured data is, for example, data of a graph-structured design drawing, the subgraph extraction unit 12 extracts, for example, a closed path including a part that can operate as a motive force as a subgraph composed of independently operating nodes and edges. Similarly, if the graph-structured data is, for example, data of a graph-structured source code of a program, the subgraph extraction unit 12 extracts an effectively operating process flow as a subgraph composed of independently operating nodes and edges. The determination of an independently operating process flow in a program may be performed by statically analyzing the graph-structured data, or may be performed by analyzing a record of the operation results obtained by virtually executing the processing of the program represented by the graph structure.

[0013] The path extraction unit 13 extracts paths from the subgraph extracted by the subgraph extraction unit 12. A path is data having a graph structure that includes a predetermined number of nodes and does not include branches. The path extraction may be performed by any method. For example, the path extraction unit 13 randomly extracts a predetermined number of paths from the subgraph.

[0014] The learning unit 14 learns an embedding model using the paths extracted by the path extraction unit 13. The embedding model is a model that is trained to convert data of each node of the input graph-structured data into an embedding vector according to the characteristics of the graph-structured data. The embedding model may be, for example, a word2vec (MIKOLOV, Tomas, et al. Efficient estimation of word representations in vector space. arXiv preprint arXiv:1301.3781, 2013.) model. In this case, the embedding model considers paths as parts of sentences in natural language and nodes as words in natural language, and applies a method of calculating the roles and meanings of words by machine learning to calculate the roles and meanings of each node in the graph-structured data, and converts each node into an embedding vector according to the calculated roles and meanings. The embedding model may be ngram2vec (ZHAO, Zhe, et al. Ngram2vec: Learning improved word representations from ngram co-occurrence statistics. In: Proceedings of the 2017 conference on empirical methods in natural language processing. 2017. p. 244-253.) instead of word2vec. With ngram2vec, embedding vectors can be calculated for connections between multiple nodes, not just for a single node.

[0015] FIG. 2 is a diagram showing an example of a hardware configuration of the information processing device 1. The information processing device 1 has, for example, a processor 101, a memory 102, an input device 103, a display device 104, a communication device 105, and a storage 106 as hardware. The processor 101, the memory 102, the input device 103, the display device 104, the communication device 105, and the storage 106 are connected to a bus 107. The information processing device 1 may be a terminal device such as a personal computer (PC), a smartphone, or a tablet terminal. However, the information processing device 1 may be incorporated in any device. In addition, the information processing device 1 may not have all of the elements shown in FIG. 2. For example, the information processing device 1 may not have the display device 104 and the communication device 105.

[0016] The processor 101 is a processor that controls the overall operation of the information processing device 1. The processor 101 operates as an input unit 11, a subgraph extraction unit 12, a path extraction unit 13, and a learning unit 14 by executing a program stored in, for example, a storage 106. The processor 101 is, for example, a CPU. The processor 101 may be an MPU, a GPU, an ASIC, an FPGA, or the like. The processor 101 may be a single CPU or the like, or may be multiple CPUs or the like.

[0017] The memory 102 includes a ROM and a RAM. The ROM is a non-volatile memory. The ROM stores a startup program for the information processing device 1 and the like. The RAM is a volatile memory. The RAM is used as a working memory for processing by the processor 101, for example.

[0018] The input device 103 is an input device such as a touch panel, a keyboard, a mouse, etc. When the input device 103 is operated, a signal corresponding to the operation content is input to the processor 101 via the bus 107. The processor 101 performs various processes according to the signal. The input device 103 can be used, for example, to input data of an input graph structure.

[0019] The display device 104 is a display device such as a liquid crystal display, an organic EL display, etc. The display device 104 displays various images. For example, the display device 104 displays images such as graph structure data and embedding results.

[0020] The communication device 105 is a communication device for allowing the information processing device 1 to communicate with an external device. The communication device 105 may be a communication device for wired communication, or may be a communication device for wireless communication.

[0021] The storage 106 is, for example, a storage such as a hard disk drive or a solid state drive. The storage 106 stores an information processing program 1061 executed by the processor 101, such as an information processing program. The storage 106 may also store an embedding model 1062. The embedding model 1062 does not necessarily have to be stored in the storage 106. For example, the embedding model 1062 may be stored in a storage external to the information processing device 1. In this case, the information processing device 1 acquires necessary information by accessing the external storage using the communication device 105.

[0022] The bus 107 is a data transfer path for transmitting data between the processor 101, the memory 102, the input device 103, the display device 104, the communication device 105, and the storage 106.

[0023] Next, a description will be given of the operation of the information processing device 1. Fig. 3 is a flowchart showing an information processing method by the information processing device 1. The processing in Fig. 3 is executed by the processor 101.

[0024] In step S1, the processor 101 acquires data of an input graph structure. As described above, the data of the input graph structure may be input by a user. The user operates the input device 103, for example, to input the data of the input graph structure.

[0025] In step S2, the processor 101 determines whether the input graph structure data is data of a design diagram of a graph-structured electric circuit or the like. For example, if an identifier indicating that the input graph structure data is data of a design diagram is assigned to the input graph structure data, the processor 101 can determine whether the input graph structure data is data of a design diagram of a graph-structured electric circuit or the like from the identifier. Alternatively, whether the input graph structure data is data of a design diagram of a graph-structured electric circuit or the like may be determined by any method, such as a method of determining from a label attached to a node. When it is determined in step S2 that the input graph structure data is data of a design diagram of a graph-structured electric circuit or the like, the process proceeds to step S3. When it is determined in step S2 that the input graph structure data is not data of a design diagram of a graph-structured electric circuit or the like, the process proceeds to step S8.

[0026] In step S3, the processor 101 extracts one or more closed paths from the input graph structure data. A closed path is a path in which the start node and the end node match. For example, a closed path can be searched for from information on the connection destinations of the nodes and edges. After extracting the closed path, the processor 101 stores the graph structure data of the extracted closed path in, for example, the memory 102.

[0027] In step S4, the processor 101 selects one of the extracted closed paths.

[0028] In step S5, the processor 101 determines whether the selected closed path includes a node of a part that can act as a motive force. In the case of a design drawing of an electric circuit, the part that can act as a motive force is a circuit part that supplies power to each circuit part in the electric circuit, such as a power source. In the case of a design drawing of an electric circuit, the motive force may also include a circuit part such as a transformer that supplies power transmitted from another electric circuit to other circuit parts in the closed path. In the case of a design drawing of a machine, the part that can act as a motive force may include an engine or the like. Information on the parts that can act as a motive force is registered in the storage 106, for example. The processor 101 determines whether each node is a node that includes a part that can act as a motive force by checking the label information associated with each node of the extracted closed path against the information on the parts that can act as a motive force registered in the storage 106. When it is determined in step S5 that the selected closed path includes a node of a part that can act as a motive force, the process proceeds to step S6. When it is determined in step S5 that the selected closed path does not include a node of a part that can act as a motive force, the process proceeds to step S7.

[0029] In step S6, the processor 101 extracts the selected cycle as a subgraph. Then, the processor 101 stores the extracted subgraph in, for example, the storage 106. After that, the process proceeds to step S7.

[0030] In step S7, the processor 101 determines whether or not the processing for all the extracted closed paths has been completed. If it is determined in step S7 that the processing for all the extracted closed paths has not been completed, the processing returns to step S4. In this case, the processor 101 selects another closed path and continues the processing. If it is determined in step S7 that the processing for all the extracted closed paths has been completed, the processing proceeds to step S13.

[0031] Here, the process of steps S3-S7 will be specifically described with reference to Fig. 4A and Fig. 4B. Fig. 4A is a diagram showing an example of data of a graph-structured design drawing of an electric circuit input to the information processing device 1. The graph structure G1 shown in Fig. 4A is composed of eight nodes N11-N18. A label representing the name of a circuit part is associated with each node. For example, the label "battery" is associated with node N11. Similarly, the label "switch" is associated with node N12, the label "buzzer" is associated with node N13, the label "switch" is associated with node N14, the label "lamp" is associated with node N15, the label "transformer" is associated with node N16, the label "resistor" is associated with node N17, and the label "coil" is associated with node N18.

[0032] First, a closed path is extracted from the graph structure shown in FIG. 4A. As described above, a closed path is a graph structure in which the start node and the end node are the same. Four closed paths C1, C2, C3, and C4 are extracted from the graph structure G1 in FIG. 4A. The closed path C1 has a graph structure that returns to the node N11, for example, from the node N11 via the node N12, the node N13, and the node N16. The closed path C2 has a graph structure that returns to the node N11, for example, from the node N11 via the node N14, the node N15, and the node N16. The closed path C3 has a graph structure that returns to the node N12, for example, from the node N12 via the node N14, the node N15, and the node N13. The closed path C4 has a graph structure that returns to the node N16, for example, from the node N16 via the node N18 and the node N17. In the embodiment, these closed paths C1, C2, C3, and C4 can be candidates for subgraphs.

[0033] Next, the presence or absence of a power node is determined for each closed circuit. For closed circuit C1, node N11 is a "battery" node, so it is determined that there is power. Similarly, for closed circuit C2, node N11 is a "battery" node, so it is determined that there is power. For closed circuit C4, although it does not include a "battery" node, node N16 connected to a closed circuit that includes a battery is a "transformer" node, so it is determined that there is power. On the other hand, for closed circuit C3, it does not include a "battery" node or any other node that could be a power source, so it is determined that there is no power.

[0034] Next, a closed circuit including a power node is extracted as a subgraph. As a result, as shown in FIG. 4B, a subgraph SG11 having a graph structure of a closed circuit C2, a subgraph SG12 having a graph structure of a closed circuit C1, and a subgraph SG13 having a graph structure of a closed circuit C4 are extracted. On the other hand, the closed circuit C3 is not extracted as a subgraph. An electric circuit without power such as the closed circuit C3 is an electric circuit that does not operate independently. Such an electric circuit that does not operate independently is often not useful in analysis. Therefore, in the embodiment, the graph structure of such an electric circuit that does not operate independently is not extracted as a subgraph.

[0035] Returning now to the explanation of FIG. 3, in step S8 when it is determined in step S2 that the input graph structure data is not data of a design drawing of a graph-structured electric circuit or the like, the processor 101 determines whether or not the input graph structure data is data of source code of a graph-structured program. As in step S2, the determination of whether or not the input graph structure data is data of source code of a graph-structured program may be performed by any method. When it is determined in step S8 that the input graph structure data is data of source code of a graph-structured program, the process proceeds to step S9. When it is determined in step S8 that the input graph structure data is not data of source code of a graph-structured program, the process proceeds to step S13.

[0036] In step S9, the processor 101 virtually executes the processing of the graph-structured program by inputting test data to the program. A plurality of pieces of test data are prepared in advance for each program, and are registered in the storage 106, for example.

[0037] In step S10, the processor 101 records the operation result of the program, for example, in the storage 106. The operation result of the program includes information on a node corresponding to a process operated by the execution of the virtual program. For example, the processor 101 records the operation result of the program from a log obtained by the execution of the virtual program, for example, in the storage 106.

[0038] In step S11, the processor 101 determines whether or not the processing using all the test data has been completed. If it is determined in step S11 that the processing using all the test data has not been completed, the processing returns to step S9. In this case, the processor 101 inputs other test data and continues the processing. If it is determined in step S11 that the processing using all the test data has been completed, the processing proceeds to step S12.

[0039] In step S12, the processor 101 refers to the operation results of the program recorded in the storage 106, for example, and extracts a combination of processes with a large number of operations as a subgraph. After that, the process proceeds to step S13. The threshold for the number of operations may be any integer equal to or greater than 1. The higher the threshold for the number of operations, the fewer the combinations of processes are likely to be extracted as subgraphs.

[0040] Here, the process of steps S9-S12 will be specifically described with reference to FIG. 5A and FIG. 5B. FIG. 5A is a diagram showing an example of data of a graph-structured program source code input to the information processing device 1. The graph structure G2 shown in FIG. 5A is composed of 10 nodes N21-N210. A label representing the content of the process is associated with each node. For example, the label "Process 1" is associated with node N21. Here, "Process 2" of node N22, "Process 5" of node N25, and "Process 8" of node N28 are branch processes. Therefore, the program shown in FIG. 5A can perform eight different operations depending on the input data. In the embodiment, each of these eight operations can be a candidate for a subgraph.

[0041] A plurality of test data are input to the program shown in Fig. 5A, and information on the nodes corresponding to the processes that have been run is recorded. Then, the combination of processes that have been run many times is identified. For example, suppose that the combination of "Process 1", "Process 2", "Process 3", "Process 5", "Process 6", "Process 8", and "Process 9" and the combination of "Process 1", "Process 2", "Process 4", "Process 5", "Process 7", "Process 8", and "Process 10" are the combinations of processes that have been run many times.

[0042] Next, a combination of processes that have been operated many times is extracted as a subgraph. As a result, as shown in FIG. 5B, a subgraph SG21 having a graph structure including nodes N21, N22, N23, N25, N26, N28, and N29, and a subgraph SG22 having a graph structure including nodes N21, N22, N24, N25, N27, N28, and N210 are extracted. On the other hand, other combinations of processes are not extracted as subgraphs. A combination of processes that does not operate often is often not useful in analysis. Therefore, in the embodiment, the graph structure of such a combination of processes that does not operate often is not extracted as a subgraph. Note that if the threshold value of the number of operations is 1, a combination of processes that is not extracted as a subgraph is a combination of processes that does not operate at all.

[0043] Returning now to the description of FIG. 3, in step S13, the processor 101 extracts paths from the graph structure data. As described above, the path extraction may be performed by any method. For example, a method of randomly extracting a predetermined number of paths from the graph structure may be used. If a subgraph has been extracted in a previous process, the paths extracted in step S13 are expected to be useful paths for learning.

[0044] In step S14, the processor 101 inputs the data of the graph structure of the extracted path to the embedding model 1062, and performs learning of the embedding model 1062. Thereafter, the processing in FIG. 3 ends.

[0045] As described above, according to one embodiment, the information processing device 1 extracts, as a subgraph, graph-structured data that operates independently from the input graph-structured data. Then, the information processing device 1 extracts paths from the subgraph, and uses the extracted paths to train the embedding model 1062. That is, in the embodiment, it is expected that the paths used for training the embedding model 1062 have fewer useless paths that are not useful in training. As a result, effective training can be performed even with a small number of paths. Furthermore, since the number of paths is reduced, it is expected that training can be completed in a realistic time.

[0046] Here, in the embodiment, as a method for extracting graph-structured data that operates independently from graph-structured data as a subgraph, a method for extracting a closed circuit including a motive force in a design drawing of an electric circuit or the like, and a method for extracting a combination of processes that operates when test data is input to a program are given. Graph-structured data that operates independently may be extracted by a method other than these. In this case, the graph-structured data does not necessarily have to be data of a design drawing of an electric circuit or the like, or data of a program source code.

[0047] Here, the instructions shown in the processing procedure shown in the above-mentioned embodiment can be executed based on a program, which is software. A general-purpose computer system can store this program in advance and obtain the same effect as the above-mentioned information processing device by reading this program. The instructions described in the above-mentioned embodiment are recorded as a program that can be executed by a computer on a magnetic disk (flexible disk, hard disk, etc.), an optical disk (CD-ROM, CD-R, CD-RW, DVD-ROM, DVD±R, DVD±RW, Blu-ray (registered trademark) Disc, etc.), a semiconductor memory, or a recording medium similar thereto. The recording medium may be in any storage format as long as it is readable by a computer or an embedded system. The computer can realize the same operation as the information processing device of the above-mentioned embodiment by reading the program from this recording medium and executing the instructions described in the program based on this program with a CPU. Of course, when the computer acquires or reads the program, it may acquire or read it through a network. In addition, an OS (operating system), database management software, network, or other MW (middleware) running on a computer may execute some of the processes required to realize this embodiment based on instructions from a program installed on the computer or embedded system from a recording medium. Furthermore, the recording medium in this embodiment is not limited to a medium independent of a computer or an embedded system, but also includes a recording medium that stores or temporarily stores a program downloaded via a LAN, the Internet, or the like. Furthermore, the number of recording media is not limited to one, and a case where the processing in this embodiment is executed from a plurality of media is also included in the recording media in this embodiment, and the media may have any configuration.

[0048] The computer or embedded system in this embodiment is for executing each process in this embodiment based on a program stored in a recording medium, and may be configured as any one of a device such as a personal computer or a microcomputer, or a system in which multiple devices are connected to a network. In addition, the computer in this embodiment is not limited to a personal computer but also includes an arithmetic processing device, a microcomputer, etc. included in information processing equipment, and is a general term for equipment or devices that can realize the functions in this embodiment by a program.

[0049] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0050] 1 Information processing device, 11 Input unit, 12 Subgraph extraction unit, 13 Path extraction unit, 14 Learning unit, 101 Processor, 102 Memory, 103 Input device, 104 Display device, 105 Communication device, 106 Storage, 107 Bus, 1061 Information processing program, 1062 Embedding model.

Claims

1. a subgraph extraction unit that extracts a subgraph, which is a graph structure in which an operation is completed only by the extracted nodes and edges, from input graph structure data having a plurality of nodes and edges connecting the nodes; a path extraction unit that extracts a path from the extracted subgraph; A learning unit that performs learning of an embedding model that performs embedding on graph structure data using the extracted paths; An information processing device comprising:

2. The subgraph extraction unit Extracting one or more cycles in the input graph structure data; determining whether or not a node including a part that can function as a power source is present for each extracted loop; extracting, as the subgraph, a graph structure having a node including a part that can act as the motive force; The information processing device according to claim 1 .

3. The subgraph extraction unit inputting test data into the program represented by the input graph structure data; Recording information on a combination of nodes corresponding to the processing of the program operated according to the input test data; extracting a combination of the nodes that have been operated on a large number of times as the subgraph; The information processing device according to claim 1 .

4. the path extraction unit randomly extracts a predetermined number of the paths from the subgraph; The information processing device according to claim 1 .

5. The embedding model is a word2vec model or an ngram2vec model. The information processing device according to claim 1 .

6. Extracting a subgraph, which is a graph structure in which an operation is completed only by the extracted nodes and edges, from input graph structure data having a plurality of nodes and edges connecting the nodes; Extracting a path from the extracted subgraph; learning an embedding model that embeds the graph-structured data using the extracted paths; An information processing method comprising:

7. Extracting a subgraph, which is a graph structure in which an operation is completed only by the extracted nodes and edges, from input graph structure data having a plurality of nodes and edges connecting the nodes; Extracting a path from the extracted subgraph; learning an embedding model that embeds the graph-structured data using the extracted paths; An information processing program for causing a computer to execute the above.

Images