Motion Blur with Dynamic Quantization Grid

Abstract

To provide an apparatus and method for encoding a motion of a geometric object inside a spatial acceleration structure used for ray tracing.SOLUTION: A graphics processing unit (GPU) 3105 for processing motion blur operations comprises: a bounding volume hierarchy (BVH) generator 3304 to build a BVH comprising hierarchically arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes; and motion blur processing hardware logic 3312 to determine motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node and to map linear bounds of each of the child nodes to the quantization grid.SELECTED DRAWING: Figure 33

Description

[Technical field]

[0001] The present invention relates generally to the field of graphics processors, and more particularly to an apparatus and method for implementing motion blur using a dynamic quantization grid. [Background technology]

[0002] Path tracing is an existing technique for rendering photorealistic images for special effects in movies, animated films, and professional visualization. Generating these realistic images requires the computation of a physical simulation of light propagation in a virtual 3D scene using ray tracing for visibility queries. A high-performance implementation of these visibility queries requires the construction of a 3D hierarchy on the scene primitives (typically triangles) in a pre-processing stage. The hierarchy allows the ray tracing step to quickly determine the closest intersection points between rays and primitives (triangles).

[0003] Motion blur is an important construct in photorealistic rendering of animations that simulates the effect of objects moving in a scene while the camera shutter is open. Simulating this effect causes an orientation blur of the moving objects, which makes the animation appear smooth when it is played back. Rendering motion blur requires randomly sampling the time for each ray path evaluated, and an average of many of these paths provides the desired blur effect. To implement this technique, the underlying ray tracing engine must be able to trace rays through the scene at any time within the camera shutter interval. This requires encoding the motion of geometric objects in the spatial acceleration structures used for ray tracing. Summary of the Invention

[0004] A better understanding of the invention can be obtained from the following detailed description taken in conjunction with the following drawings. [Brief description of the drawings]

[0005] [Figure 1] FIG. 1 is a block diagram of an embodiment of a computer system having a processor with one or more processor cores and a graphics processor.

[0006] [Diagram 2] 1 is a block diagram of an embodiment of a processor having one or more processor cores, an integrated memory controller, and an integrated graphics processor.

[0007] [Diagram 3]FIG. 1 is a block diagram of one embodiment of a graphics processor, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores.

[0008] [Figure 4] FIG. 1 is a block diagram of an embodiment of a graphics processing engine for a graphics processor.

[0009] [Diagram 5] FIG. 2 is a block diagram of another embodiment of a graphics processor.

[0010] [Figure 6A] 1 illustrates an example of implementation circuitry and logic. [Figure 6B] 1 illustrates an example of implementation circuitry and logic.

[0011] [Figure 7] 1 illustrates a graphics processor execution unit instruction format according to an embodiment.

[0012] [Figure 8] FIG. 2 is a block diagram of another embodiment of a graphics processor including a graphics pipeline, a media pipeline, a display engine, thread execution logic, and a rendering output pipeline.

[0013] [Figure 9A] FIG. 2 is a block diagram illustrating a graphics processor command format according to an embodiment.

[0014] [Figure 9B] FIG. 2 is a block diagram illustrating a graphics processor command sequence according to an embodiment.

[0015] [Figure 10]1 illustrates an exemplary graphics software architecture for a data processing system according to an embodiment.

[0016] [Figure 11A] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly. [Figure 11B] 1 illustrates an exemplary IP core development system that may be used to manufacture an integrated circuit and an exemplary package assembly.

[0017] [Figure 12] 1 illustrates an exemplary system of a system-on-chip integrated circuit that may be manufactured using one or more IP cores, according to an embodiment.

[0018] [Figure 13A] 1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores. [Figure 13B] 1 illustrates an exemplary graphics processor of a system-on-chip integrated circuit that may be manufactured using one or more IP cores.

[0019] [Figure 14A] 1 illustrates an exemplary graphics processor architecture. [Figure 14B] 1 illustrates an exemplary graphics processor architecture.

[0020] [Figure 15] 1 is a diagrammatic view of a bounding volume according to an embodiment.

[0021] [Figure 16A] 1 shows a representation of a bounding volume hierarchy. [Figure 16B] 1 shows a representation of a bounding volume hierarchy.

[0022] [Figure 17] 1 is an illustration of a ray-box intersection test according to an embodiment.

[0023] [Figure 18] FIG. 2 is a block diagram illustrating an example quantized BVH node according to an embodiment.

[0024] [Figure 19] FIG. 11 is a block diagram of a complex floating-point data block for use by a quantized BVH node according to a further embodiment.

[0025] [Figure 20] 1 illustrates a ray-box intersection using quantized values ​​to define a child bounding box relative to a parent bounding box according to an embodiment.

[0026] [Figure 21] FIG. 13 is a flow diagram of BVH decompression and traversal logic according to an embodiment.

[0027] [Figure 22] 1 is a diagram of an exemplary two-dimensional coplanar bounding box.

[0028] [Diagram 23] FIG. 13 is a flow diagram of shared surface BVH logic according to an embodiment.

[0029] [Figure 24] FIG. 1 is a block diagram of a computing device including a graphics processor having bounding volume hierarchy logic according to one embodiment.

[0030] [Diagram 25] 1 illustrates an apparatus or system in which an embodiment of the present invention may be implemented;

[0031] [Figure 26] 1 illustrates one embodiment of an apparatus for constructing, compressing and decompressing nodes of a bounding volume hierarchy.

[0032] [Figure 27] 1 illustrates an embodiment in which leaf nodes are compressed by replacing pointers with offsets.

[0033] [Figure 28] Illustrates the three BVH node types and the associated code.

[0034] [Figure 29] An embodiment of the present invention is compared with existing implementations in terms of memory consumption (in MB) and total rendering performance (in fps).

[0035] [Diagram 30] It is used to compare existing implementations with embodiments of the present invention in terms of memory consumption (in MB), traversal statistics, and overall performance.

[0036] [Diagram 31] Illustrates a naive extension of quantized bounding boxes to motion blur triangles.

[0037] [Diagram 32] 1 illustrates an embodiment of the present invention using smaller quantization grids at the beginning and end.

[0038] [Diagram 33] 1 illustrates one embodiment of an architecture including motion blur processing hardware / logic.

[0039] [Diagram 34]1 illustrates a method according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0040]

[0041] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention described below. However, it will be apparent to one skilled in the art that embodiments of the invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the underlying principles of the embodiments of the invention.

[0042] [Exemplary Graphics Processor Architecture and Data Types] (System Overview) 1 is a block diagram of a processing system 100 according to an embodiment. In various embodiments, system 100 includes one or more processors 102 and one or more graphics processors 108 and may be a single desktop system, a multi-processor workstation system, or a server system having multiple processors 102 or processor cores 107. In one embodiment, system 100 is a processing platform integrated into a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0043] In one embodiment, the system 100 can include or be incorporated within a server-based gaming platform, a gaming console, including a game and media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In some embodiments, the system 100 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. The processing system 100 can also include, be coupled to, or be integrated within a wearable device, such as a smart watch wearable device, a smart eyewear device, an augmented reality device, or a virtual reality device. In some embodiments, the processing system 100 is a television or set-top box device having one or more processors 102 and a graphics interface generated by one or more graphics processors 108.

[0044] In some embodiments, the one or more processors 102 each include one or more processor cores 107 that process instructions that, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor cores 107 is configured to process a particular instruction set 109. In some embodiments, the instruction set 109 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or Very Long Instruction Word (VLIW). The multiple processor cores 107 may each process a different instruction set 109, and the different instruction sets 109 may include instructions to facilitate emulation of other instruction sets. The processor cores 107 may include other processing devices, such as a Digital Signal Processor (DSP).

[0045] In some embodiments, the processor 102 includes a cache memory 104. Depending on the architecture, the processor 102 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 102. In some embodiments, the processor 102 also uses an external cache (e.g., a Level-3 (L3) cache or a Last Level Cache (LLC)) (not shown), which may be shared among the processor cores 107 using known cache coherency techniques. A register file 106 is additionally included in the processor 102, which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general purpose registers, while other registers may be specific to the design of the processor 102.

[0046] In some embodiments, the one or more processors 102 are coupled to one or more interface buses 110 for transmitting communication signals, such as address, data, or control signals, between the processors 102 and other components in the system 100. In one embodiment, the interface bus 110 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. However, the processor bus is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In one embodiment, the processor 102 includes an integrated memory controller 116 and a platform controller hub 130. The memory controller 116 facilitates communication between memory devices and other components of the system 100, while the platform controller hub (PCH) 130 provides connectivity to I / O devices via a local I / O bus.

[0047] The memory device 120 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other memory device with suitable performance to function as a process memory. In one embodiment, the memory device 120 can operate as a system memory for the system 100 to store data 122 and instructions 121 for use when the one or more processors 102 execute applications or processes. The memory controller 116 also couples to an optional external graphics processor 112, which may communicate with one or more graphics processors 108 in the processor 102 to perform graphics and media operations. In some embodiments, a display device 111 can be connected to the processor 102. The display device 111 can be one or more of an internal display device, such as in a mobile electronic device or laptop device, or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display device 111 may be a head mounted display (HMD), such as a stereoscopic display device for use in virtual reality (VR) or augmented reality (AR) applications.

[0048] In some embodiments, the platform controller hub 130 allows peripherals to connect to the memory device 120 and the processor 102 via a high-speed I / O bus. The I / O peripherals include, but are not limited to, an audio controller 146, a network controller 134, a firmware interface 128, a wireless transceiver 126, a touch sensor 125, and a data storage device 124 (e.g., hard disk drive, flash memory, etc.). The data storage device 124 can be connected via a peripheral bus such as a storage interface (e.g., SATA) or a peripheral component interconnect bus (e.g., PCI, PCI Express). The touch sensor 125 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. The wireless transceiver 126 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long-Term Evolution (LTE) transceiver. Firmware interface 128 enables communication with system firmware and can be, for example, a unified extensible firmware interface (UEFI). Network controller 134 can enable network connectivity to a wired network. In some embodiments, a high performance network controller (not shown) couples to interface bus 110. In one embodiment, audio controller 146 is a multi-channel high definition audio controller. In one embodiment, system 100 includes an optional legacy I / O controller 140 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system.Platform controller hub 130 may also connect to one or more Universal Serial Bus (USB) controllers 142 that connect input devices, such as a keyboard and mouse 143 combination, a camera 144, or other USB input devices.

[0049] It is recognized that the illustrated system 100 is exemplary and not limiting, as other types of data processing systems configured differently may also be used. For example, instances of memory controller 116 and platform controller hub 130 may be integrated into a separate external graphics processor, such as external graphics processor 112. In one embodiment, platform controller hub 130 and / or memory controller 116 may be external to one or more processors 102. For example, system 100 may include external memory controller 116 and platform controller hub 130, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 102.

[0050] FIG. 2 is a block diagram of an embodiment of a processor 200 having one or more processor cores 202A-202N, an integrated memory controller 214, and an integrated graphics processor 208. These embodiments of FIG. 2 having the same reference numbers (or names) as any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processor 200 may include additional cores, including additional core 202N represented by a dashed box. Each of processor cores 202A-202N includes one or more internal cache units 204A-204N. In some embodiments, each processor core also has access to one or more shared cache units 206.

[0051] Internal cache units 204A-204N and shared cache unit 206 represent a cache memory hierarchy within processor 200. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core, and one or more levels of shared mid-level cache, such as a level 2 (L2), level 3 (L3), level 4 (L4) or other level cache, with the highest level of cache before external memory classified as an LLC. In some embodiments, cache coherency logic maintains coherency between the various cache units 206 and 204A-204N.

[0052] In some embodiments, processor 200 may include a set of one or more bus controller units 216 and a system agent core 210. The one or more bus controller units 216 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. The system agent core 210 provides management functions for various processor components. In some embodiments, system agent core 210 includes one or more integrated memory controllers 214 to manage access to various external memory devices (not shown).

[0053] In some embodiments, one or more of processor cores 202A-202N include support for simultaneous multithreading. In such embodiments, system agent core 210 includes components for coordinating operation of cores 202A-202N during multithreaded processing. System agent core 210 may additionally include a power control unit (PCU), which includes logic and components for coordinating the power state of processor cores 202A-202N and graphics processor 208.

[0054] In some embodiments, processor 200 additionally includes a graphics processor 208 for performing graphics processing operations. In some embodiments, graphics processor 208 couples to a system agent core 210 and a set of shared cache units 206, including one or more integrated memory controllers 214. In some embodiments, system agent core 210 also includes a display controller 211 for driving the graphics processor output to one or more coupled displays. In some embodiments, display controller 211 may be a separate module coupled to the graphics processor via at least one interconnect, or may be integrated within graphics processor 208.

[0055] In some embodiments, a ring-based interconnect unit 212 is used to couple the internal components of processor 200. However, alternative interconnect units may be used, such as a point-to-point interconnect, a switched interconnect, or other technologies, including those known in the art. In some embodiments, graphics processor 208 couples to ring interconnect 212 via I / O link 213.

[0056] The exemplary I / O link 213 represents at least one of several types of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and the graphics processor 208 uses the embedded memory module 218 as a shared last-level cache.

[0057] In some embodiments, the processor cores 202A-202N are homogenous cores that execute the same instruction set architecture. In other embodiments, the processor cores 202A-202N are heterogeneous with respect to instruction set architecture (ISA), where one or more of the processor cores 202A-202N execute a first instruction set while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, the processor cores 202A-202N are heterogeneous with respect to microarchitecture, where one or more cores having relatively high power consumption are combined with one or more power cores having lower power consumption. Additionally, the processor 200 can be implemented on one or more chips having the illustrated components, in addition to other components, or as an SoC integrated circuit.

[0058] 3 is a block diagram of a graphics processor 300, which may be a separate graphics processing unit or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with commands located in the processor memory via a memory-mapped I / O interface to registers on the graphics processor. In some embodiments, the graphics processor 300 includes a memory interface 314 for accessing memory. The memory interface 314 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0059] In some embodiments, graphics processor 300 also includes a display controller 302 for driving display output data to a display device 320. Display controller 302 includes hardware for one or more overlay surfaces for the display and composition of multiple layers of video or user interface elements. Display device 320 can be an internal or external display device. In one embodiment, display device 320 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processor 300 includes a video codec engine 306 for encoding, decoding, or transcoding media to, from, or between, one or more media coding formats, including, but not limited to, Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG and Motion JPEG (MJPEG) formats.

[0060] In some embodiments, graphics processor 300 includes a block image transfer (BLIT) engine 304 for performing two-dimensional (2D) rasterization operations, including, for example, bit-boundary block transfer. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 310. In some embodiments, GPE 310 is a computation engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0061] In some embodiments, GPE 310 includes a 3D pipeline 312 for performing 3D operations such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 312 includes programmable and fixed function elements that perform various tasks within the elements and / or spawn execution threads to 3D / media subsystem 315. While 3D pipeline 312 can be used to perform media operations, embodiments of GPE 310 also include a media pipeline 316 that is used specifically to perform media operations such as video post-processing and image enhancement.

[0062] In some embodiments, the media pipeline 316 includes fixed function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video de-interlacing, and video encoding acceleration, instead of or for the video codec engine 306. In some embodiments, the media pipeline 316 additionally includes a thread spawning unit that spawns threads for execution on the 3D / media subsystem 315. The spawned threads perform computations for the media operations on one or more graphics execution units included in the 3D / media subsystem 315.

[0063] In some embodiments, the 3D / Media subsystem 315 includes logic for executing threads created by the 3D pipeline 312 and the media pipeline 316. In one embodiment, the pipelines send thread execution requests to the 3D / Media subsystem 315, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units for processing the 3D and media threads. In some embodiments, the 3D / Media subsystem 315 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystems also include shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0064] (Graphics Processing Engine)

[0065] FIG. 4 is a block diagram of a graphics processing engine 410 of a graphics processor according to some embodiments. In one embodiment, the graphics processing engine (GPE) 410 is a version of the GPE 310 shown in FIG. 3. Elements of FIG. 4 having the same reference numbers (or names) as elements of any other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. For example, the 3D pipeline 312 and the media pipeline 316 of FIG. 3 are shown. The media pipeline 316 is optional in some embodiments of the GPE 410 and may not be explicitly included within the GPE 410. For example, in at least one embodiment, a separate media and / or image processor is coupled to the GPE 410.

[0066] In some embodiments, the GPE 410 is coupled to or includes a command streamer 403 that provides a command stream to the 3D pipeline 312 and / or the media pipeline 316. In some embodiments, the command streamer 403 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 403 receives commands from the memory and sends the commands to the 3D pipeline 312 and / or the media pipeline 316. The commands are directives fetched from a ring buffer that stores commands for the 3D pipeline 312 and the media pipeline 316. In one embodiment, the ring buffer may additionally include a batch command buffer that stores a batch of multiple commands. The commands for the 3D pipeline 312 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for the 3D pipeline 312 and / or image data and memory objects for the media pipeline 316. The 3D pipeline 312 and the media pipeline 316 process commands and data by executing operations through logic within the respective pipelines or by dispatching one or more execution threads to the graphics core array 414. In one embodiment, the graphics core array 414 includes one or more blocks of graphics cores (e.g., graphics core 415A, graphics core 415B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources including general-purpose and graphics-specific execution logic for performing graphics and computational operations, and fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0067] In various embodiments, the 3D pipeline 312 includes fixed function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 414. The graphics core array 414 provides a unified block of execution resources for use in processing these shader programs. General purpose execution logic (e.g., execution units) within the graphics cores 415A-414B of the graphics core array 414 includes support for a variety of 3D API shader languages ​​and can execute multiple concurrent threads of execution associated with multiple shaders.

[0068] In some embodiments, graphics core array 414 also includes execution logic for performing media functions, such as video and / or image processing. In one embodiment, the execution unit additionally includes general purpose logic that is programmable to perform parallel general purpose computing operations in addition to graphics processing operations. The general purpose logic can perform processing operations in parallel or in conjunction with the general purpose logic in processor core 107 of FIG. 1 or cores 202A-202N as in FIG. 2.

[0069] Output data generated by threads executing on the graphics core array 414 can output data to memory in a unified return buffer (URB) 418. The URB 418 can store data for multiple threads. In some embodiments, the URB 418 can be used to send data between different threads executing on the graphics core array 414. In some embodiments, the URB 418 can additionally be used for synchronization between threads on the graphics core array and fixed function logic in the shared function logic 420.

[0070] In some embodiments, graphics core array 414 is scalable such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance levels of GPE 410. In one embodiment, the execution resources are dynamically scalable such that execution resources may be enabled or disabled as needed.

[0071] The graphics core array 414 couples to shared functionality logic 420, which includes multiple resources shared among the graphics cores in the graphics core array. The shared functionality in the shared functionality logic 420 is a hardware logic unit that provides specialized supplemental functionality to the graphics core array 414. In various embodiments, the shared functionality logic 420 includes, but is not limited to, sampler 421, numeric arithmetic 422, and inter-thread communication (ITC) 423 logic. Additionally, some embodiments implement one or more caches 425 in the shared functionality logic 420.

[0072] Shared functions are implemented when the demand for a given specialized function is insufficient to be included within the graphics core array 414. Instead, a single instantiation of that specialized function is implemented as a standalone entity within the shared function logic 420 and shared among the execution resources within the graphics core array 414. The exact set of functions shared among and included within the graphics core array 414 varies by embodiment. In some embodiments, certain shared functions within the shared function logic 420 that are used more extensively by the graphics core array 414 may be included within the shared function logic 416 within the graphics core array 414. In various embodiments, the shared function logic 416 within the graphics core array 414 may include some or all of the logic within the shared function logic 420. In one embodiment, all of the logic elements within the shared function logic 420 may be duplicated within the shared function logic 416 of the graphics core array 414. In one embodiment, the shared function logic 420 is omitted in favor of the shared function logic 416 within the graphics core array 414.

[0073] FIG. 5 is a block diagram of hardware logic of a graphics processor core 500 according to some embodiments described herein. Elements of FIG. 5 having the same reference number (or name) as elements of any other figure herein may operate or function in a similar manner as described elsewhere herein, including, but not limited to, the same manner as described elsewhere herein. The illustrated graphics processor core 500 is included in the graphics core array 414 of FIG. 4 in some embodiments. The graphics processor core 500, sometimes referred to as a core slice, may be one or more graphics cores in a modular graphics processor. The graphics processor core 500 is an example of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor core 500 may include a fixed function block 530 coupled to multiple sub-cores 501A-501F, sometimes referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0074] In some embodiments, fixed function block 530 includes a geometry / fixed function pipeline 536 that can be shared by all sub-cores in graphics processor core 500, for example in lower performance and / or lower power graphics processor implementations. In various embodiments, geometry / fixed function pipeline 536 includes a 3D fixed function pipeline (e.g., 3D pipeline 312 as in FIGS. 3 and 4), a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer, such as unified return buffer 418 of FIG. 4.

[0075] In one embodiment, the fixed function block 530 also includes a graphics SoC interface 537, a graphics microcontroller 538, and a media pipeline 539. The graphics SoC interface 537 provides an interface between the graphics processor core 500 and other processor cores in a system-on-chip integrated circuit. The graphics microcontroller 538 is a programmable sub-processor that can be configured to manage various functions of the graphics processor core 500, including thread dispatch, scheduling, and pre-emption. The media pipeline 539 (e.g., media pipeline 316 of FIGS. 3 and 4) includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. The media pipeline 539 performs media operations via requests to compute or sample logic in the sub-cores 501-501F.

[0076] In one embodiment, the SoC interface 537 enables the graphics processor core 500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components in the SoC, including memory hierarchy elements such as shared last level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. The SoC interface 537 may also enable communication with fixed function devices in the SoC, such as a camera imaging pipeline, and may enable the use and / or implementation of global memory atoms that may be shared between the CPU and the graphics processor core 500 in the SoC. The SoC interface 537 may also implement power management controls for the graphics processor core 500 and may enable an interface between the clock domain of the graphics core 500 and other clock domains in the SoC. In one embodiment, the SoC interface 537 enables the receipt of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. Commands and instructions can be dispatched to the media pipeline 539 when media operations are being performed, or to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 536, geometry and fixed function pipelines 514) when graphics processing operations are being performed.

[0077] Graphics microcontroller 538 can be configured to perform various scheduling and management tasks for graphics processor core 500. In one embodiment, graphics microcontroller 538 can execute graphics on various graphics parallel engines in execution unit (EU) arrays 502A-502F, 504A-504F in sub-cores 501A-501F and / or compute workload scheduling. In this scheduling model, host software executing on a CPU core of an SoC including graphics processor core 500 can submit a workload to one of multiple graphics processor doorbells, which triggers a scheduling operation on the appropriate graphics engine. The scheduling operation includes determining which workload to run next, submitting the workload to a command streamer, pre-empting existing workloads running on the engines, monitoring the progress of the workloads, and notifying the host software when the workloads are completed. In one embodiment, graphics microcontroller 538 may also facilitate low power or hibernate states for graphics processor core 500 and may provide graphics processor core 500 with the ability to save and restore registers within graphics processor core 500 across low power state transitions independent of the operating system and / or graphics driver software on the system.

[0078] Graphics processor core 500 may have up to N modular sub-cores, which may be larger or smaller than the illustrated sub-cores 501A-501F. For each set of N sub-cores, graphics processor core 500 may also include shared function logic 510, shared and / or cache memory 512, geometry / fixed function pipeline 514, and additional fixed function logic 516 for accelerating various graphics and computing processing operations. Shared function logic 510 may include logic units related to shared function logic 420 of FIG. 4 (e.g., sampler, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores in graphics processor core 500. Shared and / or cache memory 512 may be a last level cache for the set of N sub-cores 501A-501F in graphics processor core 500, and may also function as a shared memory accessible by multiple sub-cores. Geometry / fixed function pipeline 514 may be included in place of geometry / fixed function pipeline 536 in fixed function block 530 and may include the same or similar logical units.

[0079] In one embodiment, graphics processor core 500 includes additional fixed function logic 516, which may include various fixed function acceleration logic for use by graphics processor core 500. In one embodiment, additional fixed function logic 516 includes an additional geometry pipeline for use in position-only shading. There are two geometry pipelines in position-only shading: a full geometry pipeline in geometry / fixed function pipelines 516, 536, and a cull pipeline, an additional geometry pipeline that may be included in additional fixed function logic 516. In one embodiment, the cull pipeline is a trimmed version of the full geometry pipeline. The full pipeline and the cull pipeline may run different instances of the same application, with each instance having a separate context. Position-only shading may hide long cull runs of discarded triangles, potentially allowing shading to complete sooner. For example, in one embodiment, the cull pipeline logic in the additional fixed function logic 516 can execute position shaders in parallel with the main application and generally produce critical results faster than the full pipeline because the cull pipeline fetches and shades only the position attributes of vertices without rasterizing and rendering pixels to the frame buffer. The cull pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled or not. The full pipeline (sometimes called the regeneration pipeline in this case) can consume the visibility information to skip culled triangles in order to shade only the visible triangles that are ultimately passed to the rasterization phase.

[0080] In one embodiment, the additional fixed function logic 516 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inference.

[0081] Within each graphics sub-core 501A-501F is a set of execution resources that may be used to execute graphics, media, and computation in response to requests by a graphics pipeline, a media pipeline, or a shader program. The graphics sub-cores 501A-501F include a number of EU arrays 502A-502F, 504A-504F, thread dispatch and inter-thread communication (TD / IC) logic 503A-503F, 3D (e.g., texture) samplers 505A-505F, media samplers 506A-506F, shader processors 507A-507F, and shared local memories (SLMs) 508A-508F. The EU arrays 502A-502F, 504A-504F are general purpose graphics processing units that each include multiple execution units capable of performing floating point and integer / fixed point logic operations in service of graphics, media, or computation operations, including graphics, media, and computation shader programs. The TD / IC logic 503A-503F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. The 3D samplers 505A-505F can read textures or other 3D graphics related data into memory. The 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. The media samplers 506A-506F can perform similar read operations based on the type and format associated with the media data. In one embodiment, each graphics sub-core 501A-501F can alternatively include an integrated 3D and media sampler. Threads executing on execution units in each sub-core 501A-501F use shared local memory 508A-508F in each sub-core, allowing threads executing within a thread group to execute using a common pool of on-chip memory.

[0082] (Execution unit)

[0083] 6A-6B illustrate thread execution logic 500 including an array of processing elements used in a graphics processor core in accordance with embodiments described herein. Elements of FIG. 6A-6B having the same reference numbers (or names) as elements of any other figures herein may operate or function in a similar manner as described elsewhere herein, but are not limited to such. FIG. 6A illustrates an overview of thread execution logic 600, which may include variations of the hardware logic illustrated in each of sub-cores 501A-501F of FIG. 5. FIG. 6B illustrates exemplary internal details of an execution unit.

[0084] As shown in FIG. 6A, in some embodiments, the thread execution logic 500 includes a shader processor 502, a thread dispatcher 504, an instruction cache 506, a scalable execution unit array including multiple execution units 608A-608N, a sampler 610, a data cache 612, and a data port 614. In one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 608A, 608B, 608C, 608D-608N-1, and 608N) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect fabric that couples each of the components. In some embodiments, the thread execution logic 500 includes one or more connections to a memory, such as a system memory or a cache memory, through one or more of the instruction cache 606, the data port 614, the sampler 610, and the execution units 608A-608N. In some embodiments, each execution unit (e.g., 608A) is a stand-alone, programmable, general-purpose computational unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution units 608A-N is scalable to include any number of individual execution units.

[0085] In some embodiments, the execution units 608A-608N are primarily used to execute shader programs. The shader processor 602 can process various shader programs and dispatch execution threads associated with the shader programs via the thread dispatcher 604. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution units within the execution units 608A-608N. For example, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In some embodiments, the thread dispatcher 604 can also handle run-time thread creation requests from executing shader programs.

[0086] In some embodiments, the execution units 608A-N support an instruction set that includes native support for many standard 3D graphics shader instructions so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). Each of the execution units 608A-N is capable of multi-issue single instruction multiple data (SIMD) execution, and multi-threaded operation allows for an efficient execution environment when faced with higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. Execution is multiple issue per clock into a pipeline capable of integer, single and double precision floating point operations, SIMD branching capability, logical operations, transcendental operations, and a variety of other operations. While waiting for data from memory or one of the shared functions, dependent logic within the execution units 608A-608N causes the waiting thread to sleep until the requested data is returned. While the waiting thread is sleeping, hardware resources may be allocated to process other threads. For example, during the delay associated with a vertex shader operation, the execution unit may execute operations for other types of shader programs, including pixel shaders, fragment shaders, or different vertex shaders.

[0087] Each execution unit in execution units 608A-608N operates on an array of data elements. The number of data elements is the "execution size" or number of channels of an instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution units 608A-608N support integer and floating point data types.

[0088] The execution unit instruction set includes SIMD instructions. Various data elements can be stored as packed data types in registers, and the execution unit processes the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register, and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) sized data elements), eight separate 32-bit packed data elements (Double-Word (DW) sized data elements), sixteen separate 16-bit packed data elements (Word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0089] In one embodiment, one or more execution units can be coupled to a fused execution unit 609A-609N having thread control logic (607A-607N) common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to the embodiment. Furthermore, various SIMD widths can be executed per EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 609A-609N includes at least two execution units. For example, the fused execution unit 609A includes a first EU 608A, a second EU 608B, and thread control logic 607A that is common to the first EU 608A and the second EU 608B. The thread control logic 607A controls the threads executing on the fused graphics execution unit 609A and enables each EU in the fused execution units 609A-N to execute using a common instruction pointer register.

[0090] One or more internal instruction caches (e.g., 606) are included in the thread execution logic 600 for caching thread instructions for the execution units. In some embodiments, one or more data caches (e.g., 612) are included for caching thread data during thread execution. In some embodiments, a sampler 610 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 610 includes specialized texture or media sampling functions to process the texture or media data during the sampling process before providing the sampled data to the execution units.

[0091] During execution, the graphics and media pipeline sends thread start requests to the thread execution logic 600 via thread creation and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 602 is invoked to further compute output information and write the results to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, a pixel shader or fragment shader computes values ​​for various vertex attributes to be interpolated between the rasterized objects. In some embodiments, the pixel processor logic within the shader processor 602 then executes pixel or fragment shader programs provided by an application programming interface (API). To execute the shader programs, the shader processor 602 dispatches threads to execution units (e.g., 608A) via the thread dispatcher 604. In some embodiments, the shader processor 502 uses texture sampling logic in the sampler 610 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment or discard one or more pixels from further processing.

[0092] In some embodiments, data port 614 provides a memory access mechanism for thread execution logic 600 to output processed data to memory for further processing on the graphics processor output pipeline. In some embodiments, data port 514 includes or is coupled to one or more cache memories (e.g., data cache 612) for caching data for memory access via the data port.

[0093] As shown in FIG. 6B, the graphics execution unit 608 includes an instruction fetch unit 637, a general register file array (GRF) 624, an architectural register file array (ARF) 626, a thread arbiter 622, a send unit 630, a branch unit 632, a set of SIMD floating point units 634, and in one embodiment, a set of dedicated integer SIMD ALUs 635. The GRF 624 and ARF 626 include a set of general register files and architectural register files associated with each concurrent hardware thread that may be active in the graphics execution unit 608. In one embodiment, per-thread architectural state is maintained in the ARF 626, while data used during thread execution is stored in the GRF 624. The execution state of each thread, including an instruction pointer for each thread, may be held in thread-specific registers within the ARF 626.

[0094] In one embodiment, the graphics execution units 608 have an architecture that is a combination of Simultaneous Multi-Threading (SMT) and Fine-Grained Interleaved Multi-Threading (IMT) with a modular organization that can be tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, and execution unit resources are divided among the logic used to execute multiple simultaneous threads.

[0095] In one embodiment, the graphics execution unit 608 can issue multiple instructions simultaneously, each of which may be a different instruction. The thread arbiter 622 of the graphics execution unit thread 608 can dispatch the instruction to one of the send unit 630, the branch unit 632, or the SIMD FPU 634 for execution. Each execution thread can access 128 general purpose registers in the GRF 624, each of which can store 32 bytes and is accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4K bytes in the GRF 624, although embodiments are not so limited and other embodiments may provide more or less register resources. In one embodiment, up to seven threads can execute simultaneously, although the number of threads per execution unit may vary according to the embodiment. In an embodiment in which seven threads may access 4K bytes, the GRF 624 can store a total of 28K bytes. Flexible addressing modes can allow registers to be addressed together to effectively build wider registers or represent strided rectangular block data structures.

[0096] In one embodiment, memory operations, sampler operations and other longer latency system communications are dispatched via "send" instructions performed by messages passing through send unit 530. In one embodiment, branch instructions are dispatched to a dedicated branch unit 632 to facilitate SIMD divergence and eventual convergence.

[0097] In one embodiment, the graphics execution unit 608 includes one or more SIMD floating point units (FPUs) 634 for performing floating point operations. In one embodiment, the FPUs 534 also support integer calculations. In one embodiment, the FPUs 634 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In one embodiment, at least one of the FPUs provides extended math capability supporting high-throughput transcendental math functions and double precision 64-bit floating point. In some embodiments, a set of 8-bit integer SIMD ALUs 535 are also present and may be specifically optimized for performing operations related to machine learning calculations.

[0098] In one embodiment, an array of multiple instances of the graphics execution unit 608 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, the exact number of execution units per sub-core group can be selected by the product architect. In one embodiment, the execution unit 608 can execute instructions across multiple execution channels. In a further embodiment, each thread executing on the graphics execution unit 608 executes on a different channel.

[0099] 7 is a block diagram illustrating a graphics processor instruction format 700 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. The solid lined boxes illustrate components that are typically included in execution unit instructions, while the dashed lines include components that are optional or are only included in a subset of the instructions. In some embodiments, the instruction format 700 described and illustrated is a macro instruction, in that it is an instruction that is supplied to an execution unit as the instruction is processed, as opposed to a micro operation that results from an instruction decode.

[0100] In some embodiments, the graphics processor execution units natively support instructions in 128-bit instruction format 710. A 64-bit compact instruction format 730 is available for some instructions based on the selected instruction, instruction options, and number of operands. While the native 128-bit instruction format 710 provides access to all instruction options, some options and operations are restricted in the 64-bit format 730. The native instructions available in the 64-bit format 730 vary depending on the embodiment. In some embodiments, the instructions are compacted in part using a set of index values ​​in index field 713. The execution unit hardware looks up a set of compaction tables based on the index values ​​and uses the output of the compaction tables to reconstruct the native instruction in the 128-bit instruction format 710.

[0101] For each format, an instruction opcode 712 defines the operation that the execution unit is to perform. The execution unit executes each instruction in parallel among multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous add operation across each color channel representing a texture or picture element. By default, the execution unit executes each instruction across all data channels of an operand. In some embodiments, an instruction control field 714 allows control over certain execution options, such as channel selection (e.g., prediction) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction format 710, an exec size field 716 limits the number of data channels that are executed in parallel. In some embodiments, the exec size field 716 is not available for use in the 64-bit compact instruction format 730.

[0102] Some execution unit instructions have up to three operands, including two source operands, src0 720 and src1 722, and one destination 718. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions may have a third source operand (e.g., SRC2 724), and the instruction opcode 712 determines the number of source operands. The last source operand of an instruction may be an immediate value (e.g., a hard-coded value) passed with the instruction.

[0103] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies, for example, whether a direct or indirect register addressing mode is used. When a direct register addressing mode is used, the register addresses of one or more operands are provided directly by bits in the instruction.

[0104] In some embodiments, the 128-bit instruction format 710 includes an access / address mode field 726 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands, and when in a second mode, the instruction may use 16-byte aligned addressing for all source and destination operands.

[0105] In one embodiment, the address mode portion of the access / address mode field 726 determines whether the instruction uses direct or indirect addressing. When the direct register addressing mode is used, bits in the instruction directly provide the register address of one or more operands. When the indirect register addressing mode is used, the register address of one or more operands may be calculated based on an address register value and an address immediate field in the instruction.

[0106] In some embodiments, instructions are grouped based on a bit field of the opcode 712 to simplify opcode decode 740. For 8-bit opcodes, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode groupings shown are merely examples. In some embodiments, the move and logic opcode group 742 includes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 742 shares the five most significant bits (MSBs), with move (mov) instructions being of the form 0000xxxxb and logic instructions being of the form 0001xxxb. The flow control instruction group 744 (e.g., call, jump (jmp)) includes instructions of the form 0010xxxxb (e.g., 0x20). The Miscellaneous Instruction Group 746 includes a mix of instructions including synchronization instructions (e.g., wait, send) in the format of 0011xxxxb (e.g., 0x30). The Parallel Math Instruction Group 748 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the format of 0100xxxxb (e.g., 0x40). The Parallel Math Group 748 performs arithmetic operations in parallel across data channels. The Vector Math Group 750 includes arithmetic instructions (e.g., dp4) in the format of 0101xxxxb (e.g., 0x50). The Vector Math Group performs arithmetic such as dot product calculations on vector operands.

[0107] (Graphics Pipeline)

[0108] Figure 8 is a block diagram of another embodiment of a graphics processor 800. Elements of Figure 8 having the same reference numbers (or names) as elements of any other figure herein may operate or function in a similar manner as described elsewhere herein, including, but not limited to, those described herein.

[0109] In some embodiments, graphics processor 800 includes a geometry pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a rendering output pipeline 870. In some embodiments, graphics processor 800 is a graphics processor in a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processor 800 via a ring interconnect 802. In some embodiments, ring interconnect 802 couples graphics processor 800 to other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnect 802 are interpreted by a command streamer 803, which provides instructions to individual components of geometry pipeline 820 or media pipeline 830.

[0110] In some embodiments, command streamer 803 directs the operation of a vertex fetcher 805, which reads vertex data from memory and executes vertex processing commands provided by command streamer 803. In some embodiments, vertex fetcher 805 provides the vertex data to a vertex shader 807, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, vertex fetcher 805 and vertex shader 807 execute vertex processing instructions by dispatching execution threads to execution units 852A-852B via thread dispatcher 831.

[0111] In some embodiments, the execution units 852A-852B are an array of vector processors with an instruction set for performing graphics and media operations. In some embodiments, the execution units 852A-852B have an attached L1 cache 851 that is specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache partitioned to contain data and instructions in different partitions.

[0112] In some embodiments, the geometry pipeline 820 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 811 configures the tessellation operations. A programmable domain shader 817 provides back-end evaluation of the tessellation output. A tessellator 813 operates at the hull shader 811's direction and includes special purpose logic for generating a set of detailed geometric objects based on a coarse geometric model provided as input to the geometry pipeline 820. In some embodiments, the tessellation components (e.g., the hull shader 811, the tessellator 813, and the domain shader 817) can be bypassed if tessellation is not used.

[0113] In some embodiments, a complete geometric object can be processed by the geometry shader 819 via one or more threads dispatched to execution units 852A-852B, or can proceed directly to the clipper 829. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in earlier stages of the graphics pipeline. If tessellation is disabled, the geometry shader 819 receives input from the vertex shader 807. In some embodiments, the geometry shader 819 is programmable by the geometry shader program to perform geometry tessellation if the tessellation units are disabled.

[0114] Before rasterization, a clipper 829 processes the vertex data. The clipper 829 may be a fixed function clipper or a programmable clipper with clipping and geometry shader functions. In some embodiments, a rasterizer and depth test component 873 in the rendering output pipeline 870 dispatches pixel shaders to convert geometric objects into per-pixel representations. In some embodiments, pixel shader logic is included in the thread execution logic 850. In some embodiments, an application can bypass the rasterizer and depth test component 873 and access un-rasterized vertex data via the stream output unit 823.

[0115] The graphics processor 800 includes an interconnect bus, interconnect fabric, or some other interconnect mechanism for passing data and messages between the major components of the processor. In some embodiments, the execution units 852A-852B and associated logic units (e.g., L1 cache 851, sampler 854, texture cache 858, etc.) interconnect via data port 856 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the sampler 854, caches 851, 858, and the execution units 852A-852B each have a separate memory access path. In one embodiment, the texture cache 858 may also be configured as a sampler cache.

[0116] In some embodiments, the rendering output pipeline 870 includes a rasterizer and depth test component 873 that converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower / masker unit to perform fixed function triangle and line rasterization. In some embodiments, an associated rendering cache 878 and depth cache 879 are also available. A pixel operations component 877 performs pixel-based operations on the data, although in some instances pixel operations related to 2D operations (e.g., bit-block image transfer with blending) are performed by the 2D engine 841 or replaced at display time by the display controller 843 using an overlay display surface. In some embodiments, a shared L3 cache 875 is available to all graphics components, allowing sharing of data without using main system memory.

[0117] In some embodiments, graphics processor media pipeline 830 includes a media engine 837 and a video front end 834. In some embodiments, the video front end 834 receives pipeline commands from a command streamer 803. In some embodiments, the media pipeline 830 includes a separate command streamer. In some embodiments, the video front end 834 processes the media commands before sending the commands to the media engine 837. In some embodiments, the media engine 837 includes a thread generation function to generate threads for dispatching to the thread execution logic 850 via the thread dispatcher 831.

[0118] In some embodiments, graphics processor 800 includes a display engine 840. In some embodiments, display engine 840 is external to processor 800 and couples to the graphics processor via ring interconnect 802 or other interconnect bus or fabric. In some embodiments, display engine 840 includes a 2D engine 841 and a display controller 843. In some embodiments, display engine 840 includes special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controller 843 couples to a display device (not shown), which may be a system integrated display device, such as in a laptop computer, or an external display device attached via a display device connector.

[0119] In some embodiments, the geometry pipeline 820 and the media pipeline 830 are configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and / or Vulkan graphics and compute APIs, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines are also supported, provided that a mapping from the future API's pipeline to the graphics processor's pipeline is possible.

[0120] (Graphics Pipeline Programming)

[0121] Figure 9A is a block diagram illustrating a graphics processor command format 900 according to some embodiments. Figure 9B is a block diagram illustrating a graphics processor command sequence 910 according to an embodiment. The solid lined boxes in Figure 9A illustrate components that are typically included in a graphics command, while the dashed lines include components that are optional or are included in only a subset of the graphics commands. The example graphics processor command format 900 of Figure 9A includes data fields to identify the client 902, the command operation code (opcode) 904, and the data 906 of the command. Sub-opcodes 905 and command size 908 are also included in some commands.

[0122] In some embodiments, the client 902 specifies a client unit of the graphics device that will process the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the command. When a command is received by a client unit, the client unit reads the opcode 904 and, if present, the sub-opcode 905 to determine the operation to perform. The client unit executes the command using the information in the data field 906. For some commands, an explicit command size 908 is assumed to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments, the commands are aligned on multiples of double words.

[0123] The flow diagram in Figure 9B illustrates an exemplary graphics processor command sequence 910. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of a command sequence that is shown to configure and execute a set of graphics operations to completion. The sample command sequence is shown and described for purposes of example only, as embodiments are not limited to these particular commands or this command sequence. Furthermore, commands may be issued as a batch of commands within a command sequence such that the graphics processor processes the sequence of commands at least partially concurrently.

[0124] In some embodiments, a graphics processor command sequence 910 may begin with a pipeline flush command 912 to cause any active graphics pipelines to complete commands currently pending for that pipeline. In some embodiments, the 3D pipeline 922 and the media pipeline 924 do not operate simultaneously. A pipeline flush is performed to cause the active graphics pipelines to complete any pending commands. In response to a pipeline flush, the graphics processor's command parser pauses command processing until the active drawing engines have completed pending operations and the associated read caches are invalidated. Optionally, any data in the rendering cache that is marked as "dirty" may be flushed to memory. In some embodiments, the pipeline flush command 912 may be used for pipeline synchronization or before placing the graphics processor into a low power state.

[0125] In some embodiments, the pipeline select command 913 is used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, the pipeline select command 913 is only needed once in an execution context before issuing a pipeline command, unless the context issues commands to both pipelines. In some embodiments, a pipeline flush command 912 is needed immediately before switching pipelines via the pipeline select command 913.

[0126] In some embodiments, pipeline control commands 914 are used to configure the graphics pipeline for operations and to program the 3D pipeline 922 and the media pipeline 924. In some embodiments, pipeline control commands 914 configure the pipeline state for active pipelines. In one embodiment, pipeline control commands 914 are used for pipeline synchronization and to clear data from one or more cache memories in active pipelines before processing a batch of commands.

[0127] In some embodiments, return buffer state commands 916 are used to configure a set of return buffers for each pipeline to write data to. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers to which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform inter-thread communication. In some embodiments, return buffer state 916 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0128] The remaining commands in the command sequence differ based on the active pipeline for the operation. Based on the pipeline determination 920, the command sequence is adjusted to either the 3D pipeline 922, beginning with a 3D pipeline state 930, or the media pipeline 924, beginning with a media pipeline state 940.

[0129] The commands that configure the 3D pipeline state 930 include 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that should be configured before 3D primitive commands are processed. The values ​​of these commands are determined at least in part based on the particular 3D API being used. In some embodiments, the 3D pipeline state 930 commands can also selectively disable or bypass certain pipeline elements if the particular pipeline elements are not used.

[0130] In some embodiments, the 3D primitive 932 command is used to submit a 3D primitive to be processed by the 3D pipeline. The command and associated parameters passed to the graphics processor via the 3D primitive 932 command are forwarded to a vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 932 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, the 3D primitive 932 command is used to perform vertex operations on the 3D primitives via vertex shaders. To process the vertex shaders, the 3D pipeline 922 dispatches shader execution threads to the graphics processor execution units.

[0131] In some embodiments, the 3D pipeline 922 is triggered via an execute 934 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a "go" or "kick" command in a command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline performs geometry operations on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel backend operations may also be included for these operations.

[0132] In some embodiments, the graphics processor command sequence 910 follows a media pipeline 924 path when performing media operations. In general, the particular use and manner of programming for the media pipeline 924 depends on the media or compute operations being performed. Certain media decode operations may be offloaded to the media pipeline during media decoding. In some embodiments, the media pipeline may be bypassed and media decode may be performed in whole or in part using resources provided by one or more general purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using compute shader programs that are not explicitly related to rendering graphics primitives.

[0133] In some embodiments, the media pipeline 924 is configured in a similar manner as the 3D pipeline 922. A set of commands to configure the media pipeline state 940 are dispatched or placed in a command queue before the media object commands 942. In some embodiments, the commands for the media pipeline state 940 contain data to configure the media pipeline elements used to process the media object. This includes data to configure the video decoding and video encoding logic in the media pipeline, such as the encoding or decoding format. In some embodiments, the commands for the media pipeline state 940 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0134] In some embodiments, the media object command 942 provides a pointer to a media object for processing by the media pipeline. A media object includes a memory buffer that contains the video data to be processed. In some embodiments, all media pipeline state must be valid before issuing the media object command 942. Once the pipeline state is configured and the media object command 942 is queued, the media pipeline 924 is triggered via an execute command 944 or equivalent execute event (e.g., a register write). The output from the media pipeline 924 may then be post-processed by operations provided by the 3D pipeline 922 or the media pipeline 924. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

[0135] (Graphics Software Architecture)

[0136] 10 illustrates an exemplary graphics software architecture for a data processing system 1000 according to some embodiments. In some embodiments, the software architecture includes a 3D graphics application 1010, an operating system 1020, and at least one processor 1030. In some embodiments, the processor 1030 includes a graphics processor 1032 and one or more general-purpose processor cores 1034. The graphics application 1010 and the operating system 1020 each execute within the system memory 1050 of the data processing system.

[0137] In some embodiments, the 3D graphics application 1010 includes one or more shader programs that include shader instructions 1012. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 1014 in a machine language suitable for execution by a general-purpose processor core 1034. The application also includes graphics objects 1016 defined by vertex data.

[0138] In some embodiments, the operating system 1020 is a Microsoft® Windows® operating system from Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variation of the Linux® kernel. The operating system 1020 can support a graphics API 1022, such as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is used, the operating system 1020 uses a front-end shader compiler 1024 to compile the shader instructions 1012, either HLSL or a low-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can perform pre-compilation of the shaders. In some embodiments, the high-level shaders are compiled into the low-level shaders during compilation of the 3D graphics application 1010. In some embodiments, the shader instructions 1012 are provided in an intermediate format, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

[0139] In some embodiments, the user mode graphics driver 1026 includes a back-end shader compiler 1027 for converting the shader instructions 1012 into a hardware-specific representation. When the OpenGL API is used, the shader instructions 1012 in the GLSL high-level language are passed to the user mode graphics driver 1026 for compilation. In some embodiments, the user mode graphics driver 1026 uses operating system kernel mode functions 1028 to communicate with a kernel mode graphics driver 1029. In some embodiments, the kernel mode graphics driver 1029 communicates with a graphics processor 1032 to dispatch commands and instructions.

[0140] (IP core implementation)

[0141] One or more aspects of at least one embodiment may be implemented by representational code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions that represent various logic within a processor. When read by a machine, the instructions may cause the machine to manufacture logic for performing the techniques described herein. Such representations, known as "IP cores," are reusable units of logic for integrated circuits that may be stored on a tangible machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be provided to various customers or manufacturing facilities, which load the hardware model into manufacturing machines that manufacture the integrated circuits. The integrated circuits may be manufactured to perform the operations described in connection with any of the embodiments described herein.

[0142] FIG. 11A is a block diagram illustrating an IP core development system 1100 that may be used to fabricate an integrated circuit to perform operations according to an embodiment. The IP core development system 1100 may be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). A design facility 1130 may generate a software simulation 1110 of the IP core design in a high-level programming language (e.g., C / C++). The software simulation 1110 may be used to design, test, and verify the behavior of the IP core using a simulation model 1112. The simulation model 1112 may include functional, behavioral, and / or timing simulation. A register transfer level (RTL) design 1115 may then be created or synthesized from the simulation model 1112. The RTL design 1115 is an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including associated logic that is executed using the modeled digital signals. In addition to the RTL design 1115, a lower level design at the logic level or transistor level may also be created, designed, or synthesized, so the specific details of the initial design and simulation may vary.

[0143] The RTL design 1115 or equivalent may be further synthesized by a design facility into a hardware model 1120, which may be a hardware description language (HDL) or other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 1140 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party manufacturing facility 1165. Alternatively, the IP core design may be transmitted over a wired connection 1150 or a wireless connection 1160 (e.g., via the Internet). The manufacturing facility 1165 may then manufacture an integrated circuit based at least in part on the IP core design. The manufactured integrated circuit may be configured to perform operations according to at least one embodiment described herein.

[0144] 11B illustrates a cross-sectional side view of an integrated circuit package assembly 1170 according to some embodiments described herein. The integrated circuit package assembly 1170 illustrates an implementation of one or more processors or accelerator devices described herein. The package assembly 1170 includes multiple units of hardware logic 1172, 1174 coupled to a substrate 1180. The logic 1172, 1174 may be at least partially implemented in configurable logic or fixed function logic hardware and may include one or more portions of any of the processor cores, graphics processors, or other accelerator devices described herein. Each unit of logic 1172, 1174 may be implemented in a semiconductor die and coupled to the substrate 1180 via an interconnect structure 1173. The interconnect structure 1173 may be configured to route electrical signals between the logic 1172, 1174 and the substrate 1180 and may include, but is not limited to, interconnects such as bumps or pillars. In some embodiments, the interconnect structure 1173 may be configured to route electrical signals, such as, for example, input / output (I / O) signals and / or power or ground signals associated with the operation of the logic 1172, 1174. In some embodiments, the substrate 1180 is an epoxy-based laminate substrate. In other embodiments, the package substrate 1180 may include other suitable types of substrates. The package assembly 1170 may be connected to other electrical devices via the package interconnect 1183. The package interconnect 1183 may be coupled to a surface of the substrate 1180 to route electrical signals to other electrical devices, such as a motherboard, another chipset, or a multi-chip module.

[0145] In some embodiments, the units of logic 1172, 1174 are electrically coupled to a bridge 1182 configured to route electrical signals between the logic 1172, 1174. The bridge 1182 may be a high density interconnect structure that provides a path for the electrical signals. The bridge 1182 may include a bridge substrate comprised of glass or a suitable semiconductor material. Electrical routing structures may be formed on the bridge substrate to provide chip-to-chip connections between the logic 1172, 1174.

[0146] Although two units of logic 1172, 1174 and bridge 1182 are shown, embodiments described herein may include more or fewer logic units on one or more dies. Bridge 1182 may be omitted when logic is included on a single die, and thus one or more dies may be connected by zero or more bridges. Alternatively, multiple dies or logic units may be connected by one or more bridges. Additionally, multiple logic units, dies and bridges may be connected to each other in other possible configurations, including three-dimensional configurations.

[0147] Exemplary System-on-Chip Integrated Circuits

[0148] 12-14 illustrate example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores in accordance with various embodiments described herein. In addition to what is illustrated, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0149] 12 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1200 that may be manufactured using one or more IP cores according to an embodiment. The exemplary integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs) and at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, a UART controller 1230, a SPI / SDIO controller 1235, and an I2S / I2C controller 1240. In addition, the integrated circuit may include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. Storage may be provided by a flash memory subsystem 1260 that includes a flash memory and a flash memory controller. A memory interface may be provided through a memory controller 1265 for access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 1270.

[0150] 13A-13B are block diagrams illustrating example graphics processors for use within an SoC in accordance with embodiments described herein. FIG. 13A illustrates an example graphics processor 1310 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. FIG. 13B illustrates an additional example graphics processor 1340 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with an embodiment. The graphics processor 1310 of FIG. 13A is an example of a low-power graphics processor core. The graphics processor 1340 of FIG. 13B is an example of a high-performance graphics processor core. Each of the graphics processors 1310, 1340 can be a variation of the graphics processor 1210 of FIG. 12.

[0151] As shown in FIG. 13A, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D-1315N-1, and 1315N). The graphics processor 1310 can execute different shader programs through separate logic such that the vertex processor 1305 is optimized to execute operations for vertex shader programs, while one or more fragment processors 1315A-1315N execute fragment (e.g., pixel) shader operations for fragment or pixel shader programs. The vertex processor 1305 executes the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. The fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate a frame buffer that is displayed on a display device. In one embodiment, the fragment processors 1315A-1315N are optimized to execute fragment shader programs such as those provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs such as those provided in the Direct 3D API.

[0152] Graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B. The one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for graphics processor 1310, including vertex processor 1305 and / or fragment processors 1315A-1315N, which may reference vertices or image / texture data stored in memory in addition to vertices or image / texture data stored in one or more caches 1325A-1325B. In one embodiment, one or more MMUs 1320A-1320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more of application processors 1205, image processor 1215, and / or video processor 1220 of Figure 12, such that each processor 1205-1220 can participate in a shared or unified virtual memory system. One or more circuit interconnects 1330A-1330B enable graphics processor 1310 to interface with other IP cores in the SoC via the SoC's internal bus or direct connections, according to an embodiment.

[0153] As shown in Figure 13B, graphics processor 1340 includes one or more MMUs 1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330B of graphics processor 1310 of Figure 13A. Graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1455A, 1355B, 1355C, 1355D, 1355E, 1355F-1355N-1, and 1355N), which provides a unified shader core architecture in which a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. The exact number of shader cores present may vary between embodiments and implementations. In addition, graphics processor 1340 includes an inter-core task manager 1345 that functions as a thread dispatcher for dispatching execution threads to one or more shader cores 1355A-1355N, and a tile unit 1358 that accelerates tile operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within the scene or to optimize use of internal caches.

[0154] Figures 14A-B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 14A illustrates a graphics core 1400 that may be included within the graphics processor 1210 of Figure 12 and may be a unified shader core 1355A-N as in Figure 13B. Figure 14B illustrates an additional highly parallel general purpose graphics processing unit 1430, which is a highly parallel general purpose graphics processing unit suitable for deployment on a multi-chip module.

[0155] 14A, graphics core 1400 includes a shared instruction cache 1402 common to execution resources within graphics core 1400, a texture unit 1418, and a cache / shared memory 1420. Graphics core 1400 may include multiple slices 1401A-1401N or partitions for each core, and a graphics processor may include multiple instances of graphics core 1400. Slices 1401A-1401N may include supporting logic including local instruction caches 1404A-1404N, thread schedulers 1406A-1406N, thread dispatchers 1408A-1408N, and sets of registers 1410A-1440N. To perform logical operations, slices 1401A-1401N may include a set of additional functional units (AFUs 1412A-1412N), floating point units (FPUs 1414A-1414N), integer arithmetic logic units (ALUs 1416-1416N), address calculation units (ACUs 1413A-1413N), double precision floating point units (DPFUs 1415A-1415N), and matrix processing units (MPUs 1417A-1417N).

[0156] Some computational units operate at a particular precision. For example, the FPUs 1414A-1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 1415A-1415N can perform double-precision (64-bit) floating-point operations. The ALUs 1416A-1416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. The MPUs 1417A-1417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. The MPUs 1417-1417N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). The AFUs 1412A-1412N may perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0157] As shown in FIG. 14B, a general-purpose processing unit (GPGPU) 1430 can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. Furthermore, the GPGPU 1430 can be directly linked to other instances of GPGPUs to create multi-GPU clusters to improve training speed, particularly for deep neural networks. The GPGPU 1430 includes a host interface 1432 to enable connection to a host processor. In one embodiment, the host interface 1432 is a PCI Express interface. However, the host interface can also be a vendor-specific communication interface or fabric. The GPGPU 1430 receives commands from the host processor and uses a global scheduler 1434 to distribute execution threads associated with those commands to a set of compute clusters 1436A-1436H. The compute clusters 1436A-1436H share a cache memory 1438. Cache memory 1438 may act as a higher level cache for the cache memories in compute clusters 1436A-1436H.

[0158] GPGPU 1430 includes memories 14434A-14434B coupled to compute clusters 1436A-1436H via a set of memory controllers 1442A-1442B. In various embodiments, memory 1434A-1434B may include various types of memory devices, including graphics random access memory, such as dynamic random access memory (DRAM) or synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0159] In one embodiment, compute clusters 1436A-1436H each include a set of graphics cores, such as graphics core 1400 of FIG. 14A, which may include multiple types of integer and floating point logic units capable of performing compute operations with a range of precisions, including precisions suitable for machine learning computations. For example, in one embodiment, at least a subset of the floating point units in each of compute clusters 1436A-1436H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0160] Multiple instances of GPGPU 1430 can be configured to operate as a compute cluster. The communication mechanisms used by the compute cluster for synchronization and data exchange vary by embodiment. In one embodiment, multiple instances of GPGPU 1430 communicate through host interface 1432. In one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples GPGPU 1430 with a GPU link 1440 that allows direct connection to other instances of GPGPU. In one embodiment, GPU link 1440 is coupled to a dedicated GPU-to-GPU bridge that allows communication and synchronization between multiple instances of GPGPU 1430. In one embodiment, GPU link 1440 couples to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In one embodiment, multiple instances of GPGPU 1430 communicate through a network device located in separate data processing systems and accessible via host interface 1432. In one embodiment, GPU link 1440 can be configured to allow connection to a host processor in addition to or as an alternative to host interface 1432.

[0161] While the illustrated configuration of GPGPU 1430 may be configured to train a neural network, one embodiment provides alternative configurations of GPGPU 1430 that may be configured for deployment in a high performance or low power inference platform. In the inference configuration, GPGPU 1430 includes fewer compute clusters 1436A-1436H than the training configuration. In addition, the memory technology associated with memories 1434A-1434B may differ between the inference and training configurations, with higher bandwidth memory technology being dedicated to the training configuration. In one embodiment, the inference configuration of GPGPU 1430 may support inference of certain instructions. For example, the inference configuration may provide support for one or more 8-bit integer dot product instructions that are commonly used during inference operations on deployed neural networks.

[0162] (Apparatus and method for Bounding Volume Hierarchy (BVH) compression) A bounding volume hierarchy (BVH) node of N width contains N bounding volumes corresponding to the N children of a given node. In addition to the bounding volumes, a reference to each child node is included, either as an index or a pointer. One bit in the index or pointer can be assigned to indicate whether the node is an interior node or a leaf node. A commonly used bounding volume format, especially for ray tracing, is the axis-aligned bounding volume (AABV) or axis-aligned bounding box (AABB). AABBs can be defined with only the minimum and maximum extent in each dimension, providing efficient ray intersection testing.

[0163] Typically, AABBs are stored in uncompressed form using single precision (e.g., 4 byte) floating point values. To define an uncompressed 3D AABB, two single precision floating point values ​​(min / max) are used for each of the three axes (e.g., 2x3x4), resulting in 24 bytes to store the extent of the AABB plus an index or pointer (e.g., 4 byte integer or 8 byte pointer) to the child node. Thus, each AABB defined for a BVH node may be up to 32 bytes. Thus, a binary BVH node with children may require 64 bytes, a 4-wide BVH node may require 128 bytes, and an 8-wide BVH may require up to 256 bytes.

[0164] Oriented bounding boxes, using k-directional discretely oriented polytopes (k-DOPs), are also a commonly used bounding volume format that may be used in embodiments described herein. In k-DOPs, lower and upper bounds are stored in multiple arbitrary directions. In contrast to AABBs, k-DOPs are not limited to bounds in only the coordinate axis directions, but may bound geometry in any number of directions in space.

[0165] To reduce the memory size requirements for using bounding volume hierarchies (BVHs), BVH data may be stored in a compressed format. For example, each AABB can be stored in a hierarchically compressed format relative to the AABB's parent. However, hierarchical encoding can cause problems in ray tracing implementations when BVH node references are pushed onto a stack during ray traversal. When later dereferenced, a path to the root node is followed to compute the final AABB, resulting in a potentially long dependency chain. An alternative solution stores the current AABB in a stack, which requires a significant amount of stack memory to store the additional data, since stack depths per ray are typically in the range of 40-60 entries.

[0166] The embodiments described herein provide an apparatus, system, method, and various logical processes for compressing BVH nodes in a simple and efficient manner without requiring references to parent nodes or extra stack storage space to decompress the child bounds of the nodes, significantly reducing the complexity of implementing ray tracing acceleration hardware.

[0167] In one embodiment, to reduce memory requirements, the N child bounding boxes are encoded for the merged box of all children by storing the parent bounding box in absolute coordinates and full (e.g., floating point) precision, while the child bounding boxes are stored with less precision relative to the parent bounding box.

[0168] The approach described herein reduces memory storage and bandwidth requirements compared to conventional approaches that store full precision bounding boxes for all children. Each node may be decompressed separately from other nodes. As a result, complete bounding boxes are not stored in a stack during traversal, and the entire path from the root of the tree is not re-traversed to decompress a node on pop operations. In addition, ray-node intersection tests can be performed with reduced precision, reducing the complexity required in the arithmetic hardware unit.

[0169] (bounding volume and ray-box intersection testing) FIG. 15 is an illustration of a bounding volume 1502 according to an embodiment. The bounding volume 1502 shown is axis aligned to a three-dimensional axis 1500. However, the embodiment is applicable to different bounding representations (e.g., oriented bounding box, discrete oriented polytope, sphere, etc.) and any number of dimensions. The bounding volume 1502 defines the minimum and maximum extent of the three-dimensional object 1504 along each of the axis dimensions. To generate the BVH of a scene, a bounding box is constructed for each object in a set of objects in the scene. A set of parent bounding boxes can then be constructed around the group of bounding boxes constructed for each object.

[0170] Figures 16A-16B illustrate a representation of a bounding volume hierarchy for two-dimensional objects. Figure 16A shows a set of bounding volumes 5200 around a set of geometric objects. Figure 16B shows an ordered tree 5202 of the bounding volumes 5200 of Figure 52A.

[0171] As shown in Figure 52A, the set of bounding volumes 5200 includes a root bounding volume N1, which is the parent bounding volume of all other bounding volumes N2 to N7. Bounding volumes N2 and N3 are internal bounding volumes between the root volume N1 and leaf volumes N4 to N7. The leaf volumes N4 to N7 contain the geometric objects O1 to O8 of the scene.

[0172] 16B illustrates an ordered tree 1602 of bounding volumes N1-N7 and geometric objects O1-O8. The illustrated ordered tree 1602 is a binary tree where each node in the tree has two child nodes. A data structure configured to contain information for each node may include bounding information for the node's bounding volume (e.g., a bounding box), as well as at least a reference to each of the node's child nodes.

[0173] The ordered tree 1602 representation of bounding volumes defines a hierarchy that can be used to perform various operations in hierarchical versions, including, but not limited to, collision detection and ray-box intersection. In the example of ray-box intersection, nodes can be tested hierarchically starting with a root node N1 that is the parent node to all other bounding volume nodes in the hierarchy. If the ray-box intersection test for the root node N1 fails, all other nodes in the tree may be bypassed. If the ray-box intersection test for the root node N1 passes, subtrees of the tree can be tested and traversed or bypassed in an ordered manner until at least a set of intersecting leaf nodes N4-N7 has been determined. The exact tests and traversal algorithms used can vary according to the embodiment.

[0174] FIG. 17 is an illustration of a ray-box intersection test according to an embodiment. During a ray-box intersection test, a ray 1702 is shot and an equation defining the ray can be used to determine whether the ray intersects with a face defining a bounding box 1700 under test. A ray 5302 can be expressed as O+D·t, where O corresponds to the ray's origin viewpoint, D is the ray's direction, and t is a real value. Varying t can be used to define any point along the ray. A ray 1702 is said to intersect with a bounding box 1700 when the maximum entrance face intersection distance is less than or equal to the minimum exit face distance. For the ray 1702 in FIG. 17, the y-face entrance intersection distance is tmin-y 1704. The y-plane exit crossover distance is t max-y 1708. The x-plane incidence crossing distance is t min-x 1706, and the x-plane exit intersection distance is t max-x 1710. Thus, a given ray 1702 can be mathematically shown to intersect the bounding box along at least the x and y planes because t min-x 1706 is t max-y 1708. To perform ray-box intersection testing using a graphics processor, the graphics processor is configured to store an acceleration data structure that defines at least each bounding box to be tested. For acceleration using a bounding volume hierarchy, references to at least child nodes to the bounding boxes are stored.

[0175] (Bounding Volume Node Compression) For axis-aligned bounding boxes in 3D space, the accelerated data structures can store the lower and upper bounds of the bounding box in the third dimension. A software implementation can use 32-bit floating point numbers to store these bounds, totaling 2 x 3 x 4 = 24 bytes per bounding box. For an N-wide BVH node, N boxes and N child references must be stored. In total, the storage for a 4-wide BVH node, assuming 4 bytes per reference, is N*24 bytes + N*4 bytes for the child references, totaling (24+4)*N bytes, totaling 112 bytes for a 4-wide BVH node and 224 bytes for an 8-wide BVH node.

[0176] In one embodiment, the size of the BVH node is reduced by storing a single more accurate parent bounding box that encloses all child bounding boxes, and storing each child bounding box at a lower precision compared to its parent box. Depending on the usage scenario, different numbers of representations may be used to store the high precision parent bounding boxes and the low precision relative child bounds.

[0177] 18 is a block diagram illustrating an example quantized BVH node 1810, according to an embodiment. The quantized BVH node 1810 can include higher precision values ​​to define the parent bounding box of the BVH node. For example, parent_lower_x 1812, parent_lower_y 1814, parent_lower_z 1816, parent_upper_x 1822, parent_upper_y 1824, and parent_upper_z 1826 can be stored using single or double precision floating point values. The child bounding box values ​​for each child bounding box stored in the node can be quantized and stored as lower precision values, such as a fixed point representation for the bounding box values ​​defined for the parent bounding box. For example, child_lower_x 1832, child_lower_y 1834, and child_lower_z 1836, and child_upper_x 1842, child_upper_y 1844, and child_upper_z 1846 can be stored as lower precision fixed point values. In addition, a child reference 1852 can be stored for each child. The child reference 1852 can be an index into a table that stores the location of each child node, or can be a pointer to the child node.

[0178] As shown in Figure 18, single or double precision floating point values ​​may be used to store the parent bounding box, while M-bit fixed point values ​​may be used to encode the relative child bounding boxes. The data structure for the quantized BVH node 1810 of Figure 18 can be defined by the quantized N-wide BVH node shown in Table 1 below. [Table 1]

[0179] The quantized nodes in Table 1 achieve reduced data structure size by quantizing child values ​​while maintaining a baseline level of precision by storing higher precision values ​​for the extents of the parent bounding box. In Table 1, Real indicates a higher precision number representation (e.g., 32-bit or 64-bit floating point values) and UintM indicates a lower precision unsigned integer using M bits of precision used to represent fixed point numbers. Reference indicates a type used to represent a reference to a child node (e.g., a 4-byte index of an 8-byte pointer).

[0180] A typical instantiation of this technique might use 32-bit child references, single precision floating point values ​​for the parent bounds, and M=8 bits (1 byte) for the relative child bounds. This compressed node requires 6*4+6*N+4*N bytes. For a 4-wide BVH, this amounts to 64 bytes in total (compared to 112 bytes for the uncompressed version), and for an 8-byte BVH, this amounts to 104 bytes in total (compared to 224 bytes for the uncompressed version).

[0181] To traverse such a compressed BVH node, the graphics processing logic can decompress the relative child bounding boxes and then intersect with the decompressed nodes using standard techniques. The uncompressed lower bounds can then be obtained for each dimension x, y, and z. Equation 1 below shows the formula for obtaining the child lower_x value.

number

[0182] In the above equation 1, M represents the number of bits of precision for the fixed-point representation of the child bounds. The logic for decompressing the child data for each dimension of the BVH node can be implemented as shown in Table 2 below. [Table 2]

[0183] Table 2 illustrates the calculation of a floating-point value for the lower bound of a child bounding box based on a floating-point value for the extent of the parent bounding box and a fixed-point value for the child bounding box stored as an offset from the extent of the parent bounding box. The upper bound of the child may be calculated in a similar manner.

[0184] In one embodiment, stretch performance is improved by using the scaled parent bounding box size, e.g. (parent_upper_x-parent_lower_x) / (2 M-1 ) In such an embodiment, the extent of the child bounding box may be calculated according to the exemplary logic shown in Table 3. [Table 3]

[0185] Note that in an optimized version, the stretch / dequantization can be formulated as a MAD (multiply-and-add) instruction, and hardware support exists for such instructions. In one embodiment, the operations for each child node can be performed using SIMD / vector logic, allowing for simultaneous evaluation of each child within a node.

[0186] While the above approach works well for shader or CPU-based implementations, one embodiment provides specialized hardware configured to perform ray tracing operations including ray-box intersection tests using bounding volume hierarchies. In such an embodiment, the specialized hardware can be configured to store further quantized representations of the BVH node data and automatically dequantize such data when performing ray-box intersection tests.

[0187] FIG. 19 is a block diagram of a composite floating point data block 1900 for use by a quantized BVH node 1910 according to a further embodiment. In one embodiment, logic to support the composite floating point data block 1900 may be defined by special logic within the graphics processor, as opposed to a 32-bit single precision floating point or 64-bit double precision floating point representation of the parent bounding box extent. The composite floating point (CFP) data block 1900 may include a one-bit signed bit 1902, a variable-sized (E-bit) signed integer exponent 1904, and a variable-sized (K-bit) mantissa 1906. Multiple values ​​for E and K may be configurable by adjusting values ​​stored in configuration registers of the graphics processor. In one embodiment, values ​​for E and K may be independently configured within a range of values. In one embodiment, a fixed set of interrelated values ​​for E and K may be selected via a configuration register. In one embodiment, a single value for each of E and K is hard-coded into the graphics processor's BVH logic. The values ​​E and K allow the CFP data block 1900 to be used as a customized (e.g., special-purpose) floating-point data type that can be tailored to a data set.

[0188] Using the CFP data block 1900, a graphics processor can be configured to store bounding box data in quantized BVH nodes 1910. In one embodiment, the lower bounds of the parent bounding boxes (parent_lower_x 1912, parent_lower_y 1914, parent_lower_z 1916) are stored at a level of precision determined by the E and K values ​​selected for the CFP data block 1900. The level of precision of the stored values ​​for the lower bounds of the parent bounding boxes is typically set to a higher precision than the values ​​of the child bounding boxes (child_lower_x 1924, child_upper_x 1926, child_lower_y 1934, child_upper_y 1936, child_lower_z 1944, and child_upper_z 1946), which are stored as fixed point values. Scaled parent bounding box sizes are stored as powers of two (e.g., exp_x 1922, exp_y 1932, exp_z 1942). In addition, references for each child (e.g., child references 1952) can be stored. The size of the quantized BVH nodes 1910 can be scaled based on the width (e.g., number of children) stored at each node, and the amount of storage used to store the child references and bounding box values ​​for the child nodes increases with each additional node.

[0189] The logic for the implementation of the quantized BVH node of Figure 55 is shown in Table 4 below. [Table 4]

[0190] A compound floating-point data block (e.g., struct Float) can be defined to represent parent bounding box values, as shown in Table 4. The Float structure includes a 1-bit sign (int1 sign), an E-bit signed integer (intE exp) to store the power of 2 exponent, and a K-bit unsigned integer (uintK mantissa) to represent the mantissa used to store the high-precision bounds. For child bounding box data, M-bit unsigned integers (uintM child_lower_x / y / z; uintM child_upper_x / y / z) can be used to store fixed-point numbers to encode the relative child bounds.

[0191] For the example of E=8, K=16, M=8, using 32 bits for child references, the QuantizedNodeHW structure of Table 4 has a size of 52 bytes for a 4-wide BVH and 92 bytes for an 8-wide BVH, which is a reduction in structure size over the quantized nodes of Table 1 and a significant reduction in structure size over existing implementations. Note that for mantissa values ​​(K=16), one bit of the mantissa may be implied, reducing the storage requirement to 15 bits.

[0192] The layout of the BVH node structure in Table 4 allows for reduced hardware to perform ray-box intersection tests on child bounding boxes. The hardware complexity is reduced based on several factors. A smaller number of bits can be chosen for K because the relative child bounds add an additional M bits of precision. The scaled parent bounding box sizes are stored as powers of 2 (exp_x / y / z fields), which simplifies the calculations. Additionally, the calculations are refactored to reduce the size of the multipliers.

[0193] In one embodiment, the ray intersection logic of the graphics processor calculates the hit distance of the ray to the axis-aligned face to perform the ray-box test. The ray intersection logic can use the BVH node logic, including support for the quantized node structure of Table 4. The logic can calculate the distance to the lower bound of the parent bounding box using higher precision of the parent's lower bound and the quantized relative extent of the child box. Exemplary logic for the x-face calculation is shown below in Table 5. [Table 5]

[0194] Regarding the logic of Table 5, if single-precision floating-point precision is assumed to represent the ray, a 23-bit by 15-bit multiplier can be used, since the parent_lower_x value is stored with a 15-bit mantissa. The distance to the lower limit of the parent bounding box on the y and z planes can be calculated similarly to the calculation for dist_peartner_lower_x.

[0195] Using the parent lower bound, the intersection distance to the relative child bounding box can be calculated for the child bounding box, as illustrated by the calculations for dist_child_lower_x and dist_child_upper_x as in Table 5. The calculation of the dist_child_lower / upper_x / y / z values ​​can be performed using 23-bit by 8-bit multipliers.

[0196] 20 illustrates a ray-box intersection using quantized values ​​to define a child bounding box 5610 relative to a parent bounding box 2000, according to an embodiment. The ray-box intersection distance determination formula for the x-plane shown in Table 5 can be applied to determine the distance along the ray 2002 where the ray intersects the bounds of the parent bounding box 2000 along the x-plane. A location dist_parent_lower_x 2003 where the ray 2002 intersects the lower bounding surface 5604 of the parent bounding box 2000 can be determined. Based on dist_parent_lower_x 2003, a location dist_child_lower_x 2005 where the ray intersects the minimum bounding surface 2006 of the child bounding box 2010 can be determined. Further, based on dist_parent_lower_x 2003, dist_child_upper_x 2007 can be determined for where the ray intersects the maximum bounding plane 2008 of the child bounding box 2010. Similar determinations can be performed for each dimension in which the parent bounding box 2000 and the child bounding box 2010 are defined (e.g., along the y-axis and z-axis). The plane intersection distance can then be used to determine whether the ray intersects the child bounding box. In one embodiment, the graphics processing logic can determine intersection distances for multiple dimensions and multiple bounding boxes in parallel using SIMD and / or vector logic. Furthermore, at least a first portion of the calculations described herein may be performed on a graphics processor, while a second portion of the calculations may be performed on one or more application processors coupled to the graphics processor.

[0197] FIG. 21 is a flow diagram of the BVH decompression and traversal logic 2100 according to an embodiment. In one embodiment, the BVH decompression and traversal logic may reside in special purpose hardware logic of a graphics processor or may be executed by shader logic executing on the execution resources of the graphics processor. The BVH decompression and traversal logic 2100 may cause the graphics processor to perform operations to calculate a distance along a ray to a lower bounding surface of a parent bounding volume, as shown in block 2102. In block 2104, the logic may calculate a distance to a lower bounding surface of a child bounding volume based in part on the calculated distance to the lower bounding surface of the parent bounding volume. In block 2106, the logic may calculate a distance to an upper bounding surface of a child bounding volume based in part on the calculated distance to the lower bounding surface of the parent bounding volume.

[0198] At block 2108, the BVH stretch and traversal logic 2100 can determine a ray intersection for the child bounding volume based in part on the distance to the upper and lower bounding surfaces of the child bounding volume, where the intersection distance for each dimension of the bounding box is used to determine the intersection. In one embodiment, the BVH stretch and traversal logic 2100 determines the ray intersection for the child bounding volume by determining whether the maximum entrance surface intersection distance of the ray is less than or equal to the minimum exit surface distance. In other words, a ray intersects a child bounding volume when the ray enters the bounding volume along all defined surfaces before exiting the bounding volume along any of the defined surfaces. If the BVH stretch and traversal logic 2100 determines at 2110 that the ray intersects the child bounding volume, the logic can traverse the child node for the bounding volume to test the child bounding volumes within the child node, as shown in block 2112. At block 2112, node traversal can be performed and a reference to the node associated with the intersected bounding box can be accessed. The child bounding volume can become a parent bounding volume and the children of the intersected bounding volume can be evaluated. If the BVH decompression and traversal logic 2100 determines at 2110 that the ray does not intersect with a child bounding volume, then the branch of the bounding hierarchy associated with the child bounding volume is skipped, as shown at block 2114, because the ray does not intersect with a bounding volume until further down the subtree branch associated with the non-intersected child bounding volume.

[0199] (Further compression via coplanar bounding boxes) For any N-wide BVH using bounding boxes, a bounding volume hierarchy can be constructed such that each of the six sides of a 3D bounding box is shared by at least one child bounding box. For 3D co-planar bounding boxes, 6×log2 N bits can be used to indicate whether a given face of a parent bounding box is shared with a child bounding box. For N=4 for 3D co-planar bounding boxes, 12 bits are used to indicate the shared faces, with each of two bits being used to identify which of the four children reuses each potentially shared parent face. Each bit can be used to indicate whether a parent face is reused for a particular child. For 2-wide BVHs, for each face of a parent bounding box, six additional bits can be added to indicate whether a bounding box face (e.g., a side) is shared by a child. Although the concept of SPBBs can be applied to any number of dimensions, in one embodiment, the benefits of SPBBs are generally greatest for 2-wide (e.g., binary) SPBBs.

[0200] The use of shared surface bounding boxes can further reduce the amount of data stored when using BVH node quantization as described herein. In a 3D 2-wide BVH example, the six shared surface bits can reference min_x, max_x, min_y, max_y, min_z, and max_z for the parent bounding box. If the min_x bit is zero, the first child inherits the shared surface from the parent bounding box. For children that share a surface with the parent bounding box, the quantized value of that surface does not need to be stored, which reduces storage and decompression costs for the node. In addition, a higher precision value for that surface can be used for the child bounding box.

[0201] FIG. 22 is a diagram of an example two-dimensional shared plane bounding box 2200. The two-dimensional (2D) shared plane bounding box (SPBB) 2200 includes a left child 2202 and a right child 2204. In a 2D binary SPBPP, 4log22 additional bits can be used to indicate which of the four shared faces of the parent bounding box are shared, with a bit associated with each face. In one embodiment, a zero can be associated with the left child 2202 and a one can be associated with the right child, such that the shared plane bits for the SPBB 2200 are min_x=0, max_x=1, min_y=0, max_y=0 because the left child 2202 shares the lower_x, upper_y, and lower_y faces with the parent SPB 2200, and the right child 2204 shares the upper_x face.

[0202] FIG. 23 is a flow diagram of the shared-plane BVH logic 2300 according to an embodiment. The shared-plane BVH logic 2300 can be used to reduce the number of quantized values ​​stored for the lower and upper bounds of one or more child bounding boxes, reduce stretch / dequantization costs for a BVH node, and improve the accuracy of values ​​used in ray-box intersection tests for child bounding boxes of a BVH node. In one embodiment, as shown in block 2302, the shared-plane BVH logic 2300 includes defining a parent bounding box for a set of child bounding boxes such that the parent bounding box shares one or more faces with one or more child bounding boxes. The parent bounding box can be defined in one embodiment by selecting a set of existing axis-aligned bounding boxes for geometric objects in a scene and defining the parent bounding box based on the minimum and maximum extent of the set of bounding boxes in each face. For example, the top value for each face of the parent bounding box is defined as the maximum value for each plane in the set of child bounding boxes. At block 2304, the shared surface BVH logic 2300 can encode shared child faces for each face of a parent bounding box. As shown in block 2306, the shared surface BVH logic 2300 can inherit parent surface values ​​for child faces that have shared faces during ray-box intersection testing. The shared surface values ​​for the children can be inherited with higher precision and the parent surface values ​​can be stored in the BVH node structure, and generating and storing lower precision quantized values ​​for the shared faces can be bypassed.

[0203] FIG. 24 is a block diagram of a computing device 2400 including a graphics processor 2404 with bounding volume hierarchy logic 2424 according to one embodiment. The computing device 2400 can be a computing device such as the data processing system 100 in FIG. 1. The computing device 2400 can also be or be included in a communication device such as a set-top box (e.g., an Internet-based cable television set-top box, etc.), a global positioning system (GPS)-based device, etc. The computing device 2400 can also be or be included in a mobile computing device such as a mobile phone, a smartphone, a personal digital assistant (PDA), a tablet computer, a laptop computer, an e-reader, a smart television, a television platform, a wearable device (e.g., glasses, a watch, a bracelet, a smart card, jewelry, clothing, etc.), a media player, etc. For example, in one embodiment, computing device 2400 includes a mobile computing device that utilizes a system-on-chip ("SoC" or "SOC") integrated circuit ("IC") that integrates various hardware and / or software components of computing device 2400 on a single chip.

[0204] In one embodiment, the bounding volume hierarchy (BVH) logic 2424 includes logic for encoding a compressed representation of a bounding volume hierarchy and additional logic for decoding and interpreting the compressed representation of the bounding volume hierarchy. The BVH logic 2424 can work in conjunction with the ray tracing logic 2434 to perform hardware accelerated ray-box intersection testing. In one embodiment, the BVH logic 2424 is configured to encode multiple child bounding volumes for a reference bounding volume. For example, the BVH logic 2424 can encode the reference bounding volume and the child bounding volumes using upper and lower bounds in multiple directions, where the reference bounding volume is encoded using floating point values ​​and the child bounding volumes are encoded using fixed point values. The BVH logic 2424 can be configured to encode the reference bounding volume as a scaled extend of the bounds and the child bounding volumes using lower and upper bounds in multiple directions. In one embodiment, the BVH logic 2424 is configured to encode a node of a bounding volume hierarchy using multiple encoded child bounding volumes.

[0205] The ray tracing logic 2434 may operate at least in part in conjunction with the execution resources 2444 of the graphics processor 2404, and may include execution units and associated logic, such as logic within the graphics cores 580A-N of FIG. 5 and / or execution logic 600 illustrated in FIG. 6. A ray traversal may be performed through the bounding volume hierarchy to test if a ray intersects with the encoded child bounding volume of a node. The ray tracing logic 2434 may be configured to calculate the distance to all child bounding surfaces, calculating the bounding surface distance to test for ray bounding volume intersection by calculating the distance to the plane of the lower reference bounding surface and adding to that distance the arithmetic product of the reciprocal ray direction, the scaled extent of the reference bounding surface, and the relative child bounding surface location.

[0206] In one embodiment, a set of registers 2454 may be included to store configuration and operational data for the components of the graphics processor 2404. The graphics processor 2404 may additionally include a memory device configured as a cache 2414. In one embodiment, the cache 2414 is a rendering cache for performing rendering operations. In one embodiment, the cache 2414 may also include an additional level of a memory hierarchy, such as a last level cache stored in the embedded memory module 218 of FIG. 2.

[0207] As shown, in one embodiment, in addition to the graphics processor 2404, the computing device 2400 may further include any number and type of hardware and / or software components, such as, but not limited to, an application processor 2406, memory 2408, and input / output (I / O) sources 2410. The application processor 2406 may interact with a hardware graphics pipeline to share graphics pipeline functions, as illustrated with reference to FIG. 3. Processed data is stored in buffers within the hardware graphics pipeline, and state information is stored in memory 2408. The resulting image is then transferred to a display device for output via a display device, such as the display device 320 of FIG. 3. The display device may be of various types, such as a cathode ray tube (CRT), thin film transistor (TFT), liquid crystal display (LCD), organic light emitting diode (OLED) array, etc., and may be configured to display information to a user.

[0208] The application processor 2406 may include one or more processors, such as the processor 102 of FIG. 1, and may be a central processing unit (CPU) used at least in part to execute an operating system (OS) 2402 of the computing device 2400. The OS 2402 may act as an interface between a user and the hardware and / or physical resources of the computing device 2400. The OS 2402 may include driver logic 2422 for various hardware devices in the computing device 2400. The driver logic 2422 may include graphics driver logic 2423, such as the user mode graphics driver 1026 and / or the kernel mode graphics driver 1029 of FIG. 10. In one embodiment, the graphics driver logic 2423 may be used to configure the BVH logic 2424 and the ray tracing logic 2434 of the graphics processor 2404.

[0209] In some embodiments, the graphics processor 2404 may be part of the application processor 2406 (such as part of a physical CPU package), in which case at least a portion of the memory 2408 may be shared by the application processor 2406 and the graphics processor 2404, but at least a portion of the memory 2408 may be dedicated to the graphics processor 2404, or the graphics processor 2404 may have a separate store of memory. The memory 2408 may include a pre-allocated area of ​​a buffer (e.g., a frame buffer), but it should be understood by those skilled in the art that the embodiment is not so limited and that any memory accessible to the underlying graphics pipeline may be used. The memory 2408 may include various forms of random access memory (RAM) (e.g., SDRAM, SRAM, etc.), including applications that utilize the graphics processor 2404 to render desktop or 3D graphics scenes. A memory controller hub, such as the memory controller hub 116 of FIG. 1, may access the data in the memory 2408 and transfer it to the graphics processor 2404 for graphics pipeline processing. Memory 2408 may be made available to other components within computing device 2400. For example, any data received from various I / O sources 2410 of computing device 2400 (e.g., input graphics data) may be temporarily queued in memory 2408 before being manipulated by one or more processors (e.g., application processor 2406) in the implementation of a software program or application. Similarly, data that a software program determines should be transmitted from computing device 2400 to an external entity via one of the computing system interfaces or stored in an internal storage element is often temporarily queued in memory 2408 before it is transmitted or stored.

[0210] The I / O sources may include devices such as a touch screen, touch panel, touch pad, virtual or standard keyboard, virtual or standard mouse, port, connector, network device, or the like, and may be attached via an input / output (I / O) control hub (ICH) 130, as shown in FIG. 1. In addition, the I / O sources 2010 may include one or more I / O devices implemented for transferring data to and from the computing device 2400 (e.g., a networking adapter) or for large-scale non-volatile storage within the computing device 2400 (e.g., a hard disk drive). User input devices including alphanumeric and other keys may be used to communicate information and command selections to the graphics processor 2404. Another type of user input device is a cursor control device, such as a mouse, trackball, touch screen, touch pad, or cursor direction keys, which communicates directional information and command selections to the GPU and controls cursor movement on a display device. The camera and microphone array of the computing device 2400 may be utilized to observe gestures, record audio and video, and send and receive visual and voice commands.

[0211] I / O sources 2410 configured as a network interface may provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a cellular or mobile network (e.g., third generation (3G), fourth generation (4G), etc.), an intranet, the Internet, etc. The network interface may include, for example, a wireless network interface having one or more antennas. The network interface may include a wired network interface for communicating with a remote device via a network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

[0212] The network interface may provide access to a LAN, for example by conforming to the IEEE 802.11 standard, and / or the wireless network interface may provide access to a personal area network, for example by conforming to the Bluetooth standard. Other wireless network interfaces and / or protocols, including earlier or later version standards, may also be supported. In addition to or instead of communication via a wireless LAN standard, the network interface may provide wireless communication using, for example, a Time Division, Multiple Access (TDMA) protocol, a Global Systems for Mobile Communications (GSM) protocol, a Code Division, Multiple Access (CDMA) protocol, and / or any other type of wireless communication protocol.

[0213] It should be understood that smaller or more equipped systems than the above examples may be preferred for a particular implementation. Thus, the configuration of computing device 2400 may vary from implementation to implementation depending on numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances. Examples include (without limitation) a mobile device, a personal digital assistant, a mobile computing device, a smart phone, a mobile phone, a handset, a one-way pager, a two-way pager, a messaging device, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a handheld computer, a tablet computer, a server, a server array or server farm, a web server, a network server, an Internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, a multiprocessor system, a processor-based system, a home appliance, a programmable home appliance, a television, a digital television, a set-top box, a wireless access point, a base station, a subscriber station, a mobile network center, a radio network controller, a router, a hub, a gateway, a bridge, a switch, a machine, or a combination thereof.

[0214] (Apparatus and method for compressing leaf nodes of a bounding volume hierarchy) A downside of acceleration structures such as bounding volume hierarchies (BVHs) and kd-trees is that they require both time and memory to be constructed and stored. One way to reduce this overhead is to utilize some sort of compression and / or quantization of the acceleration data structures, which works particularly well for BVHs, which naturally lend themselves to conservative and progressive encoding. On the upside, this can significantly reduce the size of the acceleration structures, often halving the size of the BVH nodes. On the downside, compressing BVH nodes also incurs overhead, which can fall into a different category. First, there is a clear cost in decompressing each BVH node during traversal, second, especially for hierarchical encoding schemes, the need to keep track of parent information slightly complicates stacking operations, and third, conservatively quantizing the bounds means that the bounding boxes are somewhat less strict than decompressed boxes, causing a measurable increase in the number of nodes and primitives that must be traversed and intersected, respectively.

[0215] Compressing the BVH by local quantization is a known method to reduce its size. An n-wide BVH node contains the axis-aligned bounding boxes (AABBs) of its "n" children in single-precision floating-point format. Local quantization represents the "n" children AABBs relative to their parent's AABB and stores these values ​​in a quantized, e.g., 8-bit format, thereby reducing the size of the BVH node.

[0216] Local quantization of the entire BVH introduces multiple overhead factors because (a) the dequantized AABB is coarser than the original single-precision floating-point AABB, thereby introducing an additional traversal and intersection step for each ray, and (b) the dequantization operation itself is expensive and adds overhead to each ray traversal step. Due to these disadvantages, compressed BVHs are only used in specific application scenarios and have not been widely adopted.

[0217] One embodiment of the present invention employs a technique to compress leaf nodes for hair primitives in a bounding volume hierarchy. In particular, in one embodiment, several groups of oriented primitives are stored with a parent bounding box, eliminating the storage of child pointers in the leaf nodes. An oriented bounding box is then stored for each primitive using 16-bit coordinates that are quantized with respect to the corners of the parent box. Finally, quantized normals are stored for each primitive group to indicate direction. This approach can result in a significant reduction in bandwidth and memory footprint for BVH hair primitives.

[0218] In some embodiments, BVH nodes are compressed by storing a parent bounding box using lower precision and encoding N child bounding boxes (e.g., 8 children) relative to that parent bounding box. The disadvantage of applying this idea to each node of the BVH is that some decompression overhead is introduced at each node when traversing rays through this structure, which can reduce performance.

[0219] To address this issue, one embodiment of the present invention uses compression nodes only at the lowest level of the BVH, which provides the advantage of higher BVH levels operating at optimal performance (i.e., they are the larger the boxes are, the more frequently they are touched, but there are very few of them), and compression at the lower / lowest levels is also very effective, since most of the data in the BVH is at the lowest level.

[0220] In addition, in one embodiment, quantization is also applied to BVH nodes that store oriented bounding boxes. As discussed below, the computations are somewhat more complex than for axis-aligned bounding boxes. In one implementation, the use of compressed BVH nodes with oriented bounding boxes is combined with the use of compressed nodes only at the lowest level (or lower) of the BVH.

[0221] Thus, one embodiment improves upon the fully compressed BVH by introducing a single dedicated layer of compressed leaf nodes while using regular decompressed BVH nodes for the interior nodes. One motivation behind this approach is that almost all of the compression savings come from the lowest level BVH (which accounts for the majority of all nodes, especially for 4-wide and 8-wide BVHs), while most of the overhead comes from the interior nodes. As a result, introducing a single layer of dedicated "compressed leaf nodes" results in nearly the same compression gains (and in some cases even better) as the fully compressed BVH, while maintaining nearly the same traversal performance as the decompressed BVH.

[0222] In one embodiment, the techniques described herein are integrated into traversal / intersection circuitry within a graphics processor, such as GPU 2505 illustrated in Figure 25, which includes dedicated sets of graphics processing resources arranged into multi-core groups 2500A-2500N. Although details of only a single multi-core group 2500A are provided, it will be understood that the other multi-core groups 2500B-2500N may include the same or similar sets of graphics processing resources.

[0223] As shown, multi-core group 2500A may include a set of graphics cores 2530, a set of tensor cores 2540, and a set of ray tracing cores 2550. A scheduler / dispatcher 2510 schedules and dispatches graphics threads for execution on the various cores 2530, 2540, 2550. A set of register files 2520 store operand values ​​used by the cores 2530, 2540, 2550 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and / or floating point data elements), and tile registers for storing tensor / matrix values. In one embodiment, the tile registers are implemented as a combined set of vector registers.

[0224] One or more level 1 caches and texture units 2560 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc. locally within each multicore group 2500A. A level 2 (L2) cache 2580 shared by all or a subset of multicore groups 2500A-2500N stores graphics data and / or instructions for multiple simultaneous graphics threads. One or more memory controllers 2570 couple the GPU 2505 to memory 2598, which may be system memory (e.g., DRAM) and / or dedicated graphics memory (e.g., GDDR6 memory).

[0225] Input / output (I / O) circuitry 2595 couples GPU 2505 to one or more I / O devices 2590, such as a digital signal processor (DSP), a network controller, or a user input device. An on-chip interconnect may be used to couple I / O devices 2590 to GPU 2505 and memory 2598. One or more I / O memory management units (IOMMUs) 2570 of I / O circuitry 2595 directly couple I / O devices 2590 to system memory 2598. In one embodiment, IOMMU 2570 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 2598. In this embodiment, I / O devices 2590, CPU 2599, and GPU 2505 may share the same virtual address space.

[0226] In one embodiment, IOMMU 2570 supports virtualization, in which case it may use a first set of page tables to map guest / graphics virtual addresses to guest / graphics physical addresses and a second set of page tables to map guest / graphics physical addresses to system / host physical addresses (e.g., in system memory 2598).

[0227] In one embodiment, CPU 2599, GPU 2505, and I / O devices 2590 are integrated onto a single semiconductor chip and / or chip package. The illustrated memory 2598 may be integrated onto the same chip or may be coupled to memory controller 2570 via an off-chip interface. In one embodiment, memory 2598 includes GDDR6 memory that shares the same virtual address space as other physical system-level memory, although the underlying principles of the invention are not limited to this particular embodiment.

[0228] In one embodiment, tensor cores 2540 include multiple execution units specifically designed to perform matrix operations, which are fundamental computational operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inference. Tensor cores 2540 may perform matrix operations using a variety of operand precisions, including single-precision floating point (e.g., 32-bit), half-precision floating point (e.g., 16-bit), integer word (16-bit), byte (8-bit), and half-byte (4-bit). In one embodiment, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames to construct a high-quality final image.

[0229] In one embodiment, the ray tracing core 2550 accelerates ray tracing operations for both real-time and non-real-time ray tracing implementations. For example, with respect to an embodiment of the present invention, the ray tracing core 2550 may include circuitry / logic for compressing leaf nodes of the BVH. In addition, the ray tracing core 2550 may include ray tracing / intersection circuitry for performing ray tracing using the BVH and identifying intersections between rays and primitives enclosed within the BVH volume. The ray tracing core 2550 may include circuitry for depth testing and culling (e.g., using a Z-buffer or similar configuration). Using a dedicated ray tracing core 2550 for traversal / intersection operations significantly reduces the load on the graphics core 2530. Without these ray tracing cores 2550, traversal and intersection operations would be performed using shaders running on the graphics cores 2530 which would consume most of the graphics processing resources of the GPU 2505, making real-time ray tracing impractical.

[0230] 26 illustrates an example ray tracing engine 2600 for performing the leaf node compression and decompression operations described herein. In one embodiment, the ray tracing engine 2600 includes the circuitry of one or more of the ray tracing cores 2550 described above. Alternatively, the ray tracing engine 2600 may be implemented on a core of the CPU 2599 or other type of graphics core (e.g., Gfx core 2530, tensor core 2540, etc.).

[0231] In one embodiment, a ray generator 2602 generates rays that a traversal / intersection unit 2603 traces through a scene containing multiple input primitives 2606. For example, an app such as a virtual reality game may generate a stream of commands that generate the input primitives 2606. The traversal / intersection unit 2603 traverses the rays through a BVH 2605 generated by a BVH builder 2607 and identifies hit points where the rays intersect with one or more of the primitives 2606. Although illustrated as a single unit, the traversal / intersection unit 2603 may include a traversal unit coupled to a separate intersection unit. These units may be implemented with circuitry, software / commands executed by a GPU or CPU, or any combination thereof.

[0232] (node ​​compression / expansion) In one embodiment, the BVH processing circuitry / logic 2604 includes a BVH builder 2607 that generates a BVH 2605 as described herein based on spatial relationships between primitives 2606 in a scene. In addition, the BVH processing circuitry / logic 2604 includes a BVH compressor 2609 and a BVH decompressor 2609 for compressing and decompressing, respectively, leaf nodes as described herein. The following description focuses on an 8-wide BVH (BVH8) for illustrative purposes.

[0233] As shown in Figure 27, one embodiment of a single 8-wide BVH node 2700A includes eight bounding boxes 2701-2708 and eight (64-bit) child pointers / references 2710 that point to the bounding box / leaf data 2701-2708. In one embodiment, the BVH compressor 2625 performs an encoding in which the eight child bounding boxes 2701A-2708A are expressed relative to the parent bounding box 2700A and quantized to 8-bit uniform values ​​shown as bounding box leaf data 2701B-2708B. The quantized 8-wide BVH, QBVH8 node 2700B, is encoded by the BVH compressor 2725 using start and range values ​​stored as two 3-dimensional single precision vectors (2x12 bytes). The eight quantized child bounding boxes 2701B-2708B are stored as 2 x 8 bytes (48 bytes total) for the lower and upper bounding box bounds per dimension. Note that this layout differs from existing implementations because the ranges are stored completely exactly, which generally provides tighter bounds but requires more space.

[0234] In one embodiment, the BVH decompressor 2626 decompresses the QBVH8 node 2700B as follows: i +(byte-to-float)QBVH8.lower i *QBVH8.extend iwhich requires five instructions per dimension and box on the CPU 4099: two loads (start, extend), a byte-to-int load + upconversion, an int-to-float conversion, and one multiply-add. In one embodiment, the decompression is performed in parallel for all eight quantized child bounding boxes 2701B-2708B using SIMD instructions, which adds an overhead of about 10 instructions to the ray-node intersection test, making it at least twice as expensive as a standard decompression node. In one embodiment, these instructions are executed on the CPU 4099 core. Alternatively, an equivalent set of instructions is executed by the ray tracing core 4050.

[0235] Without pointers, a QBVH8 node requires 72 bytes while an expanded BVH8 node requires 192 bytes, resulting in a reduction factor of 2.66x. With 8 (64-bit) pointers, the reduction factor drops to 1.88x, which makes it necessary to deal with the storage costs of handling leaf pointers.

[0236] (Leaf-level compression and layout) In one embodiment, when compressing only the leaf layer of a BVH8 node into a QBVH8 node, all child pointers of the eight children 2701-2708 reference only leaf primitive data. In one implementation, this fact is exploited by storing all referenced primitive data immediately after the QBVH8 node 2700B itself, as shown in FIG. 27. This allows the full 64-bit child pointers 2710 of QBVH8 to be reduced to only 8-bit offsets 2722. In one embodiment, if the primitive data is fixed size, offsets 2722 are skipped entirely, since they can be calculated directly from the index of the intersected bounding box and the pointer to the QBVH8 node 2700B itself.

[0237] (BVH Builder changes) When using a top-down BVH8 builder, compressing only the BVH8 leaf level requires only minor changes to the build process. In one embodiment, these build changes are implemented in the BVH builder 2607. During the recursive build phase, the BVH builder 2607 tracks whether the current number of primitives is below a certain threshold. In one implementation, N×M is the threshold, where N refers to the width of the BVH and M is the number of primitives in the BVH leaf. For BVH8 nodes and, for example, four triangles per leaf, the threshold is 32. Thus, for all subtrees with less than 32 primitives, the BVH processing circuitry / logic 2604 enters a special code path where it continues the surface area heuristic (SAH) based splitting process but produces a single QBVH8 node 2700B. When the QBVH8 node 2700B is finally created, the BVH compressor 2609 then collects all referenced primitive data and copies it immediately after the QBVH8 node.

[0238] (Traversal) The actual BVH8 traversal performed by the ray tracing core 2750 or CPU 2799 is only slightly affected by the leaf-level compression. Essentially, the leaf-level QBVH8 node 2700B is treated as an extended leaf type (e.g., it is marked as a leaf). This means that normal BVH8 top-down traversal continues until the QBVH node 2700B is reached. At this point, a single ray-QBVH node intersection is performed, and for all its intersected children 2701B-2708B, the respective leaf pointers are reconstructed and a regular ray primitive intersection is performed. Interestingly, ordering the QBVH intersected children 2701B-2708B based on intersection distance may not provide any measurable benefit, since in most cases only a single child is intersected by the ray anyway.

[0239] (Leaf data compression) One embodiment of the leaf-level compression scheme allows even lossless compression of the actual primitive leaf data by extracting common features. For example, triangles within a compressed leaf BVH (CLBVH) node are very likely to share properties such as vertices / vertex indices and the same object ID. By storing these shared properties only once per CLBVH node and using a small local byte-sized index for the primitives, memory consumption is further reduced.

[0240] In one embodiment, the technique for exploiting common spatially coherent geometric features within the BVH leaves is also used for other more complex primitive types. Primitives such as hair segments are likely to share a common orientation per BVH leaf. In one embodiment, the BVH compressor 2609 implements a compression scheme that takes this common directional property into account to efficiently compress oriented bounding boxes, which has been shown to be very useful for bounding long diagonal primitive types.

[0241] The leaf-level compressed BVH described herein introduces BVH node quantization only at the lowest BVH level, thus allowing additional memory reduction optimizations while maintaining the traversal performance of the decompressed BVH. Because only the BVH nodes at the lowest level are quantized, all of their child pointers to leaf data 2701B-2708B may be stored contiguously in a block of memory or one or more cache lines 2698.

[0242] This idea can also be applied to hierarchies that use oriented bounding boxes (OBBs), which are typically used to speed up rendering of hair primitives.To illustrate one particular embodiment, the memory reduction in the typical case of a standard 8-wide BVH across triangles is evaluated.

[0243] The layout of an 8-wide BVH node 2700 is represented by the following core sequence: [Table 6] This requires 276 bytes of memory. A standard 8-wide quantization node layout may be defined as follows: [Table 7] It requires 136 bytes.

[0244] Since only quantized BVH nodes are used at the leaf level, all child pointers actually point to leaf data 2701A-2708A. In one embodiment, by storing quantized node 2700B and all leaf data 2701B-2708B and its children point within a single contiguous block of memory 2698, the eight child pointers in quantized BVH node 2700B are eliminated. Saving child pointers reduces the quantized node layout to: [Table 8] It only requires 72 bytes. Because of the contiguous layout in the memory / cache 2698, the child pointer of the ith child can be simply calculated as follows: childPtr(i)=addr(QBVH8NodeLeaf)+sizeof(QBVH8NodeLeaf)+i*sizeof(LeafDataType).

[0245] Since the lowest level nodes of the BVH account for more than half of the total size of the BVH, only the leaf-level compression described herein results in a reduction of 0.5+0.5*72 / 256=0.64x of the original size.

[0246] In addition, the overhead of having coarser bounds and the cost of stretching the quantized BVH nodes themselves is incurred only at the BVH leaf levels (as opposed to at all levels when the entire BVH is quantized), thus the often very significant traversal and intersection overhead due to the coarse bounds (introduced by quantization) is largely avoided.

[0247] Another advantage of embodiments of the present invention is improved hardware and software prefetching efficiency, which results from the fact that all leaf data is stored in a relatively small contiguous block of memory or a cache line.

[0248] Because geometry at the BVH leaf level is spatially coherent, all primitives referenced by a QBVH8NodeLeaf node are very likely to share common properties / characteristics, such as an objectID, one or more vertices, etc. As a result, one embodiment of the present invention further reduces storage by eliminating primitive data duplication. For example, primitives and associated data may be stored only once per QBVH8NodeLeaf node, thereby further reducing memory consumption for leaf data.

[0249] (Quantized Oriented Bounding Box (OBB) at BVH leaf level) The effective bounding of the hair primitive is described below as an example of the significant memory reduction achieved by exploiting common geometry properties at the BVH leaf level. To accurately bound the hair primitive, which is a long but thin structure oriented in space, a well-known approach is to compute an oriented bounding box to tightly bound the geometry. First, a coordinate space aligned with the hair direction is computed. For example, the z-axis may be determined to point in the hair direction, while the x- and y-axes are perpendicular to the z-axis. This oriented space can then be used to tightly bound the hair primitive using a standard AABB. Intersecting a ray with such an oriented bound requires first transforming the ray into oriented space and then performing a standard ray / box intersection test.

[0250] The problem with this approach is memory usage: the transformation to oriented space requires 9 floating point values, while storing the bounding box requires an additional 6 floating point values, generating a total of 60 bytes.

[0251] In one embodiment of the present invention, the BVH compressor 2625 compresses this oriented space and the bounding boxes for multiple hair primitives that are spatially close to each other. These compressed bounds are then stored in a compressed leaf level, allowing the hair primitives stored inside the leaf to be tightly bounded. The following approach is used in one embodiment to compress the oriented bounds: The oriented space is compressed by a set of mutually orthogonal normalized vectors v x , v y and v z Transforming a point ρ into that space works by projecting it onto these axes.

number

[0252] Vector ν x , v y and v z When v is normalized, its components are in the range [-1,1]. Therefore, these vectors are quantized using 8-bit signed fixed-point numbers, rather than using 8-bit signed integers and a constant scale. In this way, the quantized v x ',ν y ' and ν z This technique reduces the memory required to encode the oriented space from 36 bytes (9 floating point values) to 9 bytes (9 fixed point numbers, 1 byte each).

[0253] In one embodiment, the memory consumption of the oriented space is further reduced by exploiting the fact that all vectors are mutually orthogonal. Thus, two vectors (e.g., ρ y ' and ρ z ') and ρ x '=cross(ρ y ',ρ z '), further reducing the storage requirement to only 6 bytes.

[0254] What remains is to quantize the AABBs in the quantized oriented space. The problem here is that (e.g., dot(ν x The drawback is that projecting the point ρ onto the compressed coordinate axis of that space (by computing ρ') potentially results in a large range of values ​​(because the value ρ is typically encoded as a floating-point number), making it necessary to encode the bounds using floating-point numbers, reducing the potential savings.

[0255] To solve this problem, one embodiment of the present invention first transforms the hair primitives into space whose coordinates are in the range [0,1 / √3]. This may be done by determining the world-space axis-aligned bounding box b of the hair primitives, and then using a transform T that first translates left by b.lower, then scales by 1 / max(b.size.z,b.size.ybsize.z) in each coordinate.

number

[0256] In one embodiment, this transformed geometry is expressed as a quantized vector ρ y ', ρ y ' or ρ z ' stays inside the range [0,1 / √3] so that the projection of the transformation points onto ' stays inside the range [-1,1]. This means that the AABB of the curved geometry may be quantized when transformed with T and then transformed into the quantized oriented space. In one embodiment, 8-bit signed fixed-point arithmetic is used. However, for precision reasons, 16-bit signed fixed-point numbers may be used (e.g., encoded using a 16-bit signed integer and a constant scale). This reduces the memory requirement for encoding an axis-aligned bounding box from 24 bytes (6 floating point values) to only 12 bytes (6 words) plus the offset b.lower (3 floats) and scale (1 float) shared for multiple hair primitives.

[0257] For example, by bounding eight hair primitives, this embodiment reduces memory consumption from 8*60 bytes=480 bytes to only 8*(6+12)+3*4+4=160 bytes, a factor of three reduction. Intersecting a ray with these quantized oriented bounds involves first transforming the ray with the transform T and then applying the quantized v x ',ν y ' and ν zIt works by casting a ray with '. Finally, the ray is intersected with the quantized AABB.

[0258] The table in Figure 29 shows memory consumption (in MB) and total rendering performance (in fps) for one embodiment of the present invention (CLBVH) implemented on the Intel Embree architecture, including Embree's standard BVH8 (baseline) and Embree's fully compressed QBVH8 variant, in a typical two-in-two Embree configuration, i.e., best performance (SBVH+pre-collected triangle data) and lowest memory consumption (BVH+triangle index). Generally speaking, in its two possible configurations ("Fast" and "Compact"), an embodiment of the present invention has the same memory savings of Embree's QBVH with much lower performance impact ("Fast"), or achieves much better compression with about the same performance impact ("Compact").

[0259] The table in Figure 30 illustrates memory consumption (in MB), traversal statistics, and overall performance for two Embree BVH configurations: the best performing (SBVH + pre-collected triangle data) and the lowest memory consumption (BVH + triangle index). One embodiment of the present invention (CLBVH) achieves similar or sometimes even greater memory savings than a fully compressed BVH, while reducing runtime overhead to only a few percent.

[0260] One embodiment utilizes a modified version of the Embree3.0

[11] CPU ray tracing framework. As a comparison framework, the publicly available Proray path tracer[1] was used. For benchmarking, the path tracer was set to pure diffuse path tracing (max 8 bounces) while each CPU HW thread traces a single ray. For this benchmark, 15-20% of the time is spent on shading. The hardware platform setup is a dual socket Xeon workstation with 2x28 cores and 96GB memory. As benchmark scenes, four different models with complexities ranging from 10M to 350M triangles were tested (using many different camera positions). Performance and memory consumption were measured for two setups, namely "best performance" and "lowest memory consumption". These two modes required different BVH settings and primitive layouts. That is, the first pre-gathering packs all triangles per BVH leaf into a compact layout and uses a BVH with spatial partitioning (SBVH), while the second mode simply stores vertex indices per triangle and uses a standard BVH without spatial partitioning.

[0261] For best performance, the table in Figure 30 shows that the overhead of decompressing BVH nodes reduces rendering performance by 10-20%. Instead, the CLBVH approach only results in a 2-4% slowdown compared to fully compressed BVH, while providing a similar or sometimes even slightly larger size reduction of BVH nodes (43-45%). The size of the primitive data is unchanged. In terms of total size (BVH + leaf primitive data), these embodiments provide a similar reduction as fully compressed BVH of 8-10%.

[0262] Reducing the memory consumption of BVH nodes is more efficient in memory setups where the size of primitive data is smaller with respect to the size of the BVH nodes (storing only vertex indices instead of the complete pre-collected vertices). The total reduction in memory consumption increases to 16-24% when using fully compressed BVH nodes or the CLBVH approach. However, the CLBVH approach has only 0-3.7% runtime overhead, while for fully compressed BVH nodes the overhead ranges from 7-14%.

[0263] To achieve maximum memory reduction, we employ a lossless leaf data compression scheme for the CLBVH approach (see above). This CLBVH* variant has a larger runtime overhead than CLBVH, but allows us to reduce the leaf data (vertex indices per triangle, object IDs, etc.) size by only 15-23%, thereby increasing the total size reduction to 26-37% compared to the uncompressed baseline.

[0264] (References) [1] Attila T. Afra, Carsten Benthin, Ingo Wald, and Jacob Munkberg. 2016. Local Shading Coherence Extraction for SIMD-Efficient Path Tracing on CPUs. In Proceedings of High Performance Graphics (HPG '16). Eurographics Association, 119-128.

[0265] [2] Holger Dammertz, Johannes Hanika, and Alexander Keller. 2008. Shallow Bounding Volume Hierarchies for Fast SIMD Ray Tracing of Incoherent Rays. In Computer Graphics Forum (Proc. 19 thEurographics Symposium on Rendering). 1225-1234.

[0266] [3] Manfred Ernst and Gunter Greiner. 2008. Multi Bounding Volume Hierarchies. In Proceedings of the 2008 IEEE / EG Symposium on Interactive Ray Tracing. 35-40.

[0267] [4] Vlastimil Havran. 2001. Heuristic Ray Shooting Algorithms. Ph.D. Dissertation. Faculty of Electrical Engineering, Czech TU in Prague.

[0268] [5] Sean Keely. 2014. Reduced Precision for Hardware Ray Tracing in GPUs. In Proceedings of the Conference on High Performance Graphics 2014.

[0269] [6] Christian Lauterbach, Sung-Eui Yoon, Ming Tang, and Dinesh Manocha. 2008. ReduceM: Interactive and Memory Efficient Ray Tracing of Large Models. Computer Graphics Forum 27, 4 (2008), 1313-1321.

[0270] [7] Jeffrey Mahovsky and BrianWyvill. 2006. Memory-Conserving Bounding Volume Hierarchies with Coherent Raytracing. Computer Graphics Forum 25, 2 (June 2006).

[0271] [8] S.G. Parker, J. Bigler, A. Dietrich, H. Friedrich, J. Hoberock, D. Luebke, D. McAllister, M. McGuire, K. Morley, A. Robison, and others. 2010. OptiX: a general purpose ray tracing engine. ACM Transactions on Graphics (TOG) 29, 4 (2010).

[0272] [9] Benjamin Segovia and Manfred Ernst. 2010. Memory Efficient Ray Tracing with Hierarchical Mesh Quantization. In Graphics Interface 2010. 153-160.

[0273]

[10] Ingo Wald, Carsten Benthin, and Solomon Boulos. 2008. Getting Rid of Packets: Efficient SIMD Single-Ray Traversal using Multi-branching BVHs. In Proc. Of the IEEE / EG Symposium on Interactive Ray Tracing. 49-57.

[0274]

[11] Ingo Wald, Sven Woop, Carsten Benthin, Gregory S. Johnson, and Manfred Ernst. 2014. Embree: A Kernel Framework for Efficient CPU Ray Tracing. ACM Transactions on Graphics 33, 4, Article 143 (2014), 8 pages.

[0275]

[12] Henri Ylitie, Tero Karras, and Samuli Laine. 2017. Efficient Incoherent Ray Traversal on GPUs Through Compressed Wide BVHs. In Eurographics / ACM IGGRAPH Symposium on High Performance Graphics. ACM.

[0276] (Apparatus and method for motion blur using dynamic quantization grid) As mentioned above, motion blur may be used to simulate the effect of objects moving in a scene while the camera shutter is open. Simulating this effect results in a directed blur of the moving objects, which makes the animation appear smooth when it is played back. Rendering motion blur requires random sampling of the time for each ray path evaluated, and averaging over many of these paths results in the desired blur effect. To implement this technique, the underlying ray tracing engine must be able to trace rays through the scene at any time within the camera shutter interval. This requires encoding the motion of geometric objects in the spatial acceleration structures used for ray tracing.

[0277] In practice, such a data structure is constructed by building a bounding volume hierarchy (BVH) on the linear motion segments of a triangle, where the vertices of the triangle are simply linearly blended from the start time to the end time. Using many such motion segments makes it possible to encode complex motion during a camera shutter interval by bounding the motion using linear bounds. These linear bounds store bounding boxes for the start and end times of this motion, so that linearly interpolating these bounds to any time in between properly bounds the geometry at that particular time.

[0278] For ray tracing hardware implementation, it is important that individual BVH nodes consume as little memory as possible to reduce node fetching bandwidth. In one embodiment, a local per-node quantization of the bounding boxes of all children of a wide BVH node is applied. In particular, the quantization grid of a wide BVH node encodes the bounding box of each child using grid coordinates with a small number of bits (e.g., 8 bits vs. 32 bits in full floating-point precision).

[0279] One embodiment extends this technique to linear bounds for motion blur by storing quantized bounds for the start and end using this quantization scheme for each child. However, due to the fast motion of highly detailed geometry, this naive extension is prone to performance issues. The problem is that a small triangle that moves far relative to its size causes the BVH node to store a very large, and therefore coarse, quantization grid, which cannot properly combine small triangle configurations.

[0280] One embodiment of the present invention solves this problem by not using a static quantization grid (as in current implementations), but a dynamic quantization grid that moves according to the movement of bounded children nodes. This embodiment exploits the fact that adjacent geometries typically move in very similar ways, and thus children of a BVH node stay reasonably close to each other during motion, and often move in the same direction.

[0281] This property is exploited in one implementation by determining a fixed-range quantization grid that moves linearly along the common motion of the BVH node's children. The linear bounds of each child can now be mapped to this moving quantization grid, because the residual motion obtained by subtracting the linear grid motion from the linear child motion is still a linear motion from which the linear quantized bounds can be directly derived.

[0282] The advantage of this technique is that the extent of the moving interpolation grid only needs to be large enough to cover all of the geometry at the start when it is placed at the start grid location, and all of the geometry at the end when it is placed at the end grid location. Thus, the size depends on the approximate size of the geometry contained within the start and end BVH nodes, rather than the volume spanned by the entire animation path. As a result, the quantization grid can be much smaller, reducing storage requirements.

[0283] Figure 31 illustrates an implementation of a naive extension of quantized bounding boxes to motion blurred triangles 3101-3103. A BVH node is assumed to have the three illustrated triangles 3101-3103 as children moving from left to right position as shown. Thus, the quantization grid 3100 for this BVH node over the entire motion is large and can only coarsely combine triangles at the beginning and end.

[0284] FIG. 32 illustrates the change used in an embodiment of the present invention using a smaller quantization grid that binds the same triangles 3201-3203 significantly tighter. In particular, the starting quantization grid 3200A is transformed to the ending quantization grid 3200B based on the detected motion of the triangles 3201-3203 from left to right. The quantization grids 3200A-B are linearly shifted along the common motion of the children of the BVH node. Here, the linear bounds of each child can be mapped to this shifted quantization grid 3200A-3200B because the residual motion obtained by subtracting the linear grid motion from the linear child motion is still a linear motion that may directly derive the linear quantized bounds.

[0285] Figure 33 illustrates one embodiment of an architecture for implementing the motion blur techniques described herein. In operation, the BVH processor 3304 constructs a BVH 3300 based on a current set of input primitives 3309 for a graphics scene. A ray generator 3301 generates rays that traversal circuitry 3305 traverses the BVH 3307. Intersection circuitry 3310 identifies ray-primitive intersections to generate hits 3315 that are used for further processing (e.g., generating secondary rays based on material specifications, etc.). One or more shaders may perform specified shader operations to render an image frame.

[0286] In one embodiment, the motion blur processing logic 3312 implements the motion blur techniques described herein based on the detected movement of graphics primitives in the BVH nodes and the grid data 3318. In one embodiment, a quantization grid motion evaluator 3314 determines the motion of a quantization grid over a specified time period that the motion blur processing logic 3312 uses to perform its motion blur operations. The motion blur processing logic 3312 may be implemented as program code (e.g., an executable shader), circuitry, or using a combination of circuitry and program code. The underlying principles of the present invention are not limited to any particular implementation of the motion blur processing logic 3312.

[0287] One embodiment of a motion blur processing method is illustrated in Figure 34. This method may be implemented in the context of the architectures described above, but is not limited to any particular architecture.

[0288] At 3400, a bounding volume hierarchy (BVH) is generated including hierarchically arranged BVH nodes based on the input primitive. At 3401, a quantization grid is generated including a set of BVH nodes, each BVH node including one or more child nodes. The motion of the quantization grid is determined at 3402 based on the detected motion of the child nodes of a particular BVH node. At 3404, the linear bounds of each child node are mapped to the moving quantization grid. In one embodiment, to perform the mapping, one or more residual motion values ​​are obtained by subtracting the linear quantization grid motion from the linear child node motion. A linear quantized bound is then derived from the residual motion values.

[0289] If another BVH node's child nodes need to be processed and determined in 3404, the process returns to 3401 where a new quantization for the current BVH node is calculated. If not, the process ends.

[0290] Additional details about one embodiment of the present invention will now be provided, however it should be noted that the underlying principles of the present invention are not limited to these specific details.

[0291] In one embodiment, the interpolation grid data 3318 includes a start location (grid_start), an end location (grid_end), and a size of the grid (grid_size) that is the same for all time values ​​(i.e., as the grid is moved based on the movement of primitives in the scene). In one embodiment, all of these grid properties are stored as 3D vectors.

[0292] The quantized grid motion estimator 3314 represents the grid motion as:

number

number

[0293] This is also linear motion. In one embodiment, the motion quantization grid motion evaluator 3314 transforms the linear bounds of the triangular motion bounds (time) into grid coordinate space to obtain the residual motion, residual_bounds(time), for the moving grid.

number

[0294] So the grid relative bounds of the starting triangle are residual_bounds_start = (bounds_start - grid_start) / grid_size and the ending grid relative bounds are residual_bounds_end = (bounds_end - grid_end) / grid_size. The residual motion for the moving grid is simply a linear blend of these residual_bounds_start and residual_bounds_end positions. As a result, the linear bounds for the moving grid move linearly within the grid itself.

[0295] Note that this embodiment only obtains residual linear motion because the grid_size is not linearly blended, but there is only one fixed grid_size. If the grid_size were also to vary linearly, then the Quantized Grid Motion Estimator 3314 would determine a product of two lerp operations that does not decompose into a sum of two lerps.

[0296] The residual bounds resistal_bounds_start and resid_bounds_end can be easily quantized using a quantization grid at the start and end positions to obtain the quantized residual bounds quantized_residual_bounds_start and quantized_resid_bounds_end with corresponding linear interpolation.

number

[0297] To obtain these world-space dequantized bounds, the Quantization Grid Motion Estimator 3314 blends the quantization boundaries, scales them by the grid_size factor, and then adds the blended grid positions.

number

[0298] To intersect these bounds with a line of intersection having the linear equation org+t*dir, the distance to the bounding surface is determined.

number

[0299] This provides the distances to the three lower bounding surfaces and the three upper bounding surfaces, which are then used by the intersection circuitry 3310 to test whether the bounds are collided using a ray / box test.

[0300] In one embodiment, the processing required for the distance calculations is reduced using the techniques described above (i.e., stretching and traversing the bounding volume hierarchy), which include reducing the complexity by using a higher precision distance calculation that is shared among all children of a node, and adding some corrections that are determined using reduced precision quantized bounds.

number

[0301] The first term, (grid_base(time)-org)*rcp(dir), is determined once for all children because it depends only on the quantization grid. The second term, quantized_residual_bounds(time)*grid_size*rcp(dir), is determined for each child. However, if the interpolation of the quantized bounds produces a lower precision output and grid_size is chosen as a power of two, this term is only a few bits times the floating point number rcp(dir), which is also cheap to implement in hardware.

[0302] In one embodiment, the computational complexity of the first term is further reduced as follows:

number

[0303] Statistical evaluation of the above embodiment on scenes with many small triangles and large motion shows that it reduces the number of intersection steps per ray by more than an order of magnitude compared to a naive quantization approach.

[0304] In embodiments, the terms "engine" or "module" or "logic" may refer to, be a part of, or include application specific integrated circuits (ASICs), electronic circuits, processors (shared, dedicated, or groups), and / or memories (shared, dedicated, or groups) that execute one or more software or firmware programs, combinatorial logic circuits, and / or other suitable components that provide the functionality described above. In embodiments, an engine, module, or logic may be implemented in firmware, hardware, software, or any combination of firmware, hardware, and software.

[0305] (example)

[0306] Below are exemplary implementations of different embodiments of the present invention.

[0307] Example 1. A method including generating a bounding volume hierarchy (BVH) including BVH nodes arranged hierarchically based on input primitives, at least one BVH node including one or more child nodes, determining motion values ​​for a quantization grid based on motion values ​​of one or more child nodes of the at least one BVH node, and mapping a linear bound of each child node of the child nodes to the quantization grid.

[0308] Example 2. The method of example 1, wherein mapping the linear bounds of each child node of the child nodes further includes obtaining one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes, and deriving quantized bounds of the one or more child nodes from the one or more residual motion values.

[0309] Example 3. The method of example 2, wherein one or more child nodes include a primitive.

[0310] Example 4. The method of example 3, wherein the primitive is in motion.

[0311] Example 5. The method of example 4, wherein motion values ​​associated with one or more child nodes are determined based on the motion of the primitive.

[0312] Example 6. The method of example 3, wherein the primitives include triangles.

[0313] Example 7. The method of example 2, further comprising performing ray traversal and / or intersection operations according to quantized bounds of the one or more child nodes to determine one or more intersection points of the ray.

[0314] Example 8. The method of example 7, further comprising generating one or more shaders that perform graphics operations on the one or more intersection points.

[0315] Example 9. A machine-readable medium having program code stored thereon that, when executed by a machine, causes the machine to perform the following operations: generating a bounding volume hierarchy (BVH), the BVH including BVH nodes arranged hierarchically based on input primitives, at least one BVH node including one or more child nodes, determining motion values ​​for a quantization grid based on motion values ​​of one or more child nodes of the at least one BVH node, and mapping a linear bound of each child node of the child nodes to the quantization grid.

[0316] Example 10. The machine-readable medium of Example 9, wherein mapping the linear bound of each child node of the child nodes further includes obtaining one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes, and deriving quantized bounds of the one or more child nodes from the one or more residual motion values.

[0317] Example 11. The machine-readable medium of example 10, wherein one or more child nodes include a primitive.

[0318] Example 12. The machine-readable medium of example 11, wherein the primitive is in motion.

[0319] Example 13. The machine-readable medium of example 12, wherein the motion values ​​associated with the one or more child nodes are determined based on the motion of the primitive.

[0320] Example 14. The machine-readable medium of example 11, wherein the primitives include triangles.

[0321] Example 15. The machine-readable medium of example 10, further comprising program code for causing a machine to perform an operation of performing ray traversal and / or intersection operations according to quantized bounds of one or more child nodes to determine one or more intersection points of rays.

[0322] Example 16. The machine-readable medium of Example 15, further comprising program code for causing a machine to perform an operation of generating one or more shaders that perform graphics operations for one or more intersections.

[0323] Example 17. A graphics processor including: a Bounding Volume Hierarchy (BVH) generator that constructs a BVH including hierarchically arranged BVH nodes based on input primitives, at least one BVH node including one or more child nodes; and motion blur processing hardware logic that determines motion values ​​for a quantization grid based on motion values ​​of one or more child nodes of the at least one BVH node, and maps a linear bound of each child node of the child nodes to the quantization grid.

[0324] Example 18. The graphics processor of example 17, wherein to map a linear bound for each child node of the child nodes, the motion blur processing hardware logic obtains one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes, and derives quantized bounds for the one or more child nodes from the one or more residual motion values.

[0325] Example 19. The graphics processor of example 18, wherein one or more child nodes include a primitive.

[0326] Example 20. The graphics processor of example 19, wherein the primitive is in motion.

[0327] Example 21. The graphics processor of example 20, wherein the motion values ​​associated with the one or more child nodes are determined based on the motion of the primitive.

[0328] Example 22. The graphics processor of example 19, wherein the primitives include triangles.

[0329] Example 23. The graphics processor of example 18, further comprising ray traversal and / or intersection hardware logic configured to perform ray traversal and / or intersection operations according to quantized bounds of one or more child nodes to determine one or more intersection points for rays.

[0330] Example 24. The graphics processor of example 23, further comprising a plurality of execution circuits for executing one or more shaders that perform graphics operations on one or more intersections.

[0331] An embodiment of the present invention may include various steps as described above. The steps may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by specific hardware components that contain hard-wired logic for performing the steps, or by any combination of programmed computer components and custom hardware components.

[0332] As described herein, instructions may represent a particular configuration of hardware, such as an application specific integrated circuit (ASIC) configured to perform a particular operation, or may have predetermined functions or software instructions stored in memory embodied in a non-transitory computer readable medium. Thus, the techniques illustrated in the figures may be implemented using code and data stored and executed on one or more electronic devices (e.g., end stations, network elements, etc.). Such electronic devices store and communicate (internal and / or with other electronic devices over a network) code and data using computer readable media, such as non-transitory computer machine readable storage media (e.g., magnetic disks, optical disks, random access memory, read only memory, flash memory devices, phase change memory) and transitory computer machine readable communication media (e.g., electrical, optical, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, digital signals, etc.).

[0333] Further, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input / output devices (e.g., keyboards, touch screens, and / or displays), and network connections. The coupling of the set of processors and other components is typically through one or more buses and bridges (also referred to as bus controllers). The signals carrying the storage devices and network traffic represent one or more machine-readable storage media and machine-readable communication media, respectively. Thus, the storage devices of a given electronic device typically store code and / or data for execution on the set of one or more processors of that electronic device. Of course, one or more portions of the embodiments of the present invention may be implemented using different combinations of software, firmware, and / or hardware. Throughout this detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. In certain instances, well-known structures and functions have not been described in detail in order to avoid obscuring the subject matter of the present invention. Therefore, the scope and spirit of the invention should be determined in light of the following claims.

Claims

1. generating a bounding volume hierarchy (BVH) including BVH nodes arranged hierarchically based on the input primitives, at least one BVH node including one or more child nodes; determining a motion value for a quantization grid based on motion values ​​of the one or more child nodes of the at least one BVH node; and mapping a linear bound of each child node of the child nodes onto the quantization grid; Mapping a linear bound of each child node of the child nodes onto the quantization grid includes: obtaining one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes; and deriving quantized bounds of the one or more child nodes from the one or more residual motion values. method.

2. The method of claim 1 , wherein the one or more child nodes include a primitive.

3. The method of claim 2 , wherein the primitives are in motion.

4. The method of claim 3 , wherein the motion values ​​associated with the one or more child nodes are determined based on a motion of the primitive.

5. The method of claim 2 , wherein the primitives include triangles.

6. The method of claim 1 , further comprising performing ray traversal and / or intersection operations according to the quantized bounds of the one or more child nodes to determine one or more intersection points of rays.

7. The method of claim 6 , further comprising generating one or more shaders that perform graphics operations on the one or more intersection points.

8. 1. A machine-readable medium, comprising: The machine-readable medium has stored thereon program code which, when executed by a machine, causes the machine to perform the following operations: an operation of generating a bounding volume hierarchy (BVH), the BVH including BVH nodes arranged hierarchically based on the input primitives, at least one BVH node including one or more child nodes; determining a motion value for a quantization grid based on motion values ​​of the one or more child nodes of the at least one BVH node; and performing an operation of mapping a linear bound of each child node of said child node onto said quantization grid; Mapping a linear bound of each child node of the child nodes onto the quantization grid includes: obtaining one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes; and deriving quantized bounds of the one or more child nodes from the one or more residual motion values. Machine-readable medium.

9. The machine-readable medium of claim 8 , wherein the one or more child nodes comprises a primitive.

10. The machine-readable medium of claim 9 , wherein the primitives are in motion.

11. The machine-readable medium of claim 10 , wherein the motion values ​​associated with the one or more child nodes are determined based on a motion of the primitive.

12. The machine-readable medium of claim 9 , wherein the primitives include triangles.

13. 13. The machine-readable medium of claim 9, further comprising program code for causing the machine to perform an operation of performing ray traversal and / or intersection operations according to the quantized bounds of the one or more child nodes to determine one or more intersection points of rays.

14. 14. The machine-readable medium of claim 13, further comprising program code that causes the machine to perform an operation of generating one or more shaders that perform graphics operations with respect to the one or more intersections.

15. a bounding volume hierarchy (BVH) generator that constructs a BVH including hierarchically arranged BVH nodes based on input primitives, at least one BVH node including one or more child nodes; and motion blur processing hardware logic that determines a motion value for a quantization grid based on motion values ​​of the one or more child nodes of the at least one BVH node, and maps a linear bound of each of the child nodes to the quantization grid; to map the linear bound of each child node of the child nodes onto the quantization grid, the motion blur processing hardware logic obtains one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes, and derives quantized bounds of the one or more child nodes from the one or more residual motion values. Graphics processor.

16. The graphics processor of claim 15, wherein the one or more child nodes include a primitive.

17. 17. The graphics processor of claim 16, wherein the primitives are in motion.

18. 20. The graphics processor of claim 17, wherein the motion values ​​associated with the one or more child nodes are determined based on a motion of the primitive.

19. A graphics processor according to any one of claims 16 to 18, wherein the primitives include triangles.

20. 20. A graphics processor according to claim 15, further comprising ray traversal and / or intersection hardware logic configured to perform ray traversal and / or intersection operations according to the quantized bounds of the one or more child nodes to determine one or more intersection points of rays.

21. The graphics processor of claim 20, further comprising a plurality of execution circuits for executing one or more shaders that perform graphics operations with respect to the one or more intersections.

22. means for generating a bounding volume hierarchy (BVH), the BVH including BVH nodes arranged hierarchically based on input primitives, at least one BVH node including one or more child nodes; means for determining a motion value for a quantization grid based on motion values ​​of the one or more child nodes of the at least one BVH node; means for mapping a linear bound of each child node of the child nodes onto the quantization grid; Mapping a linear bound of each child node of the child nodes onto the quantization grid includes: obtaining one or more residual motion values ​​by subtracting motion values ​​of the quantization grid from motion values ​​associated with the one or more child nodes; and deriving quantized bounds of the one or more child nodes from the one or more residual motion values. Device.

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