Light-emitting display device

Abstract

To provide a light-emitting display device in which each of multiple display areas of a display panel can selectively limit a viewing angle.SOLUTION: A light-emitting display device includes a display panel in which multiple display areas including a first display area and a second display area are defined, multiple sub-pixels disposed in each of the multiple display areas, and a gate driver implemented on the multiple display areas. Each of the multiple sub-pixels includes a first light-emitting element that emits light in response to a driving current, a first lens that refracts the light emitted from the first light-emitting element, a second light-emitting element that emits light in response to the driving current, and a second lens that refracts the light emitted from the second light-emitting element and has a shape different from the first lens. Accordingly, the device can operate the light-emitting display device in any one of a narrow view mode and a wide view by using the first lens and the second lens.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a light-emitting display device, and more particularly to a light-emitting display device capable of controlling a viewing angle. [Background technology]

[0002] An organic light emitting diode (OLED), which is a self-emitting device, includes an anode electrode, a cathode electrode, and an organic compound layer formed between them. The organic compound layer includes a hole transport layer (HTL), an emission layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode electrode and the cathode electrode, holes that have passed through the hole transport layer (HTL) and electrons that have passed through the electron transport layer (ETL) are transferred to the emission layer (EML) to form excitons, and as a result, the emission layer (EML) generates visible light. An active matrix type light emitting display device includes an organic light emitting diode (OLED) that emits light by itself, and is used in a variety of applications due to its advantages of fast response speed, luminous efficiency, brightness, and wide viewing angle.

[0003] The light emitting display device arranges pixels, each including an organic light emitting element, in a matrix form and adjusts the brightness of the pixels according to the gray scale of video data. Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, the viewing angle of a light emitting display device is not limited, but for reasons of privacy protection, information protection, etc., it is beneficial to limit the viewing angle.

[0005] Furthermore, when a light-emitting display device is used to provide vehicle driving information, the image displayed by the light-emitting display device may be reflected from the vehicle window and obstruct the driver's view. Such image reflection in a vehicle is particularly severe when driving at night, and may adversely affect the driver's safe driving. Therefore, a light-emitting display device applied to a vehicle is required to have a limited viewing angle.

[0006] Such a viewing angle restriction differs depending on whether the vehicle is moving or not, and whether the driver and passengers are viewing or not, so it is necessary to selectively switch the viewing angle.

[0007] Also, in some countries, it is prohibited to show the driver the multimedia played in front of the passenger seat, so the viewing angle must be selectively switched.

[0008] According to one or more embodiments of the present invention, there is provided a light emitting display device capable of selectively limiting the viewing angle in each of a plurality of display regions of a display panel.

[0009] According to one or more embodiments of the present invention, there is provided a light emitting display device capable of independently driving a narrow viewing mode and a wide viewing mode in each of a plurality of display regions.

[0010] According to another embodiment of the present invention, there is provided a light emitting display device with a reduced bezel.

[0011] According to another embodiment of the present invention, there is provided a light emitting display device that reduces a delay that occurs when a signal output from a gate driver is transmitted to a signal line.

[0012] The technical effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0013] A light emitting display device according to an embodiment of the present invention includes a display panel having a plurality of display regions defined therein, including a first display region and a second display region, a plurality of sub-pixels disposed in each of the plurality of display regions, and a gate driver mounted in each of the plurality of display regions, each of the plurality of sub-pixels including a first light emitting element that emits light in response to a driving current, a first lens that refracts light from the first light emitting element, a second light emitting element that emits light in response to a driving current, and a second lens that refracts light from the second light emitting element and has a shape different from that of the first lens. Thus, the present invention can drive the light emitting display device in either a narrow viewing mode or a wide viewing mode by using the first lens and the second lens.

[0014] A light emitting display device according to another embodiment of the present invention includes a display panel having a display area defined including a first display area and a second display area, a plurality of sub-pixels arranged in each of the first display area and the second display area, and a gate driver mounted in the first display area and the second display area, each of the plurality of sub-pixels including a first light emitting element emitting light in a narrow viewing mode with a driving current, a hemispherical lens configured to refract light from the first light emitting element and limit a viewing angle in a first direction and a second direction, a second light emitting element emitting light in a wide viewing mode with a driving current, and a semi-cylindrical lens configured to refract light from the second light emitting element and limit a viewing angle only in the first direction. Thus, the present invention can independently drive each of the first display area and the second display area in either a narrow viewing mode or a wide viewing mode.

[0015] Further details of the embodiments are included in the detailed description and the drawings. Effect of the Invention

[0016] The present invention allows each of a plurality of display regions to be driven independently in a narrow viewing mode and a wide viewing mode.

[0017] The present invention can selectively limit the viewing angle in each of a plurality of display regions.

[0018] The present invention can reduce delays that occur when a signal output from a gate driver is transmitted to a signal line.

[0019] The present invention allows the gate drivers to be mounted in the display area, minimizing the bezel.

[0020] The effects of the present invention are not limited to the above-mentioned examples, and various other effects are included within the scope of the present invention. [Brief description of the drawings]

[0021] [Figure 1] 1 is a schematic plan view of a light emitting display device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic cross-sectional view of a light emitting display device according to an embodiment of the present invention; [Diagram 3] 1 is a schematic cross-sectional view of a display panel of a light emitting display device according to an embodiment of the present invention; [Figure 4A] 2 is a schematic diagram illustrating a first lens of a light emitting display device according to an embodiment of the present invention. [Figure 4B] 4 is a schematic diagram illustrating a second lens of a light emitting display device according to an embodiment of the present invention. [Figure 5A] 4 is a diagram showing an optical profile with respect to a viewing angle of a first lens of a light emitting display device according to an embodiment of the present invention. [Figure 5B] 5 is a diagram showing an optical profile with respect to a viewing angle of a second lens of a light emitting display device according to an embodiment of the present invention. FIG. [Figure 6] 4A and 4B are diagrams illustrating operations of a wide viewing mode and a narrow viewing mode of a light emitting display device according to an embodiment of the present invention; [Figure 7] 2 is a circuit diagram of a sub-pixel of a light emitting display device according to an embodiment of the present invention. [Figure 8A] 4 is a waveform diagram showing an emission signal and a scan signal in a wide viewing mode of an organic light emitting display device according to an embodiment of the present invention. [Figure 8B] 4 is a waveform diagram showing an emission signal and a scan signal in a wide viewing mode of an organic light emitting display device according to an embodiment of the present invention. [Figure 9A] 4 is a circuit diagram of a subpixel of a light emitting display device according to an embodiment of the present invention during an initial period in a wide viewing mode and a narrow viewing mode, respectively. [Figure 9B] 4A and 4B are circuit diagrams of a sub-pixel of an organic light emitting display device according to an embodiment of the present invention during a sampling period in a wide viewing mode and a narrow viewing mode, respectively. [Figure 9C] 1 is a circuit diagram of a sub-pixel of a light emitting display device according to an embodiment of the present invention during an emission period in a wide viewing mode. [Figure 9D] 4 is a circuit diagram of a sub-pixel of a light emitting display device according to an embodiment of the present invention during an emission period in a narrow viewing mode. [Figure 10] 1 is a schematic enlarged plan view of a display panel of a light emitting display device according to an embodiment of the present invention; [Figure 11] 2 is a schematic enlarged plan view of a display panel operated in a wide viewing mode and a narrow viewing mode; [Figure 12] 11 is a schematic enlarged plan view of a display panel of a light emitting display device according to another embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The advantages and features of the present invention, and the methods for achieving them, will become apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be implemented in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the invention to those skilled in the art. The present invention is defined solely by the claims.

[0023] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are illustrative, and the present invention is not limited to the illustrated matters. The same reference symbols refer to the same components throughout the specification. In addition, when describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. When "includes," "has," "is made," etc. are used in the present invention, other parts may be added since "only" is not used. When a component is expressed in the singular, it includes the plural unless otherwise explicitly stated.

[0024] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0025] When describing a positional relationship, for example when describing the positional relationship of two parts using "on top of," "at the top of," "at the bottom of," "next to," etc., since "immediately" or "directly" is not used, one or more other parts may be located between the two parts.

[0026] When an element or layer is referred to as "on" another element or layer, this includes the case where the element or layer is directly on top of the other element, or has other layers or elements interposed therebetween.

[0027] In addition, although the terms "first", "second" and the like are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, the first component referred to below may be the second component within the technical concept of the present invention.

[0028] Like reference numbers refer to like elements throughout the specification.

[0029] The area and thickness of each component shown in the drawings are shown for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the components shown.

[0030] The respective features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

[0031] In the following, the invention will be described with reference to the drawings.

[0032] 1 is a schematic plan view of a light emitting display device according to an embodiment of the present invention, in which only a display panel PN, a plurality of flexible films COF, and a plurality of printed circuit boards PCB are shown among various components of the light emitting display device 100 for ease of explanation.

[0033] Referring to FIG. 1, a light emitting display device 100 according to an embodiment of the present invention includes a display panel PN, a plurality of flexible films COF, and a plurality of printed circuit boards PCB.

[0034] The display panel PN is a component for displaying images to a user, and may be equipped with light-emitting elements for displaying images, pixel circuits for driving the light-emitting elements, signal lines for transmitting various signals to the light-emitting elements and pixel circuits, etc.

[0035] The display panel PN includes a display area AA and a non-display area NA.

[0036] The display area AA is an area where an image is displayed on the display panel PN. A plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP are the smallest units constituting the display area AA, and a plurality of scan signal lines and a plurality of data lines cross each other, and each of the plurality of sub-pixels SP may be connected to the scan signal lines and the data lines.

[0037] The display area AA includes a first display area AA1 and a second display area AA2. The first display area AA1 and the second display area AA2 are areas that are driven independently, and each of the first display area AA1 and the second display area AA2 may be driven in one of a wide viewing angle (shared) mode and a narrow viewing angle (private) mode in the horizontal direction. The first display area AA1 and the second display area AA2 may be driven in the same mode or in different modes. In the narrow viewing mode, only some viewers among a plurality of viewers can view an image by having a narrow viewing angle in the horizontal direction, and in the wide viewing mode, more viewers can view an image by having a wide viewing angle in the horizontal direction. A more detailed description of the narrow viewing mode and the wide viewing mode will be given later with reference to FIG. 4A to FIG. 6.

[0038] The non-display area NA is an area where no image is displayed. Various signal lines and circuits for driving light emitting elements in the display area AA are arranged in the non-display area NA. For example, but not limited to, link wiring for transmitting signals to a plurality of sub-pixels SP and circuits in the display area AA may be arranged in the non-display area NA.

[0039] Meanwhile, although not shown, a gate driver is disposed in the display panel PN. For example, the gate driver may be mounted in each of the first display area AA1 and the second display area AA2 of the display panel PN in a GIA (Gate In Active Area) manner. In the light emitting display device 100 according to an embodiment of the present invention, the gate driver is mounted in the display area AA to reduce the area of ​​the non-display area NA, and the first display area AA1 and the second display area AA2 can be independently driven in wide viewing mode and narrow viewing mode. A more detailed description of the gate driver will be given later with reference to FIGS. 10 and 11.

[0040] One or more flexible film COFs are disposed at one end of the display panel PN. The flexible film COFs may be electrically connected to the non-display area NA of the display panel PN. The flexible film COFs are films in which various components are disposed on a ductile base film, and are for supplying signals to the sub-pixels SP and driving circuits of the display area AA, and may be electrically connected to the display panel PN. For example, the flexible film COFs may supply power supply voltages, data voltages, etc. to the sub-pixels SP and driving circuits of the display area AA.

[0041] Meanwhile, a driving IC such as a data driver IC may be disposed on the multiple flexible film COFs. The driving IC is a component that processes data for displaying an image and a driving signal for processing the data. The driving IC may be disposed in a manner such as chip on glass (COG), chip on film (COF), tape carrier package (TCP), etc., depending on the mounting manner. However, for the convenience of explanation, the driving IC is described as being mounted on the multiple flexible film COFs in a chip on film manner, but is not limited thereto. Also, the driving IC may be disposed as a single chip by being integrated with a timing controller.

[0042] Each of the plurality of printed circuit boards PCB is electrically connected to the plurality of flexible films COF. The plurality of printed circuit boards PCB are components that supply signals to the driving IC. The plurality of printed circuit boards PCB may have various components arranged thereon for supplying various signals, such as driving signals, data signals, etc., to the driving IC.

[0043] Hereinafter, a display panel of a light emitting display device 100 according to an embodiment of the present invention will be described with reference to FIG. 2 and FIG.

[0044] Fig. 2 is a schematic cross-sectional view of a light emitting display device according to an embodiment of the present invention, and Fig. 3 is a schematic cross-sectional view of a display panel of the light emitting display device according to an embodiment of the present invention.

[0045] Referring to FIG. 2, the light emitting display device 100 according to the embodiment of the present invention includes a display panel PN, a light blocking pattern 210, an optical gap layer 220, a lens layer 230, a planarization film 240, and a polarizing layer 250.

[0046] 2 and 3, the display panel PN includes a substrate 110, a plurality of first light emitting elements De1, a plurality of second light emitting elements De2, and an encapsulation layer 190. The display panel PN includes a substrate 110, a plurality of first light emitting elements De1, a plurality of second light emitting elements De2, and an encapsulation layer 190.

[0047] A plurality of subpixels SP including first to third subpixels SP1, SP2, and SP3 are defined on the substrate 110. Each of the first to third subpixels SP1, SP2, and SP3 has a first light-emitting portion (light-emitting area) EA1 and a second light-emitting portion (light-emitting area) EA2.

[0048] The first light emitting section EA1 includes a first light emitting element De1, and the second light emitting section EA2 includes a second light emitting element De2.

[0049] The first to third subpixels SP1, SP2, and SP3 may be red, green, and blue subpixels, respectively, so that the first and second light emitting elements De1 and De2 of the first subpixel SP1 may emit red light, the first and second light emitting elements De1 and De2 of the second subpixel SP2 may emit green light, and the first and second light emitting elements De1 and De2 of the third subpixel SP3 may emit blue light.

[0050] 2 and 3, a display panel PN of a light emitting display device 100 according to an embodiment of the present invention includes a substrate 110, a plurality of thin film transistors Tr1 and Tr2, a plurality of light emitting elements De1 and De2, and an encapsulation layer 190.

[0051] Specifically, each sub-pixel SP includes a first light emitting portion EA1 and a second light emitting portion EA2 on the substrate 110. The substrate 110 may be a glass substrate or a plastic substrate.

[0052] As an example, polyimide (PI) may be used as the plastic substrate, but is not limited thereto.

[0053] A buffer layer 120 is formed on the substrate 110. The buffer layer 120 is located on substantially the entire surface of the substrate 110. The buffer layer 120 may be formed of an inorganic material such as silicon oxide (SiO2) or silicon nitride (SiNx) and may be formed as a single layer or multiple layers.

[0054] A patterned first semiconductor layer 122 and a patterned second semiconductor layer 124 are formed on the first light emitting portion EA1 and the second light emitting portion EA2 on the buffer layer 120, respectively.

[0055] Each of the first semiconductor layer 122 and the second semiconductor layer 124 may be made of an oxide semiconductor material, in which case a shielding pattern may be further formed under the first semiconductor layer 122 and the second semiconductor layer 124. The shielding pattern blocks light incident on the first semiconductor layer 122 and the second semiconductor layer 124 to prevent the first semiconductor layer 122 and the second semiconductor layer 124 from being deteriorated by light.

[0056] Alternatively, each of the first semiconductor layer 122 and the second semiconductor layer 124 may be made of polycrystalline silicon, in which case both edges of each of the first semiconductor layer 122 and the second semiconductor layer 124 may be doped with impurities.

[0057] A gate insulating layer 130 made of an insulating material is formed on the first semiconductor layer 122 and the second semiconductor layer 124 substantially over the entire surface of the substrate 110. The gate insulating layer 130 may be made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx).

[0058] In this case, when the first semiconductor layer 122 and the second semiconductor layer 124 are made of an oxide semiconductor material, the gate insulating layer 130 may be made of silicon oxide (SiO2). In contrast, when the first semiconductor layer 122 and the second semiconductor layer 124 are made of polycrystalline silicon, the gate insulating layer 130 may be made of silicon oxide (SiO2) or silicon nitride (SiNx).

[0059] A first gate electrode 132 and a second gate electrode 134 made of a conductive material such as a metal are formed on the gate insulating layer 130 to correspond to the first semiconductor layer 122 and the second semiconductor layer 124, respectively. In addition, a scan signal line (not shown) may be formed on the gate insulating layer 130. The scan signal line may extend in one direction.

[0060] Meanwhile, in one embodiment of the present invention, the gate insulating film 130 is formed on the entire surface of the substrate 110, but the gate insulating film 130 may be patterned to have the same pattern as the first gate electrode 132 and the second gate electrode 134 and may be disposed only below the first gate electrode 132 and the second gate electrode 134.

[0061] An interlayer insulating film 140 made of an insulating material is formed on substantially the entire surface of the substrate 110 on the first gate electrode 132 and the second gate electrode 134. The interlayer insulating film 140 may be made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx), or an organic insulating material such as photo acryl or benzocyclobutene.

[0062] The interlayer insulating film 140 has contact holes exposing both upper surfaces of the first semiconductor layer 122 and the second semiconductor layer 124. The contact holes may also be formed in the gate insulating film 130. A first source electrode 142, a first drain electrode 144, a second source electrode 146, and a second drain electrode 148 are respectively formed on the first light emitting unit EA1 and the second light emitting unit EA2 on the interlayer insulating film 140 using a conductive material such as a metal. In addition, a data line (not shown) and a power line (not shown) may be formed on the interlayer insulating film 140 to extend in a direction perpendicular to one direction.

[0063] The first source electrode 142 and the first drain electrode 144 contact both sides of the first semiconductor layer 122 through contact holes in the interlayer insulating film 140, and the second source electrode 146 and the second drain electrode 148 contact both sides of the second semiconductor layer 124 through contact holes in the interlayer insulating film 140. Although not shown, the data lines extend in a direction perpendicular to one direction and cross the scan signal lines to define pixel areas corresponding to each sub-pixel SP, and power lines supplying a high potential voltage are located spaced apart from the data lines.

[0064] On the other hand, the first semiconductor layer 122, the first gate electrode 132, the first source electrode 142 and the first drain electrode 144 form a first thin film transistor Tr1, and the second semiconductor layer 124, the second gate electrode 134, the second source electrode 146 and the second drain electrode 148 form a second thin film transistor Tr2.

[0065] One or more thin film transistors having the same structure as the first thin film transistor Tr1 and the second thin film transistor Tr2 may be further formed on the substrate 110 of each sub-pixel SP, but is not limited thereto.

[0066] A passivation layer 150 made of an insulating material is formed on the first source electrode 142, the first drain electrode 144, the second source electrode 146, and the second drain electrode 148 substantially over the entire surface of the substrate 110. The passivation layer 150 may be made of an organic insulating material such as photoacryl or benzocyclobutene. The passivation layer 150 has a flat upper surface.

[0067] Meanwhile, an insulating film made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiNx) may be further formed under the passivation film 150, i.e., between the first thin film transistor Tr1 and the second thin film transistor Tr2 and the passivation film 150.

[0068] The passivation film 150 has a first drain contact hole 150a and a second drain contact hole 150b that expose the first drain electrode 144 and the second drain electrode 148, respectively.

[0069] A first anode electrode 162 and a second anode electrode 164 are formed on the protective film 150 using a conductive material having a relatively high work function. The first anode electrode 162 is located in the first light emitting portion EA1 and contacts the first drain electrode 144 through the first drain contact hole 150a. The second anode electrode 164 is located in the second light emitting portion EA2 and contacts the second drain electrode 148 through the second drain contact hole 150b.

[0070] For example, each of the first anode electrode 162 and the second anode electrode 164 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0071] Meanwhile, the display panel PN of the light emitting display device 100 according to an embodiment of the present invention may be a top emission type in which light from a plurality of light emitting elements is output toward the upper side of the substrate 110, and therefore, each of the first anode electrode 162 and the second anode electrode 164 may further include a reflective electrode or a reflective layer made of a metal material having high reflectivity under a transparent conductive material. For example, the reflective electrode or the reflective layer may be made of an aluminum-palladium-copper (APC) alloy, silver (Ag), or aluminum (Al). In this case, each of the first anode electrode 162 and the second anode electrode 164 may have a triple layer structure of ITO / APC / ITO, ITO / Ag / ITO, or ITO / Al / ITO, but is not limited thereto.

[0072] A bank 165 made of an insulating material is formed on the first anode electrode 162 and the second anode electrode 164. The bank 165 overlaps edges of the first anode electrode 162 and the second anode electrode 164 and covers the edges of the first anode electrode 162 and the second anode electrode 164. The bank 165 has a first opening 165a and a second opening 165b exposing the first anode electrode 162 and the second anode electrode 164.

[0073] At least the top surface of the bank 165 is hydrophobic, and the side surface of the bank 165 may be hydrophobic or hydrophilic. Such a bank 165 may be formed of an organic insulating material having hydrophobic properties. Alternatively, the bank 165 may be formed of an organic insulating material having hydrophilic properties and then subjected to a hydrophobic treatment.

[0074] In the present invention, the bank 165 has a single layer structure, but the bank 165 may have a double layer structure, i.e., the bank 165 may have a double layer structure including a lower hydrophilic bank 165 and an upper hydrophobic bank 165.

[0075] Next, an emission layer 170 is formed on the first anode electrode 162 and the second anode electrode 164 exposed through the first opening 165a and the second opening 165b of the bank 165. The emission layer 170 on the first anode electrode 162 and the emission layer 170 on the second anode electrode 164 are connected to each other to form an integrated structure. However, the present invention is not limited thereto, and the emission layer 170 on the first anode electrode 162 and the emission layer 170 on the second anode electrode 164 may be separated from each other.

[0076] Although not shown, the light-emitting layer 170 may include a first charge auxiliary layer, a light-emitting material layer, and a second charge auxiliary layer, which are sequentially positioned from the top of the first anode electrode 162 and the second anode electrode 164. The light-emitting material layer may be made of any one of red, green, and blue light-emitting materials, but is not limited thereto. Such a light-emitting material may be an organic light-emitting material, such as a phosphorescent compound or a fluorescent compound. However, the present invention is not limited thereto, and an inorganic light-emitting material, such as a quantum dot, may also be used.

[0077] The first charge auxiliary layer may be a hole auxiliary layer, which may include at least one of a hole injection layer (HIL) and a hole transport layer (HTL), and the second charge auxiliary layer may be an electron auxiliary layer, which may include at least one of an electron injection layer (EIL) and an electron transport layer (ETL).

[0078] The light emitting layer 170 may be formed through an evaporation process. At this time, a fine metal mask (FMM) may be used to pattern the light emitting layer 170 for each sub-pixel SP. Alternatively, the light emitting layer 170 may be formed through a solution process. In this case, the light emitting layer 170 may be provided only in the first opening 165a and the second opening 165b, and the light emitting layer 170 may have a higher height near the bank 165.

[0079] A cathode electrode 180 made of a conductive material having a relatively low work function is formed on the light emitting layer 170 substantially over the entire surface of the substrate 110. The cathode electrode 180 may be made of aluminum, magnesium, silver, or an alloy thereof. The cathode electrode 180 has a relatively thin thickness so that light from the light emitting layer 170 can be transmitted therethrough.

[0080] Alternatively, the cathode electrode 180 may be formed of a transparent conductive material such as, but not limited to, indium-gallium-oxide (IGO).

[0081] The first anode electrode 162, the light emitting layer 170, and the cathode electrode 180 of the first light emitting unit EA1 form a first light emitting element De1, and the second anode electrode 164, the light emitting layer 170, and the cathode electrode 180 of the second light emitting unit EA2 form a second light emitting element De2.

[0082] As mentioned above, the display panel PN according to one embodiment of the present invention may be a top emission type in which light from the light emitting layer 170 of the first light emitting element De1 and the second light emitting element De2 is output in the opposite direction to the substrate 110, for example, through the cathode electrode 180 to the outside. Such a top emission type can have a wider light emitting area compared to a bottom emission type of the same area, thereby improving brightness and reducing power consumption.

[0083] An encapsulation layer 190 having a flat upper surface is formed on substantially the entire surface of the substrate 110 above the cathode electrode 180. The encapsulation layer 190 prevents moisture and oxygen from the outside from entering the first light emitting element De1 and the second light emitting element De2. Therefore, the encapsulation layer 190 may also be referred to as an encapsulation layer.

[0084] The sealing layer 190 may have a laminated structure of a first inorganic film 192, an organic film 194, and a second inorganic film 196. Here, the organic film 194 may be a film that covers foreign matter generated during the manufacturing process.

[0085] 2, a light-shielding pattern 210 is provided on an upper portion of the display panel PN, specifically, on an upper portion of the encapsulation layer 190. The light-shielding pattern 210 is formed corresponding to between adjacent first to third sub-pixels SP1, SP2, and SP3, or between the first light emitting portion EA1 and the second light emitting portion EA2.

[0086] The light blocking pattern 210 may be a black matrix and may be made of black resin, chromium oxide, etc. Alternatively, the light blocking pattern 210 may be a touch electrode and may be made of metal. In this case, the touch electrode includes a number of intersecting transmitting electrodes and a number of receiving electrodes, and a touch can be sensed from a change in capacitance between the number of transmitting electrodes and the number of receiving electrodes.

[0087] An optical gap layer 220 is provided on the light-shielding pattern 210. The optical gap layer 220 secures an optical gap between the first and second light-emitting elements De1 and De2 and the lenses 232 and 234 of the lens layer 230, and improves the efficiency of the lenses 232 and 234 by refracting the light from the first and second light-emitting elements De1 and De2 in a specific direction by the lenses 232 and 234. The optical gap layer 220 may have a thickness of several to several tens of μm and may be made of an organic insulating material.

[0088] As an example, the optical gap layer 220 may be made of, but is not limited to, photo acryl, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA).

[0089] The lens layer 230 is provided on the optical gap layer 220. The lens layer 230 includes a first lens 232 and a second lens 234. The first lens 232 is disposed in the first light emitting unit EA1 and refracts light from the first light emitting element De1 in a specific direction. The second lens 234 is disposed in the second light emitting unit EA2 and refracts light from the second light emitting element De2 in a specific direction. Each of the first lens 232 and the second lens 234 may partially overlap with the light blocking pattern 210.

[0090] The first lens 232 is a half-spherical lens, and the second lens 234 is a half-cylindrical lens. As a result, the first light L1 emitted from the first light-emitting element De1 of each subpixel SP is refracted at a specific angle by the first lens 232 and output. And the second light L2 emitted from the second light-emitting element De2 of each subpixel SP is refracted at a specific angle by the second lens 234 and output. As a result, the viewing angle of each subpixel SP can be limited.

[0091] As shown in FIG. 2, in one embodiment, the first lens 232 at least partially overlaps the first light-emitting portion EA1, and the second lens 234 at least partially overlaps the second light-emitting portion EA2.

[0092] A planarization film 240 is provided on the lens layer 230 to protect the first lens 232 and the second lens 234. The planarization film 240 is made of an organic insulating material and has a flat upper surface. The refractive index of the planarization film 240 is smaller than the refractive index of the first lens 232 and the second lens 234.

[0093] As an example, the planarization layer 240 may be made of, but is not limited to, photo acryl, benzocyclobutene (BCB), polyimide (PI), or polyamide (PA).

[0094] A polarizing layer 250 is provided on the planarization film 240. The polarizing layer 250 may include a linear polarizing layer and a retardation layer, and serves to prevent the external light from being reflected by the display panel PN and then emitted to the outside by converting the polarization state of the external light incident on the display panel PN.

[0095] Meanwhile, in the light emitting display device 100 according to one embodiment of the present invention, each sub-pixel SP has a first light emitting portion EA1 and a second light emitting portion EA2, and a hemispherical first lens 232 is provided on the upper portion of the first light emitting portion EA1, and a semicylindrical second lens 234 is provided on the upper portion of the second light emitting portion EA2 to limit the viewing angle, thereby realizing a wide viewing mode and a narrow viewing mode.

[0096] 4A is a schematic diagram illustrating a first lens of a light emitting display device according to an embodiment of the present invention, and FIG 4B is a schematic diagram illustrating a second lens of the light emitting display device according to an embodiment of the present invention.

[0097] 4A, the first lens 232 is a half-spherical lens having a semicircular cross section in the X and Y directions. Therefore, the first lens 232 limits the viewing angles in the X and Y directions.

[0098] 4B, the second lens 234 is a half-cylindrical lens, and has a rectangular cross section in the X direction and a semicircular cross section in the Y direction. Therefore, the second lens 234 limits the viewing angle in the Y direction, but does not limit the viewing angle in the longitudinal direction of the second lens 234, for example, in the X direction.

[0099] The viewing angle characteristics of the first lens 232 and the second lens 234 will be described with reference to FIGS. 5A and 5B.

[0100] 5A and 5B are diagrams illustrating an optical profile for a viewing angle of a first lens and a second lens of an organic light emitting display device according to an embodiment of the present invention, respectively.

[0101] As shown in Figures 5A and 5B, the first light-emitting unit EA1 equipped with a hemispherical first lens 232 has a narrow viewing angle of less than 30 degrees in all directions, while the second light-emitting unit EA2 equipped with a semi-cylindrical second lens 234 has a narrow viewing angle of less than 30 degrees in the vertical direction and a wide viewing angle of more than 60 degrees in the horizontal direction.

[0102] Therefore, the vertical narrow viewing mode and the horizontal narrow viewing mode can be realized by driving the first light-emitting section EA1, and the vertical narrow viewing mode and the horizontal wide viewing mode can be realized by driving the second light-emitting section EA2.

[0103] In the light emitting display device 100 according to an embodiment of the present invention, a narrow viewing angle can always be realized in the vertical direction by the first and second lenses 232 and 234. In addition, a wide viewing mode and a narrow viewing mode can be selectively realized in the horizontal direction.

[0104] Such a wide viewing angle mode and a narrow viewing angle mode in the left-right direction will be described with reference to FIG.

[0105] FIG. 6 is a diagram illustrating an operation of a wide viewing mode and a narrow viewing mode of a light emitting display device according to an embodiment of the present invention.

[0106] As shown in FIG. 6, one pixel of the viewing angle convertible light emitting display device 100 according to one embodiment of the present invention includes a plurality of sub-pixels SP, for example, first to third sub-pixels SP1, SP2, and SP3, and each of the first to third sub-pixels SP1, SP2, and SP3 has a first light emitting portion EA1 and a second light emitting portion EA2.

[0107] A hemispherical first lens 232 is provided corresponding to the first light-emitting portion EA1, and a semicylindrical second lens 234 is provided corresponding to the second light-emitting portion EA2.

[0108] When operating in the wide viewing mode, the first light emitting element De1 of the first light emitting unit EA1 is turned off, and the second light emitting element De2 of the second light emitting unit EA2 is turned on, so that the light emitted from the second light emitting element De2 has a viewing angle limited in the Y direction, e.g., the up-down direction, by the second lens 234, and is output without viewing angle limitation in the X direction, e.g., the left-right direction. That is, the viewing angle of the second lens 234 is different from that of the first lens 232, and in most cases is larger than that of the first lens 232.

[0109] In contrast, when operating in narrow field of view mode, the first light-emitting element De1 of the first light-emitting unit EA1 is turned on, and the second light-emitting element De2 of the second light-emitting unit EA2 is turned off, and the light emitted from the first light-emitting element De1 is output with the field of view limited in the vertical and horizontal directions by the first lens 232.

[0110] In this way, the light emitting display device 100 according to an embodiment of the present invention can always have a narrow viewing angle in the up-down direction. If the light emitting display device 100 according to an embodiment of the present invention having a narrow viewing angle in the up-down direction (e.g., vertical direction) is applied to a vehicle, it is possible to prevent an image from being reflected on the windshield of the vehicle, thereby preventing the driver's field of vision from being obstructed.

[0111] In addition, an image having a wide viewing angle in the left-right direction can be displayed in the wide viewing mode, and an image having a narrow viewing angle in the left-right direction (e.g., horizontal direction) can be displayed in the narrow viewing mode, where both the driver's seat and the passenger seat users can view the image in the wide viewing mode, and one of the driver's seat and the passenger seat users can view the image in the narrow viewing mode. For example, according to one embodiment of the narrow viewing mode, the display device can display an image such that only the user sitting in either the driver's seat or the passenger seat can view the image, but not both at the same time. That is, in one embodiment, during the narrow viewing mode, the degree of the viewing angle restricted to the left direction can be made different from the degree of the viewing angle restricted to the right direction, so that only the user sitting in either the driver's seat or the passenger seat can view the image from the display device. For example, the viewing angle can be limited to the left direction (e.g., toward the driver's seat) and not limited to the right direction (e.g., toward the passenger seat) so that only the user sitting in the passenger seat can view the image from the display device. Therefore, the value of the viewing angle is different and is larger in the wide viewing mode than in the narrow viewing mode. Furthermore, a wide viewing angle mode and a narrow viewing angle mode can be selectively realized in the left and right direction.

[0112] The configuration and driving method of the plurality of sub-pixels SP will be specifically described below.

[0113] 7 is a circuit diagram of a subpixel of a light emitting display device according to an embodiment of the present invention, in which, for convenience of explanation, a circuit diagram of a subpixel SP arranged in an N-th row among a plurality of subpixels SP is shown.

[0114] Referring to FIG. 7, the subpixel SP includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12, a storage capacitor Cst, a first light-emitting element De1 and a second light-emitting element De2.

[0115] First, the switch elements constituting each of the subpixels SP may be configured as n-type or p-type transistors having a MOSFET structure. In the following examples, p-type transistors are illustrated, but the present invention is not limited to this.

[0116] Additionally, a transistor is a three-electrode device that includes a gate electrode, a source electrode, and a drain electrode. The source electrode is an electrode that supplies carriers to a transistor. In a transistor, carriers start flowing from the source electrode. The drain electrode is an electrode where carriers exit the transistor. That is, carriers flow in a MOSFET from the source electrode to the drain electrode. In the case of an n-type MOSFET (NMOS), the carriers are electrons, so the voltage of the source electrode is lower than the voltage of the drain electrode so that electrons can flow from the source electrode to the drain electrode. In an n-type MOSFET, electrons flow from the source electrode to the drain electrode, so the direction of current is from the drain electrode to the source electrode. In the case of a p-type MOSFET (PMOS), the carriers are holes, so the voltage of the source electrode is higher than the voltage of the drain electrode so that holes can flow from the source electrode to the drain electrode. In a p-type MOSFET, holes flow from the source electrode to the drain electrode so that current flows from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of a MOSFET are not fixed. For example, the source and drain electrodes of a MOSFET can be changed by an applied voltage. Therefore, the invention should not be limited by the source and drain electrodes of a transistor in the following embodiments.

[0117] 7, the first transistor T1 controls a driving current applied to a plurality of light emitting elements according to a source-gate voltage (Vsg). The first transistor T1 includes a source electrode connected to a first node N1, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3. The first transistor T1, which controls the driving current applied to the light emitting elements De1 and De2, may also be referred to as a driving transistor.

[0118] The second transistor T2 applies a data voltage Vdata from the data line to the first node N1. The second transistor T2 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to an Nth scan signal line transmitting an Nth scan signal Scan(N). The second transistor T2 can transmit the data voltage Vdata from the data line to the first node N1 in response to the Nth scan signal Scan(N) of a low level, which is a turn-on level.

[0119] The third transistor T3 diode-connects the gate electrode and the drain electrode of the first transistor T1, which is a driving transistor. The third transistor T3 includes a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to an Nth scan signal Scan(N) line transmitting an Nth scan signal Scan(N). Thus, the third transistor T3 diode-connects the gate electrode and the drain electrode of the first transistor T1 in response to the Nth scan signal Scan(N) of a low level, which is a turn-on level.

[0120] The fourth transistor T4 applies the initialization voltage Vini to the second node N2. The fourth transistor T4 includes a source electrode connected to an initialization line transmitting the initialization voltage Vini, a drain electrode connected to the second node N2, and a gate electrode connected to an (N-1)th scan signal line transmitting an (N-1)th scan signal Scan(N-1). The fourth transistor T4 applies the initialization voltage Vini to the second node N2 in response to the (N-1)th scan signal Scan(N-1) of a low level.

[0121] The fifth transistor T5 applies a high potential driving voltage VDD supplied from a high potential driving voltage line to the first node N1. The fifth transistor T5 includes a source electrode connected to the high potential driving voltage line, a drain electrode connected to the first node N1, and a gate electrode connected to a first light emitting signal line transmitting a first light emitting signal EM1(N). The second transistor T2 applies the high potential driving voltage VDD supplied from the high potential driving voltage line to the first node N1 in response to the first light emitting signal EM1(N) of a low level, which is a turn-on level.

[0122] The sixth transistor T6 forms a current path between the first transistor T1 and the first light emitting element De1. The sixth transistor T6 includes a source electrode connected to the third node N3, a drain electrode connected to the anode electrode of the first light emitting element De1, and a gate electrode connected to a second light emitting signal line EML2 transmitting a second light emitting signal EM2(N). The sixth transistor T6 forms a current path between the third node N3, which is the source electrode of the sixth transistor T6, and the first light emitting element De1 in response to the second light emitting signal EM2(N). Thus, the sixth transistor T6 forms a current path between the first transistor T1, which is a driving transistor, and the first light emitting element De1 in response to the second light emitting signal EM2(N) of a low level, which is a turn-on level. Thus, the sixth transistor T6 may also be referred to as a first light emitting control transistor that controls the light emission of the first light emitting element De1.

[0123] The seventh transistor T7 applies the initialization voltage Vini to the anode electrode of the first light emitting element De1. The seventh transistor T7 includes a source electrode connected to an initialization line transmitting the initialization voltage Vini, a drain electrode connected to the anode electrode of the first light emitting element De1, and a gate electrode connected to an Nth scan signal Scan(N) line transmitting an Nth scan signal Scan(N). Thus, the seventh transistor T7 applies the initialization voltage Vini to the anode electrode of the first light emitting element De1 in response to the Nth scan signal Scan(N) having a low level as a turn-on level.

[0124] The eighth transistor T8 forms a current path between the first transistor T1 and the second light emitting element De2. The eighth transistor T8 includes a source electrode connected to the third node N3, a drain electrode connected to the anode electrode of the second light emitting element De2, and a gate electrode connected to a third light emitting signal line transmitting a third light emitting signal EM3(N). The eighth transistor T8 forms a current path between the third node N3, which is the source electrode of the eighth transistor T8, and the second light emitting element De2 in response to the third light emitting signal EM3(N). Thus, the eighth transistor T8 forms a current path between the first transistor T1, which is a driving transistor, and the second light emitting element De2 in response to the third light emitting signal EM3(N) of a low level, which is a turn-on level. Thus, the eighth transistor T8 may also be referred to as a second light emitting control transistor that controls the emission of the second light emitting element De2.

[0125] The ninth transistor T9 applies the initialization voltage Vini to the anode electrode of the second light emitting element De2. The ninth transistor T9 includes a source electrode connected to an initialization line transmitting the initialization voltage Vini, a drain electrode connected to the anode electrode of the second light emitting element De2, and a gate electrode connected to an Nth scan signal Scan(N) line transmitting the Nth scan signal Scan(N). Thus, the ninth transistor T9 applies the initialization voltage Vini to the anode electrode of the second light emitting element De2 in response to the Nth scan signal Scan(N) having a low level as a turn-on level.

[0126] The tenth transistor T10 applies a reference voltage Vref to the fourth node N4. The tenth transistor T10 includes a source electrode connected to a reference line transmitting the reference voltage Vref, a drain electrode connected to the fourth node N4, and a gate electrode connected to an (N-1)th scan signal Scan(N-1) line transmitting the (N-1)th scan signal Scan(N-1). The tenth transistor T10 applies the reference voltage Vref to the fourth node N4 in response to the (N-1)th scan signal Scan(N-1) having a low level as a turn-on level.

[0127] The eleventh transistor T11 applies a reference voltage Vref to the fourth node N4. The eleventh transistor T11 includes a source electrode connected to a reference line transmitting the reference voltage Vref, a drain electrode connected to the fourth node N4, and a gate electrode connected to an Nth scan signal Scan(N) line transmitting the Nth scan signal Scan(N). The eleventh transistor T11 applies the reference voltage Vref to the fourth node N4 in response to the Nth scan signal Scan(N) having a low level as a turn-on level.

[0128] The twelfth transistor T12 applies a high potential driving voltage VDD supplied from a high potential driving voltage line to the fourth node N4. The twelfth transistor T12 includes a source electrode connected to the high potential driving voltage line, a drain electrode connected to the fourth node N4, and a gate electrode connected to a first light emitting signal line EML1 transmitting a first light emitting signal EM1(N). The twelfth transistor T12 applies the high potential driving voltage VDD supplied from the high potential driving voltage line to the fourth node N4 in response to the first light emitting signal EM1(N) of a low level, which is a turn-on level.

[0129] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the second node N2, that is, one electrode of the capacitor Cst is connected to the gate electrode of the first transistor T1, which is a driving transistor, and the other electrode of the capacitor Cst is connected to the gate electrode of the twelfth transistor T12.

[0130] Figures 8A and 8B are waveform diagrams showing emission signals and scan signals in wide viewing mode and narrow viewing mode, respectively, of an organic light emitting display device according to an embodiment of the present invention. Figure 9A is a circuit diagram of a subpixel of an organic light emitting display device according to an embodiment of the present invention during an initial period in wide viewing mode and narrow viewing mode, respectively. Figure 9B is a circuit diagram of a subpixel of an organic light emitting display device according to an embodiment of the present invention during a sampling period in wide viewing mode and narrow viewing mode, respectively. Figure 9C is a circuit diagram of a subpixel of an organic light emitting display device according to an embodiment of the present invention during an emission period in wide viewing mode. Figure 9D is a circuit diagram of a subpixel of an organic light emitting display device according to an embodiment of the present invention during an emission period in narrow viewing mode.

[0131] 7, 8A and 8B, the driving of the light emitting display device 100 according to an embodiment of the present invention in the wide viewing mode and the narrow viewing mode will be considered as follows.

[0132] Specifically, during the initial period Ti in each of the wide field mode and narrow field mode, the N-1th scan signal Scan(N-1) is at a low level which is a turn-on level, the Nth scan signal Scan(N) is at a high level which is a turn-off level, the first light-emitting signal EM1(N) is at a high level which is a turn-off level, the second light-emitting signal EM2(N) is at a high level which is a turn-off level, and the third light-emitting signal EM3(N) is at a high level which is a turn-off level.

[0133] 9A, in the wide viewing mode and the narrow viewing mode, the fourth transistor T4 is turned on during the initial period Ti and applies the initialization voltage Vini to the second node N2, which is the gate electrode of the first transistor T1, so that the gate electrode of the first transistor T1 is initialized to the initialization voltage Vini.

[0134] The initialization voltage Vini can be selected within a voltage range that is sufficiently lower than the threshold voltage of the first transistor T1, and can be set to a voltage that is equal to or lower than the low-potential drive voltage VSS.

[0135] In the wide field mode and the narrow field mode, the tenth transistor T10 is turned on during the initial period Ti to apply the reference voltage Vref to the fourth node N4, and the initialization voltage Vini is applied to the first electrode of the capacitor Cst, and the reference voltage Vref is applied to the second electrode of the capacitor Cst.

[0136] The reference voltage Vref can be selected within a voltage range that is sufficiently lower than the threshold voltage of the first transistor T1, and can be set to a voltage that is the same as or lower than the low-potential drive voltage VSS.

[0137] And, referring to FIG. 9B, during the sampling period Ts in each of the wide field mode and narrow field mode, the N-1th scan signal Scan(N-1) is at a high level which is a turn-off level, the Nth scan signal Scan(N) is at a low level which is a turn-on level, the first light-emitting signal EM1(N) is at a high level which is a turn-off level, the second light-emitting signal EM2(N) is at a high level which is a turn-off level, and the third light-emitting signal EM3(N) is at a high level which is a turn-off level.

[0138] Therefore, during the sampling period Ts in each of the wide field of view mode and the narrow field of view mode, the second transistor T2 is turned on and the data voltage Vdata is applied to the first node N1, and the third transistor T3 is also turned on, so that the first transistor T1 is in diode connection and the gate electrode and the drain electrode of the first transistor T1 are shorted, so that the first transistor T1 operates like a diode.

[0139] In the wide field mode and the narrow field mode, a current Ids flows between the source and drain of the first transistor T1 during a sampling period Ts. Since the gate electrode and the drain electrode of the first transistor T1 are in a diode-connected state, the voltage of the second node N2 rises until the gate-source voltage Vgs of the first transistor T1 becomes Vth due to the current flowing from the source electrode to the drain electrode. During the sampling period Ts, the voltage of the second node N2 is charged to a voltage (Vdata+Vth) corresponding to the sum of the data voltage Vdata and the threshold voltage Vth of the first transistor T1.

[0140] In the wide field mode and the narrow field mode, the eleventh transistor T11 is turned on during the sampling period Ts to apply the reference voltage Vref to the fourth node N4. A voltage (Vdata+Vth) corresponding to the sum of the threshold voltages Vth of the first transistors T1 and T1 is applied to the first electrode of the capacitor Cst, and the reference voltage Vref is applied to the second electrode.

[0141] Meanwhile, the seventh transistor T7 and the ninth transistor T9 are turned on to apply the initialization voltage Vini to the anode electrode of the first light emitting element De1 and the initialization voltage Vini to the anode electrode of the second light emitting element De2. As a result, the anode electrode of the first light emitting element De1 and the anode electrode of the second light emitting element De2 are both initialized to the initialization voltage Vini. The initialization voltage Vini may be selected within a voltage range sufficiently lower than the operating voltages of the light emitting elements De1 and De2, and may be set to a voltage equal to or lower than the low potential driving voltage VSS.

[0142] Then, referring to FIG. 9C, during the emission period Te in the wide field mode, the (N-1)th scan signal Scan(N-1) is at a high level which is a turn-off level, the Nth scan signal Scan(N) is at a high level which is a turn-off level, the first light-emitting signal EM1(N) is at a low level which is a turn-on level, the second light-emitting signal EM2(N) is at a high level which is a turn-off level, and the third light-emitting signal EM3(N) is at a low level which is a turn-on level.

[0143] Thus, during the emission period Te in the wide viewing mode, the fifth transistor T5 is turned on to apply the high potential driving voltage VDD to the first node N1. The twelfth transistor T12 is turned on to apply the high potential driving voltage VDD to the fourth node N4. That is, the voltage of the fourth node N4 rises from the reference voltage Vref to the high potential driving voltage VDD. Since the second node N2 is coupled to the fourth node N4 through the capacitor Cst, the voltage change amount (VDD-Vref) of the fourth node N4 is reflected in the second node N2. Thus, the voltage of the second node N2, which is the gate electrode of the first transistor T1, changes to Vdata+Vth+(VDD-Vref). Thus, the gate-source voltage Vgs of the first transistor T1 can become Vdata+Vth-Vref. The eighth transistor T8 is also turned on to form a current path between the third node N3 and the second light emitting element De2. As a result, the driving current passing through the source electrode and the drain electrode of the first transistor T1 is applied to the second light emitting element De2.

[0144] The relational expression for the driving current Ioled flowing through the second light-emitting element De2 during the emission period Te in the wide viewing mode is expressed as Equation 1 below.

[0145] Ioled = k(Vgs-Vth) 2 =k(Vdata+Vth-Vref-Vth) 2 =k(Vdata-Vref) 2 ...(Formula 1)

[0146] In Equation 1, k represents a proportionality constant determined by the electron mobility, parasitic capacitance, channel capacitance, and the like of the first transistor T1.

[0147] As can be seen from Equation 1, the threshold voltage Vth component and the high potential driving voltage VDD component of the first transistor T1 are all eliminated from the relational equation of the driving current Ioled. This means that the driving current Ioled does not change even if the threshold voltage Vth and the high potential driving voltage VDD change in the light emitting display device 100 according to the present invention. In other words, the light emitting display device 100 according to an embodiment of the present invention can program the data voltage Vdata regardless of the amount of change in the threshold voltage Vth and the high potential driving voltage VDD.

[0148] Then, referring to FIG. 9D, during the emission period Te in the narrow field mode, the (N-1)th scan signal Scan(N-1) is at a high level which is a turn-off level, the Nth scan signal Scan(N) is at a high level which is a turn-off level, the first light-emitting signal EM1(N) is at a low level which is a turn-on level, the second light-emitting signal EM2(N) is at a low level which is a turn-on level, and the third light-emitting signal EM3(N) is at a high level which is a turn-off level.

[0149] Thus, during the emission period Te in the narrow viewing mode, the fifth transistor T5 is turned on to apply the high potential driving voltage VDD to the first node N1. And the twelfth transistor T12 is turned on to apply the high potential driving voltage VDD to the fourth node N4. That is, the voltage of the fourth node N4 rises from the reference voltage Vref to the high potential driving voltage VDD. And the voltage of the second node N2 changes to Vdata+Vth+(VDD-Vref) due to the coupling of the capacitor Cst. Then, the gate-source voltage Vgs of the first transistor T1 can be Vdata+Vth-Vref. And the sixth transistor T6 is also turned on to form a current path between the third node N3 and the first light emitting element De1. As a result, the driving current passing through the source electrode and the drain electrode of the first transistor T1 is applied to the first light emitting element De1.

[0150] The relational expression for the driving current Ioled flowing through the first light emitting element De1 during the emission period Te in the narrow viewing mode is expressed as Equation 1. Therefore, the light emitting display device 100 according to an embodiment of the present invention can program the data voltage Vdata regardless of the change in the threshold voltage Vth and the high potential driving voltage VDD.

[0151] In the following, the driving operation of the first display area AA1 and the second display area AA2 will be described with reference to FIGS.

[0152] Fig. 10 is a schematic enlarged plan view of a display panel of a light emitting display device according to an embodiment of the present invention. Fig. 11 is a schematic enlarged plan view of a display panel operated in a wide viewing mode and a narrow viewing mode. For convenience of explanation, Figs. 10 and 11 show only a part of the display panel in an enlarged manner.

[0153] 10, a gate driver GD is mounted in a display area AA of a display panel PN. The gate driver GD includes a plurality of scan signal generators GIAS and a plurality of light emitting signal generators GIAE1, GIAE2, and GIAE3 mounted in the first display area AA1 and the second display area AA2, respectively, and the plurality of light emitting signal generators GIAE1, GIAE2, and GIAE3 include a plurality of first light emitting signal generators GIAE1, a plurality of second light emitting signal generators GIAE2, and a plurality of third light emitting signal generators GIAE3. The gate driver GD may be disposed between a plurality of sub-pixels SP in the display area AA. A plurality of sub-pixels SP may be disposed between the plurality of scan signal generators GIAS and the plurality of light emitting signal generators GIAE1, GIAE2, and GIAE3, respectively.

[0154] For example, the first display area AA1 includes a plurality of scan signal generating units GIAS connected to a plurality of scan signal lines SL, a plurality of first light-emitting signal generating units GIAE1 connected to a plurality of first light-emitting signal lines EML1, a plurality of second light-emitting signal generating units GIAE2 connected to a plurality of second light-emitting signal lines EML2, and a plurality of third light-emitting signal generating units GIAE3 connected to a plurality of third light-emitting signal lines EML3.

[0155] The second display area AA2 also includes a plurality of scan signal generating units GIAS connected to a plurality of scan signal lines SL, a plurality of first light-emitting signal generating units GIAE1 connected to a plurality of first light-emitting signal lines EML1, a plurality of second light-emitting signal generating units GIAE2 connected to a plurality of second light-emitting signal lines EML2, and a plurality of third light-emitting signal generating units GIAE3 connected to a plurality of third light-emitting signal lines EML3.

[0156] In this case, the scan signals Scan may be multi-output from the scan signal generating units GIAS to each of the scan signal lines SL. One scan signal line SL is connected to the scan signal generating units GIAS, and the scan signals Scan generated by each of the scan signal generating units GIAS may be simultaneously applied to the scan signal line SL. For example, one scan signal line SL may receive the scan signals Scan from the scan signal generating units GIAS in the first display area AA1 and the scan signal generating units GIAS in the second display area AA2 simultaneously. In this case, since the scan signals Scan are simultaneously input to the scan signal line SL from multiple points of the scan signal line SL, it is possible to reduce delays of the scan signals Scan transmitted through the scan signal line SL and reduce variations in the scan signals Scan transmitted to the sub-pixels SP connected to one scan signal line SL.

[0157] If the scan signal Scan is applied to only one end of the scan signal line SL, a delay may occur in the process of transmitting the scan signal Scan to the other end of the scan signal line SL, which may cause delay variations in the scan signal Scan between the multiple scan signal lines SL, resulting in a deterioration in display quality.

[0158] In contrast, as in the light emitting display device 100 according to one embodiment of the present invention, a plurality of scan signal generating units GIAS are formed in the display area AA, and the scan signal Scan is applied to the scan signal line SL from a plurality of points, thereby minimizing the delay of the scan signal Scan.

[0159] Next, each of the first light-emitting signal lines EML1 is connected to a plurality of first light-emitting signal generating units GIAE1, and the first light-emitting signals EM1(N) may be multi-output from the first light-emitting signal generating units GIAE1 to each of the first light-emitting signal lines EML1. One first light-emitting signal line EML1 is connected to the plurality of first light-emitting signal generating units GIAE1, and the first light-emitting signals EM1(N) generated by each of the first light-emitting signal generating units GIAE1 may be simultaneously applied to the first light-emitting signal line EML1. For example, one first light-emitting signal line EML1 may simultaneously receive the first light-emitting signals EM1(N) from the plurality of first light-emitting signal generating units GIAE1 in the first display area AA1 and the plurality of first light-emitting signal generating units GIAE1 in the second display area AA2. In this case, since the first light-emitting signal EM1(N) is input to the first light-emitting signal line EML1 simultaneously from multiple points on the first light-emitting signal line EML1, the delay of the first light-emitting signal EM1(N) transmitted through the first light-emitting signal line EML1 can be reduced. Also, by adjusting the position of the first light-emitting signal generating unit GIAE1 connected to the first light-emitting signal line EML1, the delay variation of the first light-emitting signal EM1(N) transmitted from the first display area AA1 and the second display area AA2 to the first light-emitting signal line EML1 can be reduced.

[0160] The second light-emitting signal lines EML2 are connected to the second light-emitting signal generating units GIAE2, and the second light-emitting signals EM2(N) may be multi-output from the second light-emitting signal generating units GIAE2 to the second light-emitting signal lines EML2. That is, the second light-emitting signal EM2(N) may be input to multiple points of the second light-emitting signal line EML2 simultaneously. One second light-emitting signal line EML2 is connected to the second light-emitting signal generating units GIAE2, and the second light-emitting signals EM2(N) generated in the second light-emitting signal generating units GIAE2 may be applied to the second light-emitting signal line EML2 simultaneously.

[0161] The third light-emitting signal lines EML3 are connected to the third light-emitting signal generating units GIAE3, and the second light-emitting signals EM2(N) may be multi-output from the third light-emitting signal generating units GIAE3 to the third light-emitting signal lines EML3. That is, the third light-emitting signal EM3(N) may be input to multiple points of the third light-emitting signal line EML3 simultaneously. One third light-emitting signal line EML3 is connected to the third light-emitting signal generating units GIAE3, and the third light-emitting signals EM3(N) generated in the third light-emitting signal generating units GIAE3 may be applied to the third light-emitting signal line EML3 simultaneously.

[0162] Meanwhile, the plurality of scan signal lines SL and the plurality of first light-emitting signal lines EML1 extend continuously throughout the first display area AA1 and the second display area AA2, but the plurality of second light-emitting signal lines EML2 and the plurality of third light-emitting signal lines EML3 are separated at the boundary between the first display area AA1 and the second display area AA2. Thus, the second light-emitting signal line EML2 disposed in the first display area AA1 is separated from the second light-emitting signal line EML2 disposed in the second display area AA2 and is spaced apart from each other, and the third light-emitting signal line EML3 disposed in the first display area AA1 is also separated from the third light-emitting signal line EML3 disposed in the second display area AA2 and is spaced apart from each other.

[0163] For example, the second light-emitting signal lines EML2 include a plurality of 2-1 light-emitting signal lines EML2-1 arranged in the first display area AA1 and transmitting the second light-emitting signal EM2(N) to the sub-pixels SP of the first display area AA1, and a plurality of 2-2 light-emitting signal lines EML2-2 arranged in the second display area AA2 and transmitting the second light-emitting signal EM2(N) to the sub-pixels SP of the second display area AA2. The third light-emitting signal lines EML3 include a plurality of 3-1 light-emitting signal lines EML3-1 arranged in the first display area AA1 and transmitting the third light-emitting signal EM3(N) to the sub-pixels SP of the first display area AA1, and a plurality of 3-2 light-emitting signal lines EML3-2 arranged in the second display area AA2 and transmitting the third light-emitting signal EM3(N) to the sub-pixels SP of the second display area AA2.

[0164] In this case, the second light-emitting signals EM2(N) from the multiple second light-emitting signal generating units GIAE2 arranged in the first display area AA1 can be transferred to the multiple 2-1 light-emitting signal lines EML2-1, and the second light-emitting signals EM2(N) from the multiple second light-emitting signal generating units GIAE2 arranged in the second display area AA2 can be transferred to the multiple 2-2 light-emitting signal lines EML2-2. And the third light-emitting signals EM3(N) from the multiple third light-emitting signal generating units GIAE3 arranged in the first display area AA1 can be transferred to the multiple 3-1 light-emitting signal lines EML3-1, and the third light-emitting signals EM3(N) from the multiple third light-emitting signal generating units GIAE3 arranged in the second display area AA2 can be transferred to the multiple 3-2 light-emitting signal lines EML3-2.

[0165] In the light emitting display device 100 according to an embodiment of the present invention, the first display area AA1 and the second display area AA2 can be independently driven in either the wide-angle mode or the narrow-angle mode by separating the second light emitting signal line EML2 and the third light emitting signal line EML3 arranged in the first display area AA1 and the second display area AA2, respectively. For example, while the first display area AA1 is driven in the wide-angle mode, the second display area AA2 can be driven in either the narrow-angle mode or the wide-angle mode, and while the second display area AA2 is driven in the narrow-angle mode, the first display area AA1 can be driven in either the narrow-angle mode or the wide-angle mode.

[0166] For example, as shown in Fig. 11, when the first display area AA1 is driven in the wide viewing mode and the second display area AA2 is driven in the narrow viewing mode, only the third light emitting signal generating unit GIAE3 of the second light emitting signal generating unit GIAE2 and the third light emitting signal generating unit GIAE3 of the first display area AA1 can output the third light emitting signal EM3(N) of a low level that is a turn-on level. In this case, the sixth transistor T6 forming a current path between the first light emitting element De1 and the first transistor T1 maintains a turned-off state, and the eighth transistor T8 forming a current path between the second light emitting element De2 and the first transistor T1 is turned on to transmit a driving current to the second light emitting element De2. That is, the sub-pixels SP arranged in the first display area AA1 can operate as shown in Fig. 9C during the emission period, and thus the first display area AA1 can operate in the wide viewing mode.

[0167] In addition, when the first display area AA1 is driven in the wide viewing mode and the second display area AA2 is driven in the narrow viewing mode, only the second light emitting signal generating unit GIAE2 of the second display area AA2 and the third light emitting signal generating unit GIAE3 can output the second light emitting signal EM2(N) of a low level that is a turn-on level. In this case, the sixth transistor T6 forming a current path between the first light emitting element De1 and the first transistor T1 can be turned on to transmit a driving current to the first light emitting element De1, and the eighth transistor T8 forming a current path between the second light emitting element De2 and the first transistor T1 can be maintained in a turned off state. That is, the sub-pixels SP arranged in the second display area AA2 can operate as shown in FIG. 9C during the emission period, and therefore the second display area AA2 can operate in the narrow viewing mode.

[0168] In this case, even if the third light-emitting signal generating unit GIAE3 in the first display area AA1 outputs a low-level third light-emitting signal EM3(N), the 3-1 light-emitting signal line EML3-1 in the first display area AA1 and the 3-2 light-emitting signal line EML3-2 in the second display area AA2 are separated from each other, so the low-level third light-emitting signal EM3(N) is not transmitted to the second display area AA2. Then, the second light-emitting signal generating unit GIAE2 in the second display area AA2 outputs a low-level second light-emitting signal EM2(N), but the 2-1 light-emitting signal line EML2-1 in the first display area AA1 and the 2-2 light-emitting signal line EML2-2 in the second display area AA2 are separated from each other, so the low-level second light-emitting signal EM2(N) is not transmitted to the first display area AA1. Therefore, by arranging a plurality of second light-emitting signal generating units GIAE2 and a plurality of third light-emitting signal generating units GIAE3 in the first display area AA1 and the second display area AA2, respectively, and separating the plurality of second light-emitting signal lines EML2 and the plurality of third light-emitting signal lines EML3 arranged in the first display area AA1 and the second display area AA2, the first display area AA1 and the second display area AA2 can be driven independently in wide-field mode and narrow-field mode.

[0169] As another example, when the first display area AA1 is driven in a narrow viewing mode and the second display area AA2 is driven in a wide viewing mode, the gate driver GD can output low-level emission signals EM2(N) and EM3(N), which are turn-on levels, only to the 2-1 emission signal line EML2-1 of the first display area AA1 and the 3-2 emission signal line EML3-2 of the second display area AA2.

[0170] As another example, when both the first display area AA1 and the second display area AA2 are driven in the wide viewing mode, the gate driver GD can output low-level emission signals EM2(N) and EM3(N), which are turn-on levels, only to the 2-2 emission signal line EML2-2 of the first display area AA1 and the 3-2 emission signal line EML3-2 of the second display area AA2.

[0171] As another example, when both the first display area AA1 and the second display area AA2 are driven in the narrow viewing mode, the gate driver GD can output low-level emission signals EM2(N) and EM3(N), which are turn-on levels, only to the 2-1 emission signal line EML2-1 of the first display area AA1 and the 3-1 emission signal line EML3-1 of the second display area AA2.

[0172] Therefore, in the light emitting display device 100 according to an embodiment of the present invention, the second light emitting signal line EML2 and the third light emitting signal line EML3 arranged in the first display area AA1 and the second display area AA2 are separated, and a separate second light emitting signal generating unit GIAE2 and a third light emitting signal generating unit GIAE3 are formed in the separated second light emitting signal line EML2 and the third light emitting signal line EML3, respectively, so that the wide viewing mode and the narrow viewing mode of the first display area AA1 and the second display area AA2 can be independently controlled. Since the second light emitting signal line EML2 of the first display area AA1 and the second light emitting signal line EML2 of the second display area AA2 are separated from each other, the second display area AA2 can be driven in the narrow viewing mode regardless of the mode of the first display area AA1, and the first display area AA1 can also be driven in the narrow viewing mode without being limited by the mode of the second display area AA2. In addition, since the third light-emitting signal line EML3 of the first display area AA1 and the third light-emitting signal line EML3 of the second display area AA2 are separated from each other, the second display area AA2 can be driven in the wide viewing mode regardless of the mode of the first display area AA1, and the first display area AA1 can also be driven in the wide viewing mode without being limited to the mode of the second display area AA2. Therefore, in the light emitting display device 100 according to an embodiment of the present invention, only a specific area of ​​the screen can be freely and selectively switched to either the wide viewing mode or the narrow viewing mode.

[0173] In the light emitting display device 100 according to an embodiment of the present invention, a plurality of scan signal generating units GIAS and a plurality of light emitting signal generating units GIAE1, GIAE2, and GIAE3 are disposed in the display area AA, thereby reducing delays of signals transmitted to a plurality of wirings. For example, scan signals Scan may be simultaneously applied from a plurality of scan signal generating units GIAS to one scan signal line SL. That is, the scan signals Scan may be multi-output to one scan signal line SL. Thus, by applying the scan signals Scan to one scan signal line SL from a plurality of points, delays of the scan signals Scan transmitted to the entire scan signal line SL may be reduced. Therefore, in the light emitting display device 100 according to an embodiment of the present invention, a plurality of scan signal generating units GIAS are connected to each of the plurality of scan signal lines SL, and a plurality of light emitting signal generating units GIAE1, GIAE2, and GIAE3 are connected to each of the plurality of light emitting signal lines EML1, EML2, and EML3, thereby reducing delays of the scan signals Scan and light emitting signals transmitted to a plurality of sub-pixels SP and variations therein.

[0174] In the light emitting display device 100 according to an embodiment of the present invention, the area of ​​the non-display area NA, for example, the size of a bezel, can be reduced by mounting the gate driver GD in the display area AA. Since the gate driver GD is disposed inside the display area AA, a part of the non-display area NA where the gate driver GD was previously disposed can be deleted, thereby reducing the area of ​​the non-display area NA.

[0175] 12 is a schematic enlarged plan view of a display panel of an organic light emitting display device according to another embodiment of the present invention. The organic light emitting display device 1200 of FIG 12 is different from the organic light emitting display device 100 of FIG 1 to FIG 11 only in the display area AA, the gate driver GD, the second light emitting signal line EML2, and the third light emitting signal line EML3, and other configurations are substantially the same, so that redundant description will be omitted.

[0176] 12, the display area AA includes a first display area AA1, a second display area AA2, and a third display area AA3. The first display area AA1, the second display area AA2, and the third display area AA3 are arranged in sequence.

[0177] A gate driver GD is disposed in each of the first display area AA1, the second display area AA2, and the third display area AA3. One or more scan signal generators GIAS and one or more light emission signal generators GIAE1, GIAE2, and GIAE3 are disposed in each of the first display area AA1, the second display area AA2, and the third display area AA3.

[0178] The scan signal lines SL and the first light-emitting signal lines EML1 are arranged to extend across the entire display area AA. One scan signal line SL and one first light-emitting signal line EML1 may be connected to sub-pixels SP arranged in the first display area AA1, the second display area AA2, and the third display area AA3. That is, the first display area AA1, the second display area AA2, and the third display area AA3 each share the scan signal line SL and the first light-emitting signal line EML1.

[0179] A plurality of second light-emitting signal lines EML2 and a plurality of third light-emitting signal lines EML3 are arranged in the first display area AA1, the second display area AA2, and the third display area AA3, respectively. The plurality of second light-emitting signal lines EML2 and the plurality of third light-emitting signal lines EML3 corresponding to the first display area AA1, the second display area AA2, and the third display area AA3, respectively, are separated from each other. The plurality of second light-emitting signal lines EML2 and the plurality of third light-emitting signal lines EML3 may be separated at the boundary between the first display area AA1 and the second display area AA2 and the boundary between the second display area AA2 and the third display area AA3.

[0180] Specifically, the second light-emitting signal lines EML2 include a 2-1 light-emitting signal line EML2-1 connected to the sub-pixels SP and the second light-emitting signal generating unit GIAE2 in the first display area AA1, a 2-2 light-emitting signal line EML2-2 connected to the sub-pixels SP and the second light-emitting signal generating unit GIAE2 in the second display area AA2, and a 2-3 light-emitting signal line EML2-3 connected to the sub-pixels SP and the second light-emitting signal generating unit GIAE2 in the third display area AA3. The 2-1 light-emitting signal line EML2-1, the 2-2 light-emitting signal line EML2-2, and the 2-3 light-emitting signal line EML2-3 are not connected to each other but are separated from each other.

[0181] The third light-emitting signal lines EML3 include a 3-1 light-emitting signal line EML3-1 connected to the sub-pixels SP and the third light-emitting signal generating unit GIAE3 in the first display area AA1, a 3-2 light-emitting signal line EML3-2 connected to the sub-pixels SP and the third light-emitting signal generating unit GIAE3 in the second display area AA2, and a 3-3 light-emitting signal line EML3-3 connected to the sub-pixels SP and the third light-emitting signal generating unit GIAE3 in the third display area AA3. The 3-1 light-emitting signal line EML3-1, the 3-2 light-emitting signal line EML3-2, and the 3-3 light-emitting signal line EML3-3 are not connected to each other but are separated from each other.

[0182] Therefore, the second light-emitting signal EM2(N) and the third light-emitting signal EM3(N) of different levels can be applied to the sub-pixels SP of each of the first display area AA1, the second display area AA2, and the third display area AA3. In this case, the first display area AA1, the second display area AA2, and the third display area AA3 can be driven in either the wide-view mode or the narrow-view mode by selecting them. For example, while the first display area AA1 is driven in the wide-view mode by applying the second light-emitting signal EM2(N) of high level and the third light-emitting signal EM3(N) of low level to the first display area AA1, the second display area AA2 and the third display area AA3 are driven in the narrow-view mode by applying the second light-emitting signal EM2(N) of low level and the third light-emitting signal EM3(N) of high level to the second display area AA2 and the third display area AA3.

[0183] Therefore, in the light emitting display device 1200 according to another embodiment of the present invention, the display area AA is separated into a plurality of areas, and each of the plurality of areas can be independently driven in a wide viewing mode or a narrow viewing mode. In this case, the number of the separated display areas AA can be variously changed according to design, and the design of the gate driver GD and the second and third light emitting signal lines EML2 and EML3 can also be changed to correspond to the display area AA.

[0184] An embodiment of the present invention can also be described as follows.

[0185] According to an aspect of the present invention, a light emitting display device according to one embodiment of the present invention includes a display panel having a plurality of display areas defined therein, including a first display area and a second display area, a plurality of sub-pixels arranged in each of the plurality of display areas, and a gate driver implemented in the plurality of display areas, each of the plurality of sub-pixels including a first light emitting element that emits light in response to a driving current, a first lens that refracts light from the first light emitting element, a second light emitting element that emits light in response to a driving current, and a second lens that refracts light from the second light emitting element and has a shape different from the first lens.

[0186] According to another feature of the present invention, the first lens may be a half-spherical lens, and the second lens may be a half-cylindrical lens.

[0187] According to another feature of the present invention, each of the plurality of display regions can be independently driven in either a narrow viewing mode or a wide viewing mode, in which a first light-emitting element emits light and the light from the first light-emitting element is output with a viewing angle limited by a first lens in a first direction and a second direction, and in which a second light-emitting element emits light and the light from the second light-emitting element is output with a viewing angle limited only in the first direction by a second lens, the viewing angle of the second lens being different from that of the first lens and in most cases being larger than that of the first lens.

[0188] According to another aspect of the present invention, each of the sub-pixels may be separately driven during an initial period, a sampling period, and an emission period, and a driving current may be applied to the first light emitting element or the second light emitting element during the emission period.

[0189] According to another feature of the present invention, each of the plurality of sub-pixels further includes a driving transistor for controlling a driving current, a first emission control transistor connected between the driving transistor and the first light-emitting element and for transmitting the driving current to the first light-emitting element, and a second emission control transistor connected between the driving transistor and the second light-emitting element and for transmitting the driving current to the second light-emitting element, and in a narrow field of view mode, the first emission control transistor is turned on and the second emission control transistor is turned off, and in a wide field of view mode, the first emission control transistor is turned off and the second emission control transistor is turned on.

[0190] According to another feature of the present invention, the display device may further include an emission signal line for transmitting an emission signal to a gate electrode of the first emission control transistor, and the emission signal line of the first display area may be separated from the emission signal line of the second display area.

[0191] According to another aspect of the present invention, the gate driver includes a plurality of light emission signal generating units mounted in each of the first and second display areas and outputting light emission signals to light emission signal lines of each of the first and second display areas, and one light emission signal line can receive a plurality of light emission signals output from the plurality of light emission signal generating units.

[0192] According to another aspect of the present invention, the pixel may further include an emission signal line for transmitting an emission signal to a gate electrode of the second emission control transistor, and the emission signal line of the first display area may be separated from the emission signal line of the second display area.

[0193] According to another feature of the present invention, the gate driver includes a plurality of light emitting signal generating units mounted in the first display area and the second display area, respectively, for outputting light emitting signals to light emitting signal lines of the first display area and the second display area, and the light emitting signals outputted by the plurality of light emitting signal generating units mounted in the first display area are transmitted only to the light emitting signal lines of the first display area, and the light emitting signals outputted by the plurality of light emitting signal generating units mounted in the second display area are transmitted only to the light emitting signal lines of the second display area.

[0194] According to another aspect of the present invention, a light emitting display device according to another embodiment of the present invention includes a display panel having a display area defined including a first display area and a second display area, a plurality of sub-pixels arranged in each of the first display area and the second display area, and a gate driver implemented in the first display area and the second display area, and each of the plurality of sub-pixels includes a first light emitting element that emits light in a narrow viewing mode by a driving current, a hemispherical lens configured to refract light from the first light emitting element and limit the viewing angle in a first direction and a second direction, a second light emitting element that emits light in a wide viewing mode by a driving current, and a semi-cylindrical lens configured to refract light from the second light emitting element and limit the viewing angle only in the first direction.

[0195] According to another aspect of the present invention, each of the plurality of subpixels may further include a first transistor for controlling a driving current, the first transistor including a source electrode connected to the first node, a gate electrode connected to the second node, and a drain electrode connected to the third node, a second transistor for applying a data voltage to the first node, a third transistor for diode-connecting a gate electrode and a drain electrode of the first transistor, a fourth transistor for applying an initialization voltage to a gate electrode of the first transistor, a fifth transistor for applying a high potential driving voltage to the first node, a sixth transistor for forming a current path between the first transistor and the first light emitting element, a seventh transistor for applying an initialization voltage to an anode electrode of the first light emitting element, an eighth transistor for forming a current path between the first transistor and the second light emitting element, a ninth transistor for applying an initialization voltage to an anode electrode of the second light emitting element, a capacitor having one end connected to the second node and the other end connected to the fourth node, tenth and eleventh transistors for applying a reference voltage to the fourth node, and a twelfth transistor for applying a high potential driving voltage to the fourth node.

[0196] According to another aspect of the present invention, the display panel may further include a first light-emitting signal line applying a first light-emitting signal to a gate electrode of the fifth transistor and a gate electrode of the twelfth transistor of each of the plurality of sub-pixels, a second light-emitting signal line applying a second light-emitting signal to a gate electrode of the sixth transistor of each of the plurality of sub-pixels, and a third light-emitting signal line applying a third light-emitting signal to a gate electrode of the eighth transistor of each of the plurality of sub-pixels.

[0197] According to another aspect of the present invention, the gate driver may include a plurality of first light-emitting signal generating units each outputting a first light-emitting signal to a first light-emitting signal line, a plurality of second light-emitting signal generating units each outputting a second light-emitting signal to a second light-emitting signal line, and a plurality of third light-emitting signal generating units each outputting a third light-emitting signal to a third light-emitting signal line.

[0198] According to another feature of the present invention, the second light-emitting signal line includes a 2-1 light-emitting signal line connected to a plurality of sub-pixels in the first display region and a 2-2 light-emitting signal line connected to a plurality of sub-pixels in the second display region, and some of the plurality of second light-emitting signal generating units output the second light-emitting signal to the 2-1 light-emitting signal line, and other some of the plurality of second light-emitting signal generating units output the second light-emitting signal to the 2-2 light-emitting signal line.

[0199] According to another feature of the present invention, the third light-emitting signal line includes a 3-1 light-emitting signal line connected to a plurality of sub-pixels in the first display region and a 3-2 light-emitting signal line connected to a plurality of sub-pixels in the second display region, and some of the plurality of third light-emitting signal generators output the third light-emitting signal to the 3-1 light-emitting signal line, and other some of the plurality of third light-emitting signal generators output the third light-emitting signal to the 3-2 light-emitting signal line.

[0200] According to another feature of the present invention, when the first display area is driven in a wide viewing mode and the second display area is driven in a narrow viewing mode, the gate driver can output a second light-emitting signal and a third light-emitting signal of a turn-on level to the 2-2 light-emitting signal line and the 3-1 light-emitting signal line.

[0201] According to another feature of the present invention, when the first display area is driven in a narrow viewing mode and the second display area is driven in a wide viewing mode, the gate driver can output a second light-emitting signal and a third light-emitting signal of a turn-on level to the 2-1 light-emitting signal line and the 3-2 light-emitting signal line.

[0202] According to another feature of the present invention, when the first and second display areas are driven in a wide viewing mode, the gate driver outputs a second light-emitting signal and a third light-emitting signal of a turn-on level to the 2-2 light-emitting signal line and the 3-2 light-emitting signal line, and when the first and second display areas are driven in a narrow viewing mode, the gate driver outputs a second light-emitting signal and a third light-emitting signal of a turn-on level to the 2-1 light-emitting signal line and the 3-1 light-emitting signal line.

[0203] According to another feature of the present invention, the display area further includes a third display area, the second light-emitting signal line further includes a 2-3 light-emitting signal line connected to a plurality of sub-pixels of the third display area, the third light-emitting signal line further includes a 3-3 light-emitting signal line connected to a plurality of sub-pixels of the third display area, and another portion of the plurality of second light-emitting signal generating units output a second light-emitting signal to the 2-3 light-emitting signal line, and another portion of the plurality of third light-emitting signal generating units output a third light-emitting signal to the 3-3 light-emitting signal line.

[0204] Although the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made within the scope of the technical idea of ​​the present invention. Therefore, the embodiments disclosed in the present invention are for illustration purposes, not for limiting the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative and not restrictive in all respects. The scope of protection of the present invention should be interpreted according to the following claims, and all technical ideas within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

[0205] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments, along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by this disclosure. [Explanation of symbols]

[0206] 100 Light emitting display device 210 Shading Pattern 220 Optical Gap Layer 230 Lens Layer

Claims

1. a display panel in which a plurality of display areas including a first display area and a second display area are defined; A plurality of sub-pixels arranged in each of the plurality of display regions; a gate driver mounted in the plurality of display areas and supplying gate signals to gate lines of the display panel; Each of the plurality of sub-pixels is a first light emitting element that emits light in response to a driving current; A first lens that refracts light from the first light emitting element; a second light emitting element that emits light in response to the driving current; a second lens that refracts light from the second light emitting element and has a shape different from that of the first lens; The first lens includes a half-spherical lens, The light emitting display device, wherein the second lens includes a half-cylindrical lens.

2. Each of the plurality of display areas is independently driven in either a narrow viewing mode or a wide viewing mode; In the narrow field mode, the first light-emitting element emits light, and the light from the first light-emitting element is output with a viewing angle limited by the first lens in a first direction and a second direction intersecting the first direction; The light-emitting display device according to claim 1 , wherein in the wide viewing mode, the second light-emitting element emits light, and the light from the second light-emitting element is output with a viewing angle limited only in the first direction by the second lens.

3. Each of the plurality of sub-pixels is separately driven during an initial period, a sampling period, and an emission period; The light emitting display device according to claim 2 , wherein the driving current is applied to the first light emitting element or the second light emitting element during the emission period.

4. Each of the plurality of sub-pixels is a drive transistor for controlling the drive current; a first light-emitting control transistor electrically connected between the driving transistor and the first light-emitting element and configured to transmit the driving current to the first light-emitting element; a second light-emitting control transistor electrically connected between the driving transistor and the second light-emitting element and configured to transmit the driving current to the second light-emitting element; In the narrow viewing mode, the first light-emitting control transistor is turned on and the second light-emitting control transistor is turned off; 4. The light emitting display device of claim 3, wherein in the wide viewing mode, the first light emitting control transistor is turned off and the second light emitting control transistor is turned on.

5. a light emission signal line for transmitting a light emission signal to a gate electrode of the first light emission control transistor, The light emitting display device according to claim 4 , wherein the light emitting signal line of the first display area is separated from the light emitting signal line of the second display area.

6. The gate driver includes: a plurality of light emission signal generating units mounted in the first display area and the second display area, respectively, for outputting the light emission signal to the light emission signal line of each of the first display area and the second display area; The light emitting display device of claim 5 , wherein one of the light emitting signal lines receives the light emitting signals output from the light emitting signal generators.

7. a light emission signal line for transmitting a light emission signal to a gate electrode of the second light emission control transistor, The light emitting display device of claim 4 , wherein the light emitting signal line of the first display area is spaced apart from the light emitting signal line of the second display area.

8. The gate driver includes: a plurality of light emission signal generating units mounted in the first display area and the second display area, respectively, for outputting the light emission signal to the light emission signal line of each of the first display area and the second display area; the light emission signals outputted from the plurality of light emission signal generating units mounted in the first display region are transmitted only to the light emission signal lines of the first display region; The light emitting display device according to claim 7 , wherein the light emitting signals outputted from the plurality of light emitting signal generating units mounted in the second display area are transmitted only to the light emitting signal lines of the second display area.

9. a display panel having a display area defined therein, the display area including a first display area and a second display area; A plurality of sub-pixels arranged in each of the first display region and the second display region; a gate driver mounted in the first display area and the second display area and supplying gate signals to gate lines of the display panel; Each of the plurality of sub-pixels is a first light emitting element that emits light in a narrow viewing mode in response to a driving current; a hemispherical lens configured to refract light from the first light emitting element to limit a viewing angle in a first direction and a second direction intersecting the first direction; a second light-emitting element that emits light in a wide viewing mode by the driving current; a semi-cylindrical lens configured to refract light from the second light emitting element to limit a viewing angle only to the first direction.

10. the first direction includes a vertical direction including an upward direction and a downward direction; The light emitting display device of claim 9 , wherein the second direction comprises a horizontal direction including a right direction and a left direction.

11. Each of the plurality of sub-pixels is a first transistor for controlling the driving current, the first transistor including a source electrode electrically connected to a first node, a gate electrode electrically connected to a second node, and a drain electrode electrically connected to a third node; a second transistor for applying a data voltage to the first node; a third transistor for diode-connecting a gate electrode and a drain electrode of the first transistor; a fourth transistor for applying an initialization voltage to a gate electrode of the first transistor; a fifth transistor for applying a high potential drive voltage to the first node; a sixth transistor forming a current path between the first transistor and the first light emitting element; a seventh transistor that applies the initialization voltage to an anode electrode of the first light emitting element; an eighth transistor that forms a current path between the first transistor and the second light emitting element; a ninth transistor that applies the initialization voltage to an anode electrode of the second light emitting element; a capacitor having one end electrically connected to the second node and the other end electrically isolated from the fourth node; a tenth transistor and an eleventh transistor for applying a reference voltage to the fourth node; The light emitting display device of claim 9 , further comprising: a twelfth transistor applying the high potential driving voltage to the fourth node.

12. The display panel includes: a first light-emitting signal line applying a first light-emitting signal to a gate electrode of the fifth transistor and a gate electrode of the twelfth transistor of each of the plurality of sub-pixels; a second light-emitting signal line applying a second light-emitting signal to a gate electrode of the sixth transistor of each of the plurality of sub-pixels; The light emitting display device of claim 11 , further comprising: a third light emitting signal line applying a third light emitting signal to a gate electrode of the eighth transistor of each of the plurality of sub-pixels.

13. The gate driver includes: a plurality of first light emission signal generating units that output the first light emission signals to the first light emission signal lines; a plurality of second light emission signal generating units that output the second light emission signals to the second light emission signal lines; The light emitting display device of claim 12 , further comprising: a plurality of third light emitting signal generators outputting the third light emitting signals to the third light emitting signal lines.

14. the second light-emitting signal line includes a 2-1 light-emitting signal line electrically connected to the plurality of sub-pixels in the first display region and a 2-2 light-emitting signal line electrically connected to the plurality of sub-pixels in the second display region; 13. The light emitting display device of claim 12, wherein some of the plurality of second light emitting signal generating units output the second light emitting signal to the 2-1 light emitting signal line, and other some of the plurality of second light emitting signal generating units output the second light emitting signal to the 2-2 light emitting signal line.

15. the third light-emitting signal line includes a 3-1 light-emitting signal line electrically connected to the plurality of sub-pixels in the first display region and a 3-2 light-emitting signal line electrically connected to the plurality of sub-pixels in the second display region; 14. The light emitting display device of claim 13, wherein some of the plurality of third light emitting signal generating units output the third light emitting signal to the 3-1 light emitting signal line, and other some of the plurality of third light emitting signal generating units output the third light emitting signal to the 3-2 light emitting signal line.

16. 15. The light emitting display device of claim 14, wherein when the first display area is driven in the wide viewing mode and the second display area is driven in the narrow viewing mode, the gate driver outputs the second light emitting signal and the third light emitting signal of a turn-on level to the 2-2 light emitting signal line and the 3-1 light emitting signal line.

17. 15. The light emitting display device of claim 14, wherein when the first display area is driven in the narrow viewing mode and the second display area is driven in the wide viewing mode, the gate driver outputs the second light emitting signal and the third light emitting signal of a turn-on level to the 2-1 light emitting signal line and the 3-2 light emitting signal line.

18. When the first display area and the second display area are driven in the wide viewing mode, the gate driver outputs the second light emitting signal and the third light emitting signal of a turn-on level to the 2-2 light emitting signal line and the 3-2 light emitting signal line, 15. The light emitting display device of claim 14, wherein when the first display area and the second display area are driven in the narrow viewing mode, the gate driver outputs the second light emitting signal and the third light emitting signal of a turn-on level to the 2-1 light emitting signal line and the 3-1 light emitting signal line.

19. The display area further includes a third display area, the second light-emitting signal line further includes a second-third light-emitting signal line electrically connected to the plurality of sub-pixels of the third display area; the third light-emitting signal line further includes a 3-3 light-emitting signal line electrically connected to the plurality of sub-pixels of the third display area, 15. The light emitting display device of claim 14, wherein another part of the plurality of second light emitting signal generating units outputs the second light emitting signal to the second-third light emitting signal line, and another part of the plurality of third light emitting signal generating units outputs the third light emitting signal to the third-third light emitting signal line.

20. 1. A light-emitting display device comprising: a display panel configured to display an image, the image output by the display panel having a viewing angle, the display panel configured to selectively operate in a narrow viewing mode using a first lens and a wide viewing mode using a second lens that adjusts the viewing angle in one or more directions relative to the viewing angle of the first lens; the viewing angle is limited to a first value in the left and right directions in the narrow field of view mode; The light-emitting display device, wherein the viewing angle is greater than the first value in the left and right directions in the wide viewing mode.

21. a first light-emitting region of a sub-pixel in the display panel disposed below the first lens; The light emitting display device of claim 20 , further comprising: a second light emitting region of the sub-pixel in the display panel disposed below the second lens.

22. The light emitting display device of claim 21 , wherein in the narrow viewing mode, the first light emitting region is turned off and the second light emitting region is turned on.

23. The light emitting display device of claim 20 , wherein in the narrow viewing mode, a viewing angle is limited in an upward and downward direction by the second lens.

24. The light emitting display device of claim 21 , wherein in the narrow viewing mode, the first light emitting region is turned on and the second light emitting region is turned off.

25. The light emitting display device of claim 20 , wherein in the narrow viewing mode, a viewing angle is limited in an upward and downward direction by the first lens.

26. The light emitting display device of claim 20 , wherein in the narrow viewing mode, the degree of the viewing angle restricted in the left direction is different from the degree of the viewing angle restricted in the right direction.

27. the first lens comprises a hemispherical lens and the second lens comprises a hemicylindrical lens; The light emitting display device of claim 21 , wherein the first lens at least partially overlaps the first light emitting area, and the second lens at least partially overlaps the second light emitting area.

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