Display device and method for manufacturing the same

Abstract

To solve various problems with sub-pixels.SOLUTION: A display device is such that, in each sub-pixel, a cathode electrode layer and a power connection line at each undercut are electrically connected to each other via a structure providing the undercut, so that power can be stably supplied to each of sub-pixels via the power connection line electrically connected to a power line.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] This specification relates to a display device and a method of manufacturing the display device, and more particularly, provides a display device and a method of manufacturing the display device having a structure for applying a power supply to a cathode electrode layer.

Background Art

[0002] Display devices are configured in various forms such as televisions, monitors, smartphones, tablet PCs, notebook computers, wearable devices, and the like.

[0003] In an example of a display device, an organic light-emitting display device (OLED), which is a self-emitting display device, is advantageous not only in terms of power consumption by low-voltage driving but also has advantages in terms of color rendering, response speed, viewing angle, and contrast ratio of brightness and darkness.

[0004] The organic light-emitting display device may include a gate wiring intersecting with each other and a plurality of pixels defined by data wiring.

[0005] In this case, a power supply can be applied to each pixel for driving a plurality of pixels.

Summary of the Invention

Problems to be Solved by the Invention

[0006] The display device may include a power supply unit that applies a power supply to a plurality of pixels and a power supply wiring that supplies the power supply from the power supply unit.

[0007] The power supply wiring may be a high-potential voltage (VDD) wiring or a low-potential voltage (VSS) wiring.

[0008] For example, when the display device is an organic light-emitting display device, the low-potential voltage wiring can apply a low-potential voltage to a cathode electrode constituting an organic light-emitting diode.

[0009] When a low - potential voltage is applied to the cathode electrode, each pixel including an organic light - emitting diode connected to the cathode electrode can emit light.

[0010] Thus, in order to cause a plurality of pixels arranged in the display area to emit light, a low - potential voltage must be applied to the cathode electrodes connected to the plurality of pixels. The cathode electrode can be formed over the entire display area.

[0011] For example, the cathode electrode can be formed in the form of a planar electrode that covers the entire surface of the display area and can be formed as a common electrode for a plurality of pixels.

[0012] However, when the cathode electrode is formed in the form of a planar electrode that covers the entire surface of the display area, a parasitic capacitor may be formed between the cathode electrode and the data wiring that are arranged to overlap each other.

[0013] When a parasitic capacitor is formed between the cathode electrode and the data wiring in this way, a delay phenomenon of the electrical transmission speed (RC Delay) occurs, which may make it difficult to drive the display device at high speed.

[0014] Therefore, the inventors of the present specification have conducted various experiments that can reduce the occurrence of the delay phenomenon of the electrical transmission speed of the display device.

[0015] Through various experiments, the inventors of the present specification have found a display device and a method for manufacturing the display device, which have a structure that can reduce the generation of a parasitic capacitor between the cathode electrode layer and the data wiring and can supply a stable power source to the cathode electrode layer.

[0016] The problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device, which have a structure that can stably supply power to a plurality of sub - pixels respectively.

[0017] Another problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device, which can improve the light extraction efficiency in the organic light-emitting layer included in a plurality of sub-pixels.

[0018] Another problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device, which can reduce the generation of lateral leakage current in the organic light-emitting layer included in a plurality of sub-pixels.

[0019] Another problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device, which can reduce the generation of a parasitic capacitor between the cathode electrode layer and the data wiring.

[0020] Another problem to be solved by the embodiments of the present specification is to provide a display device and a method for manufacturing the display device, which can reduce the damage to the organic light-emitting layer that may occur during the formation process of the organic light-emitting layers included in a plurality of sub-pixels.

[0021] The problems to be solved by the embodiments of the present specification are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0022] The display device according to the embodiments of the present specification includes a plurality of sub-pixels, a power supply wiring for applying a voltage to the plurality of sub-pixels, and a plurality of power supply connection wirings for electrically connecting the plurality of sub-pixels to the power supply wiring.

[0023] In this case, each sub-pixel includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked. However, the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other. Each sub-pixel includes a structure that provides an undercut portion. The power connection wiring is arranged to overlap the structure and is electrically connected to the cathode electrode layer in the undercut portion.

[0024] Also, the display device according to the embodiment of the present specification includes a substrate on which a plurality of sub-pixels are defined, a plurality of power connection wirings arranged on the substrate, a plurality of structures arranged on the power connection wirings so as to be included in each sub-pixel and providing an undercut portion that exposes a part of the power connection wiring, a bank layer arranged on the power connection wiring and including a first opening that is opened to expose the undercut portion, and an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked so as to cover the bank layer and the structure.

[0025] In this case, the power connection wiring is electrically connected to the cathode electrode layer in the undercut portion, and the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other.

[0026] In addition, the method for manufacturing a display device according to the embodiments of the present specification includes forming a plurality of source-drain electrodes, a plurality of power connection wirings, and a plurality of data wirings on a substrate, and forming an overcoat layer; forming a plurality of anode electrode layers each electrically connected to a corresponding one of the plurality of source-drain electrodes and a plurality of second structure layers each electrically connected to a corresponding one of the plurality of power connection wirings on the overcoat layer; patterning the overcoat layer to form a plurality of first structure layers each providing an undercut portion below a corresponding one of the plurality of second structure layers, the plurality of first structure layers including a plurality of first openings exposing the outer peripheral sides of the plurality of undercut portions and a plurality of second openings exposing a part of the plurality of anode electrode layers; forming a first protective layer and a first photoresist film so as to expose the first openings and the second openings corresponding to a first sub-pixel, sequentially forming a first organic light-emitting layer exhibiting a first hue, a first cathode electrode layer, and a first passivation layer, and then removing the first protective layer and the first photoresist film; forming a second protective layer and a second photoresist film so as to expose the first openings and the second openings corresponding to a second sub-pixel, sequentially forming a second organic light-emitting layer exhibiting a second hue, a second cathode electrode layer, and a second passivation layer, and then removing the second protective layer and the second photoresist film; and forming a third protective layer and a third photoresist film so as to expose the first openings and the second openings corresponding to a third sub-pixel, sequentially forming a third organic light-emitting layer exhibiting a third hue, a third cathode electrode layer, and a third passivation layer, and then removing the third protective layer and the third photoresist film.

Advantages of the Invention

[0027] According to the embodiments of the present specification, since the cathode electrode layer and the power connection wiring in each of the undercut portions provided by the structures are electrically connected in each sub-pixel, power can be stably supplied to the plurality of sub-pixels respectively through the power connection wirings electrically connected to the power wiring.

[0028] Also, according to the embodiments of the present specification, since the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other, by the occurrence of an out-coupling phenomenon that allows the light of the organic light-emitting layer to escape to the outside at the insulated end, the light extraction efficiency can be improved by the organic light-emitting layer, and a low-power display device can be implemented.

[0029] Also, according to the embodiments of the present specification, since the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other, the occurrence of lateral leakage current in the organic light-emitting layer that may occur when the organic light-emitting layers are continuously connected to each other can be reduced.

[0030] Also, according to the embodiments of the present specification, by arranging the cathode electrode layer and the data wiring so as not to overlap each other in the vertical direction, the generation of a parasitic capacitor between the cathode electrode layer and the data wiring can be reduced, and thus the occurrence of an RC delay in the electrical transmission speed can be reduced.

[0031] Also, according to the embodiments of the present specification, after forming the organic light-emitting layer, cathode electrode layer, and passivation layer that embody the first hue, the organic light-emitting layer that embodies the second hue and the organic light-emitting layer that embodies the third hue are further formed in the same process. Therefore, the passivation layer can serve as a protective film that reduces the deterioration of the organic light-emitting layer that may occur in a continuous process, and the damage to the organic light-emitting layer can be reduced.

[0032] The above-described effects and the specific effects of the present invention will be described and described while explaining the embodiments for carrying out the following invention.

Brief Description of the Drawings

[0033]

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Mode for Carrying Out the Invention

[0034] The advantages, features, and methods for achieving them of the present specification will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below and can be embodied in various different forms. However, this embodiment is provided to complete the disclosure of the present specification and to fully inform those having ordinary knowledge in the technical field to which the present specification pertains of the scope of the invention, and the present specification is only defined by the scope of the claims.

[0035] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the matters shown in the drawings. The same reference numerals throughout the specification refer to the same components. Also, in explaining the present specification, when a specific explanation of a related known technique is determined to obscure the gist of the present specification, the detailed description thereof will be omitted. When terms such as "including", "having", "becoming", etc. mentioned in the present specification are used, other parts can be added unless "only" is used. When a component is shown in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0036] When interpreting a component, even if there is no separate explicit description, it is interpreted as including an error range.

[0037] In the case of an explanation of a positional relationship, for example, when explaining the positional relationship between both parts such as "on ~", "above ~", "below ~", "on the side of ~", etc., unless "immediately" or "directly" is used, one or more other parts can also be located between both parts.

[0038] In the case of an explanation regarding the relationship of time, for example, when explaining the chronological relationship such as "after ~", "subsequent to ~", "next to ~", "before ~", etc., unless "immediately" or "directly" is used, cases where they are not consecutive can also be included.

[0039] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Thus, the first component mentioned below may be the second component within the technical idea of this specification.

[0040] The features of the multiple embodiments of this specification can be combined or combined with each other partially or entirely, various interlocks and drives are technically possible, and each embodiment can be implemented independently of each other or can also be implemented together in an associated relationship.

[0041] Hereinafter, with reference to FIGS. 1 to 4, the display device according to the embodiment of this specification will be described in detail.

[0042] FIG. 1 is a schematic plan view of a display device according to an embodiment of this specification.

[0043] Although the display device 1 described below is described by taking an organic light emitting diodes display device as an example, it is not limited thereto.

[0044] The display device 1 can include a display area (AA) and a non-display area (NA) surrounding the periphery of the display area (AA).

[0045] In the display area (AA), a plurality of data wirings (DL) extending in the first direction and a plurality of gate wirings (GL) extending in a second direction intersecting the first direction may be arranged.

[0046] By the intersection of the data wiring (DL) and the gate wiring (GL), the partitioned regions can be defined as sub-pixels SP1, SP2, and SP3, respectively.

[0047] Each of the sub-pixels SP1, SP2, and SP3 can be implemented to emit light of the same color for each sub-pixel, such as white (W) light, or can be implemented to emit different colors for each sub-pixel, such as red (R), green (G), or blue (B) light.

[0048] For example, the sub-pixels SP1, SP2, and SP3 can be implemented as a combination of red (R), green (G), and blue (B), or as a combination of red (R), green (G), blue (B), and white (W) light.

[0049] One pixel (P) can be constituted by a combination of the plurality of sub-pixels SP1, SP2, and SP3 as described above.

[0050] Hereinafter, as an example, it will be described that one pixel (P) includes a first sub-pixel (SP1) that implements a first hue, a second sub-pixel (SP2) that implements the first hue, and a third sub-pixel (SP3) that implements a third hue.

[0051] In this case, the first hue may be red (R), the second hue may be green (G), and the third hue may be blue (B), but is not limited thereto.

[0052] The plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix arranged in a plurality of rows and columns.

[0053] The first direction in this specification is the column direction and is defined as the Y-axis direction, and the second direction is the row direction and can be defined as the X-axis direction.

[0054] In the non-display area (NA), a plurality of wirings, pads, etc. for supplying various signals, power supplies, etc. inside the pixel may be arranged.

[0055] A data driving circuit (D-IC; 10) may be arranged on one side of the non-display area (NA).

[0056] The data driving circuit 10 can apply a data signal to the data wiring (DL) and apply driving voltages such as a high potential voltage (VDD) and a low potential voltage (VSS) to the pixel (P).

[0057] A power supply wiring 20 may be arranged along the edge of the display area (AA) excluding one side of the non-display area (NA) where the data driving circuit 10 is arranged.

[0058] For example, a gate driving unit 30 that applies a gate signal to the gate wiring (GL) may be arranged in the non-display areas (NA) located on both sides of the display area (AA), and a power supply wiring 20 that can apply a voltage to the anode electrode or the cathode electrode in the pixel (P) may be arranged along the outer contour of the gate driving unit 30.

[0059] The power supply wiring 20 may be a low potential voltage wiring that can apply a low potential voltage (VSS) to the cathode electrode of the pixel (P), but is not limited thereto, and a high potential voltage wiring that can apply a high potential voltage (VDD) to the thin film transistor of the pixel (P) may be further arranged.

[0060] In the display area (AA), a plurality of power connection wirings 112 may be arranged to electrically connect the power supply wiring 20 and the plurality of sub-pixels SP1, SP2, SP3 so as to apply a low potential voltage to the plurality of sub-pixels SP1, SP2, SP3.

[0061] For example, the plurality of power connection wirings 112 may extend in the same manner in a first direction in which the plurality of data wirings (DL) extend.

[0062] The plurality of power connection wirings 112 and the plurality of data wirings (DL) may be alternately arranged one by one in a second direction.

[0063] One power connection wiring 112 can extend to pass through a plurality of sub-pixels arranged in the column direction and be electrically connected to a power wiring 20 disposed at the lower part of the display area (AA).

[0064] Therefore, a plurality of sub-pixels arranged in the same column direction may be electrically connected to the same one power connection wiring 112, and a low-potential voltage may be applied from the power wiring 20 through the power connection wiring 112.

[0065] FIG. 2 is a circuit diagram regarding one sub-pixel of a display device according to an embodiment of the present specification.

[0066] As described above, a switching thin-film transistor (Ts), a driving thin-film transistor (Td), a storage capacitor (Cst), and a light-emitting diode (De) may be formed in each of the sub-pixels SP1, SP2, SP3 defined by the gate wiring (GL) and the data wiring (DL) that cross each other.

[0067] The gate electrode of the switching thin-film transistor (Ts) may be connected to the gate wiring (GL), and the source electrode may be connected to the data wiring (DL).

[0068] The gate electrode of the driving thin-film transistor (Td) may be connected to the drain electrode of the switching thin-film transistor (Ts), and the source electrode may be connected to a high-potential voltage (VDD).

[0069] The anode electrode of the light-emitting diode (De) may be connected to the drain electrode of the driving thin-film transistor (Td), and the cathode electrode may be connected to a low-potential voltage (VSS).

[0070] One side and the other side of the storage capacitor (Cst) may be connected to the gate electrode and the drain electrode of the driving thin-film transistor (Td), respectively.

[0071] The display device 1 including the sub-pixels SP1, SP2, and SP3 having such a circuit diagram can display an image as follows.

[0072] According to the gate signal applied via the gate wiring (GL), the switching thin-film transistor (Ts) is turned on, and the data signal applied via the data wiring (DL) can be applied to the gate electrode of the driving thin-film transistor (Td) and one electrode of the storage capacitor (Cst) via the switching thin-film transistor (Ts).

[0073] The driving thin-film transistor (Td) is turned on according to the data signal, and an image can be displayed by controlling the current flowing through the light-emitting diode (De).

[0074] The light-emitting diode (De) can emit light by the current of the high-potential voltage (VDD) transmitted via the driving thin-film transistor (Td).

[0075] FIG. 3a and FIG. 3b are enlarged plan views of a plurality of sub-pixels of the display device according to the embodiment of the present specification shown in FIG. 1, and FIG. 4 is a cross-sectional view of a plurality of sub-pixels of the display device according to the embodiment of the present specification shown in FIG. 3a.

[0076] Specifically, FIG. 3a shows an enlargement of a plurality of sub-pixels corresponding to the region of reference numeral 3 in FIG. 1.

[0077] Hereinafter, although one sub-pixel will be described as a reference, unless otherwise specified, it can be similarly applied to other sub-pixels.

[0078] Referring to FIGS. 3a and 4, a thin-film transistor including an active layer 101 may be disposed on the substrate 100. In this case, the thin-film transistor may be a driving thin-film transistor (Td) or a switching thin-film transistor (Ts).

[0079] A buffer layer may be further disposed between the substrate 100 and the thin film transistor.

[0080] The thin film transistor may include an active layer 101, a gate electrode, and a pair of source-drain electrodes 111.

[0081] On the active layer 101 and the gate electrode, a first insulating layer 102 which is an interlayer insulating layer is disposed, and the source-drain electrode 111 can be electrically connected to the active layer 101 through a contact hole formed in the first insulating layer 102.

[0082] A second insulating layer 103 may be further disposed on the first insulating layer 102 and the source-drain electrode 111, and the source-drain electrode 111 may be disposed on the second insulating layer 103 through a contact hole formed in the second insulating layer 103.

[0083] On the second insulating layer 103, a power supply connection wiring 112 and a data wiring (DL) disposed in the same layer as the source-drain electrode 111 may be disposed.

[0084] The power supply connection wiring 112 and the data wiring (DL) may extend side by side in the first direction and be alternately arranged (see FIG. 1).

[0085] Thereby, the plurality of data wirings (DL) and the plurality of power supply connection wirings 112 may be arranged so as not to overlap each other in the vertical direction, and the generation of parasitic capacitors formed between the data wiring (DL) and the power supply connection wiring 112 can be reduced.

[0086] An overcoat layer 120 is formed on the source-drain electrode 111, and an anode electrode layer 130 may be formed on the overcoat layer 120.

[0087] The overcoat layer 120 can be formed from an organic material.

[0088] The anode electrode layer 130 can be electrically connected to the source-drain electrode 111 through the contact hole 120h of the overcoat layer 120.

[0089] On the power supply connection wiring 112, a first structure layer 121 made of the same material as the overcoat layer 120 may be disposed.

[0090] The first structure layer 121 can be formed by patterning the overcoat layer 120 in an island shape.

[0091] The first structure layer 121 may be disposed so as to overlap the power supply connection wiring 112 in the vertical direction.

[0092] The first structure layer 121 can be formed in a positive taper shape in which the width decreases from the lower part to the upper part.

[0093] The left and right widths (in the x-axis direction in FIG. 4) of the lower surface of the first structure layer 121 can be formed smaller than the left and right widths (in the x-axis direction in FIG. 4) of the power supply connection wiring 112.

[0094] As a result, a partial region and the side surface of the upper surface of the power supply connection wiring 112 that do not overlap with the first structure layer 121 can be exposed to the outside without being covered by the first structure layer 121.

[0095] In this way, a partial region of the upper surface of the power supply connection wiring 112 exposed to the outside may be an undercut portion (UC).

[0096] For example, the undercut portion (UC) can be formed along the peripheral portion of the lower surface of the first structure layer 121, and the power supply connection wiring 112 corresponding to the undercut portion (UC) can be exposed to the outside without being covered by the first structure layer 121.

[0097] On the first structure layer 121, a second structure layer 131 made of the same material as the anode electrode layer 130 may be disposed.

[0098] The second structure layer 131 can be formed by patterning the anode electrode layer 130 in an island shape.

[0099] The second structure layer 131 may be arranged so as to overlap the first structure layer 121 and the power supply connection wiring 112 in the vertical direction.

[0100] The second structure layer 131 can be electrically connected to the power supply connection wiring 112 through the contact hole 121h of the first structure layer 121.

[0101] The second structure layer 131 can be formed such that its left - right width (in the x - axis direction in FIG. 4) is larger than the left - right widths (in the x - axis direction in FIG. 4) of the upper and lower surfaces of the first structure layer 121 disposed below.

[0102] As a result, the second structure layer 131 can include a protruding portion 1311 that protrudes outside the upper and lower surfaces of the first structure layer 121.

[0103] Due to the protruding portion 1311 of the second structure layer 131 formed in this way, an undercut portion (UC) may be formed along the outer periphery of the lower surface of the first structure layer 121 on the power supply connection wiring 112.

[0104] Based on the plan view, at least a part of the undercut portion (UC) may be located inside the second structure layer 131.

[0105] Therefore, although the outermost contour boundary portion of the undercut portion (UC) may be located outside the second structure layer 131, it is not limited thereto. The outermost contour boundary portion of the undercut portion (UC) may be located inside the second structure layer 131 or may coincide with each other.

[0106] A bank layer 140 may be formed on the anode electrode layer 130, the second structure layer 131, and the data wiring (DL).

[0107] The bank layer 140 can function as a pixel definition layer (PDL) that divides a plurality of sub-pixels SP1, SP2, and SP3.

[0108] Therefore, between each of the sub-pixels SP1, SP2, and SP3, the bank layer 140, which is a pixel definition layer, can be disposed to define a boundary between the sub-pixels SP1, SP2, and SP3 having different hues and prevent color mixing.

[0109] The bank layer 140 disposed on the power connection wiring 112 can include a first opening 1401 that is opened to expose an undercut portion (UC).

[0110] The meaning that the first opening 1401 of the bank layer 140 in this specification exposes the undercut portion (UC) means that the bank layer 140 has a pattern that is opened without covering the undercut portion (UC).

[0111] Specifically, the outermost boundary portion of the first opening 1401 may be formed outside the outermost boundary portion of the undercut portion (UC), and the first opening 1401 may be formed to include the undercut portion (UC).

[0112] Therefore, not only the undercut portion (UC), which is a partial region above the power connection wiring 112, but also a partial region of the second insulating layer 103 can be exposed to the outside through the first opening 1401.

[0113] A third structure layer 141 made of the same material as the bank layer 140 may be disposed on the second structure layer 131.

[0114] The third structure layer 141 can be formed by patterning the bank layer 140 in an island shape.

[0115] The third structure layer 141 may be disposed so as to overlap the second structure layer 131, the first structure layer 121, and the power connection wiring 112 in the vertical direction.

[0116] The third structure layer 141 can be formed in a positive taper shape with a width decreasing from the bottom to the top.

[0117] The left - right width (in the x - axis direction in FIG. 4) of the third structure layer 141 can be formed smaller than the left - right width (in the x - axis direction in FIG. 4) of the upper surface of the second structure layer 131 disposed at the bottom.

[0118] Therefore, the upper surface of the protruding portion 1311 of the second structure layer 131 protruding outside the first structure layer 121 can be exposed to the outside without being covered by the third structure layer 141.

[0119] In this way, the first structure layer 121, the second structure layer 131, and the third structure layer 141 sequentially stacked can form a structure (ST).

[0120] Thereby, the structure (ST) may be disposed to overlap with the power connection wiring 112 so as to provide an undercut portion (UC) that exposes a partial region above the power connection wiring 112.

[0121] Also, the bank layer 140 may include a second opening 1402 opened to expose a partial region of the anode electrode layer 130.

[0122] The second opening 1402 formed in the first sub - pixel (SP1) defines the first light - emitting portion (OLE1), the second opening 1402 formed in the second sub - pixel (SP2) defines the second light - emitting portion (OLE2), and the second opening 1402 formed in the third sub - pixel (SP3) can define the third light - emitting portion (OLE3).

[0123] An organic light - emitting layer, a cathode electrode layer, and a passivation layer can be sequentially stacked on the bank layer 140.

[0124] Specifically, in the first sub-pixel (SP1), a first organic light-emitting layer 151 that embodies a first hue, a first cathode electrode layer 161, and a first passivation layer 171 are disposed. In the second sub-pixel (SP2), a second organic light-emitting layer 152 that embodies a second hue, a second cathode electrode layer 162, and a second passivation layer 172 are disposed. In the third sub-pixel (SP3), a third organic light-emitting layer 153 that embodies a third hue, a third cathode electrode layer 163, and a third passivation layer 173 may be disposed.

[0125] In this case, the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels can be arranged so as to be insulated from each other.

[0126] As used herein, "insulated" means physically separated from each other and not electrically connected to each other.

[0127] However, even if they are insulated from each other, they can be electrically connected indirectly by other intermediate media.

[0128] For example, the first organic light-emitting layer 151 and the second organic light-emitting layer 152 adjacent to each other may be insulated from each other, the second organic light-emitting layer 152 and the third organic light-emitting layer 153 adjacent to each other may be insulated from each other, and the third organic light-emitting layer 153 and the first organic light-emitting layer 151 adjacent to each other may be insulated from each other.

[0129] Also, the first cathode electrode layer 161 and the second cathode electrode layer 162 adjacent to each other may be insulated from each other, the second cathode electrode layer 162 and the third cathode electrode layer 163 adjacent to each other may be insulated from each other, and the third cathode electrode layer 163 and the first cathode electrode layer 161 adjacent to each other may be insulated from each other.

[0130] Further, the first passivation layer 171 and the second passivation layer 172 adjacent to each other are insulated from each other, the second passivation layer 172 and the third passivation layer 173 adjacent to each other are insulated from each other, and the third passivation layer 173 and the first passivation layer 171 adjacent to each other may be insulated from each other.

[0131] The outermost boundary portion 1511 of the first organic light-emitting layer 151, the outermost boundary portion 1611 of the first cathode electrode layer 161, and the outermost boundary portion 1711 of the first passivation layer 171 may be disposed within a first sub-pixel (SP1) formed between adjacent data wirings (DL).

[0132] Therefore, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may not overlap the data wiring (DL) in the vertical direction.

[0133] Also, the outermost boundary portion 1521 of the second organic light-emitting layer 152, the outermost boundary portion 1621 of the second cathode electrode layer 162, and the outermost boundary portion 1721 of the second passivation layer 172 may be disposed within a second sub-pixel (SP2) formed between adjacent data wirings (DL).

[0134] Therefore, the second organic light-emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 may not overlap the data wiring (DL) in the vertical direction.

[0135] Also, the outermost boundary portion 1531 of the third organic light-emitting layer 153, the outermost boundary portion 1631 of the third cathode electrode layer 163, and the outermost boundary portion 1731 of the third passivation layer 173 may be disposed within a third sub-pixel (SP3) formed between adjacent data wirings (DL).

[0136] Therefore, the third organic light-emitting layer 153, the third cathode electrode layer 163, and the third passivation layer 173 may not overlap the data wiring (DL) in the vertical direction.

[0137] If adjacent cathode electrode layers are formed from a cylindrical electrode and continuously arranged so as to cover the entire display area without being disconnected from each other, the cathode electrode layer may be arranged so as to overlap with the data wiring, thereby generating an unintentional parasitic capacitor between the cathode electrode layer and the data wiring.

[0138] Thus, when a parasitic capacitor is generated, the RC delay may increase.

[0139] The RC delay is a value obtained by multiplying the resistance (R) and the capacitance (C), and means a delay in the electrical transmission speed.

[0140] Therefore, when the RC delay increases, the delay in the electrical transmission speed increases, which makes it difficult to drive the display device at high speed.

[0141] However, according to the embodiments of the present specification, by arranging the cathode electrode layer and the data wiring so as not to overlap each other in the vertical direction, the generation of a parasitic capacitor that can be formed between the cathode electrode layer and the data wiring can be reduced.

[0142] Accordingly, according to the embodiments of the present specification, by reducing the occurrence of the RC delay, the difficulty of driving the display device at high speed can be greatly reduced.

[0143] In a region corresponding to the second opening 1402 of the first sub-pixel (SP1) of the bank layer 140, a first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 are sequentially stacked, and a region where the anode electrode layer 130, the first organic light-emitting layer 151, and the first cathode electrode layer 161 overlap may be a first light-emitting portion (OLE1) that emits light.

[0144] In addition, a second organic light-emitting layer 152, a second cathode electrode layer 162, and a second passivation layer 172 are sequentially stacked in a region corresponding to a second opening 1402 of a second sub-pixel (SP2) of the bank layer 140, and a region where the anode electrode layer 130, the second organic light-emitting layer 152, and the second cathode electrode layer 162 overlap may be a second light-emitting portion (OLE2) that emits light.

[0145] In addition, a third organic light-emitting layer 153, a third cathode electrode layer 163, and a third passivation layer 173 are sequentially stacked in a region corresponding to a second opening 1402 of a third sub-pixel (SP3) of the bank layer 140, and a region where the anode electrode layer 130, the third organic light-emitting layer 153, and the third cathode electrode layer 163 overlap may be a third light-emitting portion (OLE3) that emits light.

[0146] The first organic light-emitting layer 151, the second organic light-emitting layer 152, and the third organic light-emitting layer 153 may each include a light-emitting layer (Emission layer: EML) that emits red, green, and blue light, respectively. The light-emitting layer may be made of a phosphorescent material or a fluorescent material, and specific materials are not particularly limited.

[0147] For example, a hole injection layer (Hole injection layer: HIL) and / or a hole transporting layer (Hole transporting layer: HTL) may be further disposed between the anode electrode layer 130 and the organic light-emitting layer, and an electron transporting layer (Electron transporting layer: ETL) and / or an electron injection layer (Electron injection layer: HIL) may be disposed between the light-emitting layer (Emission layer: EML) and the cathode electrode layer.

[0148] If the adjacent organic light-emitting layers are continuously arranged so as to cover the entire display area without being disconnected from each other, there may be a problem that light generated in the light-emitting portion and not escaping to the outside continues to be reflected at the interface and then propagates to the side and disappears.

[0149] However, according to the embodiments of the present specification, since the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other, the light of the organic light-emitting layer can escape to the outside while the path changes at the insulated end portion.

[0150] Therefore, according to the embodiments of the present specification, the light extraction efficiency in the organic light-emitting layer can be further improved by the occurrence of the out-coupling phenomenon.

[0151] In addition, according to the embodiments of the present specification, since the organic light-emitting layers, cathode electrode layers, and passivation layers of adjacent sub-pixels are insulated from each other, the occurrence of lateral leakage current in the organic light-emitting layer that may occur when the organic light-emitting layers are continuously connected to each other can also be reduced.

[0152] In order to drive each of the sub-pixels SP1, SP2, and SP3, a low potential voltage (VSS) must be applied to the cathode electrode layer.

[0153] However, according to the embodiments of the present specification, since the cathode electrode layers included in the adjacent sub-pixels SP1, SP2, and SP3 are insulated from each other, a low potential voltage (VSS) can be applied to the cathode electrode layers included in each of the sub-pixels SP1, SP2, and SP3 via the power connection wiring 112.

[0154] In the case of the first sub-pixel (SP1), the first cathode electrode layer 161 and the power connection wiring 112 can be electrically connected by contacting each other at the undercut portion (UC) of the power connection wiring 112 disposed below the structure (ST).

[0155] Specifically, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can contact the undercut portion (UC).

[0156] For example, the first organic light-emitting layer 151 can be formed in the first opening 1401 so as to contact the side surface of the power connection wiring 112.

[0157] In this case, the first organic light-emitting layer 151 may also contact a partial region of the undercut portion (UC).

[0158] The first cathode electrode layer 161 formed on the first organic light-emitting layer 151 can be formed in the first opening 1401 so as to contact a partial region of the undercut portion (UC).

[0159] The first cathode electrode layer 161 can use a material that is relatively superior in step coverage to the first organic light-emitting layer 151. As a result, the end portion of the first cathode electrode layer 161 adjacent to the undercut portion (UC) may be located closer to the inside of the undercut portion (UC), that is, closer to the structure (ST), than the end portion of the first organic light-emitting layer 151.

[0160] Therefore, overall, by being formed so as to cover the first organic light-emitting layer 151, the outermost boundary portion 1611 of the first cathode electrode layer 161 can be formed outside the outermost boundary portion 1511 of the first organic light-emitting layer 151.

[0161] The first cathode electrode layer 161 formed in this way can be electrically connected to the power connection wiring 112 by contacting a partial region of the undercut portion (UC).

[0162] As a result, each of the first cathode electrode layers 161 that are insulated from each other can apply a low potential voltage by being electrically connected to the power supply wiring 20 by one power connection wiring 112 passing through a plurality of first sub-pixels (SP1).

[0163] The first passivation layer 171 formed on the first cathode electrode layer 161 can be formed in the first opening 1401 so as to contact a partial region of the undercut portion (UC).

[0164] However, not limited thereto, the first passivation layer 171 may further contact the side surface of the first structure layer 121 or may contact the side surface of the first structure layer 121 of the structure (ST) without directly contacting the undercut portion (UC).

[0165] The first passivation layer 171 may be made of a material with relatively better step coverage than the first cathode electrode layer 161. As a result, the end portion of the first passivation layer 171 adjacent to the undercut portion (UC) may be located closer to the inside of the undercut portion (UC), that is, closer to the structure (ST), than the end portion of the first cathode electrode layer 161. In this case, having better step coverage means having a relatively uniform thickness over the entire step.

[0166] Therefore, overall, the first passivation layer 171 is formed to cover the first cathode electrode layer 161, so that the outermost boundary portion 1711 of the first passivation layer 171 can be formed outside the outermost boundary portion 1611 of the first cathode electrode layer 161.

[0167] Thus, according to the embodiments of the present specification, in each sub-pixel, the cathode electrode layer and the power supply connection wiring in each undercut portion are electrically connected through a structure that provides the undercut portion. Therefore, power can be stably supplied to each of the plurality of sub-pixels through the power supply connection wiring electrically connected to the power supply wiring.

[0168] Also, according to the embodiments of the present specification, undercut portions are formed along at least both side surfaces or the periphery of the structure, and the cathode electrode layer and the power supply connection wiring in the undercut portion are brought into contact. Therefore, even when the structure of one side undercut portion is not fully realized due to external factors such as the occurrence of process errors, the structure of the other side undercut portion can be used.

[0169] Therefore, according to the embodiments of the present specification, power can be stably supplied to a plurality of sub-pixels through a power connection wiring electrically connected to a power wiring.

[0170] On the structure (ST) of the first sub-pixel (SP1), a first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 can be sequentially stacked (see FIG. 4).

[0171] Specifically, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can be formed to cover the third structure layer 141.

[0172] The first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 may be formed to cover the protrusion 1311 of the second structure layer 131 and extend to cover the side surface of the second structure layer 131.

[0173] In this case, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 can be formed in an island shape by being interrupted by the first structure layer 121 disposed below the second structure layer 131.

[0174] The first cathode electrode layer 161 disposed on the third structure layer 141 can be electrically connected to the second structure layer 131 formed of the same material as the anode electrode layer 130.

[0175] Since the second structure layer 131 is electrically connected to the lower power connection wiring 112 through the contact hole 121h of the first structure layer 121, the first cathode electrode layer 161, the second structure layer 131, and the power connection wiring 112 disposed on the third structure layer 141 can be electrically connected.

[0176] Since the first cathode electrode layer 161 and the second structure layer 131 are formed of a conductive material such as metal, when the first cathode electrode layer 161, the second structure layer 131, and the power connection wiring 112 are electrically connected, there is an advantageous effect of reducing the overall resistance of the power connection wiring 112.

[0177] As described above, the connection structure in the undercut portion (UC) of the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 of the first sub-pixel (SP1) can be similarly applied to the second sub-pixel (SP2) and the third sub-pixel (SP3). Duplicate content will be omitted.

[0178] FIG. 3b is an enlarged plan view of a plurality of sub-pixels of a display device according to another embodiment of the present specification shown in FIG. 1.

[0179] Referring to FIG. 3b, the structure (ST) of the first sub-pixel (SP1) is continuously formed along the periphery of the first light-emitting portion (OLE1), the structure (ST) of the second sub-pixel (SP2) is continuously formed along the periphery of the second light-emitting portion (OLE2), and the structure (ST) of the third sub-pixel (SP3) may be continuously formed along the periphery of the third light-emitting portion (OLE3).

[0180] In this way, when the structure (ST) is continuously formed along the periphery of each light-emitting portion, the undercut portion (UC) provided by the structure (ST) may also be continuously formed along the periphery of the light-emitting portion.

[0181] In this way, when the structure (ST) and the undercut portion (UC) provided by the structure (ST) are continuously formed along the periphery of the light-emitting portion, even when the structure of one side structure or the structure of the undercut portion is not sufficiently realized due to external factors such as process errors, the cathode electrode layer and the power connection wiring can be stably connected using the structure of the other side structure and the structure of the undercut portion.

[0182] Although not shown in the drawings, the structure (ST) can be discontinuously formed along the periphery of each light-emitting portion, and the arrangement form of the structure (ST) is not particularly limited.

[0183] Figs. 5a to 5n are process plan views related to a plurality of sub-pixels of a display device according to an embodiment of the present specification, and Figs. 6a to 6n are process cross-sectional views related to the plurality of sub-pixels of the display device according to the embodiment of the present specification shown in Figs. 5a to 5n.

[0184] For the sake of convenience of explanation, in the case of the process plan views of Figs. 5a to 5n, only some of the configurations shown in the process cross-sectional views of Figs. 6a to 6n will be shown.

[0185] The pattern formation method for each layer described below can use a photolithography process including deposition, photoresist coating (PR Coating), exposure, development, etching, and photoresist stripping (PR Strip), which are techniques implemented by ordinary technicians in the art. Details thereof will be omitted.

[0186] For example, when depositing a metal material, sputtering can be used separately, and when depositing a semiconductor or an insulating film, a method such as plasma enhanced vapor deposition (PECVD) can be used separately. In the case of etching, dry etching and wet etching can be selected and used according to the material, and the techniques implemented by ordinary technicians in the art can be applied.

[0187] Referring to Figs. 5a and 6a, a thin-film transistor including an active layer 101 can be formed on a substrate 100, and a first insulating layer 102 and a second insulating layer 103 can be sequentially formed.

[0188] A plurality of source-drain electrodes 111 connected to the active layer 101 can be formed on the second insulating layer 103.

[0189] Further, on the second insulating layer 103, a plurality of power connection wirings 112 and a plurality of data wirings (DL) can be formed.

[0190] The source-drain electrodes 111, the power connection wirings 112, and the data wirings (DL) can be formed to have the same material in the same layer by the same patterning process.

[0191] Although the plurality of power connection wirings 112 and the plurality of data wirings (DL) are formed to extend in the first direction, they can be alternately arranged in the second direction.

[0192] An overcoat film 120a may be formed on the plurality of source-drain electrodes 111, the plurality of power connection wirings 112, and the plurality of data wirings (DL).

[0193] Referring to FIGS. 5b and 6b, contact holes 120h connected to the respective source-drain electrodes 111 are formed in the overcoat film 120a, and a plurality of anode electrode layers 130 electrically connected to the source-drain electrodes 111 through the contact holes 120h may be formed on the overcoat film 120a.

[0194] Further, contact holes 121h connected to the respective power connection wirings 112 are formed in the overcoat film 120a, and a plurality of second structure layers 131 electrically connected to the power connection wirings 112 through the contact holes 121h may be formed on the overcoat film 120a.

[0195] The anode electrode layer 130 and the second structure layer 131 can be formed to have the same material in the same layer by the same patterning process.

[0196] The second structure layer 131 may be formed with a pair of protruding portions 1311 extending so as to protrude outward.

[0197] For example, although one end of the protrusion 1311 of the second structure layer 131 may be located inside one end of the power connection wiring 112, it is not limited thereto.

[0198] When referring to a plan view, the protrusion 1311 of the second structure layer 131 can be continuously formed along the perimeter of the second structure layer 131.

[0199] Referring to FIGS. 5c and 6c, a photoresist layer 132 having a predetermined pattern can be formed on the anode electrode layer 130 and the second structure layer 131.

[0200] For example, the photoresist layer 132 can be formed to have a predetermined pattern by depositing a photoresist material and developing it.

[0201] The photoresist layer 132 formed on the anode electrode layer 130 can be formed with an area wider than that of the anode electrode layer 130 so as to cover the anode electrode layer 130.

[0202] The photoresist layer 132 formed on the second structure layer 131 can be formed with an area narrower than that of the second structure layer 131 so that a frame region corresponding to a partial region of the protrusion 1311 of the second structure layer 131 is exposed.

[0203] Referring to FIGS. 5d and 6d, the overcoat film 120a can be etched using the photoresist layer 132 as a photomask to form the overcoat layer 120 and the first structure layer 121.

[0204] Thereby, the overcoat layer 120 and the first structure layer 121 can be formed to have the same material in the same layer by the same patterning process.

[0205] For example, the overcoat film 120a can be patterned by a dry etching method.

[0206] An overcoat layer 120 may be formed under the anode electrode layer 130.

[0207] Under each of the second structure layers 131, a first structure layer 121 with a patterned overcoat film 120a may be formed.

[0208] Specifically, the second structure layer 131 and the photoresist layer 132 formed on the second structure layer 131 can serve as a photomask for patterning the overcoat film 120a to form the first structure layer 121.

[0209] In this case, the first structure layer 121 can be formed in a positive taper shape where the width decreases from the bottom to the top.

[0210] The outermost boundary portion of the lower surface of the first structure layer 121 can be formed to be located inside the outermost boundary portion of the protruding portion 1311 of the second structure layer 131.

[0211] Therefore, the first structure layer 121 is formed to have a left - right width (in the x - axis direction in FIG. 4) narrower than that of the power connection wiring 112, and the frame region of the power connection wiring 112 can be formed as an undercut portion (UC) that is not covered by the first structure layer 121 and is exposed to the outside.

[0212] Based on the plan view, although the undercut portion (UC) can be formed so as not to be exposed by the protruding portion 1311 of the second structure layer 131, it is not limited thereto, and a partial upper region located in the frame portion of the undercut portion (UC) based on the plan view can be exposed to the outside.

[0213] Therefore, a plurality of first structure layers 121 that respectively provide undercut portions (UC) under the plurality of second structure layers 131 may be formed.

[0214] In this way, the side surface of the power connection wiring 112 and a partial region of the upper part of the power connection wiring 112 corresponding to the undercut portion (UC) can be exposed to the outside by the overcoat layer 120 and the first structure layer 121 formed by patterning the overcoat film 120a.

[0215] Further, the overcoat film 120a in the region between the power connection wiring 112 and the overcoat layer 120 can be removed, so that the second insulating layer 103 can be exposed to the outside.

[0216] Also, the overcoat film 120a on the data wiring (DL) can be removed, so that the data wiring (DL) can be exposed to the outside. By removing the overcoat film 120a between the data wiring (DL) and the power connection wiring 112, the second insulating layer 103 can also be exposed to the outside.

[0217] Referring to FIGS. 5e and 6e, the photoresist layer 132 disposed on the anode electrode layer 130 and the second structure layer 131 can be removed.

[0218] For example, the photoresist layer 132 can be removed by peeling it off through a strip process.

[0219] Referring to FIGS. 5f and 6f, a bank layer 140 can be formed, which includes a plurality of first openings 1401 that expose the outer peripheral sides of the plurality of undercut portions (UC) and a plurality of second openings 1402 that expose a part of the plurality of anode electrode layers 130.

[0220] Except for the regions corresponding to the first openings 1401 and the second openings 1402, the bank layer 140 can be formed so as to cover the entire surface of the display area (AA).

[0221] A third structure layer 141, which is formed by patterning the bank layer 140, may be formed on the second structure layer 131.

[0222] The third structure layer 141 can be formed by the same patterning process as the first opening 1401 and the second opening 1402.

[0223] The third structure layer 141 can be formed in a positive taper shape where the width decreases as going from the lower part to the upper part.

[0224] By forming the lower surface of the third structure layer 141 to have a narrower width than the upper surface of the second structure layer 131, at least a part of the protruding portion 1311 of the second structure layer 131 can be exposed to the outside without being covered by the third structure layer 141.

[0225] In this way, by sequentially laminating the first structure layer 121, the second structure layer 131, and the third structure layer 141, a structure (ST) can be formed.

[0226] In this case, the second structure layer 131 of the structure (ST) can provide a roof structure, and by means of the roof structure of the second structure layer 131, the cathode electrode layer and the power connection wiring 112 in the undercut portion (UC) located below can be electrically connected.

[0227] As described above, both the first structure layer 121 and the third structure layer 141 of the structure (ST) can be formed in a positive taper shape.

[0228] If the third structure layer 141 is in an inverted taper shape where the width increases as going from the lower part to the upper part, during the deposition of the organic light-emitting layer described later, the organic light-emitting layer can penetrate deeply inside the undercut portion (UC) of the structure (ST).

[0229] As a result, it may become difficult for the cathode electrode layer formed in a subsequent process to contact the undercut portion (UC), which may prevent a stable connection between the cathode electrode layer and the power connection wiring.

[0230] Accordingly, when the third structure layer 141 is reverse-tapered, in order to stably connect the cathode electrode layer and the power connection wiring, the length of the eaves must be increased by increasing the width of the upper surface of the third structure layer 141.

[0231] However, when the length of the eaves increases in this way, the total area occupied by the structure (ST) increases, which may be disadvantageous in terms of the aperture ratio of the display device.

[0232] Therefore, as in the embodiment of the present specification, both the first structure layer 121 and the third structure layer 141 are formed in a positive-tapered shape, and the second structure layer 131 located in the middle provides an eaves structure, so that the length of the eaves can be increased without increasing the size of the structure (ST), and a stable connection between the cathode electrode layer and the power connection wiring can be provided.

[0233] The structure (ST) formed in this way may be located inside the first opening 1401 of the bank layer 140.

[0234] That is, the region of the bank layer 140 exposed by the first opening 1401 can be formed to surround the periphery of the structure (ST).

[0235] Also, the first opening 1401 can be opened so that a part of the power connection wiring 112 including the undercut portion (UC) and the second insulating layer 103 are exposed.

[0236] In this way, the plurality of structures (ST) and the plurality of first openings 1401 formed in each sub-pixel may be located on the power connection wiring 112 extending in one direction and arranged to overlap the power connection wiring 112 with reference to the plan view.

[0237] The pixel definition layer (PDL) formed in each sub-pixel is defined by the second opening 1402 of the bank layer 140.

[0238] Referring to FIGS. 5g and 6g, the first protective film 142a can be formed to cover the entire surface of the substrate 100.

[0239] The first protective film 142a can contain a fluorine-based substance.

[0240] For example, the first protective film 142a can be composed of a fluoropolymer substance in which carbon-carbon bonds are continuously formed in a chain structure (carbon-carbon backbone) and which contains a large amount of fluorine (F) in functional groups.

[0241] In Chemical Formula 1 below, a chemical structural formula of a fluoropolymer substance containing a large amount of fluorine (F) in functional groups is shown according to an example of this specification.

Chemical Formula

[0242] As shown in Chemical Formula 1, the fluoropolymer used as the material of the protective film contains a large amount of fluorine (F) in functional groups.

[0243] A fluoropolymer containing a large amount of fluorine (F) in functional groups can have orthogonality to organic substances.

[0244] Orthogonality can be understood as a property in which two certain things exist independently without relation to each other.

[0245] As a result, the first protective film 142a can have both hydrophobicity with low affinity for water and oleophobicity with low affinity for oil.

[0246] Due to such orthogonality, the first protective film 142a can block the path through which moisture permeates due to its property of separating or repelling moisture.

[0247] In addition, since it is less affected by the developer containing an organic solvent used in the process of recommending process steps, damage to organic substances by the organic solvent can be reduced.

[0248] Referring to FIGS. 5h and 6h, the first photoresist film 143 can be formed on the first protective film 142a.

[0249] For example, the first photoresist film 143 can be formed to have a predetermined pattern by forming a photoresist substance into a film and developing it.

[0250] The first photoresist film 143 can be formed in a pattern that opens in the region corresponding to the first sub-pixel (SP1), but does not open in the regions corresponding to the second sub-pixel (SP2) and the third sub-pixel (SP3), and covers the second sub-pixel (SP2) and the third sub-pixel (SP3).

[0251] Specifically, the first photoresist film 143 can be formed in a pattern in which the first protective film 142a corresponding to the first opening 1401 and the second opening 1402 of the first sub-pixel (SP1) can be exposed.

[0252] Referring to FIGS. 5i and 6i, by developing the first protective film 142a disposed below using the first photoresist film 143 as a photomask, the first protective layer 142 having a predetermined pattern can be formed.

[0253] The first protective layer 142 formed in this way can expose the first opening 1401 and the second opening 1402 of the bank layer 140 to the outside.

[0254] In this case, the first protective layer 142 is located further inside than the first photoresist film 143 disposed on the upper part, so that the first photoresist film 143 can provide a shielding structure on the first protective layer 142.

[0255] Referring to FIGS. 5j and 6j, a first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 that embody a first hue can be formed by sequentially laminating them.

[0256] For example, it can be formed by sequentially depositing a first organic light-emitting layer 151, a first cathode electrode layer 161, and a first passivation layer 171 that embody a first hue on the entire surface of the substrate 100.

[0257] As a result, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 are sequentially laminated on the first opening 1401 and the second opening 1402 of the bank layer 140, and the connection of the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 in the structure (ST) having a shielding structure can be made discontinuously.

[0258] In addition, the connection of the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 in the first protective layer 142 can also be made discontinuously through the first photoresist film 143 having another shielding structure.

[0259] Based on the structure (ST), the first passivation layer 171, the first cathode electrode layer 161, and the first organic light-emitting layer 151 can be formed in this order so as to extend close to the structure (ST).

[0260] Specifically, for the first cathode electrode layer 161, a material with relatively better step coverage than the first organic light-emitting layer 151 can be used. As a result, the end portion of the first cathode electrode layer 161 adjacent to the undercut portion (UC) may be located closer to the structure (ST), that is, further inside the undercut portion (UC) than the end portion of the first organic light-emitting layer 151.

[0261] Therefore, overall, the first cathode electrode layer 161 is formed to cover the first organic light-emitting layer 151, so that the outermost boundary portion 1611 of the first cathode electrode layer 161 can be formed outside the outermost boundary portion 1511 of the first organic light-emitting layer 151.

[0262] The first cathode electrode layer 161 formed in this way can be electrically connected to the power supply connection wiring 112 by contacting a partial region of the undercut portion (UC).

[0263] As a result, each of the first cathode electrode layers 161 that are insulated from each other can be electrically connected to the power supply wiring 20 by one power supply connection wiring 112 passing through a plurality of first sub-pixels (SP1), and a low-potential voltage can be applied.

[0264] The first passivation layer 171 formed on the first cathode electrode layer 161 can be formed in the first opening 1401 so as to contact a partial region of the undercut portion (UC).

[0265] However, it is not limited thereto, and the first passivation layer 171 may further contact the side surface of the first structure layer 121 or may contact the side surface of the first structure layer 121 of the structure (ST) without directly contacting the undercut portion (UC).

[0266] The first passivation layer 171 can use a material with relatively better step coverage than the first cathode electrode layer 161. As a result, the end portion of the first passivation layer 171 adjacent to the undercut portion (UC) may be located closer to the structure (ST), that is, inside the undercut portion (UC) rather than the end portion of the first cathode electrode layer 161.

[0267] Therefore, overall, by forming the first passivation layer 171 so as to cover the first cathode electrode layer 161, the outermost boundary portion 1711 of the first passivation layer 171 can be formed outside the outermost boundary portion 1611 of the first cathode electrode layer 161.

[0268] On the other hand, by sequentially laminating the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 on the second opening 1402, the region where the first organic light-emitting layer 151, the first cathode electrode layer 161, and the anode electrode layer 130 overlap can be embodied in the first light-emitting portion (OLE1).

[0269] Referring to FIGS. 5k and 6k, the first protective layer 142 and the first photoresist film 143 can be removed.

[0270] Specifically, by the process of stripping the first protective layer 142, the first photoresist film 143, the first organic light-emitting layer 151, the first cathode electrode layer 161, and the first passivation layer 171 laminated on the first protective layer 142 can be removed together.

[0271] Referring to FIGS. 5l, 5m and FIGS. 6l, 6m, the processes in the first sub-pixel (SP1) described above with reference to FIGS. 5g to 5k and FIGS. 6g to 6k can be similarly repeated in the second sub-pixel (SP2) and the third sub-pixel (SP3).

[0272] Specifically, a second protective layer and a second photoresist film are formed so as to expose the first opening 1401 and the second opening 1402 corresponding to the second sub-pixel (SP2), and after sequentially forming the second organic light-emitting layer 152, the second cathode electrode layer 162, and the second passivation layer 172 that embody the second color phase, the second protective layer and the second photoresist film can be removed.

[0273] As a result, the second light-emitting part (OLE2) of the second sub-pixel (SP2) is formed, and the power connection wiring 112 passing through the second sub-pixel (SP2) and the second cathode electrode layer 162 in the undercut part (UC) of the structure (ST) of each second sub-pixel (SP2) can be electrically connected.

[0274] In this way, after the process for the second sub-pixel (SP2) is performed, a third protective layer and a third photoresist film are formed so as to expose the first opening 1401 and the second opening 1402 corresponding to the third sub-pixel (SP3). After sequentially forming the third organic light-emitting layer 153 having the third color phase, the third cathode electrode layer 163, and the third passivation layer 173, the third protective layer and the third photoresist film can be removed.

[0275] As a result, the third light-emitting part (OLE3) of the third sub-pixel (SP3) is formed, and the power connection wiring 112 passing through the third sub-pixel (SP3) and the third cathode electrode layer 163 in the undercut part (UC) of the structure (ST) of each third sub-pixel (SP3) can be electrically connected.

[0276] In this way, according to the embodiment of the present specification, after forming the organic light-emitting layer, the cathode electrode layer, and the passivation layer having the first color phase, the organic light-emitting layer having the second color phase and the organic light-emitting layer having the third color phase can be further formed in the same process.

[0277] Therefore, since the passivation layer disposed on the organic light-emitting layer can serve as a protective film that reduces the deterioration of the organic light-emitting layer that may occur in the continuous process for forming the organic light-emitting layer corresponding to each sub-pixel, the damage to the organic light-emitting layer can be reduced.

[0278] Further, according to the embodiment of the present specification, since the cathode electrode layer and the power connection wiring 112 in the undercut part (UC) of the structure (ST) are not contacted on the bank layer 140 but are contacted at the opening where the bank layer 140 is removed, the total number of mask processes can be reduced.

[0279] Referring to FIGS. 5n and 6n, a capping layer 180 and a fourth passivation layer 190 may be further formed so as to cover the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3).

[0280] The display device and the method of manufacturing the display device according to the embodiments of the present specification described above can be explained as follows.

[0281] The display device according to the embodiments of the present specification includes a plurality of sub-pixels, a power supply wiring for applying a voltage to the plurality of sub-pixels, and a plurality of power connection wirings for electrically connecting the plurality of sub-pixels to the power supply wiring.

[0282] In this case, each of the sub-pixels includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked. However, the organic light-emitting layer, the cathode electrode layer, and the passivation layer of the adjacent sub-pixels are insulated from each other. Each of the sub-pixels includes a structure that provides an undercut portion. However, the power connection wiring is arranged to overlap with the structure and is electrically connected to the cathode electrode layer in the undercut portion.

[0283] The display device further includes a plurality of data wirings arranged between the adjacent sub-pixels, and the data wirings may be arranged so as not to overlap with the cathode electrode layer.

[0284] The plurality of data wirings and the plurality of power connection wirings extend alternately in a first direction, and the plurality of data wirings and the plurality of power connection wirings may be arranged so as not to overlap with each other.

[0285] The plurality of sub-pixels are arranged in a matrix along a first direction and a second direction intersecting the first direction, and each of the power connection wirings may extend in the first direction so as to electrically connect the plurality of sub-pixels arranged in the first direction to the power wiring.

[0286] Each of the sub-pixels includes an outermost boundary portion of the organic light-emitting layer, an outermost boundary portion of the cathode electrode layer, and an outermost boundary portion of the passivation layer. The outermost boundary portion of the organic light-emitting layer is located inside the outermost boundary portion of the passivation layer, and the outermost boundary portion of the cathode electrode layer may be disposed between the outermost boundary portion of the organic light-emitting layer and the outermost boundary portion of the passivation layer.

[0287] The structure included in each of the sub-pixels may be located within the outermost boundary portion of the organic light-emitting layer, the outermost boundary portion of the cathode electrode layer, and the outermost boundary portion of the passivation layer.

[0288] The power wiring is a low-potential voltage (VSS) wiring, and a low-potential voltage can be applied to each of the cathode electrode layers included in each of the sub-pixels by the power connection wiring.

[0289] In addition, a display device according to an embodiment of the present specification includes a substrate on which a plurality of sub-pixels are defined; a plurality of power connection wirings disposed on the substrate; a plurality of structures disposed on the power connection wirings so as to be included in each of the sub-pixels and providing an undercut portion that exposes a part of the power connection wiring; a bank layer disposed on the power connection wiring and including a first opening that is opened so as to expose the undercut portion; and an organic light-emitting layer, a cathode electrode layer, and a passivation layer sequentially stacked so as to cover the bank layer and the structure.

[0290] In this case, the power connection wiring is electrically connected to the cathode electrode layer in the undercut portion, and the organic light-emitting layer, the cathode electrode layer, and the passivation layer of the sub-pixels adjacent to each other are insulated from each other.

[0291] The display device is further provided with a plurality of thin film transistors including source-drain electrodes, which are arranged on the substrate so as to be included in each of the sub-pixels, and a plurality of data wirings arranged on the substrate. The power connection wiring, the source-drain electrodes, and the data wirings can be arranged in the same layer and formed of the same material.

[0292] The bank layer is arranged so as to overlap the data wiring, and the data wiring may be arranged so as not to overlap the cathode electrode layer.

[0293] The display device further includes an overcoat layer arranged on the source-drain electrodes, and an anode electrode layer arranged between the overcoat layer and the bank layer and electrically connected to the source-drain electrodes. The structure includes a first structure layer, a second structure layer, and a third structure layer sequentially stacked. The first structure layer is arranged in the same layer as the overcoat layer and formed of the same material. The second structure layer is arranged in the same layer as the anode electrode layer and formed of the same material. The third structure layer may be arranged in the same layer as the bank layer and formed of the same material.

[0294] The first structure layer and the third structure layer may be in a positive taper shape.

[0295] The second structure layer can be electrically connected to the power connection wiring through a contact hole in the first structure layer.

[0296] The second structure layer may include a protruding portion protruding outward from the first structure layer and the third structure layer.

[0297] The cathode electrode layer arranged on the structure can be electrically connected to the protruding portion.

[0298] The display device further includes a power supply wiring which is a low potential voltage (VSS) wiring, and a low potential voltage can be applied to each of the cathode electrode layers included in each of the sub-pixels by the power supply connection wiring electrically connected to the power supply wiring.

[0299] Further, the display device according to the embodiment of the present specification includes steps of forming a plurality of source-drain electrodes, a plurality of power connection wirings, and a plurality of data wirings on a substrate, forming an overcoat layer, forming a plurality of anode electrode layers electrically connected to the plurality of source-drain electrodes respectively and a plurality of second structure layers electrically connected to the plurality of power connection wirings respectively on the overcoat layer, patterning the overcoat layer to provide undercut portions respectively below the plurality of second structure layers, forming a plurality of first structure layers, forming a bank layer including a plurality of first openings exposing the outer circumferences of the plurality of undercut portions and a plurality of second openings exposing a part of the plurality of anode electrode layers, forming a first protective layer and a first photoresist film so as to cover the substrate, patterning the first protective layer and the first photoresist film so as to expose the first openings and the second openings corresponding to a first sub-pixel, sequentially forming a first organic light-emitting layer having a first hue, a first cathode electrode layer, and a first passivation layer, and then removing the first protective layer and the first photoresist film, forming a second protective layer and a second photoresist film so as to cover the substrate, patterning the second protective layer and the second photoresist film so as to expose the first openings and the second openings corresponding to a second sub-pixel, sequentially forming a second organic light-emitting layer having a second hue, a second cathode electrode layer, and a second passivation layer, and then removing the second protective layer and the second photoresist film, forming a third protective layer and a third photoresist film so as to cover the substrate, patterning the third protective layer and the third photoresist film so as to expose the first openings and the second openings corresponding to a third sub-pixel, sequentially forming a third organic light-emitting layer having a third hue, a third cathode electrode layer, and a third passivation layer, and then removing the third protective layer and the third photoresist film, and can include these steps.

[0300] In the step of forming the bank layer, the step of forming a third structure layer on the second structure layer is included, and the third structure layer can be formed by the same patterning process as the first opening and the second opening.

[0301] The first organic light-emitting layer, the second organic light-emitting layer, and the third organic light-emitting layer are formed so as to be insulated from each other, the first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer are formed so as to be insulated from each other, and the first passivation layer, the second passivation layer, and the third passivation layer can be formed so as to be insulated from each other.

[0302] In the above, the embodiments of this specification have been further described with reference to the accompanying drawings. However, this specification is not necessarily limited to these embodiments, and various modified implementations within the scope not departing from the technical idea of this specification are possible. Therefore, the embodiments disclosed in this specification are for the purpose of explanation, not for limiting the technical idea of this specification, and the scope of the technical idea of this specification is not limited by these embodiments. Therefore, it must be understood that the above-described embodiments are illustrative and not restrictive in all respects.

Claims

1. a plurality of sub-pixels, a power supply wiring for applying a voltage to the plurality of sub-pixels, and a plurality of power connection wirings for electrically connecting the plurality of sub-pixels to the power supply wiring, each of the sub-pixels includes an organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked, the organic light-emitting layers of the plurality of sub-pixels adjacent to each other are insulated from each other, the cathode electrode layers of the plurality of sub-pixels adjacent to each other are insulated from each other, the passivation layers of the plurality of sub-pixels adjacent to each other are insulated from each other, each of the sub-pixels includes a structure providing an undercut portion, but each of the power connection wirings is arranged to overlap with the structure and is electrically connected to the cathode electrode layer in the undercut portion, A display device.

2. further including a plurality of data wirings arranged between the sub-pixels adjacent to each other, the plurality of data wirings are arranged so as not to overlap with the cathode electrode layer, The display device according to claim 1.

3. the plurality of data wirings and the plurality of power connection wirings extend alternately in a first direction, the plurality of data wirings and the plurality of power connection wirings are arranged so as not to overlap with each other, The display device according to claim 2.

4. the plurality of sub-pixels are arranged in a matrix along a first direction and a second direction intersecting the first direction, each of the power connection wirings extends in the first direction so as to electrically connect the plurality of sub-pixels arranged in the first direction to the power supply wiring, The display device according to claim 1.

5. Each of the sub-pixels includes the outermost boundary portion of the organic light-emitting layer, the outermost boundary portion of the cathode electrode layer, and the outermost boundary portion of the passivation layer. The outermost boundary portion of the organic light-emitting layer is located inside the outermost boundary portion of the passivation layer. The outermost boundary portion of the cathode electrode layer is disposed between the outermost boundary portion of the organic light-emitting layer and the outermost boundary portion of the passivation layer. The display device according to claim 1.

6. The structure included in each of the sub-pixels is located within the outermost boundary portion of the organic light-emitting layer, the outermost boundary portion of the cathode electrode layer, and the outermost boundary portion of the passivation layer. The display device according to claim 5.

7. The power supply wiring is a low-potential voltage (VSS) wiring. A low-potential voltage can be applied to each of the cathode electrode layers included in each of the sub-pixels by the power supply connection wiring. The display device according to claim 1.

8. A substrate on which a plurality of sub-pixels are defined. A plurality of power supply connection wirings disposed on the substrate. A plurality of structures disposed on the power supply connection wiring so as to be included in each of the sub-pixels, and providing an undercut portion that exposes a part of the power supply connection wiring. A bank layer disposed on the power supply connection wiring and including a first opening that is opened so as to expose the undercut portion. An organic light-emitting layer, a cathode electrode layer, and a passivation layer that are sequentially stacked so as to cover the bank layer and the structure. The power supply connection wiring is electrically connected to the cathode electrode layer at the undercut portion. The organic light-emitting layers of the plurality of adjacent sub-pixels are insulated from each other. The cathode electrode layers of the plurality of adjacent sub-pixels are insulated from each other. The passivation layers of the plurality of sub-pixels adjacent to each other are insulated from each other. Display device.

9. A plurality of thin film transistors including source-drain electrodes, disposed on the substrate so as to be included in each of the sub-pixels, and further including a plurality of data wirings disposed on the substrate. The power connection wiring, the source-drain electrode, and the data wiring are disposed in the same layer and formed of the same material. The display device according to claim 8.

10. The bank layer is disposed so as to overlap on the data wiring. The data wiring is disposed so as not to overlap with the cathode electrode layer. The display device according to claim 9.

11. An overcoat layer disposed on the source-drain electrode, and further including an anode electrode layer disposed between the overcoat layer and the bank layer and electrically connected to the source-drain electrode. The structure has a first structure layer, a second structure layer, and a third structure layer sequentially laminated. The first structure layer is disposed in the same layer as the overcoat layer and formed of the same material. The second structure layer is disposed in the same layer as the anode electrode layer and formed of the same material. The third structure layer is disposed in the same layer as the bank layer and formed of the same material. The display device according to claim 9.

12. The first structure layer and the third structure layer are in a positive taper shape. The display device according to claim 11.

13. The second structure layer is electrically connected to the power connection wiring through a contact hole of the first structure layer. The display device according to claim 11.

14. The second structure layer includes a protruding portion that protrudes outward from the first structure layer and the third structure layer. The display device according to claim 11.

15. The cathode electrode layer disposed on the structure is electrically connected to the protruding portion. The display device according to claim 14.

16. Further includes a power supply wiring that is a low potential voltage (VSS) wiring, A low potential voltage is applied to each of the cathode electrode layers included in each of the sub-pixels by the power supply connection wiring that is electrically connected to the power supply wiring. The display device according to claim 8.

17. Forming a plurality of source-drain electrodes, a plurality of power supply connection wirings, and a plurality of data wirings on a substrate to form an overcoat layer; Forming a plurality of anode electrode layers electrically connected to the plurality of source-drain electrodes respectively and a plurality of second structure layers electrically connected to the plurality of power supply connection wirings respectively on the overcoat layer; A step of patterning the overcoat layer to form a plurality of first structure layers below the plurality of second structure layers, wherein each of the plurality of first structure layers provides an undercut portion; Forming a bank layer including a plurality of first openings that expose the outer periphery of the plurality of undercut portions and a plurality of second openings that expose a part of the plurality of anode electrode layers; A first protective layer and a first photoresist film are formed to cover the substrate, and the first protective layer and the first photoresist film are patterned to expose the first opening and the second opening corresponding to the first sub-pixel. After sequentially forming a first organic light-emitting layer, a first cathode electrode layer, and a first passivation layer that embody a first hue, the first protective layer and the first photoresist film are removed. A second protective layer and a second photoresist film are formed to cover the substrate, and the second protective layer and the second photoresist film are patterned to expose the first opening and the second opening corresponding to the second sub-pixel. After sequentially forming a second organic light-emitting layer, a second cathode electrode layer, and a second passivation layer that embody a second hue, the second protective layer and the second photoresist film are removed. A third protective layer and a third photoresist film are formed to cover the substrate, and the third protective layer and the third photoresist film are patterned to expose the first opening and the second opening corresponding to the third sub-pixel. After sequentially forming a third organic light-emitting layer, a third cathode electrode layer, and a third passivation layer that embody a third hue, the third protective layer and the third photoresist film are removed. A method for manufacturing a display device.

18. In the step of forming the bank layer, It includes the step of forming a third structure layer on the second structure layer, The third structure layer is formed in the same patterning process as the first opening and the second opening. The method for manufacturing a display device according to claim 17.

19. The first organic light-emitting layer, the second organic light-emitting layer, and the third organic light-emitting layer are formed so as to be insulated from each other. The first cathode electrode layer, the second cathode electrode layer, and the third cathode electrode layer are formed so as to be insulated from each other. The first passivation layer, the second passivation layer, and the third passivation layer are formed so as to be insulated from each other. The method of manufacturing a display device according to claim 17.

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