Data transmission method and transmission apparatus according to an inter-integrated circuit protocol

Abstract

This application provides a data transmission method and transmission device according to the I2C protocol. The method includes a step in which a first transmission chip receives I2C data from a first device, the I2C data being data that the first device transmits to a second device, the first transmission chip corresponding to the first device. The first transmission chip transmits first feedback information to the first device, the first feedback information being used to indicate whether the I2C data has been successfully received. The first transmission chip transfers the I2C data to a second transmission chip corresponding to the second device. The first transmission chip receives second feedback information from the second transmission chip, the second feedback information being used to indicate whether the I2C data has been successfully received. The first transmission chip stores the second feedback information in a first memory space, the first memory space being the memory space of the first transmission chip. The method provided by this application enables an improvement in the effective rate of long-distance I2C data transmission.

Description

Technical Field

[0001] This application relates to the field of communications, and more specifically, to a data transmission method and a transmission device according to an inter-integrated circuit protocol.

Background Art

[0002] Currently, there are two methods of long-distance data transmission according to the inter-integrated circuit (I2C) protocol. Method 1 is that every time the transmission chip #1 corresponding to the master device receives 1 bit of I2C data from the master device, the transmission chip #1 transmits the received 1-bit I2C data to the transmission chip #2 corresponding to the slave device, and then, in turn, the transmission chip #2 further transmits the received 1-bit I2C data to the slave device. The master device repeats the above steps to transmit 8 bits of I2C data to the slave device. Method 2 is that every time the transmission chip #1 receives 8 bits of I2C data from the master device, the transmission chip #1 transmits the received 8-bit I2C data to the transmission chip #2, and then, in turn, the transmission chip #2 further transmits the received 8-bit I2C data to the slave device.

[0003] However, in the case of the above two methods, according to the I2C data transmission mechanism, after transmitting 8 bits of I2C data, the master device can transmit the next I2C data only after receiving 1 bit of feedback information (by the slave device transmitting feedback information to the transmission chip #2, the transmission chip #2 transmitting the feedback information to the transmission chip #1, and then, in turn, the transmission chip #1 transmitting the feedback information to the master device). Therefore, the actual rate of long-distance I2C data transmission is low.

Summary of the Invention

[0004] This application provides a data transmission method according to the I2C protocol to improve the effective rate of long-distance I2C data transmission.

[0005] According to a first aspect, a data transmission method according to the I2C protocol is provided. The method includes steps in which a first transmission chip acquires I2C data from a first device, where the I2C data is data that the first device transmits to a second device, and the first transmission chip corresponds to the first device; the first transmission chip transmits first feedback information to the first device, where the first feedback information is used to indicate whether reception of the I2C data was successful; the first transmission chip transfers the I2C data to a second transmission chip corresponding to the second device; the first transmission chip receives second feedback information from the second transmission chip, where the second feedback information is used to indicate whether reception of the I2C data was successful; and the first transmission chip stores the second feedback information in a first storage space, where the first storage space is the storage space of the first transmission chip.

[0006] Based on the above technical solution, in the process of a first device transmitting I2C data to a second device, the first transmission chip returns one piece of feedback information (i.e., the first feedback information) to the first device based on whether reception of the I2C data was successful. In this way, it is possible to continuously use the I2C interface between the first device and transmission chip #1 for transmission, thereby improving the effective rate of I2C data transmission. In addition, the second transmission chip transmits the actual feedback information received from the second device (i.e., the second feedback information) to the first transmission chip, so that the first device can obtain the actual feedback information of the slave device from the first transmission chip.

[0007] Optionally, the first device may be a master device, and the second device is a slave device.

[0008] Optionally, the first device may be a slave device, and the second device is a master device.

[0009] Regarding the first aspect, in some of the multiple implementations of the first aspect, the transfer of the I2C data by the first transmission chip to a second transmission chip corresponding to the second device includes that after the amount of at least one I2C data stored in a second storage space satisfies a preset condition, the first transmission chip transfers the at least one stored I2C data to the second transmission chip. The second storage space is the storage space of the first transmission chip. The at least one I2C data is data from the first device, and the at least one I2C data includes the I2C data.

[0010] Based on the above technical solution, after obtaining a plurality of I2C data, the first transmission chip may transfer the plurality of I2C data to the second transmission chip. In this way, the transmission frequency of the long-distance transmission data packet between the first transmission chip and the second transmission chip is decoupled from the transmission rate of the I2C data. In other words, the transmission frequency of the long-distance transmission data packet may be smaller than the transmission rate of the I2C data. Therefore, the long-distance transmission data packet may be made larger, thereby improving the transmission efficiency of the long-distance transmission.

[0011] Regarding the first aspect, in some of the multiple implementations of the first aspect, the first transmission chip receiving the second feedback information from the second transmission chip includes the first transmission chip receiving third feedback information from the second transmission chip, and the third feedback information is used to indicate second feedback information corresponding to one or more I2C data including the I2C data.

[0012] It is possible to understand that the second feedback information is feedback by the slave device for a certain received I2C data. In other words, the second feedback information fed back by the slave device has a one-to-one correspondence with the I2C data received by the slave device.

[0013] Regarding the first aspect, in some of the multiple implementations of the first aspect, after the first transmission chip receives the second feedback information from the second transmission chip, the method further includes the step of the first transmission chip setting the second storage space to a write-prohibited state.

[0014] Regarding the first aspect, in some of the multiple implementations of the first aspect, the first transmission chip obtaining the I2C data from the first device includes the first transmission chip reading the I2C data stored in the second storage space.

[0015] According to a second aspect, a data transmission method according to the I2C protocol is provided. The method includes steps in which a second transmission chip receives I2C data from a first transmission chip corresponding to a first device, where the second transmission chip corresponds to a second device; the second transmission chip transmits the I2C data to the second device; the second transmission chip receives second feedback information from the second device, where the second feedback information is used to indicate whether the reception of the I2C data was successful; and the second transmission chip transmits the second feedback information to the first transmission chip.

[0016] Based on the above technical solution, in the process of a first device transmitting I2C data to a second device, the first transmission chip returns one piece of feedback information (i.e., first feedback information) in the first device based on whether the reception of the I2C data was successful. In this way, it is possible to continuously use the I2C interface between the first device and transmission chip #1 for transmission, thereby improving the effective rate of I2C data transmission. In addition, the second transmission chip transmits the actual feedback information received from the second device (i.e., second feedback information) to the first transmission chip, so that the first device can obtain the actual feedback information of the slave device from the first transmission chip.

[0017] Optionally, the first device may be a master device, and the second device may be a slave device.

[0018] Optionally, the first device may be a slave device, and the second device may be a master device.

[0019] Regarding the second aspect, in some of the multiple implementations of the second aspect, the second transmission chip transmitting the second feedback information to the first transmission chip includes the second transmission chip transmitting third feedback information to the first transmission chip, and the third feedback information is used to indicate the second feedback information corresponding to one or more I2C data including the I2C data respectively.

[0020] It is possible to understand that the second feedback information is feedback by the slave device for a certain received I2C data. In other words, the second feedback information fed back by the slave device has a one-to-one correspondence with the I2C data received by the slave device.

[0021] Regarding the second aspect, in some of the multiple implementations of the second aspect, the second transmission chip transmitting the third feedback information to the first transmission chip includes the second transmission chip transmitting the third feedback information to the first transmission chip when a preset trigger condition is satisfied, and the preset trigger condition is that the amount of the second feedback information satisfies a preset condition, and / or the preset trigger condition is that at least one of the one or more I2C data fails to be received.

[0022] Regarding the second aspect, in some of the multiple implementations of the second aspect, the method further includes a step of the second transmission chip storing at least one I2C data from the first transmission chip in a third storage space, where the third storage space is the storage space of the second transmission chip, and the at least one I2C data includes the I2C data.

[0023] Based on the above technical solution, after obtaining a plurality of I2C data, the first transmission chip may transfer the plurality of I2C data to the second transmission chip. In this way, the transmission frequency of the long-distance transmission data packet between the first transmission chip and the second transmission chip is decoupled from the transmission rate of the I2C data. In other words, the transmission frequency of the long-distance transmission data packet may be smaller than the transmission rate of the I2C data. Therefore, the long-distance transmission data packet may be made larger, thereby improving the transmission efficiency of the long-distance transmission.

[0024] According to a third aspect, a data transmission method according to the I2C protocol is provided. The method includes steps in which a master device transmits I2C data to a first transmission chip, where the first transmission chip corresponds to the master device; the master device receives first feedback information from the first transmission chip, where the first feedback information is used to indicate whether the reception of the I2C data is successful; and the master device reads a first storage space corresponding to the first transmission chip to obtain second feedback information, where the second feedback information is used to indicate whether the reception of the I2C data is successful.

[0025] Based on the above technical solution, in the process of the master device writing data to the slave device, the first transmission chip returns one piece of feedback information (i.e., the first feedback information) in the master device based on whether the reception of the I2C data is successful. In this way, for transmission, it is possible to continuously use the I2C interface between the master device and the first transmission chip, thereby improving the actual rate of I2C data transmission. In addition, the second transmission chip transmits the actual feedback information of the slave device (i.e., the second feedback information) to the first transmission chip. Furthermore, the master device can obtain the actual feedback information of the slave device from the first transmission chip.

[0026] Regarding the third aspect, in some of the multiple implementations of the third aspect, the master device reading the first storage space corresponding to the first transmission chip includes the master device periodically reading the first storage space.

[0027] Regarding the third aspect, in some of the multiple implementations of the third aspect, before the master device reads the first storage space corresponding to the first transmission chip, the method further includes the step of the master device determining that the second storage space corresponding to the first transmission chip is in a write-prohibited state.

[0028] According to the fourth aspect, a transmission device is provided that includes a plurality of modules or a plurality of units configured to execute the method in any one of the first aspect and the possible implementations of the first aspect.

[0029] According to the fifth aspect, a transmission device is provided that includes a plurality of modules or a plurality of units configured to execute the method in any one of the second aspect and the possible implementations of the second aspect.

[0030] According to a sixth aspect, a transmission device including a processor is provided. The processor is coupled to a memory and configured to execute instructions in the memory to implement a method according to any one of the first aspect and the second aspect or a plurality of possible implementations of the first aspect and the second aspect.

[0031] According to a seventh aspect, a transmission device including a plurality of modules or a plurality of units configured to execute a method according to any one of the third aspect and a plurality of possible implementations of the third aspect is provided.

[0032] According to an eighth aspect, a communication device including a processor is provided. The processor is coupled to a memory and configured to execute instructions in the memory to implement a method according to any one of the third aspect and a plurality of possible implementations of the third aspect.

[0033] According to a ninth aspect, a processor including an input circuit, an output circuit, and a processing circuit is provided. The processing circuit is configured to receive a signal by using the input circuit and transmit a signal by using the output circuit, whereby the processor executes a method according to any one of the first aspect to the third aspect or a plurality of possible implementations of the first aspect to the third aspect.

[0034] In a particular implementation process, the processor may be a chip, the input circuit may be an input pin, the output circuit may be an output pin, and the processing circuit may be a transistor, a gate circuit, a trigger, or various logic circuits, etc. The input signal received by the input circuit may be, for example, but not limited to, what a receiver may receive and input, and the signal output by the output circuit may be, for example, but not limited to, output to a transmitter, and that transmitter may transmit it. The input circuit and the output circuit may be the same circuit, and that circuit may be used as an input circuit and as an output circuit at multiple different times. The specific implementation of the processor and those circuits is not limited to those multiple embodiments of this application.

[0035] According to a tenth aspect, a processing device is provided. The processing device includes a processor and may further include a memory. The memory is configured to store instructions, and the processor is configured to read the instructions stored in the memory, receive signals by using a receiver, and transmit signals by using a transmitter to execute a method in any one of the first aspect to the third aspect or a plurality of possible implementations of the first aspect to the third aspect.

[0036] Optionally, one or more processors exist, and one or more memories exist.

[0037] Optionally, the memory and the processor may be integrated, or the memory and the processor may be arranged separately.

[0038] In a particular implementation process, the memory may be a non-transitory memory such as a read-only memory (ROM). The memory and the processor may be integrated into one chip, or may be arranged on multiple different chips. The type of the memory and the way the memory and the processor are arranged are not limited in those multiple embodiments of this application.

[0039] Regarding related data exchange processes, for example, it should be understood that the instruction information transmission process may be a process of outputting instruction information from a processor, and the capability information reception process may be a process of receiving input capability information by the processor. Specifically, the data output by the processor may be output to a transmitter, and the input data received by the processor may be data from a receiver. The transmitter and the receiver may collectively be referred to as a transceiver.

[0040] The processing device according to the tenth aspect may be a chip. The processor may be implemented by using hardware or software. When implementing the processor by using hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implementing the processor by using software, the processor may be a general-purpose processor and is implemented by reading software code stored in a memory. The memory may be integrated into the processor or may be arranged outside the processor and exist independently.

[0041] According to the eleventh aspect, a computer program product is provided. The computer program product includes a computer program (which may also be referred to as code or instructions). When the computer program is executed, it enables the computer to execute a method according to any one of the first aspect to the third aspect or a plurality of possible implementations of the first aspect to the third aspect.

[0042] According to a twelfth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program (which may also be referred to as code or instructions). When the computer program is executed by a computer, it enables the computer to execute a method according to any one of the first aspect to the third aspect or a plurality of possible implementations of the first aspect to the third aspect.

[0043] According to a thirteenth aspect, an I2C data transmission system including a master device, a first transmission chip, a second transmission chip, and a slave device is provided.

Brief Description of the Drawings

[0044]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Embodiments for Carrying Out the Invention

[0045] The following description explains multiple technical solution methods of this application with reference to multiple attached drawings.

[0046] The Inter-Integrated Circuit (I2C) is a low-speed serial bus configured to connect microcontrollers such as master devices and peripheral device devices such as slave devices, and is also a short-distance transmission bus routed on a printed circuit board (PCB). As shown in FIG. 1, the I2C includes two lines. One line is the serial clock line (SCL), and the serial clock line is configured to transmit a clock. The SCL is unidirectional transmission, that is, only the microcontroller can transmit the clock to the peripheral device device. The other line is the serial data line (SDA), and the serial data line is configured to transmit data. The SDA is bidirectional transmission, that is, data may be transmitted from the microcontroller to the peripheral device device, or from the peripheral device device to the microcontroller.

[0047] The microcontroller controls the I2C behavior by controlling the level states of two lines. As shown in Figure 2, when SCL is at a high level and SDA changes from a high level to a low level, the state transition indicates the start of data transmission. When SCL is at a high level and SDA changes from a low level to a high level, the state transition indicates the end of data transmission.

[0048] During I2C-based data transmission, each period of interaction fixedly includes 9 bits, with 8 bits representing data and 1 bit representing feedback. That is, each time the transmitter sends 8 bits of data, the transmitter needs to receive 1 bit of feedback from the receiver before performing the next operation. As shown in Figure 2, the 8 bits of data initially sent by the transmitter to the receiver include a 7-bit receiving device address and 1 bit of read / write

Number

[0049] In the scenario of long-distance I2C data transmission, the distance between the microcontroller and the peripheral device is relatively long (usually approximately 10 [m]). Therefore, based on long-distance transmission technology, it is necessary to transparently transmit I2C data within the data packet. As shown in Figure 3, in the scenario of an in-vehicle network, as the microcontroller, a multi-domain controller (MDC) is used, and the MDC is installed in the vehicle. As the peripheral device, an in-vehicle camera is usually installed on the front windshield, rear bumper, or door post. Therefore, there is a long distance between the camera and the MDC. There is a high-speed transmission line, and the high-speed transmission line may be used to transmit images between the MDC and the camera. Therefore, the I2C data may be transmitted collinearly on the long-distance high-speed transmission line between the camera and the MDC.

[0050] Currently, I2C data may be transmitted over a long distance by the following two methods.

[0051] Method 1:

[0052] One example where the MDC transmits I2C data to the camera (e.g., the data to be transmitted is 10101001) is shown in FIG. 3. The MDC transmits 1-bit of I2C data to the corresponding transmission chip #1 each time. Further, the transmission chip #1 transmits the 1-bit of I2C data it received to the corresponding transmission chip #2 for the camera. Further, the transmission chip #2 transmits the 1-bit of I2C data it received to the camera. The above steps are repeated until the MDC transmits all 8 bits of I2C data to the camera and the camera feeds back a 1-bit ACK message or a 1-bit negative acknowledgment (NACK) message to the transmission chip #2. Further, the transmission chip #2 inserts 1-bit of feedback information and transmits the 1-bit of feedback information to the transmission chip #1. Further, the transmission chip #1 feeds back the feedback information it received to the MDC. The MDC transmits the next 8 bits of I2C data only after receiving the 1-bit of feedback information.

[0053] As shown in FIG. 3, the I2C transmission between transmission chip #1 and transmission chip #2 is a long-distance transmission. That is, for the transmission, in the long-distance transmission data packet, it is necessary to carry the I2C data that transmission chip #1 sends to transmission chip #2. Therefore, the prerequisite for transmitting I2C data by using the above method is that it is necessary to increase the transmission frequency of the long-distance transmission data packet more than the transmission rate of the I2C data. For example, the transmission rate of the I2C data is 400 kilobits per second (Kbps). According to the method in Method 1, when transmitting the I2C data, every time transmission chip #1 transmits 1 bit of I2C data to transmission chip #2, it is necessary to carry that 1 bit of I2C data in the long-distance transmission data packet. In other words, within 1 second, when transmission chip #1 needs to transmit 400 kilobits of I2C data to transmission chip #2, it is necessary to transmit at least 400,000 data packets between transmission chip #1 and transmission chip #2. Therefore, it is necessary to increase the transmission frequency of the long-distance transmission data packet to be greater than 400 [KHz]. Table 1 shows the long-distance transmission rate and the packet size for long-distance transmission corresponding to multiple different I2C data transmission rates, and the encapsulated packet size (byte) = long-distance transmission rate / I2C data transmission rate / 8. For example, 1 [Gbps] / 400 [Kbps] / 8 = 312.5 [bytes]. For example, the transmission rate of the I2C data is 400 [Kbps], that is, within 1 second, it is necessary to transmit at least 400,000 long-distance transmission packets. When the long-distance transmission rate is 1 [Gbps], the size of each packet is 1 [Gb] / 400,000 / 8 = 312.5 [bytes]. The following table is only one example and uses simplified calculations, that is, it should be noted that 1 [Kbps] = 1,000 [bps], 1 [Mbps] = 1,000,000 [bps], and 1 [Gbps] = 1,000,000,000 [bps]. Other overheads such as packet headers and signaling are not considered.

Table 1

[0054] Therefore, when transmitting I2C data by using the above method, since the transmission rate of the I2C data is linked to the transmission frequency of the long-distance transmission data packet, the size of the long-distance transmission data packet is limited. However, each long-distance transmission data packet indicates the format of the data to be transmitted, and it is necessary to inspect the data packet. Therefore, smaller long-distance transmission data packets exhibit lower transmission efficiency. In other words, when transmitting I2C data by using the above method, the long-distance transmission rate is linked to the transmission rate of the I2C data, thereby affecting the size of the encapsulated packet for long-distance transmission and reducing the transmission efficiency of the long-distance interface.

[0055] Method 2:

[0056] One example where MDC transmits I2C data to the camera (for example, the data to be transmitted is 10101001) is shown in FIG. 4. After receiving 8-bit I2C data from MDC, the transmission chip #1 corresponding to MDC inserts the 8-bit I2C data and transmits the 8-bit I2C data to the transmission chip #2 corresponding to the remote camera at one time. Further, the transmission chip #2 transmits the 8-bit I2C data to the camera. After receiving the 8-bit I2C data, the camera feeds back 1-bit ACK / NACK to the transmission chip #2. Further, the transmission chip #2 transmits the received 1-bit feedback information to the transmission chip #1. The transmission chip #1 then feeds back 1-bit feedback information to MDC. After receiving the 1-bit feedback information, MDC transmits the next 8-bit I2C data.

[0057] For example, the transmission rate of I2C data is 400 [Kbps]. In the short-distance transmission process of I2C data, the time required to transmit 8-bit data and 1-bit feedback information between the microcontroller and the peripheral device is 2.5×9 microseconds. In contrast, in the process of performing long-distance transmission of I2C data by using the above method, it takes 2.5×8 microseconds for MDC to transmit 8-bit I2C data to transmission chip #1, and it takes 2.5×8 microseconds for transmission chip #2 to transmit 8-bit I2C data to the camera. In addition, it takes 2.5 microseconds for the camera to return 1-bit feedback information to transmission chip #2, and it takes 2.5 microseconds for transmission chip #1 to feedback the 1-bit feedback information from transmission chip #2 to MDC. Furthermore, there is a transmission delay between transmission chip #1 and transmission chip #2.

[0058] Therefore, the long-distance transmission of I2C is performed by using the above method, and the interaction time between MDC and the camera is greater than 2.5×9×2 microseconds (2.5×9×2 microseconds + the transmission delay between transmission chip #1 and transmission chip #2). In other words, compared with the short-distance transmission of I2C data, the transmission interaction time of the long-distance transmission of I2C data performed in Method 2 is greater than twice. Therefore, the long-distance transmission of I2C data by using the above method significantly reduces the effective rate of I2C data transmission by more than twice.

[0059] Based on this, one embodiment of this application provides a data transmission method according to the I2C protocol to improve the effective transmission rate of I2C data.

[0060] FIG. 5 is a schematic diagram of a communication system 100 applicable to a method according to one embodiment of this application. As shown in FIG. 5, the master device is connected to the corresponding transmission chip #1, and the slave device is connected to the corresponding transmission chip #2 by the I2C bus. That is, I2C data may be transmitted between the master device and transmission chip #1 and between the slave device and transmission chip #2 according to the existing I2C mechanism. The master device corresponds to transmission chip #1 (or, transmission chip #1 corresponds to the master device). It is possible to understand that the master device is connected to transmission chip #1 by the I2C bus. Specifically, transmission chip #1 may be integrated into the master device or may be independent of the master device. This is not limited in this application. The slave device corresponds to transmission chip #2 (or, transmission chip #2 corresponds to the slave device). It is possible to understand that the slave device is connected to transmission chip #2 by the I2C bus. Specifically, transmission chip #2 may be integrated into the slave device or may be independent of the slave device. This is not limited in this application.

[0061] Transmission chip #1 and transmission chip #2 are connected by a long-distance transmission line, that is, long-distance transmission data packets may be transmitted between transmission chip #1 and transmission chip #2. In addition, the I2C data transmitted between transmission chip #1 and transmission chip #2 may be carried in the long-distance transmission data packet for transmission.

[0062] In the communication system shown in FIG. 5, the transmission chip #1 corresponding to the master device is connected to the transmission chip corresponding to only one slave device. In some of the multiple scenarios, the transmission chip #1 may be connected to multiple transmission chips corresponding to multiple slave devices. In the communication system 200 shown in FIG. 6, the transmission chip #1 is connected to the transmission chip #2 and the transmission chip #3. In the case of the communication system shown in FIG. 6, only one example is shown where there is one I2C interface between the master device and the transmission chip #1, but there may be multiple I2C interfaces between the master device and the transmission chip #1. When there is one I2C interface between the master device and the transmission chip #1, it is possible to understand that the master device can interact with only one slave device at a time. When there are multiple I2C interfaces between the slave device and the transmission chip #1, the master device can interact with multiple slave devices simultaneously. In this case, each I2C interface between the slave device and the transmission chip #1 corresponds to multiple different slave devices.

[0063] In the case of the communication system 300 shown in FIG. 7, in some of the multiple application scenarios, the transmission chip #1 corresponding to the master device may be further connected to the transmission chip #2 corresponding to the slave device by using a gateway or a switch.

[0064] The following description provides a detailed explanation of a data transmission method according to the I2C protocol provided by one embodiment of this application with reference to multiple accompanying drawings.

[0065] It should be understood that the following description is only for the purpose of facilitating understanding and explanation. For the sake of explanation, one example is used where a first device interacts with only one second device. On the other hand, this should not constitute a limitation to the multiple embodiments of this application. The methods provided by the multiple embodiments of this application are also applicable to a scenario where a first device interacts with multiple second devices. The first device may be a master device, and the second device may be a slave device. Alternatively, the first device may be a slave device, and the second device may be a master device. In a scenario where the first device interacts with multiple second devices, the first device may interact with each second device by using the methods provided by the multiple embodiments of this application.

[0066] It should be noted that the memory space #1 and memory space #2 mentioned in the multiple embodiments shown below correspond to transmission chip #1, and the memory space #1 and memory space #2 may correspond to the same memory in transmission chip #1, or may correspond to multiple different memories in transmission chip #1. This is not limited to the multiple embodiments of this application.

[0067] Furthermore, it should be noted that the memory space #3 and memory space #4 mentioned in the multiple embodiments shown below correspond to transmission chip #2, and the memory space #3 and memory space #4 may correspond to the same memory in transmission chip #2, or may correspond to multiple different memories in transmission chip #2. This is not limited in the multiple embodiments of this application.

[0068] FIG. 8 is a schematic flowchart of a data transmission method according to one embodiment of this application. A first device and a corresponding transmission chip #1 are connected by an I2C bus, a second device and a corresponding transmission chip #2 are connected by an I2C bus, and the transmission chip #1 and the transmission chip #2 are connected by a long-distance transmission line. The method 400 shown in FIG. 8 may be applied to the communication systems 100 to 300 shown in FIGS. 5 to 7. The first device and the second device shown in FIG. 8 may be the master device and the slave device in the communication systems 100 to 300 respectively, or the first device and the second device shown in FIG. 8 may be the slave device and the master device in the communication systems 100 to 300 respectively. The method shown in FIG. 8 may include S410 to S470. The following description will explain in detail those multiple steps in the method 400.

[0069] S410: The first device transmits I2C data to the transmission chip #1 (which is an example of one of the first transmission chips). Correspondingly, in S410, the transmission chip #1 acquires the I2C data from the first device.

[0070] The I2C data is the data that the first device transmits to the second device.

[0071] S420: The transmission chip #1 transmits feedback information #1 (which is an example of one of the first feedback information) to the first device.

[0072] The feedback information #1 is used to indicate whether the reception of the I2C data is successful.

[0073] The first device transmitting I2C data to transmission chip #1 may mean that the first device writes the I2C data to the address of transmission chip #1. For example, the first device writes the I2C data to memory space #2 (which is an example of one of the second storage spaces) corresponding to address #2 of transmission chip #1.

[0074] Transmission chip #1 obtaining I2C data from the first device may mean that transmission chip #1 reads the I2C data that the first device has written to memory space #2.

[0075] After obtaining the I2C data, transmission chip #1 may return feedback information #1 to the first device based on whether the I2C data is complete (such as whether the I2C data is sufficient in 8 bits). When the I2C data is complete, or when transmission chip #1 has successfully received the I2C data, the feedback information #1 transmitted by transmission chip #1 to the first device may be an ACK message. When the I2C data is not complete, or when transmission chip #1 has failed to receive the I2C data, the feedback information #1 transmitted by transmission chip #1 to the first device may be a NACK message.

[0076] When used to indicate that the feedback information #1 has successfully received the I2C data, the first device continues to transmit the next I2C data to the transmission chip #1. When used to indicate that the feedback information #1 has failed to receive the I2C data, the first device retransmits the I2C data corresponding to the feedback information #1 to the transmission chip #2. For example, after transmitting the I2C data #1 to the transmission chip #1, when the first device receives the ACK message fed back by the transmission chip #1, the first device continues to transmit the I2C data #2 to the transmission chip #1. When the first device receives the NACK message fed back by the transmission chip #1, the first device retransmits the I2C data #1 to the transmission chip #1.

[0077] According to the I2C transmission mechanism, after transmitting one 8-bit I2C data, the first device can transmit the next 8-bit I2C data only after receiving one 1-bit feedback information. In this embodiment of this application, according to the solution in which the transmission chip #1 returns 1-bit feedback information #1 to the first device based on whether the reception of the I2C data is successful, the effective rate for transmitting the I2C data by the first device is improved.

[0078] S430: The transmission chip #1 transfers the I2C data to the transmission chip #2 (which is an example of one of the second transmission chips).

[0079] It can be understood that the I2C data transmitted by the transmission chip #1 to the transmission chip #2 is carried in the long-distance transmission data packet.

[0080] The method by which transmission chip #1 transfers I2C data to transmission chip #2 may be that transmission chip #1 conveys the I2C data within a long-distance transmission data packet and transparently transmits the I2C data to transmission chip #2. Alternatively, transmission chip #1 may encapsulate the I2C data to form a new data packet, and then convey the new data packet within the long-distance transmission packet to transmit the I2C data to transmission chip #2. Alternatively, transmission chip #1 may segment and insert the I2C data to form a plurality of data packets, and then convey those plurality of data packets within the long-distance transmission data packet to transmit the I2C data to transmission chip #2. Of course, a specific implementation in which transmission chip #1 transfers I2C data is not limited to the methods listed above. This is not limited in this embodiment of this application.

[0081] In one implementation, each time transmission chip #1 acquires one 8-bit I2C data, transmission chip #1 may transfer the acquired I2C data to transmission chip #2.

[0082] In other implementations, after acquiring a plurality of 8-bit I2C data, transmission chip #1 may transfer those plurality of 8-bit I2C data to transmission chip #2 at once. For example, after the amount of I2C data stored in storage space #2 meets a preset condition, transmission chip #1The transmission chip #2 may transfer those multiple I2C data stored therein. The pre-set condition may be, for example, that the amount of I2C data stored in the storage space #2 is equal to N, where N is an integer greater than 1. For example, alternatively, the pre-set condition may be, for example, when the storage time of the earliest stored I2C data exceeds a threshold value, or when the average storage time of the multiple stored I2C data exceeds that threshold value, or when the storage time of the latest stored I2C data exceeds that threshold value, etc., that is, when the time of the I2C data stored in the storage space #2 exceeds a certain specific threshold value. This is not limited in this application.

[0083] The method for the transmission chip #1 to determine whether the amount of I2C data stored in the storage space #2 is equal to N is not limited in this embodiment of this application.

[0084] For example, each time one I2C data is acquired, the transmission chip #1 determines the amount of I2C data stored in the storage space #2, that is, determines whether the amount of I2C data is equal to N.

[0085] In another example, the transmission chip #1 holds a counter. Each time the transmission chip #1 acquires one I2C data, it increases the value of the counter by only one. Further, the transmission chip #1 determines whether the value of the counter is equal to N. After the transmission chip #1 transfers N I2C data to the transmission chip #2, it clears the value of the counter.

[0086] The manner in which the transmission chip #1 transfers multiple I2C data is not limited in this embodiment of this application.

[0087] As an example, transmission chip #1 may generate one packet based on a plurality of I2C data (such as arranging a plurality of I2C data sequentially to generate one data packet), carry the generated data packet in a long-distance transmission data packet, and transmit the data packet to transmission chip #2.

[0088] In another example, transmission chip #1 carries a plurality of I2C data in a long-distance transmission data packet and transmits the plurality of I2C data to transmission chip #2.

[0089] In an embodiment of this application, after acquiring a plurality of I2C data, transmission chip #1 transfers the plurality of I2C data to transmission chip #2. Therefore, the transmission frequency of the long-distance transmission data packet between transmission chip #1 and transmission chip #2 is decoupled from the transmission rate of the I2C data, that is, the transmission frequency of the long-distance transmission data packet may be lower than the transmission rate of the I2C data. Therefore, the long-distance transmission data packet may be larger, thereby improving the transmission efficiency of long-distance transmission.

[0090] S440: Transmission chip #2 transmits I2C data to the second device.

[0091] When the first device is a master device and the second device is a slave device, after receiving the I2C data from transmission chip #1, transmission chip #2 actively transmits the received I2C data to the slave device.

[0092] When the first device is a slave device and the second device is a master device, after receiving the I2C data from transmission chip #1, transmission chip #2 stores the I2C data in memory space #3 (which is one example of a third storage space), and then waits for the master device to read memory space #3. Referring to other embodiments, a method for the master device to read memory space #3 will be described. Details will not be described for the time being in this specification.

[0093] S450: The second device transmits feedback information #2 (which is one example of the second feedback information) to transmission chip #2.

[0094] Feedback information #2 is used to indicate whether the reception of the I2C data is successful.

[0095] After receiving the I2C data from transmission chip #1, transmission chip #2 transmits the I2C data to the second device according to the existing I2C procedure, that is, writes the I2C data to the address of the second device.

[0096] After receiving the I2C data from transmission chip #2, the second device transmits feedback information #2 to transmission chip #2 based on whether the I2C data is complete (such as whether the I2C data is sufficient for 8 bits) and whether the content is complete. When the I2C data is complete and the content is correct, or when the second device has successfully received the I2C data, the feedback information #2 transmitted by the second device to transmission chip #2 may be an ACK message. When the I2C data is incomplete and / or the content is incorrect, or when the second device has failed to receive the I2C data, the feedback information #2 transmitted by the second device to transmission chip #2 may be a NACK message.

[0097] As described above, transmission chip #1 may transmit a plurality of I2C data to transmission chip #2 at once. In this case, transmission chip #2 may store the plurality of received I2C data in storage space #3. Further, transmission chip #2 sequentially transmits the plurality of I2C data to the second device according to the I2C procedure. For example, transmission chip #2 transmits I2C data #1 to the second device, and after receiving feedback information #2 transmitted by the second device, transmission chip #2 transmits I2C data #2 to the second device.

[0098] S460: Transmission chip #2 transmits feedback information #2 to transmission chip #1.

[0099] In one implementation, transmission chip #2 may generate new feedback information such as feedback information #3 (which is one example of the third feedback information) based on the received feedback information #2, and transmit feedback information #3 to transmission chip #1. Transmission chip #1 may obtain feedback information #2 based on the received feedback information #3. In one possible design, feedback information #3 may be information in the I2C data.

[0100] Of course, one specific implementation in which transmission chip #2 transmits feedback information #2 is not limited to the methods listed above. For example, transmission chip #2 may directly transmit the received feedback information #2 to transmission chip #1. One specific implementation in which transmission chip #2 transmits feedback information #2 is not limited in this application.

[0101] It can be understood that the feedback information #3 transmitted by transmission chip #2 to transmission chip #1 is carried in the long-distance transmission data packet.

[0102] Optionally, each time transmission chip #2 receives one piece of feedback information #2, transmission chip #2 may generate one piece of feedback information #3 based on that one piece of feedback information #2, and further transmit the feedback information #3 to transmission chip #1.

[0103] Optionally, transmission chip #2 may transmit feedback information #3 to transmission chip #1 when a preset trigger condition is satisfied, and the feedback information #3 is used to indicate the feedback information #2 corresponding to one or more I2C data respectively. The preset trigger condition may be that the amount of feedback information #2 received by transmission chip #2 satisfies a preset condition, and / or at least one of the one or more I2C data reception fails. The preset condition may be, for example, that the amount of feedback information #2 is equal to M, and M is an integer greater than 1.

[0104] For example, transmission chip #2 may transmit feedback information #3 to transmission chip #1 when the amount of received feedback information #2 satisfies a preset condition. For example, when the amount of received feedback information #2 is equal to M, transmission chip #2 may generate feedback information #3 based on those M pieces of feedback information #2, and transmit the feedback information #3 to transmission chip #1. The feedback information #3 is used to indicate the feedback information #2 corresponding to M pieces of I2C data respectively.

[0105] In another example, transmission chip #2 may, for example, determine whether the reception of the I2C data corresponding to each piece of feedback information #2 is successful based on one or more pieces of received feedback information #2, and when it is determined that at least one of the one or more I2C data reception fails, transmission chip #2 may transmit feedback information #3 to transmission chip #1.

[0106] For example, transmission chip #2 receives K pieces of feedback information #2, and these K pieces of feedback information #2 are each used to indicate that the reception of I2C data #1 to I2C data #K has been successful. Transmission chip #2 then transmits I2C data #K+1 to the second device and receives the (K+1)th piece of feedback information #2 fed back by the second device. The (K+1)th piece of feedback information #2 is used to indicate that the reception of I2C data #K+1 has failed. Subsequently, based on the K+1 pieces of received feedback information #2, transmission chip #2 generates feedback information #3 and transmits the feedback information #3 to transmission chip #1. K is an integer.

[0107] In yet another example, when it is determined that the amount of received feedback information #2 meets a preset condition and that at least one of the one or more I2C data has failed to be received, transmission chip #2 transmits feedback information #3 to transmission chip #1. For example, when the amount of feedback information #2 received by the transmission chip is equal to M and at least one of the M pieces of feedback information #2 is used to indicate that the reception of the I2C data corresponding to that feedback information #2 has failed, the transmission chip generates feedback information #3 based on the M pieces of feedback information #2 and transmits the feedback information #3 to transmission chip #1.

[0108] When the amount of feedback information #2 received by transmission chip #2 meets the pre-set conditions, and multiple pieces of feedback information #2 are used to indicate that the reception of I2C data corresponding to each piece of feedback information #2 is successful, transmission chip #2 may generate feedback information #3 based on those multiple pieces of received feedback information #2 and transmit that feedback information #3 to transmission chip #1. Alternatively, after receiving feedback information #2 that is used to indicate that the reception of I2C data has failed, transmission chip #2 may generate feedback information #3 based on the received feedback information #2 and transmit that feedback information #3 to transmission chip #1.

[0109] As an example, the time when transmission chip #2 stores feedback information #2 in storage space #4 may exceed a certain specific threshold. For example, the storage time of the earliest stored feedback information #2 exceeds that threshold, or the average storage time of multiple stored pieces of feedback information #2 exceeds that threshold, or the storage time of the latest stored feedback information #2 exceeds that threshold. This is not limited in this application. When transmission chip #2 generates feedback information #3 based on those multiple pieces of feedback information #2 after receiving them, transmission chip #2 may store those multiple pieces of feedback information #2 in storage space #4 before generating feedback information #3. After generating feedback information #3 based on multiple pieces of feedback information #2 and transmitting that feedback information #3 to transmission chip #1, transmission chip #2 clears those multiple pieces of feedback information #2 stored in storage space #4.

[0110] The method by which transmission chip #2 determines whether the amount of received feedback information #2 is equal to M is not limited in this embodiment of this application.

[0111] In one example, each time the transmission chip #2 receives one piece of feedback information #2, the transmission chip #2 determines the amount of feedback information #2 stored in the storage space #4, that is, determines whether the amount of feedback information #2 is equal to M.

[0112] In another example, the transmission chip #2 holds a counter. Each time the transmission chip #2 receives one piece of feedback information #2, it increments the value of the counter by one. Further, the transmission chip #2 determines whether the value of the counter is equal to M. After the transmission chip #2 transmits the feedback information #3 to the transmission chip #1 based on those M pieces of feedback information #2, it clears the value of the counter.

[0113] S470: The transmission chip #1 stores the feedback information #2 in the storage space #1 (which is an example of the first storage space).

[0114] In one implementation, after receiving the feedback information #3 from the transmission chip #2, the transmission chip #1 obtains the feedback information #2 based on the feedback information #3.

[0115] In one implementation, when the first device is the master device and the second device is the slave device, after S470, the method may further include the master device reading the storage space #1 of the transmission chip #1 to obtain the feedback information #2. The following description explains how the master device reads the storage space #1 with reference to other embodiments. For the sake of brevity, details are not described herein.

[0116] In other implementations, when the first device is the slave device and the second device is the master device, after S470, the method may include the transmission chip #1 transmitting the feedback information #2 to the slave device.

[0117] In this embodiment of this application, during the process in which the first device transmits I2C data to the second device, based on whether the transmission chip #1 has successfully received the I2C data, it returns one piece of feedback information (i.e., feedback information #1) to the first device. In this way, for transmission, it is possible to continuously use the I2C interface between the first device and the transmission chip #1, thereby improving the actual transmission rate of the I2C data. In addition, the transmission chip #2 may transmit the actual feedback information (i.e., feedback information #2) from the second device to the transmission chip #1. Thereby, the first device can obtain the actual feedback information of the slave device from the first transmission chip. Further, the transmission chip #1 can trigger the first device to obtain the actual feedback information of the second device, or transmit the actual feedback information of the second device to the first device to ensure that the first device can receive the actual feedback information from the second device.

[0118] Referring to FIG. 9, the following description uses one example where the first device is a master device and the second device is a slave device to explain the data transmission method provided by these multiple embodiments of this application.

[0119] FIG. 9 is a schematic flowchart of a data transmission method compliant with the I2C protocol according to one embodiment of this application. The method 500 shown in FIG. 9 may include S510 to S570. The following description will explain these multiple steps in detail.

[0120] S510: The master device transmits a write command to the transmission chip #1 (one example of the first transmission chip).

[0121] When the master device sends a write command to transmission chip #1, the master device can understand that it writes the write command to the address of transmission chip #1. For example, the master device writes the write command to memory space #2 (which is one example of the second memory space) of transmission chip #1.

[0122] Correspondingly, after obtaining the write command from the master device, transmission chip #1 returns a 1-bit ACK message or a 1-bit NACK message to the master device based on whether the write command is sufficient for 8 bits and whether the content of the write command is correct. If the write command is sufficient for 8 bits and its content is correct, transmission chip #1 returns an ACK message to the master device. If the write command is smaller than 8 bits and / or the content is incorrect, transmission chip #1 returns a NACK message to the master device.

[0123] Furthermore, when the master device receives an ACK message from transmission chip #1, the master device starts transmitting I2C data to transmission chip #1. When the master device receives a NACK message from transmission chip #1, the master device restarts the data writing procedure, that is, it resends the write command to transmission chip #1 until the master device receives an ACK message from transmission chip #1, and then the master device starts transmitting I2C data to transmission chip #1.

[0124] S520: The master device transmits I2C data to transmission chip #1.

[0125] The I2C data is data transmitted from the master device to the slave device. Hereinafter, for the sake of explanation, one example is used where the master device transmits N I2C data to transmission chip #1, and N is a positive integer.

[0126] S5201a: The master device transmits I2C data #1 to transmission chip #1.

[0127] It can be understood that the first I2C data (such as I2C data #1, etc.) transmitted by the master device to the slave device is a write command of the master device to the address of the slave device.

[0128] The master device transmits I2C data #1 to transmission chip #1. It can be understood that the master device writes the I2C data into storage space #2 of transmission chip #1. Correspondingly, transmission chip #1 reads storage space #2 to obtain I2C data #1.

[0129] S5201b. Transmission chip #1 transmits an ACK message (which is one example of the first feedback information) to the master device.

[0130] After obtaining I2C data #1 from the master device, transmission chip #1 transmits 1-bit feedback information #1 (which is one example of the first feedback information) to the master device based on a determination of whether I2C data #1 is sufficient for 8 bits. For example, the feedback information #1 may be an ACK message or a NACK message. When I2C data #1 is sufficient for 8 bits, transmission chip #1 transmits an ACK message to the master device. When I2C data #1 is less than 8 bits, transmission chip #1 transmits a NACK message to the master device.

[0131] After receiving the ACK message from transmission chip #1, the master device continues to transmit the next I2C data to transmission chip #1. …

[0132] S520Na: The master device transmits I2C data #N to transmission chip #1.

[0133] S520Nb: Transmission chip #1 sends an ACK message to the master device.

[0134] It should be noted that FIG. 9 is described by using only one example in which the feedback information #1 returned by the transmission chip #1 to the master device is an ACK message. However, this does not constitute a limitation to this embodiment of this application.

[0135] S530: Transmission chip #1 transfers N I2C data of the master device to transmission chip #2 (which is one example of the second transmission chip).

[0136] It is possible to understand that the N I2C data sent by transmission chip #1 to transmission chip #2 is carried in the long - distance transmission data packet.

[0137] When the amount of I2C data stored in memory space #2 is equal to N, transmission chip #1 transfers N I2C data to transmission chip #2 at one time. For the method by which transmission chip #1 determines whether the amount of I2C data stored in memory space #2 is equal to N, reference should be made to the above description in S430. For the sake of brevity, details are not repeatedly described in this specification.

[0138] S540: Transmission chip #2 sends I2C data to the slave device.

[0139] After receiving N I2C data from transmission chip #1, transmission chip #2 may store the N I2C data in memory space #3 (which is one example of the third memory space), and then sequentially send the N I2C data to the slave device.

[0140] S5401a: Transmission chip #2 sends I2C data #1 to the slave device.

[0141] S5401b: The slave device transmits feedback information #2 to the transmission chip #2 (which is one example of the second feedback information).

[0142] The feedback information #2 is used to indicate whether the reception of the I2C data #1 has been successful.

[0143] After receiving the I2C data #1 from the transmission chip #2, the slave device transmits 1-bit feedback information #2 to the transmission chip #2 based on the determination of whether the I2C data #1 is sufficient for 8 bits and the determination of whether the content is correct. For example, the feedback information #2 may be an ACK message or a NACK message. If the I2C data #1 is sufficient for 8 bits and its content is correct, the slave device transmits an ACK message to the transmission chip #2. If the I2C data #1 is smaller than 8 bits and / or the content is incorrect, the slave device transmits a NACK message to the transmission chip #2.

[0144] After receiving the feedback information #2 from the slave device, the transmission chip #2 stores the feedback information #2 in the storage space #4 and may continue to transmit the next I2C data to the slave device. …

[0145] S540Na: The transmission chip #2 transmits I2C data #N to the slave device.

[0146] S540Nb: The slave device transmits feedback information #2 to the transmission chip #2.

[0147] The feedback information #2 is used to indicate whether the reception of the I2C data #N has been successful.

[0148] S550: Transmission chip #2 generates feedback information #3 (which is one example of the third feedback information) based on the N pieces of received feedback information #2, and the feedback information #3 is used to indicate those N pieces of feedback information #2.

[0149] It can be understood that the feedback information #3 transmitted by transmission chip #2 to transmission chip #1 is carried in the long - distance transmission data packet.

[0150] When the amount of feedback information #2 stored in memory space #4 is equal to N, transmission chip #2 transmits feedback information #3 to transmission chip #1 based on the N pieces of feedback information #2. For the method by which transmission chip #2 determines whether the amount of feedback information #2 stored in memory space #4 is equal to N, reference should be made to the above description in S460. For the sake of brevity, details will not be repeatedly described in this specification.

[0151] It should be understood that FIG. 9 is only one example, showing that transmission chip #2 is triggered to transmit feedback information #3 to transmission chip #1 after the amount of feedback information #2 received by transmission chip #2 becomes equal to N. This should not constitute a limitation to this application. When the amount of received feedback information #2 is equal to M, transmission chip #2 may further transmit feedback information #3 to transmission chip #1 based on the M pieces of feedback information #2. M is a positive integer and M is not equal to N.

[0152] In some of the multiple implementations, when the received feedback information #2 is a NACK message, the transmission chip #2 may send the feedback information #3 to the transmission chip #1. Specifically, when all of the feedback information #2 received by the transmission chip #2 is an ACK message, the transmission chip #2 does not send the feedback information #3 to the transmission chip #1. The transmission chip #2 generates the feedback information #3 based on the received feedback information #2 only after receiving a NACK message, and then sends the feedback information #3 to the transmission chip #1.

[0153] In some of the other multiple implementations, when the amount of the feedback information #2 stored in the memory space #4 is equal to N, and at least one of the N feedback information #2 is a NACK message, the transmission chip #2 generates the feedback information #3 based on those N feedback information #2, and then sends the feedback information #3 to the transmission chip #1.

[0154] S560: The transmission chip #1 obtains those N feedback information #2 based on the received feedback information #3, and stores the feedback information #2 in the memory space #1.

[0155] It is possible to understand that the transmission chip #2 transmits the feedback information #3 to the transmission chip #1 only when at least one of the received multiple pieces of feedback information #2 is a NACK message. Therefore, before the transmission chip #1 receives the feedback information #3, all the messages stored in the memory space #1 (which is an example of one of the first storage spaces) of the transmission chip #1 are default ACK messages. After receiving the feedback information #3, the transmission chip #1 updates the ACK messages stored in the memory space #1 by default to the feedback information #2 obtained based on the feedback information #3. Further, after the master device reads the memory space #1, the transmission chip #1 returns its memory space #1 to the state where ACK messages are stored by default.

[0156] S570: The master device reads the memory space #1 of the transmission chip #1.

[0157] The time when the master device reads the memory space #1 is not limited in this embodiment of this application.

[0158] In one implementation, the master device may read the memory space #1 periodically.

[0159] For example, the master device may set the period for reading the memory space #1 according to the rule that the transmission chip #1 transmits I2C data to the transmission chip #2. For example, every time the master device receives N pieces of I2C data, the transmission chip #1 transmits those N pieces of I2C data to the transmission chip #2 at once. In this case, the master device may read the memory space #1 once every time it transmits 2N pieces of I2C data, or may read the memory space #1 once every time it transmits 3N pieces of I2C data.

[0160] In other implementations, the master device may read Memory Space #1 when determining that Memory Space #2 is in a write - prohibited state.

[0161] After Transmission Chip #1 receives the feedback information #3 from Transmission Chip #2, when the master device continues to write I2C data into Memory Space #2 of Transmission Chip #1, Memory Space #2 of Transmission Chip #1 stops receiving I2C data. That is, Memory Space #2 is set to a non - receivable state. When Memory Space #2 of Transmission Chip #1 stops receiving I2C data, Transmission Chip #1 feeds back a NACK message to the master device. Correspondingly, after receiving the NACK message fed back by Transmission Chip #1, the master device determines that Memory Space #2 is in a write - prohibited state. Further, the master device reads Memory Space #1.

[0162] If all of the feedback information #2 obtained by the master device by reading Memory Space #1 is an ACK message, that is, if the feedback information #2 is used to indicate that the reception of I2C data has been successful, the master device determines that an error has occurred in the I2C link between the master device and Transmission Chip #1. If at least one of the feedback information #2 obtained by the master device by reading Memory Space #1 is a NACK message, that is, if at least one of the feedback information is used to indicate that the reception of I2C data has failed, the master device determines that an error has occurred in the I2C link between Transmission Chip #2 and the slave device. Further, after determining the location of the link error, the master device re - transmits the corresponding I2C data according to a pre - set rule.

[0163] If all of the I2C data sent by the master device to the slave device has been transmitted, but it has not been determined whether the reception of the last I2C data was successful, the master device may periodically read memory space #1.

[0164] In this embodiment of this application, it should be understood that after the master device transmits 8-bit I2C data, it may determine that the received feedback information #1 is being returned by transmission chip #1. The feedback information #2 obtained by the master device by reading the memory space #1 of transmission chip #1 is the actual feedback information of the device.

[0165] If one of the feedback information #2 obtained by the master device by reading the memory space #1 is an ACK message, it is determined that the slave device has successfully received the I2C data corresponding to the feedback information #2. If one of the feedback information #2 obtained by the master device by reading the memory space #1 is a NACK message, it is determined that the slave device has failed to receive the I2C data corresponding to the feedback information #2, and then the master device re-transmits the I2C data corresponding to the feedback information #2 to the slave device.

[0166] In this embodiment of this application, in the process of the master device writing data to the slave device, the transmission chip #1 returns one piece of feedback information (i.e., feedback information #1) to the master device based on whether it has successfully received the I2C data. In this way, for transmission, the I2C interface between the master device and the transmission chip #1 may be continuously used, thereby improving the effective rate of I2C data transmission. In addition, the transmission chip #2 may transmit the actual feedback information of the slave device (i.e., feedback information #2) to the transmission chip #1. Furthermore, the transmission chip #1 may trigger the master device to obtain the actual feedback information of the slave device, ensuring that the master device can receive the actual feedback information from the slave device.

[0167] Referring to FIG. 10, the following description uses one example where the first device is a slave device and the second device is a master device to explain the data transmission method provided by these multiple embodiments of this application.

[0168] FIG. 10 is a schematic flowchart of a data transmission method compliant with the I2C protocol according to one embodiment of this application. The method 600 shown in FIG. 10 may include S601 to S615. The following description details these multiple steps.

[0169] S601: The master device sends a write command to the transmission chip #2 (which is one example of the second transmission chip).

[0170] When the master device sends a write command to transmission chip #2, the master device can understand that it writes the write command to the address of transmission chip #2. For example, the master device writes the write command to memory space #3 (which is an example of the third memory space) of transmission chip #2.

[0171] S602: Transmission chip #2 sends an ACK message to the master device.

[0172] After obtaining the write command from the master device, transmission chip #2 returns a 1-bit ACK message or a 1-bit NACK message to the master device based on whether the write command is sufficient for 8 bits and whether the content of the write command is correct. If the write command is sufficient for 8 bits and its content is correct, transmission chip #2 returns an ACK message to the master device. If the write command is smaller than 8 bits and / or the content is incorrect, transmission chip #2 returns a NACK message to the master device.

[0173] Furthermore, when the master device receives an ACK message from transmission chip #2, the master device starts to execute the next step. When the master device receives a NACK message from transmission chip #2, the master device retransmits the write command, that is, the master device retransmits the write command to transmission chip #2 until the master device receives an ACK message from transmission chip #2 and the master device starts to execute the next step.

[0174] S603: The master device sends read command #1 to transmission chip #2.

[0175] The master device can understand that it writes the read command #1 to the storage space #3 of the transmission chip #2. The read command #1 indicates the address of the slave device that the master device needs to read and the read flag.

[0176] S604: The transmission chip #2 sends an ACK message to the master device.

[0177] After obtaining the read command #1 from the master device, the transmission chip #2 returns a 1-bit ACK message or a 1-bit NACK message to the master device based on whether the read command #1 is sufficient in 8 bits. If the write command is sufficient in 8 bits, the transmission chip #2 returns an ACK message to the master device. If the write command is less than 8 bits, the transmission chip #2 returns a NACK message to the master device.

[0178] S605: The transmission chip #2 transfers the read command #1 to the transmission chip #1 (which is an example of one of the first transmission chips).

[0179] It can be understood that the read command #1 transferred by the transmission chip #2 to the transmission chip #1 is carried in the long-distance transmission data packet.

[0180] After obtaining the read command #1, the transmission chip #2 may determine that the master device has started a read operation, and then transfer the read command #1 to the transmission chip #1.

[0181] S606: The transmission chip #1 sends the read command #1 to the slave device.

[0182] S607: The slave device sends an ACK message to the transmission chip #1.

[0183] After receiving the read command #1 from the transmission chip #1, the slave device returns a 1-bit ACK message or a 1-bit NACK message to the transmission chip #1 based on whether the read command #1 is sufficient for 8 bits and whether the content is correct.

[0184] If the read command #1 is sufficient for 8 bits and its content is correct, the slave device returns an ACK message to the transmission chip #1. Next, the slave device starts the transmission of I2C data to the transmission chip #1.

[0185] If the read command #1 is smaller than 8 bits and / or its content is incorrect, the slave device returns a NACK message to the transmission chip #1. Further, after receiving the NACK message sent by the slave device, the transmission chip #1 transfers the NACK message to the transmission chip #2. Further, after receiving the NACK message from the transmission chip #1, the transmission chip #2 triggers the master device to read the storage space #3 of the transmission chip #2. In this case, since the transmission chip #2 has not received the I2C data from the transmission chip #1, that is, there is no I2C data in the storage space #3, the transmission chip #2 feeds back a NACK message to the master device. Further, based on the NACK message fed back by the transmission chip #2, the master device may determine that an I2C error has occurred between the transmission chip #1 and the slave device. Therefore, the master device restarts the read operation to the slave device.

[0186] In this embodiment of this application, the transmission chip #2 transfers the NACK message of the slave device corresponding to the read command #1 to the transmission chip #1, and further, when the master device reads the storage space #3, the transmission chip #1 feeds back the NACK message to the master device. In this way, the master device can obtain the actual feedback information of the slave device corresponding to the read command #1.

[0187] S608: The slave device transmits I2C data to the transmission chip #1.

[0188] The slave device transmits the I2C data in the storage space corresponding to the address indicated by the read command #1 to the transmission chip #1. The I2C data is the data that the slave device transmits to the master device. Hereinafter, for the sake of explanation, one example in which the slave device transmits N I2C data to the transmission chip #1 is used, and N is a positive integer.

[0189] S6081a: The slave device transmits I2C data #1 to the transmission chip #1.

[0190] S6081b: The transmission chip #1 transmits an ACK message to the slave device.

[0191] After receiving the I2C data #1 from the slave device, based on the determination of whether the I2C data #1 is sufficient for 8 bits, the transmission chip #1 transmits 1-bit feedback information #1 (one example of the first feedback information) to the slave device. For example, the feedback information #1 may be an ACK message or a NACK message.

[0192] When transmission chip #1 determines that the I2C data is less than 8 bits, i.e., when an error occurs during the reading of the data of the slave device, transmission chip #1 sends a NACK message to the slave device. In this case, transmission chip #1 may determine that an error has occurred in the I2C link between transmission chip #1 and the slave device, and then, transmission chip #1 restarts the reading process to the slave device, i.e., resends the read command #1 to the slave device. Further, after receiving the ACK message corresponding to the read command #1 of the slave device, transmission chip #1 continues to read the data of the slave device.

[0193] When I2C data #1 is sufficient for 8 bits, transmission chip #1 sends an ACK message to the slave device. After receiving the ACK message from transmission chip #1, the slave device continues to send the next I2C data to transmission chip #1. …

[0194] S608Na: The slave device sends I2C data #N to transmission chip #1.

[0195] S608Nb: Transmission chip #1 sends an ACK message to the slave device.

[0196] It should be understood that FIG. 10 is described by using only one example where the feedback information #1 returned by transmission chip #1 to the slave device is an ACK message. However, this does not constitute a limitation to this embodiment of this application.

[0197] S609: Transmission chip #1 transfers those N I2C data of the slave device to transmission chip #2.

[0198] It is possible to understand that the N I2C data transmitted from transmission chip #1 to transmission chip #2 are carried in a long-distance transmission data packet.

[0199] (One example with a second storage space) Storage space #2 When the amount of I2C data stored in the storage space is equal to N, transmission chip #1 transfers N I2C data to transmission chip #2 at once. For how transmission chip #1 determines whether the amount of I2C data stored in storage space #2 is equal to N, reference should be made to the above description in S430. For the sake of brevity, details will not be repeatedly described in this specification.

[0200] Correspondingly, after receiving the I2C data from transmission chip #1, transmission chip #2 stores the I2C data in storage space #3, and then waits for the master device to read the I2C data.

[0201] S610: The master device sends a read command #2 to transmission chip #2.

[0202] Before starting to read storage space #3 of transmission chip #2, the master device may first send a read command #2 to transmission chip #2, and the read command #2 is used to indicate the address of storage space #3 and the read flag.

[0203] The time for the master device to read storage space #3 is not limited in this embodiment of this application.

[0204] In one implementation, the master device may read storage space #3 periodically.

[0205] For example, the master device may set the period for reading the memory space #3 according to the rule that the transmission chip #1 transmits I2C data to the transmission chip #2. For example, every time the transmission chip #1 receives N I2C data from the slave device, the transmission chip #1 transmits N I2C data to the transmission chip #2 at once. In this case, the master device may read the memory space #3 at intervals of transmitting 2N I2C data, or may read the memory space #3 at intervals of transmitting 3N I2C data.

[0206] In other implementations, the master device may read the memory space #3 after the transmission chip #2 releases SCL.

[0207] In this case, the transmission chip #2 pulls down SCL low to a low level state before receiving I2C data from the transmission chip #1. After receiving the I2C data from the transmission chip #1, the transmission chip #2 releases SCL.

[0208] S611: The transmission chip #2 sends an ACK message to the master device.

[0209] After obtaining the read command #2 from the master device, the transmission chip #2 returns a 1-bit ACK message or a 1-bit NACK message to the master device based on whether the read command #2 is sufficient for 8 bits and whether the content of the read command #2 is correct. If the read command #2 is sufficient for 8 bits and its content is correct, the transmission chip #2 returns an ACK message to the master device. If the read command #2 is less than 8 bits and / or its content is incorrect, the transmission chip #2 returns a NACK message to the master device.

[0210] Furthermore, when the master device receives an ACK message from transmission chip #2, the master device starts reading the storage space #3 of transmission chip #2. When the master device receives a NACK message from transmission chip #2, the master device retransmits read command #2 to transmission chip #2 until the master device receives an ACK message from transmission chip #2, and then starts reading the storage space #3 of transmission chip #2.

[0211] S612: The master device reads the storage space #3 of transmission chip #2.

[0212] The master device sequentially reads the N I2C data stored in storage space #3.

[0213] S6121a: The master device reads I2C data #1.

[0214] S6121b: The master device transmits feedback information #2 (which is one example of the second feedback information) to transmission chip #2.

[0215] Feedback information #2 is used to indicate whether the reception of I2C data #1 was successful.

[0216] After reading I2C data #1 from transmission chip #2, the master device transmits 1-bit feedback information #2 to transmission chip #2 based on a determination of whether I2C data #1 is sufficient for 8 bits and whether the content is correct. For example, feedback information #2 may be an ACK message or a NACK message. If I2C data #1 is sufficient for 8 bits and its content is correct, the master device transmits an ACK message to transmission chip #2. If I2C data #1 is smaller than 8 bits and / or its content is incorrect, the master device transmits a NACK message to transmission chip #2.

[0217] Master device After receiving the feedback information #2 from

[0217] , the transmission chip #2 may store the feedback information #2 in the memory space #4. …

[0218] S612Na: The master device reads the I2C data #N.

[0219] S612Nb: The master device sends the feedback information #2 to the transmission chip #2.

[0220] The feedback information #2 is used to indicate whether the reception of the I2C data #N is successful.

[0221] Optionally, based on the N received feedback information #2, the transmission chip #2 generates the feedback information #3 (which is one example of the third feedback information), and sends the feedback information #3 to the transmission chip #1, and the feedback information #3 is used to indicate the N feedback information #2. Further, after obtaining the feedback information #2 based on the feedback information #3, Transmission chip #1 sends the feedback information #2 to the slave device. For the method by which the transmission chip #2 sends the feedback information #3 to the transmission chip #1, reference should be made to the above description of S550. For the sake of brevity, details are not repeatedly described in this specification.

[0222] S613: When the master device stops the read operation, it sends a NACK message to the transmission chip #2.

[0223] S614: The transmission chip #2 transfers the NACK message of the master device to the transmission chip #1.

[0224] It can be understood that the NACK message sent by the transmission chip #2 to the transmission chip #1 is carried in the long - distance transmission data packet.

[0225] Correspondingly, after receiving the NACK message from the transmission chip #2, the transmission chip #1 clears the I2C data stored in the memory space #2.

[0226] S615: The transmission chip #1 sends the NACK message from the transmission chip #2 to the slave device.

[0227] In this embodiment of this application, in the process of the master device reading the data of the slave device, the transmission chip #1 returns one piece of feedback information (i.e., feedback information #1) to the slave device based on whether the reception of the I2C data is successful. In this way, for transmission, it is possible to continuously use the I2C interface between the slave device and the transmission chip #1, thereby improving the actual transmission rate of the I2C data.

[0228] The above description details the data transmission method according to the I2C protocol provided by one embodiment of this application with reference to FIGS. 8 to 10. Hereinafter, with reference to FIGS. 11 to 14, the apparatuses provided by those multiple embodiments of this application will be described in detail.

[0229] FIG. 11 is a schematic block diagram of a transmission apparatus 700 according to one embodiment of this application. As shown in that figure, the transmission apparatus 700 may include a transceiver unit 710 and a processing unit 720.

[0230] In one possible design, the transmission apparatus 700 may correspond to the first transmission chip in the embodiment of the above method.

[0231] It should be understood that the transmission device 700 may include a unit configured to execute the method executed by the first transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. In addition, the plurality of units in the transmission device 700 and the other operations and / or functions described above are respectively used to implement a plurality of corresponding procedures executed by the first transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. It should be understood that the specific processes for each unit to execute the corresponding steps are described in detail in the embodiments of the above plurality of methods. For the sake of brevity, details are not described in this specification.

[0232] In other possible designs, the transmission device 700 may correspond to the second transmission chip in the embodiments of the above plurality of methods.

[0233] It should be understood that the transmission device 700 may include a unit configured to execute the method executed by the second transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. In addition, the plurality of units in the transmission device 700 and the other operations and / or functions described above are respectively used to implement a plurality of corresponding procedures executed by the second transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. It should be understood that the specific processes for each unit to execute the corresponding steps are described in detail in the embodiments of the above plurality of methods. For the sake of brevity, details are not described in this specification.

[0234] It should be understood that the transceiver unit 710 in the transmission device 700 may correspond to the transceiver unit 810 in the transmission device 800 shown in FIG. 12, and the processing unit 720 in the transmission device 700 may correspond to the processor 820 in the transmission device 800 shown in FIG. 12.

[0235] FIG. 12 is a schematic block diagram of a transmission device 800 according to one embodiment of this application. As shown in that figure, the transmission device 800 may include a processor 820 and may further include a transceiver 810 and a memory 830. The processor 820 is coupled to the memory 830 and is configured to execute instructions stored therein to control the transceiver 810 to transmit and / or receive signals.

[0236] It should be understood that the processor 820 and the memory 830 may be integrated into one processing device. The processor 820 is configured to execute program code stored in the memory 830 to implement the above-mentioned multiple functions. In a specific implementation, the memory 830 may alternatively be integrated into the processor 820 or may be independent of the processor 820.

[0237] In one possible design, the transmission device 800 may correspond to the first transmission chip in the above-mentioned multiple method embodiments.

[0238] Specifically, the transmission device 800 may include a unit configured to execute the method executed by the first transmission chip in method 400 in FIG. 8, method 500 in FIG. 9, and method 600 in FIG. 10. In addition, the multiple units in the transmission device 800 and the above-mentioned other operations and / or functions are respectively used to implement the multiple corresponding procedures executed by the first transmission chip in method 400 in FIG. 8, method 500 in FIG. 9, and method 600 in FIG. 10. It should be understood that the specific process of executing the corresponding steps by each unit is described in detail in the above-mentioned multiple method embodiments. For the sake of brevity, details are not described in this specification.

[0239] In one possible design, the transmission device 800 may correspond to the second transmission chip in the above-mentioned multiple method embodiments.

[0240] Specifically, the transmission device 800 may include a unit configured to execute the method executed by the second transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. In addition, a plurality of units in the transmission device 800 and the above other operations and / or functions are respectively used to implement a plurality of corresponding procedures executed by the second transmission chip among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. It should be understood that the specific process of executing the corresponding steps by each unit is described in detail in the embodiments of the above plurality of methods. For the sake of brevity, details are not described in this specification.

[0241] FIG. 13 is a schematic block diagram of a communication device 900 according to an embodiment of this application. As shown in the figure, the communication device 900 may include a transceiver unit 910 and a processing unit 920.

[0242] Specifically, the communication device 900 may include a unit configured to execute the method executed by the master device among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. In addition, a plurality of units in the communication device 900 and the above other operations and / or functions are respectively used to implement a plurality of corresponding procedures executed by the master device among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. It should be understood that the specific process of executing the corresponding steps by each unit is described in detail in the embodiments of the above plurality of methods. For the sake of brevity, details are not described in this specification. It should be understood that the transceiver unit 910 in the communication device 900 may correspond to the transceiver 1010 in the communication device 1000 shown in FIG. 14, and the processing unit 920 in the communication device 900 may correspond to the processor 1020 in the communication device 1000 shown in FIG. 14.

[0243] FIG. 14 is a schematic block diagram of a communication device 1000 according to one embodiment of this application. As shown in that figure, the communication device 1000 includes a processor 1020 and may further include a transceiver 1010. Optionally, the communication device 1000 further includes a memory 1030 configured to store instructions. The processor 1020 is coupled to the memory 1030 and is configured to execute the instructions stored therein to control the transceiver 1010 to transmit signals and / or receive signals.

[0244] It should be understood that the processor 1020 and the memory 1030 may be integrated as one processing device. The processor 1020 is configured to execute program code stored in the memory 1030 to implement the above-mentioned multiple functions. In a specific implementation, the memory 1030 may alternatively be integrated into the processor 1020 or may be independent of the processor 1020.

[0245] Furthermore, it should be understood that the transceiver 1010 may include a receiver (also referred to as a receiving machine) and a transmitter (also referred to as a transmitting machine). The transceiver may further include an antenna, and there may be one or more antennas.

[0246] Specifically, the communication device 1000 may include a unit configured to execute the method executed by the master device among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. In addition, a plurality of units in the communication device 1000 and the above other operations and / or functions are each used to implement a plurality of corresponding procedures executed by the master device among the method 400 in FIG. 8, the method 500 in FIG. 9, and the method 600 in FIG. 10. It should be understood that the specific process of executing the corresponding steps by each unit is described in detail in the embodiments of the above plurality of methods. For the sake of brevity, details are not described in this specification.

[0247] According to the method provided by the multiple embodiments of this application, this application further provides a computer program product. The computer program product includes computer program code. When the computer program code is executed by a computer, the computer is enabled to execute the method in any of the multiple embodiments shown in FIGS. 8 to 10.

[0248] According to the method provided by the multiple embodiments of this application, this application further provides a computer-readable medium. The computer-readable medium stores program code. When the program code is executed by a computer, the computer is enabled to execute the method in any of the multiple embodiments shown in FIGS. 8 to 10.

[0249] According to the method provided by the multiple embodiments of this application, this application further provides a system. The system includes a master device, the above first transmission chip, second transmission chip, and slave device.

[0250] In the above-described multiple embodiments, all or part of the above-described multiple embodiments can be implemented by using software, hardware, firmware, or any combination thereof. When implemented by using software, all or part of those multiple embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed by a computer, procedures or functions according to those multiple embodiments of this application are generated in whole or in part. The computer may be a general-purpose computer, a dedicated computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or may be transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired method (such as coaxial cable, optical fiber, or digital subscriber line (DSL), etc.) or by a wireless method (such as infrared, wireless, and microwave, etc.). The computer-readable storage medium may be any usable medium accessible by a computer, or may be a data storage device such as a server or a data center integrating one or more usable media. The usable medium may be a magnetic medium (such as a floppy disk, a hard disk, or a magnetic tape, etc.), an optical medium (such as a high-density digital video disc (DVD), etc.), or a semiconductor medium (such as a solid-state drive (SSD), etc.).

[0251] The network elements in the embodiments of the above-mentioned plurality of devices may exactly correspond to the network elements in the method embodiments. The corresponding units execute the corresponding steps. For example, a transceiver unit (transceiver) executes the receiving step or the transmitting step in the method embodiment, and a processing unit (processor) may execute other steps other than the transmitting step and the receiving step. Regarding the functions of a specific unit, reference should be made to the corresponding method embodiments. There may be one or more processors.

[0252] It should be understood that "a certain embodiment" or "an embodiment" mentioned throughout the specification does not mean that a plurality of specific features, configurations, or characteristics related to that embodiment are included in at least one embodiment of this application. Therefore, throughout the specification, "in a certain embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, these specific features, configurations, or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in the plurality of embodiments of this application, the sequence numbers of the above processes do not mean the execution order. The execution order of the plurality of processes needs to be determined based on the functions and internal logics of the plurality of processes, and should not be construed as any limitation to the implementation process of the plurality of embodiments of the present invention.

[0253] As used herein, terms such as "unit" and "system" are used to denote entities related to computers, hardware, firmware, combinations of hardware and software, software, or software being executed. For example, a component may be, but is not limited to, a process executed by a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As shown in the figures, both a computing device and an application executed by the computing device may be components. One or more components may be present within a process and / or an execution thread, a component may be located on one computer, and / or may be distributed between two or more computers. In addition, these components may be executed from various computer-readable media storing various data structures. These components may communicate based on signals having one or more data packets (such as data from two components that interact with other components, for example, within a local system, within a distributed system, and / or across a network such as the Internet that uses signals to interact with other systems).

[0254] One of ordinary skill in the art would recognize that the units, methods, and steps in the examples described with reference to the various embodiments disclosed herein can be implemented by electronic hardware or combinations of computer software and electronic hardware. Whether the various functions are executed by hardware or software depends on the particular application and design constraints of the various technical solutions. One of ordinary skill in the art may implement the functions described for each particular application using multiple different methods, but the implementation should not be construed as exceeding the scope of this application.

[0255] Those skilled in the art can clearly understand that, for the sake of a beneficial and concise description, they should refer to the corresponding processes in the embodiments of the above-mentioned multiple methods for the detailed operation processes of the above-mentioned systems, devices, and units, and details will not be repeatedly described herein.

[0256] In the multiple embodiments provided by this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the described device embodiments are merely one example. For example, the division of units is only a logical function division, and in actual implementation, other divisions may be possible. For example, multiple units or components may be combined or integrated into other systems, or some of the multiple functions may be ignored or not executed. In addition, the mutual connection, direct connection, or communication connection shown or described may be implemented by some of the multiple interfaces. The non-direct connection or communication connection between multiple devices or multiple units may be implemented in electrical form, mechanical form, or other forms.

[0257] The above-mentioned units described as individual parts may or may not be physically separated, and the multiple parts shown as multiple units may or may not be multiple physical units. They may be located in one place or may be distributed across multiple network units. Based on actual requirements, some or all of those multiple units may be selected to achieve the purposes of the multiple solution methods of those multiple embodiments.

[0258] In addition, a plurality of functional units in these multiple embodiments of this application may be integrated into one processing unit, or each of these multiple units may physically exist independently, or two or more units may be integrated into one unit.

[0259] When these multiple functions are implemented in the form of software functional units and are sold or used as independent products, these multiple functions may be stored in a computer-readable storage medium. Based on such an understanding, the multiple technical solution methods of this application, in essence, or the part that contributes to the prior art or some of these multiple technical solution methods may also be implemented in the form of software products. The computer software product is stored in a storage medium and contains several instructions, and some of these instructions are used to instruct a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the multiple steps of the multiple methods described in these multiple embodiments of this application. The above storage medium includes any medium such as a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk that can store program code.

[0260] The above description is only a plurality of specific implementations of this application and is not intended to limit the protection scope of this application. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application shall belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the invention described in the claims.

Claims

1. A data transmission method according to the Inter-Integrated Circuit (I2C) protocol, comprising: obtaining I2C data from a first device by a first transmission chip, wherein the I2C data is data that the first device transmits to a second device, and the first transmission chip corresponds to the first device; transmitting first feedback information to the first device by the first transmission chip, wherein the first feedback information is used to indicate whether the reception of the I2C data is successful; transferring the I2C data by the first transmission chip to a second transmission chip corresponding to the second device; receiving second feedback information from the second transmission chip by the first transmission chip, wherein the second feedback information is used to indicate whether the reception of the I2C data is successful; storing the second feedback information in a first storage space by the first transmission chip, wherein the first storage space is the storage space of the first transmission chip; The step of transferring, by the first transmission chip, the I2C data to the second transmission chip corresponding to the second device comprises: after the amount of at least one I2C data stored in a second storage space satisfies a preset condition, transferring, by the first transmission chip, the at least one stored I2C data to the second transmission chip, wherein the second storage space is the storage space of the first transmission chip, the at least one I2C data is data from the first device, and the at least one I2C data includes the I2C data; The preset condition is that the amount of the at least one I2C data stored in the second storage space is equal to N, where N is an integer greater than 1; After the step of receiving, by the first transmission chip, the second feedback information from the second transmission chip, the method further comprises: setting the second storage space to a write-prohibited state by the first transmission chip; A method.

2. The step of receiving, by the first transmission chip, second feedback information from the second transmission chip is: The step of receiving, by the first transmission chip, third feedback information from the second transmission chip, wherein the third feedback information is used to indicate second feedback information respectively corresponding to one or more I2C data including the I2C data, the method according to claim 1, comprising the step.

3. The step of obtaining, by the first transmission chip, I2C data from the first device is: The method according to claim 1, comprising the step of reading, by the first transmission chip, the I2C data stored in the second storage space.

4. The first device is a master device, and the second device is a slave device, or the first device is a slave device, and the second device is a master device, the method according to any one of claims 1 to 3.

5. A data transmission method according to the Inter-Integrated Circuit (I2C) protocol, comprising: Receiving, by a second transmission chip, I2C data from a first transmission chip corresponding to a first device, wherein the second transmission chip corresponds to a second device; Storing, by the second transmission chip, at least one I2C data from the first transmission chip in a third storage space, wherein the third storage space is a storage space of the second transmission chip, the at least one I2C data includes the I2C data, and an amount of the at least one I2C data is equal to N, and N is an integer greater than 1; Transmitting, by the second transmission chip, the I2C data to the second device; Receiving, by the second transmission chip, second feedback information from the second device, wherein the second feedback information is used to indicate whether reception of the I2C data is successful; Transmitting, by the second transmission chip, the second feedback information to the first transmission chip. The step of transmitting the second feedback information from the second transmission chip to the first transmission chip is as follows: The step of transmitting third feedback information from the second transmission chip to the first transmission chip, where the third feedback information is used to indicate second feedback information respectively corresponding to one or more I2C data including the I2C data. The step of transmitting third feedback information from the second transmission chip to the first transmission chip is as follows: When a preset trigger condition is satisfied, it includes the step of transmitting the third feedback information from the second transmission chip to the first transmission chip. The preset trigger condition is that the amount of the second feedback information satisfies a preset condition, and / or The preset trigger condition is that at least one of the one or more I2C data fails to be received. Method.

6. The method according to claim 5, wherein the first device is a master device and the second device is a slave device, or the first device is a slave device and the second device is a master device.

7. The third storage space is read at a period that is an integer multiple of the interval at which the first transmission chip transmits N I2C data. The method according to claim 5.

8. A data transmission method according to the Inter-Integrated Circuit (I2C) protocol, comprising: A step of transmitting I2C data from a master device to a first transmission chip, where the first transmission chip corresponds to the master device; A step of receiving, by the master device, first feedback information from the first transmission chip, where the first feedback information is used to indicate whether the I2C data has been successfully received; A step of reading, by the master device, a first storage space corresponding to the first transmission chip to obtain second feedback information, where the second feedback information is used to indicate whether the I2C data has been successfully received. The step of the master device reading the first storage space corresponding to the first transmission chip includes the step of the master device periodically reading the first storage space, and the period at which the master device reads the first storage space is an integer multiple of the interval at which the first transmission chip transmits N I2C data. Before the step of the master device reading the first storage space corresponding to the first transmission chip, the method further includes the step of the master device determining that the second storage space corresponding to the first transmission chip is in a write-prohibited state. Method.

9. A transmission device corresponding to a first device, including a processing unit and a transceiver unit, The transceiver unit is configured to obtain Inter-Integrated Circuit (I2C) data from the first device, and the I2C data is data that the first device transmits to a second device. The transceiver unit is further configured to transmit first feedback information to the first device, and the first feedback information is used to indicate whether the reception of the I2C data is successful. The transceiver unit is further configured to transfer the I2C data to a second transmission chip corresponding to the second device. The transceiver unit is further configured to receive second feedback information from the second transmission chip, and the second feedback information is used to indicate whether the reception of the I2C data is successful. The processing unit is configured to store the second feedback information in a first storage space, and the first storage space is the storage space of the transmission device. After the amount of at least one I2C data stored in the second storage space satisfies a preset condition, the transceiver unit is configured to transfer the at least one stored I2C data to the second transmission chip. The second storage space is the storage space of the transmission device. The at least one I2C data is data from the first device. The at least one I2C data includes the I2C data. The preset condition is that the amount of the at least one I2C data stored in the second storage space is equal to N, where N is an integer greater than 1. After the transceiver unit receives the second feedback information from the second transmission chip, the processing unit is further configured to set the second storage space to a write-prohibited state. Transmission device.

10. The transmission device according to claim 9, wherein the transceiver unit is configured to receive third feedback information from the second transmission chip, and the third feedback information is used to indicate second feedback information corresponding to one or more I2C data including the I2C data respectively.

11. The transmission device according to claim 9, wherein the transceiver unit is configured to read the I2C data stored in the second storage space.

12. A transmission device corresponding to a second device and including a transceiver unit and a processing unit, wherein the transceiver unit is configured to receive Inter-Integrated Circuit (I2C) data from a first transmission chip corresponding to a first device, the transceiver unit is further configured to transmit the I2C data to the second device, the transceiver unit is further configured to receive second feedback information from the second device, and the second feedback information is used to indicate whether the reception of the I2C data is successful, the transceiver unit is further configured to transmit the second feedback information to the first transmission chip. The processing unit is configured to store at least one I2C data from the first transmission chip in a third storage space, the third storage space being the storage space of the transmission device, the at least one I2C data including the I2C data, the amount of the at least one I2C data being equal to N, and N being an integer greater than 1. The transceiver unit is configured to transmit third feedback information to the first transmission chip, and the third feedback information is used to indicate second feedback information corresponding to one or more I2C data including the I2C data. When a preset trigger condition is satisfied, the transceiver unit is configured to transmit the third feedback information to the first transmission chip. The preset trigger condition is that the amount of the second feedback information satisfies a preset condition, and / or The preset trigger condition is that at least one of the one or more I2C data fails to be received. Transmission device.

13. The third storage space is read at intervals at which the first transmission chip transmits N I2C data or at intervals that are an integer multiple of such intervals. The transmission device according to claim 12.

14. A communication device including a transceiver unit and a processing unit, The transceiver unit is configured to transmit Inter-Integrated Circuit (I2C) data to a first transmission chip corresponding to the communication device. The transceiver unit is further configured to receive first feedback information from the first transmission chip, and the first feedback information is used to indicate whether the reception of the I2C data is successful. The transceiver unit is further configured to read a first storage space corresponding to the first transmission chip to obtain second feedback information, and the second feedback information is used to indicate whether the reception of the I2C data is successful. The transceiver unit is configured to periodically read the first storage space, and the period at which the transceiver unit reads the first storage space is an integral multiple of the interval during which the first transmission chip transmits N I2C data. The processing unit is configured to determine that the second storage space corresponding to the first transmission chip is in a write-prohibited state. Communication device.

15. A communication device including at least one processor, wherein the at least one processor is configured to execute a computer program stored in a memory, whereby the communication device implements the method according to any one of claims 1 to 8.

16. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a computing device, the computing device is enabled to implement the method according to any one of claims 1 to 8.

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