Communication device

Abstract

To suppress jitter in a multichannel communication device.SOLUTION: A communication device includes an oscillator, a signal generation circuit, an insulation element, and an output circuit. The oscillator is configured to output a carrier signal when an input signal externally input is at a first logic level. The signal generation circuit includes: a delay circuit; a first logic circuit having a first input end to receive an input signal and a second input end to receive an input signal via the delay circuit; a second logic circuit having a first input end connected to an output end of the first logic circuit and having a second input end to receive a carrier signal; a third logic circuit having a first input end to receive an input signal and a second input end connected to an output end of the second logic circuit; and a driving circuit to amplify a voltage output by the third logic circuit. The insulation element is connected to an output of the driving circuit. The output circuit receives a signal based on the output signal of the driving circuit via the insulation element and outputs the signal to the outside.SELECTED DRAWING: Figure 23

Description

Technical Field

[0001] Embodiments relate to a communication device.

Background Art

[0002] As an element included in a communication device that connects a high-voltage device and a low-voltage device, a galvanic insulation element is known. The galvanic insulation element is used to avoid noise intrusion and electric shock between the high-voltage device and the low-voltage device, and can transmit only signals while ensuring electrical insulation of the input and output. Examples of the medium used by the galvanic insulation element for signal transmission include light, an electric field, and a magnetic field.

[0003] For example, as a galvanic insulation element that uses an optical signal as a signal transmission medium, a photocoupler including a light-emitting diode (LED) as a light-emitting element and a photodiode (PD) as a light-receiving element is known. The photocoupler ensures electrical insulation by a resin provided between the LED and the PD. Therefore, the photocoupler has high reliability with respect to the insulation function.

[0004] However, when the communication device transmits a plurality of signals, the photocoupler needs to include a set of LEDs and PDs equal in number to the number of signals to be transmitted. When a plurality of LEDs and a plurality of PDs are mounted on one photocoupler, crosstalk may occur between the plurality of signals to be transmitted. In addition, mounting a plurality of LEDs and a plurality of PDs on the photocoupler may cause a decrease in reliability and an increase in cost due to complicated assembly.

[0005] On the other hand, a galvanic insulation element that uses an electric field or a magnetic field as a signal transmission medium can address the concerns of the above-mentioned photocoupler. A galvanic insulation element that uses an electric field or a magnetic field as a signal transmission medium is also called a digital isolator. When an electric field is used as the signal transmission medium, for example, a capacitive isolator with metal plates formed at both ends of an insulating layer is used. When a magnetic field is used as the signal transmission medium, for example, an isolation transformer with coils formed at both ends of an insulating layer is used. Mounting a plurality of capacitive isolators or isolation transformers on the same semiconductor substrate can be easily achieved. Therefore, a communication device that transmits multiple signals can suppress costs more than when using a photocoupler by using a digital isolator as a galvanic insulation element.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0007] Suppress jitter in a multi-channel communication device.

Means for Solving the Problems

[0008] The communication device according to the embodiment includes an oscillator, a first signal generation circuit, a second signal generation circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a first carrier signal and a second carrier signal when at least one of a first input signal and a second input signal input from the outside is at a first logic level. The first signal generation circuit includes a first delay circuit, a first logic circuit having the first input signal input to a first input terminal and the first input signal passed through the first delay circuit input to a second input terminal, a second logic circuit having an output terminal of the first logic circuit connected to the first input terminal and the first carrier signal input to the second input terminal, a third logic circuit having the first input signal input to the first input terminal and an output terminal of the second logic circuit connected to the second input terminal, and a first drive circuit that amplifies the voltage output by the third logic circuit. The second signal generation circuit includes a second delay circuit, a fourth logic circuit having the second input signal input to a first input terminal and the second input signal passed through the second delay circuit input to a second input terminal, a fifth logic circuit having an output terminal of the fourth logic circuit connected to the first input terminal and the second carrier signal input to the second input terminal, a sixth logic circuit having the second input signal input to the first input terminal and an output terminal of the fifth logic circuit connected to the second input terminal, and a second drive circuit that amplifies the voltage output by the sixth logic circuit. The first insulating element is connected to the output of the first drive circuit. The second insulating element is connected to the output of the second drive circuit. The first output circuit receives, via the first insulating element, a signal based on the output signal of the first drive circuit and outputs it to the outside. The second output circuit receives, via the second insulating element, a signal based on the output signal of the second drive circuit and outputs it to the outside.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus and a method for embodying the technical idea of the invention. The drawings are schematic or conceptual, and the dimensions, ratios, etc. of each drawing are not necessarily the same as those in reality. The technical idea of the present invention is not specified by the shape, structure, arrangement, etc. of the components.

[0011] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. The numbers after the characters constituting the reference numerals are referred to by the reference numerals including the same characters, and are used to distinguish between elements having the same configurations. Similarly, the characters after the numbers constituting the reference numerals are referred to by the reference numerals including the same numbers, and are used to distinguish between elements having the same configurations.

[0012] [1] First Embodiment The first embodiment relates to a communication device that transmits two signals using a galvanic insulating element, that is, a multi-channel communication device. Hereinafter, as an example, the case where an insulating transformer is used as the galvanic insulating element will be described for the communication device 1 according to the first embodiment.

[0013] [1-1] Configuration [1-1-1] Regarding the overall configuration of the communication device 1 FIG. 1 shows an example of the configuration of the communication device 1 according to the first embodiment. As shown in FIG. 1, the communication device 1 according to the first embodiment includes, for example, input circuits 10A and 10B, an RF (Radio Frequency) generator 20, signal generation circuits 30A and 30B, insulating elements 40A and 40B, reception circuits 50A and 50B, and output circuits 60A and 60B.

[0014] The input circuit 10 is used for inputting signals from an external device to the communication device 1 and includes, for example, a buffer circuit. Input signals IN1 and IN2 are input to the input circuits 10A and 10B, respectively, from an external device. Then, the input circuit 10A outputs an input signal Vin1 based on the input signal IN1 to the RF generator 20 and the signal generation circuit 30A. The input circuit 10B outputs an input signal Vin2 based on the input signal IN2 to the RF generator 20 and the signal generation circuit 30B.

[0015] The RF generator 20 is a signal generator such as a ring oscillator circuit, for example. The RF generator 20 generates and outputs a carrier signal CS based on the input signal Vin1 input from the input circuit 10A and the input signal Vin2 input from the input circuit 10B. The carrier signal CS is input to the signal generation circuits 30A and 30B.

[0016] The signal generation circuit 30 modulates the input signal Vin (modulation signal) input from the input circuit 10 using the carrier signal CS. Then, the signal generation circuit 30 outputs the modulated electrical signal (modulated signal) to the insulation element 40. Specifically, the signal generation circuit 30A modulates the input signal Vin1 and outputs it to the insulation element 40A. The signal generation circuit 30B modulates the input signal Vin2 and outputs it to the insulation element 40B.

[0017] The insulation element 40 is a galvanic insulation element used in the OOK (On-Off Keying) method and includes, for example, an insulation transformer. In the first embodiment, the insulation element 40 transmits signals using magnetic field coupling. The insulation element 40A transmits the electrical signal input from the signal generation circuit 30A to the receiving circuit 50A. The insulation element 40B transmits the electrical signal input from the signal generation circuit 30B to the receiving circuit 50B.

[0018] The receiving circuit 50 includes a demodulation circuit. The receiving circuit 50A detects and demodulates the electrical signal transmitted from the insulation element 40A and outputs it to the output circuit 60A. The receiving circuit 50B detects and demodulates the electrical signal transmitted from the insulation element 40B and outputs it to the output circuit 60B.

[0019] The output circuit 60 is used to output the signal transmitted through the insulation element 40 inside the communication device 1 to the outside and includes, for example, a buffer circuit. The output circuit 60A outputs the output signal OUT1 to an external device based on the signal input from the receiving circuit 50A. The output circuit 60B outputs the output signal OUT2 to an external device based on the signal input from the receiving circuit 50B.

[0020] In the configuration of the communication device 1 described above, the set of the input circuit 10A, the signal generation circuit 30A, the insulating element 40A, the reception circuit 50A, and the output circuit 60A corresponds to the first channel of the communication device 1. Similarly, the set of the input circuit 10B, the signal generation circuit 30B, the insulating element 40B, the reception circuit 50B, and the output circuit 60B corresponds to the second channel of the communication device 1. Thus, the communication device 1 according to the first embodiment is a two-channel communication device that can transmit two types of signals.

[0021] Further, in the communication device 1 according to the first embodiment, for example, the set of the input circuits 10A and 10B, the RF generator 20, and the signal generation circuits 30A and 30B is constituted by semiconductor elements mounted on the first substrate. On the other hand, the set of the insulating elements 40A and 40B, the reception circuits 50A and 50B, and the output circuits 60A and 60B is constituted by semiconductor elements mounted on a second substrate different from the first substrate. The circuit provided on the first substrate and the circuit provided on the second substrate are electrically connected using, for example, bonding wires.

[0022] Hereinafter, the set of the circuit mounted on the first substrate and the first substrate is referred to as chip CP1, and the set of the circuit mounted on the second substrate and the second substrate is referred to as chip CP2. For example, the circuit in chip CP1 is connected to the ground GND1, and the power supply voltage VDD1 is applied to the circuit in chip CP1. The circuit in chip CP2 is connected to the ground GND2, and the power supply voltage VDD2 is applied to the circuit in chip CP2. For example, one of the power supply voltages VDD1 and VDD2 corresponds to a high voltage system and the other corresponds to a low voltage system.

[0023] [1-1-2] Circuit Configuration of Communication Device 1 Hereinafter, an example of each circuit configuration of the RF generator 20, the signal generation circuit 30, and the insulating element 40 in the communication device 1 according to the first embodiment will be described in order.

[0024] (Regarding the Circuit Configuration of RF Generator 20) FIG. 2 shows an example of the circuit configuration of the RF generator 20 included in the communication device 1 according to the first embodiment. As shown in FIG. 2, the RF generator 20 in the first embodiment includes, for example, an OR circuit 21, a NAND circuit 22, and inverters 23, 24, and 25.

[0025] An input signal Vin1 output from the input circuit 10A is input to the first input terminal of the OR circuit 21. An input signal Vin2 output from the input circuit 10B is input to the second input terminal of the OR circuit 21. The output terminal of the OR circuit 21 is connected to the first input terminal of the NAND circuit 22. The output terminal of the NAND circuit 22 is connected to the input terminal of the inverter 23. The output terminal of the inverter 23 is connected to the input terminal of the inverter 24. The output terminal of the inverter 24 is connected to the input terminal of the inverter 25 and the second input terminal of the NAND circuit 22. The signal output from the inverter 25 corresponds to the carrier signal CS.

[0026] Here, a method for generating the carrier signal CS by the RF generator 20 will be briefly described. Hereinafter, the node corresponding to the output terminal of the NAND circuit 22 will be referred to as "N1". The node corresponding to the output terminal of the inverter 23 will be referred to as "N2". The node corresponding to the output terminal of the inverter 24 will be referred to as "N3".

[0027] When both of the input signals Vin1 and Vin2 are at the "L" level, the OR circuit 21 outputs a voltage at the "L" level. Then, the NAND circuit 22 having a voltage at the "L" level input to its first input terminal outputs a voltage at the "H" level. As a result, the voltages of the nodes N1, N2, and N3 become "H", "L", and "H" levels, respectively, and the inverter 25 outputs a voltage at the "L" level. Further, when the voltage of the node N3 is at the "H" level, since the input voltages of the first input terminal and the second input terminal of the NAND circuit 22 are different, the output of the NAND circuit 22 is maintained at the "H" level. Thereby, when both of the input signals Vin1 and Vin2 are at the "L" level, the carrier signal CS maintains the "L" level.

[0028] On the other hand, when at least one of the input signals Vin1 and Vin2 is at the "H" level, the OR circuit 21 outputs a voltage at the "H" level. Then, when a voltage at the "H" level is input to the first input terminal of the NAND circuit 22, for example, when the voltage at the second input terminal is at the "H" level, the NAND circuit 22 outputs a voltage at the "L" level. As a result, the voltages at nodes N1, N2, and N3 become "L", "H", and "L" levels respectively, and the inverter 25 outputs a voltage at the "H" level.

[0029] Also, when the voltage at node N3 becomes the "L" level, since a voltage at the "H" level is input to the first input terminal of the NAND circuit 22 and a voltage at the "L" level is input to the second input terminal, the output voltage of the NAND circuit 22 changes from the "L" level to the "H" level. As a result, the voltages at nodes N1, N2, and N3 become "H", "L", and "H" levels respectively, and the inverter 25 outputs a voltage at the "L" level. When at least one of the input signals Vin1 and Vin2 is at the "H" level, these operations are repeated, and the output of the carrier signal CS oscillates.

[0030] As described above, the RF generator 20 in the first embodiment can generate the carrier signal CS using the OR signal of the input signal Vin1 and the input signal Vin2. Note that the circuit configuration of the RF generator 20 described above is merely an example. The RF generator 20 may have other circuit configurations as long as it can generate the carrier signal CS based on at least one of the input signals Vin1 and Vin2 being at the "H" level.

[0031] (Regarding the circuit configuration of the signal generation circuit 30) FIG. 3 shows an example of the circuit configuration of the signal generation circuit 30 provided in the communication device 1 according to the first embodiment. As shown in FIG. 3, the signal generation circuit 30 in the first embodiment includes, for example, a signal generation unit 31 and a drive unit 32. The signal generation circuit 30 includes, for example, an AND circuit 311, a delay circuit 312, a NAND circuit 313, and an AND circuit 314. The drive unit 32 includes, for example, a drive circuit 321.

[0032] The input signal Vin (modulation signal) is input to the first input terminal of the AND circuit 311. The input signal Vind corresponding to the input signal Vin delayed via the delay circuit 312 is input to the second input terminal of the AND circuit 311. The delay circuit 312 is, for example, several inverters connected in series. Other circuits may be used as the delay circuit 312.

[0033] The output terminal of the AND circuit 311 is connected to the first input terminal of the NAND circuit 313. The carrier signal CS is input to the second input terminal of the NAND circuit 313. The input signal Vin is input to the first input terminal of the AND circuit 314. The output terminal of the NAND circuit 313 is connected to the second input terminal of the AND circuit 314. The AND circuit 314 outputs the modulated signal MS. The drive circuit 321 amplifies the modulated signal MS and outputs the output voltage Vout.

[0034] The signal generation circuit 30 in the first embodiment described above can modulate the input signal Vin based on the carrier signal CS. For example, the output voltage Vout of the signal generation circuit 30 becomes a voltage of the "L" level when the input signal Vin is at the "L" level, and becomes a voltage based on the carrier signal CS generated by the RF generator 20 when the input signal Vin is at the "H" level. Note that the circuit configuration of the signal generation circuit 30 described above is merely an example. The signal generation circuit 30 may have other circuit configurations as long as it can modulate the input signal Vin based on the carrier signal CS.

[0035] (Regarding the circuit configuration of the insulating element 40) FIG. 4 shows an example of the circuit configuration of the insulating element 40 provided in the communication device 1 according to the first embodiment. As shown in FIG. 4, the insulating element 40 in the first embodiment includes, for example, coils 41 and 42.

[0036] Coil 41 and coil 42 face each other with an insulator layer ISO therebetween. As the insulator layer ISO, an oxide film or polyimide may be used. An output voltage Vout is applied to one end of coil 41 by a signal generation circuit 30 in chip CP1. The other end of coil 41 is grounded by chip CP1, for example. One end of coil 42 is connected to a reception circuit 50. The other end of coil 42 is grounded by chip CP2, for example.

[0037] In the insulating element 40 in the first embodiment described above, a magnetic field coupling is formed between coil 41 and coil 42. Thereby, the output voltage Vout applied to coil 41 is transmitted to coil 42 by the magnetic field coupling, and the transmitted output voltage Vout is applied to the reception circuit 50. Note that the circuit configuration of the insulating element 40 described above is merely an example. The insulating element 40 may have another circuit configuration as long as it can transmit the output voltage Vout using magnetic field coupling.

[0038] [1-2] Operation [1-2-1] Regarding modulation of input signal A communication method using an isolation transformer or an isolation capacitor can improve efficiency by modulating an input signal to a high frequency band. As modulation methods of a digital isolator, an edge encoding method and an OOK (On Off Keying) method are known. The edge encoding method is advantageous from the viewpoint of current consumption during low-speed communication, and the OOK method is advantageous from the viewpoints of current consumption and transmission delay time during high-speed communication. The communication device 1 according to the first embodiment uses the OOK method.

[0039] FIG. 5 shows an example of the basic modulation operation of an input signal. As shown in FIG. 5, the input signal is a voltage of "L" level or "H" level and contains 1-bit information. When the input signal becomes the "H" level, the RF generator 20 is turned on, and when the input signal becomes the "L" level, the RF generator 20 is turned off. Since the RF generator 20 operates based on the input signal becoming the "H" level, the carrier signal oscillates during the period when the input signal is at the "H" level. The modulated signal is a signal generated based on the carrier signal during the period when the input signal is at the "H" level. Therefore, the modulated signal oscillates, for example, in the same manner as the carrier signal during the period when the input signal is at the "H" level.

[0040] [1-2-2] Regarding the operation of the communication device 1 FIG. 6 shows an example of a timing chart of the operation in the communication device 1 according to the first embodiment. "MSA" indicates the modulated signal corresponding to the input signal Vin1. "MSB" indicates the modulated signal corresponding to the input signal Vin2. (1) to (4) indicate the phases of the carrier signal CS when the input signal Vin transitions from the "L" level to the "H" level.

[0041] As shown in FIG. 6(1), when the input signal Vin1 becomes the "H" level with the input signal Vin2 at the "L" level, the RF generator 20 is turned on and the carrier signal CS oscillates. At this time, in the signal generation circuit 30A, the voltage at the first input terminal of the AND circuit 314 becomes the "H" level based on the input signal Vin1, and the voltage at the second input terminal of the AND circuit 314 becomes a level based on the carrier signal CS, the AND circuit 311, the delay circuit 312, and the NAND circuit 313.

[0042] Specifically, until the delay time td by the delay circuit 312 elapses, a voltage of "H" level is applied to the first input terminal of the AND circuit 311, and a voltage of "L" level is applied to the second input terminal. Therefore, a signal of "L" level is output. As a result, since the voltage at the first input terminal of the NAND circuit 313 becomes "L" level, the NAND circuit 313 inputs a voltage of "H" level to the second input terminal of the AND circuit 314 regardless of the state of the carrier signal CS. As a result, the output of the AND circuit 314 is maintained at "H" level.

[0043] On the other hand, after the delay time td elapses, voltages of "H" level are applied to each of the first input terminal and the second input terminal of the AND circuit 311. As a result, the AND circuit 311 outputs a signal of "H" level, and the voltage at the first input terminal of the NAND circuit 313 becomes "H" level. Since the carrier signal CS is oscillating, the NAND circuit 313 inputs an inverted signal of the carrier signal CS to the second input terminal of the AND circuit 314. As a result, the output of the AND circuit 314 oscillates based on the carrier signal CS.

[0044] As described above, the output of the AND circuit 314, that is, the modulated signal MSA, becomes "H" level based on, for example, the input signal Vin1 becoming "H" level, and then maintains the "H" level until the delay time td elapses. When the delay time td elapses, the modulated signal MSA oscillates based on the carrier signal CS. Then, when the input signal Vin1 becomes "L" level, the RF generator 20 is turned off, and the oscillation of the carrier signal CS and the oscillation of the modulated signal MSA stop.

[0045] As shown in FIG. 6(2), when the input signal Vin1 is at the “L” level and the input signal Vin2 becomes the “H” level, the RF generator 20 is turned on and the carrier signal CS oscillates. The operation of the signal generation circuit 30B at this time is the same as the operation of the signal generation circuit 30A in FIG. 6(1). In each of FIGS. 6(1) and (2), the carrier signal CS oscillates based on the input signal Vin that becomes the “H” level. That is, since the input signal Vin and the carrier signal CS are synchronized, the phase of the carrier signal CS becomes 0° when the input signal Vin transitions from the “L” level to the “H” level.

[0046] As shown in FIG. 6(3), when the input signal Vin1 becomes the “H” level while the input signal Vin2 is at the “H” level, the input signal Vin1 is modulated based on the already oscillating carrier signal CS. That is, the carrier signal CS of the RF generator 20 and the input signal Vin1 of the input circuit 10A are in an asynchronous relationship. For this reason, a shift can occur between the timing of the input signal Vin1 transitioning from the “L” level to the “H” level and the phase of the carrier signal CS. FIG. 6(3) shows the case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input.

[0047] Even in such a case, in the signal generation circuit 30A, the AND circuit 314 immediately outputs a voltage of the “H” level based on the input signal Vin1 becoming the “H” level. That is, the modulation signal MSA becomes the “H” level based on the input signal Vin1 becoming the “H” level. Then, after the delay time td has elapsed, the modulation signal MSA oscillates based on the carrier signal CS.

[0048] After each of the input signals Vin1 and Vin2 reaches the "H" level, only the input signal Vin2 changes to the "L" level. In this case, based on the transition of the input signal Vin2 from the "H" level to the "L" level, the oscillation of the modulated signal MSB stops. On the other hand, since the input signal Vin1 maintains the "H" level, the RF generator 20 remains in the on state. That is, during the period when any of the input signals Vin is at the "H" level, the RF generator 20 maintains the state of oscillating the carrier signal CS.

[0049] As shown in FIG. 6(4), when the input signal Vin2 reaches the "H" level while the input signal Vin1 is at the "H" level, the input signal Vin2 is modulated based on the already oscillating carrier signal CS. That is, the carrier signal CS of the RF generator 20 and the input signal Vin2 of the input circuit 10B are in an asynchronous relationship. Similar to FIG. 6(3), FIG. 6(4) shows the case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input.

[0050] Even in such a case, in the signal generation circuit 30B, the AND circuit 314 immediately outputs a voltage of the "H" level based on the input signal Vin2 reaching the "H" level. That is, the modulated signal MSB becomes the "H" level based on the input signal Vin2 reaching the "H" level. Then, after the delay time td has elapsed, the modulated signal MSB oscillates based on the carrier signal CS.

[0051] Then, after each of the input signals Vin1 and Vin2 becomes the “H” level again, only the input signal Vin1 changes to the “L” level. In this case, based on the transition of the input signal Vin1 from the “H” level to the “L” level, the oscillation of the modulated signal MSA stops. On the other hand, since the input signal Vin2 maintains the “H” level, the RF generator 20 remains in the on state. Then, when the input signal Vin2 becomes the “L” level, the oscillation of the modulated signal MSB stops. Further, when each of the input signals Vin1 and Vin2 becomes the “L” level, the RF generator 20 turns off, so the carrier signal CS becomes the “L” level.

[0052] As described above, in the communication device 1 according to the first embodiment, based on the input signal Vin becoming the “H” level, the corresponding modulated signal MS immediately becomes the “H” level. Then, after the delay time td has elapsed, that is, after a pulse of the delay time td has been applied, the modulated signal MS becomes a pulse based on the carrier signal CS.

[0053] [1-3] Effects of the First Embodiment According to the communication device 1 according to the first embodiment described above, jitter in a communication device using one RF generator can be suppressed. Hereinafter, the details of the effects in the communication device 1 according to the first embodiment will be described.

[0054] As a modulation method of a communication device using the OOK method, a method of using an AND signal of an RF carrier (for example, the carrier signal CS) and an input signal is known. When the communication device is multi-channel, it is preferable that the RF generator for generating the RF carrier is provided for each channel. On the other hand, providing a plurality of RF generators may lead to an increase in power consumption and an increase in chip area. Therefore, in a multi-channel communication device, in order to suppress power consumption, a method of sharing one RF generator among a plurality of channels has been considered.

[0055] Here, as a comparative example of the first embodiment, a case where a communication device having a plurality of inputs uses one RF generator 20 and uses, as a modulated signal MS, a signal obtained by performing an AND operation on an input signal Vin and a carrier signal CS will be described. Briefly stated, the communication device according to the comparative example of the first embodiment has a configuration in which, for example, the AND circuit 311, the delay circuit 312, and the NAND circuit 313 are omitted from the signal generation circuit 30 described in FIG. 3, and the RF generator 20 is directly connected to the second input terminal of the AND circuit 314.

[0056] FIG. 7 shows an example of a timing chart of the operation in the communication device according to the comparative example of the first embodiment, and illustrates a case where the input signals Vin1 and Vin2 become the "H" level at the same timing as in FIG. 6. When the RF generator 20 operates using the AND signal of the input signals Vin1 and Vin2, modulated signals MSA and MSB as shown in FIG. 7 are obtained.

[0057] As shown in FIG. 7, when either one of the input signals Vin1 and Vin2 changes from the "L" level state to the "H" level, for example, the modulated signal MSA or MSB oscillates in the same manner as the carrier signal CS. Also, as shown in FIGS. 7(1) and (2), when the input signal Vin and the carrier signal CS are synchronized, the phase of the carrier signal CS at the timing when the input signal Vin transitions from the "L" level to the "H" level is 0°.

[0058] On the other hand, as shown in FIGS. 7(3) and (4), when one input signal Vin is at the "H" level and the other input signal Vin transitions from the "L" level to the "H" level, the input signal Vin and the carrier signal CS become asynchronous. In this case, a deviation may occur between this timing and the phase of the carrier signal CS based on the timing when the input signal Vin transitions from the "L" level to the "H" level. FIG. 7(3) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin1 is input, and FIG. 7(4) shows a case where the phase of the carrier signal CS is 90° when the input signal Vin2 is input.

[0059] In the communication device 1 according to the comparative example of the first embodiment, when the transition timing of the input signal Vin is synchronized with the carrier signal CS, that is, when the input signal Vin is input when the RF generator 20 is in the off state, the rising waveform of the carrier signal CS and the rising waveform of the modulated signal MS can be made substantially the same. In this case, the communication device 1 can make the waveforms of the output signals OUT1 and OUT2 substantially the same.

[0060] On the other hand, in the communication device 1 according to the comparative example of the first embodiment, when the input signal Vin is input when the RF generator 20 is in the on state, the transition timing of the input signal Vin cannot be synchronized with the carrier signal CS, so a shift can occur between the rising edge of the input signal Vin and the phase of the carrier signal CS. When the rising edge of the input signal Vin and the phase of the carrier signal CS are shifted, the voltage value of the carrier signal CS input to the AND circuit 314 varies, and the shape of the rising waveform of the modulated signal MS becomes random. Such variations in the shape of the rising waveform of the modulated signal MS are reflected in the variations in the waveforms of the output signals OUT1 and OUT2. Then, the change in the rising waveform of the modulated signal MS based on the operation timing of the input signal Vin and the carrier signal CS becomes a factor in the generation of jitter and the degradation of the operation stability of the receiving circuit 50.

[0061] In contrast, the communication device 1 according to the first embodiment uses the signal generation circuit 30 having the delay circuit 312 for modulating the input signal Vin. Briefly stated, the communication device 1 according to the first embodiment includes an AND circuit 311 to which the input signal Vin is input at the first input terminal and the input signal Vin via the delay circuit 312 is input at the second input terminal, and a NAND circuit 313 to which the output of the AND circuit 311 is connected at the first input terminal, the output of the RF generator 20 is connected at the second input terminal, and the output terminal is connected to the second input terminal of the AND circuit 314.

[0062] In the signal generation circuit 30 according to the first embodiment, when the input signal Vin becomes the "H" level, the AND circuit 314 sets the modulated signal MS to the "H" level regardless of the state of the carrier signal CS. Also, the RF generator 20 becomes turned on with the input of the input signal Vin. On the other hand, the input to the AND circuit 314 of the signal oscillated based on the carrier signal CS is delayed by the AND circuit 311, the delay circuit 312, and the NAND circuit 313. For this reason, the modulated signal MS is maintained at the "H" level until the delay time td by the delay circuit 312 elapses after the input signal Vin becomes the "H" level. Then, when the delay time td elapses, the output of the AND circuit 311 becomes the "H" level, and the NAND circuit 313 outputs the signal oscillated based on the carrier signal CS. As a result, the input signal Vin is modulated based on the carrier signal CS when the delay time td elapses after becoming the "H" level.

[0063] As described above, in the communication device 1 according to the first embodiment, the modulated signal MS is set to the "H" level based on the input signal Vin regardless of whether the RF generator 20 is in the on state or not. That is, in the communication device 1 according to the first embodiment, unlike the comparative example, the rising waveform of the modulated signal MS is the same in each of the case where the input signal Vin and the carrier signal CS are synchronized and the case where they are asynchronous.

[0064] Thereby, in the communication device 1 according to the first embodiment, the variation in the rising of the modulated signal MS is suppressed, so the variation in the waveforms of the output signals OUT1 and OUT2 is suppressed. And since the communication device 1 according to the first embodiment can input the signal oscillated based on the carrier signal CS to the AND circuit 314 after the elapse of the delay time td by the delay circuit 312, OOK - type communication can be executed in the same way as in the comparative example.

[0065] As a result, the communication device 1 according to the first embodiment can suppress the jitter of the output signal OUT and stabilize the operation of the receiving circuit 50. Therefore, the communication device 1 according to the first embodiment can transmit a high-quality signal using one RF carrier generation circuit in a digital isolator that transmits signals using the OOK method in a multi-channel configuration. In addition, since the communication device 1 according to the first embodiment can operate a plurality of channels with only one RF generator 20, it is possible to suppress power consumption and reduce the chip area.

[0066] In addition, as described above, the communication device 1 according to the first embodiment synchronously uses the carrier signals CS related to the respective insulating devices. Therefore, in the communication device 1 according to the first embodiment, the phases of the respective insulating devices may be adjusted. By adjusting the phases of the respective insulating devices, the communication device 1 according to the first embodiment can suppress EMI (Electro Magnetic Interference).

[0067] [1-4] Modification Example of the First Embodiment The communication device 1 according to the first embodiment described above can be variously modified. Hereinafter, differences from the first embodiment will be described for the first modification example, the second modification example, and the third modification example of the first embodiment.

[0068] [1-4-1] First Modification Example of the First Embodiment FIG. 8 shows an example of the configuration of the communication device 1 according to the first modification example of the first embodiment. As shown in FIG. 8, in the communication device 1 according to the first modification example of the first embodiment, the combination of the circuits included in the chip CP1 and the circuits included in the chip CP2 is different from that of the first embodiment.

[0069] Specifically, in the communication device 1 according to the first modification example of the first embodiment, the sets of the input circuits 10A and 10B, the RF generator 20, the signal generation circuits 30A and 30B, and the insulating elements 40A and 40B are mounted on the chip CP1. On the other hand, the sets of the receiving circuits 50A and 50B and the output circuits 60A and 60B are mounted on the chip CP2.

[0070] Thus, in the communication device 1, the insulating elements 40A and 40B may be mounted on the chip CP1 instead of the chip CP2. The communication device 1 can obtain the same effects as those in the first embodiment regardless of whether the insulating elements 40A and 40B are mounted on either of the chips CP1 and CP2. In this way, the method of the communication device 1 in which one insulating element 40 is provided for each channel and one insulating element 40 is mounted on either the chip CP1 or CP2 is also called the single insulation method.

[0071] [1-4-2] Second Modification of the First Embodiment FIG. 9 shows an example of the configuration of the communication device 1 according to the second modification of the first embodiment. As shown in FIG. 9, the insulating elements 40A and 40B may be mounted on both of the chips CP1 and CP2.

[0072] Specifically, in the communication device 1 according to the second modification of the first embodiment, the sets of the input circuits 10A and 10B, the RF generator 20, the signal generation circuits 30A and 30B, and the insulating elements 40A-1 and 40B-1 are mounted on the chip CP1. On the other hand, the sets of the insulating elements 40A-2 and 40B-2, the reception circuits 50A and 50B, and the output circuits 60A and 60B are mounted on the chip CP2.

[0073] Then, the insulating elements 40A-1 and 40B-2 are connected in series between the signal generation circuit 30A and the reception circuit 50A. The insulating elements 40B-1 and 40B-2 are connected in series between the signal generation circuit 30B and the reception circuit 50B. In other words, between the signal generation circuit 30 in the chip CP1 and the reception circuit 50 in the chip CP2, the insulating element 40 of the chip CP1 and the insulating element 40 of the chip CP2 are connected in series. In this way, the method of the communication device 1 in which two insulating elements 40 are provided for each channel and the insulating elements 40 are mounted on both of the chips CP1 and CP2 is also called the double insulation method.

[0074] [1-4-3] Third Modification of the First Embodiment Figure 10 shows an example of the configuration of the communication device 1 according to the third modification of the first embodiment. As shown in Figure 10, the communication device 1 according to the third modification of the first embodiment has a configuration in which input circuits 10C and 10D, signal generation circuits 30C and 30D, insulating elements 40C and 40D, reception circuits 50C and 50D, and output circuits 60C and 60D are added to the communication device 1 according to the first embodiment.

[0075] Input signals IN3 and IN4 are respectively input to the input circuits 10C and 10D from an external device. Then, the input circuits 10C and 10D respectively output input signals Vin3 and Vin4. The input signal Vin3 is input to the RF generator 20 and the signal generation circuit 30C. The input signal Vin4 is input to the RF generator 20 and the signal generation circuit 30D.

[0076] In the RF generator 20 in the third modification of the first embodiment, although not shown in the figure, input signals Vin1, Vin2, Vin3, and Vin4 are respectively input to the first input terminal, the second input terminal, the third input terminal, and the fourth input terminal of the OR circuit 21. Then, the RF generator 20 in the third modification of the first embodiment generates and outputs a carrier signal CS based on the input signals Vin1, Vin2, Vin3, and Vin4. Other configurations and operations of the RF generator 20 in the third modification of the first embodiment are the same as those in the first embodiment.

[0077] The signal generation circuit 30C modulates the input signal Vin3 and outputs it to the insulating element 40C. The signal generation circuit 30D modulates the input signal Vin4 and outputs it to the insulating element 40D. The insulating element 40C transmits the electrical signal input from the signal generation circuit 30C to the reception circuit 50C. The insulating element 40D transmits the electrical signal input from the signal generation circuit 30D to the reception circuit 50D.

[0078] The receiving circuit 50C demodulates the electrical signal transmitted from the insulating element 40C and outputs it to the output circuit 60C. The receiving circuit 50D demodulates the electrical signal transmitted from the insulating element 40D and outputs it to the output circuit 60D. The output circuit 60C outputs the output signal OUT3 to an external device based on the signal input from the receiving circuit 50C. The output circuit 60D outputs the output signal OUT4 to an external device based on the signal input from the receiving circuit 50D. Other configurations of the communication device 1 according to the third modification of the first embodiment are the same as those of the first embodiment.

[0079] As described above, the communication device 1 according to the third modification of the first embodiment includes four sets (channels) of an input circuit 10, a signal generation circuit 30, an insulating element 40, a receiving circuit 50, and an output circuit 60. And one RF generator 20 is shared by the signal generation circuits 30 included in each channel. In this way, the RF generator 20 in the first embodiment may be shared among four channels, or may be shared by N (N is an integer of 3 or more) channels. The communication device 1 can obtain the same effects as those of the first embodiment by operating the RF generator 20 based on the OR signal of N input signals.

[0080] [2] Second Embodiment The communication device 2 according to the second embodiment has a configuration in which the signal generation circuit 30 generates and outputs a differential signal. Hereinafter, differences from the first embodiment in the communication device 2 according to the second embodiment will be described.

[0081] [2-1] Configuration FIG. 11 shows an example of the circuit configuration of the signal generation circuit 30 provided in the communication device 2 according to the second embodiment. As shown in FIG. 11, the signal generation circuit 30 in the second embodiment has a configuration in which an inverter 315 and an AND circuit 316 are added to the signal generation unit 31, and the drive circuit 321 of the drive unit 32 is replaced with transistors 322, 323, 324, and 325, and a current source 326, as compared with the signal generation circuit 30 in the first embodiment.

[0082] The input terminal of the inverter 315 is connected to the output terminal of the NAND circuit 313. The input signal Vin is input to the first input terminal of the AND circuit 316. The output terminal of the inverter 315 is connected to the second input terminal of the AND circuit 316. The AND circuits 314 and 316 output the modulated signals MS1 and MS2, respectively. The modulated signals MS1 and MS2 are in a complementary relationship, for example, corresponding to signals in the positive phase and the inverted phase, respectively.

[0083] The transistors 322 and 323 are, for example, P-type MOS transistors. The power supply voltage VDD1 is applied to the respective sources of the transistors 322 and 323. The gate of the transistor 322 is connected to the output terminal of the AND circuit 316. The gate of the transistor 323 is connected to the output terminal of the AND circuit 314.

[0084] The transistors 324 and 325 are, for example, N-type MOS transistors. The drain of the transistor 324 is connected to the drain of the transistor 322. The drain of the transistor 325 is connected to the drain of the transistor 323. The gate of the transistor 324 is connected to the output terminal of the AND circuit 316. The gate of the transistor 325 is connected to the output terminal of the AND circuit 314.

[0085] The input terminal of the current source 326 is connected to the respective sources of the transistors 324 and 325. The output terminal of the current source 326 is connected to the ground GND1. Thereby, the current source 326 maintains the sum of the current through the transistors 322 and 324 and the current through the transistors 323 and 325 to be constant.

[0086] In the signal generation circuit 30 according to the second embodiment described above, the output current Iout1 is output from the node between the transistors 323 and 325, and the output current Iout2 is output from the node between the transistors 322 and 324. The output currents Iout1 and Iout2 correspond to a differential signal, and the differential signal is input to the insulating element 40.

[0087] In other words, the signal generation unit 31 of the signal generation circuit 30 outputs a differential output voltage based on the input signal Vin from the input circuit 10 and the carrier signal CS from the RF generator 20. Then, the driving unit 32 of the signal generation circuit 30 transmits the differential output voltage to the insulating element 40. In the second embodiment, as a typical example for driving an insulating transformer, the case where the driving unit 32 of the signal generation circuit 30 is of an H-bridge type with current limiting is illustrated.

[0088] FIG. 12 shows an example of the circuit configuration of the insulating element 40 provided in the communication device 2 according to the second embodiment. As shown in FIG. 12, the insulating element 40 in the second embodiment differs from that in the first embodiment in the connection of the coils 41 and 42 and the like.

[0089] Specifically, an output current Iout1 is supplied to one end of the coil 41 by the signal generation circuit 30 in the chip CP1. An output current Iout2 is supplied to the other end of the coil 41 by the signal generation circuit 30 in the chip CP1. One end and the other end of the coil 42 are connected to the reception circuit 50.

[0090] In the insulating element 40 in the second embodiment described above, a magnetic field coupling is formed between the coil 41 and the coil 42 in the same manner as in the first embodiment. Specifically, such an insulating transformer generates a magnetic field when a current is input. The direction of this magnetic field changes by switching between the path in which the transistors 323 and 324 in the signal generation circuit 30 are turned on and a current flows and the path in which the transistors 322 and 325 in the signal generation circuit 30 are turned on and a current flows.

[0091] As a result, the voltage based on the output currents Iout1 and Iout2 applied to the coil 41 is transmitted to the coil 42 by magnetic field coupling, and the transmitted voltage is applied to the receiving circuit 50. In other words, the insulating element 40 can transmit the modulated signal based on the principle of electromagnetic induction between the coil 41 and the coil 42 and apply a voltage to the receiving circuit 50. Then, the receiving circuit 50 demodulates the voltage based on the voltages at one end and the other end of the coil 42 and outputs it to the output circuit 60. Other configurations of the communication device 2 according to the second embodiment are the same as those of the first embodiment.

[0092] [2-2] Operation FIG. 13 shows an example of a timing chart of the operation in the communication device 2 according to the second embodiment, and illustrates the case where the input signals Vin1 and Vin2 become the "H" level at the same timing as in FIG. 6. "MS1A" and "MS2A" respectively indicate the modulated signal MS in the same phase and the modulated signal MS in the opposite phase with respect to the input signal Vin1. "MS1B" and "MS2B" respectively indicate the modulated signal MS in the same phase and the modulated signal MS in the opposite phase with respect to the input signal Vin2.

[0093] As shown in FIG. 13, in the second embodiment, the modulated signal MS1A in the same phase with respect to the input signal Vin1 and the modulated signal MS1B in the same phase with respect to the input signal Vin2 change in the same manner as the modulated signals MSA and MSB described in the first embodiment, respectively. On the other hand, the modulated signal MS2A in the opposite phase with respect to the input signal Vin1 and the modulated signal MS2B in the opposite phase with respect to the input signal Vin2 become the inverted signals of the modulated signals MS1A and MS1B, respectively.

[0094] Briefly stated, the AND circuit 314 corresponding to the positive phase operates in the same manner as the AND circuit 314 of the first embodiment. The AND circuit 316 corresponding to the negative phase has the input signal Vin input to its first input terminal, and a signal obtained by inverting the output of the NAND circuit 313 by the inverter 315 input to its second input terminal. That is, the same signal is input to the first input terminal of the AND circuit 314 and the first input terminal of the AND circuit 316. On the other hand, inverted signals are input to the second input terminal of the AND circuit 314 and the second input terminal of the AND circuit 316. As a result, the AND circuit 316 outputs an inverted signal of the AND circuit 314.

[0095] Also, in the communication device 2 according to the second embodiment, when the input signal Vin is at the "L" level, each of the AND circuits 314 and 316 outputs a signal at the "L" level. Then, in the driving unit 32 of the signal generation circuit 30, the current path between the power supply and the ground is interrupted. As a result, the driving unit 32 of the signal generation circuit 30 stops applying a voltage to the insulating element 40. Other operations of the communication device 2 according to the second embodiment are the same as those of the first embodiment.

[0096] [2-3] Effects of the Second Embodiment When the insulating element 40 is driven by an H-bridge circuit as in the communication device 2 according to the second embodiment, a differential signal is required. However, when the input signal Vin is at the "L" level, applying current and voltage to the insulating element 40 is not preferable because it causes an increase in power consumption and generation of noise.

[0097] In contrast, the communication device 2 according to the second embodiment sets both the positive-phase voltage of the modulated signal (i.e., the modulated signal MS1) and the negative-phase voltage of the modulated signal (i.e., the modulated signal MS2) to the "L" level when the input signal Vin is at the "L" level. Thereby, the communication device 2 according to the second embodiment can suppress power consumption and noise when driving the insulating element 40 by an H-bridge circuit.

[0098] Furthermore, similar to the first embodiment, the communication device 2 according to the second embodiment can make the rising waveform of the positive-phase modulated signal MS1 constant regardless of whether the input signal Vin and the carrier signal CS are synchronized. Also, since the modulated signal MS2 for driving the H-bridge circuit is the inverted signal of the modulated signal MS1, it is at the "L" level when the input signal Vin becomes the "H" level. Therefore, noise generation can also be suppressed in the modulated signal MS2. As a result, the communication device 2 according to the second embodiment can suppress the jitter of the output signal by the signal generation circuit 30 and improve the stability of the operation.

[0099] [2-4] Modification Example of the Second Embodiment The communication device 2 according to the second embodiment can be variously modified. For example, the signal generation circuit 30 may have a circuit configuration that sets the modulated signals MS1 and MS2 to the "H" level when the input signal Vin is at the "L" level. In this case, for example, each of the AND circuits 314 and 316 is replaced with a NAND circuit. Even in such a case, the communication device 2 can obtain the same effects as the second embodiment.

[0100] Also, the communication device 2 according to the second embodiment can be combined with the third modification example of the first embodiment. FIG. 14 shows an example of the circuit configuration of the insulating element 40 provided in the communication device 2 according to the modification example of the second embodiment. As shown in FIG. 14, the insulating element 40 in the modification example of the second embodiment has a configuration in which the coils 41 and 42 in the second embodiment are replaced with capacitors 43 and 44.

[0101] Specifically, an output current Iout1 is applied to one electrode of the capacitor 43 by the signal generation circuit 30 in the chip CP1. The other electrode of the capacitor 43 is connected to one end of the reception circuit 50. An output current Iout2 is supplied to one electrode of the capacitor 44 by the signal generation circuit 30 in the chip CP1. The other electrode of the capacitor 44 is connected to the other end of the reception circuit 50. In this case, each of the insulators provided between one electrode and the other electrode of the capacitor 43 and the insulators provided between one electrode and the other electrode of the capacitor 44 corresponds to the insulator layer ISO.

[0102] In the insulating element 40 in the modification of the second embodiment, an electric field coupling is formed between one electrode and the other electrode of the capacitor 43 and between one electrode and the other electrode of the capacitor 44. As a result, the voltage based on the output current Iout1 supplied to one electrode of the capacitor 43 is transmitted to the other electrode of the capacitor 43 by the electric field coupling, and the transmitted output voltage Vout is applied to one end of the reception circuit 50. Similarly, the voltage based on the output current Iout2 supplied to one electrode of the capacitor 44 is transmitted to the other electrode of the capacitor 44 by the electric field coupling, and the transmitted output voltage Vout is applied to the other end of the reception circuit 50.

[0103] Thus, the insulating element 40 used in the communication device 2 according to the second embodiment may be an insulating capacitor instead of an insulating transformer. The communication device 2 can obtain the same effects as those of the second embodiment even when an insulating capacitor is used as the insulating element 40. Note that the circuit configuration of the insulating element 40 described above is merely an example. The insulating element 40 may have other circuit configurations as long as it can transmit the output currents Iout1 and Iout2 using electric field coupling.

[0104] FIG. 15 shows an example of the circuit configuration of a signal generation circuit 30 included in a communication device 2 according to a modification of the second embodiment. As shown in FIG. 15, in the modification of the second embodiment, the signal generation circuit 30 has a configuration in which the current source 326 is omitted from the signal generation circuit 30 in the second embodiment because the insulating element 40 uses capacitive coupling. Specifically, the sources of the transistors 324 and 325 are connected to the ground GND1.

[0105] As described above, when an insulating capacitor is used as the insulating device, for example, an inverter circuit is used in the driving unit 32 of the signal generation circuit 30. Then, the insulating capacitors (capacitors 43 and 44) in the insulating element 40 are driven by the voltage from the inverter circuit. Other configurations and operations of the communication device 2 according to the modification of the second embodiment are the same as those of the second embodiment. Thereby, the communication device 2 according to the modification of the second embodiment can obtain the same effects as the second embodiment.

[0106] [3] Third Embodiment The communication device 3 according to the third embodiment has a configuration in which the RF generator 20 generates and outputs a plurality of types of carrier signals CS. Hereinafter, the differences between the communication device 3 according to the third embodiment and the first and second embodiments will be described.

[0107] [3-1] Configuration FIG. 16 shows an example of the configuration of the communication device 3 according to the third embodiment. As shown in FIG. 16, the communication device 3 according to the third embodiment has four channels, similar to the third modification of the first embodiment. Further, the communication device 3 according to the third embodiment is different from the third modification of the first embodiment in that the RF generator 20 outputs four types of carrier signals CS.

[0108] Specifically, the RF generator 20 in the third embodiment generates and outputs carrier signals CS1, CS2, CS3, and CS4 based on the input signal Vin1 input from the input circuit 10A, the input signal Vin2 input from the input circuit 10B, the input signal Vin3 input from the input circuit 10C, and the input signal Vin4 input from the input circuit 10D. The carrier signals CS1, CS2, CS3, and CS4 are respectively input to the signal generation circuits 30A, 30B, 30C, and 30D.

[0109] FIG. 17 shows an example of the circuit configuration of the RF generator 20 included in the communication device 3 according to the third embodiment. As shown in FIG. 17, for example, the signal output from the node N1 corresponds to the carrier signal CS4. The signal output from the node N2 corresponds to the carrier signal CS2. The signal output from the node N3 corresponds to the carrier signal CS1. The signal output from the inverter 25 corresponds to the carrier signal CS3.

[0110] In the RF generator 20 described above, the phases of the carrier signals CS1 to CS4 are different from each other. In the third embodiment, the assignment of the carrier signal CS to the nodes N1, N2, and N3 and the output terminal of the inverter can be arbitrarily changed. Other configurations of the communication device 3 according to the third embodiment are the same as those of the third modification example of the first embodiment.

[0111] [3-2] Effects of the Third Embodiment In a communication device capable of inputting an N-bit signal, N signal generation circuits 30 operate synchronously, and carrier signals synchronized with each other flow through N insulating elements 40. As a result, the EMI radiated from the signal generation circuits 30 and the insulating elements 40 also becomes N times. In the first and second embodiments, the signals (pulses) output by each signal generation circuit 30 are completely synchronized with the carrier signal CS. As a method for improving EMI, it is conceivable to change the driving phase between the plurality of insulating elements 40.

[0112] Therefore, the communication device 3 according to the third embodiment includes an RF generator 20 capable of generating a plurality of types of carrier signals CS. Briefly speaking, in the RF generator 20 in the third embodiment, among a plurality of nodes connected to any one of the inverters 23 to 25 connected in series, four types of carrier signals CS1 to CS4 are extracted from four different nodes. Then, the signal generation circuits 30A, 30B, 30C, and 30D modulate the input signal Vin using the carrier signals CS1, CS2, CS3, and CS4, respectively, and drive the corresponding insulating elements 40.

[0113] Here, let the carrier signal flowing through the insulating element x (corresponding to the insulating element 40, where x is an integer from 1 to 4) be Ax·sin(ω0·t + φx). In this case, the EMI signals radiated from the four insulating elements are expressed as in the following equation (1). Note that ω0 corresponds to the oscillation angular frequency of the RF generator 20. Ax corresponds to the one-sided amplitude of the carrier signal flowing through the insulating element x.

[0114]

Equation

[0115] In equation (1), when φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad]. Also, the combined amplitude A of equation (1) is expressed as in the following equation (2A), and the phase φ of equation (1) is expressed as in the following equation (2B).

[0116]

Equation

[0117]

Equation

[0118] When φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], when A1 = 0 and A2 = A3 = A4 = 1, the maximum combined amplitude A = 2. On the other hand, when φ1 = φ2 = φ3 = φ4 = 0 [rad], when A1 = A2 = A3 = A4 = 1, the maximum combined amplitude A = 4. Comparing these cases, the communication device 3 according to the third embodiment can halve the combined amplitude A and improve the EMI by 6 dB by setting φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad].

[0119] By similar discussion, it is also possible to discuss the EMI of the second harmonic. When considering the EMI of the harmonic, for example, equation (1) is rewritten as the following equation (3A).

[0120]

Equation

[0121] That is, in the case of the second harmonic, ω = 2ω0. Therefore, compared with the case of the fundamental wave, the phase with respect to the second harmonic is doubled. When ω = nω0 which is the nth harmonic is considered, the carrier signal flowing through the insulating element x is expressed as the following equation (3B).

[0122]

Equation

[0123] Also, the combined amplitude A of equation (3B) is expressed as the following equation (4A), and the phase φ of equation (3B) is expressed as the following equation (4B).

[0124]

Equation

[0125]

Equation

[0126] When φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], and A1 = A3 = 1 and A2 = A4 = 1, the maximum combined amplitude A = 2. On the other hand, when φ1 = φ2 = φ3 = φ4 = 0 [rad] and A1 = A2 = A3 = A4 = 1, the maximum combined amplitude A = 4. Comparing these cases, the communication device 3 according to the third embodiment can halve the combined amplitude A and improve the harmonic EMI by 6 dB by setting φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad], similar to the case of the fundamental wave.

[0127] [3-3] First Modification of the Third Embodiment The communication device 3 according to the third embodiment described above can be variously modified. For example, in the third embodiment, the case where four types of carrier signals with different phases of φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = π [rad], and φ4 = 4π / 3 [rad] are used is exemplified, but it is not limited thereto. Similarly, the communication device 3 can improve the harmonic EMI even when the number of types of carrier signals is other than four. Hereinafter, the differences from the third embodiment will be described for the first modification and the second modification of the third embodiment.

[0128] [3-3-1] First Modification of the Third Embodiment FIG. 18 shows an example of the configuration of the communication device 3 according to the first modification of the third embodiment. As shown in FIG. 18, the communication device 3 according to the first modification of the third embodiment is different from the third embodiment in that the RF generator 20 outputs three types of carrier signals CS.

[0129] Specifically, in the first modification of the third embodiment, the RF generator 20 generates and outputs carrier signals CS1, CS2, and CS3 based on the input signal Vin1 input from the input circuit 10A, the input signal Vin2 input from the input circuit 10B, the input signal Vin3 input from the input circuit 10C, and the input signal Vin4 input from the input circuit 10D. For example, the carrier signal CS1 is input to the signal generation circuits 30A and 30B. The carrier signals CS2 and CS3 are input to the signal generation circuits 30C and 30D, respectively.

[0130] FIG. 19 shows an example of the circuit configuration of the RF generator 20 included in the communication device 3 according to the first modification of the third embodiment. As shown in FIG. 19, in the first modification of the third embodiment, the inverter 25 is omitted from the RF generator 20 in the first embodiment, and a configuration in which a plurality of carrier signals CS are output from a plurality of nodes is provided.

[0131] Specifically, in the first modification of the third embodiment, for example, the signal output from the node N1 corresponds to the carrier signal CS3. The signal output from the node N2 corresponds to the carrier signal CS2. The signal output from the node N3 corresponds to the carrier signal CS1. Note that, in the first modification of the third embodiment, the assignment of the carrier signals CS to the nodes N1, N2, and N3 can be arbitrarily changed. Other configurations of the communication device 3 according to the first modification of the third embodiment are the same as those of the third embodiment.

[0132] In the communication device 3 according to the first modification of the third embodiment described above, φ1 = φ2 = 0 [rad], φ3 = 2π / 3 [rad], and φ4 = 4π / 3 [rad]. As a result, similar to the third embodiment, the communication device 3 according to the first modification of the third embodiment can improve the EMI performance of the fundamental wave and the second harmonic by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad].

[0133] In the first modification of the third embodiment, the case where the carrier signal CS1 is input to the two signal generation circuits 30A and 30B has been illustrated. However, other carrier signals CS may be input to the two signal generation circuits 30A and 30B. When the carrier signal CS2 is input to the signal generation circuits 30A and 30B, φ1 = 0 [rad], φ2 = φ3 = 2π / 3 [rad], and φ4 = 4π / 3 [rad]. When the carrier signal CS3 is input to the signal generation circuits 30A and 30B, φ1 = 0 [rad], φ2 = 2π / 3 [rad], φ3 = φ4 = 4π / 3 [rad]. In any case, the communication device 3 can improve the EMI performance of the fundamental wave and the second harmonic by 6 dB, similar to the third embodiment.

[0134] [3-3-2] Second Modification of the Third Embodiment FIG. 20 shows an example of the configuration of the communication device 3 according to the second modification of the third embodiment. As shown in FIG. 20, the communication device 3 according to the second modification of the third embodiment is different from the third embodiment in that the RF generator 20 outputs two types of carrier signals CS.

[0135] Specifically, the RF generator 20 in the second modification of the third embodiment generates and outputs the carrier signals CS1 and CS2 based on the input signal Vin1 input from the input circuit 10A, the input signal Vin2 input from the input circuit 10B, the input signal Vin3 input from the input circuit 10C, and the input signal Vin4 input from the input circuit 10D. For example, the carrier signal CS1 is input to the signal generation circuits 30A and 30B. The carrier signal CS2 is input to the signal generation circuits 30C and 30D.

[0136] FIG. 21 shows an example of the circuit configuration of the RF generator 20 provided in the communication device 3 according to the second modification of the third embodiment. As shown in FIG. 21, the RF generator 20 in the second modification of the third embodiment has a configuration in which the output of the carrier signal CS from the node N2 is omitted compared to the RF generator 20 in the first modification of the third embodiment.

[0137] In the second modification of the third embodiment, for example, the signal output from node N1 corresponds to the carrier signal CS2. The signal output from node N3 corresponds to the carrier signal CS1. Note that in the second modification of the third embodiment, the assignment of the carrier signal CS to nodes N1 and N3 can be arbitrarily changed. Other configurations of the communication device 3 according to the second modification of the third embodiment are the same as those of the first modification of the third embodiment.

[0138] In the communication device 3 according to the second modification of the third embodiment described above, φ1 = φ2 = 0 [rad] and φ3 = φ4 = 2π / 3 [rad]. As a result, the communication device 3 according to the second modification of the third embodiment can improve the fundamental wave and second harmonic EMI performance by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad], similar to the third embodiment.

[0139] [3-3-3] Third Modification of the Third Embodiment FIG. 22 shows an example of the circuit configuration of the RF generator 20 included in the communication device 3 according to the third modification of the third embodiment. As shown in FIG. 22, the RF generator 20 in the third modification of the third embodiment has a configuration in which the output of the carrier signal CS from node N1 is omitted compared to the RF generator 20 in the first modification of the third embodiment.

[0140] In the third modification of the third embodiment, for example, the signal output from node N2 corresponds to the carrier signal CS1. The signal output from node N3 corresponds to the carrier signal CS2. Note that in the third modification of the third embodiment, the assignment of the carrier signal CS to nodes N2 and N3 can be arbitrarily changed. Other configurations of the communication device 3 according to the third modification of the third embodiment are the same as those of the first modification of the third embodiment.

[0141] In the communication device 3 according to the third modification of the third embodiment described above, φ1 = φ2 = 0 [rad] and φ3 = φ4 = 4π / 3 [rad]. As a result, the communication device 3 according to the third modification of the third embodiment can improve the EMI performance of the fundamental wave and the second harmonic by 6 dB compared to the case where φ1 = φ2 = φ3 = φ4 = 0 [rad], similar to the third embodiment.

[0142] [4] Fourth Embodiment The communication device 4 according to the fourth embodiment is a modification of the signal generation circuit 30 that uses the in-phase and anti-phase modulated signals described in the second embodiment. Hereinafter, the differences between the communication device 4 according to the fourth embodiment and the second embodiment will be described.

[0143] [4-1] Configuration FIG. 23 shows an example of the circuit configuration of the signal generation circuit 30 included in the communication device 4 according to the fourth embodiment. As shown in FIG. 23, the signal generation circuit 30 in the fourth embodiment includes a signal generation unit 31 having a different circuit configuration compared to the second embodiment. The signal generation unit 31 in the fourth embodiment includes, for example, a first delay circuit 330, a second delay circuit 331, a clock transition detection circuit 332, a pulse generation circuit 333, a NAND circuit 334, a phase detection circuit 335, a selector circuit 336, an OR circuit 337, and a NOR circuit 338.

[0144] An input signal Vin is input to the first delay circuit 330. Then, the first delay circuit 330 inputs the delayed input signal Vin to the pulse generation circuit 333. The delay amount of the first delay circuit is designed to be equal to, for example, the delay amount of the signal via the clock transition detection circuit 332. Hereinafter, the input signal Vin delayed by the first delay circuit will be referred to as the delayed input signal VinD.

[0145] The second delay circuit 331 receives the carrier signal CS. Then, the second delay circuit 331 inputs the delayed carrier signal CS to the selector circuit 336. The delay amount of the second delay circuit is designed to be equal to, for example, the sum of the delay amount of the signal via the clock transition detection circuit 332 and the delay amount of the signal via the phase detection circuit 335. Hereinafter, the carrier signal CS delayed by the second delay circuit is referred to as the delayed carrier signal CSd.

[0146] The clock transition detection circuit 332 receives the input signal Vin and the carrier signal CS, and generates clock transition signals CT1 and CT2 based on the input input signal Vin and carrier signal CS. Then, the clock transition detection circuit 332 inputs the generated clock transition signals CT1 and CT2 to each of the pulse generation circuit 333, the NAND circuit 334, and the phase detection circuit 335.

[0147] The pulse generation circuit 333 generates a non-inverting input signal VinNP based on the input delayed input signal VinD and the clock transition signals CT1 and CT2. Then, the pulse generation circuit 333 inputs the generated non-inverting input signal VinNP to the OR circuit 337.

[0148] The NAND circuit 334 performs a NAND operation on the input clock transition signals CT1 and CT2. Then, the NAND circuit 334 inputs the operation result as an inverting input signal VinRP to the NOR circuit 338.

[0149] The phase detection circuit 335 generates phase detection signals PD1 and PD2 based on the input clock transition signals CT1 and CT2. Then, the phase detection circuit 335 inputs the generated phase detection signals PD1 and PD2 to the selector circuit 336.

[0150] The selector circuit 336 generates an internal carrier signal Vcs based on the input phase detection signals PD1 and PD2 and the delayed carrier signal CSd. Then, the selector circuit 336 inputs the generated internal carrier signal Vcs to the OR circuit 337 and the NOR circuit 338.

[0151] The OR circuit 337 corresponds to the positive-phase output of the signal generation circuit 30. Specifically, the OR circuit 337 performs an OR operation on the input positive-phase input signal VinNP and the internal carrier signal Vcs. Then, the OR circuit 337 outputs the operation result as the positive-phase modulated signal MS1 to the driving unit 32.

[0152] The NOR circuit 338 corresponds to the inverted-phase output of the signal generation circuit 30. Specifically, the NOR circuit 338 performs a NOR operation on the input inverted-phase input signal VinRP and the internal carrier signal Vcs. Then, the NOR circuit 338 outputs the operation result as the inverted-phase modulated signal MS2 to the driving unit 32.

[0153] Other configurations of the communication device 4 according to the fourth embodiment are the same as those of the second embodiment. That is, the modulated signals MS1 and MS2 generated by the signal generation unit 31 are input to a driving unit 32 (not shown). Then, the driving unit 32 differentially amplifies the modulated signals MS1 and MS2 and outputs the amplified voltage to the insulating element 40. Note that the signal generation circuit 30 in the fourth embodiment may have other circuit configurations as long as it can execute the operations described later.

[0154] [4-2] Operation The operation of the communication device 4 according to the fourth embodiment can change according to the state of the RF generator 20 and the timing at which the input signal Vin rises. Hereinafter, a specific example of the operation of the communication device 4 according to the fourth embodiment will be described with reference to FIGS. 24 to 26. Each of FIGS. 24 to 26 shows an example of a timing chart of the operation in the communication device 4 according to the fourth embodiment and displays the voltages of the respective signals corresponding to one signal generation circuit 30.

[0155] Still, in the following description, the fact that the RF generator 20 is in the on state indicates that at least one input signal Vin corresponding to the other signal generation circuit 30 has risen, and the carrier signal CS has already started oscillating. On the other hand, the fact that the RF generator 20 is in the off state indicates that all of the input signals Vin corresponding to the other signal generation circuit 30 have fallen, and the carrier signal CS is not oscillating.

[0156] Also, the voltages of the initial states of the input signal Vin, the delayed input signal VinD, the clock transition signals CT1 and CT2, the phase detection signals PD1 and PD2, the internal carrier signal Vcs, and the non-inverting input signal VinNP are set to the "L" level. At this time, the NAND circuit 334 outputs the inverted input signal VinRP at the "H" level. The OR circuit 337 outputs the modulated signal MS1 at the "L" level. The NOR circuit 338 outputs the modulated signal MS2 at the "L" level.

[0157] (When Vin rises when the RF generator 20 is in the on state and CS = "L" level) FIG. 24 corresponds to the operation when the RF generator 20 is in the on state and the input signal Vin rises when the carrier signal CS is at the "L" level (RF: on, "L" → "H" detection). As shown in FIG. 24, in the initial state of this example, the carrier signal CS is oscillating, and the delayed carrier signal CSd is oscillating with a delay with respect to the carrier signal CS.

[0158] When the input signal Vin rises, the first delay circuit 330 delays the delayed input signal VinD with respect to the input signal Vin and transitions it from the "L" level to the "H" level (FIG. 24(1)). Then, based on the fact that the delayed input signal VinD has become the "H" level, the pulse generation circuit 333 transitions the non-inverting input signal VinNP from the "L" level to the "H" level. As a result, the non-inverting input signal VinNP at the "H" level is input to the OR circuit 337, and the OR circuit 337 sets the modulated signal MS1 to the "H" level.

[0159] Also, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, based on the fact that the carrier signal CS has risen, the clock transition detection circuit 332 first transitions the clock transition signal CT1 from the "L" level to the "H" level (Fig. 24(2)). Subsequently, based on the fact that the carrier signal CS has fallen, the clock transition detection circuit 332 transitions the clock transition signal CT2 from the "L" level to the "H" level (Fig. 24(3)). When both the clock transition signals CT1 and CT2 become the "H" level, the pulse generation circuit 333 transitions the non-inverted input signal VinNP from the "H" level to the "L" level, and the NAND circuit 334 transitions the inverted input signal VinRP from the "H" level to the "L" level. Also, based on the fact that the clock transition signal CT1 transitions to the "H" level earlier than the clock transition signal CT2, the phase detection circuit 335 transitions the phase detection signal PD1 from the "L" level to the "H" level (Fig. 24(4)).

[0160] Then, based on the fact that the phase detection signal PD1 is at the "H" level, the selector circuit 336 outputs a signal having the same phase as the phase of the delayed carrier signal CSd as the internal carrier signal Vcs (Fig. 24(5)). When the "L" level non-inverted input signal VinNP is input to the OR circuit 337, the OR circuit 337 sets the modulated signal MS1 to the "L" level and then outputs the modulated signal MS1 having a phase that maintains the phase of the internal carrier signal Vcs. When the "L" level inverted input signal VinRP is input to the NOR circuit 338, the NOR circuit 338 outputs the modulated signal MS2 having a phase obtained by inverting the phase of the internal carrier signal Vcs.

[0161] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generation circuit 333, and the subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the same phase as the carrier signal CS. Then, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the "H" level to the "L" level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the "H" level to the "L" level (Fig. 24(6)). Based on both the clock transition signals CT1 and CT2 becoming the "L" level, the NAND circuit 334 outputs the inverted input signal VinRP of the "H" level, the phase detection circuit 335 transitions the phase detection signal PD1 from the "H" level to the "L" level, and the selector circuit 336 maintains the internal carrier signal Vcs at the "L" level. As a result, the signal generation circuit 30 returns to the initial state.

[0162] (When Vin rises when the RF generator 20 is on and CS = "H" level) Fig. 25 corresponds to the operation when the input signal Vin rises when the RF generator 20 is on and the carrier signal CS is at the "H" level (RF: on, "H" → "L" detection). As shown in Fig. 25, in the initial state of this example, the carrier signal CS is oscillating, and the delayed carrier signal CSd is oscillating with a delay relative to the carrier signal CS.

[0163] When the input signal Vin rises, the first delay circuit 330 delays the delayed input signal VinD relative to the input signal Vin and transitions it from the "L" level to the "H" level (Fig. 25(1)). Then, based on the delayed input signal VinD becoming the "H" level, the pulse generation circuit 333 transitions the non-inverted input signal VinNP from the "L" level to the "H" level. As a result, the non-inverted input signal VinNP of the "H" level is input to the OR circuit 337, and the OR circuit 337 sets the modulated signal MS1 to the "H" level.

[0164] Also, when the input signal Vin rises, the clock transition detection circuit 332 starts monitoring the state of the carrier signal CS. At this time, based on the fact that the carrier signal CS has fallen, the clock transition detection circuit 332 first transitions the clock transition signal CT2 from the "L" level to the "H" level (Fig. 25(2)). Subsequently, based on the fact that the carrier signal CS has risen, the clock transition detection circuit 332 transitions the clock transition signal CT1 from the "L" level to the "H" level (Fig. 25(3)). When both the clock transition signals CT1 and CT2 become the "H" level, the pulse generation circuit 333 transitions the non-inverting input signal VinNP from the "H" level to the "L" level, and the NAND circuit 334 transitions the inverting input signal VinRP from the "H" level to the "L" level. Also, based on the fact that the clock transition signal CT2 has transitioned to the "H" level earlier than the clock transition signal CT1, the phase detection circuit 335 transitions the phase detection signal PD2 from the "L" level to the "H" level (Fig. 25(4)).

[0165] Then, based on the fact that the phase detection signal PD2 is at the "H" level, the selector circuit 336 outputs, as the internal carrier signal Vcs, a signal having a phase obtained by inverting the phase of the delayed carrier signal CSd (Fig. 25(5)). When the non-inverting input signal VinNP at the "L" level is input to the OR circuit 337, the OR circuit 337 sets the modulated signal MS1 to the "L" level and then outputs the modulated signal MS1 having the same phase as the phase of the internal carrier signal Vcs. When the inverting input signal VinRP at the "L" level is input to the NOR circuit 338, the NOR circuit 338 outputs the modulated signal MS2 having a phase obtained by inverting the phase of the internal carrier signal Vcs.

[0166] As described above, in this example, when the input signal Vin rises, the first pulse signal of the modulated signal MS1 is immediately generated by the pulse generation circuit 333, and the second and subsequent pulse signals are generated based on the internal carrier signal Vcs corresponding to the inverted output of the carrier signal CS. Then, when the input signal Vin falls, the first delay circuit 330 transitions the delayed input signal VinD from the "H" level to the "L" level, and the clock transition detection circuit 332 transitions the clock transition signals CT1 and CT2 from the "H" level to the "L" level (FIG. 25(6)). Based on both the clock transition signals CT1 and CT2 becoming the "L" level, the NAND circuit 334 outputs the inverted input signal VinRP of the "H" level, the phase detection circuit 335 transitions the phase detection signal PD2 from the "H" level to the "L" level, and the selector circuit 336 maintains the internal carrier signal Vcs at the "L" level. As a result, the signal generation circuit 30 returns to the initial state.

[0167] (When Vin rises when the RF generator 20 is in the off state) FIG. 26 corresponds to the operation when the input signal Vin rises when the RF generator 20 is in the off state (RF: off → on). As shown in FIG. 26, in the initial state of this example, the carrier signal CS is in the off state ("L" level).

[0168] When the input signal Vin rises, the RF generator 20 becomes on, and the oscillation of the carrier signal CS starts (RF on). In this case, the clock transition detection circuit 332 first detects the rise of the carrier signal CS and then detects the fall of the carrier signal CS. That is, in this example, after the input signal Vin rises, the clock transition signal CT1 first becomes the "H" level, and the clock transition signal CT2 later becomes the "H" level. The other operations shown in FIG. 26 are the same as the operations described with reference to FIG. 24. Incidentally, when other input signals Vin maintain the "L" level, when the input signal Vin falls, the RF generator 20 becomes off (RF off).

[0169] [4-3] Effects of the Fourth Embodiment As described above, the signal generation circuit 30 included in the communication device 4 according to the fourth embodiment includes a signal generation unit 31 that changes the phase of the internal carrier signal Vcs according to the rising timing of the input signal Vin.

[0170] Briefly stated, when the signal generation unit 31 in the fourth embodiment detects that the input signal Vin has risen, it generates a first pulse signal (modulated signal MS1) regardless of whether the RF generator 20 is in the on state or the off state. The pulse width of this first pulse signal becomes 0.5 to 1.0 times the period of the carrier signal CS according to the rising timing of the input signal Vin. And when the signal generation unit 31 in the fourth embodiment detects the rising of the input signal Vin when the carrier signal CS is at the "L" level, it generates an internal carrier signal Vcs based on the phase of the delayed carrier signal CS. On the other hand, when the signal generation unit 31 in the fourth embodiment detects the rising of the input signal Vin when the carrier signal CS is at the "H" level, it generates an internal carrier signal Vcs based on the phase obtained by inverting the phase of the delayed carrier signal CS.

[0171] As described above, since the first pulse signal is generated regardless of the state of the RF generator 20, the rising waveform of the in-phase modulated signal MS1 becomes constant regardless of whether the input signal Vin and the carrier signal CS are synchronized. In other words, even when the input signal Vin and the carrier signal CS are operated asynchronously, the leading waveforms of the modulated signal MS used in the OOK method are aligned. Thereby, the communication device 4 according to the fourth embodiment can stabilize the rising time of the detection circuit, and can suppress the jitter of the output signal by the signal generation circuit 30 as in the first and second embodiments.

[0172] Furthermore, by generating the second and subsequent pulse signals based on an inverted or non-inverted internal carrier signal Vcs corresponding to the rising timing of the input signal Vin, the falling edge of the first pulse signal and the rising edges of the second and subsequent pulse signals are smoothly connected. In other words, the signal generation unit 31 in the fourth embodiment can stably generate the second and subsequent pulses. As a result, the communication device 4 according to the fourth embodiment can suppress the generation of high-frequency pulses such as glitches. Therefore, the communication device 4 according to the fourth embodiment can improve the operational stability more than the second embodiment.

[0173] Note that in the fourth embodiment, the case where the signal generation circuit 30 uses the in-phase modulated signal MS1 and the anti-phase modulated signal MS2 has been illustrated, but it is not limited thereto. For example, the signal generation circuit 30 may handle one modulated signal MS as in the first embodiment. In this case, the signal generation unit 31 has a configuration in which the NAND circuit 334 and the NOR circuit 338 are omitted from the configuration shown in FIG. 23, for example. A communication device having such a signal generation circuit 30 can obtain the same effects as the fourth embodiment and can improve the operational stability more than the first embodiment.

[0174] [5] Others The above embodiments can be combined. For example, the second embodiment may be combined with any of the first to fourth modification examples of the first embodiment. The third embodiment may be combined with any of the first embodiment, the first and second modification examples of the first embodiment, the second embodiment, and the modification example of the second embodiment. The fourth embodiment may be combined with any of the third embodiment and the first to third modification examples of the third embodiment. The signal generation circuit 30 of the fourth embodiment may be applied to each of the N channels as in the third modification example of the first embodiment. The communication device 1 combined with a plurality of embodiments and modification examples can obtain the effects of each of the combined embodiments and modification examples. Adjusting the phase of each insulating element 40 to suppress EMI as in the third embodiment can also be applied to the first and second embodiments. That is, the third embodiment can be applied regardless of the configuration of the signal generation circuit 30, the number of channels provided in the communication device 1, and the type of insulating element used.

[0175] In this specification, the voltage of the "H" level is a voltage at which an N-type transistor with the voltage applied to the gate is turned on and a P-type transistor with the voltage applied to the gate is turned off. The voltage of the "L" level is a voltage at which an N-type transistor with the voltage applied to the gate is turned off and a P-type transistor with the voltage applied to the gate is turned on. Each of the "first logic level" and the "second logic level" corresponds to either the "H" level or the "L" level. The oscillated signal output by the RF generator 20 may be called an "RF signal" or a "clock signal". The RF generator 20 may be called an "oscillator". The combination of the receiving circuit 50 and the output circuit 60 may be called an "output circuit".

[0176] As used herein, "connected" means electrically connected, and does not exclude, for example, having another element in between. Also, as used herein, "on state" means that a voltage equal to or higher than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor. "Off state" means that a voltage lower than the threshold voltage of the corresponding transistor is applied to the gate of the corresponding transistor, and does not exclude, for example, a minute current such as the leakage current of the transistor from flowing. "The signal rises" means that the voltage of the signal changes from the "L" level to the "H" level. "The signal falls" means that the voltage of the signal changes from the "H" level to the "L" level. "The state where the signal has risen" corresponds to the "H" level. "The state where the signal has fallen" corresponds to the "L" level. "One pulse signal" corresponds to, for example, the portion where the signal transitions from the "L" level → "H" level → "L" level. "Pulse width" corresponds to, for example, the period during which the signal transitions from the "L" level → "H" level → "L" level.

[0177] Regarding the claim aspects of this specification, the following is appended.

[0178] <1> The communication device includes an oscillator, a first signal generation circuit, a second signal generation circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of the first signal and the second signal input from the outside is at a first logic level. The first signal generation circuit includes a first signal generation unit and a first drive circuit. The first signal generation unit generates a first pulse signal when detecting the rising edge of the first signal, and outputs a signal having the same phase as the carrier signal as subsequent pulse signals when the carrier signal is at a second logic level different from the first logic level when the rising edge of the first signal is detected, and outputs a signal with the phase of the carrier signal inverted as subsequent pulse signals when the carrier signal is at the first logic level when the rising edge of the first signal is detected. The first drive circuit amplifies the output signal of the first signal generation unit. The second signal generation circuit includes a second signal generation unit and a second drive circuit. The second signal generation unit generates a first pulse signal when detecting the rising edge of the second signal, and outputs a signal having the same phase as the carrier signal as subsequent pulse signals when the carrier signal is at the second logic level when the rising edge of the second signal is detected, and outputs a signal with the phase of the carrier signal inverted as subsequent pulse signals when the carrier signal is at the first logic level when the rising edge of the first signal is detected. The second drive circuit amplifies the output signal of the second signal generation unit. The first insulating element is connected to the output of the first drive circuit. The second insulating element is connected to the output of the second drive circuit. The first output circuit receives a signal based on the output signal of the first drive circuit via the first insulating element and outputs it to the outside. The second output circuit receives a signal based on the output signal of the second drive circuit via the second insulating element and outputs it to the outside.

[0179] <2> The communication device described in <1> has the following-described configuration. The first signal generation unit includes a clock transition detection circuit, a pulse generation circuit, a phase detection circuit, a selector circuit, and a first OR circuit. The clock transition detection circuit receives the first signal and the carrier signal, and generates a first control signal and a second control signal based on the received first signal and carrier signal. The pulse generation circuit generates a first input signal based on the first signal, the first control signal, and the second control signal. The phase detection circuit generates a third control signal and a fourth control signal based on the first control signal and the second control signal. The selector circuit generates an internal carrier signal based on the third control signal, the fourth control signal, and the carrier signal. The first OR circuit performs an OR operation on the first input signal and the internal carrier signal, and the operation result is output by the first drive circuit. The clock transition detection circuit transitions the first control signal from the second logic level to the first logic level when it detects the rising edge of the carrier signal after the first signal has risen, and transitions the second control signal from the second logic level to the first logic level when it detects the falling edge of the carrier signal. The pulse generation circuit transitions the first input signal from the second logic level to the first logic level when it detects the rising edge of the first signal, and transitions the first input signal from the first logic level to the second logic level in response to both the first control signal and the second control signal becoming the first logic level after it has detected the rising edge of the first signal. The phase detection circuit generates an internal carrier signal having the same phase as the carrier signal when the third control signal transitions to the first logic level before the fourth control signal when both the third control signal and the fourth control signal become the first logic level, and generates an internal carrier signal having a phase with the phase of the carrier signal inverted when the fourth control signal transitions to the first logic level before the third control signal.

[0180] <3> The communication device described in <2> has the following configuration. The first signal generation unit further includes a first delay circuit and a second delay circuit. The first delay circuit generates a delay equivalent to the delay amount of the clock transition detection circuit. The second delay circuit generates a delay equivalent to the total delay amount of the clock transition detection circuit and the phase detection circuit. A first signal passing through the first delay circuit is input to the pulse generation circuit, and the pulse generation circuit generates a first input signal based on the delayed first signal. A carrier signal passing through the second delay circuit is input to the selector circuit, and the selector circuit generates an internal carrier signal based on the delayed carrier signal.

[0181] <4> The communication device described in <2> or <3> has the following configuration. The first signal generation unit further includes a first NAND circuit and a first NOR circuit. The first NAND circuit performs a NAND operation on the first control signal and the second control signal, and outputs the operation result as the second input signal. The first NOR circuit performs a NOR operation on the second input signal and the internal carrier signal, and the operation result is output by the first drive circuit. The first drive circuit differentially amplifies the output of the first OR circuit and the output of the first NOR circuit.

[0182] <5> The communication device described in any one of <1> to <4> has the following configuration. After detecting the rising edge of the first signal, when the falling edge of the first signal is detected, the first signal generation unit outputs a signal of the second logic level to the first drive circuit.

[0183] <6>The communication device includes an oscillator, a first signal generation circuit, a second signal generation circuit, a first insulating element, a second insulating element, a first output circuit, and a second output circuit. The oscillator outputs a carrier signal when at least one of the first signal and the second signal input from the outside is at the first logic level. The first signal generation circuit includes a first delay circuit, a first logic circuit, a second logic circuit, a third logic circuit, and a first drive circuit. The first logic circuit has the first signal input to its first input terminal and the first signal passed through the first delay circuit input to its second input terminal. The second logic circuit has the output terminal of the first logic circuit connected to its first input terminal and the carrier signal input to its second input terminal. The third logic circuit has the first signal input to its first input terminal and the output terminal of the second logic circuit connected to its second input terminal. The first drive circuit amplifies the voltage output by the third logic circuit. The second signal generation circuit includes a second delay circuit, a fourth logic circuit, a fifth logic circuit, a sixth logic circuit, and a second drive circuit. The fourth logic circuit has the second signal input to its first input terminal and the second signal passed through the second delay circuit input to its second input terminal. The fifth logic circuit has the output terminal of the fourth logic circuit connected to its first input terminal and the carrier signal input to its second input terminal. The sixth logic circuit has the second signal input to its first input terminal and the output terminal of the fifth logic circuit connected to its second input terminal. The second drive circuit amplifies the voltage output by the sixth logic circuit. The first insulating element is connected to the output of the first drive circuit. The second insulating element is connected to the output of the second drive circuit. The first output circuit receives, via the first insulating element, a signal based on the output signal of the first drive circuit and outputs it to the outside. The second output circuit receives, via the second insulating element, a signal based on the output signal of the second drive circuit and outputs it to the outside.

[0184] <7>In the communication device according to <6>, the first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, and the second logic circuit and the fifth logic circuit are NAND circuits.

[0185] The communication device according to <8>, <6> or <7> has the following-described configuration. The first signal generation circuit further includes a fourth inverter and a thirteenth logic circuit. The input terminal of the fourth inverter is connected to the output terminal of the second logic circuit. The thirteenth logic circuit has the first signal input to its first input terminal and the output terminal of the fourth inverter connected to its second input terminal. The second signal generation circuit further includes a fifth inverter and a fourteenth logic circuit. The input terminal of the second signal generation circuit is connected to the output terminal of the fifth logic circuit. The fourteenth logic circuit has the second signal input to its first input terminal and the output terminal of the fifth inverter connected to its second input terminal. The first drive circuit differentially amplifies the output of the third logic circuit and the output of the thirteenth logic circuit. The second drive circuit differentially amplifies the output of the sixth logic circuit and the output of the fourteenth logic circuit.

[0186] The communication device according to any one of <9>, <1> to <8> has the following-described configuration. The first insulating element includes a first coil and a second coil. The first coil is connected to the output of the first drive circuit. The second coil faces the first coil via an insulator layer and is connected to the first output circuit. The second insulating element includes a third coil and a fourth coil. The third coil is connected to the output of the second drive circuit. The fourth coil faces the third coil via an insulator layer and is connected to the second output circuit.

[0187] The communication device according to any one of <10>, <1> to <8> has the following-described configuration. The first insulating element includes a first capacitor. One electrode of the first capacitor is connected to the output of the first drive circuit, and the other electrode is connected to the first output circuit. The second insulating element includes a second capacitor. One electrode of the second capacitor is connected to the output of the second drive circuit, and the other electrode is connected to the second output circuit.

[0188] <11> The communication device according to any one of <1> to <10> further includes a first substrate and a second substrate. An oscillator, a first signal generation circuit, and a second signal generation circuit are mounted on the first substrate. A first output circuit and a second output circuit are mounted on the second substrate. The first insulating element and the second insulating element are mounted on either the first substrate or the second substrate.

[0189] <12> In the communication device according to <1> or <6>, the phase of the carrier signal input to the first signal generation circuit is different from the phase of the carrier signal input to the second signal generation circuit.

[0190] <13> In the communication device according to <12>, the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first signal input to its first input terminal and a second signal input to its second input terminal. The second NAND circuit has the output terminal of the second OR circuit connected to its first input terminal. The first inverter has the output terminal of the second NAND circuit connected to its input terminal. The second inverter has the output terminal of the first inverter connected to its input terminal and its output terminal connected to the second input terminal of the second NAND circuit. The output terminal of the second NAND circuit is connected to the second signal generation circuit. The output terminal of the second inverter is connected to the first signal generation circuit.

[0191] <14> In the communication device according to <12>, the oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first signal input to its first input terminal and a second signal input to its second input terminal. The second NAND circuit has the output terminal of the second OR circuit connected to its first input terminal. The first inverter has the output terminal of the second NAND circuit connected to its input terminal. The second inverter has the output terminal of the first inverter connected to its input terminal and its output terminal connected to the second input terminal of the second NAND circuit. The output terminal of the first inverter is connected to the second signal generation circuit. The output terminal of the second inverter is connected to the first signal generation circuit.

[0192] The communication device described in <15> <6> further includes a third signal generation circuit, a third insulating element, and a third output circuit. The third signal generation circuit includes a third delay circuit, a seventh logic circuit, an eighth logic circuit, a ninth logic circuit, and a third drive circuit. The seventh logic circuit has a third signal input from outside the communication device to the first input terminal and a third signal via the third delay circuit input to the second input terminal. The eighth logic circuit has the output terminal of the seventh logic circuit connected to the first input terminal and a carrier signal input to the second input terminal. The ninth logic circuit has a third signal input to the first input terminal and the output terminal of the eighth logic circuit connected to the second input terminal. The third drive circuit amplifies the voltage output by the ninth logic circuit. The third insulating element is connected to the output of the third drive circuit. The third output circuit receives a signal based on the output signal of the third drive circuit via the third insulating element and outputs it to the outside.

[0193] <16> The communication device described in <15> has the configuration described subsequently. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, and the third signal is at the first logic level. The phase of the carrier signal input to the first signal generation circuit, the phase of the carrier signal input to the second signal generation circuit, and the phase of the carrier signal input to the third signal generation circuit are different from each other.

[0194] <17> The communication device described in <16> has the configuration described subsequently. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, and a second inverter. The second OR circuit has a first signal input to the first input terminal, a second signal input to the second input terminal, and a third signal input to the third input terminal. The second NAND circuit has the output terminal of the second OR circuit connected to the first input terminal. The first inverter has the output terminal of the second NAND circuit connected to the input terminal. The second inverter has the output terminal of the first inverter connected to the input terminal and the output terminal connected to the second input terminal of the second NAND circuit. The output terminal of the second NAND circuit is connected to the third signal generation circuit. The output terminal of the first inverter is connected to the second signal generation circuit. The output terminal of the second inverter is connected to the first signal generation circuit.

[0195] <18> The communication device described in <15> further includes a fourth signal generation circuit, a fourth insulating element, and a fourth output circuit. The fourth signal generation circuit includes a fourth delay circuit, a tenth logic circuit, an eleventh logic circuit, a twelfth logic circuit, and a fourth drive circuit. The tenth logic circuit has a fourth signal input from outside the communication device to the first input terminal and a fourth signal via the fourth delay circuit input to the second input terminal. The eleventh logic circuit has the output terminal of the tenth logic circuit connected to the first input terminal and a carrier signal input to the second input terminal. The twelfth logic circuit has a fourth signal input to the first input terminal and the output terminal of the eleventh logic circuit connected to the second input terminal. The fourth drive circuit amplifies the voltage output by the twelfth logic circuit. The fourth insulating element is connected to the output of the fourth drive circuit. The fourth output circuit receives a signal based on the output signal of the fourth drive circuit via the fourth insulating element and outputs it to the outside.

[0196] <19> The communication device described in <18> has the configuration described subsequently. The oscillator outputs a carrier signal when at least one of the first signal, the second signal, the third signal, and the fourth signal is at the first logic level. The phase of the carrier signal input to the first signal generation circuit, the phase of the carrier signal input to the second signal generation circuit, the phase of the carrier signal input to the third signal generation circuit, and the phase of the carrier signal input to the fourth signal generation circuit are different from each other.

[0197] The communication device described in <20> <19> has the configuration described below. The oscillator includes a second OR circuit, a second NAND circuit, a first inverter, a second inverter, and a third inverter. The second OR circuit has a first signal input to its first input terminal, a second signal input to its second input terminal, a third signal input to its third input terminal, and a fourth signal input to its fourth input terminal. The second NAND circuit has the output terminal of the second OR circuit connected to its first input terminal. The first inverter has the output terminal of the second NAND circuit connected to its input terminal. The second inverter has the output terminal of the first inverter connected to its input terminal and its output terminal connected to the second input terminal of the second NAND circuit. The third inverter has the output terminal of the second inverter connected to its input terminal. The output terminal of the second NAND circuit is connected to a fourth signal generation circuit. The output terminal of the first inverter is connected to a second signal generation circuit. The output terminal of the second inverter is connected to a first signal generation circuit. The output terminal of the third inverter is connected to a third signal generation circuit.

[0198] <21> The communication device includes an oscillator, an Nth signal generation circuit, an Nth insulating element, an Nth receiving circuit, and an Nth output circuit. The oscillator outputs a carrier signal when at least one of the first signal and the second signal input from the outside is at the first logic level. The Nth signal generation unit generates a first pulse signal when detecting that the first logic level of the Nth signal (N is an integer greater than or equal to 1) among a plurality of signals, and the carrier signal is behind the first pulse signal, and outputs a pulse signal such that the carrier signal stops when the Nth signal becomes the second logic level. The Nth driving circuit amplifies the output signal of the Nth signal generation unit. The Nth insulating element is connected to the output of the Nth driving circuit. The Nth receiving circuit receives a signal based on the output signal of the Nth driving circuit via the Nth insulating element and demodulates the signal from the received signal. The Nth output circuit outputs a signal based on the output signal of the Nth receiving circuit to the outside.

[0199] Although some embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

Explanation of Reference Numerals

[0200] 1... Communication device, 10... Input circuit, 20... RF generator, 21... OR circuit, 22... NAND circuit, 23 - 25... Inverters, 30... Signal generation circuit, 31... Signal generation unit, 32... Driving unit, 40... Insulating element, 41, 42... Coils, 43, 44... Capacitors, 50... Receiving circuit, 60... Output circuit, 311, 314, 316... AND circuits, 312... Delay circuit, 313... NAND circuit, 315... Inverter, 321... Driving circuit, 322 - 325... Transistors, 326... Current source, 330... First delay circuit, 331... Second delay circuit, 332... Clock transition detection circuit, 333... Pulse generation circuit, 334... NAND circuit, 335... Phase detection circuit, 336... Selector circuit, 337... OR circuit, 338... NOR circuit, CP1, CP2... Chips, CS... Carrier signal

Claims

1. An oscillator that outputs a first carrier signal and a second carrier signal when at least one of a first input signal and a second input signal input from the outside is at a first logic level; a first delay circuit; a first logic circuit having the first input signal input to a first input terminal and the first input signal via the first delay circuit input to a second input terminal; a second logic circuit having an output terminal of the first logic circuit connected to the first input terminal and the first carrier signal input to the second input terminal; a third logic circuit having the first input signal input to the first input terminal and an output terminal of the second logic circuit connected to the second input terminal; and a first drive circuit that amplifies a voltage output by the third logic circuit, the first signal generation circuit including the same; a second delay circuit; a fourth logic circuit having the second input signal input to a first input terminal and the second input signal via the second delay circuit input to a second input terminal; a fifth logic circuit having an output terminal of the fourth logic circuit connected to the first input terminal and the second carrier signal input to the second input terminal; a sixth logic circuit having the second input signal input to the first input terminal and an output terminal of the fifth logic circuit connected to the second input terminal; and a second drive circuit that amplifies a voltage output by the sixth logic circuit, the second signal generation circuit including the same; a first insulating element connected to an output of the first drive circuit; a second insulating element connected to an output of the second drive circuit; a first output circuit that receives, via the first insulating element, a signal based on an output signal of the first drive circuit and outputs the signal to the outside; a second output circuit that receives, via the second insulating element, a signal based on an output signal of the second drive circuit and outputs the signal to the outside; A communication device comprising:

2. The first logic circuit, the third logic circuit, the fourth logic circuit, and the sixth logic circuit are AND circuits, The second logic circuit and the fifth logic circuit are NAND circuits, The communication device according to Claim 1.

3. The first signal generation circuit further includes a first inverter having an output terminal of the second logic circuit connected to an input terminal, and a seventh logic circuit having the first input signal input to a first input terminal and an output terminal of the first inverter connected to a second input terminal. The second signal generation circuit further includes a second inverter having an output terminal of the fifth logic circuit connected to an input terminal thereof, and an eighth logic circuit having the second input signal input to a first input terminal thereof and an output terminal of the second inverter connected to a second input terminal thereof. The first drive circuit differentially amplifies the output of the third logic circuit and the output of the seventh logic circuit. The second drive circuit differentially amplifies the output of the sixth logic circuit and the output of the eighth logic circuit. The communication device according to claim 1 or claim 2.

4. The phases of the first carrier signal and the second carrier signal are different. The communication device according to any one of claims 1 to 3.

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