Current-biased tunable qubit

Abstract

Techniques for designing, fabricating, and utilizing current-biased tunable qubits are presented. The qubit device can include a first Josephson junction (JJ) located along a first current path of the device and a second and third JJ coupled in series along a second current path parallel to the first current path, where the second and third JJs facilitate frequency control of the device. The area of ​​the first JJ can be larger than the area of ​​each of the second and third JJs, thereby increasing the current division ratio between the first and second current paths. The device can include a capacitor including a first terminal associated with the second and third JJs and a second terminal associated with ground. Alternatively, a high kinetic inductance wire can be used in the first current path in place of the JJs.

Description

[Technical Field]

[0001] The present disclosure relates to quantum circuits, and more particularly to current-biased tunable qubits. Summary of the Invention

[0002] The following presents a summary intended to provide a basic understanding of one or more embodiments of the disclosed subject matter. This summary is not intended to identify key or critical elements, nor is it intended to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, systems, devices, structures, methods, apparatus, and / or computer program products are presented that can facilitate the creation, design, or utilization of current-biased tunable qubits, or combinations thereof.

[0003] According to an embodiment, a device can include a first Josephson junction located along a first current path of the device. The device can also include a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path.

[0004] Another embodiment relates to a method that can include forming a first Josephson junction along a first current path of a device. The method can also include forming a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path.

[0005] Further embodiments relate to qubit devices that can include a high kinetic inductance wire located along a first current path of the device, the high kinetic inductance wire having a kinetic inductance level that meets a defined threshold kinetic inductance level. The qubit device can also include a first Josephson junction and a second Josephson junction coupled in series along a second current path of the device that is parallel to the first current path.

[0006] These and other features will become apparent from the following detailed description of exemplary embodiments, which description should be read in conjunction with the accompanying drawings.

[0007] The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the U.S. Patent Office upon request and payment of the necessary fee. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 illustrates an example non-limiting device that may be utilized to provide desirable current-biased frequency adjustment in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 2] FIG. 10 illustrates an exemplary graph of frequency (e.g., qubit frequency) of a device as a function of current in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 3] FIG. 10 illustrates an exemplary graph of inductance of a device as a function of current in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 4]FIG. 10 illustrates exemplary graphs of design curves for a device (e.g., a current-biased, frequency-tunable qubit device) for first, second, and third Josephson junctions of various sizes in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 5] FIG. 10 illustrates exemplary graphs of design curves for a device (e.g., a current-biased, frequency-tunable qubit device) for first, second, and third Josephson junctions of various sizes in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 6] FIG. 10 illustrates exemplary graphs of design curves for a device (e.g., a current-biased, frequency-tunable qubit device) for first, second, and third Josephson junctions of various sizes in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 7] FIG. 10 illustrates exemplary graphs of design curves for a device (e.g., a current-biased, frequency-tunable qubit device) for first, second, and third Josephson junctions of various sizes in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 8] FIG. 1 illustrates an exemplary device that can be utilized to provide desirable current-biased frequency adjustment and that can employ low-pass filters and / or current splitters to facilitate reducing the device's sensitivity to electrical noise and Purcell losses in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 9] FIG. 10 shows an exemplary graph of qubit frequency of a device as a function of input current in various embodiments where the device includes a low-pass filter component and a current splitter component, only a current splitter component, or neither a low-pass filter component nor a current splitter component. [Figure 10]FIG. 10 shows an exemplary graph of device anharmonicity as a function of input current in various embodiments where the device includes a low-pass filter component and a current splitter component, includes only a current splitter component, or includes neither a low-pass filter component nor a current splitter component. [Figure 11] FIG. 10 illustrates an exemplary graph of the T1 Purcell bound of a device as a function of input current in various embodiments where the device includes a low pass filter component and a current splitter component, includes only a current splitter component, or includes neither a low pass filter component nor a current splitter component. [Figure 12] FIG. 10 illustrates an example graph of desired frequency T2* of a device as a function of input current in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 13] FIG. 1 illustrates an example device that can be utilized to provide desirable current-biased frequency tuning, that has desirably low mutual inductance, and that can have a desirably modified geometry to also have desirably reduced sensitivity to noise, in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 14] FIG. 10 illustrates an example graph of magnetic flux noise of a device (e.g., a current-biased, frequency-tunable device) as a function of spatial dimension Y of a circuit loop of the device for various dimension values of spatial dimension X of the circuit loop of the device and width of a first current path in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 15] 10A-10C illustrate example graphs of simulations of cross capacitance between input, capacitor, and ground charge islands of an example device for various spatial dimensions X and Y of the device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 16]10A-10C illustrate example graphs of simulations of cross capacitance between input, capacitor, and ground charge islands of an example device for various spatial dimensions X and Y of the device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 17] 10A-10C illustrate example graphs of simulations of cross capacitance between input, capacitor, and ground charge islands of an example device for various spatial dimensions X and Y of the device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 18] 10A-10C illustrate exemplary graphs of respective simulations of self-resonant frequency from respective Josephson junction components as a function of dimension Y for various sizes of spatial dimension X of a device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 19] 10A-10C illustrate exemplary graphs of respective simulations of self-resonant frequency from respective Josephson junction components as a function of dimension Y for various sizes of spatial dimension X of a device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 20] 10A-10C illustrate exemplary graphs of respective simulations of self-resonant frequency from respective Josephson junction components as a function of dimension Y for various sizes of spatial dimension X of a device in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 21] FIG. 1 illustrates an example non-limiting device that can employ high kinetic inductance wires in conjunction with Josephson junctions to facilitate desirable current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 22] FIG. 10 illustrates an exemplary graph of frequency (e.g., qubit frequency) of a device as a function of current in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 23]FIG. 1 is a flow diagram illustrating an example, non-limiting method for forming a device that can be utilized to provide desirable current-biased frequency adjustment in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 24] FIG. 1 is a flow diagram illustrating an example, non-limiting method for forming low-pass filter and / or current splitter components on a device that can be utilized to facilitate providing desirable current-biased frequency adjustment and reducing the device's sensitivity to noise and parcel losses in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 25] FIG. 10 is a flow diagram illustrating an exemplary, non-limiting method for modifying or structuring the geometry of a device's circuitry that may be utilized to facilitate providing desirable current-biased frequency tuning, reducing the device's sensitivity to noise, and having desirably low mutual inductance, in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 26] FIG. 1 is a flow diagram illustrating an exemplary, non-limiting method for forming a device that can employ high kinetic inductance wires in conjunction with Josephson junctions to facilitate desirable current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. [Figure 27] FIG. 1 illustrates a block diagram of an exemplary non-limiting operating environment that can facilitate one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following detailed description is exemplary only and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Technical Field" or "Summary" sections or in the "Detailed Description" section.

[0010] One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It will be apparent, however, that one or more embodiments may be practiced in various instances without these specific details.

[0011] Frequency-tunable qubit devices can be useful and desirable in many quantum computing architectures. They can be used for parametric operation or, for example, as tunable coupling devices. It can be desirable (e.g., ideal or optimal) for frequency-tunable qubit devices to have low loss and high coherence.

[0012] Frequency-tunable devices exist based on superconducting quantum interference devices (SQUIDs) that can be tuned using magnetic fields generated on-chip or using external coils. While tunable qubit devices using magnetically tuned SQUIDs are possible, these devices can be deficient in many ways because they can suffer from undesirable universal magnetic flux noise and / or magnetic crosstalk, or they can require relatively high, undesirable levels of current (e.g., approximately 1 milliampere (mA)) to operate.

[0013] As a result, it may be desirable to have frequency tunable devices that do not suffer from these or other imperfections, or both. For example, it may be desirable to create, realize, or develop desirably designed current controlled qubits (e.g., current controlled couplers) that can have higher performance, be more efficient (e.g., by utilizing or requiring less current to achieve a desired or similar tuning range as a SQUID-based frequency tunable device), be desirably small, and be less sensitive to magnetic flux noise and magnetic crosstalk.

[0014] As such, various embodiments described herein relate to techniques for designing, creating, or utilizing, or a combination thereof, current-biased, frequency-tunable qubits. In some embodiments, a device (e.g., a qubit device) can include a first Josephson junction located along a first current path of the device, and a second Josephson junction and a third Josephson junction can be coupled in series along a second current path parallel to the first current path, where the second and third Josephson junctions can facilitate controlling the frequency of the device. In particular embodiments, the device can be a transmon qubit device. There can also be a first inductive component (e.g., a first wire having a first amount of inductance) located along the first current path and a second inductive component (e.g., a second wire having a second amount of inductance) located along the second current path. The device can also include a capacitor component (e.g., a capacitor) that can include a first terminal associated with the second and third Josephson junctions and a second terminal associated with device ground.

[0015] In some embodiments, the area of the first Josephson junction can be larger (e.g., significantly larger) than the area of each of the second and third Josephson junctions, and the current division ratio between the first current path and the second current path can be increased based at least in part on the area of the first Josephson junction being larger than the areas of the second and third Josephson junctions. The frequency of the device can be controlled based at least in part on the amount of current applied to the device and the placement of the second and third Josephson junctions relative to the first Josephson junction.

[0016] Alternatively (or additionally), in other embodiments, a device can include a high kinetic inductance wire in the first current path instead of (or in addition to) a Josephson junction. For example, a device (e.g., a qubit device) can include a high kinetic inductance wire located along the first current path of the device, where the high kinetic inductance wire can have a kinetic inductance level that can meet a defined threshold kinetic inductance level. The device can also include a first Josephson junction and a second Josephson junction that can be coupled in series along a second current path of the device that is parallel to the first current path. The first Josephson junction and the second Josephson junction can facilitate tuning the frequency of the device.

[0017] There may also be a first inductive component (e.g., a first wire having a first amount of inductance (in addition to the inductance of the high kinetic inductance wire)) located along the first current path, and a second inductive component (e.g., a second wire having a second amount of inductance) located along the second current path. The device may also include a capacitive component (e.g., a capacitor) that may include a first terminal associated with the first and second Josephson junctions and a second terminal associated with device ground.

[0018] The frequency of the qubit device can be tuned based at least in part on the amount of current applied to the device and the placement of the first and second Josephson junctions relative to the high kinetic inductance wire. A current division ratio between the first and second current paths can be based at least in part on the relationship between the high kinetic inductance wire, the first Josephson junction, and the second Josephson junction.

[0019] These and other aspects and embodiments of the disclosed subject matter will now be described with reference to the drawings.

[0020] 1 shows a diagram of an exemplary, non-limiting device 100 that may be utilized to provide desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. In some embodiments, device 100 may be a qubit device (e.g., a qubit device capable of current-biased frequency tuning), such as, for example, a transmon qubit device.

[0021] The device 100 may include a first Josephson junction component 102 (JJ1) that may be located along a first current path 104 that may have a first current (I1) (e.g., when current is supplied to the device 100). The first current path 104 may also include a first inductive component 106 that may be associated with the first Josephson junction component 102. The first inductive component 106 may be or may comprise a first wire of a desired conductive material, and the first inductive component 106 may have a first level of inductance (L1). A Josephson junction may be a quantum mechanical device that may include two superconducting components (e.g., superconducting electrodes) that may be separated from each other by a relatively thin barrier (e.g., a barrier formed of a non-superconducting or insulating material), where the barrier may be or include, for example, a relatively thin insulating tunnel barrier, a desired metallic material, a semiconductor, or a desired magnetic material (e.g., a ferromagnet).

[0022] Device 100 may also include a second Josephson junction component 108 (JJ2) and a third Josephson junction component 110 (JJ3) that may be coupled in series along a second current path 112 in parallel with first current path 104, which may have a second current (I2) (e.g., when current is supplied to device 100), and as described in further detail herein, second Josephson junction component 108 and third Josephson junction component 110 may facilitate controlling the frequency of device 100. For example, if a current source (e.g., a current generator component) is used to control (e.g., adjust or tune) the frequency (e.g., qubit frequency) of device 100 and the second Josephson junction component 108 and third Josephson junction component 110 are controlled relative to the current source, then second Josephson junction component 108 and third Josephson junction component 110 may be in series with each other in second current path 112. That is, from the perspective of a current source, the second Josephson junction component 108 and the third Josephson junction component 110 can be in series with each other. The second current path 112 can also include a second inductive component 114 that can be associated with the second Josephson junction component 108 and the third Josephson junction component 110. The second inductive component 114 can be or comprise a second wire of a desired conductive material, and the second inductive component 114 can have a second level of inductance (L2). The first level of inductance of the first inductive component 106 can include, for example, the self-inductance or effective inductance of the first inductive component 106 (e.g., the self-inductance or effective inductance of the first wire), and the second level of inductance of the second inductive component 114 can include, for example, the self-inductance or effective inductance of the second inductive component 114 (e.g., the self-inductance or effective inductance of the second wire).

[0023] The device 100 may also include a capacitor component 116 (e.g., a capacitor) that may include a first terminal associated with (e.g., connected to) the second Josephson junction component 108 and the third Josephson junction component 110 and a second terminal that may be associated with (e.g., connected to) a ground 118 of the device 100. When considering the second Josephson junction component 108 and the third Josephson junction component 110 from the perspective of the capacitor component 116 (e.g., a qubit capacitor) of the device 100, the second Josephson junction component 108 and the third Josephson junction component 110 appear to be in parallel with respect to the capacitor component 116, but again, from the perspective of a current source, the second Josephson junction component 108 and the third Josephson junction component 110 may be coupled in series with each other in the second current path 112. In one non-limiting example, the capacitor component 116 can be 60 femtofarads (fF), although capacitors of other desirable capacitances greater than or less than 60 fF can be utilized in the device 100 as needed.

[0024] The device 100 may also include a current generator component 120 (e.g., a current pulse generator) capable of generating a desired current having a desired current level (e.g., a current pulse having a desired pulse shape). The current generator component 120 may apply or provide a desired current bias to a circuit loop (e.g., a superconducting circuit loop) including the first current path 104 and the second current path 112 to facilitate controlled tuning of the frequency of the device 100. A first portion of the current may flow through the first current path 104 and a second portion of the current may flow through the second current path 112 based at least in part on the respective sizes (e.g., respective areas) of the first Josephson junction component 102 associated with the first current path 104 and the second Josephson junction component 108 and the third Josephson junction component 110 associated with the second current path 112. As the current portions flow through the first current path 104 and the second current path 112, the current portions can be used to change the phase differences between the Josephson junctions (e.g., 102, 108, and 110), and the phase differences (e.g., superconducting phase differences) between the Josephson junctions can be represented by δ1 for the first Josephson junction component 102, δ2 for the second Josephson junction component 108, and δ3 for the third Josephson junction component 110. When the phase differences of the Josephson junctions are changed, the inductance (e.g., amount or level of inductance) of the Josephson junctions can be changed accordingly.

[0025] In some embodiments, the area of the first Josephson junction component 102 can be larger (e.g., significantly larger) than the area of each of the second Josephson junction component 108 and the third Josephson junction component 110. For example, the first area of the first Josephson junction component 102 can be approximately 100 times larger or smaller (e.g., 50 times, 60 times, 70 times, ..., 110 times, 120 times, ...) larger than the second area of the second Josephson junction component 108 and the third area of the third Josephson junction component 110. In certain embodiments, the sizes of the second Josephson junction component 108 and the third Josephson junction component 110 can be the same, although in other embodiments, the sizes of the second Josephson junction component 108 and the third Josephson junction component 110 can differ from one another, if desired.

[0026] The current division ratio (e.g., I2 / I1) between the first current path 104 and the second current path 112 can be increased based at least in part on the area of the first Josephson junction component 102 being greater than the areas of the second Josephson junction component 108 and the third Josephson junction component 110. The frequency of the device 100 can be controlled (e.g., managed, regulated, changed, or tuned) based at least in part on the amount of current applied to the device 100 by the current generator component 120, the placement of the second Josephson junction component 108 and the third Josephson junction component 110 relative to the first Josephson junction component 102, and the size (e.g., area) of the first Josephson junction component 102 relative to (e.g., compared to) the size of the second Josephson junction component 108 and the third Josephson junction component 110.

[0027] Device 100, which may be particularly desirable and capable of current-controlled frequency tuning, may utilize three Josephson junctions (e.g., first, second, and third Josephson junction components 102, 108, and 110) arranged in the circuitry of device 100, such that an applied current (e.g., supplied from current generator component 120) through the Josephson junctions can be used to vary the inductance of the Josephson junctions, such that I=I c sinδ, and the induction of the Josephson junction (L JJ ) can be determined in equation (Equation (1)) for example as follows:

[0028]

number

[0029] However, conventional tunable qubit or coupler devices employing Josephson junctions tune the qubit frequency using a magnetic field generated from a current line, where the current loop is electrically isolated from the circuit containing the Josephson junction and is associated or coupled to the circuit containing the Josephson junction only through mutual inductance from the magnetic field generated by the current loop. There is no direct current path from the current bias to the Josephson junction. In such conventional tunable qubit or coupler devices, a magnetic field (e.g., a magnetic flux passed through a SQUID loop) can change the phase difference of the Josephson junction and thus the Josephson junction inductance, thus enabling a change in the qubit frequency. That is, in such conventional tunable qubit or coupler devices, a magnetic field (e.g., a magnetic flux passed through a SQUID loop) controls the phase difference associated with the Josephson junction inductance, which can be used to tune the qubit or coupler frequency.

[0030] In contrast, the disclosed subject matter, including device 100 (e.g., a device capable of current-controlled frequency tuning), does not need to use a magnetic field generated from a current line to tune the qubit frequency. Instead, the disclosed subject matter (e.g., device 100) can utilize an applied current (e.g., a current supplied from current generator component 120) through a Josephson junction (e.g., first, second, or third Josephson junction component 102, 108, or 110) to modify the inductance of the Josephson junction, as described in further detail herein, to facilitate enabling desired (e.g., improved, adequate, acceptable, or optimal) tuning of the device's frequency.

[0031] 2 and 3 (together with FIG. 1 ), in accordance with various aspects and embodiments of the disclosed subject matter, FIG. 2 illustrates an example graph 200 of the frequency (e.g., qubit frequency) of device 100 in gigahertz (GHz) as a function of current in microamperes (μA), and FIG. 3 illustrates an example graph 300 of the inductance of device 100 in nanohenries (nH) as a function of current in microamperes. In a non-limiting example, the area of first Josephson junction component 102 can be approximately 100 times greater than the areas of second Josephson junction component 108 and third Josephson junction component 110. For second Josephson junction component 108 and third Josephson junction component 110, the current I C2 can be 20 nanoamperes (nA), and the current I C3 can be 20 nA. The current I associated with the first Josephson junction component 102 C1can be 2000 nA. The capacitance of the capacitor component 116 can be 65 fF. The inductance levels of the first level inductance (L1) and the second level inductance (L2) can each be 12 picohenries (pH). When the first Josephson junction component 102 is positioned and sized relative to the second Josephson junction component 108 and the third Josephson junction component 110 as described herein, the first Josephson junction component 102 can facilitate (e.g., enable) a desired increase in the current division ratio (I2 / I1) and can provide a desired current bias effect for the second Josephson junction component 108 and the third Josephson junction component 110. For example, the first Josephson junction component 102 may be desirably utilized to increase the current division ratio (I2 / I1), and a majority of the tuning effect (e.g., the effect of current-biased tuning) of the device 100 may be attributable (e.g., generated) in part by the second Josephson junction component 108 and the third Josephson junction component 110.

[0032] In graph 200 of FIG. 2, the current I in From plot 202 of frequency as a function of μA, it can be observed that for a 10% tuning from a desired frequency spot (e.g., a sweet spot frequency such as about 6.65 GHz at 0.0 μA), device 100 (e.g., a current-biased qubit device) can involve the use of only about 1.85 μA. In contrast, a standard field-based device (e.g., a transmon device tuned by a magnetic field) may require significantly more current (e.g., up to 34 μA) to achieve a 10% tuning from the desired frequency spot (e.g., the sweet spot frequency). The sweet spot frequency can be the top of the curve in plot 202 or can be another desired frequency.

[0033] 3, graph 300 may include a plot 302 of the inductance of first Josephson junction component 102 as a function of current through device 100. Graph 300 may also include plots 304 and 306 of the inductance of second Josephson junction component 108 and third Josephson junction component 110 as a function of current through device 100 (in graph 300, plot 304 and plot 306 overlap, or at least substantially overlap, each other, so that plot 304 and plot 306 essentially appear as a single line graph).

[0034] In graph 300, it can be observed from plot 302 that the inductance of first Josephson junction component 102 can be close to 0.5 nH (e.g., can range between about 0.15 nH and about 0.9 nH) over a range of currents from −2.0 μA to 2.0 μA. It can also be observed from plots 304 and 306 that the inductances of second Josephson junction component 108 and third Josephson junction component 110 can be the same, or at least substantially the same, can be relatively higher than the inductance of first Josephson junction component 102, and can vary more over the range of currents compared to the inductance of first Josephson junction component 102. For example, the inductance of the second Josephson junction component 108 and the third Josephson junction component 110 may each be approximately 17.0 nH at 0.0 μA and gradually increase to approximately 22.0 nH as the current changes from 0.0 μA to 2.0 μA or from 0.0 μA to −2.0 μA.

[0035] The following analysis of device 100 can provide further details regarding the three Josephson junction couplers of device 100. The first level inductance (L1) and the second level inductance (L2) can be the geometric inductances of the two branches of the circuit of device 100. The magnetic fluxes (Φ1 and Φ2) in the circuit of device 100 due to the first current (I1) and the second current (I2) can be determined in equations (2) and (3), respectively, as follows:

number

number

[0036] The total magnetic flux (Φ T ) can be determined in equation (4) as follows:

number

[0037] Due to the set of topological conditions from single-valuedness, we have:

[0038]

number

[0039]

number

[0040] Using the current relationship for a Josephson junction (assuming a critical current for the device below) and Kirchhoff's Current Law (KCL), we can proceed from equations (4), (5), and (6) to follow the equation below:

[0041]

number

[0042]

number

[0043]

number

number

number

number

[0044] 4-7 (in conjunction with FIG. 1 ), which illustrate exemplary graphs 400, 500, 600, and 700 of respective design curves for a device (e.g., a current-biased, frequency-tunable qubit device) for first, second, and third Josephson junction components of various sizes, in accordance with various aspects and embodiments of the disclosed subject matter. By adjusting the sizes of first Josephson junction component 102, second Josephson junction component 108, and third Josephson junction component 110, the tuning range and sensitivity of device 100 can be altered (e.g., varied). In that regard, for graphs 400, 500, 600, and 700 of FIGS. 4-7, I C = r × 20 nA, and I Cr can be the critical current of the Josephson junction, and a particular value of r for a particular Josephson junction can be related to the size of that particular Josephson junction. The sizes of the second Josephson junction component 108 and the third Josephson junction component 110 are only increased to a maximum of 5 (e.g., r2 = 5 or r3 = 5, or both) to prevent undesirable capacitive loading of the qubit capacitor (e.g., capacitor component 116). Note that in each of graphs 400, 500, 600, and 700 in Figures 4-7, the qubit capacitance is varied to a maximum of approximately 400 fF to enable maintaining a maximum qubit frequency of approximately 6 GHz across all of graphs 400, 500, 600, and 700. Also, in all models shown in graphs 400, 500, 600, and 700, the Josephson junction capacitance (e.g., 2 fF / 20 nA) is considered. Based at least in part on a design curve (eg, graphs 400, 500, 600, or 700, or other design curves that may be derived from the disclosed subject matter), a desired tuning range or a desired frequency may be determined.

[0045] FIG. 4 illustrates a graph of the current I for various values (e.g., size values) of r1 of the first Josephson junction component 102 when the values of r2 of the second Josephson junction component 108 and r3 of the third Josephson junction component 110 are each set to 1 in accordance with various aspects and embodiments of the disclosed subject matter. in 4 shows an example graph 400 of design curves relating frequency (e.g., qubit frequency) of device 100 as a function of r. In graph 400, the value of r can range from 1 to 100, and r and r3 are each equal to 1. Graph 400 shows plot 402 when r1=1, plot 404 when r1=5, plot 406 when r1=10, plot 408 when r1=25, plot 410 when r1=50, and plot 412 when r1=100.

[0046] FIG. 5 illustrates the current I for various values of r1 of the first Josephson junction component 102 when the value of r2 of the second Josephson junction component 108 is set to 1 and the value of r3 of the third Josephson junction component 110 is set to 5 in accordance with various aspects and embodiments of the disclosed subject matter. in 1 shows an illustration of an example graph 500 of design curves relating to frequency (e.g., qubit frequency) of device 100 as a function of r. Graph 500 shows plot 502 for r=1, plot 504 for r=5, plot 506 for r=10, plot 508 for r=25, plot 510 for r=50, and plot 512 for r=100.

[0047] FIG. 6 illustrates a graph of the current I for various values of r1 of the first Josephson junction component 102 when the value of r2 of the second Josephson junction component 108 is set to 5 and the value of r3 of the third Josephson junction component 110 is set to 1 in accordance with various aspects and embodiments of the disclosed subject matter. in 6 shows an example graph 600 of design curves relating to frequency (e.g., qubit frequency) of device 100 as a function of r. Graph 600 shows plot 602 for r=1, plot 604 for r=5, plot 606 for r=10, plot 608 for r=25, plot 610 for r=50, and plot 612 for r=100.

[0048] FIG. 7 illustrates the r of the second Josephson junction component 108 in accordance with various aspects and embodiments of the disclosed subject matter. 2、 The current I for various values of r1 of the first Josephson junction component 102 when the value of r3 of the third Josephson junction component 110 is set to 5, in7 shows an example graph 700 of design curves relating to frequency (e.g., qubit frequency) of device 100 as a function of r. Graph 700 shows plot 702 for r=1, plot 704 for r=5, plot 706 for r=10, plot 708 for r=25, plot 710 for r=50, and plot 712 for r=100.

[0049] As can be observed from each plot of graphs 400, 500, 600, and 700, the ratio of I2 / I1 can be further increased by reducing the size of the first Josephson junction component 102 (e.g., by reducing the value of r1), resulting in a larger frequency tuning range for the qubit device. However, even if the area of the first Josephson junction component 102 is selected to be approximately 100 times larger than the areas of the second Josephson junction component 108 and the third Josephson junction component 110, the first Josephson junction component 102 can desirably increase the current division ratio (e.g., the ratio of I2 / I1) of the device 100, resulting in a desirable frequency tuning range for the device 100.

[0050] In some examples, device 100 may be sensitive to Purcell loss and electrical noise, which may be undesirable. In some embodiments, to facilitate reducing the sensitivity of a device (e.g., a current-biased qubit device), a low-pass filter and / or current splitter may be utilized that can desirably (e.g., adequately, acceptably, or optimally) reduce the sensitivity of the device to Purcell loss and electrical noise.

[0051] In that regard, FIG. 8 illustrates a diagram of an example device 800 (e.g., an example circuit of a device) that can be utilized to provide desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter and that can employ a low-pass filter and / or a current splitter to facilitate reducing the device 800's sensitivity to electrical noise and Purcell loss. In some embodiments, the device 800 can be a qubit device (e.g., a qubit device capable of current-biased frequency tuning), such as a transmon qubit device. The device 800 can include a first Josephson junction component 102 (JJ1) that can be located along a first current path 104 that can have a first current (I1). The first current path 104 can also include a first inductive component 106 that can be associated with the first Josephson junction component 102. The first inductive component 106 can be or can comprise a first wire of a desired conductive material, and the first inductive component 106 can have a first level of inductance (L1).

[0052] The device 800 may also include a second Josephson junction component 108 (JJ2) and a third Josephson junction component 110 (JJ3), which may be coupled in series along a second current path 112 in parallel with the first current path 104, the second current path 112 may have a second current (I2), and as described in further detail herein, the second Josephson junction component 108 and the third Josephson junction component 110 may facilitate controlling the frequency of the device 800. The second current path 112 may also include a second inductive component 114, which may be associated with the second Josephson junction component 108 and the third Josephson junction component 110. The second inductive component 114 may be or may comprise a second wire of a desired conductive material, and the second inductive component 114 may have a second level of inductance (L2).

[0053] Device 800 may also include a capacitor component 116 that may include a first terminal associated with second Josephson junction component 108 and third Josephson junction component 110 and a second terminal associated with ground 118 of device 800. Device 800 may further include a current generator component 120 that may generate a desired current having a desired current level (e.g., a current pulse having a desired pulse shape).

[0054] In some embodiments, the area of the first Josephson junction component 102 can be larger (e.g., more than 100 times larger, or less than 100 times larger) than the area of each of the second Josephson junction component 108 and the third Josephson junction component 110. The current division ratio (e.g., I2 / I1) between the first current path 104 and the second current path 112 can be increased based at least in part on the area of the first Josephson junction component 102 being larger than the areas of the second Josephson junction component 108 and the third Josephson junction component 110. The frequency of device 800 can be controlled based at least in part on the amount of current applied to device 800 by current generator component 120, the arrangement of second Josephson junction component 108 and third Josephson junction component 110 relative to first Josephson junction component 102, and the size (e.g., area) of first Josephson junction component 102 relative to (e.g., compared to) the size of second Josephson junction component 108 and third Josephson junction component 110.

[0055] In particular embodiments, device 800 may include a low-pass filter component 802, an input of which may be associated (e.g., connected) to the output of current generator component 120, and an output of which may be associated with first current path 104 and second current path 112 (e.g., a node in a circuit may be associated with first current path 104 and second current path 112). In some embodiments, low-pass filter component 802 may be a 1.4 GHz low-pass filter, although in other embodiments, low-pass filter component 802 may be designed and constructed to have a low-pass cutoff frequency higher or lower than 1.4 GHz, as desired. Low-pass filter component 802 may include a capacitor component 804 and an inductor component 806, where inductor component 806 may be connected in series between current generator component 120 and a load (e.g., Josephson junction components 102, 108, and 110 and capacitor component 116), and capacitor component 804 may be in parallel with current generator component 120 and the load, with a first terminal connected to current generator component 120 and inductor component 806 and a second terminal connected to ground 118. In an example embodiment, capacitor component 804 may have a capacitance of 1.5 picofarads (pF) and inductor component 806 may have an inductance of 8 nH, although in other embodiments, capacitor component 804 may have a capacitance greater than or less than 1.5 pF and / or inductor component 806 may have an inductance greater than or less than 8 nH, as desired.

[0056] In some embodiments, additionally or alternatively, device 800 may include a current splitter component 808 that may be connected at a first terminal to inductor component 806, first current path 104, and second current path 112, and that may be connected at a second terminal to ground 118. Current splitter component 808 may split (e.g., divide) the current flowing from the output of low pass filter component 802 to first current path 104 and second current path 112 and redirect a portion of the current through current splitter component 808 to a ground plane (e.g., ground 118). In certain embodiments, current splitter component 808 may include an inductor component that may have a desired inductance, such as, for example, 12 pH or another desired inductance greater than or less than 12 pH. According to various embodiments, the current splitter component 808 can be on-chip (e.g., an integrated circuit (IC) chip) with the other components of the device 800, or the current splitter component 808 can be off-chip (e.g., located on a separate IC chip from all or some of the other components of the device 800) but lossless so as not to introduce additional undesirable noise into the device 800.

[0057] Quantum circuit analyzer tool (QuCAT) modeling of exemplary device 800 can illustrate certain characteristics of device 800. QuCAT can be used to derive a Hamiltonian for the circuit of device 800. The model of the circuit can include a low-pass filter component and a current splitter component, as described herein. Briefly referring to FIGS. 9 and 10 (in conjunction with FIG. 8), FIG. 9 illustrates a model of an input (e.g., source) current (I ) in various embodiments where the device includes a low-pass filter component 802 and a current splitter component 808, only a current splitter component 808, or neither a low-pass filter component 802 nor a current splitter component 808. in 10 shows a diagram of an exemplary graph 900 of qubit frequency of exemplary device 800 as a function of input current (in megahertz (MHz)). Figure 10 shows a diagram of an exemplary graph 1000 of anharmonicity (in megahertz (MHz)) of exemplary device 800 as a function of input current in various embodiments where the device includes low pass filter component 802 and current splitter component 808, includes only current splitter component 808, or includes neither low pass filter component 802 nor current splitter component 808.

[0058] With respect to the example graph 900 of FIG. 9, the graph 900 shows the input current (I in μA) when the device 800 does not include the low-pass filter component 802 or the current splitter component 808. inGraph 900 may include a plot 902 of the qubit frequency (in GHz) of exemplary device 800 as a function of input current when device 800 includes both lowpass filter component 802 and current splitter component 808. Graph 900 may also include a plot 904 of the qubit frequency of exemplary device 800 as a function of input current when device 800 includes both lowpass filter component 802 and current splitter component 808. Graph 900 may further include a plot 906 of the qubit frequency of exemplary device 800 as a function of input current when device 800 includes only current splitter component 808. (Note that in graph 900, plot 904 and plot 906 substantially overlap each other, resulting in plot 904 and plot 906 appearing as essentially a single line.) For analytical modeling, it is desirable that there be a good match in qubit frequency versus source current.

[0059] With respect to the example graph 1000 of FIG. 10, the graph 1000 shows the input current (I in μA) when the device 800 does not include the low-pass filter component 802 or the current splitter component 808. in Graph 1000 may include a plot 1002 of the anharmonicity (in MHz) of exemplary device 800 as a function of input current when device 800 includes both low pass filter component 802 and current splitter component 808. Graph 1000 may also include a plot 1004 of the anharmonicity of exemplary device 800 as a function of input current when device 800 includes both low pass filter component 802 and current splitter component 808. Graph 1000 may further include a plot 1006 of the anharmonicity of exemplary device 800 as a function of input current when device 800 includes only current splitter component 808. (Note that in graph 1000, plot 1004 and plot 1006 substantially overlap each other, resulting in plot 1004 and plot 1006 essentially appearing as a single line.)

[0060] QuCAT modeling can also be used to investigate current noise and Purcell loss in qubit devices. Current noise in qubit devices can cause relaxation, which can be described by the fluctuation-dissipation theorem, given by equation (10) as follows:

[0061]

number

number

number

[0062] The Purcell loss of a device such as device 800 (e.g., a qubit device) can be determined by admittance form or directly from QuCAT (e.g., for devices with T>3 milliseconds (ms) that include a low-pass filter component and a current splitter component). Briefly referring to FIG. 11 (in conjunction with FIG. 8), FIG. 11 illustrates the input (e.g., source) current (I in11 shows a diagram of an example graph 1100 of T1 parcel boundaries of the example device 800 as a function of input current (in μA) when the device 800 does not include a low pass filter component 802 or a current splitter component 808. The graph 1100 may include a plot 1102 of the T1 parcel boundaries of the example device 800 as a function of input current (in μA) when the device 800 does not include a low pass filter component 802 or a current splitter component 808. The graph 1100 may also include a plot 1104 of the T1 parcel boundaries of the example device 800 as a function of input current when the device 800 includes both a low pass filter component 802 and a current splitter component 808. The graph 1100 may further include a plot 1106 of the T1 parcel boundaries of the example device 800 as a function of input current when the device 800 includes only a current splitter component 808.

[0063] The Johnson noise sensitivity of device 800 can also be investigated. Because typically only a relatively small amount of current (e.g., a few μA) is utilized for frequency tuning of device 800, further attenuation can be added, if desired, compared to conventional qubits. Assuming an arbitrary waveform generator (AWG) supplying 5 volts (V) and approximately 100 mA, device 800 can be attenuated by 100 decibels (dB) if desired and still have 10 μA available for frequency tuning.

[0064] For example, in exemplary device 800, if there is 20 dB of attenuation on each of the 4K, 1K, and 100 mK plates, the noise current is

number

[0065] To facilitate investigating the sensitivity and power spectral density noise of a qubit device, for example, the following equations (Equations 11, 12, and 13) can be utilized as follows:

[0066]

number

[0067]

number

[0068]

number

[0069] If desired, in some embodiments, the sensitivity of device 800 may be reduced by design, or by adding a current splitter (e.g., current splitter component 808) that can divert a desired amount of current to the ground plane, as described herein, or both. For example, by diverting 10 times the current in device 800 (e.g., by design, current splitter component 808, or both), the sensitivity D may be reduced by a factor of 10, and the power spectral density noise S I can be reduced to 1 / 100, and T * 2=43.5 ms, while also achieving the desired suppression of parcel loss as described herein.

[0070] If we examine the change in qubit frequency for a relatively small change in magnetic flux, T * 2 can be estimated as a function of input current with different amounts of universal flux noise, for example, using equation (14) as follows:

[0071]

number

[0072] Referring briefly to FIG. 12 (in conjunction with FIG. 8), FIG. 12 illustrates a typical input (e.g., source) current (I in) as a function of the desired frequency (e.g., sweet spot frequency or other desired frequency) T * 2. Graph 1200 shows an example graph 1200 for A=10 -5 Φ 0 , the desired frequency (e.g., sweet spot frequency or other desired frequency) T * 2 (in seconds (s)) plot 1202. The graph 1200 can be used for -6 Φ 0 , the desired frequency (e.g., sweet spot frequency or other desired frequency) T * 2 plot 1204.

[0073] In accordance with various embodiments of the disclosed subject matter, the magnetic flux noise sensitivity and mutual inductance of a qubit device (e.g., device 100 or device 800) may be desirably reduced by the geometry of the device's components. Because the qubit device does not require magnetic field tuning or sufficiently large mutual inductance, the geometry of the qubit device may be modified to have a relatively small (e.g., very small) mutual inductance and also have reduced sensitivity to magnetic flux noise.

[0074] Referring to FIG. 13 , FIG. 13 shows a diagram of an example device 1300 that can be utilized to provide desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter, and that can have a desirably modified geometry to have desirably small mutual inductance and also desirably reduced sensitivity to noise (e.g., magnetic flux noise and / or other noise). The example device 1300 can be, for example, a current-biased qubit device. In some embodiments, the example device 1300 can be a current-biased transmon qubit device. The device 1300 is shown in a first view 1302 of the device 1300 and a second view 1304 (e.g., an exploded or enlarged view) of a portion of the device 1300 including a Josephson junction.

[0075] Device 1300 can include a first Josephson junction component 1306 (JJ1), a second Josephson junction component 1308 (JJ2), a third Josephson junction component 1310 (JJ3), a capacitor component 1312 (e.g., a qubit capacitor), a ground plane 1314 (e.g., ground), and an input 1316. Each component (e.g., 1306, 1308, 1310, 1312, 1314, and 1316) can be arranged in a circuit relative to one another, for example, as described herein with respect to device 100 of FIG. 1. For example, first Josephson junction component 1306 can be located along a first current path 1318 that can have a first current (I1) (e.g., when current is applied by a current generator component, e.g., via input 1316). The first current path 104 may also include a first inductive component (not explicitly shown in FIG. 13 ) that may be associated with the first Josephson junction component 1306. The first inductive component may be or may comprise a first wire of a desired conductive material, and the first inductive component may have a first level of inductance (L1). The second Josephson junction component 1308 and the third Josephson junction component 1310 may be coupled in series along a second current path 1320 that may be in parallel with the first current path 1318, and the second current path 1320 may have a second current (I2). The second current path 1320 may include a second inductive component (not explicitly shown in FIG. 13 ) that may be associated with the second Josephson junction component 1308 and the third Josephson junction component 1310. The second inductive component can be or can comprise a second wire of a desired conductive material, and the second inductive component can have a second level of inductance (L2).The capacitor component 1312 may include a first terminal associated with the second Josephson junction component 1308 and the third Josephson junction component 1310 (e.g., connected to a second current path 1320 therebetween), and a second terminal that may be associated with (e.g., connected to) a ground plane 1314.

[0076] Geometric characteristics of device 1300 may include a width 1322 (W) of first current path 1318 (e.g., a first wire of first current path 1318) and first Josephson junction component 1306, and dimensions X 1324 and Y 1326 of a space 1328 defined (e.g., surrounded by) first current path 1318, second current path 1320, first Josephson junction component 1306, second Josephson junction component 1308, third Josephson junction component 1310, and pads 1330 associated with capacitor component 1312 (e.g., pads or capacitor charge islands that may connect to capacitor component 1312).

[0077] According to various embodiments of the disclosed subject matter, the width 1322 (W) of the first current path 1318 and associated first Josephson junction component 1306, or the dimensions X 1324 and / or Y 1326 of the space 1328 (e.g., the space of the circuit loop of the device 1300), may be designed, changed, or adjusted so that the device 1300 has a desirably small (e.g., very small) mutual inductance (e.g., reduced mutual inductance) and / or also has a desirably reduced sensitivity to magnetic flux noise.

[0078] In that regard, it may be helpful to examine certain geometry design points related to magnetic flux noise. The mathematical relationship between magnetic flux, magnetic flux noise, dimension W 1322, and dimensions X 1324 and Y 1326 of space 1328 may be given, for example, by exemplary equation (15) as follows:

[0079]

number

[0080] In that regard, referring briefly to FIG. 14 (together with FIG. 13), FIG. 14 shows a diagram of an example graph 1400 of magnetic flux noise of a device as a function of dimension Y 1326 of space 1328 (e.g., dimension X of the circuit loop of the device) for various dimension values of dimension X 1324 of space 1328 (e.g., dimension X of the circuit loop of the device) and dimension W 1322 (e.g., width of the first current path of the device), in accordance with various aspects and embodiments of the disclosed subject matter. Example graph 1400 shows the magnetic flux noise of a device (e.g., device 1300) for X=24 micrometers (μm), Y=24 μm, and W=10.2 μm.

number

[0081] As can be observed from graph 1400, the flux noise of exemplary device 1300 can be significantly lower than the flux noise of conventional qubit devices. As can also be observed from graph 1400, the flux noise of device 1300 can be altered (e.g., reduced) by modifying (e.g., reducing (or increasing)) the dimensions X 1324 and / or Y 1326 of space 1328 of device 1300, or the dimension W 1322 of device 1300, or both. For example, as the size of dimension X 1324 of space 1328 is reduced, the flux noise of device 1300 can be reduced, and as the size of dimension Y 1326 of space 1328 is reduced (or the size of dimension W 1322 is increased, or both), the flux noise of device 1300 can be reduced.

[0082] Regarding the design of qubit devices, certain constraints on design geometry may exist. For example, one constraint on sizing (e.g., smaller loop size and larger width) for better (e.g., improved or enhanced) flux noise reduction of qubit devices may be cross capacitance, such as the cross capacitance between input charge island (1) 1332 and capacitor charge island (2) 1330 (e.g., pad 1330), the cross capacitance between input charge island (1) 1332 and ground charge island (3) 1334, and the cross capacitance between capacitor charge island (2) 1330 and ground charge island (3) 1334. This sizing may be limited by capacitances that do not change the resonant frequency of the Josephson junctions (e.g., first Josephson junction component 1306, second Josephson junction component 1308, or third Josephson junction component 1310, or a combination thereof).

[0083] Simulations using Q3D can enable the determination of cross capacitance between input charge island (1) 1332, capacitor charge island (2) 1330, and ground charge island (3) 1334. In that regard, briefly referring to FIGS. 15-17 (in conjunction with FIG. 13), FIGS. 15-17 show exemplary graph illustrations of respective simulations of cross capacitance between input charge island (1) 1332, capacitor charge island (2) 1330, and ground charge island (3) 1334 for various dimensions X and Y of device space 1328, in accordance with various aspects and embodiments of the disclosed subject matter. FIG. 15 shows an exemplary graph illustration 1500 of respective simulations of cross capacitance between input charge island (1) 1332 and capacitor charge island (2) 1330 as a function of dimension Y for various sizes of dimension X of device space 1328, in accordance with various aspects and embodiments of the disclosed subject matter. An exemplary graph 1500 shows the cross capacitance (C) between input charge island (1) 1332 and capacitor charge island (2) 1330 as a function of dimension Y for a dimension X=10 μm. 12 ) (in fF). The exemplary graph 1500 shows the cross capacitance C as a function of dimension Y for dimension X=15 μm. 12 Plot 1504 of cross capacitance C as a function of dimension Y for dimension X=20 μm 12 Plot 1506 of cross capacitance C as a function of dimension Y for dimension X = 25 μm 12 Plot 1508 of the cross capacitance C as a function of dimension Y for dimension X=30 μm. 12 It may also include a plot 1510 of:

[0084] 16 shows an illustration of an exemplary graph 1600 of simulations of cross capacitance between input charge island (1) 1332 and ground charge island (3) 1334 as a function of dimension Y for various sizes of dimension X of device space 1328 in accordance with various aspects and embodiments of the disclosed subject matter. The exemplary graph 1600 shows the cross capacitance (C) between input charge island (1) 1332 and ground charge island (3) 1334 as a function of dimension Y for dimension X=10 μm. 13 ) (in fF). The exemplary graph 1600 shows the cross capacitance C as a function of dimension Y for dimension X=15 μm. 13 Plot 1604 of cross capacitance C as a function of dimension Y for dimension X=20 μm 13 Plot 1606 of cross capacitance C as a function of dimension Y for dimension X = 25 μm 13 1608, and the cross capacitance C as a function of dimension Y for dimension X=30 μm. 13 It may also include a plot 1610 of:

[0085] 17 shows an illustration of an exemplary graph 1700 of simulations of cross capacitance between capacitor charge island (2) 1330 and ground charge island (3) 1334 as a function of dimension Y for various sizes of dimension X of device space 1328 in accordance with various aspects and embodiments of the disclosed subject matter. The exemplary graph 1700 shows the cross capacitance (C) between capacitor charge island (2) 1330 and ground charge island (3) 1334 as a function of dimension Y for dimension X=10 μm. 23 ) (in fF). The exemplary graph 1700 shows the cross capacitance C as a function of dimension Y for dimension X=15 μm. 23 Plot 1704 of cross capacitance C as a function of dimension Y for dimension X=20 μm 23 Plot 1706 of cross capacitance C as a function of dimension Y for dimension X = 25 μm 23Plot 1708 of the cross capacitance C as a function of dimension Y for dimension X=30 μm. 23 It may also include a plot 1710 of:

[0086] Simulations of the self-resonant frequency from each Josephson junction component due to cross capacitance can also be performed and examined, ranging from X=30 μm and Y=15 μm to X=10 μm and Y=0.1 μm. It can be observed in the following graphs of FIGS. 18-20 that even when varying the X and Y dimensions within the range from X=30 μm and Y=15 μm to X=10 μm and Y=0.1 μm, the self-resonant frequency resulting from each Josephson junction component due to cross capacitance is still acceptable, since the self-resonant frequency can typically be about 20 GHz or higher for a qubit device. With reference to FIGS. 18-20 (along with FIG. 13), FIGS. 18-20 show exemplary graphs of simulations of the self-resonant frequency from each Josephson junction component as a function of dimension Y for various sizes of dimension X of the device cavity 1328, in accordance with various aspects and embodiments of the disclosed subject matter. 18 shows an illustration of an example graph 1800 of a simulation of the self-resonant frequency from the first Josephson junction component 1306 (JJ1) as a function of dimension Y for various sizes of dimension X of the space 1328 of the device in accordance with various aspects and embodiments of the disclosed subject matter. The example graph 1800 may include a plot 1802 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X=10 μm, a plot 1804 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X=15 μm, a plot 1806 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X=20 μm, a plot 1808 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X=25 μm, and a plot 1810 of the self-resonant frequency from JJ1 as a function of dimension Y for dimension X=30 μm.

[0087] 19 shows an illustration of an example graph 1900 of a simulation of the self-resonant frequency from the second Josephson junction component 1308 (JJ2) as a function of dimension Y for various sizes of dimension X of the space 1328 of the device in accordance with various aspects and embodiments of the disclosed subject matter. The example graph 1900 may include a plot 1902 of the self-resonant frequency from JJ2 as a function of dimension Y for dimension X=10 μm, a plot 1904 of the self-resonant frequency from JJ2 as a function of dimension Y for dimension X=15 μm, a plot 1906 of the self-resonant frequency from JJ2 as a function of dimension Y for dimension X=20 μm, a plot 1908 of the self-resonant frequency from JJ2 as a function of dimension Y for dimension X=25 μm, and a plot 1910 of the self-resonant frequency from JJ2 as a function of dimension Y for dimension X=30 μm.

[0088] 20 shows an illustration of an example graph 2000 of a simulation of the self-resonant frequency from the third Josephson junction component 1310 (JJ3) as a function of dimension Y for various sizes of dimension X of the space 1328 of the device, in accordance with various aspects and embodiments of the disclosed subject matter. The example graph 2000 may include a plot 2002 of the self-resonant frequency from JJ3 as a function of dimension Y for dimension X=10 μm, a plot 2004 of the self-resonant frequency from JJ3 as a function of dimension Y for dimension X=15 μm, a plot 2006 of the self-resonant frequency from JJ3 as a function of dimension Y for dimension X=20 μm, a plot 2008 of the self-resonant frequency from JJ3 as a function of dimension Y for dimension X=25 μm, and a plot 2010 of the self-resonant frequency from JJ3 as a function of dimension Y for dimension X=30 μm.

[0089] 21 , which illustrates a diagram of an exemplary, non-limiting device 2100 that can employ a high kinetic inductance wire in conjunction with a Josephson junction to facilitate desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. In some embodiments, the Josephson junction of the first current path (e.g., the first Josephson junction component 102 of device 100) can be replaced with a high kinetic inductance wire formed of a desirable high kinetic inductance material. In some embodiments, device 2100 can be a qubit device (e.g., a qubit device capable of current-biased frequency tuning), such as, for example, a transmon qubit device.

[0090] The device 2100 can include a high kinetic inductance wire 2102 that can be located along a first current path 2104 that can have a first current (I1) (e.g., when current is supplied to the device 2100). The high kinetic inductance wire 2102 can have an inductance (L k ) and an inductance (L k) can be based at least in part on the height of the high kinetic inductance of wire 2102 and the dimensions of high kinetic inductance wire 2102. High kinetic inductance wire 2102 can have a kinetic inductance level that meets (e.g., is sufficiently high, matches, or exceeds) a defined threshold kinetic inductance level, which can indicate whether wire 2102 has a kinetic inductance level that is high enough to be considered a high kinetic inductance wire. In some embodiments, the defined threshold kinetic inductance level can be 1 nH / μm, although it should be understood that in other embodiments, the defined threshold kinetic inductance level can be greater than or less than 1 nH / μm. In some embodiments, the high kinetic inductance wire 2102 can be formed of a desired superconducting material (e.g., niobium nitride, niobium titanium nitride, or other desired superconducting material) that meets a defined threshold kinetic inductance level. The first current path 2104 can also include a first inductive component 2106 that can be associated with the high kinetic inductance wire 2102. The first inductive component 2106 can be or comprise a first wire of a desired conductive material (or can be part of the high kinetic inductance wire 2102), and the first inductive component 2106 can have a first level of inductance (L1). The first level of inductance of the first inductive component 2106 can be relatively small (e.g., very small or negligible) compared to the amount of inductance of the high kinetic inductance wire 2102.

[0091] Device 2100 may also include a first Josephson junction component 2108 (identified in FIG. 21 as JJ2) and a second Josephson junction component 2110 (identified in FIG. 21 as JJ3) that may be coupled in series along a second current path 2112 in parallel with first current path 2104, which may have a second current (I2) (e.g., when current is supplied to device 2100), and as described in further detail herein, first Josephson junction component 2108 and second Josephson junction component 2110 may facilitate controlling the frequency of device 2100. Second current path 2112 may also include a second inductive component 2114 that may be associated with first Josephson junction component 2108 and second Josephson junction component 2110. The second inductive component 2114 can be or comprise a second wire of a desired conductive material, and the second inductive component 2114 can have a second level of inductance (L2). The first level of inductance of the first inductive component 2106 can include, for example, the self-inductance or effective inductance of the first inductive component 2106 (e.g., the self-inductance or effective inductance of the first wire), and the second level of inductance of the second inductive component 2114 can include, for example, the self-inductance or effective inductance of the second inductive component 2114 (e.g., the self-inductance or effective inductance of the second wire).

[0092] Device 2100 may also include a capacitor component 2116 (e.g., a capacitor) that may include a first terminal associated with first Josephson junction component 2108 and second Josephson junction component 2110 (e.g., connected to a second current path 2112 therebetween), and a second terminal associated with (e.g., connected to) ground 2118 of device 2100. In one non-limiting example, capacitor component 2116 may be 65 fF, although capacitors of other desired capacitances greater than or less than 65 fF may be utilized in device 2100 as needed. Device 2100 may further include a current generator component 2120 that may generate a desired current having a desired current level (e.g., a current pulse having a desired pulse shape), which may be supplied or applied to first current path 2104 and second current path 2112.

[0093] The current division ratio (e.g., I2 / I1) between the first current path 2104 and the second current path 2112 can be determined or changed (e.g., increased (or decreased)) based at least in part on the characteristics (e.g., high kinetic inductance) of the high kinetic inductance wire 2102 relative to the area of the first Josephson junction component 2108 and the area of the second Josephson junction component 2110. The frequency of device 2100 can be controlled (e.g., managed, regulated, changed, or adjusted) based at least in part on the amount of current applied to device 2100 by current generator component 2120, the amount of kinetic inductance of high kinetic inductance wire 2102, the size (e.g., area) of first Josephson junction component 2108 and second Josephson junction component 2110, or the arrangement of high kinetic inductance wire 2102 relative to first Josephson junction component 2108 and second Josephson junction component 2110, or a combination thereof.

[0094] An inductance (L k 21, including a high kinetic inductance wire 2102 having a phase difference between the first and second ends of the high kinetic inductance wire 2102, is relatively similar to the analysis of the device 100 of FIG. 1 described herein, except that there may be differences in the analysis that may include, for example, a phase difference between the two ends of the high kinetic inductance wire 2102, and that the kinetic inductance does not have an associated magnetic flux contribution (e.g., similar to the first Josephson junction component 102 of the device 100).

[0095] Due to the condition of single-valuedness of the phase δ as considered in equation (16),

[0096]

number

number

[0097] Using the current relationship for the Josephson junction (assuming the critical current below) and KCL, we can proceed from equation (16) and follow the following equation (17):

[0098]

number

[0099] Referring briefly to FIG. 22 (together with FIG. 21 ), FIG. 22 illustrates a current I in 22 shows an example graph 2200 of the frequency (e.g., qubit frequency) of device 2100 as a function of . In a non-limiting example, the current I associated with the first Josephson junction component 2108 C2 can be 20 nanoamperes (nA), and the current I associated with the second Josephson junction component 2110 C3 The current I associated with the high kinetic inductance wire 2102 can be 20 nA. in-I2 can be 2000 nA. The capacitance of capacitor component 2116 can be 65 fF. The inductance levels of the first level inductance (L1) and the second level inductance (L2) can each be 12 pH. As described herein, when high kinetic inductance wire 2102 having a high kinetic inductance is disposed relative to first Josephson junction component 2108 and second Josephson junction component 2110, high kinetic inductance wire 2102 can facilitate (e.g., enable) a desired increase in the current division ratio (I2 / I1), which can result in a desired current biasing effect for first Josephson junction component 2108 and second Josephson junction component 2110. For example, high kinetic inductance wire 2102 may be desirable to utilize to increase the current division ratio (I2 / I1), such that a majority of the tuning effect (e.g., the effect of current-biased tuning) of device 2100 can be attributed (e.g., can be generated) in part by first Josephson junction component 2108 and second Josephson junction component 2110.

[0100] 22, from a plot 2202 of frequency (GHz) as a function of current (in μA) for device 2100, it can be observed that for a 10% tuning from a desired frequency spot (e.g., a sweet-spot frequency such as about 6.9 GHz at 0.0 μA), device 100 (e.g., a current-biased qubit device) can involve the use of only about 2.3 μA. In contrast, a standard field-based device (e.g., a magnetic field-based Xmon-coupler device) can require significantly more current (e.g., up to 34 μA) to achieve a 10% tuning from a desired frequency spot (e.g., a sweet-spot frequency). As can also be observed, plot 2202 in FIG. 22 for device 2100 including high kinetic inductance wire 2102 in first current path 2104 can be substantially similar to plot 202 in FIG. 2 for device 100 including first Josephson junction component 102 in first current path 104.

[0101] 21, device 2100 may include low-pass filter components (e.g., low-pass filter component 802) and / or current splitter components (e.g., current splitter component 808) the same as or similar to those described with respect to device 800 of FIG. 8 to facilitate reducing undesirable sensitivity of device 2100 to noise (e.g., current noise, magnetic flux noise, or Johnson noise) and / or Purcell loss. In certain embodiments, device 2100 may also have designed or modified (e.g., adjusted) geometry (e.g., dimensions W, X, and / or a combination thereof) the same as or similar to those described with respect to device 1300 of FIG. 13 to facilitate reducing noise sensitivity and / or mutual inductance of device 2100.

[0102] Device 2100 may be particularly desirable, being one capable of current-controlled frequency tuning, and may utilize a high kinetic inductance wire 2102 and two Josephson junctions (e.g., first and second Josephson junction components 2108 and 2110) arranged in the circuitry of device 2100, such that an applied current (e.g., supplied from current generator component 2120) through the Josephson junction can be used to change the inductance of the Josephson junction, or an applied current through the high kinetic inductance wire can be used to change the inductance of the high kinetic inductance wire.

[0103] However, conventional tunable qubit or coupler devices use magnetic fields generated from current lines to tune the qubit frequency. In such conventional tunable qubit or coupler devices, a magnetic field (e.g., a magnetic flux passed through a SQUID loop) can change the phase difference of the Josephson junction and therefore the Josephson junction inductance, thus enabling a change in the qubit frequency. The disclosed subject matter including device 2100 (e.g., a device capable of current-controlled frequency tuning) does not need to use magnetic fields generated from current lines to tune the qubit frequency because the disclosed subject matter (e.g., device 2100) can easily utilize an applied current (e.g., a current supplied from current generator component 2120) through a Josephson junction (e.g., first or second Josephson junction component 2108 or 2110) to change the inductance of the Josephson junction or an applied current through a high-kinetic inductance wire to change the inductance of the high-kinetic inductance wire, as described in further detail herein.

[0104] Devices (e.g., device 100, device 800, device 1300, and device 2100), which can be current-biased frequency-tunable qubit devices as described herein, can be desirable, improved, and reliable frequency-tunable or flux-tunable devices, can include desirably fast tunable gates and tunable qubits to facilitate preventing undesirable frequency collisions and dispersive interactions (e.g., ZZ interactions), and can also mitigate, reduce, or minimize magnetic crosstalk and magnetic flux noise, which can be desirable because magnetic crosstalk and magnetic flux noise can unnecessarily limit the gate fidelity of qubit devices. Devices (e.g., device 100, device 800, device 1300, and device 2100) can also be useful tools in the design of tunable elements in addition to flux-based approaches.

[0105] The devices described herein (e.g., device 100, device 800, device 1300, and device 2100) can be utilized in multiple qubit systems that use tunable elements (e.g., couplers or qubits) controlled by magnetic flux. The devices (e.g., device 100, device 800, device 1300, and device 2100) can also help reduce power dissipation (e.g., heating) in cables or attenuators as the number of qubits in qubit-based systems is expanded. The current-biased schemes (e.g., designs) and techniques of the disclosed subject matter, in which desirably low (e.g., very low) currents are utilized in the devices described herein (e.g., device 100, device 800, device 1300, and device 2100), can also reduce the complexity associated with having to meet or adhere to requirements or constraints (e.g., design constraints) applicable to cryogenic electronics and hardware designed to drive and control flux-tunable qubits, as described herein with respect to such devices. Devices (e.g., device 100, device 800, device 1300, and device 2100) and current-biased schemes (e.g., designs) and techniques described herein may be employed (e.g., may be suitable for or desirable to employ) in the fields of quantum circuits and quantum computing as desirable techniques for achieving frequency tunability of quantum bits.

[0106] Systems and / or devices have been described (or will be described) herein with respect to interactions between multiple components. It should be understood that such systems and components can include those components or subcomponents designated therein, portions of the designated components or subcomponents, or additional components, or combinations thereof. Subcomponents may also be implemented as components communicatively coupled to other components rather than being contained within a parent component. Furthermore, one or more components and / or subcomponents may be combined into a single component that provides a collective functionality. Components may interact with one or more other components not specifically described herein for brevity but known by those skilled in the art.

[0107] 23 illustrates a flow diagram of an exemplary, non-limiting method 2300 for forming a device that can be utilized to provide desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. Method 2300 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to a processor component and memory. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted or may be omitted for the sake of brevity.

[0108] At 2302, a first Josephson junction component may be formed along a first current path of the device. At 2304, a second Josephson junction component and a third Josephson junction component may be formed on the device, which may be coupled in series along a second current path of the device in parallel with the first current path. For example, the system may form the first Josephson junction component along the first current path, and may form the second Josephson junction component and the third Josephson junction component that may be coupled in series along a second current path of the device in parallel with the first current path of the device. The first current path may be associated with a first inductive component having a first inductance, and the second current path may be associated with a second inductive component having a second inductance.

[0109] At 2306, a capacitor component can be formed having a first terminal that can be associated with the second current path and a second terminal that can be associated with a ground of the device. The capacitor component (e.g., a capacitor) can have a desired amount of capacitance as described herein. In some embodiments, the system can form or place the capacitor component on the device, where the first terminal can be connected to the second current path, for example, between the second Josephson junction component and the third Josephson junction component, and the second terminal can be connected to ground.

[0110] At 2308, a current generator component may be formed on the device that can provide desired current to the first and second current pathways of the device. In certain embodiments, the system may form or place (e.g., insert) the current generator component on the device, and the output of the current generator component may be associated with (e.g., directly or indirectly connected to) the first and second current pathways of the device.

[0111] In some embodiments, method 2300 may proceed to reference point A, and method 2400 of FIG. 24 may proceed from reference point A. In particular embodiments, method 2300 may proceed to reference point B, and method 2500 of FIG. 25 may proceed from reference point B.

[0112] FIG. 24 illustrates a flow diagram of an exemplary, non-limiting method 2400 for forming a low-pass filter component and / or a current splitter component on a device that can be utilized to facilitate providing desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning and reducing the device's sensitivity to noise (e.g., magnetic flux noise or other noise, or both) and parcel loss in accordance with various aspects and embodiments of the disclosed subject matter. Method 2300 may be performed, for example, by a system (e.g., a computer system) including or operatively coupled to a processor component and memory. Repeated descriptions of similar elements employed in other embodiments described herein may be omitted or omitted for the sake of brevity. In some embodiments, method 2400 may proceed from reference point A of method 2300 of FIG. 23.

[0113] At 2402, a low-pass filter component may be formed on the device, the low-pass filter component having an input associated with an output of the current generator component of the device and an output associated with a first current path and a second current path of the device. The system may form or place (e.g., insert) the low-pass filter component on the device, the low-pass filter component having an input (e.g., input port) associated with (e.g., connected to) an output of the current generator component of the device, and the low-pass filter component having an output associated with the first current path and the second current path of the device (e.g., a node in a circuit associated with the first current path and the second current path). The low-pass filter component may be structured as described in further detail herein and may include components (e.g., an inductor component and a capacitor component).

[0114] At 2404, a current splitter component can be formed on the device, the current splitter component can be associated with the first current path and the second current path to facilitate splitting the current output from the current generator component. In some embodiments, additionally or alternatively (e.g., in addition to or instead of a low-pass filter component), the system can form or arrange a current splitter component on the device such that the current splitter component can be associated with the first current path and the second current path to facilitate splitting the current output from the current generator component (e.g., diverting a portion of the current to a ground plane of the device). For example, the system can connect a first terminal of the current splitter component to the first current path, the second current path, or the low-pass filter component, or a combination thereof, and connect a second terminal of the current splitter component to a ground (e.g., a ground plane) of the device. The current splitter component can be structured and can include a component (e.g., an inductor component) as described in further detail herein.

[0115] FIG. 25 illustrates a flow diagram of an exemplary, non-limiting method 2500 for modifying or structuring the circuitry of a device that may be utilized to facilitate providing desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning, reducing the device's sensitivity to noise, and having desirably low mutual inductance, in accordance with various aspects and embodiments of the disclosed subject matter. Method 2500 may be performed, for example, by a system (e.g., a computer system) including or operatively coupled to a processor component and memory. Repeated descriptions of similar elements employed in other embodiments described herein may be omitted or omitted for the sake of brevity. In certain embodiments, method 2500 may proceed from reference point B of method 2300 of FIG. 23.

[0116] In 2502, a space may be defined by pads associated with the first current path, the second current path, the first Josephson junction component, the second Josephson junction component, the third Josephson junction component, and the capacitor component, and with respect to such space associated with the circuit loop of the device, a first dimension (e.g., X dimension) and / or a second dimension (e.g., Y dimension) of the space and / or a third dimension (e.g., W dimension) of the width of the first current path may be varied to facilitate reducing the device's sensitivity to noise and having a desirably low mutual inductance in the device. For example, in connection with designing or forming a circuit for a device comprising a first current path, a second current path, a first Josephson junction component, a second Josephson junction component, a third Josephson junction component, a capacitor component, a current generator component, and a ground, with respect to a space associated with the circuit loop of the device, the system may design, determine, alter (e.g., adjust), or select a first dimension (e.g., an X dimension) or a second dimension (e.g., a Y dimension) or both of the space associated with the circuit loop, or a third dimension (e.g., a W dimension) of the width of the first current path, or both, to facilitate reducing the device's sensitivity to noise and ensuring that the device has a desirably low mutual inductance.

[0117] 26 illustrates a flow diagram of an exemplary, non-limiting method 2600 for forming a device that can employ high kinetic inductance wires in conjunction with Josephson junctions to facilitate desirable (e.g., improved, adequate, acceptable, or optimal) current-biased frequency tuning in accordance with various aspects and embodiments of the disclosed subject matter. Method 2600 can be performed, for example, by a system (e.g., a computer system) that includes or is operatively coupled to a processor component and memory. Repeated descriptions of similar elements employed in other embodiments described herein have been omitted or may be omitted for the sake of brevity.

[0118] At 2602, a high kinetic inductance wire can be formed along a first current path of the device, the high kinetic inductance wire can have a kinetic inductance level that can meet a defined threshold kinetic inductance level. At 2604, a first Josephson junction component and a second Josephson junction component can be formed on the device, the first Josephson junction component and the second Josephson junction component can be coupled in series along a second current path of the device in parallel with the first current path. For example, the system can form a high kinetic inductance wire along the first current path, the high kinetic inductance wire can have a kinetic inductance level that can meet the defined threshold kinetic inductance level (e.g., the kinetic inductance level can be high enough to match or exceed a defined threshold high kinetic inductance level, which can indicate that the kinetic inductance level has a sufficiently high value). The system can also form a first Josephson junction component and a second Josephson junction component, which can be coupled in series along a second current path of the device in parallel with the first current path of the device. The first current path can also be associated with a first inductive component having a first inductance, and the second current path can be associated with a second inductive component having a second inductance.

[0119] At 2606, a capacitor component can be formed having a first terminal that can be associated with the second current path and a second terminal that can be associated with a ground of the device. The capacitor component can have a desired amount of capacitance as described herein. In some embodiments, the system can form or place (e.g., insert) the capacitor component on the device, and the first terminal can be connected to the second current path, for example, between the first Josephson junction component and the second Josephson junction component, and the second terminal of the capacitor component can be connected to ground.

[0120] At 2608, a current generator component may be formed on the device that can provide the desired current to the first and second current pathways of the device. In certain embodiments, the system may form or place (e.g., insert) the current generator component on the device, and the output of the current generator component may be associated with (e.g., directly or indirectly connected to) the first and second current pathways of the device.

[0121] In some embodiments, the method 2600 may proceed to reference point A, and the method 2400 of FIG.

[0122] For ease of explanation, methods and / or computer-implemented methods are depicted and described as a series of acts. It should be understood that the disclosed subject matter is not limited by the depicted acts and / or the order of acts, e.g., acts can occur in various orders, simultaneously, or both, with other acts not presented or described herein. Moreover, not all depicted acts may be required to implement a computer-implemented method in accordance with the disclosed subject matter. In addition, those skilled in the art will appreciate that a computer-implemented method could alternatively be represented as a series of interrelated states or events via a state diagram. Additionally, it should be further understood that the computer-implemented methods disclosed below and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methods to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or computer-readable storage medium.

[0123] To provide background for various aspects of the disclosed subject matter, FIG. 27 and the following discussion are intended to provide a general overview of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 27 illustrates a block diagram of an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein may be omitted or omitted for the sake of brevity. Referring to FIG. 27, a suitable operating environment 2700 for implementing various aspects of the present disclosure may include a computer 2712. The computer 2712 may also include a processing unit 2714, a system memory 2716, and a system bus 2718. The system bus 2718 couples system components, including, but not limited to, the system memory 2716, to the processing unit 2714. The processing unit 2714 may be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures may also be employed as the processing unit 2714.The system bus 2718 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnects (PCI), CardBus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI). The system memory 2716 can also include volatile memory 2720 and nonvolatile memory 2722. A basic input / output system (BIOS), containing the basic routines to transfer information between elements within computer 2712, such as during start-up, is stored in nonvolatile memory 2722. Examples of nonvolatile memory 2722 include, but are not limited to, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) such as ferroelectric RAM (FeRAM).The volatile memory 2720 may also include random access memory (RAM), which acts as external cache memory. For example, RAM is available in many forms, including but not limited to static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM).

[0124] The computer 2712 may also include removable / non-removable, volatile / non-volatile computer storage media. For example, FIG. 27 shows disk storage 2724. Disk storage 2724 may include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. Disk storage 2724 may also include, separately or in combination with other storage media, storage media including, but not limited to, an optical disk drive such as a compact disk ROM (CD-ROM), a recordable CD drive (CD-R drive), a rewritable CD drive (CD-RW drive), or a digital versatile disk ROM (DVD-ROM) drive. A removable or non-removable interface, such as interface 2726, is typically used to facilitate connection of disk storage 2724 to system bus 2718. FIG. 27 also illustrates software that acts as an intermediary between users and the basic computer resources described in suitable operating environment 2700. Such software may include, for example, an operating system 2728. The operating system 2728, which may be stored on disk storage 2724, acts to control and allocate resources of the computer 2712. System applications 2730 take advantage of the management of resources by the operating system 2728, for example, through program modules 2732 and program data 2734 stored either in system memory 2716 or on disk storage 2724. It should be understood that the present disclosure may be implemented using various operating systems or combinations of operating systems.A user enters commands or information into computer 2712 through input devices 2736. Input devices 2736 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, and webcam. These and other input devices connect to processing unit 2714 through system bus 2718 via interface ports 2738. Interface ports 2738 include, for example, serial ports, parallel ports, game ports, and universal serial bus (USB). Output devices 2740 use some of the same types of ports as input devices 2736. In this manner, for example, a USB port can be used to provide input to computer 2712 and to output information from computer 2712 to output device 2740. Output adapter 2742 is provided to indicate the presence of any output device(s) 2740 such as monitors, speakers, and printers, among other output devices 2740 that require special adapters. Examples of output adapters 2742 include, but are not limited to, video cards and sound cards, which provide a method of connection between the output device(s) 2740 and the system bus 2718. It should be noted that other devices and / or systems of devices, such as remote computer(s) 2744, provide both input and output capabilities.

[0125] The computer 2712 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 2744. The remote computer 2744 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device, or other common network node, and can typically include many or all of the elements described relative to the computer 2712. For simplicity, only a memory storage device 2746 is shown with the remote computer 2744. The remote computer 2744 is logically connected to the computer 2712 through a network interface 2748 and then physically connected via a communication connection 2750. The network interface 2748 encompasses wired and / or wireless communication networks such as local-area networks (LANs), wide-area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereof, packet-switched networks, and Digital Subscriber Lines (DSL). Communications connection(s) 2750 refers to the hardware / software employed connecting network interface 2748 to system bus 2718. Communications connection(s) 2750 are shown within computer 2712 for clarity of illustration, but may also be external to computer 2712.The hardware / software for connecting to the network interface 2748 may include, by way of example only, internal and external technologies such as modems, including regular telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0126] One or more embodiments may be a system, method, apparatus, or computer program product at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium containing computer-readable program instructions for causing a processor to execute aspects of one or more embodiments. The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction-execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may include portable computer diskettes, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), SRAM, portable CD-ROMs, digital versatile disks (DVDs), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, and any suitable combinations thereof. As used herein, computer-readable storage media should not itself be construed as being ephemeral signals such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted over wires.

[0127] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). This network may comprise copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device. The computer-readable program instructions for carrying out the operations of the disclosed subject matter can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk®, C++, and procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions can execute entirely on a user's computer, partially on a user's computer as a stand-alone software package, partially on a user's computer and on a remote computer, or entirely on a remote computer or a server.In the latter scenario, the remote computer can be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be to an external computer (e.g., over the Internet using an Internet service provider). In some embodiments, to perform aspects of the disclosed subject matter, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0128] Aspects of the disclosed subject matter are described herein with reference to flowchart diagrams and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart diagrams and / or block diagrams, and combinations of blocks included in the flowchart diagrams and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions, executed by a processor of the computer or other programmable data processing device, produce a method that performs the functions / operations specified in the blocks of the flowchart and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium and can direct a computer, programmable data processing device, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions that implement aspects of the functions / operations specified in the blocks of the flowchart and / or block diagrams. The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to generate a computer-implemented process that causes a series of operable operations to be performed on the computer, other programmable apparatus, or other device, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in the flowchart and / or block diagram blocks.

[0129] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the disclosed subject matter. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur in an order different from that shown in the figures. For example, two blocks shown in succession may be executed substantially concurrently or in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks included in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified function or operation or executes a combination of special-purpose hardware and computer instructions.

[0130] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one or more computers, or both, those skilled in the art will recognize that the present disclosure can also be implemented in combination with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the computer-implemented methods disclosed herein can be practiced using other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, computers, handheld computing devices (e.g., PDAs, phones), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure can be practiced on standalone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0131] As used in this application, terms such as “component,” “system,” “platform,” and “interface” can refer to and / or include computer-related or operable machine-related entities that include one or more particular functions. The entities disclosed herein can be hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of example, both an application running on a server and the server can be a component. One or more components can reside within a process and / or a thread of execution, and a component can be localized on one computer or distributed between two or more computers. In another example, each component can execute from various computer-readable media having various data structures stored thereon. Components can communicate via local and / or remote processes, such as according to signals containing one or more data packets (e.g., data from one component communicating with another component in a local or distributed system, or communicating with other systems via signals over a network such as the Internet, or both). As another example, a component can be a device having a specific function provided by mechanical parts operated by electrical or electronic circuits, operated by a software or firmware application executed by a processor. In such cases, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application.As yet another example, a component can be a device that provides a particular function through electronic components that do not include mechanical parts, and those electronic components can include a processor or other means for executing software or firmware that provides at least some of the functionality of the electronic component. In one aspect, a component can emulate an electronic component through a virtual machine, for example, within a cloud computing system.

[0132] Additionally, the term "or" is intended to mean an inclusive or, rather than an exclusive or. That is, unless otherwise specified or clear from the context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, or X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an," as used in this specification and the accompanying drawings, should generally be construed to mean "one or more" unless otherwise specified or clear from the context to refer to the singular form. As used herein, the words "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0133] As used herein, the term "processor" may refer to virtually any computing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreading, a multi-core processor, a multi-core processor with software multithreading, a multi-core processor with hardware multithreading, a parallel platform, and a parallel platform with distributed shared memory. Furthermore, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization and improve performance of user equipment. A processor may be implemented as a combination of computing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component, relating to the operation and functionality of a component, are used to refer to a "memory component," an entity embodied in a "memory," or a component comprising a memory.It should be understood that the memory and / or memory components described herein can be either volatile or nonvolatile, or can include both volatile and nonvolatile memory. Examples of nonvolatile memory include, but are not limited to, ROM, PROM, EPROM, EEPROM, flash memory, or nonvolatile RAM (e.g., FeRAM). Volatile memory can include RAM, which can act as external cache memory, for example. RAM is available in many forms, including, but not limited to, SRAM, DRAM, SDRAM, DDR SDRAM, ESDRAM, SLDRAM, DRRAM, DRDRAM, and RDRAM. Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to include memory, including, but not limited to, these and any other suitable types of memory.

[0134] The foregoing includes merely exemplary systems and computer-implemented methods. Of course, it is not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing this disclosure, but those skilled in the art will recognize that many other combinations and permutations of the present disclosure are possible. Furthermore, to the extent terms such as "including," "having," and "possessing" are used in the detailed description, claims, appendices, and drawings, these terms are intended to be inclusive in the same manner as the term "comprising" is interpreted when used as a transitional term in a claim. The descriptions of various embodiments are presented for illustrative purposes but are not intended to be exhaustive and are not limited to the disclosed embodiments. Many modifications and variations that do not depart from the scope and spirit of the described embodiments will be apparent to those skilled in the art. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements of the embodiments beyond those found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device, a first Josephson junction located along a first current path of the device; a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path; a current generator component for generating a current; a capacitor having a first terminal and a second terminal; Equipped with the first terminal is associated with the second Josephson junction and the third Josephson junction, and the second terminal is associated with a ground of the device.

2. The device of claim 1 , wherein the device is a qubit device.

3. 3. The device of claim 1, wherein the device is a transmon qubit device.

4. A device as described in any one of claims 1 to 3, wherein the current generator component changes the phase difference between each Josephson junction to control the frequency of the device.

5. A device as described in claim 4, wherein the frequency of the device is controlled by changing the phase difference between each Josephson junction based on the amount of current applied to the device by the current generator component and the size of the second Josephson junction and the third Josephson junction relative to the first Josephson junction.

6. 6. The device of claim 1, wherein an area of the first Josephson junction is larger compared to areas of the second Josephson junction and the third Josephson junction, and a current division ratio between the first current path and the second current path is increased based on the area of the first Josephson junction being larger than areas of the second Josephson junction and the third Josephson junction.

7. a first inductive component located along the first current path; The device of claim 1 , further comprising a second inductive component located along the second current path.

8. A low pass filter component that applies a low pass filter to the current, wherein at least a portion of the filtered current output from the low pass filter component is supplied to the first current path and the second current path, and the low pass filter is associated with a defined threshold frequency that indicates a cutoff frequency of the low pass filter; 8. The device of claim 1, further comprising: a current splitter component that diverts another portion of the output filtered current to a ground of the device.

9. forming a first Josephson junction along a first current path of the device; forming a second Josephson junction and a third Josephson junction coupled in series along a second current path of the device in parallel with the first current path; forming a current generator component that generates a current; forming a capacitor having a first terminal and a second terminal; Including, the first terminal is associated with the second current path and the second terminal is associated with a ground of the device; method.

10. 10. The method of claim 9, wherein the device is a qubit device.

11. 11. The method of claim 10, wherein the qubit device is a transmon qubit device.

12. A method as described in any of claims 9 to 11, further comprising adjusting the frequency of the device by changing the phase difference between each Josephson junction based on the level of current applied to the device by the current generator component and the sizes of the second Josephson junction and the third Josephson junction relative to the first Josephson junction.

13. 13. The method of claim 9, wherein a current division ratio between the first current path and the second current path is increased based on the fact that an area of the first Josephson junction is larger than an area of each of the second Josephson junction and the third Josephson junction, and the area of the first Josephson junction is larger than an area of the second Josephson junction and the third Josephson junction.

14. 14. The method of claim 9, wherein the first current path is associated with a first wire having a first inductance level and the second current path is associated with a second wire having a second inductance level.

15. 1. A qubit device, comprising: a high kinetic inductance wire located along a first current path of the device, the high kinetic inductance wire having a kinetic inductance level that meets a defined threshold kinetic inductance level; a first Josephson junction and a second Josephson junction coupled in series along a second current path of the device in parallel with the first current path; a current generator component for generating a current; a capacitor having a first terminal and a second terminal; Equipped with a qubit device, wherein the first terminal is associated with the second current path and the second terminal is associated with a ground of the qubit device;

16. 16. The qubit device of claim 15, wherein the qubit device is a transmon qubit device.

17. A quantum bit device as described in claim 15 or 16, wherein the phase difference between each Josephson junction is changed based on the amount of current applied to the quantum bit device by the current generator component and the size of the first Josephson junction and the second Josephson junction relative to the high kinetic inductance wire, thereby adjusting the frequency of the quantum bit device.

18. 18. The qubit device of claim 15, wherein a current division ratio between the first current path and the second current path is based on a relationship between the high kinetic inductance wire, the first Josephson junction, and the second Josephson junction.

19. a first inductive component located along the first current path; and a second inductive component located along the second current path.

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