gaming machines

Abstract

To provide a game machine capable of more efficiently processing some errors by using an area (second storage area) different from a used area (first storage area).SOLUTION: A game machine includes a first storage area provided so as to be within a predetermined upper limit capacity and a second storage area different from the first storage area, and stores an in-area program for executing in-area processing in the first storage area and an out-of-area program for executing out-of-area processing in the second storage area, respectively. In the game machine, among multiple types of errors, a first type error is determined in the in-area processing and a second type error is determined in the out-of-area processing, respectively. Error commands are transmitted in the in-area processing for the first type error and in the out-of-area processing for the second type error, respectively. After the in-area processing is shifted to the out-of-area processing, the error commands for the multiple types of second type errors can be transmitted, until the out-of-area processing is returned to the in-area processing.SELECTED DRAWING: Figure 20

Description

[Technical Field]

[0001] The present invention relates to gaming machines such as pachinko machines, arrange ball machines, and slot machines. [Background technology]

[0002] In gaming machines such as pachinko machines, the so-called gaming machine regulations prescribe standards for storage means such as ROM mounted on the main board, and in addition to the overall storage capacity, for example, restrictions are placed on the storage capacity of the usage area (first storage area) for ROM, which consists of a control area and a data area, and all information other than that necessary to prevent unauthorized modification or other changes is to be processed within that usage area. Ru( For example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2019-092882 Summary of the Invention [Problem to be solved by the invention]

[0004] Book The invention is More appropriate processing using storage means with limited storage capacity The object of the present invention is to provide a gaming machine that can perform the above. [Means for solving the problem]

[0005] The present invention relates to a gaming machine having an in-area program stored in a first storage area and an out-of-area program stored in a second storage area different from the first storage area, wherein the gaming machine is capable of executing one of a plurality of processes including a backup restoration process and a RAM clear process when powered on, and based on a determination process by the out-of-area program, stores a predetermined RAM area. No. 1 Predetermined determination information can be set, No. 1When the predetermined determination information is set, a specific notification is made by the control of the predetermined control means. No. 1 command of The sending can be performed by the out-of-domain program; second predetermined judgment information can be set in a predetermined RAM area based on a judgment process by the program in the area, and when the second predetermined judgment information is set, transmission of a second command different from the first command can be executed by the program in the area; If the backup recovery process is performed when the power is turned on, No. 1 The specific notification is continued by not clearing the predetermined determination information, while when the RAM clear process is performed when the power is turned on, No. 1 The specific notification is not executed by clearing predetermined determination information, and the specific notification is not executed by clearing predetermined determination information. No. 1 When the predetermined determination information is set, the program in the area is configured to be able to execute a game stop process. 。 [Effects of the Invention]

[0006] According to the present invention, More appropriate processing using storage means with limited storage capacity It is possible to do this. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an overall front view of a pachinko machine according to an embodiment of the present invention; [Figure 2] FIG. [Figure 3] FIG. 2 is a front view of the game board of the pachinko machine. [Figure 4] FIG. 2 is a front view of the game information display means of the pachinko machine. [Figure 5] FIG. [Figure 6] FIG. 2 is a block diagram of the control system of the pachinko machine. [Figure 7] FIG. 10 is a diagram showing the connection relationship between the LED common port and LED data port of the pachinko machine and the game information display means and performance information display means (setting display means, performance display means). [Figure 8] 10 is an explanatory diagram of a memory area in the main control board of the pachinko machine. FIG. [Figure 9]FIG. 2 is a diagram showing the flow (first half) of the power-on process of the pachinko machine. [Figure 10] FIG. 10 is a diagram showing the flow (middle stage) of the power-on process of the pachinko machine. [Figure 11] FIG. 10 is a diagram showing the flow (second half) of the power-on process of the pachinko machine. [Figure 12] FIG. 10 is a diagram showing the flow of the first power supply abnormality check process of the pachinko machine. [Figure 13] 10 is a diagram showing a source program corresponding to a part of the power-on process of the pachinko machine, and the processing order for each processing mode. FIG. [Figure 14] FIG. 2 is an explanatory diagram of input port 1 of the pachinko machine. [Figure 15] This figure shows the correspondence between the input information of the setting change operation means, door and game information clearing means of the pachinko machine and the value of the W register, as well as the correspondence between these and the transition branch destinations. [Figure 16] FIG. 2 is a diagram showing a flow of setting processing of the pachinko machine. [Figure 17] This figure shows the command sending address table when changing the settings of the pachinko machine, the command sending address table when clearing RAM, the RAM clear command creation table, the spec command creation table, and the command creation table while waiting for customers. [Figure 18] FIG. 10 is a diagram showing the flow of the transmission command table selection process of the pachinko machine. [Figure 19] FIG. 2 is a diagram showing the flow of the command data creation process of the pachinko machine. [Figure 20] 10 is an explanatory diagram of in-area error information and out-of-area error information of the same pachinko machine. [Figure 21] FIG. 10 is a diagram showing the flow of the command transmission process when the pachinko machine is restored to backup mode. [Figure 22] FIG. 10 is a diagram showing the flow of the second command data creation process of the pachinko machine. [Figure 23]This figure shows the command sending address table when the pachinko machine is restored to backup, the power outage recovery display command creation table, the first special hold number designation command creation table, and the second special hold number designation command creation table. [Figure 24] FIG. 10 is a diagram showing the flow of the out-of-area error information clearing process of the pachinko machine. [Figure 25] FIG. 2 is a diagram showing the flow of the initial setting process of the pachinko machine. [Figure 26] FIG. 10 is a diagram showing the flow of processing outside the area within the main loop of the pachinko machine. [Figure 27] FIG. 10 is a diagram showing the flow of timer interrupt processing of the pachinko machine. [Figure 28] FIG. 10 is a diagram showing the flow of the second power supply abnormality check process of the pachinko machine. [Figure 29] FIG. 10 is a diagram showing the flow of the in-area error determination process of the pachinko machine. [Figure 30] FIG. 10 is a diagram showing the flow of the in-area random number circuit processing of the pachinko machine. [Figure 31] FIG. 10 is a diagram showing the flow of processing prize balls within the area of ​​the pachinko machine. [Figure 32] FIG. 10 is a diagram showing the flow of LED management processing of the pachinko machine. [Figure 33] 10 is an explanatory diagram of an LED common output selection table and an LED data output information table of the pachinko machine. FIG. [Figure 34] A diagram showing the flow of processing outside the timer interrupt area of ​​the same pachinko machine. [Figure 35] FIG. 10 is a diagram showing the flow of the out-of-area timer subtraction process of the pachinko machine. [Figure 36] FIG. 10 is a diagram showing the flow of the out-of-area error determination process of the pachinko machine. [Figure 37] FIG. 2 is a diagram showing a flow of monitoring processing of the pachinko machine. [Figure 38] FIG. 10 is a diagram showing the flow of the performance display monitor display update process (first half) of the pachinko machine. [Figure 39]FIG. 10 is a diagram showing the flow of the performance display monitor display update process (second half: when the on / off switching counter is an even number) of the same pachinko machine. [Figure 40] FIG. 10 is a diagram showing the flow of the performance display monitor display update process of the same pachinko machine (second half: when the on / off switching counter is an odd number). [Figure 41] 10A and 10B are diagrams showing the display modes of the identification display section and the numerical display section corresponding to the display content pointer and the section pointer of the same pachinko machine. BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Figures 1 to 41 illustrate an embodiment in which the present invention is adopted in a pachinko machine. In Figures 1 and 2, a gaming machine main body 1 includes an outer frame 2 and a front frame 3 arranged in front of the outer frame 2. The front frame 3 is pivotally attached to the outer frame 2 via a first hinge 4 in the up-down direction arranged at one end in the left-right direction, for example, at the left end, so as to be openable, closable, and detachable. The front frame 3 can be locked in a closed state relative to the outer frame 2 by a locking means 5 provided on the opposite side in the left-right direction from the first hinge 4, for example, at the right end.

[0009] The front frame 3 includes a main body frame 6 and a glass door 7 arranged in front of the main body frame 6. The glass door 7 is pivotally attached to the main body frame 6 via a second hinge 8 in the vertical direction arranged at one end in the left-right direction, for example, at the left end, so as to be openable, closable, and detachable, and can be locked in the closed state relative to the main body frame 6 by a locking means 5.

[0010] As shown in Figure 2, the outer frame 2 is formed into a rectangular shape by a pair of vertical frame members 2a, 2b on the left and right and a pair of horizontal frame members 2c, 2d on the top and bottom. A front cover member 9 is attached to the lower front side of the outer frame 2, and a main frame 6 is disposed above the front cover member 9. The main frame 6 is made of synthetic resin and includes, for example, a rectangular frame portion 13 that can abut the front edge of the outer frame 2 above the front cover member 9, a game board mounting portion 14 provided on the upper side of the frame portion 13, and a lower mounting portion 15 provided on the lower side of the frame portion 13, which are integrally formed. A game board 16 is detachably mounted on the game board mounting portion 14, for example, from the front side, and a launching means 17, a lower speaker 18, etc. are disposed on the front side of the lower mounting portion 15.

[0011] The glass door 7 is provided with a door base 22 made of resin and formed in a rectangular shape corresponding to the front side of the main body frame 6. In this door base 22, a window hole 24a of a glass window 24 is formed corresponding to the front side of a playing area 23 formed on the playing board 16, and multiple (four in this case) presentation means such as upper speakers 25 and a blower presentation device 26 are arranged around the window hole 24a, and an upper decorative cover 27 is attached to substantially cover the upper speakers 25 etc. from the front side.

[0012] Also, at the lower front side of the door base 22 are arranged an upper tray 30 that stores game balls paid out from the payout means 28 located at the rear of the main body frame 6 and supplies them to the launching means 17, a lower tray 31 that stores surplus balls when the upper tray 30 is full, a launch handle 32 that is operated to activate the launching means 17, etc., and further, a lower decorative cover 33 is attached that substantially covers the upper tray 30, lower tray 31, etc. from the front. The lower decorative cover 33 is formed in a forward-facing bulge, and on its upper side are provided predetermined operating means such as an effect button 34 that can be pressed by the player and a cross operating means 35.

[0013] A glass unit 36 ​​is removably attached to the rear side of the door base 22 so as to substantially block the window hole 24a from the rear side, and a ball feeding unit 42, a lower tray guide unit 43, etc. are attached to its lower side. The ball feeding unit 42 is for supplying the game balls in the upper tray 30 one by one to the launching means 17, and is arranged corresponding to the front side of the launching means 17. The lower tray guide unit 43 is for guiding surplus balls when the upper tray 30 is full, and foul balls that have been launched by the launching means 17 but have returned without reaching the playing area 23, to the lower tray 31, and is arranged, for example, adjacent to the ball feeding unit 42 on the side of its first and second hinges 4, 8.

[0014] The main body frame 6 is also provided with a door open switch 44 that can detect whether the front frame 3 is open relative to the outer frame 2. The door open switch 44 is configured to be ON when the front frame 3 is open to the front relative to the outer frame 2, and to be OFF when the front frame 3 is closed.

[0015] As shown in Figure 3, the game board 16 has a base plate 45 made of plywood or the like, and a guide rail 46 that guides the game balls launched from the launching means 17 is arranged in a circular shape on the front side of the base plate 45, and in the game area 23 inside the guide rail 46, a central display frame unit 47, a start-up winning unit 48, a normal winning unit 49, etc., as well as a number of game nails (not shown), are arranged, and a game information display means 50 is arranged on the outside lower part of the game area 23.

[0016] As shown in Figure 4, the game information display means 50 has four LED groups consisting of eight LEDs 60, and a total of 32 LEDs 60 are assigned in predetermined numbers to a normal pattern display means 51, a normal reserved number display means 52, a first special pattern display means 53, a second special pattern display means 54, a first special reserved number display means 55, a second special reserved number display means 56, a fluctuation reduction notification means 57, a right hit notification means 58 and a round number notification means 59. That is, the eight LEDs 60 belonging to the first and second LED groups 50a and 50b constitute the first and second special pattern display means 53 and 54, respectively, the eight LEDs 60 belonging to the third LED group 50c are divided into pairs each constituting a first special reserve number display means 55, a second special reserve number display means 56, a normal reserve number display means 52, and a fluctuation reduction notification means 57, and of the eight LEDs 60 belonging to the fourth LED group 50d, two constitute a normal pattern display means 51, the other two constitute a right-hit notification means 58, and the remaining four constitute a round number notification means 59.

[0017] On the plurality of unit components 47 to 49 of the game board 16, there are provided a normal symbol start means 61, a first special symbol start means 62, a second special symbol start means 63, a big prize means 64, a plurality of normal prize means 65, etc. Also, on the rear side of the base plate 45, there are arranged a liquid crystal display means (image display means) 66, as well as a movable performance means 67 having a movable body 67a that can move in front of the liquid crystal display means 66.

[0018] The central display frame unit 47 constitutes a display frame for the liquid crystal display means 66 and is detachably attached from the front side to a mounting hole (not shown) formed in the base plate 45 that penetrates the front and rear directions. As shown in Fig. 3, the central display frame unit 47 includes a front mounting plate 71 that is disposed outside the mounting hole along the front surface of the base plate 45 and through which game balls can pass; a decorative frame 72 that is disposed in a generally gate-like shape in a front view extending from both the left and right sides of the liquid crystal display means 66 to the upper side and that protrudes forward from the inner periphery of the front mounting plate 71; and a stage 73 that is disposed between the left and right lower ends of the decorative frame 72. Game balls that are launched by the launching means 17 and enter the upper side of the game area 23 are sorted left and right at the top of the decorative frame 72 and flow down either a left flow path 74a on the left side of the central display frame unit 47 or a right flow path 74b on the right side.

[0019] A warp inlet 75 through which game balls can flow is provided on at least one side of the left downflow path 74a side or the right downflow path 74b side, for example, on the left downflow path 74a side, of the central display frame unit 47. A game ball that flows into the warp inlet 75 while flowing down the left downflow path 74a rolls freely in the left-right direction on the stage 73, and then falls forward from either a central drop section 76 provided corresponding to the left-right center of the game area 23 or from another section.

[0020] The start winning unit 48 is disposed below the central display frame unit 47, and is detachably attached to the base plate 45 from the front side. The normal winning unit 49 is disposed below the central display frame unit 47 on the left side of the start winning unit 48, and is detachably attached to the base plate 45 from the front side.

[0021] The normal symbol starting means 61 is for starting the variable display of normal symbols by the normal symbol display means 51, and is composed of a passage gate or the like through which gaming balls can pass, and is equipped with passage detection means (not shown) that detects the passage of gaming balls. This normal symbol starting means 61 is provided on the front side of the front mounting plate 71 on the right part of the central display frame unit 47, and gaming balls flowing down the right flow-down path 74b can pass through it.

[0022] The normal pattern display means 51 is for displaying the normal pattern in a variable manner, and is composed of two LEDs 60 in the game information display means 50 as shown in Fig. 4. When the normal pattern start means 61 detects a gaming ball, the two LEDs 60 constituting the normal pattern emit light in a normal variable light-emitting pattern, and then if the win determination random number value contained in the normal random number information acquired when the normal pattern start means 61 detects the gaming ball matches a predetermined win determination value, the fluctuation stops in a win state, and otherwise in a loss state. The two LEDs 60 constituting the normal pattern can display one or more win states and one or more loss states by combining their light-emitting states (for example, on / off).

[0023] Furthermore, when the normal symbol starting means 61 detects a gaming ball during a normal reservation period, which includes the normal symbol display means 51's symbol variation and the normal profit state, the normal random number information acquired thereby is reserved and stored up to a predetermined upper limit of reserved numbers, for example, up to four, and each time the normal reservation period ends, one is consumed at a time, causing the normal symbol to vary. The number of stored normal random number information (normal reservation number) is notified to the player by the normal reservation number display means 52, etc. As shown in Figure 4, the normal reservation number display means 52 is composed of two LEDs 60 in the game information display means 50, and five types of normal reservation numbers (0 to 4) can be displayed by combining the light-emitting modes (for example, on / blinking / off) of the two LEDs 60.

[0024] The first special symbol starting means 62 is used to start the symbol variation by the first special symbol display means 53. It is configured as a non-opening / closing winning means without an opening / closing means, and is equipped with a game ball detection means (not shown) for detecting a winning game ball. This first special symbol starting means 62 is provided in the starting winning unit 48 and is arranged with an upward opening below the central drop section 76 of the stage 73, corresponding to the central drop section 76. Because there is a winning route from the warp entrance 75 on the left flow path 74a through the stage 73, a game ball flowing down the left flow path 74a has a higher probability of winning than a game ball flowing down the right flow path 74b. When a game ball wins the first special symbol starting means 62, a predetermined number of game balls are paid out as prize balls per winning.

[0025] The second special pattern starting means 63 is used to start the pattern change by the second special pattern display means 54, and is composed of an opening and closing type winning means that can be changed between an open state in which the game ball can win a prize and a closed state in which it is not possible to win a prize (or it is more difficult to win a prize than in the open state) by operating the opening and closing section 78, and is equipped with a game ball detection means (not shown) that detects a winning game ball, and when the stopped pattern after the change of the normal pattern display means 51 becomes a winning pattern and a normal profit state occurs, the opening and closing section 78 changes from a closed state to an open state for a predetermined time.

[0026] This second special symbol starting means 63 is disposed on the front mounting plate 71 at the right part of the central display frame unit 47 and downstream of the normal symbol starting means 61, and gaming balls flowing down the right flow path 74b can win. When a gaming ball wins in this second special symbol starting means 63, a predetermined number of gaming balls are paid out as prize balls per win.

[0027] 4, the first special symbol display means 53 is composed of eight LEDs 60 in the game information display means 50, and on the condition that the first special symbol start means 62 detects a gaming ball, the eight LEDs 60 constituting the first special symbol emit light in a special variation light-emitting pattern, and then if the jackpot determination random number value included in the first special random number information acquired when the first special symbol start means 62 detects a gaming ball matches a predetermined jackpot determination value, the variation stops in a first jackpot mode, and otherwise in a first loss mode. If the stopped pattern after the variation of the first special symbol display means 53 becomes the first jackpot mode, a first special advantage state occurs.

[0028] 4, the second special symbol display means 54 is composed of eight LEDs 60 in the game information display means 50, and on the condition that the second special symbol start means 63 detects a gaming ball, the eight LEDs 60 constituting the second special symbol emit light in a special variation light-emitting pattern, and then if the jackpot determination random number value included in the second special random number information acquired when the second special symbol start means 63 detects a gaming ball matches a predetermined jackpot determination value, the variation stops in a second jackpot mode, and otherwise in a second loss mode. If the stopped pattern after the variation of the second special symbol display means 54 becomes the second jackpot mode, a second special advantage state occurs.

[0029] In addition, the first and second special pattern display means 53, 54 can display one or more first and second jackpot patterns and one or more first and second loss patterns by combining the light emission patterns (e.g., on / off) of each of the eight LEDs 60.

[0030] Furthermore, when the first and second special symbol start means 62, 63 detect a gaming ball during a special reservation period, including during the symbol change of the first special symbol display means 53, the symbol change of the second special symbol display means 54, and the first and second special advantage states, the first and second special random number information acquired thereby is reserved and stored up to a predetermined upper limit of the number of reserved pieces, for example, four pieces each. If the reserved memory on the second special symbol side is one or more at the end of the special reservation period, one reserved memory of the second special symbol is consumed to change the second special symbol. If only the reserved memory on the first special symbol side is one or more, one reserved memory of the first special symbol is consumed to change the first special symbol. Thus, in this embodiment, both the first and second special symbols are never changing, and when there are reserved memories on both the first and second special symbol sides, the second special symbol is prioritized.

[0031] The number of stored first and second special random number information (first and second special reserve numbers) is notified to the player by the first and second special reserve number display means 55, 56, the liquid crystal display means 66, etc. The first and second special reserve number display means 55, 56 are each composed of two LEDs 60 in the game information display means 50 as shown in Fig. 4, and five types of first and second special reserve numbers (0 to 4) can be displayed by combining their light emission modes (for example, on / blinking / off).

[0032] The special winning means 64 is an open / close type winning means equipped with an opening / closing plate 79 that can be switched between an open state allowing a game ball to win and a closed state preventing a game ball from winning. The opening / closing plate 79 is provided in the central display frame unit 47 and is located downstream of the second special symbol starting means 63 and upstream of the first special symbol starting means 62. A game ball flowing down the right flow path 74b has a higher probability of winning than a game ball flowing down the left flow path 74a. In the special winning means 64, when the first and second special symbols of the first and second special symbol display means 53 and 54 fluctuate and then stop in the first and second jackpot modes, the opening / closing plate 79 opens forward according to a predetermined opening pattern, allowing a game ball that falls onto the opening / closing plate 79 to win inside. When a game ball wins the special winning means 64, a predetermined number of game balls are paid out as prize balls for each win. In the following description, the first special advantage state and the second special advantage state will be collectively referred to as a "jackpot game (special game)."

[0033] In addition, the liquid crystal display means 66 is capable of displaying a changing performance pattern 80 in parallel with the changing display of the first and second special patterns by the first and second special pattern display means 53, 54, and is also capable of displaying various images such as first and second reserve images X1 to X4, Y1 to Y4 indicating the number of first and second special reserves, and a changing reserve image Z.

[0034] 3, the effect symbol 80 is composed of a symbol body 80a consisting of numbers such as 1 to 8 and the like, and a combination of characters and other decorative parts 80b associated with this symbol body 80a, and can be changed in multiple rows in a predetermined direction (here, three rows in the left-right direction), and starts to change by vertical scrolling or the like according to a predetermined change pattern at approximately the same time as the first and second special symbols start to change, and is made to finally stop at approximately the same time as the first and second special symbols stop changing. Note that in the effect symbol 80, when all the same symbols are lined up, it is a jackpot effect, and otherwise it is a miss effect, and when the first and second special symbols are in the first and second jackpot effect, the effect symbol 80 is in the jackpot effect, and when the first and second special symbols are in the first and second miss effect, the effect symbol 80 is in the miss effect.

[0035] Furthermore, with regard to the first and second reserved images X1-X4, Y1-Y4 and the changing reserved image Z, when the number of first and second special reserved items increases based on the first and second special pattern starting means 62, 63 detecting a game ball, one additional first and second reserved image X1-, Y1- is displayed on the liquid crystal display means 66, and when the number of first and second special reserved items decreases based on the start of a new change of the first and second special patterns by the first and second special pattern display means 53, 54, the changing reserved image Z is erased, the first and second reserved images X1-, Y1- are shifted by one toward the front of the queue (for example, to the right side of the screen), and the pushed-out first first and second reserved images X1, Y1 are moved to a predetermined position and changed into a new changing reserved image Z.

[0036] In addition, a rear cover 81 is attached to the back of the game board 16, as shown in Figure 5, which covers the central display frame unit 47 and the like from the rear side, and on the back side of this rear cover 81, a main board case 82 in which a main control board 82a is stored, a performance board case 83 in which a performance control board 83a and a performance interface board 83b are stored, an LCD board case 84 in which an LCD control board 84a is stored, and the like are removably attached.

[0037] In addition, an opening / closing cover 85 that covers the back side of the game board 16 is detachably attached to the back side of the front frame 3, and a game ball tank 86a and a tank rail 86b are attached above it, and a payout means 28 and a payout passage 87 are attached to one of the left and right sides, so that when a game ball enters a winning opening such as the big prize means 64, or when a ball lending command is received from an automatic ball lending machine not shown, the game ball in the game ball tank 86a is paid out by the payout means 28 via the tank rail 86b, and the game ball is guided to the upper tray 30 via the payout passage 87. The opening / closing cover 85 is arranged to cover the upper side of the main board case 82 from the rear.

[0038] In addition, a board mounting stand 88 is removably attached to the lower back side of the front frame 3, and a power supply board case 89 containing a power supply board 89a and a dispensing board case 90 containing a dispensing control board 90a are each removably attached to the back side of this board mounting stand 88.

[0039] Figure 6 is a schematic block diagram of the control system of this pachinko machine. In Figure 6, the main control board 82a controls the game control operation, and is connected via relay boards to the game information display means 50, normal symbol start means 61, first special symbol start means 62, second special symbol start means 63, big prize means 64, normal prize means 65, etc. on the game board 16. Also connected to the lower control boards are a performance control board 83a that controls performance such as sound output, illumination, and movable body drive based on control commands from the main control board 82a, a liquid crystal control board 84a that controls the liquid crystal display means 66 based on control commands from this performance control board 83a, a payout control board 90a that controls the payout means 28 based on control commands from the main control board 82a, and a launch control board 91 that controls the launch means 17 based on launch control signals from this payout control board 90a.

[0040] Also connected to the main control board 82a are operation means such as a RAM clear switch 92 and a setting change operation means 93, and display means such as a performance information display means 97. As shown in Fig. 5, the RAM clear switch 92 and the setting change operation means 93 are both mounted on the main control board 82a in a state where they can be operated from the outside of the main board case 82, and the performance information display means 97 is visible from the outside of the main board case 82.

[0041] The RAM clear switch 92 is operated to clear the RAM when the power is turned on, and can be pressed from the outside of the main board case 82. It is configured to be OFF when not in operation and ON when in operation. The setting change operation means 93 is operated when changing settings, etc., and can be switched ON / OFF by inserting a setting key into the keyhole from the outside of the main board case 82 and rotating it. In this embodiment, by operating the setting change operation means 93, etc., the jackpot probability, i.e., the probability that the first and second special symbols will become jackpots, can be changed in multiple stages (here, six stages from setting 1 to 6).

[0042] The performance information display means 97 constitutes the setting display means 94 and the performance display means 95, and is equipped with 7-segment display units 97a to 97d with multiple digits (here, 4 digits), and is mounted on the main control board 82a so that it is visible through the transparent main board case 82.It functions as the setting display means 94 during a first period, and functions as the performance display means 95 during a second period different from the first period.

[0043] The setting display means 94 displays setting information indicating which of settings 1 to 6 the setting is set to, and can display either "1" to "6" or "1." to "6." corresponding to settings 1 to 6 on at least a part of the performance information display means 97 (here, the 7-segment display unit 97a).During the setting change period, setting information before confirmation can be displayed as "1." to "6." with dots, and during the setting confirmation period, confirmed setting information can be displayed as "1" to "6" without dots.

[0044] The performance display means 95 displays so-called base values ​​on the 7-segment display units 97a to 97d. The base value is an example of information related to game performance, and is calculated by "(number of payouts in a low probability state ÷ number of outs in a low probability state) × 100." The performance display means 95 of this embodiment can switch between and display four types of base values: a real-time base value, a first cumulative base value, a second cumulative base value, and a third cumulative base value. The real-time base value is a real-time base value during a unit measurement period, which is defined as the time until the number of outs reaches a predetermined number (e.g., 60,000). The first to third cumulative base values ​​are cumulative base values ​​for the unit measurement periods one to three times prior, respectively.

[0045] As described above, the RAM clear switch 92, setting change operation means 93, and performance information display means 97 are all located at the rear of the gaming machine main body 1, and in order to access them it is necessary to unlock and open the front frame 3, so no one other than hall personnel can operate the RAM clear switch 92 or setting change operation means 93, nor can they see the display contents of the performance information display means 97.

[0046] In this embodiment, the game information display means 50 and the performance information display means 97 are driven and controlled by a dynamic lighting method. As shown in Fig. 7, a 1-byte scanning signal of dynamic lighting commons C0 to C7 can be output from the LED common port of the main control board 82a, and of these, the lines of dynamic lighting commons C0 to C3 are connected to the LED groups 50a to 50d of the game information display means 50, and the lines of dynamic lighting commons C4 to C7 are connected to the 7-segment display units 97a to 97d of the performance information display means 97, respectively.

[0047] In addition, LED data ports 1 and 2 of the main control board 82a can output one byte of dynamic lighting data D10 to D17 and D20 to D27, respectively, and the lines of the dynamic lighting data D10 to D17 of LED data port 1 are connected to the LED groups 50a to 50d of the game information display means 50, and the lines of the dynamic lighting data D20 to D27 of LED data port 2 are connected to the 7-segment display units 97a to 97d of the performance information display means 97, respectively.

[0048] The performance control board 83a and the LCD control board 84a are connected to a performance interface board 83b which is connected to the main control board 82a as shown in Figure 6, and both control commands from the main control board 82a to the performance control board 83a and control commands from the performance control board 83a to the LCD control board 84a are transmitted via the performance interface board 83b.

[0049] Furthermore, various presentation means to be controlled by the presentation control board 83a, such as speakers 18, 25, illumination means 96, movable presentation means 67, etc., as well as presentation buttons 34 and cross operation means 35 that can be operated by the player, are connected to the presentation control board 83a via a presentation interface board 83b. The illumination means 96 is composed of a number of LEDs (not shown) arranged inside the upper and lower decorative covers 27, 33, on the game board 16, etc.

[0050] Next, we will explain the power-on process (Fig. 9) executed by the main control board 82a when the power is turned on. Before that, we will briefly explain the storage means installed on the main control board 82a with reference to Fig. 8. The storage means installed on the main control board 82a include an internal ROM (first storage area) and internal RAM that are provided so as to be within a predetermined upper limit capacity, and an external ROM (second storage area) and external RAM that are separate from these. The internal ROM and external ROM each consist of a control area where programs are stored and a data area where data is stored.

[0051] An internal program stored in the control area of ​​internal ROM references the data area of ​​the same internal ROM and can reference and update internal RAM, but can only reference external RAM and cannot directly update it. Similarly, an external program stored in the control area of ​​external ROM references the data area of ​​the same external ROM and can reference and update external RAM, but can only reference internal RAM and cannot directly update it. Therefore, for example, if you want to update data in external RAM during internal processing by an internal program, you must call the external program from the internal program and update the data in external RAM through external processing by that external program.

[0052] Next, the power-on process shown in Fig. 9 will be described. This power-on process is an intra-domain process executed by an intra-domain program, and first, interrupts are disabled (S1) so that interrupt processes such as timer interrupts are not executed, a stack pointer is set (S2), and RAM protection and prohibited areas are disabled in preparation for stack use in the first power abnormality check process (S3). Then, in consideration of the possibility that the power may have been turned off / on during the setting change process described below, the security signal output from the external output terminal is turned off, setting display data related to the display of setting information on the setting display means 94 is cleared, and the launch control signal is also turned off to prevent the inadvertent output of a launch control signal (S4).

[0053] Next, a first power supply abnormality check process (S5) is executed. In this first power supply abnormality check process, as shown in Fig. 12, after executing a WDT clear process (S51a), it is determined whether or not the power supply abnormality signal is ON (S51), and if the power supply abnormality signal is ON (S51: Yes), the process proceeds to the beginning of the power-on process (S1 in Fig. 9).

[0054] If the first power supply abnormality check process (S5) determines that the power supply abnormality signal is not ON (S51: No in FIG. 12), the first power supply abnormality check process ends and the process proceeds to the next step S6 (FIG. 9). In S6, various initial settings are made regarding register values ​​within the CPU, as well as settings for the interrupt mode, interrupt priority, internal hardware random number, etc. Then, a sub-board startup wait time is set (S7), and the sub-board startup wait time subtraction process (S8), WDT clear process (S9), and the first power supply abnormality check process similar to S5 (S10, FIG. 12) are repeatedly executed until the sub-board startup wait time reaches 0 (S11).

[0055] When the sub-board startup waiting time reaches 0 (S11: Yes), a standby screen display command (BA01H) is sent to the performance control board 83a (S12). When the performance control board 83a receives the standby screen display command (BA01H), the LCD display means 66 displays "Please Wait" or the like.

[0056] Then, the first power supply abnormality check process (S13, Figure 12) is repeatedly executed until it is determined that the power-on signal of the dispensing control board 90a is ON (S14: Yes), thereby confirming the startup of the dispensing control board 90a.

[0057] Next, the process proceeds to S15 to S24 shown in Fig. 10. The processes of S15 to S24 are performed in one of five processing modes: "setting change" in which a setting change process (S17) and a RAM clear process (S18) are executed, "RAM clear" in which a RAM clear process (S18) is executed without executing the setting change process (S17), "setting check" in which a setting check process (S23) and a backup restore process (S24) are executed, "backup restore" in which a backup restore process (S24) is executed without executing the setting check process (S23), and "RAM abnormality" in which a power re-on wait process (S20) is executed.

[0058] Furthermore, of these five processing modes, the four modes excluding "RAM abnormality" are selected according to the combination of the ON / OFF state of the setting change operation means 93, the open / closed state of the door (front frame 3), and the ON / OFF state of the RAM clear switch 92.

[0059] 15, in this embodiment, when the setting change operation means 93 and the RAM clear switch 92 are both ON, "change setting" is selected as a general rule, and when the setting change operation means 93 is OFF and the RAM clear switch 92 is ON, "clear RAM" is selected, but even when the setting change operation means 93 and the RAM clear switch 92 are both ON, "clear RAM" is selected instead of "change setting" when the door is closed. Similarly, when the setting change operation means 93 is ON and the RAM clear switch 92 is OFF, "check setting" is selected as a general rule, and when the setting change operation means 93 and the RAM clear switch 92 are both OFF, "restore backup" is selected, but even when the setting change operation means 93 is ON and the RAM clear switch 92 is OFF, "restore backup" is selected instead of "check setting" when the door is closed.

[0060] The processing of S15 to S24 will be described in detail below in accordance with the source program shown in Fig. 13, while also referring to the flowchart in Fig. 10. In Fig. 13, the source program of S15 to S24 is written in the order in which it is stored in memory. Also, to the right of the source program, the processing to be executed and the execution order for each of the five processing modes mentioned above, "change settings," "clear RAM," "check settings," "restore from backup," and "RAM abnormality," are indicated by arrows and numbers to the upper right of the arrows.

[0061] In the input port data acquisition process (S15), as shown in Fig. 13, first, data from input port 1 (P_INPT1) is input to the W register (Sa1). In this embodiment, the input signals corresponding to bits 0 to 7 of input port 1 (P_INPT1) are as shown in Fig. 14, with the ON / OFF signal of the setting change operation means 93 being input to bit 0, the ON / OFF signal (door open signal) of the door open switch 44 being input to bit 5, and the ON / OFF signal of the RAM clear switch 92 being input to bit 6. In Sa1, the data from bits 0 to 7 of input port 1 (P_INPT1) are input to bits 0 to 7 of the W register, respectively.

[0062] Next, by calculating the logical product (AND) of the value of the W register and the mask data "01100001B", bits other than the 0th bit corresponding to the ON / OFF signal of the setting change operation means 93, the 5th bit corresponding to the ON / OFF signal (door open signal) of the door open switch 44, and the 6th bit corresponding to the ON / OFF signal of the RAM clear switch 92 are masked, and the W register is updated to the masked data (Sa2).

[0063] As shown in Figure 15, bit 0 of the W register is 1 when the setting change operation means 93 is ON and 0 when it is OFF, bit 5 is 1 when the door (front frame 3) is open and 0 when it is closed, and bit 6 is 1 when the RAM clear switch 92 is ON and 0 when it is OFF. There are eight combinations of values ​​for bits 0, 5, and 6 of the W register, as shown in Figure 15. Below, the combination of values ​​w0, w5, and w6 of bits 0, 5, and 6 of the W register will be expressed as W(w0, w5, w6) as necessary.

[0064] Following the input port data acquisition process (S15), the setting change branch determination process (S16) is executed. This setting change branch determination process (S16) determines whether or not "setting change" should be selected as the processing mode. As shown in FIG. 13, the value of the W register is first compared with "01100001B" to determine the difference (Sb1). The value obtained is 0 when bits 0, 5, and 6 of the W register are all 1 (W(1,1,1)), i.e., when the door (front frame 3) is open and both the setting change operating means 93 and RAM clear switch 92 are ON. If the obtained value (difference) is 0, the zero flag is set to 1. If the value obtained in Sb1 is 0 (zero flag = 1), i.e., W(1,1,1), "setting change" is selected as the processing mode, and the process proceeds to the next setting change process (S17).

[0065] In the setting change process (S17), first, BA5AH (setting change command data) indicating that the setting change period has started is stored in the DE register (Sc1), and the command data is transmitted by the command transmission process (Sc2). When the performance control board 83a receives the setting change command (BA5AH), the liquid crystal display means 66 displays "setting change in progress" or the like.

[0066] Next, a setting process subroutine (M_SETTEI) is executed (Sc3). In this setting process (Sc3), as shown in Fig. 16, first, the backup flag is cleared (S60), and input data creation processing (S61) is executed to acquire input information from the RAM clear switch 92, setting change operation means 93, etc.

[0067] Then, the setting value data is read from the setting value work area in the internal RAM and set in the C register as the setting work value (S62). In this embodiment, any of settings 1 to 6 can be selected, and the setting value work area in the internal RAM stores setting value data of any of 0 to 5 depending on which of settings 1 to 6 is selected. If the setting work value in the C register is not within the range of 0 to 5 (S63: No), 0 is stored in the C register (setting work value) (S64). In other words, if the setting value data is not within the normal range, 0 corresponding to setting 1 is forcibly set in the C register (setting work value). Of course, the value set in the C register (setting work value) may be any value within the normal range (0 to 5).

[0068] In this embodiment, the RAM abnormality determination process (S19), which will be described later, is not executed before the setting change process (S17) (see FIG. 10), so there is a possibility that the value in the setting value work area will not be within the normal range due to a RAM abnormality at the start of the setting change process (S17). In such a case, the setting work value is forcibly set to a normal value (0 in this case) in S64, so that the setting change process can proceed even in the case of a RAM abnormality.

[0069] Next, a first power supply abnormality check process (S65, FIG. 12) is executed, and a security signal is output from the external output terminal (S66). Then, a chattering prevention wait time is set (S67), and a chattering prevention wait time decrement process (S68) is repeatedly executed until the chattering prevention wait time reaches 0 (S69: Yes). In this embodiment, the processes of S65 to S75 are repeated at high speed until the setting change operation means 93 is turned OFF (S76: Yes), and each time a determination is made as to whether a setting change operation has been performed, i.e., whether the RAM clear switch 92 has changed from OFF to ON (S71, described later). However, by providing a chattering prevention wait time in S67 to S69, erroneous detection due to chattering of the RAM clear switch 92 can be prevented.

[0070] When the chattering prevention wait time reaches 0 (S69: Yes), the input data creation process (S70) is executed, and it is determined whether a predetermined setting change operation has been performed (S71). In this embodiment, the RAM clear switch 92 is also used for setting change operations, and in S71, it is determined that a setting change operation has been performed when an ON edge of the RAM clear switch 92 is detected. In this embodiment, the input data creation process for acquiring input information from the RAM clear switch 92 is executed not only in S70 immediately before S71, but also in S61 immediately after the start of the setting process. This is because, even if the setting process (FIG. 16) is started while the RAM clear switch 92 is still pressed and the ON edge of the RAM clear switch 92 suddenly rises, this is detected as null in S61, so that it does not affect the determination in S71.

[0071] Then, if it is determined in S71 that a setting change operation has been performed (S71: Yes), the setting work value is updated (S72 to S74). That is, the setting work value is incremented (S72), and if the incremented setting work value is not within the range of 0 to 5 (S73: No), the setting work value is set to 0 (S74).

[0072] Next, setting display data for specifying the setting information to be displayed on the setting display means 94 is created and output (S75). In S75, the setting display data is created based on the setting work value, so the value (for example, any of 1 to 6) displayed on the setting display means 94 during the setting change period does not indicate the setting information at that time (the value in the setting value work area), but indicates provisional setting information before it is finalized. To make this clear, the setting display means 94 displays "1" to "6" with a "." (dot) added. Of course, it is also possible to make it clear that the setting information is before it is finalized in a way other than adding a "." (dot), such as by flashing "1" to "6."

[0073] The above steps S65 to S75 are repeated until the setting change termination condition is met (S76: Yes), that is, until an OFF edge is detected on the setting change operation means 93. Through the above steps, during the setting change period, the setting work value is cyclically changed within the range of 0 to 5 depending on the number of times the RAM clear switch 92 is pressed.

[0074] If the setting change termination condition is met during the setting change period (S76: Yes), the setting change period ends, and the setting work value of register C is stored in the setting value work area (S77). This confirms the provisional setting work value changed during the setting change period as setting value data. Then, the setting display data is cleared to end the display of setting information by the setting display means 94 (S78), the security signal is turned OFF (S79), a setting change completion command (BA09H) is sent to the performance control board 83a (S80), and the setting process ends. Note that when the performance control board 83a receives the setting change completion command (BA09H), a message such as "The setting has been changed" is displayed on the liquid crystal display means 66.

[0075] Returning to Figure 13, the explanation will continue. When the above setting process (Sc3) is completed, the address (D_MKCADR2A) of the command transmission address table when the setting is changed is set in the HL register (Sc4). Here, the command transmission address table when the setting is changed specifies the command creation table for creating the commands to be sent when the setting is changed, and is composed of the number of loops and the addresses of the command creation tables for that number of loops. In the command transmission address table when the setting is changed shown in Figure 17 (a1), the number of loops is set to 2, and addresses of two types of command creation tables are set: a spec command creation table and a waiting command creation table.

[0076] Then, the process jumps to SYSTEM_550, i.e., Sd2 of the RAM clear process (S18) (Sc5). In this manner, in this embodiment, the RAM clear process (S18) following the setting change process (S17) skips Sd1 and starts from Sd2.

[0077] In Sd2 of the RAM clear process (S18), a transmission command table selection process is executed based on the command transmission address table specified in the HL register. Note that when jumping to Sd2 from the setting change process (S17), the address of the command transmission address table at the time of setting change (FIG. 17(a1)) is set in the HL register.

[0078] In the transmission command table selection process (Sd2), as shown in Fig. 18, for example, the loop number is first obtained from the specified command transmission address table (S81), and the following steps S82 and S83 are repeatedly executed the number of loops (S84). In S82, the address of the command creation table is specified from the specified command transmission address table, and in S83, command data creation process is executed based on the specified command creation table. In the case of the setting change command transmission address table shown in Fig. 17(a1), the addresses of the spec command creation table (Fig. 17(c)) and the waiting command creation table (Fig. 17(d)) ​​are specified sequentially in two loops, and command data creation process is executed for each.

[0079] In the command data creation process (S83), as shown in Fig. 19, for example, command data is created from a specified command creation table (S91), and a command transmission process (S92) is executed to transmit the command data. In the command creation table, as shown in Figs. 17(c) and 17(d), in addition to the command data, an additional value for the command data is set, and in S91, the additional value is added to the command data obtained from the command creation table to generate the command data to be actually transmitted. In the case of the command creation tables shown in Figs. 17(c) and 17(d) specified in the command transmission address table at the time of setting change, the additional values ​​are both set to 0, so F611H (spec command data) and BA04H (waiting for customer command data) are sequentially obtained from each command creation table and transmitted as is.

[0080] Following the above transmission command table selection process (Sd2 in FIG. 13), the next address in the setting value work area is set in the HL register (Sd3), the number of zero-clearing processes (here, 256-3) is set in the B register (Sd4), and the zero-clearing process is called (Sd5). In this embodiment, the range of 0 to 255 bytes in RAM is allocated as an internal work area (internal RAM), and the range of 256 to 511 bytes is allocated as an external work area (external RAM). The beginning of the internal RAM (which stores information about games, etc.) is the setting value work area. A predetermined number of bytes from the end of the internal RAM are used as a stack area; for example, in Sd5, a return address after a subroutine call is temporarily stored. Therefore, steps Sd3 to Sd5 clear 253 bytes of the internal RAM, excluding the setting value work area and the stack area in which the return address after a subroutine call is stored.

[0081] Next, the first address of the initial value setting data table is loaded into the HL register (Sd6), and some data is initialized by calling the data set process (Sd7). After setting the RAM clear flag (W_RCFLG), which indicates whether the RAM clear process has been performed, to 5AH (Sd7a), the program jumps to SYSTEM_1200, i.e., S25 shown in Figure 11 (Sd8).

[0082] In this way, in the RAM clearing process (S18) when power is turned on, of the internal RAM and external RAM, only the internal RAM is initialized, and the external RAM is not initialized. The external RAM is an area that mainly stores information related to the display of the performance display means 95, and stores various information such as count values, counted values, and display values. The internal RAM stores data related to games other than the performance display means 95 stored in the external RAM. In this way, by not initializing the external RAM in the RAM clearing process when power is turned on, it is possible to carry over data such as count values, counted values, and display values ​​related to the performance display means 95 across power outages even when the RAM clearing process is performed.

[0083] In this embodiment, information about errors is also stored separately in the in-area RAM and the out-area RAM depending on the type of error. That is, information about in-area errors (first type errors) that mainly affect the outcome of the game (FIG. 20(a)) is stored in the in-area RAM, and information about other out-area errors (second type errors) (FIG. 20(b)) is stored in the out-area RAM, and processing related to in-area errors (determination, update, command transmission, etc.) is performed by the in-area processing, and processing related to out-area errors is performed by the out-area processing. Therefore, in the RAM clearing processing (S18) by the in-area program, of the various types of error information, the in-area error information shown in FIG. 20(a) is cleared.

[0084] Returning to the setting change branch determination process of S16, if it is determined in S16 that at least one of bits 0, 5, and 6 of the W register is not 1 (≠ W(1,1,1)), that is, if the "setting change" processing mode is not selected, the process jumps to SYSTEM_600 in Fig. 13, that is, the RAM abnormality determination process (S19) (Sb2).

[0085] The RAM abnormality determination process (S19) determines whether or not to select the "RAM abnormality" processing mode. As shown in FIG. 13, first, it determines whether or not there is a RAM abnormality (Se1, Se2). That is, it acquires setting value data from the setting value work area of ​​the internal RAM, compares the setting value data with 6, and determines the difference between them (Se1). In this embodiment, since the setting value work area on RAM should store setting value data between 0 and 5, if the setting is normal, the difference between the setting value data and 6 will be a negative value. Therefore, if the difference is not a negative value (carry flag ≠ 1), it determines that there is a RAM abnormality, and jumps to SYSTEM_700, i.e., the power re-on wait process (S20) (Se2).

[0086] If there is no RAM abnormality, it is determined whether there is a backup abnormality (Se3, Se4). That is, the backup flag is compared with 5AH to find the difference therebetween (Se3). The backup flag is set to 5AH in S160 of the second power supply abnormality check process (FIG. 28) described later. If the difference is not 0 (zero flag ≠ 1), it is determined that there is a backup abnormality, and the process proceeds to the next SYSTEM_700, that is, the power re-on wait process (S20) (Se4).

[0087] In the power re-on wait process (S20), first BA07H (power re-on command data) is stored in the DE register (Sf1), and the command data is sent by the command sending process (Sf2), and the backup flag is cleared (Sf3). When the performance control board 83a receives the power re-on command (BA07H), the liquid crystal display means 66 displays a message such as "RAM error. Please turn the power back on and set the setting to 1."

[0088] The system then enters a power restart wait state (Sf4, Sf5), in which the first power supply abnormality check process (FIG. 12) is repeated indefinitely. In this manner, in this embodiment, in the event of a RAM abnormality or backup abnormality, the system is configured to forcibly restart the power supply by entering the power restart wait state. Note that if the power restart wait process (S20) is executed due to a RAM abnormality, if the next time the power is turned on, W(1,1,1) is not displayed, a RAM abnormality is again determined, and the power restart wait process (S20) is executed. Therefore, when the system enters the power restart wait state and the power is turned on again, it is necessary to open the door (front frame 3) and turn on both the setting change operating means 93 and the RAM clear switch 92, thereby executing the setting change process (S17), and setting the desired value.

[0089] In this way, in the case of a "RAM abnormality," the device enters a power-on wait state in order to execute the setting change process by powering the device back on and set the setting value to a normal value. In contrast, in the case of a "setting change" that executes the setting change process, there is no need to enter a power-on wait state even if there is a RAM abnormality. Therefore, in this embodiment, in order to eliminate unnecessary processing, the RAM abnormality determination process (S19) is executed after the setting change branch determination process (S16).

[0090] Returning to the RAM abnormality determination process in S19, the explanation will continue. If it is determined in S19 that neither a RAM abnormality nor a backup abnormality exists, the process proceeds to SYSTEM_800 in FIG. 13, i.e., the RAM clear branch determination process (S21) (Se4). This RAM clear branch determination process (S21) determines whether or not to select the "RAM clear" processing mode. As shown in FIG. 13, first, the value of the sixth bit of the W register is transferred to the carry flag (CF) (Sg1). If the carry flag (the sixth bit of the W register) is 1, i.e., if the RAM clear switch 92 is ON, the "RAM clear" processing mode is selected, and the process jumps to SYSTEM_500, i.e., the RAM clear processing (S18) described above (Sg2). Otherwise, the process proceeds to the next step, SYSTEM_900, i.e., the setting check branch determination process (S22).

[0091] In this embodiment, of the eight combinations of values ​​of the 0th, 5th, and 6th bits of the W register, the RAM clear branch judgment process (S21) is executed for seven combinations other than W(1,1,1), and of these, "RAM clear" is selected for three combinations: W(1,0,1), W(0,1,1), and W(0,0,1) (see Figure 15), so in this S21, it is sufficient to judge only the 6th bit of the 0th, 5th, and 6th bits of the W register.

[0092] The RAM clear process (S18) that is executed after the RAM clear branch determination process (S21) is different from the process executed after the setting change process (S17) and starts from Sd1. That is, first, the address of the RAM clear command transmission address table is set in the HL register (Sd1), and the transmission command table selection process (Sd2) described above is executed based on the command transmission address table. In the RAM clear command transmission address table, for example, as shown in FIG. 17(a2), the loop count is set to 3, and addresses of three command creation tables are set: the RAM clear command creation table (FIG. 17(b)), the spec command creation table (FIG. 17(c)), and the customer waiting command creation table (FIG. 17(d)). Therefore, Sd2 sequentially transmits BA02H (RAM clear command data), F611H (spec command data), and BA04H (customer waiting command data). The process from Sd3 onward in the RAM clear process (S18) has already been described.

[0093] As described above, the RAM clear process (S18) does not clear the setting value work area, so in this embodiment, the RAM abnormality determination process (S19) is executed before the RAM clear branch determination process (S21).

[0094] Returning to the RAM clear branch determination process (S21), the explanation will continue. The setting check branch determination process (S22), which is entered when it is determined in S21 that the sixth bit of the W register is not 1, determines whether to select a processing mode of "setting check" or "backup recovery." In this way, by performing the setting check branch determination process (S22) after the RAM abnormality determination process (S19), it is possible to avoid a situation in which recovery is not possible due to a RAM abnormality after it has been determined that setting check or backup recovery is to be performed.

[0095] In the setting check branch judgment process (S22), as shown in FIG. 13, the value of the W register is first compared with "00100001B" to determine the difference (Sh1). The value obtained is 0 when the 0th and 5th bits of the W register are 1 and the 6th bit is 0 (=W(1,1,0)), i.e., when the door (front frame 3) is open, the setting change operation means 93 is ON, and the RAM clear switch 92 is OFF (see FIG. 15). If the obtained value (difference) is 0, the zero flag is set to 1. If the value obtained in Sh1 is not 0 (zero flag = 0), i.e., not W(1,1,0), the "backup restoration" processing mode is selected instead of the "setting check," and the next setting check process (S23) is skipped, and the process proceeds to SYSTEM_1100, i.e., the backup restoration process (S24) (Sh2).

[0096] In this embodiment, of the eight combinations of values ​​of the 0th, 5th, and 6th bits of the W register, the setting confirmation branch judgment process (S22) is executed only for the four cases where the 6th bit is 0, and of these, "setting confirmation" is selected only for W(1,1,0), so for all the other three cases, W(1,0,0), W(0,1,0), and W(0,0,0), the "backup recovery" processing mode is selected (see Figure 15).

[0097] In the backup recovery process (S24), as shown in Fig. 13, first, the backup recovery command transmission process (M_MKINFO) is called (Sj1). In this backup recovery command transmission process (Sj1), as shown in Fig. 21, first, a backup recovery command transmission address table is selected (S101), and based on that command transmission address table, the transmission command table selection process (S102) already described in Fig. 18 is executed. In the backup recovery command transmission address table of this embodiment, as shown in Fig. 23(a), the number of loops is set to 3, and addresses of three types of command creation tables are set: a power failure recovery display command creation table, a first special reserved number designation command creation table, and a second special reserved number designation command creation table.

[0098] As described above, in the transmission command table selection process (FIG. 18), after the loop number is obtained from the specified command transmission address table (here, FIG. 23(a)) (S81), the address of the command creation table is specified (S82), and the process of executing the command data creation process (FIG. 19) based on the specified command creation table (S83) is repeated the number of times equal to the loop number.

[0099] In the command data creation process (Fig. 19), the command data and the additional value are obtained from the specified command creation table, and the additional value is added to the command data to create command data (S91), which is then sent (S92). In the power outage recovery display command creation table shown in Fig. 23(b), the additional value is set to 0 and the command data is set to BA03H, so the power outage recovery display command sent will be BA03H. On the other hand, in the first special hold quantity designation command table shown in Fig. 23(c), the additional value is set to the value of the first special hold quantity work, and the command data is set to B001H. Since the value of the first special hold quantity work is any one of 0 to 4, the first special hold quantity designation command sent will be any one of B001H to B005H, corresponding to the first special hold quantities of 0 to 4. Similarly, in the second special hold quantity designation command table shown in Figure 23(d), the value of the second special hold quantity work is set as the additional value, and the command data is set to B101H, so the second special hold quantity designation command sent will be one of B101H to B105H corresponding to the second special hold quantities 0 to 4.

[0100] Following the transmission command table selection process of S102, a second command data creation process (S103) is executed. In this second command data creation process (S103), as shown in Fig. 22, first, data of a spec command (F611H) is obtained (S111) and sent (S112). Then, data of one or more types of state designation commands (FAxxH to ​​FDxxH) is obtained (S113) and sent (S114).

[0101] Following the second command data creation process (S103) described above, it is determined whether the first and second special symbols are currently changing (S104), and if they are not currently changing (S104: Yes), the data for the customer waiting command (BA04H) is obtained (S105) and sent (S106).

[0102] As described above, the backup recovery command sending process (Sj1) sequentially sends BA03H (power outage recovery display command), B0xxH (first special hold number specification command), B1xxH (second special hold number specification command), F611H (spec command), FAxxH to ​​FDxxH (status specification command), and if the pattern is not changing, BA04H (customer waiting command) is sent.

[0103] Returning to FIG. 13, the explanation continues. Following the backup recovery command transmission process (Sj1) described above, the address of the backup flag in the in-area RAM is set in the HL register (Sj2), and the value obtained by subtracting the address of the backup flag from the address of the prize slot error detection timer 3 in the in-area RAM and adding 1 is set in the B register (Sj3), and the 0 clear process is called (Sj4). In this embodiment, the beginning of the in-area RAM is the setting value work area, followed by the backup flag work area. The area between the backup flag work area and the prize slot error detection timer 3 work area is the error-related work area. Therefore, the backup flag work area in the in-area RAM and the subsequent error-related work area are cleared to 0 by the above steps Sj2 to Sj4. In this way, even when the backup is restored, only the error-related work area (in-area error information) is cleared to 0, so that error information from before the power outage is not carried over.

[0104] Returning to the setting check branch determination process (S22), the explanation will continue. In Sh2 of Fig. 13, if the value obtained in Sh1 is 0 (zero flag = 1), that is, if W(1,1,0), the "setting check" processing mode is selected, and the process proceeds to the next setting check process S23 without jumping to SYSTEM_1100 (backup restoration process (S24)).

[0105] In the setting confirmation process (S23), as shown in Figure 13, first, E021H (setting confirmation command data) indicating that the setting confirmation period has started is stored in the DE register (Si1), and the command data is transmitted by the command transmission process (Si2). When the performance control board 83a receives the setting confirmation command (E021H), the liquid crystal display means 66 displays "setting confirmation in progress" or the like.

[0106] Also, the setting value data is obtained from the setting value work area of ​​the internal RAM and stored in the C register (Si3). Then, the processes of Si4 to Si15 are repeatedly executed until the condition of Si7 is met and a jump to SYSTEM_1060 (Si16) is made. In this loop process of Si4 to Si15, the first power supply abnormality check process (FIG. 12) is first executed (Si4), and the data of input port 1 (P_INPT1) (FIG. 14) is input to the A register (Si5). Then, by calculating the logical product (AND) of the value of the A register and the mask data "00000001B", bits other than the 0th bit corresponding to the ON / OFF signal of the setting change operation means 93 are masked, and the A register is updated with the masked data (Si6). As a result, when the setting change operation means 93 is ON (the 0th bit of the input port is 1), the value of the A register becomes "00000001B", and when the setting change operation means 93 is OFF (the 0th bit of the input port is 0), the value of the A register becomes "00000000B" and the zero flag is set to 1.

[0107] If the zero flag is 1 (the setting change operation means 93 is OFF), the process exits the loop of Si4 to Si15 and jumps to SYSTEM_1060 (Si16), but if the zero flag is 0 (the setting change operation means 93 is ON), the process moves to the next step, Si8 (Si7). In Si8, "00000010B" is input into the A register, and the value of this A register is output to external output port 2 (P_GAIBU2) (Si9). This causes a setting confirmation signal to be output to the hall computer.

[0108] Then, the first address of the setting display data table is set in the HL register (Si10), the setting value data (see Si3) stored in the C register is transferred to the A register (Si11), and the display pattern data is read from the address obtained by adding the value of the A register (setting value data) to the value of the HL register (first address of the setting display data table) and set to the W register (Si12). As a result, the W register is set to display pattern data corresponding to the setting value data, for example, "00000110B" to display "1" if the setting value data is 0, or "01111101B" to display "6" if the setting value data is 5.

[0109] Next, common data "00010000B" that turns on common C4 (FIG. 7) corresponding to the 7-segment display unit 97a is set in the A register (Si13), and the value of the A register is output to the LED common port (FIG. 7) and the value of the W register is output to LED data port 2 (FIG. 7) (Si14). As a result, one of "1" to "6" corresponding to the setting value data is displayed on the 7-segment display unit 97a of the setting display means 94, i.e., the performance information display means 97.

[0110] In this way, in the setting confirmation process S23, setting display data is created based on the setting value data acquired from the setting value work, so the value (for example, any of "1" to "6") displayed on the setting display means 94 during the setting confirmation period is the confirmed setting information at that time, unlike during the setting change period. Therefore, for example, a "." (dot) is not added to the "1" to "6" displayed on the setting display means 94 during the setting confirmation period.

[0111] When Si14 ends, the process jumps to SYSTEM_1050, and the processes from Si4 onwards are executed again. Then, when it is determined in Si7 that the zero flag is 1 (the setting change operation means 93 is OFF), the setting confirmation period ends, the process leaves this loop and jumps to SYSTEM_1060, and the processes from Si16 onwards are executed. That is, the WA register is cleared by calculating an exclusive OR (XOR) between the values ​​of the WA register and updating the value of the WA register with the obtained value (Si16), and the value of the A register of the WA register is output to the LED common port (Fig. 7), and the value of the W register is output to LED data port 2 (Fig. 7) (Si17), thereby stopping the display of the setting information on the setting display means 94.

[0112] Also, by outputting the value of the A register to external output port 2 (P_GAIBU2) (Si18), the output of the setting confirmation signal is stopped. Then, the value of the E register is incremented (Si19), and the command data is sent by the command sending process (Si20). At the time of execution of Si19, E021H is set in the DE register (see Si1), so by incrementing the E register in Si19 and then executing the command sending process (Si20), E022H (setting confirmation end command) is sent to the performance control board 83a. Note that when the performance control board 83a receives the setting confirmation end command (E022H), the display of "setting confirmation in progress" etc. on the liquid crystal display means 66 ends.

[0113] In this embodiment, when the power is turned on, if the setting change operation means 93 is ON, the RAM clear switch 92 is OFF, and the door is open (W(1,1,0)), the setting information at that time (for example, any one of 1 to 6) is displayed on the setting display means 94 during the setting confirmation period until the setting change operation means 93 is switched OFF.

[0114] Following the setting confirmation process (S23) above, the backup restoration process (S24) already explained is executed.

[0115] When the above steps S15 to S24 are completed, the process proceeds to the process in Fig. 11, where the error information clearing process of S25 to S28 is executed. That is, first, all register information is saved (S25), and then the process proceeds to the out-of-area error information clearing process (S26) (calling the out-of-area program). This out-of-area error information clearing process (S26) is an out-of-area process executed by the out-of-area program, and as shown in Fig. 24, first the in-area stack pointer is saved (S301), and after setting the out-of-area stack pointer (S302), the RAM clear flag is judged (S303). This RAM clear flag indicates whether the RAM is cleared or restored to a backup, and as already explained, 5AH is set in SD7a (Fig. 13) of the RAM clearing process (S18).

[0116] If the RAM clear flag is 5AH (when clearing RAM), out-of-area error information stored in the out-of-area RAM that is to be cleared when clearing RAM is cleared (S304), and if the RAM clear flag is not 5AH (when restoring from backup), the information to be cleared when restoring from backup is cleared (S305).

[0117] Here, we will briefly explain the out-of-area error information (Figure 20(b)). The out-of-area error flag indicates whether or not an error is being reported for multiple types of out-of-area errors (here, three types: magnetic error, radio wave error, and prize slot error), with bits 0 to 2 corresponding to prize slot error, radio wave error, and magnetic error, respectively. The detection timers for radio wave error, magnetic error, and prize slot error are used to measure the error judgment time. The notification timers for radio wave error, magnetic error, and prize slot error are used to measure the error notification period.

[0118] In this embodiment, as shown in Figure 20(b), when the RAM is cleared, all of the out-of-range error information is cleared, whereas when the backup is restored, only the out-of-range error flag and each detection timer are cleared out of the out-of-range error information, and the notification timers are not cleared. As a result, if an out-of-range error was being notified before the power outage, the error notification will continue even after the power is restored.

[0119] When the out-of-area error information clearing process (S304, S305) is completed, the in-area stack pointer is set (S306), the out-of-area error information clearing process (FIG. 24) is completed, and the process returns to the in-area processing.

[0120] 11, the explanation will be continued. When the out-of-area error information clearing process (S26) is completed, all register information is restored (S27), and then an in-area error information, etc. clearing process (S28) is executed. In this in-area error information, etc. clearing process (S28), in addition to the in-area error information stored in the in-area RAM, the level / edge data of various switches (e.g., door open switch 44) used to determine in-area errors, the RAM clear flag, etc. are cleared.

[0121] Here, we will briefly explain the in-area error information (Figure 20(a)). The backup flag indicates whether backup recovery is possible or not. The power supply abnormality confirmation counter is a counter used when checking for power supply abnormalities, and the dispensing communication abnormality confirmation counter is a counter used when checking for communication abnormalities with the dispensing control board 90a. The serial circuit error flag indicates whether there is a serial circuit error related to the circuit for serial transmission of dispensing, etc., and the random number circuit abnormality confirmation flag indicates whether there is a random number circuit abnormality related to the random number circuit. The in-area error flag indicates whether an error is being reported for a specified in-area error (here, five types: ball jam error, supply out error, counting error, open wire error, and door open error), and bits 0 to 4 correspond to ball jam error, supply out error, counting error, open wire error, and door open error, respectively.

[0122] When the error information clearing process of S25 to S28 is completed, the CTC (Counter Timer Circuit) is set so that a timer interrupt is executed at a cycle of, for example, 4 ms (S29), and an initial setting process (S30) is executed.

[0123] In this initialization process (S30), as shown in FIG. 25, the address of the initialization table is first loaded into the HL register (S121), and data set processing is called (S122), thereby setting an initial value to the operation check timer and turning on the launch control signal. The operation check timer is used to measure the execution time of the operation check of the performance display means 95. It is stored, for example, in internal RAM, and its initial value is set to, for example, a value obtained by adding 1 to a timer value corresponding to 4800 ms. In this embodiment, the operation check timer is decremented by 1 in the timer interrupt processing executed every 4 ms, as described below (S132 in FIG. 27). Therefore, the timer value corresponding to 4800 ms is 1200, and the initial value of the operation check timer is 1201, which is the value obtained by adding 1 to this value. In this manner, in this embodiment, the operation check timer is initialized during power-on processing (before the main loop processing).

[0124] Following the initial setting process (S30), a game start command (BA77H) is sent to the performance control board 83a (S31), and then the main loop process (S32-S37) is executed. In this main loop process, interrupts are prohibited (S32), various random numbers are updated (S33), all registers are saved to the stack area (S34), and after executing the main loop outside area process (S35) (calling the outside area program), all registers are restored (S36), and interrupts are permitted (S37). This repeatedly executes a series of processes. As a result, the timer interrupt process is called and executed, for example, at a 4 ms interval.

[0125] Here, the in-main loop out-of-area processing (S35) is out-of-area processing executed by the out-of-area program, and as shown in Fig. 26, first the in-area stack pointer is saved (S123), and then the out-of-area stack pointer is set (S124), after which the performance display RAM initialization determination processing (S125) is executed. In this performance display RAM initialization determination processing (S125), it is determined whether or not there is an abnormality in the RAM area related to the display (performance display) of the performance display means 95, and if there is an abnormality, the out-of-area RAM initialization processing is executed.

[0126] This out-of-area RAM initialization process may be configured to clear the RAM area related to the performance display that has been determined to be abnormal by clearing the RAM area of ​​the out-of-area RAM excluding the area for out-of-area error information, but considering the possibility that the out-of-area error information may also be abnormal, it may also be configured to clear the entire out-of-area RAM area, including the area for out-of-area error information. The RAM area related to the performance display includes the RAM area used to update the display, the RAM area used to tally base values, and the RAM area that is determined to be abnormal only when the power is turned on for the first time.

[0127] In this embodiment, even if it is determined that there is an abnormality in the out-of-area RAM in the performance display RAM initialization determination process (S125), an error command is not sent, but the configuration may be such that an error command is sent in this case as well.

[0128] Following the performance display RAM initialization determination process (S125), a performance display monitor tallying process (S126) is executed. This performance display monitor tallying process (S126) calculates a base value to be displayed on the performance display means 95. During a unit measurement period until the number of outs reaches a predetermined number (for example, 60,000), the "number of payouts in a low probability state" and the "number of outs in a low probability state" are counted, and the real-time base value is calculated by dividing the former by the latter.

[0129] In the performance display monitor tallying process (S126), the counting process of the "number of payouts in a low probability state" and the "number of outs in a low probability state" is always performed, but the division process to calculate the real-time base value using these count values ​​is performed when a start value is set in the tally division counter described below, and is not performed at any other time. Also, when the unit measurement period ends, the real-time base value at that time becomes the new first cumulative base value, and the first and second cumulative base values ​​up to that point become the new second and third cumulative base values, respectively.

[0130] After the performance display monitor tallying process (S126) is executed, the in-area stack pointer is restored (set) (S127), and the in-main loop out-area process is terminated.

[0131] Next, the timer interrupt process of the main control board 82a (FIG. 27) will be described. In this timer interrupt process (FIG. 27), first, a second power supply abnormality check process (S131) ​​is executed. In this second power supply abnormality check process, as shown in FIG. 28, first, the power supply abnormality signal transmitted from the power supply board 89a is read twice (S151). Then, it is determined whether the levels of the power supply abnormality signals read twice match (S152). If they do not match (S152: No), the process returns to S151. If they match (S152: Yes), it is determined whether the level of the power supply abnormality signal is at the "H" level (ON) (S153).

[0132] If the level of the power supply abnormality signal is not "H" level (ON) (S153: No), the backup flag (Fig. 20(a)) is set to OFF (≠ 5AH) (S154), and the value of the power supply abnormality confirmation counter (Fig. 20(a)) is cleared (S155), and the second power supply abnormality check process is terminated.

[0133] On the other hand, if the level of the power supply abnormality signal is "H" level (ON) (S153: Yes), the value of the power supply abnormality confirmation counter is incremented (S156), and it is determined whether the value of the power supply abnormality confirmation counter after the increment has reached, for example, 2 (S157). If the value of the power supply abnormality confirmation counter is less than 2 (S157: No), the second power supply abnormality check process is ended.

[0134] If the value of the power supply abnormality confirmation counter reaches 2 in S157 (S157: Yes), it is determined that a power supply abnormality has occurred, and backup processing (S158-S161) of the data (game information) stored in the internal RAM is performed. That is, the value of the power supply abnormality confirmation counter is cleared (S158), the launch control signal is set to OFF (S159), and the backup flag is set to 5AH (S160). Then, a checksum is calculated by performing continuous 8-bit addition on the working area of ​​the internal RAM, and the calculation result (SUM address) is saved as a checksum value in the SUM storage area of ​​the internal RAM (S161).

[0135] After that, a power-off command is sent to the performance control board 83a, etc. (S162), and the protection of the RAM in the area is enabled and the prohibited area is disabled (S163). This prohibits data writing to the RAM in the area in subsequent processing. In addition, output data from all output ports is cleared (S164), and timer interrupts are prohibited by setting processing for the CTC (S165). Then, an infinite loop is repeated while clearing the WDT, waiting for the power supply voltage to drop and the CPU to enter a non-operating state.

[0136] After the second power supply abnormality check process (S131 in Figure 27) is completed, the following processes are executed: a timer management process (S132) that manages various timers used for game control; an input management process (S133) that manages detection information from various sensors such as game ball detection means and operation means provided in each winning means; a setting abnormality check process (S134) that checks for abnormalities in setting values; an area error determination process (S135) that determines errors within the area; an area random number circuit process (S136) that updates various random numbers such as jackpot determination random numbers; and an area prize ball process (S137) that manages prize balls, such as sending payout control commands to the payout control board 90a.

[0137] Here, in the timer management process (S132), for example, a subtraction process of the operation check timer is also performed. This subtraction process of the operation check timer is performed, for example, until the value of the operation check timer reaches 0. The operation check timer is set to a value obtained by adding 1 to the timer value corresponding to the operation check time (here, 4800 ms) in the initial setting process (S30, FIG. 25) when the power is turned on, specifically a value of 1201. Therefore, in the first timer management process (S132) after the power is turned on, 1 is subtracted from the timer value, becoming 1200 corresponding to 4800 ms.

[0138] Here, the details of the in-area error determination process (S135), in-area random number circuit process (S136), and in-area prize ball process (S137) will be explained. In the in-area error determination process (S135), as shown in Fig. 29, first the in-area error flag (Fig. 20(a)) is obtained (S311), and the first address of the error command table is referenced (S312). Note that the error command table stores information specifying an error notification command and an error release command for each of multiple types of in-area errors (here, five types: door open error, wire break error, count error, out of supply error, and ball jam error).

[0139] Then, the process of S314 to S317 is repeated while incrementing the table address (S318), i.e., while changing the type of in-area error, until the END address of the error command table is reached (S313: No). In S314, a predetermined bit of the current in-area error flag (for example, the fourth bit in the case of a door open error) is compared with a predetermined bit of the previous in-area error flag, and if they are the same (S314: No), the table address is incremented (S318) and the process proceeds to S313.

[0140] On the other hand, if the two are different in S314 (S314: Yes), it is determined whether the error notification has ended, i.e., whether a predetermined bit of the in-area error flag has changed from 1 (ON) to 0 (OFF) or from 0 (OFF) to 1 (ON) (S315). If the error notification has not ended (0 → 1) (S315: No), an error notification command corresponding to the in-area error is sent (S316). If the error notification has ended (1 → 0) (S315: Yes), an error reset command corresponding to the in-area error is sent (S317). Then, the table address is incremented (S318), and the process returns to S313. The error notification command and the error reset command are sent using a common in-area command sending module.

[0141] If it is determined in S313 that the END address of the error command table has been reached, that is, if the processing of S314 to S317 has been completed for all of the multiple types of in-area errors (S313: No), the in-area error determination processing ends.

[0142] Next, the in-area random number circuit processing (S136) will be explained. In the in-area random number circuit processing (S136), as shown in Figure 30, first the value of the random number circuit abnormality confirmation flag (Figure 20(a)) is determined (S321), and if the random number circuit abnormality confirmation flag is 5AH, that is, if the random number circuit is already in an abnormal state, the in-area random number circuit processing is terminated.

[0143] If the random number circuit abnormality confirmation flag is not 5AH in S321, a random number value is obtained and stored in a predetermined area of ​​the in-area RAM (S322), and a determination is made as to whether or not there is a random number circuit abnormality (for example, the hardware random number circuit is not running) (S323). If there is no random number circuit abnormality (S323: No), the in-area random number circuit processing is terminated. On the other hand, if there is a random number circuit abnormality (S323: Yes), the random number value obtained in the in-area RAM is cleared (S324), the random number circuit abnormality confirmation flag is set to 5AH (S325), and a random number circuit abnormality command is sent (S326), and the in-area random number circuit processing is terminated. Note that this random number circuit abnormality command is sent using the same in-area command sending module as the error notification / clearance command in the in-area error determination processing (Figure 29).

[0144] Next, the in-area prize ball processing (S137) will be explained. In the in-area prize ball processing (S137), as shown in Figure 31, first the value of the serial circuit error flag (Figure 20(a)) is judged (S331), and if the serial circuit error flag is 5AH, that is, if a serial circuit error has already occurred, the in-area prize ball processing is terminated.

[0145] If the serial circuit error flag is not 5AH in S331, it is determined whether the payout communication is normal (S332), and if the payout communication is not normal (S332: No), the payout communication abnormality confirmation counter is incremented (S333). Then, if the payout communication abnormality confirmation counter after increment has not yet reached a predetermined value (S334: No), the in-area prize ball processing is terminated, but if the payout communication abnormality confirmation counter is at a predetermined value, that is, if the determination that the payout communication is not normal has continued for a predetermined number of times (S334: Yes), a payout communication abnormality command is sent (S335), and the in-area prize ball processing is terminated.

[0146] On the other hand, if the payout communication is normal in S332 (S332: Yes), the payout communication abnormality confirmation counter is cleared to 0 (S336), the winning information and prize ball output information are updated (S337, S338), and a prize ball number designation command is output (S339). Then, it is determined whether the serial transmission status is an abnormal value (S340), and if it is not an abnormal value (S340: No), the in-area prize ball processing is terminated, but if the serial transmission status is an abnormal value (S340: Yes), a serial transmission abnormality command is sent (S341), and the serial circuit error flag is set to 5AH (S342), and the in-area prize ball processing is terminated.

[0147] In addition, the dispensing communication abnormality command and serial transmission abnormality command are sent using the same intra-area command sending module as the error notification / cancellation command in the intra-area error determination processing (Figure 29) and the random number circuit abnormality command in the intra-area random number circuit processing (Figure 30).

[0148] Following the above-mentioned in-area error determination process (S135), in-area random number circuit process (S136), and in-area prize ball process (S137), normal symbol management process (S138), normal electric device management process (S139), special symbol management process (S140), and special electric device management process (S141) are executed.

[0149] The normal pattern management process (S138) manages the fluctuation of normal patterns by the normal pattern display means 51, and based on the detection of a game ball by the normal pattern start means 61, normal random number information such as a hit determination random number value is obtained and the normal random number information is stored in a first-in, first-out memory area up to a maximum reserved number (for example, 4), and when the normal pattern display means 51 is in a state where it can display changes and the number of reserved normal numbers is 1 or more, the first hit determination random number value is taken out from the queue of normal random number information, and a hit / miss determination is made depending on whether the hit determination random number value matches the hit determination value, and based on the hit determination result, a stop pattern and fluctuation time after the normal pattern changes are selected, and the normal pattern is changed by the normal pattern display means 51.

[0150] In addition, the normal electric device management process (S139) manages the normal profit state, and when the stop pattern after the change of the normal pattern display means 51 becomes a winning pattern based on the winning judgment result of S138 being a winning one, a normal profit state is generated in which the opening / closing section 78 of the second special pattern starting means 63 is changed to an open state according to a predetermined opening / closing pattern.

[0151] The special symbol management process (S140) manages the variation of the first and second special symbols by the first and second special symbol display means 53, 54, and acquires first and second special random number information consisting of a jackpot determination random number value, a jackpot symbol random number value, and other random number values ​​based on the detection of a gaming ball by the first and second special symbol start means 62, 63, and stores the first and second special random number information in a first-in, first-out storage area up to an upper limit of reserved numbers (for example, four each), and when the first and second special symbol display means 53, 54 are in a state where they can display the variable symbols, If the number of second special reserved items is 1 or more, the first jackpot determination random number is taken from the queue for the second special random number information, and if only the number of first special reserved items is 1 or more, the first jackpot determination random number is taken from the queue for the first special random number information, and a random number lottery using the jackpot determination random number is carried out to determine whether there is a jackpot or a loss with a predetermined jackpot probability, and depending on the jackpot determination result, the stopping pattern of the first and second special symbols, the variation pattern of the performance symbols, etc. are determined, and the first and second special symbols are varied by the first and second special symbol display means 53, 54.

[0152] The special electric device management process (S141) manages the jackpot game, and when the result of the jackpot determination is a jackpot and the stopped pattern after the first and second special pattern display means 53, 54 change to a jackpot pattern, a jackpot game (first and second special profit states) is generated in which the jackpot winning means 64 is changed to an open state according to a predetermined opening pattern.

[0153] Following the special electric accessory management process (S141), external terminal process (S142) and LED management process (S143) are executed. In the external terminal process (S142), various information is output from the external output terminal to an external device such as a hall computer.

[0154] The LED management process (S143) manages the light emission of the LEDs constituting the game information display means 50, performance display means 95 (performance information display means 97), etc. As shown in Fig. 32, first, a clear signal is output to the LED common port and the LED data port to clear the ports (S171), and the LED output counter is incremented (S172). Then, common data corresponding to the value of the LED output counter is selected from the LED common output selection table (Fig. 33(a)) (S173), and output to the LED common port (S174).

[0155] As shown in Figures 33(a) and 7, the LED common output selection table of this embodiment has four types of common data: first common data that turns on commons C0 and C4, second common data that turns on commons C1 and C5, third common data that turns on commons C2 and C6, and fourth common data that turns on commons C3 and C7, and these first to fourth common data are cyclically selected in that order as the LED output counter increases.

[0156] As a result, for each interrupt (here, every 4 ms), the lighting target of the game information display means 50 changes sequentially from LED group 50a → 50b → 50c → 50d → 50a → ..., and similarly, the lighting target of the performance display means 95 (performance information display means 97) changes sequentially from 7-segment display section 97a → 97b → 97c → 97d → 97a → ....

[0157] Next, the value of the 5th bit of the LED output counter is determined (S175) when the least significant bit is the 0th bit, and one of the two LED data output information tables A and B (FIG. 33(b)) is selected according to that value (S176a, 176b). This makes it possible to switch the LED data output information table every 32 interrupts (128 ms).

[0158] Here, the LED data output information tables A and B correspond to the LED data port 1 connected to the gaming information display means 50, and first to fourth LED data A0 to A3 and B0 to B3 corresponding to the first to fourth common data are provided as shown in Fig. 33. That is, the first LED data A0 and B0 are the LED data of the LED group 50a of the gaming information display means 50 corresponding to the common C0, the second LED data A1 and B1 are the LED data of the LED group 50b of the gaming information display means 50 corresponding to the common C1, the third LED data A2 and B2 are the LED data of the LED group 50c of the gaming information display means 50 corresponding to the common C2, and the fourth LED data A3 and B3 are the LED data of the LED group 50d of the gaming information display means 50 corresponding to the common C3.

[0159] When either the LED data output information table A or B is selected (S176a, S176b), the LED data corresponding to the value of the LED output counter is selected from that LED data output information table (S177), that LED data is output to the LED data port 1 (S178), and the LED management process ends. This allows the four LED groups 50a to 50d of the game information display means 50 to be turned on while being switched in sequence every 4 ms, and further allows the same group to be switched between two types of display modes every 128 ms.

[0160] Returning to the timer interrupt process of FIG. 27, the explanation will continue. When the LED management process (S143) described above is completed, the contents of all registers are saved to the stack area (S144), and then the timer interrupt out-of-area process (S145) is executed (calling the out-of-area program). This timer interrupt out-of-area process (S145) is an out-of-area process executed by the out-of-area program, and as shown in FIG. 34, first the in-area stack pointer is saved (S351), and then the out-of-area stack pointer is set (S352), and then the out-of-area timer subtraction process (S353) is executed. In this out-of-area timer subtraction process (S353), as shown in FIG. 35, the start address of the out-of-area error notification timer table is referenced (S361). This out-of-area error notification timer table stores information specifying an error notification timer for each of multiple types of out-of-area errors (here, three types: radio wave error, magnetic error, and prize slot error).

[0161] Then, until the END address of the out-of-area error notification timer table is reached (S362: No), the table address is incremented (S364), i.e., the type of out-of-area error is changed, and the notification timer decrement process (S363) is repeatedly executed. Then, when it is determined in S362 that the END address of the out-of-area error notification timer table has been reached, i.e., when the notification timer decrement process (S363) has been completed for all of the multiple types of out-of-area errors (S362: No), the out-of-area timer decrement process ends.

[0162] Following the out-of-area timer subtraction process (S353), an out-of-area error determination process (S354) is executed. In this out-of-area error determination process (S354), as shown in FIG. 36, a monitoring process (S371) is first executed. In this monitoring process (S371), as shown in FIG. 37, the first address of the error monitoring table is referenced (S391). The error monitoring table stores information specifying the error detection timer and error notification timer for each of multiple types of out-of-area errors (here, three types: radio wave error, magnetic error, and prize slot error).

[0163] The process of S393 to S403 is then repeated while incrementing the table address (S404) until the END address of the error monitoring table is reached (S392: No), i.e., while changing the type of out-of-range error. First, in S393, the number of loops for the next process of S394 is set according to the type of out-of-range error. In this embodiment, this number of loops is set to 1 for radio wave errors and 13 for magnetic errors and prize slot errors. Then, the value of the corresponding input port (for example, the input port corresponding to the radio wave sensor in the case of a radio wave error) is read twice (S394), and if the two values ​​are the same, the loop number is decremented (S396). This process is repeated until the loop number reaches 0 (S397: Yes). If the two values ​​read in S394 are not the same (S395: No), the process returns to S393 and the loop number is set again. In other words, the input port double reading process of S394 is repeated until the two values ​​become the same in the case of a radio wave error (loop number 1), and in the case of a magnetic error or a prize slot error, it is repeated until the two values ​​become the same 13 times in a row (loop number 13).

[0164] If it is determined in S397 that the number of loops has reached 0, it is determined whether or not an error has been detected based on the value of the input port that was read (S398), and if it is determined that an error has been detected (S398: Yes), the corresponding error detection timer (for example, a radio error detection timer in the case of a radio error) is incremented (S399), and it is determined whether or not the value of the error detection timer after the increment has reached an error determination value corresponding to the type of error (S400). In this embodiment, this error determination value is set to 2 for a radio error, and 251 for a magnetic error and a prize slot error.

[0165] If it is determined in S400 that the value of the error detection timer has not reached the error determination value (S400: No), the table address is incremented (S404), and the process proceeds to S392. On the other hand, if it is determined in S400 that the value of the error detection timer has reached the error determination value (S400: Yes), the value of the error detection timer is decremented (S401), and the corresponding error notification timer (e.g., the radio wave error notification timer in the case of a radio wave error) is set to an initial value corresponding to, for example, 30 seconds (S402), the table address is incremented (S404), and the process proceeds to S392. Also, if it is determined in S398 that no error has been detected (S398: No), the error detection timer is cleared (S403), the table address is incremented (S404), and the process proceeds to S392. In this way, if the error detection state continues a predetermined number of times depending on the type of error (twice in the case of a radio wave error), it is determined that an error has occurred.

[0166] If it is determined in S392 that the END address of the error monitoring table has been reached, that is, if the processing of S393 to S403 has been completed for all of the multiple types of out-of-area errors (S392: No), the monitoring processing ends.

[0167] If it is determined in S400 that the value of the error detection timer has reached the error determination value, the value of the error detection timer is decremented (S401) and the corresponding error notification timer is set to its initial value (S402). Therefore, in the next and subsequent interrupts, unless it is determined in S398 that no error is detected, it is determined that the value of the error detection timer has reached the error determination value and the error notification timer is set to its initial value (S402). Thus, the value of the error notification timer after an error determination is repeatedly reset to its initial value until it is determined in S398 that no error is detected and the error detection timer is cleared. Therefore, even if it is decremented by the out-of-area timer subtraction process (S353; FIG. 35), it does not actually decrease. If it is determined in S398 that no error is detected and the error detection timer is cleared, the error notification timer is no longer reset to its initial value, and the out-of-area timer subtraction process (S353; FIG. 35) effectively starts decreasing the value of the error notification timer.

[0168] Returning to Figure 36, the explanation will continue. Following the above monitoring process (S371), the first address of the error timer monitoring table is referenced (S372). This error timer monitoring table stores information specifying an error notification timer and an out-of-area error flag for each of several types of out-of-area errors (here, three types: radio wave error, magnetic error, and prize slot error).

[0169] Then, the processing of S374 and S375 is repeatedly executed while incrementing the table address (S376), i.e., while changing the type of out-of-range error, until the END address of the error timer monitoring table is reached (S373: No). In S374, it is determined whether the value of the corresponding error notification timer is 0, and if the value of the error notification timer is not 0 (S374: Yes), error status information (e.g., 1) is set in the corresponding bit of the out-of-range error flag (e.g., the second bit in the case of a magnetic error). As a result, the value of the out-of-range error flag changes from 0 to 1 when it is determined in S400 of Fig. 37 that the value of the error detection timer has reached the error determination value, and then changes from 1 to 0 when a predetermined time (e.g., 30 seconds) has elapsed since it was determined in S398 of Fig. 37 that no error was detected.

[0170] Then, when it is determined in S373 that the END address of the error timer monitoring table has been reached, that is, when the processing of S374 and S375 has been completed for all of the multiple types of out-of-area errors (S373: No), the first address of the error command table is then referenced (S377).The error command table stores information specifying an error notification command and an error release command for each of the multiple types of out-of-area errors (here, three types: radio wave error, magnetic error, and prize slot error).

[0171] Then, the process of S379 to S382 is repeated while incrementing the table address (S383), i.e., while changing the type of out-of-area error, until the END address of the error command table is reached (S378: No). In S379, a predetermined bit of the current out-of-area error flag (for example, the second bit in the case of a magnetic error) is compared with a predetermined bit of the previous out-of-area error flag, and if they are the same (S379: No), the table address is incremented (S383) and the process proceeds to S378.

[0172] On the other hand, if the two are different in S379 (S379: Yes), it is determined whether the change state is 1 → 0 or 0 → 1, i.e., whether the error notification has ended (S380). If a predetermined bit of the out-of-area error flag has changed from 0 → 1, i.e., if the error notification has not ended (S380: No), an error notification command corresponding to the out-of-area error is transmitted (S381). If the out-of-area error flag has changed from 1 → 0, i.e., if the error notification has ended (S380: Yes), an error reset command corresponding to the out-of-area error is transmitted (S382). Thereafter, the table address is incremented (S383), and the process proceeds to S378. The error notification command and the error reset command are transmitted using a common out-of-area command transmission module.

[0173] If it is determined in S378 that the END address of the error command table has been reached, that is, if the processing of S379 to S382 has been completed for all of the multiple types of out-of-area errors (S378: No), the out-of-area error determination processing ends.

[0174] Returning to Figure 34, the explanation will continue. Following the out-of-area error determination process (S354), a performance display monitor display update process (S355) is executed. This performance display monitor display update process (S355) performs an operation check in which the performance display means 95 repeatedly turns all lights on and all lights off for a predetermined operation check time (e.g., approximately 5 seconds), and then multiple base value display periods (real-time base value display period, first to third accumulated base value display periods) in which multiple types of base values ​​(here, four types: real-time base value, and first to third accumulated base values) calculated in the performance display monitor aggregation process (S126 in Figure 26) are displayed on the performance display means 95 are cyclically switched every predetermined time (e.g., 4.8 seconds).

[0175] The four 7-segment display units 97a to 97d (Figures 5 and 7) that make up the performance display means 95 are, for example, an identification display unit in which the top two digits indicate the type of base value (real-time base value, first to third cumulative base values), etc., and the bottom two digits are a numeric display unit that displays the numerical value of the base value, etc.

[0176] The base value is measured for each unit measurement period, which is the period until the number of outs reaches a predetermined number (here, 60,000). However, the first unit measurement period after the initial power-on does not start from the time the power is turned on, but after a predetermined pre-measurement period has elapsed (for example, when the number of outs reaches a predetermined number (here, 300)).

[0177] During the real-time base value display period, the identification display unit displays, for example, "bL." indicating the real-time base value, and the numeric display unit displays, for example, the real-time base value at the start of the real-time base value display period or immediately before that, but the display mode of "bL." on the identification display unit is changed, for example, to light up or flash, depending on whether the number of OUTs in the unit measurement period at that time has reached a predetermined threshold (for example, 6,000).The base value is rounded to one decimal place before being displayed on the numeric display unit, but if the rounded value is three digits or more, the numeric display unit will display "99." or the like to indicate overflow.

[0178] Furthermore, during the first to third cumulative base value display periods, the identification display section displays "b1." to "b3." indicating the first to third cumulative base values, and the numeric display section displays the first to third cumulative base values ​​at that time, but if the first to third cumulative base values ​​have not yet been obtained, the identification display section flashes and the numeric display section displays "--". Because none of the first to third cumulative base values ​​have been obtained until the end of the first unit measurement period, the display on the performance display means 95 during the first to third cumulative base value display periods will be "b1.--" to "b3.--".

[0179] During the pre-measurement period before the first unit measurement period begins (when the number of outs is less than 300), the identification display will flash "bL.", "b1." to "b3.", and the numerical display will light up with "--".

[0180] The procedure for the performance display monitor display update process (S355) will be described below. In the performance display monitor display update process (S355), as shown in FIG. 38, only if this performance display monitor display update process is being executed for the first time since power-on (S191: Yes), initial settings of various information related to the display of the performance display means 95 are made (S192). In this embodiment, the determination in S191 is made based on whether the value of the operation check timer is a value corresponding to 4800 ms, specifically, 1200. In this embodiment, the operation check timer is set to an initial value of 1201 in the initial setting process (S30 in FIG. 11, FIG. 25) when power is turned on, and is then decremented by 1 in the first timer management process (S132). As a result, the value of the operation check timer is 1200 at the time of the first performance display monitor display update process (S355) after power-on.

[0181] In S192, 0 is set in the blinking cycle timer, 15 in the on / off switching counter, a predetermined non-start value in the tally / division counter, and 4 in the display content pointer, and off data (0000H) is set in the identification display unit output buffer and the numeric display unit output buffer. Here, the blinking cycle timer is used to measure the blinking cycle, the on / off switching counter is used to switch between on and off during blinking, and the tally / division counter is used to specify the timing for calculating the real-time base value using the count value in the performance display monitor tallying process (S126). The display content pointer is used to specify the display content (type of base value) of the performance display means 95, and takes on values ​​from 1 to 4 corresponding to the real-time base value and the first to third cumulative base values.

[0182] In this embodiment, by initializing the predetermined information related to the display of the performance display means 95, i.e., the blinking cycle timer, the on / off switching counter, the tallying / division counter, and the display content pointer after power-on, the on / off state at the start of operation check does not differ each time the power is turned on, and the type of base value that is initially displayed after operation check does not differ, and the state at the start of display of the performance display means 95 after power-on can always be the same.

[0183] Furthermore, in this embodiment, among the information displayed by the performance display means 95, the operation confirmation timer is initialized during the power-on process before the interrupt process is started (S122), and other specified information is initialized during the interrupt process (S192), so the processing time when the power is turned on is short, enabling rapid start-up.

[0184] The blinking cycle timer, on / off switching counter, tally division counter, and display content pointer are stored in the external RAM. Therefore, if the performance display RAM initialization determination process (S125) determines that there is an external RAM abnormality, the operation check timer stored in the internal RAM is not cleared, but the blinking cycle timer, on / off switching counter, tally division counter, display content pointer, etc. stored in the external RAM are cleared.

[0185] Next, the blinking cycle timer is incremented (S193), and a determination is made as to whether the value of the blinking cycle timer after the increment is equal to or greater than a predetermined value (75, corresponding to 0.3 seconds in this example) (S194). If the value is less than the predetermined value (S194: No), the performance display monitor display update process ends here. If the value of the blinking cycle timer is equal to or greater than the predetermined value in S194 (S194: Yes), the blinking cycle timer is cleared (S195), and the process from S196 onwards is executed. In this way, the process from S195 onwards is executed every time the blinking cycle timer reaches the predetermined value of 75, i.e., every 0.3 seconds (=4 ms x 75) have elapsed.

[0186] In addition, in the above-mentioned S192, the identification display unit output buffer and the numeric display unit output buffer are set to off data (0000H) as their initial values, so that the performance display means 95 is in a completely off state for approximately 0.3 seconds until the first Yes judgment is made in S194.

[0187] Following S195, the on / off switching counter is incremented (S196), and it is determined whether the value of the on / off switching counter after the increment is an even number or an odd number (S197), and if it is an even number, the process proceeds to S201 in Fig. 39, and if it is an odd number, the process proceeds to S211 in Fig. 40. That is, every 0.3 seconds, the process from S201 onwards shown in Fig. 39 and the process from S211 onwards shown in Fig. 40 are performed alternately.

[0188] In this embodiment, the on / off switching counter is initialized to 15 in S192. Therefore, the first time S197 is executed after power-on, the on / off switching counter is an even number (16), and the process proceeds to S201 in FIG. 39 . Since the on / off switching counter is 16 at this point, which is greater than or equal to the predetermined value (15 in this example), the on / off switching counter is cleared to 0 in S201. Also, since the value of the operation confirmation timer at this point is 1126, not 0 (S202: No), the on data (FFFFH) is set in the identification display unit output buffer and the numeric display unit output buffer, respectively (S203, S204), and the performance display monitor display update process is terminated. This switches the performance display means 95 from the all-off state to the all-on state. The on data in S203 and S204 is written directly to each output buffer without referencing a data table or the like.

[0189] In the display update process 0.3 seconds later, the value of the on / off switching counter after incrementing in S196 is 1, so S197 determines that it is an odd number and proceeds to S211 in Figure 40. Because the value of the operation check timer at this time is 1051, not 0 (S211: No), off data (0000H) is set to the identification display unit output buffer and the numeric display unit output buffer, respectively (S212, S213). This switches the performance display means 95 from a fully on state to a fully off state. The off data in S212 and S213 is also written directly to each output buffer without referencing a data table or the like. Furthermore, because the value of the on / off switching counter at this time is 1, not the predetermined value (15 in this case) (S217: No), the performance display monitor display update process ends here.

[0190] The above processing is repeated until the on / off switching counter after increment in S196 reaches 14. Then, when the on / off switching counter after increment in S196 reaches 15, it is determined to be an odd number in S197 and the process proceeds to S211 in Fig. 40. However, since the value of the operation check timer at this point is 1, not 0, the off data (0000H) is set in the identification display unit output buffer and the numeric display unit output buffer, respectively, in S212 and S213. As a result, the performance display means 95 switches from the all-on state to the all-off state.

[0191] Since the on / off switching counter is 15 at this point, the determination in the following S217 is Yes, and the processes of S218 to S221 are executed. That is, the display content pointer is incremented (S218), and on the condition that the display content pointer after the increment is equal to or greater than a predetermined value (5 in this case) (S219: Yes), the display content pointer is set to 1 (S220). In this embodiment, since the display content pointer is set to an initial value of 4 in S192, the value of the display content pointer after the addition in S218 is 5, and it is determined in S219 that this is equal to or greater than the predetermined value, and the display content pointer is set to 1 in S220. Then, a starting value is set in the tallying and division counter (S221), and the performance display monitor display update process ends.

[0192] When the start value is set in the tally division counter, a division process is performed in the performance display monitor tally process (S126) to calculate a real-time base value using the count value at that time. When the real-time base value is calculated, a non-start value is set in the tally division counter.

[0193] In the display update process 0.3 seconds later, the on / off switching counter after increment in S196 becomes 16, so it is determined to be an even number in S197, and subsequently in S201 of Fig. 39, the on / off switching counter is cleared to 0. Then, since the operation check timer has already become 0 at this point (S202: Yes), the operation check is terminated and the processes of S205 to S208 are executed. Thus, in this embodiment, the operation check of switching the performance display means 95 between all off and all on every predetermined time (0.3 seconds) is performed for approximately 5.1 seconds (=0.3 seconds x 17).

[0194] In S205 to S208, first, the discriminable display unit display pattern data corresponding to the display content pointer is obtained from the discriminable display unit LED data table (S205), and the obtained discriminable display unit display pattern data is set in the discriminable display unit output buffer (S206). The discriminable display unit LED data table pre-stores display pattern data corresponding to the displays of "bL.", "b1.", "b2.", and "b3.", corresponding to the display content pointer values ​​of 1 to 4. Since the value of the display content pointer at this time is 1, the display pattern data corresponding to the display of "bL." is set in the discriminable display unit output buffer.

[0195] Furthermore, the digital display unit display pattern data corresponding to the content to be displayed on the digital display unit is obtained from the decimal value LED data table (S207), and the obtained digital display unit display pattern data is set in the digital display unit output buffer (S208). The content to be displayed on the digital display unit is determined based on the display content pointer and the interval pointer, for example, as shown in FIG. 41. Here, the interval pointer indicates the period related to the measurement of the base value, and as shown in FIG. 41, it takes on a value from 1 to 5 corresponding to five types of periods: the "pre-measurement period," the following "first unit measurement period," "second unit measurement period," "third unit measurement period," and "fourth unit measurement period and beyond." The decimal value LED data table also stores one byte of display pattern data corresponding to ten types of digits from "0" to "9" and "-."

[0196] At this point, the display content pointer is 1, and the interval pointer is likely to be 1 (pre-measurement period), so the display content of the numeric display unit will be "--" as shown in Figure 41. Therefore, "01000000B", which corresponds to the "-" in the tens place, and "01000000B", which corresponds to the "-" in the ones place, are obtained from the decimal value LED data table and set in the numeric display unit output buffer.

[0197] As a result of the above, the real-time base value display period (pre-measurement period) begins at the end of the operation check, and the display on the performance display means 95 is switched from the all-lights-off state to "bL.--".

[0198] In the display update process 0.3 seconds later, the value of the on / off switching counter after incrementing in S196 becomes 1, and is determined to be an odd number in S197. Then, in S211 of FIG. 40, the value of the operation check timer is determined to be 0 (S211: Yes), so in the following S214, it is determined whether the display mode of the identification display unit is on or flashing, and if the determination result is flashing (S215: Yes), the off data (0000H) is set in the identification display unit output buffer (S216). As a result, the identification display unit switches from "bL." to the off state. Note that the value of the numeric display unit output buffer is not updated, so the numeric display unit remains unchanged at "--".

[0199] The above process is repeated until the on / off switching counter after the increment in S196 reaches 15. When the on / off switching counter after the increment in S196 reaches 15, the determination in S217 of Fig. 40 becomes Yes, so that the processes in S218 to S221 change the display content pointer from 1 to 2 and set the starting value in the tallying division counter.

[0200] As a result, 0.3 seconds later, the real-time base value display period ends and a new first cumulative base value display period begins, the identification display section flashes "b1.", and the numeric display section lights up and displays "--".

[0201] Thereafter, based on the interval pointer and the display content pointer which changes periodically at a predetermined cycle, multiple types of base values ​​(here, four types: real-time base value and first to third cumulative base values) are displayed cyclically on the performance display means 95 every predetermined time (for example, 4.8 seconds).

[0202] If an abnormality occurs in the external RAM during the operation check (S125 in Figure 26), the external RAM is cleared, but the operation check timer is not cleared because it is stored in the internal RAM. Therefore, the operation check is not interrupted and continues at least until the value of the operation check timer reaches 0. However, in this case, the blink cycle timer, on / off switching counter, display content pointer, etc. stored in the external RAM are cleared, so the blink timing (the timing when the value of the blink cycle timer reaches the specified value (75)), etc. may change. Furthermore, clearing the display content pointer may change the initial display content after the operation check.

[0203] Returning to Figure 34, the explanation will continue. Following the performance display monitor display update process (S355) described above, the test firing signal management process (S356) is executed, the in-area stack pointer is restored (set) (S357), and the timer interrupt in-area out-of-area processing is terminated. In the test firing signal management process (S356), a gaming machine error status signal is output if a ball jam error, supply shortage error, counting error, disconnection error, or door open error occurs.

[0204] The explanation will continue by returning to the timer interrupt processing in Fig. 27. When the above-described timer interrupt area outside processing (S145) is completed, the saved register contents are restored (S146), the WDT is cleared (S147), and the timer interrupt processing is completed.

[0205] As explained above, in the pachinko machine of this embodiment, the in-area processing (in-area error determination processing (S135, FIG. 29), in-area random number circuit processing (S136, FIG. 30), in-area prize ball processing (S137, FIG. 31)) executes first type error processing related to the determination of an in-area error (first type error) and the transmission of an error command, and first processing related to non-errors (e.g., processing related to prize balls), and then transitions from the in-area processing to out-area processing (out-area processing within timer interrupt (S145, FIG. 34)), and the out-area processing executes second type error processing related to the determination of an out-area error (second type error) and the transmission of an error command, and second processing related to non-errors (performance display monitor display update processing, etc.), and then returns from the out-area processing to the in-area processing. In this way, in this embodiment, it is possible to more efficiently perform processing related to some errors by using an area (second storage area) separate from the used area (first storage area).

[0206] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments, and various modifications are possible without departing from the spirit of the present invention. For example, any one, all, or more (any combination) of the errors that are processed within the processing area in the embodiments may be configured to be processed outside the processing area. In this case, it is particularly desirable to configure the processing outside the processing area for any one, all, or more (any combination) of random number anomalies, RAM anomalies, abnormalities in the setting values ​​related to the jackpot probability, and backup anomalies. It is also desirable to configure the processing outside the processing area for any one, all, or more (any combination) of ball jam errors, supply shortage errors, counting errors, wire breakage errors, door open errors, etc.

[0207] In this manner, when at least some of the errors that are supposed to be processed within the area in the embodiment are configured to be processed outside the area (hereinafter referred to as "second out-of-area errors"), the processes from error detection and determination to sending of the error command may be performed outside the area, or only error detection and determination may be performed within the area, and sending of the error command may be performed outside the area. Alternatively, error detection may be performed within the area, and error determination and sending of the error command may be performed outside the area. This configuration makes it possible to further reduce the capacity of the in-area program. In addition, in this case, one or all of, or any combination of, the error detection, error determination, and sending of the error command may be performed by a common program for the second out-of-area errors and the errors that are supposed to be processed outside the area in the embodiment (hereinafter referred to as "first out-of-area errors"). This makes it possible to reduce capacity by sharing the program, and to distinguish between errors that may affect the outcome of the game and other errors.

[0208] When processing regarding abnormalities in the setting values ​​related to the probability of a jackpot is performed by an outside-area program, the setting value setting process (setting change process) and confirmation process (setting confirmation process) may also be configured to be performed by an outside-area program, or the setting value setting process (setting change process) and confirmation process (setting confirmation process) may be performed by an inside-area program, and the process may transition to an outside-area program when an abnormality in the setting value is determined.

[0209] When a game stop process is executed based on the result of an error determination by a program outside the area, it is desirable to execute the game stop process by a program within the area. In this way, it is desirable to execute processes (for example, game stop processes) whose execution results may affect the outcome of the game within the area.

[0210] In the embodiment, the out-of-area error information is cleared in the out-of-area error information clearing process (S27) before the main loop, but the out-of-area error information may also be cleared in the out-of-area processing in the main loop (S35) or in the out-of-area processing in the timer interrupt (S145). This eliminates the need to call the out-of-area program just to clear the out-of-area error information, making it possible to further reduce the program size.

[0211] For specific errors detected by the dispensing control board 90a (such as ball jam errors, out-of-supply errors, counting errors, door open errors, etc., but others are also acceptable), the program on the dispensing control board 90a may be configured to have an in-area program and an out-of-area program, with the out-of-area program performing the error detection process and transmitting the detection results to the main control board 82a. In this case, the error detection process may be performed by the out-of-area program and the transmission process of the detection results may be performed by the in-area program, or the error detection process may be performed by the in-area program and the transmission process of the detection results may be performed by the out-of-area program.

[0212] Furthermore, the present invention can be similarly implemented in various pinball gaming machines such as arrange ball machines and mahjong ball gaming machines, as well as gaming machines other than pinball gaming machines such as slot machines. [Explanation of symbols]

[0213] 82a Main control board 83a Performance control board

Claims

[Claim 1] The system has an internal program stored in a first storage area and an external program stored in a second storage area different from the first storage area. In gaming machines, Any one of a plurality of processes including a backup restoration process and a RAM clear process can be executed when the power is turned on; First predetermined determination information can be set in a predetermined RAM area based on the determination process by the out-of-area program, When the first predetermined determination information is set, the out-of-area program can execute transmission of a first command for making a specific notification under control of a predetermined control means, second predetermined determination information can be set in a predetermined RAM area based on the determination process by the program in the area; When the second predetermined determination information is set, the program in the area can transmit a second command different from the first command, When the backup recovery process is performed at the time of power-on, the specific notification is continued by not clearing the first predetermined determination information, while When the RAM clearing process is performed at power-on, the first predetermined determination information is cleared so that the specific notification is not executed. When the first predetermined determination information is set in the predetermined RAM area based on the determination process by the program outside the area, the program inside the area is configured to be able to execute a game stop process. A gaming machine characterized by:

Images