gaming machines

Abstract

To provide a game machine which can suppress, as much as possible, an adverse effect on a game progress caused by an occurrence of a trouble related to a liquid crystal control.SOLUTION: A game machine includes a transmission path which transmits a signal between a substrate having a plurality of wiring layers, and liquid crystal display means. In the substrate, there are arranged a chip integrated with a VDP circuit, and a connector to which the transmission path is connected. The VDP circuit is constituted to output, in parallel, a first signal corresponding to one of odd number / even number pixels adjacent to each other in the liquid crystal display means and a second signal corresponding to the other. The transmission path includes a first transmission path for transmitting the first signal and a second transmission path for transmitting the second signal. The substrate is provided with a first wiring line connected from the VDP circuit via the connector to the first transmission path, and a second wiring line connected to the second transmission path. The first wiring line is arranged such that a wiring rate to one wiring layer of plural wiring layers is highest, and the second wiring line is arranged such that a wiring rate to another wiring layer of plural wiring layers is highest.SELECTED DRAWING: Figure 36

Description

[Technical Field]

[0001] The present invention relates to gaming machines such as pachinko machines and slot machines. [Background technology]

[0002] Most gaming machines, such as pachinko machines, are equipped with a liquid crystal display (LCD) to display images and other effects. This LCD display is implemented by a VDP (Video Display Programmer) mounted on a control board. Display control based on image data signals and other control signals output from the processor circuit (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-093632 Summary of the Invention [Problem to be solved by the invention]

[0004] Book The invention A signal transmission path connecting the display control means and the image display means such as the liquid crystal display means is preferably configured. The object is to provide a gaming machine. [Means for solving the problem]

[0005] The present invention relates to a gaming machine comprising an image display means and a display control means for outputting image data to the image display means, the gaming machine comprising: a first substrate on which the display control means is mounted and on which a first signal line for transmitting the image data to the image display means is formed; a second substrate on which a second signal line for transmitting the image data is formed and on which an output connector for outputting the image data to the image display means is mounted; and a connector for connecting the first signal line of the first substrate and the second signal line of the second substrate, the second signal line being formed by a plurality of wiring paths, each of which is connected to a protection circuit and / or a test point, and In order to align the wiring lengths of the multiple wiring paths, An adjustment section is provided. [Effects of the Invention]

[0006] According to the present invention, A signal transmission path connecting the display control means and the image display means such as the liquid crystal display means may be configured more preferably. It becomes possible to do this. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is an overall front view of a pachinko machine according to a first embodiment of the present invention. [Figure 2] FIG. [Figure 3] FIG. 2 is an exploded perspective view of the glass door of the pachinko machine. [Figure 4] This is a plan view of the main parts of the pachinko machine, showing the operation and presentation means, cross operation button, volume adjustment button, light intensity adjustment button, etc. [Figure 5] FIG. 2 is a front view of the game board of the pachinko machine. [Figure 6] FIG. 2 is a front view of the game information display means of the pachinko machine. [Figure 7] FIG. [Figure 8] FIG. 2 is an exploded perspective view of the performance board case and performance control unit of the pachinko machine. [Figure 9] This is a plan cross-sectional view of the performance board case and performance control unit of the same pachinko machine. [Figure 10]FIG. 2 is a block diagram showing the overall circuit configuration of the pachinko machine. [Figure 11] 10 is an explanatory diagram of the specifications of the liquid crystal display means in the pachinko machine. FIG. [Figure 12] 10 is an explanatory diagram of the specifications of the liquid crystal control signal in the pachinko machine. FIG. [Figure 13] 2 is a block diagram showing the configuration of a liquid crystal display means in the pachinko machine. FIG. [Figure 14] FIG. 2 is a block diagram showing the overall configuration of the composite chip in the pachinko machine. [Figure 15] FIG. 2 is a block diagram showing the main configuration of the composite chip in the pachinko machine. [Figure 16] 10 is an explanatory diagram of the index space, index table, virtual drawing space, and drawing area in the pachinko machine. FIG. [Figure 17] FIG. 10 is a block diagram showing the internal configuration of the data transfer circuit in the pachinko machine, together with the related circuit configuration. [Figure 18] FIG. 2 is a block diagram showing the internal configuration of the display circuit in the pachinko machine together with the related circuit configuration. [Figure 19] 10 is an explanatory diagram of a data valid signal ENAB in the pachinko machine. FIG. [Figure 20] FIG. 2 is a diagram showing the first wiring layer in the liquid crystal control board of the pachinko machine. [Figure 21] FIG. 2 is a diagram showing a second wiring layer in the liquid crystal control board. [Figure 22] FIG. 2 is a diagram showing a third wiring layer in the liquid crystal control board. [Figure 23] FIG. 10 is a diagram showing a fourth wiring layer in the liquid crystal control board. [Figure 24] FIG. 10 is a diagram showing a fifth wiring layer in the liquid crystal control board. [Figure 25] FIG. 10 is a diagram showing a sixth wiring layer in the liquid crystal control board. [Figure 26] 10 is a diagram showing terminal information of a composite chip arranged on the liquid crystal control board. FIG. [Figure 27]10 is a diagram showing terminal information of a control ROM arranged on the liquid crystal control board. FIG. [Figure 28] FIG. 1 is a diagram showing wiring paths P1 to P71 extracted from a first wiring layer of the liquid crystal control board. [Figure 29] FIG. 10 is a diagram showing wiring paths P1 to P71 extracted from the second wiring layer of the liquid crystal control board. [Figure 30] FIG. 10 is a diagram showing wiring paths P1 to P71 extracted from the third wiring layer of the liquid crystal control board. [Figure 31] FIG. 10 is a diagram showing wiring paths P1 to P71 extracted from a fourth wiring layer of the liquid crystal control board. [Figure 32] FIG. 10 is a diagram showing wiring paths P1 to P71 extracted from a fifth wiring layer of the liquid crystal control board. [Figure 33] FIG. 10 is a diagram showing wiring paths P1 to P71 extracted from a sixth wiring layer of the liquid crystal control board. [Figure 34] FIG. 29 is an enlarged view of an area E1a in FIG. 28. [Figure 35] FIG. 29 is an enlarged view of a region E1b in FIG. 28. [Figure 36] FIG. 29 is an enlarged view of an area E1c in FIG. 28. [Figure 37] FIG. 31 is an enlarged view of an area E3a in FIG. 30. [Figure 38] FIG. 31 is an enlarged view of an area E3b in FIG. 30. [Figure 39] FIG. 31 is an enlarged view of an area E3c in FIG. 30. [Figure 40] FIG. 32 is an enlarged view of an area E4 in FIG. 31. [Figure 41] FIG. 34 is an enlarged view of an area E6a in FIG. 33. [Figure 42] FIG. 34 is an enlarged view of an area E6b in FIG. 33. [Figure 43] FIG. 34 is an enlarged view of an area E6c in FIG. [Figure 44] FIG. 34 is an enlarged view of an area E6d in FIG. [Figure 45] 1 is a diagram schematically showing the wiring paths of wiring paths P1 to P8 in a liquid crystal control board of a pachinko machine according to a first embodiment of the present invention. FIG. [Figure 46]FIG. 10 is a diagram schematically showing wiring paths P9 to P17 on the liquid crystal control board. [Figure 47] FIG. 10 is a diagram schematically showing wiring paths P18 to P26 on the liquid crystal control board. [Figure 48] FIG. 10 is a diagram schematically showing wiring paths P27 to P34 on the liquid crystal control board. [Figure 49] FIG. 10 is a diagram schematically showing wiring paths P35 to P42 on the liquid crystal control board. [Figure 50] FIG. 10 is a diagram schematically showing wiring paths P43 to P47 on the liquid crystal control board. [Figure 51] FIG. 10 is a diagram schematically showing wiring paths P48 to P51 on the liquid crystal control board. [Figure 52] FIG. 10 is a diagram schematically showing wiring paths P52 to P61 on the liquid crystal control board. [Figure 53] FIG. 10 is a diagram schematically showing wiring paths P62 to P71 on the liquid crystal control board. [Figure 54] FIG. 2 is a circuit diagram of a decoding circuit in the liquid crystal control board. [Figure 55] FIG. 2 is a circuit diagram of a reset circuit in the liquid crystal control board. [Figure 56] 10 is a diagram showing a silk printing pattern on the first wiring layer side of the liquid crystal control board. FIG. [Figure 57] FIG. 2 is a diagram showing the first wiring layer in the liquid crystal interface board of the pachinko machine. [Figure 58] FIG. 2 is a diagram showing the second and fifth wiring layers in the liquid crystal interface substrate. [Figure 59] FIG. 2 is a diagram showing a third wiring layer in the liquid crystal interface substrate. [Figure 60] FIG. 10 is a diagram showing a fourth wiring layer in the liquid crystal interface substrate. [Figure 61] FIG. 10 is a diagram showing a sixth wiring layer in the liquid crystal interface substrate. [Figure 62] FIG. 1 is a diagram showing only wiring paths P101 to P124 extracted from the first wiring layer of the liquid crystal interface board. [Figure 63]FIG. 10 is a diagram showing wiring paths P101 to P124 extracted from the second and fifth wiring layers of the liquid crystal interface board. [Figure 64] FIG. 10 is a diagram showing wiring paths P101 to P124 extracted from the third wiring layer of the liquid crystal interface board. [Figure 65] FIG. 10 is a diagram showing wiring paths P101 to P124 extracted from the fourth wiring layer of the liquid crystal interface board. [Figure 66] FIG. 10 is a diagram showing wiring paths P101 to P124 extracted from a sixth wiring layer of the liquid crystal interface board. [Figure 67] FIG. 63 is an enlarged view of an area E11a in FIG. 62. [Figure 68] FIG. 63 is an enlarged view of a region E11b in FIG. 62. [Figure 69] FIG. 63 is an enlarged view of a region E11c in FIG. 62. [Figure 70] FIG. 67 is an enlarged view of an area E16a in FIG. 66. [Figure 71] FIG. 67 is an enlarged view of region E16b in FIG. 66. [Figure 72] FIG. 67 is an enlarged view of area E16c in FIG. 66. [Figure 73] FIG. 2 is a diagram schematically showing wiring paths P101 to P110 in a liquid crystal interface board of the pachinko machine according to the first embodiment of the present invention. [Figure 74] FIG. 10 is a diagram schematically showing wiring paths P111 to P120 in the liquid crystal interface board. [Figure 75] FIG. 10 is a diagram schematically showing wiring paths P121 to P124 in the liquid crystal interface board. [Figure 76] FIG. 10 is a circuit diagram of the liquid crystal interface board in the vicinity of the liquid crystal IF third connector. [Figure 77] FIG. 10 is a circuit diagram of the liquid crystal interface board in the vicinity of the second liquid crystal IF connector. [Figure 78] This is a circuit diagram of the main parts of the liquid crystal interface board of the pachinko machine. [Figure 79] FIG. 2 is a block diagram showing the schematic configuration of the performance control unit of the pachinko machine. [Figure 80] A diagram showing the types of pending notification images and the probability of winning in the same pachinko machine. [Figure 81] This is an explanatory diagram of the dynamic display of the hold notification image in the same pachinko machine at the start, during, and end of display. [Figure 82] This is an explanatory diagram showing the display state of the hold notification image when either the odd image data or the even image data is missing in the same pachinko machine. [Figure 83] The diagrams show the distribution of color information on a pixel-by-pixel basis when either odd or even image data is missing in the same pachinko machine. (a) shows the case where multiple types of color information are distributed vertically, and (b) shows the case where the same information is distributed horizontally. [Figure 84] An explanatory diagram of the dynamic display when the hold notification image shifts in the same pachinko machine. [Figure 85] FIG. 2 is a diagram showing the color distribution of decorative patterns in the pachinko machine. [Figure 86] 10A and 10B are diagrams showing dynamic display of decorative symbols in the pachinko machine. [Figure 87] FIG. 2 is a diagram showing an operation guide image for the pachinko machine. [Figure 88] FIG. 10 is a diagram showing an example of a rainbow background image used in the full-rainbow image presentation of the pachinko machine. [Figure 89] FIG. 10 is a diagram showing the change over time of the rainbow background image of the pachinko machine. [Figure 90] This is a diagram showing a specific example of the win / loss branch button presentation NB1 of the same pachinko machine. [Figure 91] FIG. 10 is a diagram showing the time change of the band effect image in the pachinko machine. [Figure 92] 10A and 10B are diagrams showing types of operation guide images in the pachinko machine. [Figure 93] This figure shows the time change (moving by two dots per frame) near the boundary of the operation valid period notification image in the same pachinko machine, where (a) shows the case where no image data is missing, and (b) shows the case where either the odd image data or the even image data is missing. [Figure 94] This figure shows the change over time when the boundary of the operation validity period notification image moves by one dot per frame, where (a) shows the case where no image data is missing, and (b) shows the case where either the odd image data or the even image data is missing. [Figure 95] This is a diagram showing a case where color information changes in the vertical direction in the partial rainbow image presentation of the same pachinko machine. [Figure 96] This is a diagram showing a case where color information changes left and right in the partial rainbow image presentation of the same pachinko machine. [Figure 97] A figure showing a setting suggestion effect selection table for the same pachinko machine. [Figure 98] FIG. 10 is a diagram showing an example of a screen display during the setting suggestion performance of the pachinko machine. [Figure 99] This is an explanatory diagram showing the color distribution on a pixel-by-pixel basis when the rainbow effect, which changes left and right depending on the position and time of the pachinko machine, moves by a predetermined number of dots per frame, under normal conditions and when even / odd pixels are missing. [Figure 100] FIG. 10 is a diagram showing the time change of a band effect image in a pachinko machine according to a second embodiment of the present invention. [Figure 101] 10A is a diagram showing an example in which the star-shaped figure displayed during the reach effect is a rainbow image, and FIG. 10B is a diagram showing an example in which the reach title characters are a rainbow image. BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Figures 1 to 99 illustrate a first embodiment in which the present invention is adopted in a pachinko machine. In Figures 1 and 2, a gaming machine main body 1 includes an outer frame 2 and a front frame 3 arranged in front of the outer frame 2. The front frame 3 is pivotally attached to the outer frame 2 via a first hinge 4 in the up-down direction arranged at one end in the left-right direction, for example, at the left end, so as to be openable, closable, and detachable. The front frame 3 can be locked in a closed state relative to the outer frame 2 by a locking means 5 provided on the opposite side in the left-right direction from the first hinge 4, for example, at the right end.

[0009] The front frame 3 includes an inner frame 6 and a front door 7 arranged in front of the inner frame 6. The front door 7 is pivotally attached to the inner frame 6 via a second hinge 8 in the vertical direction arranged at one end in the left-right direction, for example, at the left end, so as to be openable, closable, and detachable, and can be locked in the closed state relative to the inner frame 6 by a locking means 5.

[0010] As shown in Figure 2, the outer frame 2 is rectangular and made up of a pair of left and right vertical frame members 2a, 2b and a pair of upper and lower horizontal frame members 2c, 2d. A front cover member 9, made of, for example, synthetic resin, is attached to the lower front side of the outer frame 2, connecting the lower front sides of the left and right vertical frame members 2a, 2b along the front edge of the lower horizontal frame member 2d. The front cover member 9 protrudes forward beyond the left and right vertical frame members 2a, 2b, with the inner frame 6 disposed above it. Furthermore, an upper outer frame hinge fitting 11, which constitutes the first hinge 4, is disposed on the upper left side of the outer frame 2, for example, and a lower outer frame hinge fitting 12 is disposed above the front cover member 9 on the lower left side.

[0011] The inner frame 6 is made of synthetic resin and, for example, integrally comprises a rectangular frame portion 13 that is above the front cover member 9 and can substantially abut against the front edge of the outer frame 2, a game board mounting portion 14 provided on the upper side within this frame portion 13, and a lower mounting portion 15 provided on the lower side within the frame portion 13. A game board 16 is detachably mounted, for example, from the front side, to the game board mounting portion 14, and a launching means 17, a lower speaker 18, etc. are disposed on the front side of the lower mounting portion 15. In addition, on the inner frame 6, a main body frame upper hinge metal fitting 19 that constitutes the first hinge 4 and a main body frame upper hinge metal fitting 20 that constitutes the second hinge 8 are disposed, for example, on the upper left side, and a main body frame lower hinge metal fitting 21 that constitutes the first and second hinges 4, 8 are disposed, for example, on the lower left side.

[0012] The front door 7 is provided with a door base 22 made of resin and formed in a rectangular shape corresponding to the front side of the inner frame 6. In this door base 22, a window hole 24a of a glass window 24 is formed corresponding to the front side of a play area 23 formed on the game board 16, and various presentation means such as a plurality of (four in this case) upper speakers 25, a frame first movable presentation means 26, a frame second movable presentation means 27, and a blower means 28 are arranged around the window hole 24a.

[0013] A side unit 30 is attached to the upper front side of the door base 22 on at least a portion of the outer periphery of the window hole 24a, for example, a portion that is inverted L-shaped when viewed from the front, corresponding to the upper right side of the window hole 24a (Figs. 1 and 3). As shown in Figs. 2 and 3, the side unit 30 can be easily attached and detached by operating fixing screws 30a, fixing levers 30b, etc. on the back side of the front frame 3 with the front frame 3 open, without using any special tools. As shown in Fig. 1, the front side of the side unit 30 is equipped with effect means such as a frame first movable effect means 26 having a frame first movable body 26a, a frame second movable effect means 27 having a frame second movable body 27a, and a ventilation means 28.

[0014] The frame first movable body 26a of the frame first movable effect means 26 is formed in any three-dimensional shape (here, a butterfly motif) and can slide approximately back and forth when driven by a drive means (not shown). The frame second movable body 27a of the frame second movable effect means 27 can slide approximately back and forth when driven by a drive means (not shown) and can vibrate when vibrated by a vibration means (not shown) disposed within the grip portion 27b. The player can also press the grip portion 27b. The air blowing means 28 can blow air toward the player's hand when the player grips the grip portion 27b. A frame lamp 304 consisting of multiple LEDs 301a-301d is arranged on the front side of the front door 7, including the side unit 30, so as to approximately surround the glass window (display window) 24.

[0015] At the lower front side of the door base 22 are arranged an upper tray 33 that stores game balls dispensed from a dispensing means 32 located at the rear of the inner frame 6 and supplies them to the launching means 17, a lower tray 34 that stores surplus balls when the upper tray 33 is full, a launching handle 35 that is operated to activate the launching means 17, and more. Furthermore, a lower decorative cover 36 is attached that substantially covers the upper tray 33, lower tray 34, etc. from the front. The lower decorative cover 36 is formed, for example, in a forward-facing bulge shape, and various operating means are provided on its upper side, such as an operating means 37, a cross operating button 38, a volume adjustment button 39, and a light intensity adjustment button 40 (Figure 4). The operating means 37 is used for preview effects during symbol fluctuations and other effects, and is equipped with an up-and-down moving effect button 41 that can be pressed by the player.

[0016] 2, a glass unit 50 that substantially covers the window hole 24a from the rear side is detachably attached to the back side of the door base 22, and a vertical hinge end reinforcing plate 51a that is arranged along the edge of the first and second hinges 4, 8, a vertical opening / closing end reinforcing plate 51b that is arranged along the edge of the opening / closing end, and a horizontal lower reinforcing plate 51c that is arranged below the window hole 24a are detachably fixed by screws, etc. Also, on the door base 22, a glass door upper hinge fitting 52a that constitutes the second hinge 8 is arranged, for example, on the upper left, and a glass door lower hinge fitting 52b is arranged, for example, on the lower left.

[0017] Also, for example, a ball feeding unit 53a, a lower tray guide unit 53b, etc. are attached to the back side of the lower reinforcing sheet metal 51c. The ball feeding unit 53a is for supplying the game balls in the upper tray 33 to the launching means 17, and is arranged corresponding to the front side of the launching means 17 arranged on the inner frame 6 side, and by operating the ball feeding solenoid 53c in synchronization with the launching operation of the launching means 17, the game balls in the upper tray 33 are supplied one by one onto the launching rail 17a of the launching means 17.

[0018] The launching means 17 comprises a launching rail 17a arranged at an angle that slopes upward to the left when viewed from the front, a launching ball stopper 17b that supports the game balls supplied onto the launching rail 17a by the ball feeding unit 53a at the launch waiting position, a striking hammer 17c that is arranged corresponding to the launch waiting position on the launching rail 17a and can swing around a drive axis in the forward and backward directions, and a launching drive means 17d such as a rotary solenoid that drives the striking hammer 17c to swing, so that when the launch handle 35 is rotated, the launching drive means 17d continuously drives the striking hammer 17c in the impact direction (clockwise) with a launch strength that corresponds to the amount of rotation.

[0019] The lower tray guide unit 53b is intended to guide surplus balls when the upper tray 33 is full, and foul balls that are launched by the launching means 17 but return without reaching the playing area 23, to the lower tray 34, and is arranged, for example, adjacent to the ball feeding unit 53a on the first and second hinges 4 and 8 sides thereof.

[0020] As shown in Figure 5, the game board 16 has a base plate 55 made of plywood, polycarbonate board, etc., and a guide rail 56 that guides the game balls launched from the launching means 17 is arranged in a circular shape on the front side of the base plate 55, and in the game area 23 inside the guide rail 56, unit parts such as a central display frame unit 57, a start winning unit 58, a normal winning unit 59, etc., as well as a large number of game nails (not shown), are arranged, and a game information display means 60 is arranged, for example, on the outside lower part of the game area 23.

[0021] As shown in Figure 6, the game information display means 60 has four LED groups consisting of eight LEDs 70, and a total of 32 LEDs 70 are assigned in predetermined numbers to a normal pattern display means 61, a normal reserved number display means 62, a first special pattern display means 63, a second special pattern display means 64, a first special reserved number display means 65, a second special reserved number display means 66, a fluctuation reduction notification means 67, a right hit notification means 68 and a round number notification means 69. That is, the eight LEDs 70 belonging to the first and second LED groups 60a and 60b constitute the first and second special pattern display means 63 and 64, respectively, the eight LEDs 70 belonging to the third LED group 60c are divided into pairs and constitute the first special reserve number display means 65, the second special reserve number display means 66, the normal reserve number display means 62, and the fluctuation reduction notification means 67, and of the eight LEDs 70 belonging to the fourth LED group 60d, two constitute the normal pattern display means 61, the other two constitute the right hit notification means 68, and the remaining four constitute the number of rounds notification means 69.

[0022] On the plurality of unit parts 57 to 59 of the game board 16, there are provided a normal symbol start means 71, a first special symbol start means 72, a second special symbol start means 73, a big prize means 74, a plurality of normal prize means 75, etc. Also, on the rear side of the base plate 55, in addition to a liquid crystal display means (image display means) 76, there are also arranged a board movable performance means 77 equipped with a movable accessory 77a that can move in front of the liquid crystal display means 76, etc.

[0023] The movable prop 77a is formed in the shape of a horizontally long rectangular box, and both left and right ends thereof are supported so as to be movable up and down on the outside of the side edges of the liquid crystal display means 76, and by driving a driving means not shown, it can be moved up and down between an origin position (see FIG. 5) on the upper side of the liquid crystal display means 76 and an operating position on the front side of the liquid crystal display means 76. In addition, a movable prop lamp 314 consisting of a plurality of LEDs 311 is arranged on the front side of the movable prop 77a.

[0024] The central display frame unit 57 constitutes a display frame for the liquid crystal display means 76 and the movable accessory 77a, and has an opening window 80 formed in the approximate center corresponding to the rear liquid crystal display means 76, and is detachably attached from the front side to a mounting hole (not shown) that penetrates in the front-rear direction and is formed in the base plate 55. As shown in Fig. 5, this central display frame unit 57 comprises a front mounting plate 81 that is arranged along the front surface of the base plate 55 outside the mounting hole and through which game balls can pass, a decorative frame 82 that is arranged in a roughly gate-like shape in front view from both the left and right sides in front of the liquid crystal display means 76 to the upper side and that protrudes forward on the inner periphery of the front mounting plate 81, and a stage 83 that is arranged between the left and right lower end portions of the decorative frame 82. The game balls that are launched by the launching means 17 and enter the upper side of the game area 23 are divided to the left and right at the top of the decorative frame 82 and flow down either the left flow path 84a on the left side of the central display frame unit 57 or the right flow path 84b on the right side.

[0025] A warp inlet 85 through which game balls can flow is provided on at least one side of the left downflow path 84a side or the right downflow path 84b side, for example, on the left downflow path 84a side, of the central display frame unit 57. A game ball that flows into the warp inlet 85 while flowing down the left downflow path 84a rolls freely in the left-right direction on the stage 83, and then falls to the front from either a central drop section 86 provided corresponding to the left-right center of the game area 23 or from another section.

[0026] Furthermore, on the front side of the central display frame unit 57, a board lamp 324 consisting of a number of LEDs 321a to 321c is arranged corresponding to at least a part of the outer periphery of the liquid crystal display means 76, for example, both the left and right sides and the upper side. Note that a part of the board lamp 324 may also be arranged on the start winning unit 58, the normal winning unit 59, etc.

[0027] 5, the starting winning unit 58 is arranged along the guide rail 56 below the central display frame unit 57, and is detachably attached to the base plate 55 from the front side. The regular winning unit 59 is arranged along the guide rail 56 below the central display frame unit 57 to the left of the starting winning unit 58, and is detachably attached to the base plate 55 from the front side.

[0028] The normal symbol starting means 71 is for starting the variable display of normal symbols by the normal symbol display means 61, and is composed of a passage gate or the like through which gaming balls can pass, and is equipped with a gaming ball detection switch (not shown) that detects the passage of gaming balls. This normal symbol starting means 71 is provided, for example, on the front side of the front mounting plate 81 on the right part of the central display frame unit 57, as shown in Figure 5, and gaming balls flowing down the right flow-down path 84b can pass through it.

[0029] The normal pattern display means 61 is for displaying a variable normal pattern, and is composed of a predetermined number (two in this case) of LEDs 70 in the game information display means 60 as shown in Fig. 6. When the normal pattern start means 71 detects a gaming ball, the two LEDs 70 constituting the normal pattern light up in a normal variation light-emitting pattern, and then if the win determination random number value included in the normal random number information acquired when the normal pattern start means 71 detects the gaming ball matches a predetermined win determination value, the variation stops in a win mode, and otherwise in a loss mode. The two LEDs 70 constituting the normal pattern can display one or more win modes and one or more loss modes by combining their light-emitting modes (for example, on / off), and the normal variation light-emitting pattern is configured to switch between, for example, multiple specific types (two types in this case) of light-emitting modes every predetermined time (for example, 128 ms).

[0030] Furthermore, when the normal symbol starting means 71 detects a gaming ball during a normal reservation period, which includes the normal symbol display means 61's symbol variation and the normal profit state, the normal random number information acquired thereby is reserved and stored up to a predetermined upper limit of reserved numbers, for example, four, and each time the normal reservation period ends, one is consumed at a time, causing the normal symbol to vary. The number of stored normal random number information (normal reservation number) is notified to the player by the normal reservation number display means 62, etc. As shown in Figure 6, the normal reservation number display means 62 is composed of a predetermined number (here, two) LEDs 70 in the game information display means 60, and five types of normal reservation numbers (0 to 4) can be displayed by combining the light-emitting modes (for example, on / blinking / off) of the two LEDs 70.

[0031] The first special symbol starting means 72 is used to start the symbol variation by the first special symbol display means 63. It is configured as a non-opening / closing winning means without an opening / closing means, and is equipped with a game ball detection switch (not shown) for detecting a winning game ball. As shown in FIG. 5, the first special symbol starting means 72 is provided, for example, in the starting winning unit 58, and is positioned below the central drop section 86 of the stage 83 with an upward opening. Because there is a winning route from the warp entrance 85 on the left flow path 84a through the stage 83, a game ball flowing down the left flow path 84a has a higher chance of winning than a game ball flowing down the right flow path 84b. When a game ball enters the first special symbol starting means 72, a predetermined number of game balls are paid out as prize balls for each winning.

[0032] The second special pattern starting means 73 is used to start the pattern change by the second special pattern display means 64, and is composed of an opening and closing type winning means that can be changed between an open state in which the game ball can win a prize and a closed state in which it is not possible to win a prize (or it is more difficult to win a prize than in the open state) by operating the opening and closing section 88, and is equipped with a game ball detection switch (not shown) that detects the winning game ball, and an opening and closing drive means such as an electromagnetic solenoid that opens and closes the opening and closing section 88, so that when the stopped pattern after the change of the normal pattern display means 61 becomes a winning pattern and a normal profit state occurs, the opening and closing section 88 changes from a closed state to an open state for a predetermined time.

[0033] 5, the second special symbol starting means 73 is disposed on the front mounting plate 81 at the right side of the central display frame unit 57 and downstream of the normal symbol starting means 71, so that gaming balls flowing down the right flow path 84b can win. The opening / closing section 88 can swing around a left-right rotation axis provided on the lower side, for example. In the closed state, it is substantially flush with the front mounting plate 81, allowing gaming balls to pass through the front side, and in the open state, it is inclined downward from the rear on the front side of the front mounting plate 81, allowing gaming balls to win backward. When a gaming ball wins the second special symbol starting means 73, a predetermined number of gaming balls are paid out as prize balls per win.

[0034] The first special symbol display means (symbol display means) 63 is composed of a predetermined number (eight in this example) of LEDs 70 in the game information display means 60, as shown in Figure 6. When the first special symbol start means 72 detects a game ball, the eight LEDs 70 constituting the first special symbol light up in a special variation light-emitting pattern. When the first special symbol start means 72 detects a game ball (when the symbol start condition is met), the first special random number information acquired contains a jackpot determination random number value. If the jackpot determination random number value included in the first special random number information matches a predetermined jackpot determination value (when a jackpot is determined by the random number lottery), the first special symbol display means stops fluctuations in a jackpot mode. If the jackpot determination value matches a predetermined minor jackpot determination value (when a minor jackpot is determined by the random number lottery), the first special symbol display means stops fluctuations in a minor jackpot mode. Otherwise, the first special symbol display means 63 stops fluctuations in a non-winning mode. When the stopped symbol after fluctuation is determined by the first special symbol display means 63, a jackpot game is executed. When the stopped symbol is determined to be a minor jackpot, a minor jackpot game is executed (profit state generating means).

[0035] The second special symbol display means (symbol display means) 64 is composed of a predetermined number (eight in this example) of LEDs 70 in the game information display means 60, as shown in Figure 6. When the second special symbol start means 73 detects a game ball, the eight LEDs 70 constituting the second special symbol light up in a special variation light-emitting pattern. When the second special symbol start means 73 detects a game ball (when the symbol start condition is met), the second special random number information acquired contains a jackpot determination random number value. If the jackpot determination random number value included in the second special random number information matches a predetermined jackpot determination value (when a jackpot is determined by the random number lottery), the second special symbol display means stops the variation in a jackpot mode. If the jackpot determination value matches a predetermined minor jackpot determination value (when a minor jackpot is determined by the random number lottery), the variation stops in a minor jackpot mode. Otherwise, the variation stops in a non-winning mode. When the stopped symbol after the variation of the second special symbol display means 64 becomes a jackpot mode, a jackpot game is executed. When the stopped symbol becomes a minor jackpot mode, a minor jackpot game is executed (profit state generating means).

[0036] The first and second special pattern display means 63, 64 can display one or more big win patterns, one or more small win patterns, and one or more miss patterns by combining the light emission patterns (e.g., on / off) of each of the eight LEDs 70, and the light emission pattern during the special variation is configured to switch between specific multiple types (here, two types) of light emission patterns every predetermined time (e.g., 128 ms).

[0037] Furthermore, when the first and second special symbol start means 72, 73 detect a gaming ball during a special reservation period, including during the symbol change of the first special symbol display means 63, the symbol change of the second special symbol display means 64, and during a jackpot game, the first and second special random number information acquired thereby is reserved and stored in the reservation storage means, each with a predetermined upper limit of reserved numbers, for example, up to four each. If, at the end of the special reservation period, there is one or more reserved memories on the second special symbol side, one reserved memory of the second special symbol is consumed to change the second special symbol; if there is only one or more reserved memories on the first special symbol side, one reserved memory of the first special symbol is consumed to change the first special symbol. Thus, in this embodiment, both the first and second special symbols are never changing, and when there are reserved memories on both the first and second special symbol sides, the second special symbol is given priority.

[0038] In this embodiment, the player hits the ball with his left hand, aiming at the first special symbol starting means 72 during the normal game state other than the special game state described below, and hits the ball with his right hand, aiming at the normal symbol starting means 71 and the second special symbol starting means 73 during the special game state, so that the first special symbol mainly fluctuates during the normal game state, and the second special symbol mainly fluctuates during the special game state.

[0039] The number of first and second special random number information pieces (first and second special reservation numbers) reserved and stored in the reservation storage means is notified to the player by the first and second special reservation number display means 65, 66, the liquid crystal display means 76, etc. Here, the first and second special reservation number display means 65, 66 are composed of a predetermined number (here, two each) of LEDs 70 in the game information display means 60 as shown in Fig. 6, and five types of first and second special reservation numbers (0 to 4) can be displayed by combining their light emission modes (for example, on / blinking / off).

[0040] In addition, there are two types of probability (jackpot probability) of jackpot determination (random number lottery) performed based on game ball detection by the first and second special symbol start means 72, 73: low probability and high probability. The probability is set to high during the probability variable state of the special game state described below, and low probability otherwise. In this embodiment, the setting value can be set to one of multiple levels (here, 6 levels), and the jackpot probability (low probability or high probability) changes depending on the setting value (settings 1 to 6). For example, the jackpot probability increases as the setting value increases.

[0041] Also, if the jackpot determination result is a miss, one or more types of misses are selected, if the jackpot determination result is a small hit, one or more types of small hits are selected, and if the jackpot determination result is a jackpot, one or more types of jackpots (for example, two types: a probability variable jackpot and a non-probability variable jackpot) are selected. Here, a probability variable jackpot is a jackpot that will generate a probability variable state (first special game state) as a special game state after the jackpot game ends, and a non-probability variable jackpot is a jackpot that will generate a time-saving state (second special game state) as a special game state after the jackpot game ends, and these allocations are made based on the jackpot pattern random number value, etc.

[0042] During the time-saving state, for example, the fluctuation time of the first and second special symbol display means 63, 64 for the first and second special symbols is switched to a shortened fluctuation time, which is shorter than the normal fluctuation time. For the normal symbols, the win probability is switched from a normal probability to a high probability, the fluctuation time is switched from a normal fluctuation time to a shortened fluctuation time, and the opening / closing pattern of the second special symbol activation means 73 in the normal win state is switched from a normal opening / closing pattern (e.g., 0.2 seconds x 1 opening) to a special opening / closing pattern (e.g., 2 seconds x 3 openings). The time-saving state begins when a jackpot game ends and ends, for example, when the first and second special symbols have changed a predetermined number of times (e.g., 50 times) or when the next jackpot game occurs. During the probability-changing state, in addition to the same switching as in the time-saving state, the jackpot probability is switched from a low probability to a high probability. The probability-changing state begins when a jackpot game ends and ends, for example, when the next jackpot game occurs.

[0043] The large prize winning means 74 is an opening / closing type winning means equipped with an opening / closing plate 89 that can be switched between an open state in which game balls can win and a closed state in which game balls cannot win, and is provided, for example, in the central display frame unit 57 as shown in Figure 5, and is equipped with a game ball detection switch (not shown) that detects winning game balls and an opening / closing drive means such as an electromagnetic solenoid that opens and closes the opening / closing plate 89.By being positioned downstream of the second special pattern starting means 73 and upstream of the first special pattern starting means 72, game balls that have flowed down the right flow path 84b have a higher probability of winning than game balls that have flowed down the left flow path 84a. This big win means 74 opens in a predetermined big win opening pattern (big win game) when the first and second special symbols of the first and second special symbol display means 63, 64 stop in a big win mode (specific mode) after fluctuating, and opens in a predetermined small win opening pattern (small win game) when they stop in a small win mode. When a game ball wins in this big win means 74, a predetermined number of game balls are paid out as prize balls for each win.

[0044] In addition, the liquid crystal display means 76 is capable of displaying a changing decorative pattern 90 in parallel with the changing display of the first and second special patterns by the first and second special pattern display means 63, 64, and is also capable of displaying various images such as first and second reserve notification images X1 to X4, Y1 to Y4 indicating the number of first and second special reserves, and a changing reserve notification image Z.

[0045] Here, the decorative pattern 90 has a plurality of pattern rows (three in the left-right direction in the example of Fig. 5) each consisting of a plurality of numerical patterns and other patterns, and each pattern constituting each pattern row is composed of a pattern main body 90a consisting of numbers such as 1 to 8 and the like, and a character or other decorative portion 90b associated with this pattern main body 90a, as shown in Fig. 5. The display mode of the decorative pattern 90 can be changed as desired, such as by enlarging or reducing it, changing the display position, or erasing the decorative portion 90b.

[0046] The decorative symbols 90 begin to vary by vertical scrolling, horizontal scrolling, etc. for each symbol row according to a predetermined variation pattern, for example, approximately simultaneously with the start of variation of the first and second special symbols, and finally stop, for example, approximately simultaneously with the stop of the first and second special symbols, so that the stopped symbols on a predetermined effective line will be in a predetermined mode. Note that with the decorative symbols 90, for example, when all the stopped symbols on an effective line are the same, a big win presentation mode is displayed, and otherwise a small win presentation mode or a miss presentation mode is displayed. When the first and second special symbols are in a big win mode, the decorative symbol 90 will be in a big win presentation mode, when the first and second special symbols are in a small win mode, the decorative symbol 90 will be in a small win presentation mode, and when the first and second special symbols are in a miss mode, the decorative symbol 90 will be in a miss presentation mode.

[0047] Furthermore, with regard to the first and second reserved notification images X1-X4, Y1-Y4 and the changing reserved notification image Z, when the number of first and second special reserved items increases based on the first and second special pattern starting means 72, 73 detecting a game ball, one additional first and second reserved notification image X1-, Y1- is displayed on the liquid crystal display means 76, and when the number of first and second special reserved items decreases based on the start of a new change of the first and second special patterns by the first and second special pattern display means 63, 64, for example, the changing reserved notification image Z is erased and the first and second reserved notification images X1-, Y1- are shifted one by one toward the front of the queue (for example, to the right side of the screen), and the pushed-out first first and second reserved notification images X1, Y1 are moved, for example, to a predetermined position and changed into a new changing reserved notification image Z.

[0048] In addition, as shown in Figure 7, a rear case 91 is attached to the back side of the game board 16 to support the LCD display means 76 on the rear side of the game board 16, and on the back side of this rear case 91, a main board case 94 containing a main control board 93 that constitutes the main control unit 92, a presentation board case 100 containing a presentation interface board 96, LCD interface board 97, LCD control board 98 and ROM board 99 that constitute the presentation control unit 95, etc. are attached in a freely attachable and detachable manner.

[0049] Here, the details of how the performance interface board 96, the liquid crystal interface board 97, the liquid crystal control board 98 and the ROM board 99 are stored in the performance board case 100 will be described with reference to FIGS.

[0050] The rendering interface board 96 and the liquid crystal interface board 97 are arranged close to each other on the left and right, with their respective surfaces 96a, 97a facing rearward. The rendering interface board 96 and the liquid crystal interface board 97 are integrated with each other by directly connecting, in the left-right direction, the first and second rendering IF connectors CN11, CN12 arranged along the edge of the rendering interface board 96 on the liquid crystal interface board 97 side, and the first and second liquid crystal IF connectors CN21, CN22 arranged along the edge of the liquid crystal interface board 97 on the rendering interface board 96 side. Note that, while various electronic components are arranged on both the front and back sides of the rendering interface board 96, various ICs such as the audio processor 101 and digital amplifier 102, various connectors such as the first to third liquid crystal IF connectors CN21 to CN23, and the audio ROM 103 are arranged on the surface 96a side. Various electronic components are also arranged on both the front and back sides of the liquid crystal interface board 97, but various connectors such as the first to third liquid crystal IF connectors CN21 to CN23, as well as the first and second liquid crystal connection connectors CN24 and CN25 for connecting the liquid crystal display means 76, are arranged on the surface 97a side.

[0051] The liquid crystal control board 98 is disposed behind the presentation interface board 96 and the liquid crystal interface board 97, with its front surface 98a facing backward and its back surface 98b facing the front surfaces 96a, 97a of the presentation interface board 96 and the liquid crystal interface board 97. The liquid crystal control board 98 is integrated with the presentation interface board 96 and the liquid crystal interface board 97 by directly connecting the liquid crystal control first connector CN31 provided on the back surface 98b to the presentation IF third connector CN13 on the presentation interface board 96 side, and directly connecting the liquid crystal control second connector CN32 also provided on the back surface 98b to the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side. Various electronic components are disposed on both the front and back surfaces of the liquid crystal control board 98, with the composite chip 104, control ROM 105, DRAM 106, liquid crystal control third connector CN33, etc., disposed on the front surface 98a side, and the liquid crystal control first and second connectors CN31, CN32, etc., disposed on the back surface 98b side.

[0052] The ROM board 99 is disposed adjacent to, for example, below, the liquid crystal control board 98, with its surface 99a facing backward and its back surface 99b facing the performance interface board 96 or the liquid crystal interface board 97, for example, the surface 97a of the liquid crystal interface board 97. The ROM board 99 is integrated with the liquid crystal control board 98 by directly connecting the ROM first connector CN41, which is disposed on the upper edge of the surface 99a side, to the liquid crystal control third connector CN33, which is disposed on the lower edge of the liquid crystal control board 98. Note that while various electronic components are disposed on both the front and back sides of the ROM board 99, the CGROM 107, the ROM first connector CN41, etc. are disposed on the surface 99a side.

[0053] As explained above, by directly connecting the connectors of the boards 96 to 99, the surfaces 96a, 97a of the performance interface board 96 and the liquid crystal interface board 97 and the back surfaces 98b, 99b of the liquid crystal control board 98 and the ROM board 99 are connected and integrated with a predetermined gap between them. Therefore, when the boards 96 to 99 are connected to each other, the back surface 98b of the liquid crystal control board 98 is hidden by the performance interface board 96 and the liquid crystal interface board 97 and cannot be seen.

[0054] The performance board case 100 is made of transparent synthetic resin and is formed in a roughly box shape with a base body 111 that covers the back sides of the boards 96-99 and a cover body 112 that covers the front sides of the boards 96-99. When storing the boards 96-99 in the performance board case 100, the liquid crystal control board 98 and the ROM board 99 are first connected to each other by direct connection of connectors, and then fixed in a predetermined position inside the cover body 112 with screws. At this time, the surfaces 98a, 99a of the liquid crystal control board 98 and the ROM board 99 face the inner surface of the back wall 113 of the cover body 112 with a predetermined gap between them.

[0055] Next, with the performance interface board 96 and the liquid crystal interface board 97 connected to each other by direct connection of the connectors, they are fitted into predetermined positions inside the cover body 112 from the rear side of the liquid crystal control board 98 and the ROM board 99. At this time, the performance IF third connector CN13 on the performance interface board 96 side is connected to the liquid crystal control first connector CN31 on the liquid crystal control board 98 side, and the liquid crystal IF third connector CN23 on the liquid crystal interface board 97 side is connected to the liquid crystal control second connector CN32 on the liquid crystal control board 98 side.

[0056] Next, the base body 111 is fitted into the cover body 112 from the rear surfaces 96b, 97b of the performance interface board 96 and the liquid crystal interface board 97. Then, the boards 96 to 99 are fixed in predetermined positions within the performance board case 100 by screwing them from the outside of the base body 111 to the screw bases 115 on the cover body 112 side through the through holes 114 of the performance interface board 96 and the liquid crystal interface board 97. The performance board case 100, which stores the boards 96 to 99, is detachably attached to the rear side of the rear case 91 with the base body 111 facing the front and the cover body 112 facing the rear.

[0057] 7, a back cover 121 that covers the back side of the game board 16 in an openable and closable manner is detachably attached to the back side of the front frame 3, and a game ball tank 122 and a tank rail 123 are attached above it, and a payout means 32 and a payout passage 124 are attached to one of the left and right sides, respectively. When a game ball enters a winning opening such as the big prize means 74, or when a ball lending command is received from an automatic ball lending machine (not shown), the game ball in the game ball tank 122 is paid out by the payout means 32 via the tank rail 123, and the game ball is guided to the upper tray 33 via the payout passage 124. The back cover 121 is arranged to cover almost the entire performance board case 100 and a portion of the upper side of the main board case 94 from the rear.

[0058] In addition, a board mounting stand 125 is removably mounted on the lower back side of the front frame 3, and a power supply board case 127 containing a power supply board 126 and a dispensing / launching board case 129 containing a dispensing / launching control board 128 are each removably mounted on the back side of this board mounting stand 125.

[0059] Figure 10 is a block diagram showing the overall configuration of the control system of this pachinko machine. As shown in Figure 10, the overall circuit configuration of this pachinko machine is made up of a board-side member 131 mounted on the game board 16 side and a frame-side member 132 mounted on the front frame 3 side.

[0060] First, we will explain the outline of the board side member 131. The board side member 131 is composed of a main control board 93 that constitutes the main control unit 92, a performance interface board 96 that constitutes the performance control unit 95, a liquid crystal interface board 97, a liquid crystal control board 98, and a ROM board 99, as well as a game board relay board 133, an LED connection board 134, a main control relay board 135, a power supply relay board 136, a frame LED relay board 137, etc.

[0061] The main control board 93 performs overall game control, and is connected to the game ball detection switches provided in the normal symbol starting means 71 and the big winning means 74, etc., the opening / closing drive means provided in the big winning means 74, etc., various sensors for magnetism, radio waves, vibrations, etc., arranged in various parts of the game board 16, the game information display means 60, etc., via relay boards such as the game board relay board 133, or directly without via a relay board. The main control board 93 is also connected to the performance interface board 96 via a performance control harness 138, and is capable of transmitting control commands CMD and strobe signals STB.

[0062] The main control relay board 135, power supply relay board 136 and frame LED relay board 137 are used to connect the board side member 131 to the frame side member 132, and the main control board 93 is connected to the payout launch control board 128 via the main control relay board 135, and the performance interface board 96 is connected to the power supply board 126 via the power supply relay board 136 and to the under-frame LED connection board 139 via the frame LED relay board 137. The main control relay board 135, power supply relay board 136, and frame LED relay board 137 on the gaming board 16 side have the first to third board-side connectors CN1a to CN3a arranged corresponding to the rear side of the gaming board 16, respectively, and the gaming board mounting section 14 on the inner frame 6 side (Figure 2) has the first to third frame-side connectors CN1b to CN3b arranged opposite the first to third board-side connectors CN1a to CN3a, respectively, so that when the gaming board 16 is mounted on the gaming board mounting section 14 of the inner frame 6 from the front side, the first to third board-side connectors CN1a to CN3a are coupled to the first to third frame-side connectors CN1b to CN3b, respectively. The frame side first connector CN1b is provided at one end of the payout firing control relay harness 141 connected to the payout firing control board 128, the frame side second connector CN2b is provided at one end of the performance control power supply harness 142 connected to the power supply board 126, and the frame side third connector CN3b is provided at one end of the under-frame LED connection harness 143 connected to the under-frame LED connection board 139.

[0063] The performance interface board 96, LCD interface board 97, LCD control board 98 and ROM board 99 that make up the performance control unit 95 are integrated with each other by directly connecting the connectors to each other without using a harness, as already explained.

[0064] Furthermore, the liquid crystal display means 76 is connected to the liquid crystal interface board 97 from the first and second liquid crystal connection connectors CN24 and CN25 via the first and second liquid crystal connection harnesses 144 and 145. Furthermore, the LED connection board 134 is connected to the performance interface board 96 via an LED connection harness 146. The LED connection board 134 is connected to various LED boards such as the LED board 312 that constitutes the movable role lamp 314 and the LED boards 322a to 322c that constitute the board lamp 324, as well as to a motor used to control the drive of the movable role 77a, a movable body drive means such as a solenoid, a position detection switch, etc.

[0065] The specifications of the liquid crystal display means 76 will now be described with reference to Figure 11 and other figures. The liquid crystal display means 76 is a liquid crystal color display with 1280 horizontal pixels x 1024 vertical pixels, and is configured so that control signals (ODD signal, EVEN signal) corresponding to odd-numbered pixels (ODD) and even-numbered pixels (EVEN) adjacent in the left-right direction are received at the receiving unit RV (RVa+RVb) via separate LVDS (Low Voltage Differential Signaling) transmission paths. In this embodiment, in accordance with this specification, the ODD signal (first signal) is transmitted via a first transmission path LVDS1 including the first liquid crystal connection connector CN24 and the first liquid crystal connection harness 144, and the EVEN signal (second signal) is transmitted via a second transmission path LVDS2 (lower left of Figure 10).

[0066] Furthermore, in this liquid crystal display means 76, the operating clock CK that regulates internal operations is specified to have a frequency in the range of 40 MHz to 70 MHz (typically 54 MHz). This operating clock CK corresponds to the dot clock DCK, but for convenience in the following explanation, the frequency of the operating clock CK will be set to a typical value of 54 MHz. A configuration will be explained in which the update time (frame rate) required to update one frame of image using this 54 MHz operating clock CK is set to approximately 1 / 60 seconds.

[0067] The liquid crystal display means 76 is configured to simultaneously process two adjacent pixels on the display screen in the horizontal direction with one operating clock CK, based on the ODD signal received from the first transmission path LVDS1 and the EVEN signal received from the second transmission path LVDS2. As a result, pixel data for 1280 pixels corresponding to one horizontal line is updated in an operating time of 640 / 54 MHz = 11.85 μs, and this operation is repeated for 1024 vertical lines, thereby updating the image display of 1280 × 1024 pixels for one frame. The image is updated line by line in a non-interlaced manner, such as first line → second line → ... → 1024th line.

[0068] 11, the specifications of the liquid crystal display means 76 stipulate that a typical horizontal wait time (blank period) WTh is 204 clocks, and a typical vertical wait time (blank period) WTv is 42 lines. Therefore, the actual screen update period taking these wait times WTh and WTv into consideration is calculated based on the typical values ​​described above as (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 ms, resulting in a frame rate of approximately 60 Hz.

[0069] Note that the horizontal wait time WTh and vertical wait time WTv each have a specified tolerance range for their typical values, so in practice it is possible to select values ​​different from the typical values ​​described above. However, to set the frame rate to 1 / 60 seconds, the horizontal and vertical wait times WTh and WTv must be set accurately so that (WTh + 640) × (WTv + 1024) / 54 MHz = 1 / 60 seconds.

[0070] Furthermore, the liquid crystal display means 76 does not require a horizontal synchronizing signal HS and a vertical synchronizing signal VS, but does require the transmission of an H-level data valid signal ENAB when transmitting ODD and EVEN signals. That is, when significant signals (ODD / EVEN signals) are being transmitted to the first and second transmission lines LVDS1 and LVDS2, the data valid signal ENAB must be at an active level (H level).

[0071] Therefore, in this embodiment, based on the specifications of the above-mentioned liquid crystal display means 76, the liquid crystal control board (display control means) 98 and the liquid crystal display means 76 are LVDS-connected via a dual link transmission line with a dot clock (pixel clock) DCK of 54 MHz (FIGS. 13 and 18). Also, the VDP circuit 172 (FIG. 14, etc.) mounted on the liquid crystal control board 98 is provided with a horizontal waiting time WTh and a vertical waiting time WTv that satisfy the specifications of the liquid crystal display means 76, and is configured so that the data valid signal ENAB is at an active level (H level) when image data (ODD / EVEN signals) are output.

[0072] That is, as shown in Fig. 12(b), the data valid signal ENAB is configured to be H level only during the horizontal display period THd of the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always L level except during the vertical display period TVd of the vertical synchronization period TV (Fig. 12(c)). Note that the horizontal waiting time WTh and the vertical waiting time WTv adopt values ​​different from their respective typical values ​​(WTh is 204, WTv is 42), but specific design values ​​will be described later with reference to Fig. 19.

[0073] In either case, as shown in Fig. 12(a), the data valid signal ENAB is repeatedly transmitted as a discrete DE signal via differential signal lines RA2 and RB2 in each operating cycle of the dot clock DCK. The data valid signal ENAB shown in Fig. 12(b) and (c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous DE signal on the time axis. As shown in Fig. 12(a), the vertical synchronizing signal VS and the horizontal synchronizing signal HS are also repeatedly transmitted via differential signal lines RA2 and RB2 following the DE signal (data valid signal ENAB). However, the liquid crystal display means 76 of this embodiment does not utilize the synchronizing signals VS and HS, and therefore does not perform internal operations related to these synchronizing signals HS and VS.

[0074] In other words, the horizontal line feed timing of the display line in the liquid crystal display means 76 of this embodiment is determined to be optimal for the internal circuitry of the liquid crystal display means 76, regardless of the received horizontal synchronization signal HS, based on the falling timing of the data valid signal ENAB, the number of operating clocks CK (corresponding to dot clocks DCK) after the rising timing of the data valid signal ENAB (640 in this embodiment), etc. (downward arrow in Figure 12(b)).

[0075] The same applies to the vertical line feed timing after one frame of image display, which is determined to be optimal for the internal circuitry of the liquid crystal display means 76 based on the number of consecutive data valid signals ENAB with a predetermined pulse width (1024 in this embodiment) and is not affected by the received vertical synchronization signal VS (downward arrow in FIG. 12(c)). As described above, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or the vertical synchronization signal VS to the liquid crystal display means 76, and therefore there is no need to optimally set the pulse widths PWh, PWv, front porch FPh, FPv, back porch BPh, BPv, etc. of the synchronization signals HS, VS, and this significantly reduces the control burden on the VDP circuit 172, etc.

[0076] Furthermore, the internal operation of the liquid crystal display means 76 is such that horizontal and vertical line feed operations are performed at optimal timing based on its own internal configuration, eliminating the risk of unnatural display operation.Incidentally, in the case of display means that operate based on horizontal and vertical synchronizing signals HS and VS received from the outside, there is a risk that normal display operation will be impaired if the pulse widths of the synchronizing signals HS and VS or the front porch and back porch periods before and after the synchronizing signals HS and VS are inappropriate.

[0077] 12(a), the first transmission path LVDS1 using differential signal lines RA0 to RA3 and RACLK transmits signals corresponding to odd-numbered pixels (ODD signals on side A), and the second transmission path LVDS2 using differential signal lines RB0 to RB3 and RBCLK transmits signals corresponding to even-numbered pixels (EVEN signals on side B). In this way, in this embodiment, by transmitting the ODD and EVEN signals over a dual-link transmission path, the frequency of the dot clock DCK can be effectively reduced by half, which improves noise resistance and also increases the transmission distance.

[0078] Meanwhile, the liquid crystal display means 76 has a built-in receiver RV that receives the ODD and EVEN signals transmitted over the dual link transmission line, and restores the RGB signal from the two LVDS signals (ODD and EVEN signals) to display an image for one frame (1280 x 1024 pixels).Since each RGB signal is composed of 8 bits, a full-color image with a gradation of 28 x 28 x 28 is displayed on the liquid crystal display means 76.

[0079] 13 is a block diagram showing the internal configuration of the liquid crystal display means 76 together with the relevant parts of the VDP circuit 172. As shown in the figure, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first transmission path LVDS1 (A side), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second transmission path LVDS2 (B side). The first transmission path LVDS1 has five differential signal lines RA0 to RA3 and RACLK, and the second transmission path LVDS2 has five differential signal lines RB0 to RB3 and RBCLK.

[0080] Of the 8-bit RGB data, image data R0-R5 and G0 are output from the differential signal line RA0 / RB0, image data G1-G5, B0 and B1 are output from the differential signal line RA1 / RB1, image data B2-B5, a DE signal (i.e., a data valid signal ENAB), a VS signal and an HS signal are output from the differential signal line RA2 / RB2, and image data G6, G7, B6, B7, R6 and R7 are output from the differential signal line RA3 / RB3. As mentioned above, the output VS and HS signals are not used.

[0081] Furthermore, the dot clock DCK of the differential signal lines RACLK / RBCLK is supplied to a PLL circuit, which generates an operating clock CK with the same frequency of 54 MHz as the dot clock DCK. This operating clock CK regulates the internal operation of the liquid crystal controller LCD_CTL, which processes image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent to each other in the left and right direction on the liquid crystal panel LCD in unison, in synchronization with a single operating clock CK.

[0082] Therefore, processing of a pixel with 1280 (=640 x 2) dots in the horizontal direction will be completed in 11.85 μS (=640 / 54 MHz), which is the processing time for 640 operating clocks. Note that the image data corresponding to one pixel is 1 byte long for each of RGB (gradation 28 x 28 x 28), so the image data for all pixels (1280 dots) that make up one line will be 3 x 1280 bytes long overall.

[0083] 13, the liquid crystal controller LCD_CTL appropriately controls the source driver SDV, which drives 1280 source signal lines with drive signals of 28 (=256) gradations each, and the gate driver GDV, which controls the ON / OFF of 1024 gate signal lines. Specifically, the liquid crystal controller LCD_CTL realizes image update operations at a frame rate of 60 Hz by appropriately operating each component based on the DE signal (data valid signal ENAB) extracted from the LVDS transmission line and the operating clock CK.

[0084] Each pixel on the LCD panel is composed of three basic RGB pixels. The total number of basic pixels (1280 dots) on one line is 3 × 1280. Therefore, the source driver SDV is configured with 10 driver elements, each with 384 output terminals. Image data DAT is sequentially supplied to these 10 driver elements from the LCD controller LCD_CTL, and transferred appropriately based on the start signal SP and the transfer clock DCLK. Analog-converted drive signals are then supplied to 3840 source signal lines in synchronization with the latch signal LT. As explained above, the time required to update all the pixels (1280 dots) on one line of the LCD panel is 11.85 μS (= 640 / 54 MHz).

[0085] Meanwhile, the LCD controller LCD_CTL updates the gate signal lines to be driven by supplying a gate start signal GS and a gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured with four driver elements, each with 256 output terminals.

[0086] The update timing of the gate signal line is determined based on the falling edge of the DE signal and the operating clock CK. The horizontal line feed period of the gate signal line is counted using the operating clock CK, and is calculated as 640 + 204 clocks in typical value calculations (see FIG. 11). Based on the number of DE signals (1024), the gate signal line to be driven is reset to its initial state, a gate start signal GS is output at the optimal timing, and output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal line is counted using the operating clock CK, and is calculated as 42 + 1024 clocks in typical value calculations (see FIG. 11). However, as explained above, in this embodiment, the liquid crystal display means 76 is operated using a design different from the typical value (see FIG. 19).

[0087] Next, returning to Figure 10, an overview of the frame side member 132 will be described. The frame side member 132 is mainly composed of a power supply board 126 and a payout / launch control board 128. The power supply board 126 receives AC 24V and outputs various DC voltages, outputting DC 5V, DC 12V, and DC 35V to the payout / launch control board 128 and DC 12V to the under-frame LED connection board 139, as well as outputting DC 5V, DC 12V, and DC 35V to the performance interface board 96 via a power supply relay board 136. A backup board 147 is connected to the payout / launch control board 128, and the payout / launch control board 128 outputs the DC 5V, DC 12V, and DC 35V received from the power supply board 126, as well as backup power and power supply abnormality signals, to the main control board 93 via a main control relay board 135.

[0088] In addition, the payout launch control board 128 is connected to the launch drive means 17d that constitutes the launch means 17, an external terminal board 148 for outputting various information to an external host computer, etc., a lending device connection terminal board 149 for connecting an external game ball lending device, as well as a frame relay board 150, a tray relay board 151, etc.

[0089] The frame relay board 150 relays the connections between the payout motor 32a, payout counting switch 32b, front door / inner frame opening switch 152, etc., arranged on the inner frame 6 side and the payout launch control board 128. The tray relay board 151 also relays the connections between the payout connection board 153, ball jam detection board 154, degree display board 155, etc., on the front door 7 side and the payout launch control board 128. The payout connection board 153 is connected to the variable resistor 35a, payout stop switch 35b, touch sensor 35c that make up the payout handle 35, as well as the ball feed solenoid 53c provided in the ball feed unit 53a.

[0090] Furthermore, in addition to the lower speaker 18 on the inner frame 6 side, a frame lower left LED connection board 156 on the front door 7 side is connected to the frame lower left LED connection board 139. To the frame lower left LED connection board 156, there are connected the LED boards 302a to 302d that constitute the frame lamp 304, a handle LED board 158 that is arranged on the firing handle 35, an effect button LED connection board 159 to which the effect button 41 and the LED boards therein are connected, a volume and light intensity button board 160 to which the volume / light intensity adjustment buttons 39, 40 and the like are connected, the upper speaker 25, a side unit relay board 161 that is connected to the side unit 30, and the like.

[0091] Next, the circuit configuration of the performance interface board 96, liquid crystal interface board 97, liquid crystal control board 98, and ROM board 99 that make up the performance control unit 95 will be described in detail with reference to Figures 10, 14, etc.

[0092] As shown in Figure 10, the performance interface board 96 includes, in addition to various input / output buffers, an audio processor 101 that reproduces audio signals based on instructions received from a CPU circuit 171 (Figure 14) mounted on the composite chip 104 of the LCD control board 98, an audio ROM 103 that stores compressed audio data, etc., which is the original data for the audio signals to be reproduced, and a digital amplifier 102 that receives audio signals output from the audio processor 101. The audio processor 101 incorporates a WDT circuit that automatically resets the setting values ​​of the internal circuit to default values ​​in the event of an abnormal operation of the internal circuit, and an audio control register SRG, and the audio control register SRG accesses the audio ROM 103 based on operating parameters received from the CPU circuit 171 of the composite chip 104, reproduces the required audio signals, and outputs them to the digital amplifier 102.

[0093] The various input / output buffers mounted on the performance interface board 96 include an input buffer for receiving control commands CMD and strobe signals STB from the main control board 93 and transferring them to the composite chip 104 of the liquid crystal control board 98, an input buffer for receiving switch signals from the performance buttons 41 etc. via the frame LED relay board 137 and transferring them to the composite chip 104 of the liquid crystal control board 98, an output buffer for transferring serial signals received from the liquid crystal control board 98 to a driver IC of an LED board etc. via the frame LED relay board 137, an input buffer for receiving switch signals from movable body position detection switches etc. via the LED connection board 134 and transferring them to the composite chip 104 of the liquid crystal control board 98, and an output buffer for transferring serial signals received from the liquid crystal control board 98 to a driver IC of an LED board etc. via the LED connection board 134.

[0094] The liquid crystal control board 98 is also equipped with a composite chip (chip) 104 incorporating a CPU circuit 171, a VDP circuit 172, etc., a control ROM (ROM connected to the chip) 105 that stores the control program for the CPU circuit 171, and a DRAM (Dynamic Random Access Memory) 106 that can access large amounts of data at high speed, and the ROM board 99 connected to the liquid crystal control board 98 is equipped with a CGROM 107 that stores large amounts of CG data required for performance control.

[0095] The control ROM 105 is located in the address space CS0 selected by the chip select signal CS0, and the DRAM 106 is located in the address space CS5 selected by the chip select signal CS5.

[0096] 14 is a circuit block diagram illustrating the composite chip 104 mounted on the liquid crystal control board 98, including related circuit elements. As shown in the figure, the composite chip 104 incorporates a CPU circuit 171 that issues a display list DL at predetermined time intervals, and a VDP circuit 172 that generates image data based on the issued display list DL and drives the liquid crystal display means 76. The CPU circuit 171 and VDP circuit 172 are connected via a CPUIF circuit 173 that relays data sent and received between them.

[0097] The CPU circuit 171 generates a CPU operating clock of approximately 266.7 MHz by frequency-multiplying (e.g., by 8) the oscillation output (e.g., 100 / 3 MHz) from the oscillator OSC1 received at the HCLKI terminal of the composite chip 104. Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby achieving EMI (Electromagnetic Interference) countermeasures to prevent radio interference / electromagnetic disturbance.

[0098] On the other hand, the VDP circuit 172 uses the oscillation output (for example, 40 MHz) received from the oscillator OSC2 at the PLLREF terminal of the combined chip 104, multiplying the frequency as necessary, as the system clock of the VDP circuit 172, the display clock (dot clock, etc.) for the display device, and the DDR clock of the external DRAM 106. In other words, the output of the oscillator OSC2 functions as the reference clock for the entire VDP circuit 172.

[0099] Considering the importance of this reference clock, the oscillator OSC2 is operated at the same power supply voltage of 3.3V as the VDP circuit 172, and is configured to oscillate and output the reference clock on the condition that the output enable terminal OE is at H level (=3.3V), and to generate a non-maskable interrupt (NMI) if the power supply voltage of 3.3V drops below a predetermined level.

[0100] The combined chip 104 is also provided with an HBTSL terminal, and the ROM that stores the boot program (initial setting program) that is executed after power-on (CPU reset) is specified based on the logic level of this HBTSL terminal. As shown in the figure, in this embodiment, HBTSL is set to L, and address zero of the address space CS0 of the CPU circuit 171 is assigned to the control ROM 105.

[0101] The CPUIF circuit 173 is connected to a control ROM 105 that stores control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 174 having a storage capacity of approximately 2 MB, each of which can be accessed from the CPU circuit 171 and the VDP circuit 172.

[0102] The control ROM 105 is located in the address space CS0 selected by the chip select signal CS0, and the work memory 174 is located in the address space CS6 selected by the chip select signal CS6. The work memory 174 has a DL buffer BUF reserved for temporarily storing a display list DL in which a series of instruction commands specifying one frame of the liquid crystal display means 76 is written.

[0103] The CPU circuit 171 is a circuit with performance equivalent to that of a general-purpose one-chip microcomputer, and is equipped with a performance control CPU 181 that comprehensively controls image performance based on the control program in the control ROM 105, an internal RAM 182 with a storage capacity of approximately 16k bytes that is used as the CPU's working area, a DMAC (Direct Memory Access Controller) 183 for realizing data transfer without going through the performance control CPU 181, a serial input / output port (SIO) 184 with multiple input ports Si and output ports So, a parallel input / output port (PIO) 185 with multiple input ports Pi and output ports Po, and a control register (REG) 186 in which setting values ​​are set to control the operation of each of these parts.

[0104] The parallel input / output port 185 is connected to an external device (performance interface board 96) via an input / output circuit 187, etc., and the performance control CPU 181 receives switch signals from the performance button 41, etc., control commands CMD, interrupt signals STB, etc. via the input / output circuit 187.

[0105] Next, we will explain the VDP circuit 172. Connected to the VDP circuit 172 are a CGROM 107 that stores compressed data that is a component of still images and moving images used in image presentations, an external DRAM 106 with a storage capacity of about 4 Gbits, and the liquid crystal display means 76. In this embodiment, the DRAM 106 is configured with DDR3 (Double-Data-Rate 3 SDRAM), and the CGROM 107 is configured with a flash SSD (solid state drive) made of NAND-type flash memory.

[0106] As shown in FIG. 14, the VDP circuit 172 controls the operation of a VDP (Video Display Processor). A control register group 201 that can set various operation parameters that define the operation by the performance control CPU 181, an internal VRAM (video RAM) 202 of about 48 MB that is used when generating image data to be displayed on the liquid crystal display means 76, and data transmission and reception between each part inside the chip. a data transfer circuit 203 that transmits and receives data to and from the outside of the chip; an index table IDXTBL that can identify address information of the source and destination for the built-in VRAM 202; a preloader 204 that can perform a preload operation to access the CGROM 107 for reading prior to a drawing operation; a graphics decoder (GDEC) 205 that decodes (decodes and expands / expands) compressed data read from the CGROM 107; a drawing circuit 206 that generates image data for one frame of the liquid crystal display means 76 by appropriately combining still image data and video data after decoding (expanding); a geometry engine 207 that generates a three-dimensional image by appropriate coordinate conversion as part of the operation of the drawing circuit 206; The image processing unit 170 includes a plurality of systems, for example, three systems (A / B / C) of display circuits 208A to 208C, which are capable of reading image data from the frame buffer FBa and executing appropriate image processing in parallel, an output selection unit 209 which appropriately selects the output of the three systems (A / B / C) of display circuits 208A to 208C, an LVDS unit 210 which converts the image data output by the output selection unit 209 into an LVDS signal, an SMC unit 211 which is capable of transmitting and receiving serial data, a CPUIF unit 212 which relays data transmission and reception with the CPUIF circuit 173, a CG bus IF unit 213 which relays data reception from the CGROM 107, a DRAMIF unit 214 which relays data transmission and reception with the external DRAM 106, a VRAMIF unit 215 which relays data transmission and reception with the built-in VRAM 202, and an audio circuit SND.

[0107] 15 illustrates the relationship between the CPUIF unit 212, CG bus IF unit 213, DRAMIF unit 214, and VRAMIF unit 215 and the control register group 201, CGROM 107, DRAM 106, and built-in VRAM 202. As shown in the figure, CG data acquired from CGROM 107 is transferred, for example, as preload data, to a preload area of ​​the external DRAM 106 via the data transfer circuit 203 and DRAMIF unit 214. Note that this preload operation is not essential, and the data transfer destination is not limited to the external DRAM 106 but may be the built-in VRAM 202. For example, when the preload operation is not configured to be executed, the CG data is transferred to the built-in VRAM 202 via the data transfer circuit 203 and VRAMIF unit 215.

[0108] The built-in VRAM 202 requires a decompression area for compressed data read from the CGROM 107, a frame buffer area for storing image data specifying each ARGB information (32 bits = 8 × 4) of the W × H display pixels of the display device, and a Z buffer area for storing depth information for each display pixel. In the ARGB information, A means 8-bit alpha plane data, and RGB means 8-bit data of the three primary colors.

[0109] Here, each of the above-mentioned areas of the built-in VRAM 202 is indirectly accessed based on the various instruction commands (textures, sprites, etc.) written in the display list DL by the performance control CPU 181, but it would be cumbersome to specify the destination address and source address of the built-in VRAM 202 for each READ / WRITE access. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as index space) required for drawing operations is secured, and an index number is assigned to each index space, making it possible to access based on the index number.

[0110] Specifically, after the CPU is reset, the internal VRAM 202 is roughly divided into three types of memory areas, and the required number of index spaces is secured in each memory area. Then, an index table IDXTBL (see FIG. 16(a)) is constructed to associate and store the index spaces with index numbers, thereby enabling subsequent operations based on the index numbers.

[0111] This index space may need to be added (1) after initial processing or, conversely, released (2). Therefore, a flag area FG is provided in the index table IDXTBL to determine whether the timing for adding / release processing is possible and whether the processing, such as adding / release, has actually been completed during the operation of the performance control CPU 181 for adding / release. The built-in VRAM 202 is broadly divided into three types of memory areas: two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), as described below. The index table IDXTBL is divided into three sections corresponding to these three types of memory areas (a1, a2), (b), and (c) (Figure 16(a)). As shown in the figure, in this embodiment, a first AAC area (a1) and a second AAC area (a2) are secured as the AAC area (a), but this is not limited thereto, and only one of them may be used. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as AAC area (a).

[0112] In this embodiment, the built-in VRAM 202 is configured to be divisible into (a) an index space and an AAC area, to which its index number is automatically assigned by internal processing and which has a memory cache function, (b) a page area, in which, for example, a two-dimensional space of 4096 bits x 128 lines is used as the unit space, and an index space can be secured within a range of an integer multiple of this, and (c) an arbitrary area, in which the start address (space start address) STx and horizontal size Hx can be set arbitrarily (see FIG. 16(b)). However, to facilitate the internal operation of the VDP circuit 172, the space start address STx of the index space, which is arbitrarily set in the arbitrary area (c), must have the lowest 11 bits set to 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0113] After the CPU is reset, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are specified, and the AAC area (a1), second AAC area (a2), and page area (b) are secured, and the remaining memory area becomes the arbitrary area (c). To facilitate the internal operation of the VDP circuit 172, the maximum value of the address space of the AAC area is specified in units of 2048 bits, and the maximum value of the address space of the page area is an integer multiple of the unit space of 4096 bits x 128 lines described above.

[0114] Next, the required number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When using the optional area (c), in order to facilitate the internal operation of the VDP circuit 172, the horizontal size Hx of the index space that handles two-dimensional data can be set arbitrarily as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

[0115] In any case, the first and second AAC areas (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 172, so if the decoding destination is specified as AAC area (a) by, for example, a texture setting command, SETINDEX, then it is sufficient to specify the source address of CGROM 107 and the horizontal and vertical size after expansion (decoding) in the TXLOAD (texture load) command that reads CG data from CGROM 107. Therefore, in this embodiment, the decoding destination for still images (textures) such as characters that appear temporarily during preview performances and I-stream video is set to AAC area (a).

[0116] Since both AAC areas (a) are provided with a memory cache function, for example, if the same texture from CGROM 107 is read into AAC area (a) multiple times, the decoded data cached in AAC area (a) can be used from the second time onwards, making it possible to reduce unnecessary READ access and decoding processing. However, since old data is automatically destroyed when AAC area (a) is used up, in this embodiment, when AAC area (a) is used, the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are stored in the second AAC area (a2).

[0117] Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview performance, background images when the background screen is constructed with still images, etc. In such cases, the SETINDEX command, which is a texture setting command, sets the decoding destination to the second AAC area (a2), and after the TXLOAD command decodes the texture of the characters, background images, etc. into the second AAC area (a2), the second AAC area (a2) is not used, thereby protecting the decoded results.

[0118] Then, if the SETINDEX command is used to specify the second AAC area (a2) as the decoding destination and the same TXLOAD command is executed to re-acquire the acquired texture, the acquired texture will be a cache hit, eliminating the time required for READ access to CGROM 107 and the decoding process. This cache hit function is also exhibited by preload data pre-read into the preload area, but what is significant is that the preload data that is a cache hit in the preload area is compressed data before decoding, whereas the preload data that is a cache hit in the AAC area is decompressed data after decoding.

[0119] The term "texture" generally refers to the feel or texture of an object's surface, but in this embodiment, the term is used to include not only sprite image data that makes up a still image, image data that makes up one frame of a video, and image data that is pasted onto drawing primitives such as triangles and rectangles, but also image data after decoding. When copying image data within the internal VRAM 202 (hereinafter, for convenience, referred to as moving), the source image data is set as a texture using the SETINDEX command, a texture setting command, and then the SPRITE command is executed.

[0120] When the SPRITE command is executed, the source Source image data is technically drawn in the virtual drawing space shown in Figure 16(c), but if the correspondence between the drawing area in the virtual drawing space that is actually drawn on the display device and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then when the SPRITE command is used to draw in the virtual drawing space, the source Source image data will be drawn in a specified index space (frame buffer) (see Figure 16(c)).

[0121] In any case, in this embodiment, the built-in VRAM 202 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured for each, and each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and the performance control CPU 181 can freely assign index numbers in the range of 0 to 255 to the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuit).

[0122] Therefore, in this embodiment, as shown in Figure 16(a), a pair of frame buffers FBa are secured in the arbitrary area (c) for the liquid crystal display means 76, and index numbers 255 and 254 are assigned to both of the double buffer structure. That is, index spaces 255 and 254 are secured as the frame buffer FBa for the liquid crystal display means 76, and are used by switching between them in a toggle manner. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the liquid crystal display means 76. Note that each pixel is specified by 32-bit ARGB information, so the horizontal size of 1280 means 32 x 1280 = 40960 bits (a multiple of 256 bits).

[0123] The reason why the frame buffer FBa is allocated in the arbitrary area (c) is that the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (=256 bits=8 pixels), and if it matches the number of horizontal pixels of the liquid crystal display means 76 as described above, no wasted space will be created in the allocated area. On the other hand, the page area (b) can only be set to horizontal / vertical sizes that are integer multiples of the unit space of 128 pixels x 128 lines. However, the vertical size of the two-dimensional index space allocated in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area with a horizontal size of 1280 x vertical size of 1024 is the valid data area for the liquid crystal display means 76.

[0124] Furthermore, in this embodiment, when an additional index space (memory area) is reserved in the arbitrary area (c) where the frame buffer FBa is reserved, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is reserved in the arbitrary area (c) as a working area for preview effects in which effect images made up of characters and other still images are made to appear in a part of the display screen in an appropriate rotated position as needed.

[0125] However, the use of a work area is not mandatory, and index space as a work area may be secured in the page area (b) instead of the optional area (c). If the page area (b) is used, an index space with dimensions that are multiples of a square unit space of horizontal size 128 (= 4096 bits) x vertical size 128 can be secured, making it suitable for handling small-sized stage images.

[0126] In this embodiment, image effects, including background images, are realized almost entirely with moving images. Particularly during a variable effect, a large number of moving images (usually 10 or more) are simultaneously rendered. These moving images are all stored in the CGROM 107 in a compressed state as a series of moving image frames, and are classified into I-stream moving images consisting of only I-frames, and IP-stream moving images consisting of I-frames and P-frames. Here, I-frames (Intra coded frames) ) refers to a frame in which the input image is compressed as is, independent of other screens. On the other hand, a P frame (Predictive coded frame) refers to a frame that undergoes forward predictive coding, and requires an I frame or P frame located in the past.

[0127] Therefore, in this embodiment, IP stream video is expanded in a page area (b) rather than in an AAC area (a) where there is a concern that old data may be destroyed. That is, a large number of index spaces (IDX0 to IDXN) are secured in the page area (b) where index spaces of dimensions that are multiples of horizontal size 128 × vertical size 128 can be secured, and a series of video frames are decoded using always the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded in the index space IDX1, video MV2 is expanded in the index space IDX2, and so on, with video MVi being expanded in the index space IDXi.

[0128] To explain the video MVi more specifically, the SETINDEX command specifies in advance that the decoding destination of the IP stream video MVi is the index space (i) of index number i in the page area (b), and then the TXLOAD command is executed to obtain one video frame of the IP stream video MVi.

[0129] Then, one video frame (any of a series of video frames) on CGROM 107 specified by the TXLOAD command is first retrieved into the AAC area (a), and then the graphics decoder (GDEC) 205, which starts automatically, decodes and expands the retrieved video frame into the index space (i) of the page area (b).

[0130] On the other hand, in this embodiment, I-stream video is treated the same as still images, and the SETINDEX command specifies that the I-stream video MVj is decoded to the first AAC area (a1), and then the TXLOAD command is executed. As a result, video frames are acquired in the first AAC area (a1), and the graphics decoder 205, which is automatically activated, then expands the decoded data to the first AAC area (a1). As explained above, the index space for the AAC area (a) is automatically generated, so there is no need to specify an index number. Note that the expansion volume required for the index space, i.e., the horizontal and vertical sizes of the decoded texture (video frame), are specified by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0131] Incidentally, IP stream video MVi and I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 107 where the kth (1≦k≦N) video frame is stored, as well as the horizontal and vertical sizes after expansion. Although not limited in any way, in this embodiment in which still images are hardly used, most of the 48 MB address space (approximately 30 MB) of the internal VRAM 202 is allocated to the page area (b). In this embodiment in which still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, and the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

[0132] It is also possible to provide a dedicated GDEC (graphics decoder) circuit to speed up the decoding process of compressed video data. If a dedicated GDEC circuit is built into VDP circuit 172, it will be sufficient to specify the start address of the compressed video data to the GDEC circuit in the decoding process of compressed video data made up of N compressed video frames, eliminating the need to specify the start address for each of the N compressed video frames.

[0133] However, if multiple dedicated GDEC circuits like this are built in for each compression algorithm, the internal configuration of the VDP circuit 172 becomes even more complex. Therefore, in this embodiment, a software GDEC is used, and decoding of data such as IP stream video, I stream video, still images, and other alpha values ​​is achieved through software processing corresponding to each compression algorithm. The difference in processing time between hardware processing and software processing is not a significant issue; the processing time that matters is primarily the access (READ) time from CGROM 107.

[0134] Let's continue the explanation by returning to Figure 14. The data transfer circuit 203 is a circuit that executes a data transfer operation in a DMA (Direct Memory Access) manner between a resource (storage medium) inside the VDP circuit and an external storage medium, with the resource being the transfer source port and the external storage medium being the transfer destination port. Figure 17 is a block diagram showing the internal configuration of this data transfer circuit 203 together with the related circuit configuration.

[0135] 17, the data transfer circuit 203 is configured to transmit and receive data to and from the CGROM 107, DRAM 106, and built-in VRAM 202 via an integrated connection bus ICM having a router function. The CGROM 107 and DRAM 106 are accessed via a CG bus IF unit 213 and a DMA MIF unit 214.

[0136] Meanwhile, the CPU circuit 171 issues a display list DL to the drawing circuit 206 and preloader 204 via a transfer port register TR_PORT built in the data transfer circuit 203. The CPU circuit 171 and the data transfer circuit 203 are connected bidirectionally, and when issuing a display list DL, the transfer port register TR_PORT functions as a data write port that accepts one unit of data that makes up the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 203d.

[0137] As shown in the figure, the performance control CPU 181 can make WRITE access to the transfer port register TR_PORT via the CPUIF unit 212, but when the DMAC circuit 183 is used, the DMAC circuit 183 makes direct WRITE access to the transfer port register TR_PORT. The series of instruction commands written to the transfer port register TR_PORT (that is, the series of instruction commands that make up the display list DL) are configured to be automatically accumulated in 32-bit units in the CPU bus control unit 203d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

[0138] In addition, this data transfer circuit 203 performs data transmission and reception operations on the transmission paths of three channels ChA to ChC, and has a ChA control circuit 203a (N=130 stages) having a FIFO buffer with a FIFO structure (64 bits x N stages), a ChB control circuit 203b (N=1026 stages), and a ChC control circuit 203c (N=130 stages).

[0139] The instruction command sequence (display list DL) stored in the CPU bus control unit 203d is then transferred to the drawing circuit 206 or preloader 204 based on the setting value of the data transfer register RGij (one type of various control registers 201) by the performance control CPU 181. As shown by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 203d to the drawing circuit 206 via the FIFO buffer of the ChB control circuit 203b, and then to the preloader 204 via the FIFO buffer of the ChC control circuit 203c.

[0140] In this embodiment, the ChB control circuit 203b and the ChC control circuit 203c are specialized for the transfer operation of the display list DL, and the data accumulated in the FIFO buffer of the CPU bus control unit 203d is transferred as part of the display list DL to the display list analyzer of the drawing circuit 206 or the preloader 204 via the FIFO buffer of the ChB control circuit 203b or the ChC control circuit 203c, respectively. do.

[0141] The drawing circuit 206 then starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 204 executes the necessary preload operations based on the transferred display list DL. Through the preload operations, the CG data in the CGROM 107 is pre-read into a preload area secured in the DRAM 106, and the display list DL with the texture source address changed in response to a TXLOAD command or the like (hereinafter referred to as a rewrite list DL') is saved in a DL buffer area BUF' secured in the DRAM 106.

[0142] On the other hand, the ChA control circuit 203a and the connection bus access arbitration circuit 203e function for data transfer between storage media such as the CGROM 107, DRAM 106, and built-in VRAM 202. Furthermore, the IDXTBL access arbitration circuit 203f functions when accessing the built-in VRAM 202, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 203a functions, for example, when (a) compressed data from the CGROM 107 is transferred to the built-in VRAM 202, (b) compressed data from the CGROM 107 is preloaded (read ahead) and transferred to the external DRAM 106, or (c) read-ahead data from the preload area is transferred to the built-in VRAM 202.

[0143] Here, the ChA control circuit 203a is configured to be able to operate in parallel with the ChB control circuit 203b and the ChC control circuit 203c, and the above operations (a) to (c) can be executed in parallel with the issuance operation of the display list DL and the transfer operation of the rewrite list DL'. The ChB control circuit 203b and the ChC control circuit 203c can also execute operations simultaneously. However, since there is only one transfer port register TR_PORT, when one of them (203b / 203c) is using the transfer port register TR_PORT, the other (203c / 203b) cannot access the transfer port register TR_PORT.

[0144] During operation of the ChA control circuit 203a, the connection bus access arbitration circuit 203e arbitrates data transmission with each storage element (CGROM 107, DRAM 106) via the integrated connection bus ICM. controls the ChA control circuit 203a based on the index table IDXTBL, thereby arbitrating data communication with the built-in VRAM 202. In the present embodiment in which the preloader 204 is functioning, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 106 is transferred to the drawing circuit 206 via the connection bus access arbitration circuit 203e and the ChB control circuit 203b.

[0145] As described above, the data transfer circuit 203 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various storage resources (Resources) and a data transfer destination arbitrarily selected from various storage resources (Resources). Note that the storage resources on which the data transfer circuit 203 functions include not only the built-in VRAM 202 but also external devices via the CPUIF unit 212, CG bus IF unit 213, and DRAMIF unit 214.

[0146] Furthermore, the amount of data to be acquired from CGROM 107 at one time (memory sequential READ) and the amount of data transferred between the external device in which the ChA control circuit 203a functions are enormous compared to the display list DL in which the ChB control circuit 203b and the ChC control circuit 203c function, and the amounts of data transferred differ greatly.

[0147] While it would be possible to configure these various data transfers so that the unit data volume and total transfer data volume could be precisely set, this would complicate the control operations within the VDP and hinder smooth transfer operations. Therefore, in this embodiment, a minimum data volume Dmin for data transfer is uniquely defined, and the total transfer data volume is limited to an integer multiple of the minimum data volume DTmin, thereby achieving fast and smooth data transfer operations. While not particularly limited, the data transfer circuit 203 of this embodiment sets the minimum data volume Dmin (unit data volume) to 256 bytes and limits the total transfer data volume to an integer multiple of this volume.

[0148] Therefore, the instruction command sequence of the display list DL stored in the FIFO buffer of the CPU bus control unit 203d for each 32 bits is transferred to the ChB control circuit 203b and the ChC control circuit 203b when the total amount reaches the minimum data amount Dmin, and is stored in each FIFO buffer.

[0149] The display list DL is made up of a series of instruction commands, but in this embodiment, the display list DL is made up of only instruction commands whose command length is an integer multiple of 32 bits (N>0) corresponding to the write unit (32 bits) of the transfer port register TR_PORT. Therefore, the drawing circuit 206 and preloader 204 that receive the instruction commands of the display list DL via the data transfer circuit 203 can quickly and smoothly start command analysis processing (DL analyze). Note that the command length of an integer multiple of 32 bits does not necessarily mean that all of the bits are significant, but rather means that it is an integer multiple of 32 bits including insignificant bits (don't care bits).

[0150] Next, the preloader 204 will be described. The preloader 204 is a circuit that interprets the display list DL transferred from the data transfer circuit 203 (ChC control circuit 203b) and transfers the CG data in the CGROM 107 referenced by the TXLOAD command to a preload area in the DRAM 106 in advance. The preloader 204 also stores a rewrite list DL' in the DL buffer BUF' of the DRAM 106, in which the reference destination of the CG data is rewritten to the address after transfer for this TXLOAD command. The DL buffer BUF' and preload area are reserved in advance during initial processing after the CPU is reset.

[0151] Then, when the drawing operation of the drawing circuit 206 starts, the rewrite list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 206 via the connection bus access arbitration circuit 203e and the ChB control circuit 203b of the data transfer circuit 203. The drawing circuit 206 executes drawing operations based on the rewrite list DL'. Therefore, based on the TCLOAD command or the like, CG data that should originally be obtained from the CGROM 107 is obtained from the preload area of ​​the DRAM 106 as preload data pre-read into the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and preload data that has been cached in the preload area is reused repeatedly.

[0152] In this embodiment, the preload area is set in the external DRAM 106, which has sufficient storage capacity, so the cache hit function described above functions effectively. Furthermore, because the external DRAM 106 has a large storage capacity, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. That is, multiple preloading is realized by appropriately setting the operating period of the preloader 204, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operating cycle δ of the VDP circuit 172 during intermittent operation.

[0153] However, in the following explanation, for convenience, a configuration without multiple preloading will be described, and therefore the preloader 204 of this embodiment will complete the preloading operation for one frame within one operation cycle (δ). In this embodiment, the operation cycle δ during intermittent operation of the VDP circuit 172 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the liquid crystal display means 76.

[0154] Next, the drawing circuit 206 is a circuit that sequentially analyzes the instruction command strings of the display list DL and the rewrite list DL' transferred via the data transfer circuit 203, and draws one frame's worth of image of the liquid crystal display means 76 in the frame buffer formed in the VRAM 202 in cooperation with the graphics decoder 205, the geometry engine 207, etc.

[0155] As described above, when the preloader 204 is activated, the CG data in the rewrite list DL' is referenced not in the CGROM 107 but in the preload area set in the DRAM 106. This allows for rapid sequential access to CG data generated during rendering by the rendering circuit 206, making it possible to render high-resolution moving images with rapid movement without any problems. In other words, according to this embodiment, complex and sophisticated image rendering can be performed while utilizing an inexpensive SATA module as the CGROM 107.

[0156] Incidentally, regardless of whether the preloader 204 is enabled or disabled, even if data corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 206 cannot detect this. Furthermore, the drawing circuit 206 may freeze due to the influence of noise or the like, causing an abnormal stop of READ / WRITE access to the internal VRAM 202. Therefore, in this embodiment, if the drawing circuit 206 detects an irrational instruction command (a bit sequence that cannot be analyzed) or if there is no READ / WRITE access to the internal VRAM 202 for a certain period of time, a drawing abnormality interrupt is generated (drawing abnormality interrupt is enabled).

[0157] Next, as explained with reference to Fig. 16, the frame buffer FB secured in the arbitrary area (c) of the VRAM 202 is a double buffer divided into a drawing area and a read area, and the two areas are used alternately. In this embodiment, one liquid crystal display means 76 is connected, so one section of the frame buffer FBa is secured, as shown in Fig. 16. Therefore, the drawing circuit 206 draws one frame's worth of image data in the drawing area (write area) of the frame buffer FBa for the liquid crystal display means 76.

[0158] The display circuits 208A-208C are circuits that read image data from the frame buffers FBa-FBc, perform final image processing, and output the result (see FIG. 18). The final image processing includes, for example, scaling processing using a scaler to enlarge or reduce the image, subtle color correction processing, and dithering processing to minimize quantization error of the entire image. The digital RGB signals (total of 24 bits) that have undergone these image processing steps are then typically output together with a horizontal synchronization signal HS, a vertical synchronization signal VS, and the like.

[0159] 18, in this embodiment, three display circuits A / B / C are provided that perform the above operations in parallel, and each of the display circuits 208A-208C reads image data from its corresponding frame buffer FBa / FBb / FBc and performs the above final image processing. However, since there is only one display device in this embodiment, the frame buffers FBb and FBc are not reserved, and the display circuits 208B and 208C do not function.

[0160] Here, the specifications of the liquid crystal display means 76 reveal that the liquid crystal display means 76 must receive adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) at the receivers RV (RVa, RVb) via separate LVDS (Low Voltage Differential Signaling) transmission paths. The dot clock DCK frequency of the liquid crystal display means 76 must be approximately 40 to 70 MHz (typically 54 MHz), and the horizontal and vertical waiting times WTh / WTv must be set so that (WTh + 640) × (WTv + 1024) / 54 MHz ≈ 1 / 60 seconds. Furthermore, when image data (ODD / EVEN signals) are output to the liquid crystal display means 76, an active-level data valid signal ENAB must be output.

[0161] Therefore, the display circuit 208A must output signals that satisfy all of the above specifications. Figures 19(a) to 19(e) illustrate various signals output from the display circuit 208A. First, the frequency of the dot clock DCK must be determined. In this embodiment, the liquid crystal display means 76 is operated by an operating clock CK with a typical value of 54 MHz, so the designed dot clock DCK in the VDP circuit 172 is set to 108 MHz (= 54 × 2) correspondingly.

[0162] This is because in a display panel LCD (see Figure 19(f)) with 1280 dots horizontally and 1024 lines vertically, two adjacent pixels on the left and right are processed at once in synchronization with the 54 MHz operating clock CK, which is essentially equivalent to operating with a 108 MHz dot clock DCK.

[0163] Various operating parameters that define the operation of the display circuit 208A are determined based on a dot clock DCK with a frequency of 108 MHz. First, the horizontal and vertical waiting times WTh / WTv must be set so that (WTh+640)×(WTv+1024) / 54 MHz≈1 / 60 seconds, and the operating parameters WTh / WTv for the display circuit 208A must satisfy (WTh+1280)×(WTv+1024) / 108 MHz≈1 / 60 seconds.

[0164] Furthermore, the tolerances for the horizontal and vertical wait times WTh / WTv must also be taken into account in the specifications of the liquid crystal display means 76. Therefore, in this embodiment, the horizontal wait time WTh is set to 382 clocks counted using a 108 MHz dot clock DCK, and the vertical wait time WTv is set to 59 lines. Therefore, the time required to update one frame of image is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, resulting in a frame rate of 1 / 60 seconds.

[0165] Corresponding to this setting, the data valid signal ENAB is at L level during the waiting time WTh (=382 / 108 MHz) corresponding to 382 clocks during the image update operation of each line, and then becomes active (H) during the active interval (=1280 / 108 MHz) corresponding to 1280 clocks (FIG. 19(c)). As shown in FIGS. 19(d) and 19(e), during the active interval of the data valid signal ENAB, image data is output so that the image update operation for one line of 1280 dot pixels is completed within a predetermined time (11.85 μS=1280 / 108 MHz). In other words, 1280 pixel data are output in synchronization with 1280 dot clocks DCK. Since a full-color image with a 28×28×28 gradation is displayed on the liquid crystal display means 76, the pixel data for one pixel is 3×8 bits long.

[0166] In this embodiment, the liquid crystal display means 76 outputs a vertical synchronization signal VS and a horizontal synchronization signal HS, although these signals are not required. The vertical synchronization signal VS is output within a vertical wait time WTv, and the horizontal synchronization signal HS is output within a horizontal wait time WTh. For ease of understanding, FIGS. 19(a) and 19(b) show the respective operating cycles. Also, in FIG. 19(f), circles are shown at the top left and bottom right vertices of a rectangular frame defined by TH×TV (=1083×1662 clocks), indicating "start of display operation" and "end of display operation," respectively. These circles represent the "V blank start" that begins every 1 / 60 seconds. Because the 1083×1662 clocks that define the display operation coincide with 1 / 60 seconds, the elapsed time from the "start of display operation" to the "end of display operation" is 1 / 60 seconds.

[0167] 18, the output selection unit 209 of this embodiment divides the output signal of the display circuit 208A into dual links by dividing the 108 MHz dot clock DCK by two, and transmits them to the LVDS unit 210a and the LVDS unit 210b, respectively (see FIGS. 18 and 13). Each of the LVDS units 210a and 210b then converts the image data (a total of 24-bit digital RGB signal) into first and second LVDS signals, adds one pair for transmitting a clock signal (54 MHz = 10 / 2), and outputs five pairs of differential signals LVDS1 and LVDS2 to the liquid crystal display means 76 via two paths (see FIGS. 18 and 12).

[0168] As explained above, in the liquid crystal display means 76, the ODD signal for one pixel and the EVEN signal for the adjacent pixel are processed at the same timing, so the actual frequency of the dot clock DCK matches the 108 MHz dot clock DCK output by the display circuit 208A.

[0169] In this embodiment, the display circuits 208A to 208C are provided with underrun counters URCNTa to URCNTc that count underrun abnormalities that occur when display data is not generated in time for the display timing (see FIG. 18). The counter values ​​of these underrun counters URCNTa to URCNTc are configured to be automatically incremented for each VBLANK when an underrun abnormality occurs.

[0170] Next, the SMC (Serial Management Controller) unit 211 is a composite controller incorporating an LED controller and a motor controller, and is configured to output LED drive signals and motor drive signals in synchronization with a clock signal to an LED / Motor driver (a driver IC incorporating a shift register) mounted on an external board, while also being able to output latch pulses at appropriate timing.

[0171] Regarding the internal circuitry and its operation of the VDP circuit 172 described above, the operation content to be executed by the internal circuitry is defined by operation parameters (setting values) set in the control register group 201 by the performance control CPU 181, and the execution state of the VDP circuit 172 can be identified by reading the operation status values ​​of the control register group 201. The control register group 201 refers to a large number of VDP registers RGij mapped to an address space of about 1 MB (0 to FFFFFH) on the memory map of the performance control CPU 181, and the performance control CPU 181 of the CPU circuit 171 is configured to execute the WRITE (setting) operation of the operation parameters and the READ operation of the operation status values ​​via the CPUIF unit 212 (see FIG. 15).

[0172] As shown in FIG. 15, the control register group 201 (VDP register RGij) includes a "system control register" in which initial setting values ​​related to system operations such as interrupt operations are written, an "index table register" for determining the AAC area (a) and page area (b) in the built-in VRAM 202 and for constructing or changing the index table IDXTBL, a "data transfer register" in which setting values ​​related to data transfer processing by the data transfer circuit 203 between the performance control CPU 181 and the internal circuit of the VDP circuit 172 are written, and a "data transfer register" in which setting values ​​related to the execution status of the graphics decoder 205 are written. The registers include a "GDEC register" that specifies the operation of the display circuit 208, a "drawing register" to which setting values ​​related to the instruction commands and the drawing circuit 206 are written, a "preloader register" to which setting values ​​related to the operation of the preloader 204 are written, a "display register" to which setting values ​​related to the operation of the display circuit 208 are written, an "LED control register" to which setting values ​​related to the LED controller (SMC unit 211) are written, a "motor control register" to which setting values ​​related to the motor controller (SMC unit 211) are written, and an "audio control register SRG" to which setting values ​​related to the audio circuit SND are written. However, the audio circuit SND is not used in this embodiment.

[0173] In either case, the performance control CPU 181 controls the internal operation of the VDP circuit 172 by writing appropriate setting values ​​to predetermined VDP registers RGij. Specifically, the performance control CPU 181 realizes predetermined image performances based on the display list DL, which is updated at appropriate time intervals, and the setting values ​​to predetermined VDP registers RGij. In this embodiment, the performance control CPU 181 is also responsible for lamp performances and motor performances, so the VDP registers RGij also include LED control registers and motor control registers.

[0174] Next, details of the wiring patterns and the like will be described for the liquid crystal control board 98 and the liquid crystal interface board 97 that make up the performance control unit 95. First, the liquid crystal control board 98 will be described.

[0175] The liquid crystal control substrate 98 has a substrate main body 190 (see FIG. 8) equipped with multiple wiring layers. Specifically, the first wiring layer La1 on the front (first surface) 98a side, the sixth wiring layer La6 on the back (second surface) 98b side, and the second to fifth wiring layers La2 to La5 arranged between them, totaling six wiring layers La1 to La6 (FIGS. 20 to 25). The second wiring layer La2 (FIG. 21) is a solid wiring layer connected to ground, and the fifth wiring layer La5 (FIG. 24) is a solid wiring layer connected to a power supply. The substrate main body 190 of the liquid crystal control substrate 98 has numerous vias (interlayer conductive portions) formed in the thickness direction, and the multiple wiring layers La1 to La6 are electrically connected to each other via these vias (interlayer conductive portions). The vias used in this embodiment are through-hole type vias in which a through-hole is plated, and penetrate from the front surface (first surface) 98a of the substrate body 190 to the back surface (second surface) 98b.

[0176] In the following description, the directions and orientations of the wiring layers La1 to La6 within the plane are shown in the coordinate systems of Figures 20 to 25, with the left-right direction in the figures being the X direction and the up-down direction being the Y direction, with rightward and leftward directions being the +X and -X directions (sides), respectively, and upward and downward directions being the +Y and -Y directions (sides). Diagonal directions are also expressed as diagonal +XY directions and diagonal -XY directions. As is clear from Figures 7 and 8, when the liquid crystal control board 98 is attached to the gaming machine main body 1, the +X direction of the liquid crystal control board 98 faces upward, and the +Y direction faces rightward when facing the gaming machine main body 1 (leftward when viewed from behind).

[0177] As shown in FIG. 20 , the first wiring layer (first wiring layer) La1 on the front surface 98a side is provided with a composite chip placement area (first placement area) 191 where the composite chip (first electronic component) 104 is placed, and a control ROM placement area (second placement area) 192 where the control ROM (second electronic component, specific electronic component) 105 is placed. The composite chip placement area 191 is substantially square in shape corresponding to the shape of the composite chip 104 and is placed near the center of the front surface 98a of the liquid crystal control board 98. Within the composite chip placement area 191, dot-shaped terminal connection portions corresponding to each terminal of the composite chip 104 are arranged in a matrix at approximately equal intervals. The composite chip 104 has a total of 1,020 terminals arranged in 32 rows and 32 columns (with four terminals missing at the four corners) on its bottom surface, and is mounted in the composite chip placement area 191 with each terminal connected to its corresponding terminal connection portion.

[0178] The control ROM placement area 192 is a substantially rectangular shape that is long in the Y direction corresponding to the shape of the ROM socket 193 (see FIG. 8) to which the control ROM 105 is attached, and the length of its long side is approximately the same as the length of one side of the composite chip placement area 191. The control ROM placement area 192 is placed near the +X side of the composite chip placement area 191, and a first edge 192a of first and second edge portions 192a, 192b that are the long sides on the -X and +X sides of the control ROM placement area 192 faces a first edge 191a of first to fourth edge portions 191a to 191d on the +X, -Y, -X, and +Y sides of the composite chip placement area 191 at a predetermined distance and shifted in the -Y direction.

[0179] The control ROM allocation area 192 has a plurality of terminal connection parts (ROM terminal connection parts) (35 on each side in this example) arranged along both long sides, i.e., first and second edges 192a, 192b. A ROM socket 193 that detachably supports the control ROM 105 is fixed to the control ROM allocation area 192, and the control ROM 105 is detachably mounted in the ROM socket 193 (FIG. 8). The control ROM 105 has a plurality of terminals (35 on each side in this example) arranged along both ends, and each of these terminals is connected to each terminal connection part of the control ROM allocation area 192 via the ROM socket 193.

[0180] As shown in FIG. 8 , the ROM socket 193 includes a substantially rectangular bottom wall 193a corresponding to the control ROM placement area 192 and a pair of ROM holders 193b that detachably hold both edges of the control ROM 105 mounted on the bottom wall 193a. The bottom wall 193a is fixed to the surface 98a of the LCD control board 98, covering substantially the entire control ROM placement area 192. Therefore, the wiring pattern (vias, etc.) in the control ROM placement area 192 on the first wiring layer La1 is shielded by the bottom wall (shielding wall) 193a of the ROM socket 193 and cannot be seen from the outside, even when the control ROM 105 is removed from the ROM socket 193. This enhances the prevention of fraudulent acts, such as tampering with the wiring pattern connecting the composite chip 104 and the control ROM 105. Furthermore, by laying the wiring pattern within the control ROM placement area 192, wiring space can be secured in other areas.

[0181] 25, the sixth wiring layer (second wiring layer) La6 on the back surface 98b side is provided with a first connector arrangement region 194 in which the liquid crystal control first connector CN31 is arranged, and a second connector arrangement region 195 in which the liquid crystal control second connector CN32 is arranged. The first connector arrangement region 194 is a substantially rectangular shape that is long in the X direction, and is arranged near the edge on the +Y side of the back surface 98b of the liquid crystal control board 98. In the first connector arrangement region 194, a plurality of terminal connection portions (70 on each side in this example) corresponding to each terminal of the liquid crystal control first connector CN31 are arranged along a pair of long sides. The second connector arrangement region 195 is a substantially rectangular shape that is long in the X direction, and is arranged near the edge on the -Y side of the back surface 98b of the liquid crystal control board 98. In the second connector arrangement region 195, a plurality of terminal connection portions (50 on each side in this example) corresponding to each terminal of the liquid crystal control second connector CN32 are arranged along a pair of long sides.

[0182] Of all the terminals of the composite chip 104, the terminals connected to the control ROM 105 are concentratedly arranged near the first edge 191a on the control ROM 105 side of the composite chip arrangement area 191. Fig. 26 shows the types (terminal information) of some of the terminals near the first edge 191a and the second edge 192b of all the terminals of the composite chip 104. The arrangement of the terminals in Fig. 26 matches the arrangement of the terminal connections in the composite chip arrangement area 191 in Fig. 20.

[0183] In Figure 26(a), HAD0 to HAD25 are address output terminals for outputting address information, HDT0 to HDT15 are data input / output terminals for inputting and outputting data information, HCS0 is a chip select output terminal for outputting a chip select signal, HRD is a read strobe output terminal for outputting a read strobe signal, and HRESET is a system reset terminal for inputting a system reset signal.

[0184] In FIG. 26(b), RA0+ and RA0- are data output terminals corresponding to the differential signal line RA0 on the first transmission path LVDS1 side, RA1+ and RA1- are data output terminals corresponding to the differential signal line RA1 on the first transmission path LVDS1 side, RA2+ and RA2- are data output terminals corresponding to the differential signal line RA2 on the first transmission path LVDS1 side, RA3+ and RA3- are data output terminals corresponding to the differential signal line RA3 on the first transmission path LVDS1 side, and RACLK+ and RACLK- are clock output terminals corresponding to the differential signal line RACLK on the first transmission path LVDS1 side. The output terminals RB0+ and RB0- are data output terminals corresponding to the differential signal line RB0 on ​​the second transmission path LVDS2 side, RB1+ and RB1- are data output terminals corresponding to the differential signal line RB1 on the second transmission path LVDS2 side, RB2+ and RB2- are data output terminals corresponding to the differential signal line RB2 on the second transmission path LVDS2 side, RB3+ and RB3- are data output terminals corresponding to the differential signal line RB3 on the second transmission path LVDS2 side, and RBCLK+ and RBCLK- are clock output terminals corresponding to the differential signal line RBCLK on the second transmission path LVDS2 side.

[0185] In the following description, the symbols HAD0 to HAD25, HDT0 to HDT15, RA1+, RA1-, RBCLK+, RBCLK-, etc. of the corresponding terminals of the composite chip 104 are used as they are for the terminal connection parts in the composite chip placement area 191. For example, the terminal connection part HRD indicates the terminal connection part corresponding to the read strobe output terminal HRD.

[0186] 27 also shows the type (terminal information) of each terminal of the control ROM 105. Of the terminals shown in FIG. 27, A0 to A24 are address input terminals for inputting address information, and Q0 to Q15 are data input / output terminals for inputting and outputting data information, which are connected to the address output terminal and data input / output terminal of the composite chip 104, respectively. CE# is a chip select input terminal for inputting a chip select signal, which is connected to the chip select output terminal of the composite chip 104. WE# is a write enable input terminal, which is connected to a power supply and always kept at H level, making it possible to switch modes depending on the value (H / L) of the OE# terminal. OE# is an output enable input terminal, which is connected to the read strobe output terminal of the composite chip 104.

[0187] RESET# is a reset terminal, and is connected to a power supply voltage monitoring integrated circuit (reset IC) together with the system reset input terminal HRESET of the composite chip 104. WP# / ACC is a write inhibit / program input terminal, and by connecting it to ground (L level) or power supply (H level), it is possible to switch between inhibiting / allowing writing and inhibiting / allowing program execution. In this embodiment, the WP# / ACC terminal is connected to the power supply and set to H level. BYTE# is an 8 / 16-bit mode selection terminal, and by connecting it to ground (L level) or power supply (H level), it is possible to select either 8-bit communication mode or 16-bit communication mode.

[0188] In the following description, the terminal connection parts corresponding to the control ROM allocation area 192 will also use the symbols A0 to A24, Q0 to Q15, CE#, etc. of the corresponding terminals of the control ROM 105. For example, the terminal connection part RESET# indicates the terminal connection part corresponding to the reset terminal RESET#.

[0189] Hereinafter, among the many wiring paths provided on the liquid crystal control board 98, attention will be focused on the multiple types of wiring paths P1 to P71 connecting the composite chip 104 and the control ROM 105, the first liquid crystal control connector CN31, the second liquid crystal control connector CN32, etc., and details thereof will be described with reference to the drawings. Note that Figs. 28 to 33 show only the portions constituting the wiring paths P1 to P71 extracted from the wiring patterns of the first to sixth wiring layers La1 to La6 shown in Figs. 20 to 25, and Figs. 34 to 44 are enlarged views of those portions. Also, Figs. 45 to 53 show schematic diagrams of the wiring routes of the wiring paths P1 to P71. In Figures 45 to 50, vias shown in gray (for example, via v86 in wiring path P1 in Figure 45) indicate vias (specific interlayer conductive parts) arranged within the control ROM placement area 192, and wiring paths shown in thick lines (for example, wiring path cp13 in wiring path P2 in Figure 45) indicate wiring paths connected to the terminal connection part on the control ROM 105 side from inside the control ROM placement area 192.

[0190] First, we will explain the wiring paths P1 to P26 connected to the address output terminals HAD0 to HAD25 of the composite chip 104. In this embodiment, of the address output terminals HAD0 to HAD25, HAD1 to HAD25 are connected to the address input terminals A0 to A24 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31. On the other hand, the address output terminal HAD0 is connected to the liquid crystal control first connector CN31, but is not connected to a terminal on the control ROM 105 side.

[0191] Note that when comparing the arrangement of the address output terminals HAD1 to HAD25 of the composite chip 104 (FIG. 26(a)) with the corresponding arrangement of the address input terminals A0 to A24 of the control ROM 105 (FIG. 27), they are clearly different. That is, the address output terminals HAD1 to HAD25 of the composite chip 104 are arranged in six rows as shown in FIG. 26(a), and the number of columns varies from row to row but the arrangement order is constant, whereas the address input terminals A0 to A24 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and the arrangement order in each column is not regular. Furthermore, the layout positions of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are involved, making the routing of the wiring pattern very complicated. Therefore, it is very important to optimize the routing of the wiring pattern connecting the composite chip 104 and the control ROM 105, which can shorten the line length of the wiring pattern, leading to noise reduction and slimming down of the entire board. This also applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and various electronic components such as connectors. In particular, with regard to the wiring patterns that connect the composite chip 104, such as HAD1 to HAD25 and HDT1 to HDT25, and the control ROM 105, and multiple electronic components such as various connectors, the effects of optimization are significant because the above-mentioned issues are significant.

[0192] Among the wiring paths P1 to P26, in the wiring path P1 (FIG. 45), as shown in FIG. 34, the terminal connection part HAD0 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp0 to a via v0 arranged nearby in the diagonal −XY direction. The via v0 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HAD0) arranged around it. This via v0 is connected to a via v41 by a wiring path cp1 provided in the third wiring layer La3, as shown in FIG. 37. This via v41 is arranged between the composite chip placement area 191 and the control ROM placement area 192. The via v41 is then connected to a via v86 arranged in the control ROM placement area 192 by a wiring path cp2 provided in the fourth wiring layer La4, as shown in FIG. 40. In this way, the wiring path drawn out from the terminal connection part HAD0 in the first wiring layer La1 is connected to the via v86 in the control ROM placement area 192 through the two wiring layers La3 and La4.

[0193] The wiring path extending from the terminal connection portion HAD0 to the via v86 branches into two at the via v86. The first branch path, as shown in FIGS. 37 and 38, is connected from the via v86 to the via v146 in the first connector placement area 194 by a wiring path cp3 provided in the third wiring layer La3 via the via v205 constituting the test point TP28, and is further connected to the terminal connection portion had0 from inside the first connector placement area 194 by a wiring path cp4 provided in the sixth wiring layer La6, as shown in FIG. 42. The second branch path, as shown in FIG. 41, is connected from the via v86 to the termination resistor RA16 by a wiring path cp5 provided in the sixth wiring layer La6. The other end of the termination resistor RA16 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0194] In the wiring path P2 (FIG. 45), as shown in FIG. 34, the terminal connection unit HAD1 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v5 arranged nearby in the diagonal −XY direction by a wiring path cp11. The via v5 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD1) arranged around it. As shown in FIG. 40, this via v5 is connected to a via v85 arranged in the control ROM placement area 192 by a wiring path cp12 provided in the fourth wiring layer La4. In this way, unlike the wiring path drawn from the terminal connection unit HAD0, the wiring path drawn from the terminal connection unit HAD1 does not pass through the third wiring layer La3 but passes through the fourth wiring layer La4 to be connected to the via v85 in the control ROM placement area 192.

[0195] The wiring path that extends from the terminal connection part HAD1 to the via v85 branches into four at the via v85. The first branch path, as shown in Fig. 35, is connected from the via v85 to the terminal connection part A0 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp13 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v85 to the termination resistor RA16 by a wiring path cp14 provided in the sixth wiring layer La6.

[0196] 37 and 38, the third branch path is connected from the via v85 to the via v145 in the first connector placement area 194 by a wiring path cp15 provided in the third wiring layer La3, and further connected to the terminal connection portion had1 from the inside of the first connector placement area 194 by a wiring path cp16 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v85 to the via v182 by a wiring path cp17 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC12 constituting the decoding circuit by a wiring path cp18 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0197] Although some parts are omitted in the wiring diagrams of Figures 43 and the like, the decoding circuit including decoders IC12 to IC14 is configured as shown in Figure 54. As shown in Figure 54, decoders IC13 and IC14 are connected to the liquid crystal display means 76 and the like via the liquid crystal IF third connector CN23 and the like, and when power is turned on, data information is input from the data input / output terminals HDT0 to HDT15 of the combined chip 104. Then, decoders IC13 and IC14 output data information to the liquid crystal display means 76 and the like based on a clock synchronized with the CPU input from decoder IC12, so that the CPU does not need to transmit fixed data information every time. This eliminates the need for the CPU to output the same data information at predetermined time intervals, and the CPU only needs to transmit new data information when the content of the data information is to be changed, thereby simplifying the control program.

[0198] In the wiring path P3 (FIG. 45), as shown in FIG. 34, the terminal connection part HAD2 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v4 arranged nearby in the diagonal +XY direction by a wiring path cp21. The via v4 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HAD2) arranged around it. This via v4 is connected to a via v84 arranged in the control ROM placement area 192 by a wiring path cp22 provided in the fourth wiring layer La4, as shown in FIG.

[0199] The wiring path that reaches the terminal connection part HAD2 to the via v84 branches into four at the via v84. The first branch path is connected from the via v84 to the terminal connection part A1 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp23 provided in the first wiring layer La1, as shown in Fig. 35. The second branch path is connected from the via v84 to the termination resistor RA16 by a wiring path cp24 provided in the sixth wiring layer La6, as shown in Fig. 41.

[0200] 37 and 38, the third branch path is connected from the via v84 to the via v144 in the first connector placement area 194 by a wiring path cp25 provided in the third wiring layer La3, and further connected to the terminal connection portion had2 from inside the first connector placement area 194 by a wiring path cp26 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v84 to the via v184 by a wiring path cp27 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC12 constituting the decoding circuit by a wiring path cp28 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0201] In the wiring path P4 (FIG. 45), as shown in FIG. 34, the terminal connection unit HAD3 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v13 arranged nearby in the diagonal +XY direction by a wiring path cp31. The via v13 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD3) arranged around it. This via v13 is connected to a via v83 arranged in the control ROM placement area 192 by a wiring path cp32 provided in the fourth wiring layer La4, as shown in FIG.

[0202] The wiring path that extends from the terminal connection part HAD3 to the via v83 branches into four at the via v83. The first branch path, as shown in Fig. 35, is connected from the via v83 to the terminal connection part A2 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp33 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v83 to the termination resistor RA16 by a wiring path cp34 provided in the sixth wiring layer La6.

[0203] 37 and 38, the third branch path is connected from the via v83 to the via v143 in the first connector placement area 194 by a wiring path cp35 provided in the third wiring layer La3, and further connected to the terminal connection part had3 from the inside of the first connector placement area 194 by a wiring path cp36 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v83 to the via v181 by a wiring path cp37 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC12 constituting the decoding circuit by a wiring path cp38 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0204] In the wiring path P5 (FIG. 45), as shown in FIG. 34, the terminal connection part HAD4 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v20 arranged nearby in the diagonal +XY direction by a wiring path cp41. The via v20 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HAD4) arranged around it. This via v20 is connected to a via v82 arranged in the control ROM placement area 192 by a wiring path cp42 provided in the fourth wiring layer La4, as shown in FIG.

[0205] The wiring path that extends from the terminal connection portion HAD4 to the via v82 branches into three at the via v82. As shown in FIG. 35, the first branch path is connected from the via v82 to the terminal connection portion A3 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp43 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v82 to the termination resistor RA15 by a wiring path cp44 provided in the sixth wiring layer La6. The other end of this termination resistor RA15 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0206] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v82 to the via v142 in the first connector placement area 194 by a wiring path cp45 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had4 from inside the first connector placement area 194 by a wiring path cp46 provided in the sixth wiring layer La6.

[0207] In the wiring path P6 (FIG. 45), as shown in FIG. 34, the terminal connection unit HAD5 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp51 to a via v34 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HAD5 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v34 is connected to a via v81 arranged in the control ROM placement area 192 by a wiring path cp52 provided in the fourth wiring layer La4.

[0208] The wiring path that extends from the terminal connection part HAD5 to the via v81 branches into three at the via v81. As shown in Fig. 35, the first branch path is connected from the via v81 to the terminal connection part A4 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp53 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v81 to the termination resistor RA15 by a wiring path cp54 provided in the sixth wiring layer La6.

[0209] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v81 to the via v141 in the first connector placement area 194 by a wiring path cp55 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had5 from inside the first connector placement area 194 by a wiring path cp56 provided in the sixth wiring layer La6.

[0210] In the wiring path P7 (FIG. 45), as shown in FIG. 34, the terminal connection unit HAD6 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp61 to a via v39 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HAD6 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v39 is connected to a via v80 arranged in the control ROM placement area 192 by a wiring path cp62 provided in the fourth wiring layer La4.

[0211] The wiring path that extends from the terminal connection part HAD6 to the via v80 branches into three at the via v80. As shown in Fig. 35, the first branch path is connected from the via v80 to the terminal connection part A5 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp63 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v80 to the termination resistor RA15 by a wiring path cp64 provided in the sixth wiring layer La6.

[0212] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v80 to the via v140 in the first connector placement area 194 by a wiring path cp65 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had6 from inside the first connector placement area 194 by a wiring path cp66 provided in the sixth wiring layer La6.

[0213] In the wiring path P8 (FIG. 45), as shown in FIG. 34, the terminal connection part HAD7 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v3 arranged nearby in the diagonal +XY direction by a wiring path cp71. The via v3 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HAD7) arranged around it. This via v3 is connected to a via v79 arranged in the control ROM placement area 192 by a wiring path cp72 provided in the fourth wiring layer La4, as shown in FIG.

[0214] The wiring path that extends from the terminal connection part HAD7 to the via v79 branches into three at the via v79. The first branch path, as shown in Fig. 35, is connected from the via v79 to the terminal connection part A6 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp73 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v79 to the termination resistor RA15 by a wiring path cp74 provided in the sixth wiring layer La6.

[0215] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v79 to the via v139 in the first connector placement area 194 by a wiring path cp75 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had7 from inside the first connector placement area 194 by a wiring path cp76 provided in the sixth wiring layer La6.

[0216] In the wiring path P9 (FIG. 46), as shown in FIG. 34, the terminal connection part HAD8 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v12 arranged nearby in the diagonal +XY direction by a wiring path cp81. The via v12 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HAD8) arranged around it. This via v12 is connected to a via v78 arranged in the control ROM placement area 192 by a wiring path cp82 provided in the fourth wiring layer La4, as shown in FIG.

[0217] The wiring path extending from the terminal connection portion HAD8 to the via v78 branches into three at the via v78. As shown in FIG. 35, the first branch path is connected from the via v78 to the terminal connection portion A7 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp83 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v78 to the termination resistor RA13 by a wiring path cp84 provided in the sixth wiring layer La6. The other end of the termination resistor RA13 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0218] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v78 to the via v138 in the first connector placement area 194 by a wiring path cp85 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had8 from inside the first connector placement area 194 by a wiring path cp86 provided in the sixth wiring layer La6.

[0219] In the wiring path P10 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD9 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp91 to a via v33 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HAD9 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v33 is connected to a via v77 arranged in the control ROM placement area 192 by a wiring path cp92 provided in the fourth wiring layer La4.

[0220] The wiring path that extends from the terminal connection part HAD9 to the via v77 branches into three at the via v77. The first branch path, as shown in Fig. 35, is connected from the via v77 to the terminal connection part A8 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp93 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v77 to the termination resistor RA13 by a wiring path cp94 provided in the sixth wiring layer La6.

[0221] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v77 to the via v137 in the first connector placement area 194 by a wiring path cp95 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had9 from inside the first connector placement area 194 by a wiring path cp96 provided in the sixth wiring layer La6.

[0222] In the wiring path P11 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD10 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp101 to a via v38 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HAD10 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v38 is connected to a via v76 arranged in the control ROM placement area 192 by a wiring path cp102 provided in the fourth wiring layer La4.

[0223] The wiring path that extends from the terminal connection part HAD10 to the via v76 branches into three at the via v76. The first branch path, as shown in Fig. 35, is connected from the via v76 to the terminal connection part A9 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp103 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v76 to the termination resistor RA13 by a wiring path cp104 provided in the sixth wiring layer La6.

[0224] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v76 to the via v136 in the first connector placement area 194 by a wiring path cp105 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had10 from inside the first connector placement area 194 by a wiring path cp106 provided in the sixth wiring layer La6.

[0225] In the wiring path P12 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD11 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v2 arranged nearby in the diagonal −X+Y direction by a wiring path cp111. The via v2 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD11) arranged around it. This via v2 is connected to a via v75 arranged in the control ROM placement area 192 by a wiring path cp112 provided in the fourth wiring layer La4, as shown in FIG.

[0226] The wiring path that extends from the terminal connection part HAD11 to the via v75 branches into three at the via v75. The first branch path, as shown in Fig. 35, is connected from the via v75 to the terminal connection part A10 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp113 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v75 to the termination resistor RA13 by a wiring path cp114 provided in the sixth wiring layer La6.

[0227] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v75 to the via v135 in the first connector placement area 194 by a wiring path cp115 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had11 from inside the first connector placement area 194 by a wiring path cp116 provided in the sixth wiring layer La6.

[0228] In the wiring path P13 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD12 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v19 arranged nearby in the diagonal +XY direction by a wiring path cp121. The via v19 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD12) arranged around it. This via v19 is connected to a via v74 arranged in the control ROM placement area 192 by a wiring path cp122 provided in the fourth wiring layer La4, as shown in FIG.

[0229] The wiring path extending from the terminal connection unit HAD12 to the via v74 branches into three at the via v74. As shown in FIG. 35, the first branch path is connected from the via v74 to the terminal connection unit A11 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp123 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v74 to the termination resistor RA11 by a wiring path cp124 provided in the sixth wiring layer La6. The other end of the termination resistor RA11 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0230] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v74 to the via v134 in the first connector placement area 194 by a wiring path cp125 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had12 from inside the first connector placement area 194 by a wiring path cp126 provided in the sixth wiring layer La6.

[0231] In the wiring path P14 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD13 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp131 to a via v49 arranged outside the composite chip placement area 191, specifically, on the +Y side of the control ROM placement area 192. The terminal connection unit HAD13 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v49 is connected to a via v73 arranged in the control ROM placement area 192 by a wiring path cp132 provided in the fourth wiring layer La4.

[0232] The wiring path that extends from the terminal connection part HAD13 to the via v73 branches into two at the via v73. The first branch path is connected from the via v73 to the termination resistor RA11 by a wiring path cp133 provided in the sixth wiring layer La6, as shown in FIG.

[0233] 37, the second branch path is connected from the via v73 to the via v107 arranged in the control ROM placement area 192 by a wiring path cp134 provided in the third wiring layer La3, and further branches into two at this point. The first branch path, 2a, is connected from the via v107 to the terminal connection portion A12 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp135 provided in the first wiring layer La1, as shown in FIG. 35. The second branch path, 2b, is connected from the via v107 to the via v133 in the first connector placement area 194 by a wiring path cp136 provided in the third wiring layer La3, as shown in FIG. 42, and is further connected to the terminal connection portion had13 from inside the first connector placement area 194 by a wiring path cp137 provided in the sixth wiring layer La6.

[0234] In the wiring path P15 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD14 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp141 to a via v50 arranged outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection unit HAD14 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v50 is connected to a via v72 arranged in the control ROM placement area 192 by a wiring path cp142 provided in the fourth wiring layer La4.

[0235] The wiring path that extends from the terminal connection part HAD14 to the via v72 branches into two at the via v72. The first branch path is connected from the via v72 to the termination resistor RA11 by a wiring path cp143 provided in the sixth wiring layer La6, as shown in FIG.

[0236] 37, the second branch path is connected from the via v72 to a via v106 arranged in the control ROM placement area 192 by a wiring path cp144 provided in the third wiring layer La3, and further branches into two at this point. The first branch path, 2a, is connected from the via v106 to the terminal connection portion A13 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp145 provided in the first wiring layer La1, as shown in FIG. 35. The second branch path, 2b, is connected from the via v106 to the via v132 in the first connector placement area 194 by a wiring path cp146 provided in the third wiring layer La3, as shown in FIG. 42, and is further connected to the terminal connection portion had14 from inside the first connector placement area 194 by a wiring path cp147 provided in the sixth wiring layer La6.

[0237] In the wiring path P16 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD15 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v11 arranged nearby in the diagonal +XY direction by a wiring path cp151. The via v11 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD15) arranged around it. This via v11 is connected to a via v71 arranged in the control ROM placement area 192 by a wiring path cp152 provided in the fourth wiring layer La4, as shown in FIG.

[0238] The wiring path that extends from the terminal connection part HAD15 to the via v71 branches into two at the via v71. The first branch path is connected from the via v71 to the termination resistor RA11 by a wiring path cp153 provided in the sixth wiring layer La6, as shown in FIG.

[0239] 37, the second branch path is connected from the via v71 to a via v105 arranged in the control ROM placement area 192 by a wiring path cp154 provided in the third wiring layer La3, and further branches into two at this point. The first branch path, 2a, is connected from the via v105 to the terminal connection portion A14 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp155 provided in the first wiring layer La1, as shown in FIG. 35. The second branch path, 2b, is connected from the via v105 to the via v131 in the first connector placement area 194 by a wiring path cp156 provided in the third wiring layer La3, as shown in FIG. 42, and is further connected to the terminal connection portion had15 from inside the first connector placement area 194 by a wiring path cp157 provided in the sixth wiring layer La6.

[0240] In the wiring path P17 (FIG. 46), as shown in FIG. 34, the terminal connection unit HAD16 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v18 arranged nearby in the diagonal +XY direction by a wiring path cp161. The via v18 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD16) arranged around it. This via v18 is connected to a via v70 arranged in the control ROM placement area 192 by a wiring path cp162 provided in the fourth wiring layer La4, as shown in FIG.

[0241] The wiring path that extends from the terminal connection unit HAD16 to the via v70 branches into two at the via v70. The first branch path is connected from the via v70 to the termination resistor RA10 by a wiring path cp163 provided in the sixth wiring layer La6, as shown in Fig. 41. The other end of the termination resistor RA10 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0242] 37, the second branch path is connected from the via v70 to a via v104 arranged in the control ROM placement area 192 by a wiring path cp164 provided in the third wiring layer La3, and further branches into two at this point. The first branch path, 2a, is connected from the via v104 to the terminal connection portion A15 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp165 provided in the first wiring layer La1, as shown in FIG. 35. The second branch path, 2b, is connected from the via v104 to the via v130 in the first connector placement area 194 by a wiring path cp166 provided in the third wiring layer La3, as shown in FIG. 42, and is further connected to the terminal connection portion had16 from inside the first connector placement area 194 by a wiring path cp167 provided in the sixth wiring layer La6.

[0243] In the wiring path P18 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD17 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp171 to a via v51 arranged outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection unit HAD17 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v51 is connected to a via v69 arranged in the control ROM placement area 192 by a wiring path cp172 provided in the fourth wiring layer La4.

[0244] The wiring path that extends from the terminal connection part HAD17 to the via v69 branches into two at the via v69. The first branch path is connected from the via v69 to the termination resistor RA10 by a wiring path cp173 provided in the sixth wiring layer La6, as shown in FIG.

[0245] 37, the second branch path is connected from the via v69 to the via v103 arranged in the control ROM placement area 192 by a wiring path cp174 provided in the third wiring layer La3, and further branches into two at this point. The first branch path, 2a, is connected from the via v103 to the terminal connection portion A16 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp175 provided in the first wiring layer La1, as shown in FIG. 35. The second branch path, 2b, is connected from the via v103 to the via v129 in the first connector placement area 194 by a wiring path cp176 provided in the third wiring layer La3, as shown in FIG. 42, and is further connected to the terminal connection portion had17 from inside the first connector placement area 194 by a wiring path cp177 provided in the sixth wiring layer La6.

[0246] In the wiring path P19 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD18 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp181 to a via v52 arranged outside the composite chip placement area 191, specifically, on the +Y side of the control ROM placement area 192. The terminal connection unit HAD18 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v52 is connected to a via v68 arranged in the control ROM placement area 192 by a wiring path cp182 provided in the fourth wiring layer La4.

[0247] The wiring path that extends from the terminal connection part HAD18 to the via v68 branches into three at the via v68. The first branch path, as shown in Fig. 35, is connected from the via v68 to the terminal connection part A17 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp183 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v68 to the termination resistor RA10 by a wiring path cp184 provided in the sixth wiring layer La6.

[0248] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v68 to the via v128 in the first connector placement area 194 by a wiring path cp185 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had18 from inside the first connector placement area 194 by a wiring path cp186 provided in the sixth wiring layer La6.

[0249] In the wiring path P20 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD19 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v1 arranged nearby in the diagonal +XY direction by a wiring path cp191. The via v1 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD19) arranged around it. This via v1 is connected to a via v67 arranged in the control ROM placement area 192 by a wiring path cp192 provided in the fourth wiring layer La4, as shown in FIG.

[0250] The wiring path that extends from the terminal connection part HAD19 to the via v67 branches into three at the via v67. The first branch path, as shown in Fig. 35, is connected from the via v67 to the terminal connection part A18 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp193 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v67 to the termination resistor RA10 by a wiring path cp194 provided in the sixth wiring layer La6.

[0251] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v67 to the via v127 in the first connector placement area 194 by a wiring path cp195 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had19 from inside the first connector placement area 194 by a wiring path cp196 provided in the sixth wiring layer La6.

[0252] In the wiring path P21 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD20 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v10 arranged nearby in the diagonal +XY direction by a wiring path cp201. The via v10 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD20) arranged around it. This via v10 is connected to a via v66 arranged in the control ROM placement area 192 by a wiring path cp202 provided in the fourth wiring layer La4, as shown in FIG.

[0253] The wiring path that extends from the terminal connection unit HAD20 to the via v66 branches into three at the via v66. The first branch path, as shown in FIG. 35, is connected from the via v66 to the terminal connection unit A19 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp203 provided in the first wiring layer La1. The second branch path, as shown in FIG. 41, is connected from the via v66 to the termination resistor RA9 by a wiring path cp204 provided in the sixth wiring layer La6. The other end of this termination resistor RA9 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0254] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v66 to the via v126 in the first connector placement area 194 by a wiring path cp205 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had20 from inside the first connector placement area 194 by a wiring path cp206 provided in the sixth wiring layer La6.

[0255] In the wiring path P22 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection unit HAD21 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp211 to a via v54 arranged outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection unit HAD21 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v54 is connected to a via v65 arranged in the control ROM placement area 192 by a wiring path cp212 provided in the fourth wiring layer La4.

[0256] The wiring path that extends from the terminal connection part HAD21 to the via v65 branches into three at the via v65. The first branch path, as shown in Fig. 35, is connected from the via v65 to the terminal connection part A20 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp213 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v65 to the termination resistor RA9 by a wiring path cp214 provided in the sixth wiring layer La6.

[0257] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v65 to the via v125 in the first connector placement area 194 by a wiring path cp215 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had21 from inside the first connector placement area 194 by a wiring path cp216 provided in the sixth wiring layer La6.

[0258] In the wiring path P23 (FIG. 47), as shown in FIGS. 34 and 35, the terminal connection unit HAD22 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp221 to a via v53 arranged outside the composite chip placement area 191, specifically on the +Y side of the control ROM placement area 192. The terminal connection unit HAD22 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v53 is connected to a via v64 arranged in the control ROM placement area 192 by a wiring path cp222 provided in the fourth wiring layer La4.

[0259] The wiring path that extends from the terminal connection part HAD22 to the via v64 branches into three at the via v64. The first branch path, as shown in Fig. 35, is connected from the via v64 to the terminal connection part A21 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp223 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v64 to the termination resistor RA9 by a wiring path cp224 provided in the sixth wiring layer La6.

[0260] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v64 to the via v124 in the first connector placement area 194 by a wiring path cp225 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had22 from inside the first connector placement area 194 by a wiring path cp226 provided in the sixth wiring layer La6.

[0261] In the wiring path P24 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD23 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp231 to a via v21 arranged nearby in the diagonal +X+Y direction. The via v21 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD23) arranged around it. As shown in FIG. 40, this via v21 is connected by a wiring path cp232 provided in the fourth wiring layer La4 to a via v36 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192, and further connected to a via v63 arranged in the control ROM placement area 192 by a wiring path cp233 provided in the first wiring layer La1, as shown in FIGS.

[0262] The wiring path that extends from the terminal connection part HAD23 to the via v63 branches into three at the via v63. The first branch path, as shown in Fig. 35, is connected from the via v63 to the terminal connection part A22 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp234 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v63 to the termination resistor RA9 by a wiring path cp235 provided in the sixth wiring layer La6.

[0263] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v63 to the via v123 in the first connector placement area 194 by a wiring path cp236 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had23 from inside the first connector placement area 194 by a wiring path cp237 provided in the sixth wiring layer La6.

[0264] In the wiring path P25 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD24 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp241 to a via v14 arranged nearby in the diagonal +X+Y direction. The via v14 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD24) arranged around it. As shown in FIG. 40, this via v14 is connected by a wiring path cp242 provided in the fourth wiring layer La4 to a via v35 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192, and further connected to a via v62 arranged in the control ROM placement area 192 by a wiring path cp243 provided in the first wiring layer La1, as shown in FIGS.

[0265] The wiring path that extends from the terminal connection unit HAD24 to the via v62 branches into four at the via v62. As shown in FIG. 35, the first branch path is connected from the via v62 to the terminal connection unit A23 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp244 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v62 to the termination resistor R45 by a wiring path cp245 provided in the sixth wiring layer La6. The other end of the termination resistor R45 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0266] 37 and 38, the third branch path is connected from the via v62 to the via v122 in the first connector placement area 194 by a wiring path cp246 provided in the third wiring layer La3, and further connected to the terminal connection part had24 from inside the first connector placement area 194 by a wiring path cp247 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v62 to the via v183 by a wiring path cp248 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC12 constituting the decoding circuit by a wiring path cp249 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0267] In the wiring path P26 (FIG. 47), as shown in FIG. 34, the terminal connection unit HAD25 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp251 to a via v6 arranged nearby in the diagonal +X+Y direction. The via v6 is arranged approximately in the center of the four terminal connection units (including the terminal connection unit HAD25) arranged around it. As shown in FIG. 40, this via v6 is connected by a wiring path cp252 provided in the fourth wiring layer La4 to a via v40 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192, and further connected to a via v61 arranged in the control ROM placement area 192 by a wiring path cp253 provided in the first wiring layer La1, as shown in FIGS.

[0268] The wiring path extending from the terminal connection portion HAD25 to the via v61 branches into three at the via v61. As shown in FIG. 35, the first branch path is connected from the via v61 to the terminal connection portion A24 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp254 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v61 to the termination resistor R44 by a wiring path cp255 provided in the sixth wiring layer La6. The other end of the termination resistor R44 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0269] Furthermore, as shown in Figures 37 and 38, the third branch path is connected from the via v61 to the via v121 in the first connector placement area 194 by a wiring path cp256 provided in the third wiring layer La3, and further, as shown in Figure 42, is connected to the terminal connection portion had25 from inside the first connector placement area 194 by a wiring path cp257 provided in the sixth wiring layer La6.

[0270] Next, we will explain the wiring paths P27 to P42 connected to the data input / output terminals HDT0 to HDT15 of the composite chip 104. The data input / output terminals HDT0 to HDT15 are connected to the data input / output terminals Q0 to Q15 on the control ROM 105 side, respectively, and are also connected to the liquid crystal control first connector CN31.

[0271] Note that, when comparing the arrangement of the data input / output terminals HDT0 to HDT15 of the composite chip 104 (FIG. 26(a)) with the corresponding arrangement of the data input / output terminals Q0 to Q15 of the control ROM 105 (FIG. 27), the two are clearly different. That is, the data input / output terminals HDT0 to HDT15 of the composite chip 104 are arranged in four rows as shown in FIG. 26(a), and the number of columns varies from row to row but the arrangement order is constant, whereas the data input / output terminals Q0 to Q15 of the control ROM 105 are arranged in two columns as shown in FIG. 27, and the arrangement order in each column is not regular. Furthermore, the layout positions of the composite chip 104 and the control ROM 105 and the large number of wiring patterns are involved, making the routing of the wiring patterns very complicated. Therefore, it is very important to optimize the routing of the wiring patterns connecting the composite chip 104 and the control ROM 105, which can shorten the line length of the wiring patterns, leading to noise reduction and a slimmer board. This also applies not only to the relationship between the composite chip 104 and the control ROM 105, but also to the relationship between the composite chip 104 and various electronic components such as connectors. In particular, with regard to the wiring patterns that connect the composite chip 104, such as HAD1 to HAD25 and HDT1 to HDT25, and the control ROM 105, and multiple electronic components such as various connectors, the effects of optimization are significant because the above-mentioned issues are significant.

[0272] Of the wiring paths P27 to P42, in the wiring path P27 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT0 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp301 to a via v32 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT0 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v32 is connected to a via v102 arranged in the control ROM placement area 192 by a wiring path cp302 provided in the fourth wiring layer La4.

[0273] The wiring path that extends from the terminal connection portion HDT0 to the via v102 branches into four at the via v102. As shown in FIG. 35, the first branch path is connected from the via v102 to the terminal connection portion Q0 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp303 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v102 to the termination resistor RA34 by a wiring path cp304 provided in the sixth wiring layer La6. The other end of the termination resistor RA34 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0274] 37 and 38, the third branch path is connected from the via v102 to the via v162 in the first connector placement area 194 by a wiring path cp305 provided in the third wiring layer La3, and further connected to the terminal connection portion hdt0 from inside the first connector placement area 194 by a wiring path cp306 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v102 to the via v197 by a wiring path cp307 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp308 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0275] In the wiring path P28 (FIG. 48), as shown in FIG. 34, the terminal connection unit HDT1 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp311 to a via v31 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HDT1 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v31 is connected to a via v101 arranged in the control ROM placement area 192 by a wiring path cp312 provided in the fourth wiring layer La4.

[0276] The wiring path that extends from the terminal connection part HDT1 to the via v101 branches into four at the via v101. As shown in Fig. 35, the first branch path is connected from the via v101 to the terminal connection part Q1 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp313 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v101 to the termination resistor RA34 by a wiring path cp314 provided in the sixth wiring layer La6.

[0277] 37 and 38, the third branch path is connected from the via v101 to the via v161 in the first connector placement area 194 by a wiring path cp315 provided in the third wiring layer La3, and further connected to the terminal connection portion hdt1 from inside the first connector placement area 194 by a wiring path cp316 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v101 to the via v198 by a wiring path cp317 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp318 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0278] In the wiring path P29 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT2 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v24 arranged nearby in the diagonal +X+Y direction by a wiring path cp321. The via v24 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT2) arranged around it. This via v24 is connected to a via v100 arranged in the control ROM placement area 192 by a wiring path cp322 provided in the fourth wiring layer La4, as shown in FIG.

[0279] The wiring path that reaches the terminal connection part HDT2 to the via v100 branches into four at the via v100. As shown in Fig. 35, the first branch path is connected from the via v100 to the terminal connection part Q2 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp323 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v100 to the termination resistor RA34 by a wiring path cp324 provided in the sixth wiring layer La6.

[0280] 37 and 38, the third branch path is connected from the via v100 to the via v160 in the first connector placement area 194 by a wiring path cp325 provided in the third wiring layer La3, and further connected to the terminal connection portion hdt2 from inside the first connector placement area 194 by a wiring path cp326 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v100 to the via v199 by a wiring path cp327 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp328 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0281] In the wiring path P30 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT3 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v8 arranged nearby in the diagonal −XY direction by a wiring path cp331. The via v8 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT3) arranged around it. This via v8 is connected to a via v99 arranged in the control ROM placement area 192 by a wiring path cp332 provided in the fourth wiring layer La4, as shown in FIG.

[0282] The wiring path that reaches the terminal connection part HDT3 and the via v99 branches into four at the via v99. As shown in Fig. 35, the first branch path is connected from the via v99 to the terminal connection part Q3 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp333 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v99 to the termination resistor RA34 by a wiring path cp334 provided in the sixth wiring layer La6.

[0283] 37 and 38, the third branch path is connected from the via v99 to the via v159 in the first connector placement area 194 by a wiring path cp335 provided in the third wiring layer La3, and further connected to the terminal connection part hdt3 from inside the first connector placement area 194 by a wiring path cp336 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v99 to the via v200 by a wiring path cp337 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp338 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0284] In the wiring path P31 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT4 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp341 to a via v37 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT4 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v37 is connected to a via v98 arranged in the control ROM placement area 192 by a wiring path cp342 provided in the fourth wiring layer La4.

[0285] The wiring path that extends from the terminal connection part HDT4 to the via v98 branches into four at the via v98. As shown in FIG. 35, the first branch path is connected from the via v98 to the terminal connection part Q4 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp343 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v98 to the termination resistor RA32 by a wiring path cp344 provided in the sixth wiring layer La6. The other end of the termination resistor RA32 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0286] 37 and 38, the third branch path is connected from the via v98 to the via v158 in the first connector placement area 194 by a wiring path cp345 provided in the third wiring layer La3, and further connected to the terminal connection part hdt4 from inside the first connector placement area 194 by a wiring path cp346 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v98 to the via v189 by a wiring path cp347 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp348 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0287] In the wiring path P32 (FIG. 48), as shown in FIG. 34, the terminal connection unit HDT5 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp351 to a via v46 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HDT5 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v46 is connected to a via v97 arranged in the control ROM placement area 192 by a wiring path cp352 provided in the fourth wiring layer La4.

[0288] The wiring path that reaches the terminal connection part HDT5 and the via v97 branches into four at the via v97. As shown in Fig. 35, the first branch path is connected from the via v97 to the terminal connection part Q5 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp353 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v97 to the termination resistor RA32 by a wiring path cp354 provided in the sixth wiring layer La6.

[0289] 37 and 38, the third branch path is connected from the via v97 to the via v157 in the first connector placement area 194 by a wiring path cp355 provided in the third wiring layer La3, and further connected to the terminal connection part hdt5 from inside the first connector placement area 194 by a wiring path cp356 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v97 to the via v190 by a wiring path cp357 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp358 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0290] In the wiring path P33 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT6 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v17 arranged nearby in the diagonal +X+Y direction by a wiring path cp361. The via v17 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT6) arranged around it. This via v17 is connected to a via v96 arranged in the control ROM placement area 192 by a wiring path cp362 provided in the fourth wiring layer La4, as shown in FIG.

[0291] The wiring path that reaches the terminal connection part HDT6 and the via v96 branches into four at the via v96. The first branch path is connected from the via v96 to the terminal connection part Q6 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp363 provided in the first wiring layer La1, as shown in Fig. 35. The second branch path is connected from the via v96 to the termination resistor RA32 by a wiring path cp364 provided in the sixth wiring layer La6, as shown in Fig. 41.

[0292] 37 and 38, the third branch path is connected from the via v96 to the via v156 in the first connector placement area 194 by a wiring path cp365 provided in the third wiring layer La3, and further connected to the terminal connection part hdt6 from inside the first connector placement area 194 by a wiring path cp366 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v96 to the via v195 by a wiring path cp367 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp368 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0293] In the wiring path P34 (FIG. 48), as shown in FIG. 34, the terminal connection part HDT7 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp371 to a via v45 arranged outside the composite chip placement area 191, specifically, between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection part HDT7 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v45 is connected to a via v95 arranged in the control ROM placement area 192 by a wiring path cp372 provided in the fourth wiring layer La4.

[0294] The wiring path that extends from the terminal connection part HDT7 to the via v95 branches into four at the via v95. The first branch path, as shown in Fig. 35, is connected from the via v95 to the terminal connection part Q7 of the control ROM 105 from outside the control ROM placement area 192 by a wiring path cp373 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v95 to the termination resistor RA32 by a wiring path cp374 provided in the sixth wiring layer La6.

[0295] 37 and 38, the third branch path is connected from the via v95 to the via v155 in the first connector placement area 194 by a wiring path cp375 provided in the third wiring layer La3, and further connected to the terminal connection part hdt7 from inside the first connector placement area 194 by a wiring path cp376 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v95 to the via v196 by a wiring path cp377 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC13 constituting the decoding circuit by a wiring path cp378 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0296] In the wiring path P35 (FIG. 49), as shown in FIG. 34, the terminal connection unit HDT8 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp381 to a via v44 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HDT8 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v44 is connected to a via v94 arranged in the control ROM placement area 192 by a wiring path cp382 provided in the fourth wiring layer La4.

[0297] The wiring path extending from the terminal connection portion HDT8 to the via v94 branches into four at the via v94. As shown in FIG. 35, the first branch path is connected from the via v94 to the terminal connection portion Q8 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp383 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v94 to the termination resistor RA30 by a wiring path cp384 provided in the sixth wiring layer La6. The other end of the termination resistor RA30 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0298] 37 and 38, the third branch path is connected from the via v94 to the via v154 in the first connector placement area 194 by a wiring path cp385 provided in the third wiring layer La3, and further connected to the terminal connection part hdt8 from inside the first connector placement area 194 by a wiring path cp386 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v94 to the via v191 by a wiring path cp387 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp388 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0299] In the wiring path P36 (FIG. 49), as shown in FIG. 34, the terminal connection part HDT9 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v23 arranged nearby in the diagonal +X+Y direction by a wiring path cp391. The via v23 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT9) arranged around it. This via v23 is connected to a via v93 arranged in the control ROM placement area 192 by a wiring path cp392 provided in the fourth wiring layer La4, as shown in FIG.

[0300] The wiring path that extends from the terminal connection part HDT9 to the via v93 branches into four at the via v93. The first branch path, as shown in Fig. 35, is connected from the via v93 to the terminal connection part Q9 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp393 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v93 to the termination resistor RA30 by a wiring path cp394 provided in the sixth wiring layer La6.

[0301] 37 and 38, the third branch path is connected from the via v93 to the via v153 in the first connector placement area 194 by a wiring path cp395 provided in the third wiring layer La3, and further connected to the terminal connection part hdt9 from inside the first connector placement area 194 by a wiring path cp396 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v93 to the via v192 by a wiring path cp397 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp398 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0302] In the wiring path P37 (FIG. 49), as shown in FIG. 34, the terminal connection part HDT10 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v16 arranged nearby in the diagonal +X+Y direction by a wiring path cp401. The via v16 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT10) arranged around it. This via v16 is connected to a via v92 arranged in the control ROM placement area 192 by a wiring path cp402 provided in the fourth wiring layer La4, as shown in FIG.

[0303] The wiring path that reaches the terminal connection part HDT10 and the via v92 branches into four at the via v92. As shown in Fig. 35, the first branch path is connected from the via v92 to the terminal connection part Q10 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp403 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v92 to the termination resistor RA30 by a wiring path cp404 provided in the sixth wiring layer La6.

[0304] 37 and 38, the third branch path is connected from the via v92 to the via v152 in the first connector placement area 194 by a wiring path cp405 provided in the third wiring layer La3, and further connected to the terminal connection part hdt10 from inside the first connector placement area 194 by a wiring path cp406 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v92 to the via v193 by a wiring path cp407 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp408 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0305] In the wiring path P38 (FIG. 49), as shown in FIG. 34, the terminal connection part HDT11 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v7 arranged nearby in the diagonal +X+Y direction by a wiring path cp411. The via v7 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT11) arranged around it. This via v7 is connected to a via v91 arranged in the control ROM placement area 192 by a wiring path cp412 provided in the fourth wiring layer La4, as shown in FIG.

[0306] The wiring path that extends from the terminal connection part HDT11 to the via v91 branches into four at the via v91. As shown in Fig. 35, the first branch path is connected from the via v91 to the terminal connection part Q11 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp413 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v91 to the termination resistor RA30 by a wiring path cp414 provided in the sixth wiring layer La6.

[0307] 37 and 38, the third branch path is connected from the via v91 to the via v151 in the first connector placement area 194 by a wiring path cp415 provided in the third wiring layer La3, and further connected to the terminal connection part hdt11 from inside the first connector placement area 194 by a wiring path cp416 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v91 to the via v194 by a wiring path cp417 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp418 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0308] In the wiring path P39 (FIG. 49), as shown in FIG. 34, the terminal connection unit HDT12 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp421 to a via v43 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HDT12 is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 40, the via v43 is connected to a via v90 arranged in the control ROM placement area 192 by a wiring path cp422 provided in the fourth wiring layer La4.

[0309] The wiring path that reaches the terminal connection part HDT12 and the via v90 branches into four at the via v90. As shown in FIG. 35, the first branch path is connected from the via v90 to the terminal connection part Q12 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp423 provided in the first wiring layer La1. As shown in FIG. 41, the second branch path is connected from the via v90 to the termination resistor RA17 by a wiring path cp424 provided in the sixth wiring layer La6. The other end of this termination resistor RA17 is connected to the solid wiring layer (GND) of the second wiring layer La2 through a predetermined via (not shown in the wiring diagram).

[0310] 37 and 38, the third branch path is connected from the via v90 to the via v150 in the first connector placement area 194 by a wiring path cp425 provided in the third wiring layer La3, and further connected to the terminal connection part hdt12 from inside the first connector placement area 194 by a wiring path cp426 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v90 to the via v185 by a wiring path cp427 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp428 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0311] In the wiring path P40 (FIG. 49), as shown in FIG. 34, the terminal connection unit HDT13 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp431 to a via v42 arranged outside the composite chip placement area 191, specifically between the composite chip placement area 191 and the control ROM placement area 192. The terminal connection unit HDT13 is arranged in the second row from the outer periphery of the composite chip placement area 191. As shown in FIG. 40, the via v42 is connected to a via v89 arranged in the control ROM placement area 192 by a wiring path cp432 provided in the fourth wiring layer La4.

[0312] The wiring path that extends from the terminal connection part HDT13 to the via v89 branches into four at the via v89. The first branch path, as shown in Fig. 35, is connected from the via v89 to the terminal connection part Q13 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp433 provided in the first wiring layer La1. The second branch path, as shown in Fig. 41, is connected from the via v89 to the termination resistor RA17 by a wiring path cp434 provided in the sixth wiring layer La6.

[0313] 37 and 38, the third branch path is connected from the via v89 to the via v149 in the first connector placement area 194 by a wiring path cp435 provided in the third wiring layer La3, and further connected to the terminal connection part hdt13 from inside the first connector placement area 194 by a wiring path cp436 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v89 to the via v186 by a wiring path cp437 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp438 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0314] In the wiring path P41 (FIG. 49), as shown in FIG. 34, the terminal connection part HDT14 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v22 arranged nearby in the diagonal +X+Y direction by a wiring path cp441. The via v22 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT14) arranged around it. This via v22 is connected to the via v88 arranged in the control ROM placement area 192 by a wiring path cp442 provided in the fourth wiring layer La4, as shown in FIG.

[0315] The wiring path that reaches the terminal connection part HDT14 and the via v88 branches into four at the via v88. As shown in Fig. 35, the first branch path is connected from the via v88 to the terminal connection part Q14 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp443 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v88 to the termination resistor RA17 by a wiring path cp444 provided in the sixth wiring layer La6.

[0316] 37 and 38, the third branch path is connected from the via v88 to the via v148 in the first connector placement area 194 by a wiring path cp445 provided in the third wiring layer La3, and further connected to the terminal connection part hdt14 from inside the first connector placement area 194 by a wiring path cp446 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v88 to the via v187 by a wiring path cp447 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 constituting the decoding circuit by a wiring path cp448 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0317] In the wiring path P42 (FIG. 49), as shown in FIG. 34, the terminal connection part HDT15 provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v15 arranged nearby in the diagonal +X+Y direction by a wiring path cp451. The via v15 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HDT15) arranged around it. This via v15 is connected to the via v87 arranged in the control ROM placement area 192 by a wiring path cp452 provided in the fourth wiring layer La4, as shown in FIG.

[0318] The wiring path that reaches the terminal connection part HDT15 and the via v87 branches into four at the via v87. As shown in Fig. 35, the first branch path is connected from the via v87 to the terminal connection part Q15 / A-1 of the control ROM 105 from inside the control ROM placement area 192 by a wiring path cp453 provided in the first wiring layer La1. As shown in Fig. 41, the second branch path is connected from the via v87 to the termination resistor RA17 by a wiring path cp454 provided in the sixth wiring layer La6.

[0319] 37 and 38, the third branch path is connected from the via v87 to the via v147 in the first connector placement area 194 by a wiring path cp455 provided in the third wiring layer La3, and further connected to the terminal connection part hdt15 from inside the first connector placement area 194 by a wiring path cp456 provided in the sixth wiring layer La6 as shown in Fig. 42. The fourth branch path is connected from the via v87 to the via v188 by a wiring path cp457 provided in the third wiring layer La3 as shown in Fig. 37 and 39, and further connected to the decoder IC14 by a wiring path cp458 provided in the sixth wiring layer La6 as shown in Fig. 43.

[0320] Next, the wiring paths P43 to P45 respectively connected to the chip select output terminal HCS0, the read strobe output terminal HRD, and the system reset terminal HRESET of the composite chip 104 will be described.

[0321] In the wiring path P43 (FIG. 50), as shown in FIG. 34, the terminal connection part HCS0 provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp501 to a via v9 arranged nearby in the diagonal −X+Y direction, where it branches into two. The via v9 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HCS0) arranged around it. The first branch path of the via v9 is connected by a wiring path cp502 provided in the sixth wiring layer La6 to a via v60 arranged in the control ROM placement area 192, as shown in FIG. 33, and is further connected to the terminal connection part CE# from inside the control ROM placement area 192 by a wiring path cp503 provided in the first wiring layer La1, as shown in FIG.

[0322] 31, the second branch path of via v9 is connected to via v173 by wiring path cp504 provided in the fourth wiring layer La4, where it further branches into two. The branch path 2a of this via v173 is connected to via v201 by wiring path cp505 provided in the sixth wiring layer La6, as shown in FIG. 33. This via v201 forms test point TP33. The branch path 2b of via v173 is connected to DC 3.3V (fifth wiring layer La5) via resistor RA12 by wiring path cp506 provided in the first wiring layer La1, as shown in FIG.

[0323] In the wiring path P44 (FIG. 50), as shown in FIG. 28, the terminal connection part HRD provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp511 to a via v25 arranged nearby in the diagonal +XY direction, where it branches into two. The via v25 is arranged approximately in the center of the four terminal connection parts (including the terminal connection part HRD) arranged around it. As shown in FIG. 33, the first branch path of the via v25 is connected by a wiring path cp512 provided in the sixth wiring layer La6 to the outside of the composite chip placement area 191, specifically to a via v47 arranged between the composite chip placement area 191 and the control ROM placement area 192, and further connected to the terminal connection part OE# from outside the control ROM placement area 192 by a wiring path cp513 provided in the first wiring layer La1, as shown in FIG.

[0324] 30, the second branch path of the via v25 is connected to the via v172 by a wiring path cp514 provided on the third wiring layer La3, where it further branches into two. The 2a branch path of the via v172 is connected to the via v171 arranged near the outside of the first connector arrangement area 194 by a wiring path cp515 provided on the third wiring layer La3, as shown in FIG. 30, and is further connected to the terminal connection portion hrd from outside the first connector arrangement area 194 by a wiring path cp516 provided on the sixth wiring layer La6, as shown in FIG. 28. The 2b branch path of the via v172 is connected to DC 3.3V (fifth wiring layer La5) via a resistor RA8 by a wiring path cp517 provided on the first wiring layer La1, as shown in FIG.

[0325] 28, in the wiring path P45 (FIG. 50), the terminal connection part HRESET provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp521 to a via v26 arranged outside (on the +X side of) the composite chip placement area 191. The terminal connection part HRESET is arranged on the outermost side of the composite chip placement area 191. As shown in FIG. 31, the via v26 is connected to a via v202 by a wiring path cp522 provided in the fourth wiring layer La4, and further connected to a via v174 by a wiring path cp523 provided in the sixth wiring layer La6, as shown in FIG. 33, where it branches into two.

[0326] 33, the first branch path of the via v174 is connected to a via v108 arranged near the outside (+X side) of the control ROM placement area 192 by a wiring path cp524 provided in the sixth wiring layer La6, and further connected to the terminal connection unit RESET# from the inside of the control ROM placement area 192 by a wiring path cp525 provided in the first wiring layer La1, as shown in Fig. 35. Note that, as shown in Fig. 33, the wiring path cp524 of the sixth wiring layer La6 is connected to DC 3.3V (fifth wiring layer La5) via a resistor R40, and is also connected to ground (second wiring layer La2) via a capacitor C151.

[0327] As shown in FIG. 28, the second branch path of via v174 is connected to via v204 by wiring path cp526 provided on the first wiring layer La1. This via v204 constitutes test point TP17. The via v204 is connected to the reset circuit on the sixth wiring layer La6. That is, as shown in FIG. 33, via v204 is connected to resistor-embedded transistor T1 by wiring path cp527 provided on the sixth wiring layer La6, further connected to logic integrated circuit IC7 by wiring path cp528, and further connected to WDT-embedded reset integrated circuit (reset IC) IC10 via via v203, which constitutes test point TP23, by wiring path cp529. The wiring path cp528 is connected to DC 3.3V (fifth wiring layer La5) via resistor R19, and the wiring path cp529 is connected to ground (second wiring layer La2) via capacitor C40 and to DC 3.3V (fifth wiring layer La5) via resistor R26.

[0328] The reset circuit on the sixth wiring layer La6 side is configured as shown in Fig. 55. A system reset signal can be input to the logic integrated circuit IC7 via the first liquid crystal control connector CN31, and a reset signal can also be input from the WDT-integrated reset integrated circuit (reset IC) IC10. When either of these reset signals is input, the reset signal is sent to the composite chip 104 and control ROM 105 via the noise-suppressing resistor-integrated transistor T1. For example, an LED data output terminal ASIBLDTB of the composite chip 104 is connected to the WDT-integrated reset integrated circuit (reset IC) IC10 for WDT reset.

[0329] Here, test point TP23 is used to check if reset integrated circuit IC10 is activated. As shown in FIG. 33, it is located on wiring path cp421 on the sixth wiring layer La6 and near reset integrated circuit IC10. Therefore, the identification information for test point TP23, "TP23," is typically silk-screened on the sixth wiring layer La6 side where wiring path cp421 is located, i.e., on the back surface 98b side. Meanwhile, the check using test point TP23 must be performed after the board is assembled (see FIGS. 8 and 9) or after the board is installed (mounted) in the gaming machine main body. In this state, however, the back surface 98b of the LCD control board 98 is shaded by the opposing presentation interface board 96 and LCD interface board 97, making it impossible to apply a tester to it. Therefore, in this embodiment, as shown in FIG. 56, the identification information for test point TP23, "TP23," is located on the front surface 98a side, not on the wiring path cp421 side where test point TP23 is located, i.e., on the back surface 98b side. Since the test point TP23 is configured by a via v203 that penetrates the substrate body 190, it is possible to apply a tester to the test point TP23 from the front surface 98a side of the substrate body 190 as well.

[0330] In addition, test point TP17 is provided in via v204 that connects wiring path cp418 on the first wiring layer La1 side and wiring path cp419 on the sixth wiring layer La6 side, and the display of "TP17", which is the identification information indicating this test point TP17, is also located on the surface 98a side, like test point TP23.

[0331] The same is true for the other test points TP28 and TP33 described above. That is, the test point TP28 is provided on the wiring path cp3 of the third wiring layer La3, but the marking "TP28" which is the identification information for this test point TP28 is located on the front surface 98a. Also, the test point TP33 is provided on the wiring path cp505 of the sixth wiring layer La6, but the marking "TP33" which is the identification information for this test point TP33 is located on the front surface 98a.

[0332] Next, we will explain the wiring paths P46 and P47 that are respectively connected to the 8 / 16-bit mode selection terminal BYTE#, the write enable input terminal WE#, and the write protect / program input terminal WP# / ACC of the control ROM 105. Note that these wiring paths P46 and P47 are not connected to the composite chip 104.

[0333] In the wiring path P46 (FIG. 50), as shown in FIG. 35, the terminal connection unit BYTE# provided in the control ROM placement area 192 of the first wiring layer La1 is connected to the via v48 by the wiring path cp531. This via v48 is arranged near the terminal connection unit BYTE# outside (-X side) of the control ROM placement area 192, and is connected to DC 3.3V via the fifth wiring layer La5 as shown in FIG. 32. As described above, in this embodiment, the 8 / 16-bit mode selection terminal BYTE# of the control ROM 105 is connected to the power supply (H level), thereby selecting the 16-bit communication mode.

[0334] In the wiring path P47 (FIG. 50), as shown in FIG. 35, a terminal connection portion WE# (first predetermined terminal) provided in the control ROM placement area 192 of the first wiring layer La1 is connected to a via v111 by a wiring path cp541. This via v111 (first predetermined interlayer conductive portion) is disposed near the terminal connection portion WE# on the outside (+X side) of the control ROM placement area 192 and is connected to DC 3.3V via the fifth wiring layer La5 as shown in FIG. 32. As described above, in this embodiment, the write enable input terminal WE# of the control ROM 105 is connected to a power supply (H level). This enables the mode to be switched according to the value (H / L) of the output enable input terminal OE#, such as setting the output disable mode at H level (non-read) and the output mode at L level (read). Note that the output enable input terminal OE# is connected to the read strobe output terminal HRD of the composite chip 104 as described above.

[0335] In addition, in the wiring path P47, as shown in FIG. 35, the terminal connection portion WP# / ACC (second predetermined terminal) provided in the control ROM placement area 192 of the first wiring layer La1 is connected to the via v112 by the wiring path cp542. This via v112 is located near the terminal connection portion WP# / ACC on the outside (+X side) of the control ROM placement area 192. Furthermore, as shown in FIG. 33, the via v112 (second predetermined interlayer conductive portion) is connected to the via v111 through the resistor R43 by the wiring path cp543 provided in the sixth wiring layer La6. As described above, this via v111 is connected to DC 3.3V through the fifth wiring layer La5. As described above, in this embodiment, the write-protect / program input terminal WP# / ACC of the control ROM (specific electronic component) 105 is set to be writable and programmable by being connected to the power supply (H level). Furthermore, by connecting to the power supply via the resistor R43, inputs exceeding the H level are excluded, ensuring a stable H level.

[0336] For example, depending on the type of control ROM, if an input exceeding the H level causes a mode setting other than write prohibition / permission or program execution prohibition / permission to be performed, by configuring it so that it remains stably at H level via a resistor in this manner, it is possible to prevent the control ROM from being set to a mode other than write prohibition / permission or program execution prohibition / permission even if an input exceeding the H level is received due to noise or the like.

[0337] Next, the wiring paths P48 to P51 for connecting the decoder IC13 to the liquid crystal control second connector CN32 to transmit the power control signals PS1 and PS2, the backlight ON / OFF control signal XSTABY1, and the backlight dimming PWM signal VBR1, respectively, will be described. Note that the connection between the data input / output terminals HDT0 to HDT7 of the composite chip 104 and the decoder IC13 has already been described with reference to the wiring paths P27 to P34 (FIG. 48). Furthermore, in the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction), and the connector terminals ps1, ps2, xstaby1, and vbr1 are arranged along the second edge 195b on the -Y side of the second connector arrangement area 195.

[0338] The wiring path P48 (Fig. 51) transmits the power supply control signal PS1, and as shown in Fig. 43, a wiring path cp551 is drawn from the decoder IC13 on the sixth wiring layer La6 to the -Y side and connected to a via v211. This via v211 is connected to a via v212 through a wiring path cp552 arranged on the third wiring layer La3, as shown in Fig. 30. And this via v212 is connected to the terminal connection portion ps1 of the liquid crystal control second connector CN32 from outside (the -Y side) of the second connector arrangement area 195 through a wiring path cp553 arranged on the sixth wiring layer La6, as shown in Fig. 44.

[0339] The wiring path P49 (Fig. 51) transmits the power supply control signal PS2, and as shown in Fig. 43, a wiring path cp561 is drawn from the decoder IC13 on the sixth wiring layer La6 to the -Y side and connected to a via v221. This via v221 is connected to a via v222 through a wiring path cp562 arranged on the third wiring layer La3, as shown in Fig. 30. And this via v222 is connected to the terminal connection portion ps2 of the liquid crystal control second connector CN32 from outside (the -Y side) of the second connector arrangement area 195 through a wiring path cp563 arranged on the sixth wiring layer La6, as shown in Fig. 44.

[0340] The wiring path (B wiring path) P50 (Fig. 51) transmits the backlight ON / OFF control signal XSTABY1, and as shown in Fig. 43, a wiring path cp571 is drawn from the decoder IC13 on the sixth wiring layer La6 to the -Y side and connected to a via v231. This via v231 is connected to a via v232 through a wiring path cp572 arranged on the third wiring layer La3, as shown in Fig. 30. And this via v232 is connected to the terminal connection portion xstaby1 of the liquid crystal control second connector CN32 from outside (the -Y side) of the second connector arrangement area 195 through a wiring path cp573 arranged on the sixth wiring layer La6, as shown in Fig. 44.

[0341] The wiring path (B wiring path) P51 (Fig. 51) transmits the backlight dimming PWM signal VBR1, and as shown in Fig. 43, a wiring path cp581 is drawn from the decoder IC13 on the sixth wiring layer La6 to the -Y side and connected to the via v241. This via v241 is connected to the via v242 through the wiring path cp582 arranged on the third wiring layer La3, as shown in Fig. 30. And this via v242 is connected to the terminal connection portion vbr1 of the liquid crystal control second connector CN32 from outside (the -Y side) of the second connector arrangement area 195 through the wiring path cp583 arranged on the sixth wiring layer La6, as shown in Fig. 44.

[0342] Next, we will explain the wiring paths (first wiring path, first wiring path) P52 to P61 that connect the data output terminals RA0+, RA0-, RA1+, RA1-, RA2+, RA2-, RA3+, RA3-, RACLK+, and RACLK- (hereinafter referred to as the ODD-side data output terminal group) of the composite chip 104 to the liquid crystal control second connector CN32, and the wiring paths (second wiring path, first wiring path) P62 to P71 that connect the data output terminals RB0+, RB0-, RB1+, RB1-, RB2+, RB2-, RB3+, RB3-, RBCLK+, and RBCLK- (hereinafter referred to as the EVEN-side data output terminal group) to the liquid crystal control second connector CN32. The wiring paths P52 to P61 constitute the first transmission path LVDS1 that transmits the ODD signal, and the wiring paths P62 to P71 constitute the second transmission path LVDS2 that transmits the EVEN signal.

[0343] 26(b), 36, etc., the ODD-side data output terminal group (first chip terminals) of the composite chip 104 is arranged in two rows along the second edge 191b of the composite chip arrangement area 191. That is, on the outermost side of the composite chip arrangement area 191, the data output terminals RA0-, RA1-, RA2-, RACLK-, RA3- are arranged in that order in the −X direction, and further inside them, the data output terminals RA0+, RA1+, RA2+, RACLK+, RA3+ are arranged in that order in the −X direction.

[0344] 26(b), 36, etc., the EVEN-side data output terminal group (second chip terminals) of the composite chip 104 are arranged in two rows inside the composite chip arrangement area 191 with respect to the ODD-side data output terminal group. That is, inside the ODD-side data output terminal group, the data output terminals RB0-, RB1-, RB2-, RBCLK-, RB3- are arranged in that order in the −X direction, with a GND terminal row in between, and further inside them, the data output terminals RB0+, RB1+, RB2+, RBCLK+, RB3+ are arranged in that order in the −X direction.

[0345] In addition, the second connector arrangement area 195 in which the liquid crystal control second connector CN32 is arranged is arranged in an elongated shape parallel to the second edge 191b on the second edge 191b side of the composite chip arrangement area 191, as shown in Figures 33, 36, etc. In the liquid crystal control second connector CN32, a large number of terminals are arranged in two rows along the longitudinal direction (X direction), and as shown in FIG. 44, the connector terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ corresponding to the ODD side data output terminal group are arranged in the -X direction along a first edge 195a on the -Y side of the second connector arrangement area 195, and the connector terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ corresponding to the EVEN side data output terminal group are arranged in the -X direction along a second edge 195b on the +Y side of the second connector arrangement area 195.

[0346] First, the wiring paths (first wiring paths) P52 to P61 (FIG. 52) constituting the first transmission path LVDS1 will be described. In the wiring path P52 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp601 to a via (specific interlayer conductive portion) v251 arranged in the second connector placement area 195 (near the connector). As shown in FIG. 44, the via v251 is connected to the terminal connection portion ra0- from inside the second connector placement area 195 by a wiring path cp602 of the sixth wiring layer La6.

[0347] In the wiring path P53 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA0+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via (specific interlayer conductive portion) v252 arranged in the second connector placement area 195 (near the connector) by a wiring path cp603. The wiring path cp603 is routed between the terminal connection portion RA0- and the adjacent terminal connection portion RA1- and is drawn out to the outside of the composite chip placement area 191. That is, the two wiring paths cp601 and cp603 constituting the actuation signal line RA0 are arranged adjacent to each other and parallel to each other. The via v252 is connected to the terminal connection portion ra0+ from inside the second connector placement area 195 by a wiring path cp604 of the sixth wiring layer La6, as shown in FIG. 44.

[0348] 36, in the wiring path P54 (FIG. 52), the terminal connection portion RA1- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp605 to a via (specific interlayer conductive portion) v253 arranged in (near the connector) the second connector placement area 195. As shown in FIG. 44, the via v253 is connected to the terminal connection portion ra1- from inside the second connector placement area 195 by a wiring path cp606 of the sixth wiring layer La6.

[0349] In the wiring path P55 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA1+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via (specific interlayer conductive portion) v254 arranged in the second connector placement area 195 (near the connector) by a wiring path cp607. The wiring path cp607 passes between the terminal connection portion RA1- and the adjacent terminal connection portion RA2- and is drawn out to the outside of the composite chip placement area 191. That is, the two wiring paths cp605 and cp607 constituting the actuation signal line RA1 are arranged adjacent to each other and parallel to each other. The via v254 is connected to the terminal connection portion ra1+ from inside the second connector placement area 195 by a wiring path cp608 of the sixth wiring layer La6, as shown in FIG. 44.

[0350] 36, in the wiring path P56 (FIG. 52), the terminal connection portion RA2- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp609 to a via (specific interlayer conductive portion) v255 arranged in (near the connector) the second connector placement area 195. As shown in FIG. 44, the via v255 is connected to the terminal connection portion ra2- from inside the second connector placement area 195 by a wiring path cp610 of the sixth wiring layer La6.

[0351] In the wiring path P57 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA2+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp611 to a via (specific interlayer conductive portion) v256 arranged in the second connector placement area 195 (near the connector). The wiring path cp611 is routed between the terminal connection portion RA2- and the adjacent terminal connection portion RACLK- and is drawn out to the outside of the composite chip placement area 191. That is, the two wiring paths cp609 and cp611 constituting the differential signal line RA2 are arranged adjacent to each other and parallel to each other. The via v256 is connected to the terminal connection portion ra2+ from inside the second connector placement area 195 by a wiring path cp612 of the sixth wiring layer La6, as shown in FIG. 44.

[0352] 36, in the wiring path P58 (FIG. 52), the terminal connection portion RACLK- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp613 to a via (specific interlayer conductive portion) v257 arranged in (near the connector) the second connector placement area 195. As shown in FIG. 44, the via v257 is connected to the terminal connection portion raclk- from inside the second connector placement area 195 by a wiring path cp614 of the sixth wiring layer La6.

[0353] In the wiring path P59 (FIG. 52), as shown in FIG. 36, the terminal connection portion RACLK+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via (specific interlayer conductive portion) v258 arranged in the second connector placement area 195 (near the connector) by a wiring path cp615. The wiring path cp615 is drawn out to the outside of the composite chip placement area 191, passing between the terminal connection portion RACLK- and the adjacent terminal connection portion RA3-. That is, the two wiring paths cp613 and cp615 constituting the differential signal line RACLK are arranged adjacent to each other and parallel to each other. The via v258 is connected to the terminal connection portion raclk+ from inside the second connector placement area 195 by a wiring path cp616 of the sixth wiring layer La6, as shown in FIG. 44.

[0354] 36, in the wiring path P60 (FIG. 52), the terminal connection portion RA3- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp617 to a via (specific interlayer conductive portion) v259 arranged in (near the connector) the second connector placement area 195. As shown in FIG. 44, the via v259 is connected to the terminal connection portion ra3- from inside the second connector placement area 195 by a wiring path cp618 of the sixth wiring layer La6.

[0355] In the wiring path P61 (FIG. 52), as shown in FIG. 36, the terminal connection portion RA3+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp619 to a via (specific interlayer conductive portion) v260 arranged in the second connector placement area 195 (near the connector). The wiring path cp619 is drawn out to the outside of the composite chip placement area 191 via the -X side of the terminal connection portion RA3-. That is, the two wiring paths cp617 and cp619 constituting the differential signal line RA3 are arranged adjacent to each other and parallel to each other. The via v260 is connected to the terminal connection portion ra3+ from inside the second connector placement area 195 by a wiring path cp620 of the sixth wiring layer La6, as shown in FIG. 44.

[0356] 36, in the first wiring layer La1, ground wiring paths gp1-gp4 are respectively arranged between the wiring paths cp601, cp603 constituting the operating signal line RA0 and the wiring paths cp605, cp607 constituting the operating signal line RA1, between the wiring paths cp605, cp607 constituting the operating signal line RA1 and the wiring paths cp609, cp611 constituting the operating signal line RA2, between the wiring paths cp609, cp611 constituting the operating signal line RA2 and the wiring paths cp613, cp615 constituting the operating signal line RACLK, and between the wiring paths cp613, cp615 constituting the operating signal line RACLK and the wiring paths cp617, cp619 constituting the operating signal line RA3. The ground wiring paths gp1-gp4 are formed in an elongated shape with a substantially constant width.

[0357] Next, the wiring paths (second wiring paths) P62 to P71 (FIG. 53) constituting the second transmission path LVDS2 will be described. In the wiring path P62 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0- provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp621 to a via v261 arranged nearby in the diagonal +XY direction. The via v261 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB0-) arranged around it. As shown in FIG. 44, this via v261 is connected to the terminal connection portion rb0- from outside the second connector placement area 195 by a wiring path cp622 of the sixth wiring layer La6.

[0358] In the wiring path P63 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB0+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v262 arranged nearby in the diagonal +XY direction by the wiring path cp623. The via v262 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB0+) arranged around it. As shown in FIG. 44, this via v262 is connected to the terminal connection portion rb0+ from outside the second connector placement area 195 by the wiring path cp624 of the sixth wiring layer La6. Note that the wiring path cp624 is drawn out to the outside of the composite chip placement area 191 via the +X side of the via v261. That is, the two wiring paths cp622 and cp624 constituting the differential signal line RB0 are arranged adjacent to each other and parallel to each other.

[0359] In the wiring path P64 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1- provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v263 arranged nearby in the diagonal +XY direction by a wiring path cp625. The via v263 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB1-) arranged around it. As shown in FIG. 44, this via v263 is connected to the terminal connection portion rb1- from outside the second connector placement area 195 by a wiring path cp626 of the sixth wiring layer La6.

[0360] In the wiring path P65 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB1+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v264 arranged nearby in the diagonal +XY direction by the wiring path cp627. The via v264 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB1+) arranged around it. As shown in FIG. 44, this via v264 is connected to the terminal connection portion rb1+ from outside the second connector placement area 195 by the wiring path cp628 of the sixth wiring layer La6. Note that the wiring path cp628 passes between the via v263 and its adjacent via v261 and is drawn out to the outside of the composite chip placement area 191. That is, the two wiring paths cp626 and cp628 constituting the differential signal line RB1 are arranged adjacent to each other and parallel to each other.

[0361] In the wiring path P66 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2- provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v265 arranged nearby in the diagonal +XY direction by a wiring path cp629. The via v265 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB2-) arranged around it. As shown in FIG. 44, this via v265 is connected to the terminal connection portion rb2- from outside the second connector placement area 195 by a wiring path cp630 of the sixth wiring layer La6.

[0362] In the wiring path P67 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB2+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v266 arranged nearby in the diagonal +XY direction by the wiring path cp631. The via v266 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB2+) arranged around it. As shown in FIG. 44, this via v266 is connected to the terminal connection portion rb2+ from outside the second connector placement area 195 by the wiring path cp632 of the sixth wiring layer La6. Note that the wiring path cp632 passes between the via v265 and its adjacent via v263 and is drawn out to the outside of the composite chip placement area 191. That is, the two wiring paths cp630 and cp632 constituting the differential signal line RB2 are arranged adjacent to each other and parallel to each other.

[0363] In the wiring path P68 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK- provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v267 arranged nearby in the diagonal +XY direction by a wiring path cp633. The via v267 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RBCLK-) arranged around it. As shown in FIG. 44, this via v267 is connected to the terminal connection portion rbclk- from outside the second connector placement area 195 by a wiring path cp634 of the sixth wiring layer La6.

[0364] In the wiring path P69 (FIG. 53), as shown in FIG. 36, the terminal connection portion RBCLK+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected to the via v268 arranged nearby in the diagonal +XY direction by the wiring path cp635. The via v268 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RBCLK+) arranged around it. As shown in FIG. 44, this via v268 is connected to the terminal connection portion rbclk+ from outside the second connector placement area 195 by the wiring path cp636 of the sixth wiring layer La6. Note that the wiring path cp636 is drawn out to the outside of the composite chip placement area 191 via the via v267 and its adjacent via v265. That is, the two wiring paths cp634 and cp636 constituting the differential signal line RBCLK are arranged adjacent to each other and parallel to each other.

[0365] In the wiring path P70 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3- provided in the composite chip placement area 191 of the first wiring layer La1 is connected to a via v269 arranged nearby in the diagonal +XY direction by a wiring path cp637. The via v269 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB3-) arranged around it. As shown in FIG. 44, this via v269 is connected to the terminal connection portion rb3- from outside the second connector placement area 195 by a wiring path cp638 of the sixth wiring layer La6.

[0366] In the wiring path P71 (FIG. 53), as shown in FIG. 36, the terminal connection portion RB3+ provided in the composite chip placement area 191 of the first wiring layer La1 is connected by a wiring path cp639 to a via v270 arranged nearby in the diagonal +XY direction. The via v270 is arranged approximately in the center of the four terminal connection portions (including the terminal connection portion RB3+) arranged around it. As shown in FIG. 44, this via v270 is connected to the terminal connection portion rb3+ from outside the second connector placement area 195 by a wiring path cp640 of the sixth wiring layer La6. Note that the wiring path cp640 is drawn out to the outside of the composite chip placement area 191 via the via v269 and the adjacent via v267. That is, the two wiring paths cp638 and cp640 constituting the differential signal line RB3 are arranged adjacent to each other and parallel to each other.

[0367] 44, in the sixth wiring layer La6, ground wiring paths gp11-gp14 are respectively arranged between the wiring paths cp622, cp624 constituting the operating signal line RB0 and the wiring paths cp626, cp628 constituting the operating signal line RB1, between the wiring paths cp626, cp628 constituting the operating signal line RB1 and the wiring paths cp630, cp632 constituting the operating signal line RB2, between the wiring paths cp630, cp632 constituting the operating signal line RB2 and the wiring paths cp634, cp636 constituting the operating signal line RBCLK, and between the wiring paths cp634, cp636 constituting the operating signal line RBCLK and the wiring paths cp638, cp640 constituting the operating signal line RB3. The ground wiring paths gp11-gp14 are formed in an elongated shape with a substantially constant width.

[0368] 36 and 44, the ground wiring paths gp1-gp4 and gp11-gp14 are arranged between the multiple sets (five sets each) of wiring path pairs that make up the differential signal lines, respectively, in order to reduce noise to the surrounding wiring paths cp601, cp622, etc. of the ground wiring paths gp1-gp4 and gp11-gp14. Note that, as shown in FIGS. 36 and 44, it is desirable that the ground wiring paths gp1-gp4 and gp11-gp14 be wider than the surrounding wiring paths cp601, cp622, etc. This is because the surrounding wiring paths cp601, cp622, etc. are wiring paths for transmitting image data, and therefore a design that is more resistant to noise is intended to prevent pattern images on the screen from becoming difficult to see due to noise.

[0369] In addition, the ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side are connected to each other via multiple through holes (vias), as shown in Figures 36 and 44, which makes it possible to further reduce noise.

[0370] As shown in Figures 36 and 44, the ground wiring paths gp1 to gp4 on the first wiring layer La1 side and the ground wiring paths gp11 to gp14 on the sixth wiring layer La6 side have different shapes depending on the surrounding wiring patterns, but are configured to pass through partially corresponding locations (areas) and are connected via through holes (vias) at the corresponding locations (here, multiple locations for each), so it is possible to adopt shapes that correspond to the surrounding wiring patterns while making the wiring pattern more noise-resistant and efficient.

[0371] To summarize the configuration of the wiring paths P1 to P71 described above, first, of the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105, the wiring paths P2 to P43 and P45 (specific wiring paths) are connected to the terminal connection portions on the control ROM 105 side through vias v60 to v108 (specific interlayer conductive portions; vias shown in gray in Figures 45 to 50) arranged in the control ROM placement area (second placement area) 192, as shown in Figures 35, 45 to 50, and further, among them, the wiring paths P2 to P16, P19 to P23, P35 to P43 and P45 (first specific wiring paths) are connected to the terminal connection portions A0 to A14, A17 to A21, Q8 to Q15, CE# and RESET# on the control ROM 105 side from inside the control ROM placement area 192 (wiring paths shown in bold lines in Figures 45 to 50). In this way, by arranging the wiring path connecting the composite chip 104 and the control ROM 105 so that it passes through the control ROM placement area 192, which has a relatively large amount of space, and by connecting to the terminals of the control ROM 105 from inside the control ROM placement area 192 as much as possible, the wiring patterns on the board can be arranged more efficiently, making it possible to make better use of the limited space.

[0372] 35, the wiring paths connecting the vias v60 to v108 (specific interlayer conductive portions) arranged in the control ROM placement area (second placement area) 192 to the terminal connection portions on the control ROM 105 side from outside the control ROM placement area 192, specifically, wiring paths cp165, cp175, cp234, cp244, cp254, cp343, cp353, cp363, cp373, cp303, cp313, cp323, and cp333, are arranged so as to cross the long sides 192a and 192b of the control ROM placement area 192 outside the respective terminal connection portions. This configuration allows the wiring length to be shorter than when wiring avoids the control ROM placement area 192, thereby improving wiring efficiency and reducing noise. Furthermore, in the range indicated by the control ROM placement area 192, the control ROM 105 is actually located, so the wiring pattern cannot be seen, which makes it possible to prevent unauthorized access to the wiring pattern.

[0373] 35, the wiring paths cp233, cp243, and cp253 connected by the first wiring layer La1 to the vias v60 to v108 (specific interlayer conductive portions) arranged in the control ROM arrangement area (second arrangement area) 192 are also arranged so as to cross the long side 192a of the control ROM arrangement area 192 outside the respective terminal connection portions. By using such a configuration in multiple places in combination with the configuration in the previous paragraph, the effect described in the previous paragraph becomes even more effective.

[0374] Furthermore, a ROM socket 193 (Figure 8) is fixed to the control ROM placement area 192, and the bottom wall (shielding wall corresponding to the specific interlayer conductive portion) 193a of the ROM socket 193 shields the control ROM placement area 192. Therefore, even when the control ROM 105 is removed from the ROM socket 193, the wiring pattern within the control ROM placement area 192, including the vias v60 to v108 (specific interlayer conductive portion), cannot be seen or accessed from the outside.

[0375] The vias v60 to v108 (specific interlayer conductive portions) in the control ROM placement area 192 enhance the heat dissipation effect by penetrating from the front surface (first surface) 98a to the back surface (second surface) 98b of the substrate body 190. In addition, the vias v60 to v108 (specific interlayer conductive portions) in the control ROM placement area 192 are connected to predetermined electronic components such as ICs, resistors, capacitors, and connectors on the back surface 98b side, i.e., the sixth wiring layer La6 side.

[0376] Moreover, the wiring paths P2 to P45 connecting the composite chip 104 and the control ROM 105 branch from a first wiring section connecting the composite chip 104 and a predetermined via (a predetermined interlayer conductive section) to a second wiring section connecting the predetermined via and the control ROM 105, and a third wiring section connecting the predetermined via and other electronic components such as the liquid crystal control first connector CN31. The second wiring section is arranged in a first predetermined wiring layer such as the first wiring layer La1, and the third wiring section is arranged in a second predetermined wiring layer such as a third wiring layer La3 or a sixth wiring layer La6 that is different from the first predetermined wiring layer.

[0377] Among these wiring paths P2-P45, the wiring paths P2-P42 that transmit address / data information have predetermined vias (predetermined interlayer conductive portions) at their branch points that are specific interlayer conductive portions (vias shown in gray in FIGS. 45-50) located within the control ROM placement area (second placement area) 192. Furthermore, the second wiring portion is located on the first wiring layer La1, at least a portion of the first wiring portion is located on the fourth wiring layer La4 (an example of a predetermined wiring layer other than the first wiring layer), and the third wiring portion is located on the first wiring layer La1 (first predetermined wiring layer). This enhances the prevention of fraudulent acts, such as tampering with the wiring patterns and vias that transmit address / data information. Furthermore, by placing wiring patterns within the control ROM placement area 192, wiring space can be secured in other areas. Furthermore, particularly with regard to branch points, wiring patterns tend to be densely packed across multiple layers of the board, so sufficient wiring space is required where the branch points are to be located. From this perspective, it is also effective to place the branch points within the control ROM placement area 192, where there is ample wiring space.

[0378] Furthermore, among the vias v60 to v107 (specific interlayer conductive portions) in the control ROM placement area 192, vias v61 to v85, v103 to v107 (first specific interlayer conductive portions) that constitute part of the wiring paths P2 to P26 (address wiring) for transmitting address information, and vias v87 to v102 (second specific interlayer conductive portions) that constitute part of the wiring paths P27 to P42 (data wiring) for transmitting data information are arranged in the Y direction (first direction), which is the arrangement direction of the terminals in the control ROM 105.

[0379] In addition, the address output terminals HAD1 to HAD25 and data input / output terminals HDT0 to HDT15 (first terminals) on the composite chip 104 side are arranged differently from the corresponding address input terminals A0 to A24 and data input / output terminals Q0 to Q15 (second terminals) on the control ROM 105 side, and the wiring paths P2 to P42 connecting them have vias v60 to v85, v87 to v107 (specific interlayer conductive parts) in the control ROM placement area 192, and the arrangement of the vias v60 to v85, v87 to v107 (specific interlayer conductive parts) in the control ROM placement area 192 is made similar to the arrangement of the corresponding terminals (specific second terminals) on the control ROM 105 side. This allows the wiring patterns connecting the specific interlayer conductive portions and the terminals of the control ROM to be organized, and, for example, there is no need to route the patterns so that the positional relationship between the multiple wiring patterns changes (twists), making the connection method easier and more effective use of the space within the control ROM placement area 192. In this way, when the terminal arrangement of the composite chip 104 and the terminal arrangement of the control ROM 105 differ, it can be said that it is more effective in terms of wiring efficiency to approximate the arrangement of the specific interlayer conductive portions to the terminal arrangement of the control ROM 105 by devising the routing of a wiring pattern with a relatively long wiring distance from the composite chip 104 to the specific interlayer conductive portion, rather than devising the routing of a wiring pattern with a relatively short wiring distance from the specific interlayer conductive portion in the placement area of ​​the control ROM 105 to the terminals of the control ROM 105.

[0380] Specifically, as shown in FIG. 35, for example, address input terminals A0 to A6 and their corresponding vias v85 to v79, address input terminals A17 to A20 and their corresponding vias v68 to v64, and data input / output terminals Q12 to Q15 and their corresponding vias v90 to v87 are each arranged in approximately the same order in the Y direction, while address input terminals A23, A22, A24, A16, A15 and their corresponding vias v62, v63, v61, v103, v104, data input / output terminals Q0 to Q3 and their corresponding vias v102 to v99, data input / output terminals Q8 to Q11 and their corresponding vias v94 to v91, and data input / output terminals Q4 to Q7 and their corresponding vias v98 to v95 are each arranged in approximately the reverse order in the Y direction. In this way, rather than designing the arrangement of the specific interlayer conductive portions based solely on the terminal arrangement of the control ROM 105, the specific interlayer conductive portions may be arranged based on the terminal arrangement of the composite chip 104 and the terminal arrangement of the LCD control first connector CN31, which are also connected. While this may complicate the connection relationship with the control ROM 105 in some places, it simplifies the connection relationship between the composite chip 104 and the LCD control first connector CN31, which are located farther away from the terminals of the control ROM 105, using the specific interlayer conductive portions as a reference. This allows for improved wiring efficiency across the entire board. In other words, by designing the arrangement of the specific interlayer conductive portions as needed within the control ROM placement area 192, the wiring efficiency across the entire board can be improved. Furthermore, the wiring efficiency across the entire board can be improved not only within the control ROM placement area 192, but also by designing the arrangement of vias, which serve as branch points, as described above.

[0381] Furthermore, the address output terminals HAD1 to HAD25 and data input / output terminals HDT0 to HDT15 (first terminals) on the composite chip 104 side are arranged differently not only from the corresponding address input terminals A0 to A24 and data input / output terminals Q0 to Q15 (second terminals) on the control ROM 105 side, but also from the terminals had1 to had25 and hdt0 to hdt15 (third terminals) of the liquid crystal control first connector CN31, and the arrangement of vias v61 to v85 and v87 to v102 (specific interlayer conductive parts) is made to match (approximate) the arrangement of the terminals had1 to had25 and hdt0 to hdt15 (third terminals) of the liquid crystal control first connector CN31. 37, 38, and 42, the Y-direction arrangement of the vias v61-v85 and v87-v102 (specific interlayer conductive portions) matches the X-direction arrangement of the corresponding terminals had1-had25 and hdt0-hdt15 of the liquid crystal control first connector CN31, so the wiring path group (third wiring path group) connecting them can be arranged in parallel without twisting. Note that this results in a complex wiring pattern including twists for the wiring path group (second wiring path group) connecting the vias v61-v85 and v87-v102 (specific interlayer conductive portions) with the address input terminals A0-A24 and data input / output terminals Q0-Q15 (second terminals) on the control ROM 105 side, but this can be easily realized by arranging them within the control ROM placement area 192, which has relatively ample space.

[0382] Of the wiring paths P2 to P42 that transmit address / data information, the wiring paths P2 to P13 and P19 to P42 branch off to the control ROM 105 side and the liquid crystal control first connector CN31 side at vias v61 to v68, v74 to v85, v87 to v102 (specific interlayer conductive parts) within the control ROM placement area 192. However, the wiring paths P14 to P18 do not branch off to the control ROM 105 side at vias v69 to v73 within the control ROM placement area 192, but instead have separate vias v103 to v107 provided within the control ROM placement area 192 on the wiring path that connects the vias v69 to v73 and the liquid crystal control first connector CN31, and branch off to the control ROM 105 side from the vias v103 to v107. By configuring it in this manner, the wiring to the liquid crystal control first connector CN31 can be arranged in parallel without twisting in harmony with other wiring paths, and the wiring to the control ROM 105 can also be arranged efficiently while avoiding interference with other wiring paths.

[0383] Further, a plurality of one-end wiring paths P2 to P9, P19, P20, P22, P23, P27 to P30, P35 to P38 respectively connect specific one-end terminals A0 to A7, A17, A18, A20, A21, Q0 to Q3, Q8 to Q11 included in the one-end terminals arranged on one end side of the control ROM (second electronic component) 105 to the corresponding first specific terminals HAD0 to HAD7, HAD17, HAD18, HAD20, HAD21, HDT0 to HDT3, HDT8 to HDT11 on the composite chip (first electronic component) 104 side via vias v65 to v68, v78 to v85, v91 to v94, v99 to v102 (first interlayer conductive portions), and specific other terminals included in the other-end terminals arranged on the other end side of the control ROM (second electronic component) 105. The first and second interlayer conductive portions are arranged adjacent to each other in an arrangement that is different from the first and second specific terminals, respectively.

[0384] Furthermore, internal connection wiring portions that connect from the inside of the control ROM placement area 192 and external connection wiring portions that connect from the outside are alternately arranged to the multiple ROM terminal connection portions arranged in a row. That is, as shown in Fig. 35, external connection wiring portions cp303, cp313, cp323, cp333 and internal connection wiring portions cp383, cp393, cp403, cp413 are alternately connected to the terminal connection portions Q0, Q8, Q1, Q9, Q2, Q10, Q3, Q11 of the control ROM placement area 192. Moreover, vias v102 to v99 on the other ends of the external connection wiring portions cp303, cp313, cp323, cp333 are arranged near one another, and vias v94 to v91 on the other ends of the internal connection wiring portions cp383, cp393, cp403, cp413 are also arranged near one another. Similarly, the internal connection wiring portions cp453, cp443, cp433, and cp423 and the external connection wiring portions cp373, cp363, cp353, and cp343 are alternately connected to the terminal connection portions Q15 / A-1, Q7, Q14, Q6, Q13, Q5, Q12, and Q4 of the control ROM placement area 192. Furthermore, the vias v87 to v90 at the other ends of the internal connection wiring portions cp453, cp443, cp433, and cp423 are arranged near each other, and the vias v95 to v98 at the other ends of the external connection wiring portions cp373, cp363, cp353, and cp343 are also arranged near each other. In this way, by grouping the internal connection wiring portions and the external connection wiring portions near each other, rather than by arranging the terminals of the control ROM 105, the routing of the wiring pattern is simplified and wiring efficiency is improved.

[0385] Furthermore, the first wiring paths P2-P42 transmitting address information or data information and the second wiring path P43 transmitting chip select information are located on different wiring layers. That is, the first wiring layers P2-P42 are located on the fourth wiring layer La4, and the second wiring path P43 is located on the sixth wiring layer La6. The first wiring layers P2-P42 are connected to vias v61-v85, v87-v101, and v60 (specific interlayer conductive portions) in the control ROM placement area 192 from the composite chip 104 side. By routing the chip select signal, which is important for data transmission, using a wiring layer different from the wiring pattern transmitting address information or data information, transmission noise from the wiring pattern transmitting address information or data information is less likely to be transmitted to the chip select signal, resulting in a noise-resistant configuration. Furthermore, by differentiating the wiring path pattern for the chip select signal from the other wiring paths, it becomes relatively easy to identify the wiring for the chip select signal. This makes it relatively easy to check for short-circuiting or other tampering in the wiring pattern and to check for electrical continuity.

[0386] In addition, the wiring path P45 constituting the reset circuit includes wiring paths cp418 to cp421 (reset first wiring paths) connecting the reset integrated circuit (reset IC) IC10 and the via v174 (predetermined interlayer conductive portion), wiring paths cp413 to cp415 (reset second wiring paths) connecting the via v174 (predetermined interlayer conductive portion) and the reset terminal HRESET of the composite chip 104, and wiring paths cp416 and cp417 (reset third wiring paths) connecting the via v174 (predetermined interlayer conductive portion) and the reset terminal RESET# of the control ROM 105. ), and test point TP17 (first test point) and test point TP23 (second test point) that penetrate the LCD control board 98 in the board thickness direction are arranged on wiring paths cp418-cp421 (reset first wiring paths). Identification information "TP17" and "TP23" indicating these test points TP17 and TP23 are displayed on the front side, i.e., the surface (first surface) 98a opposite to the boards 96 and 97, when the LCD control board 98 is assembled with other boards such as the performance interface board 96 and the LCD interface board 97. The reset integrated circuit (reset IC) IC10 is located on the back side (second surface) 98b. As a result, even though the wiring paths where the test points TP17 and TP23 are arranged are not visible when the boards are assembled (see Figures 8 and 9) or when the board is installed (placed) in the gaming machine main body, it is possible to easily check the test points TP17 and TP23 based on the identification information displayed on the visible surface 98a.

[0387] In addition, the wiring paths cp418 to cp421 (reset first wiring paths) have the wiring path cp418 (first wiring path) arranged on the front surface (first surface) 98a side, the wiring paths cp420 and cp421 (second wiring paths) arranged on the back surface (second surface) 98b side, and a via v204 (reset first interlayer conductive portion) connecting them, with the test point TP17 (first test point) arranged in the via v204 and the test point TP23 (second test point) arranged on the wiring path cp421 (second wiring path).

[0388] The control ROM (specific electronic component) 105 operates in an operating mode corresponding to the voltage level of the write protect / program input terminal WP# / ACC (second predetermined terminal), the write enable input terminal WE# (first predetermined terminal) is connected to the power supply wiring path of the fifth wiring layer La5 through a via v111 (first predetermined interlayer conductive portion), and the write protect / program input terminal WP# / ACC (second predetermined terminal) is connected to the via v111 (first predetermined interlayer conductive portion) through a resistor R43. The control ROM (specific electronic component) 105 is disposed on the front surface (first surface) 98a of the liquid crystal control board 98, and the resistor R43 is disposed on the back surface (second surface) 98b, and the write protect / program input terminal WP# / ACC (second predetermined terminal) is connected to the resistor R43 through a via v112 (second predetermined interlayer conductive portion). In this way, by using the via that connects WP# / ACC (second specified terminal) to the power wiring path through resistor R43 in common as the via that connects WE# (first specified terminal) to the power wiring path, the number of vias can be reduced compared to when connecting them individually through vias.

[0389] Furthermore, a plurality of terminals are arranged in a matrix on the bottom surface side of the composite chip 104, and among these terminals, outer terminals arranged near the periphery of the composite chip arrangement area (first arrangement area) 191, for example, terminals HDT0, HDT1, HDT4, HDT5, etc. arranged on the outermost side and in the second row inside thereof, are connected to the control ROM 105 by first wiring paths P27, P28, P31, P32, etc., and inner terminals arranged more inward than the outer terminals, for example, terminals HDT2, HDT3, HDT6, etc. are connected to the control ROM 105 by second wiring paths P29, P30, P33, etc. The first wiring paths P27, P28, P31, P32, etc. connect vias v32, v31, v37, v46, etc. (first interlayer conductive portions) arranged outside the composite chip placement area 191 to outer terminals HDT0, HDT1, HDT4, HDT5, etc. on the first wiring layer La1, and the second wiring paths P29, P30, P33, etc. connect vias v24, v8, v17, etc. (second interlayer conductive portions) arranged inside the composite chip placement area 191 to inner terminals HDT2, HDT3, HDT6, etc. on the first wiring layer La1. In addition, the distance from the inner terminals HDT2, HDT3, HDT6, etc. to the vias v24, v8, v17, etc. (second interlayer conductive portion) is shorter than the distance from the outer terminals HDT0, HDT1, HDT4, HDT5, etc. to the vias v32, v31, v37, v46, etc. (first interlayer conductive portion).

[0390] In this way, in the composite chip 104 having a plurality of terminals arranged in a matrix, outer terminals arranged near the periphery of the arrangement area of ​​the composite chip 104 can be connected to vias arranged outside the composite chip 104, thereby creating wiring space near the periphery of the composite chip 104 and making it easier to route the wiring patterns of the inner terminals of the composite chip 104 outward to the composite chip, thereby improving wiring efficiency. Also, with regard to the above-mentioned wiring space, since wiring space is created near the periphery of the composite chip in the plurality of wiring layers of the substrate, it goes without saying that it is easier to route the wiring pattern to the outside of the composite chip regardless of which wiring layer of the plurality of wiring layers is used.

[0391] In addition, the wiring paths (first wiring paths) P52 to P61 that transmit ODD signals (first signals) corresponding to odd pixels are arranged so that the wiring ratio to the first wiring layer (A wiring layer) La1 is the highest among the multiple wiring layers La1 to La6, and the wiring paths (first wiring paths) P52 to P61 that transmit EVEN signals (second signals) corresponding to even pixels are arranged so that the wiring ratio to the sixth wiring layer (B wiring layer) La6 is the highest among the multiple wiring layers La1 to La6.

[0392] That is, the ODD side data output terminal group (first chip terminals) to which the wiring paths (first wiring paths) P52 to P61 are connected are arranged closer to the outer periphery of the composite chip 104 than the EVEN side data output terminal group (second chip terminals) to which the wiring paths (second wiring paths) P62 to P71 are connected, and the liquid crystal control second connector CN32 is arranged on the sixth wiring layer (second wiring layer) Lb6 side opposite the composite chip 104. The wiring paths (first wiring paths) P52-P61 connected to the ODD-side data output terminal group (first chip terminal) are connected to the liquid crystal control second connector CN32 through vias (specific interlayer conductive portions) v251-v260 arranged near the liquid crystal control second connector CN32, and the EVEN-side data output terminal group (second chip terminal) connected to the EVEN-side data output terminal group (second chip terminal) is connected to the liquid crystal control second connector CN32 through vias (non-specific interlayer conductive portions) v261-v270 arranged near the EVEN-side data output terminal group. This configuration reduces the possibility of malfunctions due to disconnection or noise occurring simultaneously in the wiring paths (first wiring paths) P52-P61 transmitting the ODD signal (first signal) and the wiring paths (second wiring paths) P62-P7 transmitting the EVEN signal (second signal), making it possible to distribute the risk.

[0393] Furthermore, the liquid crystal control second connector CN32 is disposed on the second edge (first side) 191b side of the composite chip 104, and wiring paths (first wiring paths) P52 to P71 capable of transmitting image data signals for the liquid crystal display means 76 are drawn out from the second edge (first side) 191b side of the composite chip 104 and connected to first connector terminals of the liquid crystal control second connector CN32, and wiring paths (second wiring paths) P50, P51 capable of transmitting control signals related to the backlight are drawn out from the first edge (second side) 191a side of the composite chip 104 and connected to second connector terminals of the liquid crystal control second connector CN32. This allows for efficient wiring by separating the wiring paths (first wiring paths) P52 to P71 from the wiring paths (second wiring paths) P50, P51 while shortening the wiring length of the wiring paths (first wiring paths) P52 to P71.

[0394] Next, details of the wiring pattern and the like of the liquid crystal interface board 97 will be described. The liquid crystal interface board 97 has a substrate main body 220 (see FIG. 8) with multiple wiring layers. Specifically, the substrate main body 220 has a first wiring layer Lb1 on the front (first surface) 97a side, a sixth wiring layer Lb6 on the back (second surface) 97b side, and second to fifth wiring layers Lb2 to Lb5 arranged between them, for a total of six wiring layers, namely, first to sixth wiring layers Lb1 to Lb6 (FIGS. 57 to 61). The second and fifth wiring layers Lb2 and Lb5 (FIG. 58) are solid wiring layers connected to ground, and the fourth wiring layer Lb4 (FIG. 60) is solid wiring layer connected to a power supply. The substrate main body 220 of the liquid crystal interface board 97 has a large number of through-hole type vias (interlayer conductive portions) formed therein, similar to the liquid crystal control board 98, and the multiple wiring layers Lb1 to Lb6 are electrically connected to each other via these vias (interlayer conductive portions).

[0395] In the following explanation, the in-plane direction and orientation of each wiring layer Lb1 to Lb6 are based on an XY coordinate system (see FIG. 8) common to the liquid crystal control board 98, with the up / down direction in FIGS. 57 to 61 being the X direction and the left / right direction being the Y direction, with the up / down direction being the +X / -X direction (side), respectively, and the left / right direction being the +Y / -Y direction (side), respectively.

[0396] As shown in Figure 57, the first wiring layer Lb1 of the liquid crystal interface substrate 97 is provided with liquid crystal IF first to third connector arrangement areas 221 to 223 where the liquid crystal IF first to third connectors CN21 to CN23 are arranged, and liquid crystal connection first and second connector arrangement areas 224, 225 where the liquid crystal connection first and second connectors CN24, CN25 are arranged.

[0397] The liquid crystal IF first connector arrangement region 221 is elongated in the X direction and is arranged on the +X side near the +Y side edge of the first wiring layer Lb1. The liquid crystal IF second connector arrangement region 222 is elongated in the X direction and is arranged on the -X side near the +Y side edge of the first wiring layer Lb1. The liquid crystal IF third connector arrangement region 223 is elongated in the X direction and is arranged slightly on the +X and -Y sides of the center of the first wiring layer Lb1. Furthermore, the liquid crystal connection first and second connectors CN24 and CN25 are both elongated in the Y direction and are arranged adjacent to each other at positions closer to the -Y side near the -X side edge of the first wiring layer Lb1, with the -Y side being the liquid crystal connection second connector CN25.

[0398] Among the numerous wiring paths provided on the liquid crystal interface board 97, attention will be focused on the multiple types of wiring paths P101-P124 connected to the liquid crystal display means 76 via the first and second liquid crystal connection connectors CN24 and CN25, and details thereof will be described with reference to the drawings. Note that Figs. 62-66 show only the portions constituting the wiring paths P101-P124 extracted from the wiring patterns of the first to sixth wiring layers Lb1-Lb6 shown in Figs. 57-61, and Figs. 67-72 are enlarged views of those portions. Figs. 73-75 show schematic diagrams of the wiring paths P101-P124, and Figs. 76-78 show circuit diagrams corresponding to the wiring paths P101-P124.

[0399] First, we will explain the wiring paths P101 to P110 that constitute the first transmission path LVDS1 that transmits ODD signals. The wiring paths P101 to P110 are arranged to connect the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ in the liquid crystal IF third connector CN23 to the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ in the liquid crystal connection first connector CN24.

[0400] The LCD IF third connector CN23 is disposed in an elongated shape in the X direction as shown in Fig. 62 etc., with many terminals arranged along a pair of its long sides, and as shown in Fig. 67, the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ are arranged in that order in the -X direction along the long side on the -Y side. Note that terminals ra0- and ra0+, terminals ra1- and ra1+, terminals ra2- and ra2+, terminals raclk- and raclk+, and terminals ra3- and ra3+ are arranged adjacent to each other, and a predetermined number (here, one of each) of GND terminals are arranged between each of these five pairs (omitted in Fig. 67).

[0401] In addition, as shown in Figure 62, the first LCD connection connector CN24 is elongated in the Y direction and is arranged on the -X side of the LCD IF third connector CN23, with many terminals arranged along the long side on the +X side, and as shown in Figure 69, the ODD side terminals ra0-, ra0+, ra1-, ra1+, ra2-, ra2+, raclk-, raclk+, ra3-, ra3+ are arranged in that order in the +Y direction.

[0402] In the wiring paths P101 to P110 (FIG. 73), as shown in FIG. 67, in the first wiring layer Lb1, wiring paths cp701 to cp710 are drawn out in the −Y direction from terminal connection portions ra0−, ra0+, ra1−, ra1+, ra2−, ra2+, raclk−, raclk+, ra3−, and ra3+ on the liquid crystal IF third connector arrangement region 223 side. Then, after turning toward the liquid crystal connection first connector CN24 side (−X side), these wiring paths cp701 to cp710 are connected to terminal connection portions ra0−, ra0+, ra1−, ra1+, ra2−, ra2+, raclk−, raclk+, ra3−, and ra3+ on the liquid crystal connection first connector CN24 side via test points TP101 to TP110, as shown in FIGS.

[0403] In this way, in the wiring paths P101 to P110, the terminal arrangement on the LCD IF third connector CN23 side and the terminal arrangement on the LCD connection first connector CN24 side are aligned when facing each other, so it is possible to arrange the wiring without twisting using only the first wiring layer Lb1 without switching wiring layers.

[0404] The wiring paths cp701 and cp702, wiring paths cp703 and cp704, wiring paths cp705 and cp706, wiring paths cp707 and cp708, and wiring paths cp709 and cp710 are parallel with each other at approximately constant intervals, and ground patterns are provided between each of these five sets of wiring paths. Furthermore, these five sets of wiring paths have meandering sections of different lengths to equalize the wiring lengths. Because the diameter of the test points TP101 to TP110 is larger than the minimum spacing between each of the wiring paths, they are offset from each other relative to the axes of the wiring paths cp701 to cp710, increasing the spacing between them. Furthermore, adjacent pairs of test points, a total of five sets, are offset in the X direction to avoid interference with each other.

[0405] Furthermore, the wiring paths P101-P110 branch off from the wiring paths cp701-cp710 at test points TP101-TP110 and are connected to the ground (second wiring layer Lb2) via protection diodes arranged on the sixth wiring layer Lb6 side. That is, the wiring paths P101 and P102 are connected to the protection diode D103, the wiring paths P103 and P104 to the protection diode D105, the wiring paths P105 and P106 to the protection diode D102, the wiring paths P107 and P108 to the protection diode D104, and the wiring paths P109 and P110 to the protection diode D101.

[0406] Next, the wiring paths P111 to P120 constituting the second transmission path LVDS2 that transmits the EVEN signal will be described. The wiring paths P111 to P120 are arranged to connect the EVEN side terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ in the liquid crystal IF third connector CN23 to the EVEN side terminals rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+ in the liquid crystal connection first connector CN24.

[0407] The arrangement of the EVEN-side terminals in the liquid crystal IF third connector CN23 is reversed compared to the arrangement of the ODD-side terminals. That is, as shown in Fig. 67, the EVEN-side terminals in the liquid crystal IF third connector CN23 are arranged in the -X direction along the long side on the +Y side in the order rb0+, rb0-, rb1+, rb1-, rb2+, rb2-, rbclk+, rbclk-, rb3+, rb3-. Note that terminals rb0+ and rb0-, terminals rb1+ and rb1-, terminals rb2+ and rb2-, terminals rbclk+ and rbclk-, and terminals rb3+ and rb3- are arranged adjacent to each other, and a predetermined number (here, one of each) of GND terminals are arranged between each of these five pairs (omitted in Fig. 67).

[0408] On the other hand, the arrangement of the EVEN side terminals in the first LCD connection connector CN24 is the same as the arrangement of the ODD side terminals. That is, as shown in Fig. 69, the EVEN side terminals in the third LCD IF connector CN23 are arranged in the +Y direction on the +Y side of the ODD side terminals in the order rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, rb3+.

[0409] Comparing the EVEN side terminals on the LCD IF third connector CN23 side (Fig. 67) with the EVEN side terminals on the LCD connection first connector CN24 side (Fig. 69) face to face, the arrangement of the five terminal pairs rb0, rb1, rb2, rbclk, and rb3 on the two sides is reversed. Therefore, the wiring paths connecting them will be twisted, and unlike the wiring paths on the ODD side, they must be wired across multiple wiring layers.

[0410] In the wiring paths P111 to P120 (FIG. 74), as shown in FIG. 67, in the first wiring layer Lb1, wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are respectively drawn out in the +Y direction from terminal connection portions rb0-, rb0+, rb1-, rb1+, rb2-, rb2+, rbclk-, rbclk+, rb3-, and rb3+ on the LCD IF third connector arrangement area 223 side. Then, these wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 change direction toward the LCD-connecting first connector CN24 side (-X side), and are then connected to vias v301 to v310.

[0411] The wiring paths cp711 and cp714, the wiring paths cp717 and cp720, the wiring paths cp723 and cp726, the wiring paths cp729 and cp732, and the wiring paths cp735 and cp738 are parallel to each other with a substantially constant spacing between them, and a ground pattern is disposed between each of these five pairs of wiring paths.

[0412] Here, v301 to v310 correspond to the five terminal pairs rb0, rb1, rb2, rbclk, and rb3, and are arranged two by two adjacent to each other in the X direction. The five pairs of vias are staggered in the X direction so that vias v301 and v302 corresponding to the wiring paths cp711 and cp714 on the most +Y side are closest to the -X side, and vias v309 and v310 corresponding to the wiring paths cp735 and cp738 on the most -Y side are closest to the +Y side.

[0413] With regard to the vias v303 to v310 corresponding to the wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738, the vias v303, v305, v307, and v309 on the negative signal side are positioned on the negative X side relative to the vias v304, v306, v308, and v310 on the positive signal side, and the wiring paths cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 are each connected from the negative Y side, whereas with regard to the vias v301 and v302 corresponding to the wiring paths cp711 and cp714, the via v301 on the negative signal side is positioned on the positive X side relative to the via v302 on the positive signal side, and the wiring paths cp711 and cp714 are each connected from the positive Y side.

[0414] 70, wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the sixth wiring layer Lb6 side. These wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 are turned toward the first liquid crystal connector CN24 side (-X side) so that the wiring paths cp712 and cp715 corresponding to the vias v301 and v302 furthest on the -X side are furthest on the -Y side, and the wiring paths cp736 and cp739 corresponding to the vias v309 and v310 furthest on the +X side are furthest on the +Y side, and then connected to test points TP111 to TP120. As a result, the order of the wiring paths cp712, cp715, cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 on the sixth wiring layer Lb6 side is changed from the order of the wiring paths cp711, cp714, cp717, cp720, cp723, cp726, cp729, cp732, cp735, and cp738 on the first wiring layer Lb1 side, and matches the arrangement of the EVEN side terminals in the first LCD connection connector CN24.

[0415] Note that cp718, cp721, cp724, cp727, cp730, cp733, cp736, and cp739 are drawn out in the +Y direction relative to vias v303 to v310, while cp712 and cp715 are d...

Claims

[Claim 1] image display means; a display control means for outputting image data to the image display means; In gaming machines, a first substrate on which the display control means is mounted and on which a first signal line for transmitting the image data to the image display means is formed; a second substrate on which a second signal line for transmitting the image data is formed and on which an output connector for outputting the image data to the image display means is mounted; a connector that connects the first signal line of the first substrate and the second signal line of the second substrate, the second signal line is composed of a plurality of wiring paths, connecting a protection circuit and / or a test point to each of the plurality of wiring paths; In order to make the wiring lengths of the plurality of wiring paths uniform on the upstream side of the protection circuit and / or the test point, adjustment sections having different lengths are provided in the plurality of wiring paths. A gaming machine characterized by:

Images