Computer system and method for processing debug information for the computer system

Abstract

To provide a computer system and a method for processing debug information of the computer system.SOLUTION: A method includes the steps of: counting a time by using a first timer when a computer system is started; determining whether or not a first-stage confirmation signal has been received within a first specific time; stopping the first timer and counting a time by using a second timer if the first-stage confirmation signal has been received; determining whether or not a second-stage confirmation signal has been received within a second specific time; stopping the second timer if the second-stage confirmation signal has been received; adjusting a level of an input pin of a general-purpose input / output module to a low level if the first-stage confirmation signal has not been received within the first specific time or the second-stage confirmation signal has not been received within the second specific time; and outputting debug information according to the low level.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a computer system and a method for processing debug information for that computer system, and more particularly to a computer system that can automatically output debug information and a method for processing debug information for that computer system. [Background technology]

[0002] With the rapid advancement of science and technology, new computer system hardware and firmware are constantly being developed. However, during the development stage of a computer system, a computer system may become stuck at a certain stage of startup without completing the startup process. In the prior art, if a computer system fails to start normally, no output information is available, and only the approximate time period during which the system froze is known. This makes it impossible to identify and list in detail which driver element experienced the problem. Therefore, in the prior art, if a computer system fails to start, the system developer must create a new version of the Basic Input / Output System (BIOS) capable of exporting debug mode information via the system's serial port, rewrite it to the device, and then re-export detailed serial port information via the system serial port or Serial-over-LAN (SOL) of the Baseboard Management Controller (BMC). Even if the BIOS itself already has firmware capable of executing the debug mode, the system developer must manually select to start outputting debug information via the serial port from the BIOS menu before obtaining the debug information. Also, if the BIOS itself already has firmware that enables debug mode, the debug information can only be obtained after the system developer starts outputting debug information via the serial port of the BIOS using an Intelligent Platform Management Interface (IPMI) command.

[0003] Therefore, when a computer system has a startup problem, system developers are unable to gather detailed information in real time. Conversely, they must manually create a new version of the PI System or manually start the output of debug information via the serial port of the PI System through the PI System menu or IPMI command. This requires additional time and cost for system developers. Furthermore, creating a new PI System may prevent the true cause of the freeze from being discovered.

[0004] Therefore, there is a need to invent a new computer system and a method for processing debug information for the computer system to overcome the deficiencies of the prior art. Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for processing debug information of a computer system, characterized in that it can automatically output debug information when booting fails.

[0006] Another main object of the present invention is to provide a computer system to which the above method is applied. [Means for solving the problem]

[0007] To achieve the above object, a method for processing debug information for a computer system according to the present invention is used in a computer system including a general-purpose input / output module, a firmware control module, a basic input / output system (PI system), a first timer, and a second timer. The method includes the steps of, when the computer system is started, having the first timer measure time, having the firmware control module determine whether a first-stage confirmation signal is received within a first predetermined time, and if the first-stage confirmation signal is received, having the firmware control module stop the first timer and have the second timer measure time, having the firmware control module determine whether a second-stage confirmation signal is received within a second predetermined time, and if the second-stage confirmation signal is received, having the firmware control module stop the second timer, and if the first-stage confirmation signal is not received within the first predetermined time or if the second-stage confirmation signal is not received within the second predetermined time, having the firmware control module set an input pin of the general-purpose input / output module to a low level, and having the basic input / output system output debug information in response to the low level.

[0008] A computer system according to the present invention includes a general-purpose input / output module, a firmware control module, a basic input / output system, a first timer, and a second timer. The general-purpose input / output module includes an input pin and an output pin. The firmware control module is electrically connected to the output pin of the general-purpose input / output module. The basic input / output system is electrically connected to the input pin of the general-purpose input / output module and is capable of outputting debug information. The first timer is electrically connected to the firmware control module and is configured to set a first predetermined time. The second timer is electrically connected to the firmware control module and is configured to set a second predetermined time. When the computer system is started up, the first timer measures time. If the firmware control module detects that a first-stage confirmation signal has been received within the first predetermined time, it stops the first timer and starts measuring time with the second timer. If the firmware control module detects that the first timer has reached the first predetermined time, it controls the input pin of the general-purpose input / output module to a low level. If the firmware control module receives a second-stage confirmation signal within the second predetermined time, it stops the second timer. If the firmware control module detects that the second timer has reached the second predetermined time, it controls the input pin of the general-purpose input / output module to a low level. The BASIC outputs debug information in response to the state of an input pin being low. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram of a configuration of a computer system according to the present invention. [Figure 2] 2 is a flowchart of a method for processing debug information in a computer system according to the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to help the judges better understand the technical content of the present invention, the present invention will be described below by citing preferred and specific examples.

[0011] First, reference will be made to FIG. 1, which is a schematic diagram illustrating the configuration of a computer system according to the present invention.

[0012] The computer system 1 according to the present invention is any system under development and design, such as a desktop computer or servo computer, that allows developers to easily obtain information on the startup failure of the computer system 1. The computer system 1 includes a general-purpose input / output (GPIO) module 10, a firmware control module 20, a basic input / output system (BIOS) 30, a first timer 41, and a second timer 42. The general-purpose input / output module 10 includes an input pin 11 and an output pin 12. The firmware control module 20 may be, but is not limited to, a baseboard management controller (BMC), a system input / output (SIO) chip, a complex programmable logic device (CPLD), or a field programmable gate array (FPGA). The firmware control module 20 is electrically connected to the output pin 12 of the general-purpose input / output module 10 to execute processes required for the startup of the computer system 1. The basic input / output system 30 is electrically connected to the input pins 11 of the general-purpose input / output module 10 and similarly serves to execute processes required when the computer system 1 is started up, and software such as an operating system only starts to operate after the basic input / output system 30 has finished operating. In addition, in one embodiment of the present invention, the basic input / output system 30 can record debug information such as the timing of startup failures of the computer system 1 and frozen blocks, and can also output the recorded debug information.

[0013] The first timer 41 and the second timer 42 are electrically connected to the firmware control module 20. The first timer 41 is used to set a first predetermined time as a timing function for the first stage of booting the computer system 1. This first stage is the stage from when the computer system 1 starts up until the basic input / output system 30 starts operating, and may include processes such as initialization of chips and memory, data transfer, etc. The second timer 42 is used to set a second predetermined time as a timing function for the second stage of booting the computer system 1. This second stage may be the stage when the basic input / output system 30 of the computer system 1 operates. The first timer 41 may be a Fault Resilient Boot 3 (FRB-3) module, and the second timer 42 may be a Fault Resilient Boot 2 (FRB-2) module. The first predetermined time may be one minute, and the second predetermined time may be six minutes. However, the present invention is not limited to these values. In addition, the technology of preventing startup failures by using an FRB-3 module or an FRB-2 module to measure time when starting up computer system 1 is already well known to those with ordinary knowledge in the field of technology to which this invention pertains, so the principle behind it will not be repeated here.

[0014] During the period from when the computer system 1 boots up until when the basic input / output system 30 begins to operate, the firmware control module 20 controls the first timer 41 to count time. When the basic input / output system 30 begins to operate after the computer system 1 has booted up normally, the basic input / output system 30 outputs a first-phase confirmation signal. Therefore, if the firmware control module 20 receives the first-phase confirmation signal from the basic input / output system 30 via the output pin 12 of the general-purpose input / output module 10 within the first predetermined time, it can determine that the first-phase startup of the computer system 1 has been completed. Therefore, the firmware control module 20 stops the first timer 41 and controls the second timer 42 to count time. However, if the firmware control module 20 detects that the first timer 41 has not received the first-phase confirmation signal even after the first predetermined time has elapsed, it can determine that the computer system 1 has failed to start up due to an error during the first-phase startup process, and the firmware control module 20 controls the input pin 11 of the general-purpose input / output module 10 to a low level. When the basic input / output system 30 detects that the input pin 11 is at a low level, it automatically outputs debug information to the system developer in response to this low level. The firmware control module 20 also reboots the computer system 1. The debug information may be output directly via the general-purpose input / output module 10 or via SOL (Serial-over-LAN) of the firmware control module 20; however, the present invention is not limited thereto.

[0015] Furthermore, once the basic input / output system 30 has completed its boot process, it outputs a second-phase confirmation signal. Therefore, if the firmware control module 20 receives a second-phase confirmation signal from the basic input / output system 30 via the output pin 12 of the general-purpose input / output module 10 within the second predetermined time, the firmware control module 20 stops the second timer 42. This indicates that the boot process flow in the basic input / output system 30 has been successfully completed. If the firmware control module 20 detects that the second timer 42 has not received a second-phase confirmation signal from the basic input / output system 30 even though the second predetermined time has elapsed, it can determine that the basic input / output system 30 has failed to boot due to an error during the second-phase boot process. The firmware control module 20 controls the input pin 11 of the general-purpose input / output module 10 to a low level, causing the basic input / output system 30 to output the debug information according to the state of the input pin 11 and control the computer system 1 to reboot.

[0016] Alternatively, a system developer may issue a command via an Intelligent Platform Management Interface (IPMI). The firmware control module 20 controls the input pin 11 of the general-purpose input / output module 10 to a low level by executing the IPMI command. The basic input / output system 30 may output the debug information according to the state of the input pin 11.

[0017] Each module of the computer system 1 may be configured as a hardware device, a device combining firmware and hardware, or the like, but the present invention is not limited to these configurations. Furthermore, this embodiment illustrates only a preferred embodiment of the present invention, and to avoid repetition, not all possible modifications and combinations are described in detail. However, those skilled in the art will understand that none of the above-described modules or elements are required. Other specific conventional modules or elements may be included to implement the present invention. Each module or element may be omitted or modified as needed, and it is not necessarily the case that there are no other modules or elements between any two modules.

[0018] 2, which is a flowchart of a method for processing debug information for a computer system according to the present invention. Note that the method for processing debug information for a computer system according to the present invention will be described below using computer system 1 as an example, but the method for processing debug information for a computer system according to the present invention is not limited to being used for computer systems 1 having the same structure as the above.

[0019] First, when the computer system is started, step 201 is performed in which the first timer is used to measure time.

[0020] First, at the first stage of booting by the computer system 1, the firmware control module 20 controls the first timer 41 to count time. The first timer 41 is set to a first predetermined time.

[0021] Next, step 202 is performed to determine whether a first stage confirmation signal is received within the first predetermined time.

[0022] Next, the firmware control module 20 determines whether or not it receives a first stage confirmation signal from the basic input / output system 30 within the first predetermined time period.

[0023] If the first phase confirmation signal is received, it means that the first phase startup of the computer system 1 is completed, and step 203 is performed in which the first timer is stopped and the second timer is used to count time.

[0024] At this time, it is confirmed that the first-phase boot-up of the computer system 1 has been completed, so the firmware control module 20 stops the first timer 41 and controls the second timer 42 to count a second predetermined time.

[0025] If the first stage confirmation signal is not received within the first predetermined time in step 202, step 204 is performed to set the input pin of the general-purpose input / output module to low level.

[0026] If the firmware control module 20 detects that the first timer 41 has reached the first predetermined time but has not received the first-phase confirmation signal from the basic input / output system 30, it can determine that an error has occurred in the first-phase startup process of the computer system 1, and therefore controls the input pin 11 of the general-purpose input / output module 10 to a low level.

[0027] Next, step 205 is performed to cause the basic input / output system to output debug information.

[0028] If the basic input / output system 30 detects that the input pin 11 is at a low level, it automatically outputs debug information to the system developer.

[0029] Then, step 206 is performed to reboot the computer system.

[0030] The firmware control module 20 then reboots the computer system 1, ie, returns to step 201.

[0031] After step 203, the firmware control module 20 also performs step 207 to determine whether a second stage confirmation signal has been received within the second predetermined time period.

[0032] At this time, the firmware control module 20 determines whether a second stage confirmation signal is received from the basic input / output system 30 within the second predetermined time.

[0033] If the second stage confirmation signal is received, step 208 is performed to stop the second timer.

[0034] This means that the second phase startup of the computer system 1, i.e., the startup process flow of the basic input / output system 30, has been successfully completed and the second phase confirmation signal has been sent, so the firmware control module 20 stops the second timer 42 at this time.

[0035] In step 207, if the firmware control module 20 does not receive the second-stage confirmation signal within the second predetermined time, it means that there is an error in the boot process flow of the basic input / output system 30. The firmware control module 20 executes step 204 of setting the input pin of the general-purpose input / output module to low level, step 205 of causing the basic input / output system to output debug information, and step 206 of rebooting the computer system.

[0036] Also, before step 204, the firmware control module 20 may control the input pin 11 of the general-purpose input / output module 10 to a low level according to a command of the intelligent platform management interface issued by the system developer.

[0037] The method for processing debug information for a computer system according to the present invention is not limited to the above-described steps, and the above-described steps may be modified as long as the object of the present invention can be achieved.

[0038] As a result, the computer system 1 of the present invention can automatically obtain debug data when startup is unsuccessful, eliminating the need for system developers to add commands and effectively resolving the shortcomings of the prior art.

[0039] It should be noted that the above embodiments illustrate only preferred embodiments of the present invention, and not all possible modifications and combinations are described in detail to avoid repetition. However, those skilled in the art will understand that none of the above-described modules or elements are necessary. Other specific conventional modules or elements may be included to implement the present invention. Each module or element may be omitted or modified as needed, and it is not necessary that any two modules are separated by other modules or elements. Anything that does not deviate from the basic configuration of the present invention is within the scope of the rights claimed by this patent, and the scope of the claims should be taken as the basis.

Claims

1. 1. A method for processing debug information for a computer system including a general-purpose input / output (GPIO) module, a firmware control module, a basic input / output system, a first timer, and a second timer, the method comprising: timing the first timer upon startup of the computer system; determining, by the firmware control module, whether a first stage confirmation signal is received within a first predetermined time period; when the first-stage confirmation signal is received, stopping the first timer by the firmware control module and starting the second timer; determining, by the firmware control module, whether a second stage confirmation signal is received within a second predetermined time period; stopping the second timer by the firmware control module if the second-stage confirmation signal is received; setting an input pin of the general-purpose input / output module to a low level by the firmware control module when the first-stage confirmation signal is not received within the first predetermined time or when the second-stage confirmation signal is not received within the second predetermined time; and causing said basic input / output system to output debug information in response to a low level.

2. the method further includes controlling the firmware control module to reboot the computer system when the first timer reaches the first predetermined time or when the second timer reaches the second predetermined time.

2. The method for processing debug information in a computer system according to claim 1.

3. continuing to execute a start-up process if the first-stage confirmation signal is received within the first predetermined time period or if the second-stage confirmation signal is received within the second predetermined time period; 3. A method for processing debug information for a computer system according to claim 1.

4. The method further includes controlling the input pin of the general-purpose input / output module to a low level by executing an Intelligent Platform Management Interface (IPMI) command.

2. The method for processing debug information in a computer system according to claim 1.

5. The method further includes a step of controlling the debug information to be output via the general-purpose input / output module or a serial-over-LAN (SOL) of the firmware control module.

2. The method for processing debug information in a computer system according to claim 1.

6. A computer system, a general-purpose input / output module including input and output pins; a firmware control module electrically connected to the output pin of the general-purpose input / output module; a basic input / output system electrically connected to the input pins of the general-purpose input / output module and capable of outputting debug information; a first timer electrically connected to the firmware control module for setting a first predetermined time period; a second timer electrically connected to the firmware control module for setting a second predetermined time period; a basic input / output system (BAS) configured to output the debug information when the state of the input pin is low;

7. When the first timer reaches the first predetermined time or when the second timer reaches the second predetermined time, the firmware control module controls to reboot the computer system.

7. The computer system of claim 6.

8. the firmware control module continues executing the boot process if it receives the first-stage confirmation signal within the first predetermined time or if it receives the second-stage confirmation signal within the second predetermined time; 7. The computer system of claim 6.

9. and controlling the input pin of the general-purpose input / output module to a low level by executing an intelligent platform management interface command.

7. The computer system of claim 6.

10. The debug information is output via the general-purpose input / output module or the SOL of the firmware control module.

7. The computer system of claim 6.

11. The firmware control module is a Baseboard Management Controller (BMC), a System Input / Output (SIO) chip, a Complex Programmable Logic Device (CPLD), or a Field Programmable Gate Array (FPGA); 7. The computer system of claim 6.

12. The first timer is a Fault Resilient Boot 3 (FRB-3) module, and the second timer is a Fault Resilient Boot 2 (FRB-2) module.

7. The computer system of claim 6.

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