Semiconductor package and drive device

Abstract

To decrease the effect of offset in a semiconductor package having Hall elements built therein.SOLUTION: A semiconductor package 100 includes a semiconductor chip having a plurality of Hall elements 111 built therein, and a plurality of external terminals 102 arranged on one surface side of the semiconductor chip. A Hall element 111S1 belonging to a first group and a Hall element 111S2 belonging to a second group are arranged to be point-symmetrical with respect to a center point P of the semiconductor package in a plan view. The Hall element 111S1 is at least partially covered by an external terminal 102A1 among the plurality of external terminals in a plan view, and the Hall element 111S2 is at least partially covered by an external terminal 102B1 among the plurality of external terminals in a plan view. A region R1 covered by the external terminal 102A1 of the Hall element 111S1 in a plan view and a region R2 covered by the external terminal 102B1 of the Hall element 111S2 in a plan view are point-symmetrical with respect to the center point P of the semiconductor package in a plan view.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package and a driving device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor package having terminals arranged in a staggered pattern along the longitudinal direction. Patent Document 2 discloses a method and device for compensating a Hall sensor for both temperature and mechanical stress. Patent Document 3 discloses reducing offset by switching the direction of the drive current of a Hall element. [Prior art document] [Patent Documents] [Patent Document 1] Patent No. 6826088 [Patent Document 2] Patent No. 6371338 [Patent Document 3] Patent No. 5658715 Summary of the Invention [Problem to be solved by the invention]

[0003] It is desirable to reduce the effect of offset in a semiconductor package incorporating a Hall element. [Means for solving the problem]

[0004] A semiconductor package according to one aspect of the present invention may include a semiconductor chip incorporating a plurality of Hall elements and a plurality of external terminals arranged on one surface of the semiconductor chip. The semiconductor package may have a rectangular shape extending in a first direction in a plan view. The plurality of external terminals may include a plurality of first external terminals included in a first row along the first direction and a plurality of second external terminals included in a second row along the first direction, facing the first row across the center of the semiconductor package. The centers of gravity of the plurality of first external terminals may not overlap with the centers of gravity of the plurality of second external terminals in the first direction and in a second direction intersecting the first direction. The plurality of Hall elements may include a first Hall element and a second Hall element. The first Hall element and the second Hall element may be arranged point-symmetrically with respect to a center point of the semiconductor package in a plan view. At least a portion of the first Hall element may be covered by the first external terminal of the plurality of first external terminals in a plan view. The second Hall element may be at least partially covered by a second external terminal of the plurality of second external terminals in a plan view. A first region of the first Hall element that is covered by the first external terminal in a plan view and a second region of the second Hall element that is covered by the second external terminal in a plan view may be point-symmetric with respect to the point at the center of the semiconductor package in a plan view.

[0005] In the semiconductor package, the plurality of Hall elements may include the first and third Hall elements belonging to a first group, and the second and fourth Hall elements belonging to a second group, and the third and fourth Hall elements may be arranged point-symmetrically with respect to the point at the center of the semiconductor package in a plan view.

[0006] In any of the semiconductor packages, when the semiconductor package is divided into a first event area, a second event area, a third event area, and a fourth event area in a planar view along a first axis along the first direction and a second axis along the second direction that pass through the center of the semiconductor package, the first Hall element and the third Hall element may be arranged on the first event area, and the second Hall element and the fourth Hall element may be arranged on the third event area, or the first Hall element and the third Hall element may be arranged on the second event area, and the second Hall element and the fourth Hall element may be arranged on the fourth event area.

[0007] In any of the semiconductor packages, the semiconductor chip may further incorporate a control circuit that outputs a drive signal to control a drive unit that changes the position or attitude of a magnet relative to the semiconductor package based on the sum of outputs indicating the magnitude of the magnetic field output from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element.

[0008] In any of the semiconductor packages, the control circuit may include an amplifier circuit that amplifies the sum of the outputs.

[0009] In any of the semiconductor packages, the control circuit may control the drive unit further based on a difference between the sum of outputs indicating the magnitude of the magnetic field output from the first Hall element and the third Hall element and the sum of outputs indicating the magnitude of the magnetic field output from the second Hall element and the fourth Hall element.

[0010] In any of the semiconductor packages, the control circuit may include an amplifier circuit that amplifies the ratio of the sum of outputs indicating the magnitude of the magnetic fields output from the first Hall element, the second Hall element, the third Hall element, and the fourth Hall element to the difference.

[0011] In any of the semiconductor packages, the plurality of external terminals may include a pair of power supply terminals for supplying power to the semiconductor package, a pair of drive terminals for outputting drive signals from the control circuit to the drive unit, and a pair of communication terminals for communicating with the outside. The first external terminal and the second external terminal may be one of the pair of drive terminals and one of the pair of power supply terminals.

[0012] In any of the semiconductor packages, the third Hall element and the fourth Hall element may not overlap any of the plurality of external terminals in a plan view.

[0013] In any of the semiconductor packages, the first Hall element may be entirely covered by the first external terminal in a plan view, and the second Hall element may be entirely covered by the second external terminal in a plan view.

[0014] In any of the semiconductor packages, the first Hall element and the third Hall element may be entirely covered by the first external terminal in a plan view, and the second Hall element and the fourth Hall element may be entirely covered by the second external terminal in a plan view.

[0015] In any of the semiconductor packages, the first Hall element and the second Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. In the first Hall element, the pair of first electrodes may be output electrodes. In the second Hall element, the pair of second electrodes may be output electrodes.

[0016] In any of the semiconductor packages, the first Hall element may be entirely covered by the first external terminal in a plan view. The second Hall element may be entirely covered by the second external terminal in a plan view. The third Hall element may be partially covered by the first external terminal in a plan view. The fourth Hall element may be partially covered by the second external terminal in a plan view.

[0017] In any of the semiconductor packages, the third Hall element and the fourth Hall element may have a pair of first electrodes facing each other in the first direction and a pair of second electrodes facing each other in a second direction intersecting the first direction. In the third Hall element, the pair of second electrodes may be output electrodes. In the fourth Hall element, the pair of first electrodes may be output electrodes.

[0018] In any of the semiconductor packages, each of the first external terminal and the second external terminal may be an external terminal that is located closest to the point at the center of the semiconductor package in a plan view among the plurality of external terminals.

[0019] In any of the semiconductor packages, the first external terminal and the second external terminal may be point-symmetric with respect to the point at the center of the semiconductor package in a plan view.

[0020] In any of the semiconductor packages, the first Hall element and the third Hall element may be arranged in a line along the first direction, and the second Hall element and the fourth Hall element may be arranged in a line along the first direction.

[0021] In any of the semiconductor packages, the third Hall element and the fourth Hall element may be arranged in a line along a second direction intersecting the first direction.

[0022] In any of the semiconductor packages, the width of the semiconductor package in the first direction may be greater than the width of the semiconductor package in a second direction intersecting the first direction.

[0023] In any of the semiconductor packages, the width in the first direction may be 1.65 times or more longer than the width in the second direction.

[0024] In any of the semiconductor packages, the width in the first direction may be 2.5 times or more longer than the width in the second direction.

[0025] In any one of the semiconductor packages, the total area of ​​the plurality of external terminals in a plan view may be 14% or more of the area of ​​the semiconductor package in a plan view.

[0026] In any one of the semiconductor packages, the total area of ​​the plurality of external terminals in a plan view may be 19% or more of the area of ​​the semiconductor package in a plan view.

[0027] In any of the semiconductor packages, the external terminals may be arranged in two rows along the first direction.

[0028] The semiconductor package may further include a redistribution layer disposed above the semiconductor chip and electrically connected to the semiconductor chip, and a sealing material disposed above the redistribution layer, and the plurality of external terminals may be electrically connected to the redistribution layer via the sealing material.

[0029] In any of the semiconductor packages, the redistribution layer may include wiring that extends 100 μm or more along the first direction from at least one external terminal of the plurality of external terminals and is electrically connected to the semiconductor chip.

[0030] In any one of the semiconductor packages, the wiring may have a portion that extends on a line that passes through the center of the at least one external terminal in a plan view and that is aligned with the first direction.

[0031] In any of the semiconductor packages, the redistribution layer may include wiring that extends 100 μm or more along the second direction from at least one of the plurality of external terminals and is electrically connected to the semiconductor chip.

[0032] A wafer level chip size package (WL-CSP) may be used.

[0033] A driving device according to one aspect of the present invention may include a first portion that holds a magnet. The driving device may include a second portion that holds one of the semiconductor packages so that it faces the magnet, the second portion being held by the first portion so that the position or orientation of the second portion can be changed relative to the first portion. The driving device may include a driving unit that changes the position or orientation of the second portion relative to the first portion. The semiconductor package may output a driving signal to the driving unit based on outputs from the plurality of Hall elements.

[0034] In the driving device, the first portion may further hold a lens portion, and the second portion may further hold an imaging element that captures an image formed through the lens portion.

[0035] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0036] [Figure 1] FIG. 2 is an exploded perspective view of the camera module. [Figure 2] FIG. 1 is a diagram illustrating an example of a circuit configuration of a semiconductor package. [Figure 3] 10 is a diagram showing how the offset amount increases when the output signal of the magnetic sensor is amplified. [Figure 4] FIG. 2 is a plan view of the conductor package as viewed from the external terminal side. [Figure 5] FIG. 5 is a diagram schematically showing a cross section taken along the line AA shown in FIG. [Figure 6] 10 is a diagram showing the relationship between the movement distance of the lens unit and the magnitude of the magnetic field detected by the magnetic sensor. FIG. [Figure 7] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 8] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 9] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 10] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 11] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 12] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 13] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 14] FIG. 2 is a diagram illustrating an example of an arrangement of a plurality of Hall elements. [Figure 15] FIG. 2 is a diagram showing an equivalent circuit of a Hall element. [Figure 16A] FIG. 2 is a diagram showing an equivalent circuit of a Hall element 111S1. [Figure 16B] FIG. 10 is a diagram showing an equivalent circuit of a Hall element 111S2. [Figure 16C] FIG. 10 is a diagram showing an equivalent circuit of a Hall element 111S3. [Figure 16D] FIG. 10 is a diagram showing an equivalent circuit of a Hall element 111S4. [Figure 17] FIG. 2 is a diagram for explaining the function of each external terminal. [Figure 18] FIG. 10 is a diagram showing a wiring state in a rewiring layer of a semiconductor package. DETAILED DESCRIPTION OF THE INVENTION

[0037] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0038] 1 shows an exploded perspective view of a camera module 10 according to this embodiment. The camera module 10 includes a substrate 300, a base 20, a holding frame 30, and a lens unit 40. An image sensor 302 is disposed on the substrate 300. The image sensor 302 may be configured with a CCD or CMOS. The image sensor 302 outputs image data of an optical image formed via the lens unit 40.

[0039] The holding frame 30 holds the lens unit 40 inside. A magnet 32 ​​is arranged on the outer surface of the holding frame 30. The base 20 holds the holding frame 30 together with the lens unit 40 so that they can move in the optical axis direction (Z-axis direction) of the lens unit 40 and in directions intersecting the optical axis (X-axis and Y-axis directions). A coil 200 and a semiconductor package 100 are arranged on the side of the base 20. The coil 200 is arranged in a position facing the magnet 32. The coil 200 may be an air-core coil.

[0040] The magnet 32 ​​and the coil 200 function as a VCM (voice coil motor) that is a drive source that moves or rotates the holding frame 30 relative to the base 20. The holding frame 30 is an example of a first part, and the base 20 is an example of a second part.

[0041] When a current is passed through coil 200 in the magnetic field of magnet 32, a force is generated in coil 200 in a direction perpendicular to the magnetic field. This applies a thrust along the X or Y direction to holding frame 30. The arrangement of coil 200 or the direction of the magnetic field of magnet 32 ​​may be designed so that passing a current through coil 200 applies a thrust along the Z direction to holding frame 30.

[0042] The semiconductor package 100 is disposed in the air-core portion of the coil 200. The semiconductor package 100 may function as a position sensor that detects the position or orientation of the holding frame 30 relative to the base 20. The position sensor may be a magnetic sensor including a Hall element. The position sensor may output a voltage whose magnitude corresponds to a change in a magnetic field. As the holding frame 30 moves, the positional relationship between the semiconductor package 100 and the magnet 32 ​​changes, and the magnitude of the magnetic field detected at that position changes. As a result, the position sensor detects the position of the magnet 32 ​​relative to the semiconductor package 100, i.e., the position of the holding frame 30 relative to the base 20. In this embodiment, a magnetic sensor including a Hall element that utilizes the Hall effect to detect changes in an external magnetic field from the generated electromotive force will be described as an example of the magnetic sensor. However, the magnetic sensor is not limited to a configuration including a Hall element. The magnetic sensor may also include an electromagnetic conversion element other than a Hall element. The magnetic sensor may be any of various sensors capable of detecting a magnetic field, such as a spin-valve magnetoresistive element (GMR element, TMR element, etc.) whose resistance changes in response to changes in an external magnetic field, or may be a combination of these various sensors. The magnetic sensor may also be composed of a sensor element group consisting of multiple magnetic sensor elements.

[0043] The semiconductor package 100 supplies a current to the coil 200 to bring the position or attitude of the holding frame 30 to a target position or attitude depending on the position or attitude of the holding frame 30 relative to the base 20. The semiconductor package 100 may be provided outside the coil 200. Alternatively, the holding frame 30 may include the semiconductor package 100 and the coil 200, and the base 20 may include the magnet 32.

[0044] In the camera module 10 configured as described above, the semiconductor package 100 uses the magnet 32 ​​and the coil 200 as a driving source to pass a current through the coil 200 so that the position or orientation of the lens unit 40 relative to the imaging surface of the image sensor 302 is set to a desired position or orientation. This causes the lens unit 40 to function as a zoom lens or a focus lens. Alternatively, the semiconductor package 100 performs image stabilization by passing a current through the coil 200 so that the position or orientation of the lens unit 40 changes in a direction that cancels out image shake. In this embodiment, a VCM (voice coil motor) is used as an example of the driving source that drives the lens unit 40. However, the driving source is not limited to a VCM. In addition to a VMC, the camera module 10 may also include a microelectromechanical system (MEMS), a shape memory alloy (SMA), a polymer actuator (EAP), a bimetal actuator, or a piezoelectric element as a driving source that drives the lens unit 40.

[0045] 2 is a diagram showing an example of the circuit configuration of the semiconductor package 100. The semiconductor package 100 includes a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117. The magnetic sensor 112, the amplifier 113, the A / D converter 114, the PID control unit 115, the D / A converter 116, and the output driver 117 may be built into a semiconductor chip.

[0046] The magnetic sensor 112 has a plurality of Hall elements and outputs a voltage or current whose magnitude corresponds to the magnitude of the magnetic field as a position signal indicating the position of the lens unit 40. The amplifier 113 amplifies the position signal output from the magnetic sensor 112. The A / D converter 114 converts the analog signal, which is the position signal amplified by the amplifier 113, into a digital signal.

[0047] PID control unit 115 outputs a drive signal to control the position of lens unit 40 to the target position by PID control, based on the position of lens unit 40 indicated in the digital signal output from A / D converter 114 and the target position of lens unit 40 output from position command generation unit 210. A control unit such as a microprocessor such as a CPU or MPU, or a microcontroller such as an MCU that controls imaging of camera module 10 may include position command generation unit 210.

[0048] The D / A converter 116 converts the drive signal from a digital signal to an analog signal and outputs the signal to the output driver 117. The output driver 117 outputs to the coil 200 a current corresponding to the drive signal.

[0049] As shown in Fig. 3, the signal output from the magnetic sensor 112 contains a fair amount of noise. The amplifier 113 downstream of the magnetic sensor 112 amplifies the noise-containing signal as is. If the noise is large, i.e., if the offset amount is large, even if an attempt is made to increase the amplification factor of the amplifier 113, there is a limit to the size of the signal that can be input to the A / D converter 114, and it may not be possible to adequately amplify signals other than noise. By reducing the offset amount contained in the signal output from the magnetic sensor 112, the amplification factor can be increased, and as a result, the S / N ratio can be improved.

[0050] 4 is a plan view of the semiconductor package 100 as seen from the external terminal 102 side. The semiconductor package 100 has a plurality of external terminals 102. The semiconductor package 100 has six external terminals 102.

[0051] The semiconductor package 100 has a rectangular shape extending in a first direction (X-axis direction) in a plan view. Here, the rectangular shape conceptually includes an approximately rectangular shape. The approximately rectangular shape conceptually includes a quadrangle with four corners at angles other than 90°, a quadrangle with four corners within a range of 90°±5°, or a rounded quadrangle with four corners. The semiconductor package 100 may have a rectangular shape whose width in the first direction (X-axis direction) is longer than its width in the second direction (Z-axis direction) in a plan view. The external terminals 102 may be arranged in two rows along the first direction. The external terminals 102 include external terminals 102A1, 102A2, and 102A3 included in a first row along the first direction (X-axis direction) and external terminals 102B1, 102B2, and 102B3 included in a second row along the first direction (X-axis direction) that faces the first row across the center P of the semiconductor package 100. The centers of gravity of the external terminals 102A1, 102A2, and 102A3 do not overlap with the centers of gravity of the external terminals 102B1, 102B2, and 102B3 in a first direction (X-axis direction) and a second direction (Z-axis direction) intersecting the first direction. That is, the external terminals 102A1, 102A2, and 102A3 and the external terminals 102B1, 102B2, and 102B3 are arranged in a staggered pattern along the first direction.

[0052] The spacing in the first direction between the external terminals 102A1, 102A2, and 102A3 is the same as the spacing in the first direction between the external terminals 102B1, 102B2, and 102B3, and the external terminals 102A1, 102A2, and 102A3 are shifted in the first direction from the external terminals 102B1, 102B2, and 102B3. The external terminals 102A1, 102A2, and 102A3 are also shifted in the second direction from the external terminals 102B1, 102B2, and 102B3. Here, "same" includes the concept of "approximately the same." That is, the intervals in the first direction between the plurality of external terminals 102A1, 102A2, and 102A3 and the intervals in the first direction between the plurality of external terminals 102B1, 102B2, and 102B3 do not have to be completely the same.

[0053] As ICs such as the semiconductor package 100 become smaller, the proportion of external terminals in the surface area of ​​the IC is increasing. Furthermore, when the semiconductor package 100 is placed in the air-core portion of the coil 200, the gap in the air-core portion is narrow, so the shape of the semiconductor package 100 is preferably an elongated rectangle. By arranging multiple external terminals 102 in a staggered pattern along the first direction on the surface of such an elongated semiconductor package 100, as shown in FIG. 4, the width of the semiconductor package 100 in the second direction can be narrowed. By arranging the multiple external terminals 102B1, 102B2, and 102B3 so that each of the multiple external terminals 102B1, 102B2, and 102B3 only partially overlaps with each other in the second direction, the width of the semiconductor package 100 in the second direction can be narrowed. By arranging the multiple external terminals 102 in a staggered pattern, the semiconductor package 100 can be downsized in the second direction (width direction) while maintaining the same terminal shape or number. Therefore, even if the semiconductor package 100 is made smaller in size in the width direction, it is possible to prevent a decrease in stability during mounting.

[0054] The width of the semiconductor package 100 in the first direction may be 1.65 times or more longer than the width in the second direction. The width of the semiconductor package 100 in the first direction may be 2.5 times or more longer than the width in the second direction. The total area of ​​the multiple external terminals 102 in a planar view may be 14% or more of the area of ​​the semiconductor package 100 in a planar view. The total area of ​​the multiple external terminals 102 in a planar view may be 19% or more of the area of ​​the semiconductor package 100 in a planar view.

[0055] FIG. 5 is a schematic diagram of the cross section AA shown in FIG. 4. In this embodiment, the semiconductor package 100 is a wafer-level chip-size package (WL-CSP) type semiconductor package. However, the semiconductor package 100 may be a fan-out wafer-level package (FO-WLP) type semiconductor package. The semiconductor package 100 includes a silicon substrate 110, a redistribution layer 120 disposed on a first surface of the silicon substrate 110, and an encapsulant 130 disposed on at least a surface of the redistribution layer 120 opposite to the surface of the silicon substrate 110. The silicon substrate 110 incorporates a semiconductor chip. The semiconductor chip may include a magnetic sensor 112, an amplifier 113, an A / D converter 114, a PID control unit 115, a D / A converter 116, and an output driver 117.

[0056] In a camera module 10 including such a semiconductor package 100, the lens unit 40 is becoming heavier as the pixel density increases. The image sensor 302 tends to become larger as the pixel density increases, resulting in higher temperatures. Furthermore, as the lens unit 40 becomes heavier, the current required to drive the lens unit 40 increases, resulting in a rise in temperature. This temperature rise also affects the magnetic sensor 112 built into the semiconductor package 100. Specifically, the offset of the magnetic sensor 112 increases as the temperature rises. The larger the offset of the magnetic sensor 112, the lower the S / N ratio. When the camera module 10 controls the lens unit 40 using a magnetic sensor 112 with poor temperature characteristics and a low S / N ratio, noise suppression performance deteriorates, increasing the error between the actual position of the lens unit 40 and the target position, making it difficult to accurately control the position of the lens unit 40. This makes it difficult to achieve high-precision image stabilization.

[0057] FIG. 6 shows the relationship between the movement distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112. Line A1 shows the relationship between the movement distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112 for a standard camera. Line A2 shows the relationship between the movement distance of the lens unit 40 and the magnitude of the magnetic field detected by the magnetic sensor 112 for a high-performance camera with increased pixel count. As shown in FIG. 6, the movement distance of the lens unit 40 in response to a change in the magnitude of the magnetic field for a high-performance camera is longer than the movement distance of the lens unit 40 in response to a change in the magnitude of the magnetic field for a standard camera. In other words, even if the signal error detected by the magnetic sensor 112 is the same, the position error of the lens unit 40 in a high-performance camera is larger than that of a standard camera. As the pixel count increases, the position error of the lens unit 40 becomes more noticeable as image blur. In other words, a decrease in the S / N ratio of the magnetic sensor 112 has a more significant impact on high-performance cameras, such as making it impossible to perform high-precision image stabilization. Therefore, it is desirable to minimize the impact of the offset amount of the magnetic sensor 112.

[0058] However, as shown in Fig. 7, when the multiple Hall elements 111 constituting the magnetic sensor 112 are arranged side by side in the first direction (X-axis direction) and the second direction (Z-axis direction), the multiple external terminals 102 are arranged in a staggered pattern, which causes variations in the size of the overlapping area where the Hall elements 111 and the external terminals 102 overlap in a plan view. If the size of the overlapping area varies, the change in the magnitude of the stress applied to the Hall element 111 due to changes in the temperature or humidity around the semiconductor package 100 also varies. If the stress applied to the Hall element 111 changes, the offset amount included in the signal output from the Hall element 111 also changes.

[0059] Therefore, in this embodiment, in order to offset the change in the offset amount, a plurality of Hall elements 111 are arranged point-symmetrically with respect to the center P of the semiconductor package 100 in a plan view, as shown in FIG. 8 or FIG.

[0060] The Hall element 111S1 and the Hall element 111S2 are arranged point-symmetrically with respect to the center P. The Hall element 111S3 and the Hall element 111S4 are arranged point-symmetrically with respect to the center P.

[0061] When the semiconductor package 100 is divided into a first event region, a second event region, a third event region, and a fourth event region in a plan view by a first axis L1 along a first direction (X-axis direction) passing through the center P and a second axis L2 along a second direction (Z-axis direction), the Hall elements 111S1 and 111S3 may be arranged on the first event region. The Hall elements 111S2 and 111S4 may be arranged on a third event region that is point-symmetrical to the first event region with respect to the center P. Alternatively, the Hall elements 111S1 and 111S3 may be arranged on the second event region. The Hall elements 111S2 and 111S4 may be arranged on a fourth event region that is point-symmetrical to the second event region with respect to the center P.

[0062] 8, the Hall elements 111S1 and 111S3 are arranged side by side in a first row along the first direction. The Hall elements 111S2 and 111S4 are arranged side by side in a second row on the opposite side of the first row with the center P in between. The Hall elements 111S1 and 111S3 do not overlap with the Hall elements 111S2 and 111S4 in the second direction.

[0063] In FIG. 9, the Hall elements 111S1 and 111S3 are arranged side by side in a first row along the first direction. The Hall elements 111S2 and 111S4 are arranged side by side in a second row on the opposite side of the first row with a center P in between them along the first direction. The Hall element 111S1 does not overlap with the Hall elements 111S2 and 111S4 in the second direction. The Hall element 111S2 does not overlap with the Hall elements 111S1 and 111S3 in the second direction. On the other hand, the Hall element 111S3 overlaps with the Hall element 111S4 in the second direction. That is, the Hall elements 111S3 and 111S4 are arranged side by side in the second direction.

[0064] Here, assuming that the output of the Hall element 111S1 is S1, the output of the Hall element 111S2 is S2, the output of the Hall element 111S3 is S3, and the output of the Hall element 111S4 is S4, the magnetic sensor 112 outputs the result of a sum / difference operation or a sum operation of S1, S2, S3, and S4 as a signal indicating the magnitude of the magnetic field. That is, the magnetic sensor 112 outputs (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) or (S1+S2+S3+S4) as a signal indicating the magnitude of the magnetic field. By arranging each pair of Hall elements 111 point-symmetrically with respect to the center P, and adding up the outputs of each pair of Hall elements 111, it is possible to cancel out noise, i.e., offset, included in the output of each Hall element 111.

[0065] The PID control unit 115 may output a drive signal for controlling the coil 200, which functions as a drive unit that changes the position or attitude of the magnet 32 ​​relatively with respect to the semiconductor package 100, based on the sum (S1+S2+S3+S4) of outputs indicating the magnitude of the magnetic fields output from the Hall elements 111S1, 111S2, 111S3, and 111S4. The amplifier 113 may amplify the sum (S1+S2+S3+S4) of the outputs and provide the sum of the outputs to the PID control unit 115 via the A / D converter 114.

[0066] The PID control unit 115 may output a drive signal further based on the difference ((S1+S3)-(S2+S4)) between the sum (S1+S3) of the outputs indicating the magnitude of the magnetic fields output from the Hall elements 111S1 and 111S3 and the sum (S2+S4) of the outputs indicating the magnitude of the magnetic fields output from the Hall elements 111S2 and 111S4.

[0067] The PID control unit 115 may output a drive signal based on the ratio (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) of the sum (S1+S2+S3+S4) of outputs indicating the magnitude of the magnetic fields output from the Hall elements 111S1, 111S2, 111S3, and 111S4 to the difference ((S1+S3)-(S2+S4)). The amplifier 113 may amplify the ratio (S1+S2+S3+S4) / ((S1+S3)-(S2+S4)) and provide the sum of the outputs to the PID control unit 115 via the A / D converter 114.

[0068] 10 , the multiple Hall elements 111 include Hall elements 111S1 and S3 belonging to a first group and Hall elements 111S2 and S4 belonging to a second group. The Hall element 111S1 may be at least partially covered in a plan view by the external terminal 102A1 of the multiple external terminals 102A1, 102A2, and 102A3. The Hall element 111S2 may be at least partially covered in a plan view by the external terminal 102B1 of the multiple external terminals 102B1, 102B2, and 102B3. A region R1 of the Hall element 111S1 covered in a plan view by the external terminal 102A1 and a region R2 of the Hall element 111S2 covered in a plan view by the external terminal 102B1 are point-symmetric with respect to the center P of the semiconductor package 100 in a plan view. The Hall element 111S3 and the Hall element 111S4 are arranged point-symmetrically with respect to the center P of the semiconductor package 100 in a plan view.

[0069] 11, the Hall elements 111S1 and 111S may be entirely covered by the external terminal 102A1 in a plan view, and the Hall elements 111S2 and 111S4 may be entirely covered by the external terminal 102B1 in a plan view.

[0070] 12, the Hall element 111S1 may be completely covered by the external terminal 102A1 in a planar view. The Hall element 111S2 may be completely covered by the external terminal B1 in a planar view. On the other hand, the Hall elements 111S3 and 111S4 may not be partially covered by any of the multiple external terminals 102. In other words, the Hall elements 111S3 and 111S4 may not overlap with any of the multiple external terminals 102 in a planar view.

[0071] 13, the Hall element 111S1 may be partially covered by the external terminal 102A1 in a plan view. The Hall element 111S2 may be partially covered by the external terminal B1 in a plan view. On the other hand, the Hall elements 111S3 and 111S4 may not be partially covered by any of the multiple external terminals 102. In other words, the Hall elements 111S3 and 111S4 may not overlap with any of the multiple external terminals 102 in a plan view.

[0072] 14, the Hall element 111S1 may be completely covered by the external terminal 102A1 in a planar view. The Hall element 111S2 may be completely covered by the external terminal 102B1 in a planar view. The Hall element 111S3 may be partially covered by the external terminal 102A1 in a planar view. The Hall element 111S4 may be partially covered by the external terminal 102B1 in a planar view.

[0073] 15, the Hall element 111 can be represented by an equivalent circuit in which four resistors R1, R2, R3, and R4, each with a resistance value R, are bridge-connected. The Hall element 111 has a pair of electrodes D1 and D2 facing each other in a first direction, and a pair of electrodes D3 and D4 facing each other in a second direction.

[0074] The four resistors R1, R2, R3, and R4 have the same resistance value R. However, if the stress applied to each of the four resistors R1, R2, R3, and R4 is different, the resistance values ​​of the four resistors R1, R2, R3, and R4 will vary. As a result, the offset amount included in the signal output from the Hall element 111 will change.

[0075] To reduce such fluctuations in the offset, it is conceivable to switch the pair of electrodes output from the Hall element 111 and add the two outputs. That is, at a first timing, a signal Sa corresponding to the magnitude of the magnetic field is output from the pair of electrodes D1 and D2 of the Hall element 111, and at a second timing following the first timing, a signal Sb corresponding to the magnitude of the magnetic field is output from the pair of electrodes D3 and D4 of the Hall element 111, and the signals Sa and Sb are added together to reduce the offset. However, this requires time to switch the output electrodes, resulting in a slow response. For example, when moving the lens unit 40 to perform focusing or image shake correction, such a delayed response may cause a delay in focusing or may prevent high-precision image shake correction.

[0076] Therefore, the output electrodes of the Hall elements 111 arranged symmetrically around a point are set as pairs of electrodes in different directions. By adding the outputs of these Hall elements 111, the offset amount can be reduced, just as in the case of switching electrodes. Furthermore, there is no response delay due to electrode switching. By reducing the offset amount in this way, not only can the response delay be suppressed, but the magnetic sensor 112 can calculate S1+S2 and S1+S3 sequentially in a time-division manner, thereby calculating the output of each Hall element 111 without sacrificing the AD range.

[0077] 14, the Hall elements 111S1, 111S2, 111S3, and 111S4 each have a pair of electrodes D1 and D2 facing each other in a first direction and a pair of electrodes D3 and D4 facing each other in a second direction intersecting the first direction. In the Hall elements 111S1 and 111S4, the pair of electrodes D1 and D2 are output electrodes. In the Hall elements 111S2 and 111S3, the pair of electrodes D3 and D4 are output electrodes.

[0078] In the configuration shown in FIG. 14, the Hall element 111S1 is only partially covered by the external terminal 102A1 in a plan view. As a result, the stress acting on the Hall element 111S1 varies. FIG. 16A shows an equivalent circuit of the Hall element 111S1. As shown in FIG. 16A, of the four bridge-connected resistors R1, R2, R3, and R4 in the Hall element 111S1, the resistance value of the resistor R1 is R+r, and the resistance values ​​of the other three resistors R2, R3, and R4 are R. That is, the resistance value of the resistor R1 is different from the resistance values ​​of the resistors R2, R3, and R4.

[0079] FIG. 16B shows an equivalent circuit of the Hall element 111S2. Like the Hall element 111S1, the Hall element 111S2 is only partially covered by the external terminal 102B1 in a planar view. As a result, the stress acting on the Hall element 111S2 varies. However, the position of the area of ​​the Hall element 111S2 covered by the external terminal 102B1 in a planar view is different from the position of the area of ​​the Hall element 111S1 covered by the external terminal 102A1 in a planar view. The area of ​​the Hall element 111S2 covered by the external terminal 102B1 in a planar view is point-symmetrical with the area of ​​the Hall element 111S1 covered by the external terminal 102A1 in a planar view, with respect to the center P. Therefore, among the four bridge-connected resistors R1, R2, R3, and R4 in the Hall element 111S2, the resistance value of resistor R3 is R+r, and the resistance values ​​of the other three resistors R1, R2, and R4 are R. That is, the resistance value of the resistor R3 is different from the resistance values ​​of the resistors R1, R2, and R4.

[0080] FIG. 16C shows the equivalent circuit of the Hall element 111S3, and FIG. 16D shows the equivalent circuit of the Hall element 111S4. The Hall element 111S3 is completely covered by the external terminal 102A1 in a plan view, and the Hall element 111S4 is completely covered by the external terminal 102B1 in a plan view. As a result, there is no variation in the stress applied to the Hall elements 111S3 and 111S4. Therefore, the resistance values ​​of the four bridge-connected resistors R1, R2, R3, and R4 in the Hall elements 111S3 and 111S4 are the same.

[0081] In the equivalent circuit of the Hall element 111S1 shown in FIG. 16A, the offset voltage V offset_1 is defined by equation (1). V offset_1 =V 1_1 -V 2_1 =((R+r) / (2R+r)-1 / 2)×V in =r / (2×(2R+r)) (1)

[0082] In the equivalent circuit of the Hall element 111S2 shown in FIG. 16B, an offset voltage V offset_1 is defined by equation (2). V offset_1 =V 1_2 -V 2_2 =((R / (2R+r))-1 / 2)×V in =-r / (2×(2R+r)) (2)

[0083] In the equivalent circuit of the Hall element 111S3 shown in FIG. 16C, the offset voltage V offset_3 is defined by equation (3). V offset_3 =V 1_3 -V 2_3 =0 (3)

[0084] In the equivalent circuit of the Hall element 111S4 shown in FIG. 16D, the offset voltage V offset_4 is defined by equation (4). V offset_3 =V 1_4 -V 2_4 =0 (4)

[0085] From the above, when the outputs of the Hall elements 111S1, 111S2, 111S3, and 111S4 are all added together, an offset voltage V corresponding to the offset amount output from the magnetic sensor 112 is obtained. offset is defined by equation (5), and the offset amounts occurring in the Hall elements 111S1 and 111S2 are cancelled out to become zero. V offset =V offset_1 +V offset_2 +V offset_3 +V offset_4 =r / (2×(2R+r))-r / (2×(2R+r))=0···(5)

[0086] 17 shows the function of each external terminal 102 of the semiconductor package 100. In a plan view, the external terminal 102A1 and the external terminal 102A3 arranged in the second event region are a pair of power supply terminals. The external terminal 102B2 arranged in the third event region and the external terminal 102B1 arranged in the fourth event region are a pair of drive terminals that output a drive signal for the coil 200. The external terminal 102A2 arranged in the first event region and the external terminal 102B3 arranged in the fourth event region are a pair of communication terminals for communicating with the control unit of the camera module 10.

[0087] The Hall element 111S1 may at least partially overlap with the external terminal 102A1, which is one of a pair of power supply terminals, in a planar view, and the Hall element 111S2 may at least partially overlap with the external terminal 102B1, which is one of a pair of drive terminals, in a planar view. In this way, the Hall element 111 may overlap with an external terminal other than the pair of communication terminals in a planar view. However, it is preferable that the Hall element 111 does not overlap with the pair of communication terminals in a planar view. If the Hall element 111 overlaps with one of the pair of communication terminals in a planar view, the Hall element 111 and the pair of communication terminals will be affected by noise from each other, resulting in significant adverse effects.

[0088] Each of the external terminals 102A1 and 102B1 that at least partially overlap with the Hall element 111 in plan view is preferably the external terminal that is located closest to the center P of the semiconductor package 100 in plan view among the plurality of external terminals 102.

[0089] The external terminals 102A1 and 102B1, which at least partially overlap with the Hall element 111 in a plan view, do not need to have a circular shape in a plan view as long as they are point-symmetric with respect to the center P of the semiconductor package 100 in a plan view.

[0090] FIG. 18 shows the wiring configuration in the redistribution layer 120 of the semiconductor package 100. By arranging the multiple external terminals 102 in a staggered pattern along the first direction, there is space between each external terminal 102 and the semiconductor chip in both the first and second directions. Therefore, the wiring for electrically connecting the external terminals 102 to the semiconductor chip can be extended relatively long in both the first and second directions. For example, the redistribution layer 120 may include a wiring LB1 extending from the external terminal 102B1 along the first direction by 100 μm or more and electrically connecting to the semiconductor chip. That is, the portion kb1 of the wiring LB1 extending along the first direction may be 100 μm or more. Similarly, the redistribution layer 120 may include a wiring LB3 extending from the external terminal 102B3 along the first direction by 100 μm or more and electrically connecting to the semiconductor chip. That is, the portion kb3 of the wiring LB3 extending along the first direction may be 100 μm or more. By routing the wiring along the eleventh direction or the second direction in this way, the wiring can be achieved using the shortest route, and the area of ​​the semiconductor package 100 in plan view can be reduced.

[0091] The wiring LB1 includes a portion kb1 that extends on a line in the first direction that passes through the center of the external terminal 102B1. The wiring LB3 includes a portion kb3 that extends on a line in the first direction that passes through the center of the external terminal 102B3.

[0092] The redistribution layer 120 may include a wiring LB2 that extends 100 μm or more from the external terminal 102B2 along the second direction and is electrically connected to the semiconductor chip. The wiring LB2 includes a portion kb2 that extends on a line that passes through the center of the external terminal 102B2 along the second direction.

[0093] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0094] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0095] 10 Camera Module 20 base 30 Retaining frame 32 Magnet 40 Lens unit 100 Semiconductor Packages 102 External terminal 110 Silicon substrate 111 Hall element 112 Magnetic Sensor 113 Amplifier 114 A / D converter 115 PID control unit 116 D / A converter 117 Output Driver 120 Redistribution layer 130 Encapsulating material 200 coils 210 Position command generation section 300 boards 302 Image sensor

Claims

1. A semiconductor package having a semiconductor chip having at least a first Hall element and a second Hall element, and a plurality of external terminals provided on a first surface of the semiconductor chip, the semiconductor package having a rectangular shape with a first direction as a long side in a plan view and a second direction perpendicular to the first direction as a short side, the first Hall element is disposed symmetrically with respect to the second Hall element with respect to a center point of the first surface of the semiconductor package in a plan view, the plurality of external terminals include a plurality of first external terminals arranged to form a row along the first direction and a plurality of second external terminals arranged to form a row along the first direction, a first terminal row formed from the plurality of first external terminals and a second terminal row formed from the plurality of second external terminals are located at different positions in the second direction in a plan view, and the plurality of first external terminals and the plurality of second external terminals are arranged in a staggered pattern on the first surface; a semiconductor package in which, in a planar view, the first Hall element is arranged within the first terminal row formed from the plurality of first external terminals and on the inner side of both ends, and the second Hall element is arranged within the second terminal row formed from the plurality of second external terminals and on the inner side of both ends.

2. the plurality of first external terminals or the plurality of second external terminals include a pair of communication terminals for communication with the outside of the semiconductor package, The semiconductor package according to claim 1 , wherein the first Hall element and the second Hall element are arranged so as not to overlap the pair of communication terminals in a plan view.

3. the semiconductor chip has a plurality of Hall elements including the first Hall element and the second Hall element, the plurality of Hall elements include the first Hall element and the third Hall element belonging to a first group, and the second Hall element and the fourth Hall element belonging to a second group; The semiconductor package according to claim 2 , wherein the third Hall element and the fourth Hall element are arranged point-symmetrically with respect to the point at the center of the semiconductor package in a plan view.

4. The semiconductor package according to claim 3 , wherein the third Hall element and the fourth Hall element are arranged so as not to overlap the pair of communication terminals in a plan view.

5. 5. The semiconductor package according to claim 4, wherein, in a plan view, the first Hall element and the third Hall element belonging to a first group are arranged along the first terminal row, and the second Hall element and the fourth Hall element belonging to a second group are arranged along the second terminal row.

6. The semiconductor package according to claim 5 , wherein a width of the semiconductor package in the first direction is greater than a width of the semiconductor package in a second direction intersecting the first direction.

7. The semiconductor package according to claim 6 , wherein the width in the first direction is at least 1.65 times longer than the width in the second direction.

8. The semiconductor package according to claim 6 , wherein the width in the first direction is at least 2.5 times longer than the width in the second direction.

9. 9. The semiconductor package according to claim 7, wherein the total area of ​​said plurality of external terminals in a plan view is 14% or more of the area of ​​said semiconductor package in a plan view.

10. 9. The semiconductor package according to claim 7, wherein the total area of ​​the plurality of external terminals in a plan view is 19% or more of the area of ​​the semiconductor package in a plan view.

11. 6. The semiconductor package according to claim 5, wherein the external terminals belonging to the first terminal row and the external terminals belonging to the second terminal row that are closest to the center of the semiconductor package in a planar view are point-symmetric with respect to the center of the semiconductor package in a planar view.

12. a rewiring layer laminated on the first surface side of the semiconductor chip and electrically connected to the semiconductor chip; 6. The semiconductor package according to claim 1, wherein at least one of the plurality of external terminals is electrically connected to the first Hall element and the second Hall element via the rewiring layer.

13. The semiconductor package according to claim 12 , wherein the redistribution layer includes wiring extending from at least one of the plurality of external terminals along the first direction by 100 μm or more and electrically connected to the semiconductor chip.

14. The semiconductor package according to claim 13 , wherein the wiring has a portion that extends on a line that passes through a center of the at least one external terminal in the first direction in a plan view.

15. The semiconductor package of claim 12 , wherein the redistribution layer includes wiring extending from at least one of the plurality of external terminals along a second direction intersecting the first direction by 100 μm or more and electrically connected to the semiconductor chip.

16. The width of the first terminal row in the first direction includes the overall width of each of the first external terminals arranged at both ends of the first terminal row in the first direction, the width of the second terminal row in the first direction includes the overall width of each of the second external terminals arranged at both ends of the second terminal row in the first direction, 3. The semiconductor package according to claim 1, wherein, in a plan view, the first Hall element is arranged inside a width of the first terminal row in the first direction, and the second Hall element is arranged inside a width of the second terminal row in the first direction.

17. A semiconductor package as described in Claim 16, wherein the center of gravity of each of the plurality of first external terminals does not overlap with the center of gravity of each of the plurality of second external terminals in the first direction and the second direction.

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