Photoelectric conversion device, imaging system, mobile object

Abstract

To solve a problem in which the power consumption of pixels increases when the avalanche multiplication is frequently performed.SOLUTION: A photoelectric conversion device includes a photodiode that performs avalanche multiplication, a counter that generates a count signal that counts a pulse generated by the avalanche multiplication for a predetermined period, and a control circuit that controls the photodiode in a standby state in which the avalanche multiplication is possible and in a rest state in which the avalanche multiplication is stopped on the basis of a count signal in a predetermined period.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, an imaging system, and a moving object. [Background technology]

[0002] There is known a photon counting type photoelectric conversion device that digitally counts the number of photons incident on a light receiving section that performs avalanche multiplication and outputs the counted value as a digital signal from a pixel. Patent Document 1 describes an operation in which, after a photodiode that performs avalanche multiplication has performed avalanche multiplication, the operation of recharging the photodiode to perform avalanche multiplication again is suspended for a predetermined period of time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097519 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, there is no consideration given to reducing pixel power consumption in response to the brightness of incident light, and therefore no setting for pause operation in response to an increase in the count value. As a result, there is a problem that pixel power consumption increases if avalanche multiplication is performed frequently, for example, when high-intensity light is incident on a pixel. [Means for solving the problem]

[0005] The present invention has been made in view of the above-mentioned problems, and one aspect thereof is a photodiode having an avalanche multiplication type connected to be supplied with a first voltage and a second voltage, a counter that counts pulses generated by the photodiode and holds the count value, a control circuit that controls the supply of the first voltage to the photodiode, and a correction unit that corrects the count value output from the counter, wherein a signal input to the control circuit has a first level that supplies the first voltage to the photodiode via the control circuit and a second level that does not supply the first voltage to the photodiode, When the count value output from the counter exceeds a threshold value, a slope of the count value relative to the number of photons incident on the photodiode is smaller than a slope a of the count value relative to the number of photons incident on the photodiode until the count value output from the counter reaches the threshold value, The correction unit corrects the count value output from the counter. The aforementioned When the threshold value is exceeded, the slope of the count value relative to the number of photons incident on the photodiode is determined by the number of photons incident until the count value output from the counter reaches the threshold value and the slope of the count value. The aforementioned For count values ​​in a range different from the slope a, The aforementioned This photoelectric conversion device is characterized by correcting the angle to match the inclination a. [Effects of the Invention]

[0006] The present invention makes it possible to reduce the power consumption of a pixel. [Brief explanation of the drawings]

[0007] [Figure 1] Block diagram showing the schematic configuration of a photoelectric conversion device [Figure 2] A diagram showing the schematic configuration of a pixel [Figure 3] FIG. 1 shows an example of a pixel configuration. [Figure 4] Flowchart showing pixel operation [Figure 5] Timing diagram showing pixel operation [Figure 6] A diagram showing the relationship between the number of incident photons and the count signal [Figure 7] FIG. 1 shows an example of a pixel configuration. [Figure 8] FIG. 1 shows an example of a pixel configuration. [Figure 9]FIG. 1 shows an example of a pixel configuration. [Figure 10] FIG. 1 shows an example of the configuration of a pixel section [Figure 11] FIG. 1 shows an example of the configuration of a pixel section [Figure 12] Timing diagram showing pixel operation [Figure 13] Block diagram showing the schematic configuration of an imaging system [Figure 14] FIG. 1 is a diagram showing an example of the configuration of an imaging system and a moving object; DETAILED DESCRIPTION OF THE INVENTION

[0008] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

[0009] Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. Fig. 2 is a block diagram showing a schematic configuration of a pixel of the photoelectric conversion device according to this embodiment. Fig. 3 is a circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment.

[0010] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel region 10, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output circuit 60, and a control circuit .

[0011] The pixel region 10 has a plurality of pixels P arranged in a matrix across multiple rows and columns. Fig. 1 shows 36 pixels P arranged in six rows (row 0) to row 5 and six columns (column 0) to column 5, along with reference symbols indicating the row and column numbers. For example, the pixel P arranged in the first row and fourth column is assigned the reference symbol "P14."

[0012] The number of rows and columns of the pixel array constituting the pixel region 10 is not particularly limited. Furthermore, the pixels P do not necessarily have to be arranged two-dimensionally in the pixel region 10. For example, the pixel region 10 may be composed of a single pixel P, or the pixels P may be arranged one-dimensionally in the row direction or column direction in the pixel region 10.

[0013] A control line PVSEL is arranged in each row of the pixel array of the pixel region 10, extending in a first direction (the horizontal direction in FIG. 1). The control line PVSEL is connected to each of the pixels P arranged in the first direction, and serves as a signal line common to these pixels P. The first direction in which the control line PVSEL extends may be referred to as the row direction or the horizontal direction. Note that in FIG. 1, the control line PVSEL is shown together with a reference symbol indicating the row number. For example, the control line in the first row is designated by the reference symbol "PVSEL[1]."

[0014] The control line PVSEL of each row is connected to a vertical selection circuit 30. The vertical selection circuit 30 is a circuit section that supplies control signals for driving signal generation circuits (not shown) in the pixels P to the pixels P via the control lines PVSEL. The vertical scanning circuit 30 controls the start and end of a period during which a counter included in the pixels 11, which will be described later, accumulates counts.

[0015] In each column of the pixel array in the pixel region 10, an output line POUT is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The output line POUT is connected to each of the pixels P aligned in the second direction and serves as a signal line common to these pixels P. The second direction in which the output line POUT extends may be referred to as the column direction or vertical direction. Note that in FIG. 1, the output line POUT is shown together with a symbol indicating the column number. For example, the output line in the fourth column is labeled "POUT4." Each of the output lines POUT has n signal lines for outputting an n-bit digital signal.

[0016] The output line POUT is connected to a signal processing circuit 40. The signal processing circuits 40 are provided corresponding to each column of the pixel array in the pixel region 10, and are connected to the output line POUT of the corresponding column. The signal processing circuit 40 has a function of holding a signal output from the pixel P via the output line POUT of the corresponding column. Since the signal output from the pixel P is an n-bit signal input via n signal lines of the output lines POUT, each of the signal processing circuits 40 has at least n holding units for holding each bit of the signal.

[0017] The horizontal selection circuit 50 is a circuit section that supplies the signal processing circuit 40 with a control signal for reading out a signal from the signal processing circuit 40. The horizontal selection circuit 50 supplies a control signal to the signal processing circuit 40 of each column via a control line PHSEL. Upon receiving the control signal from the horizontal selection circuit 50, the signal processing circuit 40 outputs the signal held in the holding section to the output circuit 60 via a horizontal output line HSIG. Note that in FIG. 1, the control line PHSEL is shown together with a symbol indicating the column number. For example, the control line for the fourth column is assigned the symbol "PHSEL[4]". The horizontal output line HSIG has n signal lines for outputting an n-bit digital signal.

[0018] The output circuit 60 is a circuit section for outputting a signal supplied via the horizontal output line HSIG as an output signal SOUT to the outside of the photoelectric conversion device 100. The control circuit 70 is a circuit section for supplying control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60. Note that at least some of the control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60 may be supplied from the outside of the photoelectric conversion device 100.

[0019] As shown in FIG. 2, each pixel P includes an avalanche multiplication photodiode PD, a pixel control circuit 12, a selector 13, a PD control circuit 14, a waveform generation circuit 15, and a counter 16.

[0020] In this specification, the pixel control circuit 12 may be referred to as a control signal generation unit, and the PD control circuit 14 may be referred to as a cathode voltage control unit.

[0021] This will be explained with reference to FIG.

[0022] The pixel control circuit 12 outputs the signals P1, P2, and P3 to the selector 13. The selector 13 outputs one of the signals P1, P2, and P3 input from the pixel control circuit 12 to the PD control circuit 14 as a signal Pctrl.

[0023] The PD control circuit 14 has a PMOS transistor and an NMOS transistor connected in series in an electrical path between voltages Vdd and Vss. In this embodiment, voltage Vdd is set to approximately 3 V. Meanwhile, voltage Vss is set to ground voltage, and voltage Va is set to approximately −20 V. Note that voltages Vdd, Vss, and Va may be changed as appropriate.

[0024] A signal Pctrl is input to the gates of the PMOS transistor and the NMOS transistor. The PMOS transistor is a recharge circuit that performs a recharge operation to return the voltage Vcath to a voltage close to the voltage Vdd after the voltage Vcath drops due to avalanche multiplication. When the voltage Vcath returns to a voltage close to the voltage Vdd, the photodiode PD enters a state where avalanche multiplication is possible (avalanche multiplication standby state). In this specification, the period in the avalanche multiplication standby state is referred to as the standby period, and the period in which avalanche multiplication is paused is referred to as the pause period.

[0025] The cathode of the photodiode PD and the waveform generating circuit 15 are connected to a node where the PMOS transistor and the NMOS transistor are connected.

[0026] The anode terminal of the photodiode PD is connected to a power supply node of a voltage Va. The voltage Va is typically a negative high voltage. The cathode of the photodiode PD is connected to a PD control circuit 14. The voltage of the cathode of the photodiode PD is referred to as a voltage Vcath.

[0027] The waveform generating circuit 15 has an SR latch circuit 151 and a NOR circuit 152. The cathode of the photodiode PD is connected to the S terminal of the SR latch circuit 151, and a voltage Vcath is input to the S terminal. A signal Pctrl is input to the R terminal. The input section of the NOR circuit 152 is connected to the cathode of the photodiode PD and the SR latch circuit 151. The NOR circuit 152 receives the voltage Vcath and an inverted signal of the signal Vlat output by the SR latch circuit 151. The output section of the NOR circuit 152 is connected to the counter 16. The counter 16 counts and integrates the pulses of the signal Pp output by the NOR circuit 152 for a predetermined period (a period set by the vertical scanning circuit 30). The counter 16 outputs a count signal, which is the result of integrating this count, to the outside of the pixel as a signal POUT. The integration period set by the vertical scanning circuit 30 for count integration can be, for example, a period corresponding to one frame of an image formed using signals output by the photoelectric conversion device. Alternatively, one frame can be divided into multiple fields, and a period corresponding to one of the multiple fields can be set as the count integration period. The counter 16 integrates the count from the start to the end of the integration period. After the integration is completed and the readout of the signal POUT is completed, the count signal of the counter 16 is reset to its initial value.

[0028] The counter 16 is also connected to the selector 13. The selector 13 switches the signal Pctrl to one of the signals P1 to P3 depending on whether the count value of the counter 16 has reached a threshold value. In other words, the selector 13 is a control circuit that switches which of the signals P1 to P3 to output based on the count signal. In this way, the selector 13 is a selection circuit that switches between a standby state for performing avalanche multiplication and a pause state in which avalanche multiplication is paused based on the count signal.

[0029] When the reverse bias voltage applied between the anode and cathode of the photodiode PD is equal to or greater than the breakdown voltage Vbd, the photodiode PD generates an avalanche current in response to the incidence of a photon. The avalanche current flowing through the photodiode PD changes the voltage Vcath at the cathode of the photodiode PD. The change in voltage Vcath changes the signal Pp output by the waveform shaping circuit 15, causing a photon detection pulse to be output to the counter 16.

[0030] When the signal Pctrl output by the selector 13 is at a low level, the PD control circuit 14 performs a recharge operation when the voltage Vcath drops due to an avalanche current. That is, a current flows from the node of voltage Vdd to the node of voltage Vcath via the PMOS transistor, causing the voltage Vcath to rise. Then, the voltage between the anode and cathode of the photodiode PD again becomes equal to or greater than the breakdown voltage Vbd. This allows the photodiode PD to perform avalanche multiplication again.

[0031] On the other hand, when the signal Pctrl goes to a high level, the voltage Vcath becomes constant at a value close to the voltage Vss, and the photodiode PD therefore goes into a resting state where it does not perform avalanche multiplication.

[0032] In this embodiment, when the count value of the counter 16 reaches a threshold value, the signal level of the signal Pctrl output by the selector 13 transitions from low to high. Then, the pixel of this embodiment lengthens the pause period of avalanche multiplication of the photodiode PD in response to an increase in the count value.

[0033] FIG. 4 is a flowchart showing the operation of the pixel of this embodiment.

[0034] In step S101, a control circuit (not shown) resets the count value of the counter 16 to an initial value. Typically, the initial value is a value where all bit values ​​are 0.

[0035] In step S102, if the current time is within the count period in which the counter 16 counts, the operation proceeds to step S103. On the other hand, if the current time is not within the count period, the operation ends.

[0036] In step S103, the counter 16 performs a counting operation to count the pulses of the signal Pp.

[0037] In step S104, the operation branches depending on whether the count value of counter 16 has reached threshold value N1. If the count value has not reached threshold value N1, the operation returns to step S102 again. On the other hand, if the count value has reached threshold value N1, the operation proceeds to step S105.

[0038] In step S105, the avalanche multiplication interval is set to the interval Int1. As will be described later, this interval is set by the selector 13 setting the signal to be output as the signal Pctrl to the signal P2. In other words, an avalanche pause period of length Int1 is provided between avalanche wait periods.

[0039] In step S106, if the current time is within the count period in which counter 16 counts, the operation proceeds to step S107. On the other hand, if the current time is not within the count period, the operation proceeds to step S113.

[0040] In step S107, the counter 16 performs a counting operation to count the pulses of the signal Pp.

[0041] In step S108, the operation branches depending on whether the count value of counter 16 has reached threshold value N2. If the count value has not reached threshold value N2, the operation returns to step S106. On the other hand, if the count value has reached threshold value N2, the operation proceeds to step S109.

[0042] In step S109, the avalanche multiplication interval is set to an interval Int2 that is longer than the interval Int1. As will be described later, this interval is set by the selector 13 setting the signal to be output as the signal Pctrl to the signal P3. In other words, an avalanche pause period of length Int2 is provided between waiting periods for avalanche multiplication.

[0043] In step S110, if the current time is within the count period in which counter 16 counts, the operation proceeds to step S111. On the other hand, if the current time is not within the count period, the operation proceeds to step S113.

[0044] In step S111, the counter 16 performs a counting operation to count the pulses of the signal Pp.

[0045] In step S112, if the current time is within the count period during which counter 16 counts, the operation returns to step S111 to continue the count operation, whereas if the current time is not within the count period, the operation proceeds to step S113.

[0046] In step S113, the count value is output as a signal POUT from the counter 16 to the outside of the pixel, after which the operation ends.

[0047] 5 is a timing diagram showing the operation of the pixel of this embodiment. Each signal shown in FIG. 5 corresponds to each signal shown in FIG.

[0048] At time t1, the selector 13 selects the signal P1 as the signal Pctrl.

[0049] When a photon is incident on the photodiode PD, avalanche multiplication occurs, and the voltage Vcath drops. Because the signal Pctrl input to the R terminal of the SR latch circuit 151 is at a low level, the signal Vlat remains at a high level regardless of the level of the voltage Vcath input to the S terminal.

[0050] An inverted signal of the signal Vlat, i.e., a Low-level signal, is input to the NOR circuit 152. Therefore, when the voltage Vcath falls below the logic threshold voltage of the NOR circuit 152, the signal Pp output by the NOR circuit 152 changes to a High level. On the other hand, when the voltage Vcath exceeds the logic threshold voltage of the NOR circuit 152 due to a recharge operation, the signal Pp changes to a Low level.

[0051] The counter 16 increments the count value by one each time the signal Pp changes from low level to high level.

[0052] At time t2, the count value reaches the threshold N1. When the count value reaches the threshold N1, the selector 13 selects the signal P2 as the signal to be output as the signal Pctrl. As a result, the signal Pctrl becomes a signal that has an interval Int1 between its transition from low level to high level and its transition back to low level.

[0053] As described above, when the signal Pctrl is at a low level, the PD control circuit 14 performs a recharge operation to return the voltage Vcath to Vdd if a drop occurs in the voltage Vcath. On the other hand, when the signal Pctrl is at a high level, the voltage Vcath remains constant at a voltage (low level) near the voltage Vss.

[0054] The signal Vlat is at a low level while the voltage Vcath input to the S terminal is at a low level and the signal Pctrl input to the R terminal is at a high level. When the signal Pctrl goes low and the voltage Vcath goes high, the signal Vlat goes high again.

[0055] In this way, when the count value reaches the threshold N1, the avalanche multiplication of the photodiode PD is stopped for the interval Int1.

[0056] In the period from time t2 to time t3, the proportion of the period in which avalanche multiplication is performed and the proportion of the period in which avalanche multiplication is paused are both 50%. In other words, avalanche standby periods of a first length and avalanche multiplication pause periods of the same first length are set alternately.

[0057] After that, at time t3, the count value reaches threshold N2. When the count value reaches threshold N2, selector 13 selects signal P3 as the signal to be output as signal Pctrl. As a result, signal Pctrl becomes a signal that has an interval Int2 between its transition from low level to high level and its transition back to low level.

[0058] The operation is the same as that from time t2 to time t3, except that the interval during which the photodiode PD pauses avalanche multiplication is extended from interval Int1 to interval Int2.

[0059] In the period after time t3, the period during which avalanche multiplication is performed accounts for 25% and the period during which avalanche multiplication is paused accounts for 75%. In other words, avalanche standby periods of a first length and avalanche multiplication pause periods of a second length (three times the first length in this embodiment) longer than the first length are set alternately.

[0060] In this way, the photoelectric conversion device of this embodiment lengthens the interval between periods (standby periods) during which avalanche multiplication is performed (i.e., the length of the idle period) as the count value increases. In other words, the ratio of the length of the idle period to the length of the standby period is controlled to be greater in the period after the count value reaches the threshold value than in the period before the count value reaches the threshold value.

[0061] In this way, the photoelectric conversion device of this embodiment reduces the number of times avalanche multiplication is performed when high-intensity light is incident, thereby reducing the power consumption of the pixel.

[0062] It is not necessary for all bits of the count signal of the counter 16 to be output to the selector 13. For example, the counter 16 may be configured so that only the signal of the most significant bit corresponding to the threshold value is output to the selector 13. In this configuration, the selector 13 may change the signal to be output as the signal Pctrl in response to a change in the signal level of the most significant bit corresponding to the threshold value.

[0063] As another example, a comparison unit may be provided that compares the count value of counter 16 with a threshold value and indicates the result. The signal output by this comparison unit is input to selector 13. In response to a change in the signal output by the comparison unit, selector 13 may change the signal that it outputs as signal Pctrl.

[0064] Next, a correction process for the signal POUT output from the pixel of this embodiment will be described.

[0065] FIG. 6 is a diagram showing the relationship between the number of incident photons on the photodiode PD and the signal POUT.

[0066] Until the signal POUT reaches the threshold N1, the relationship between the number of incident photons and the slope of the signal POUT is slope a. Ideally, if the counter 16 counts all of the photons incident on the photodiode PD without any omissions, the slope a is 1, and the number of photons P1 and the threshold N1 match.

[0067] When the signal POUT reaches the threshold N1, as described above, avalanche waiting periods of a first length and avalanche multiplication pause periods of the same first length are alternately provided. Therefore, the slope of the signal POUT relative to the number of incident photons is a / 2. In general, the slope is a × length of the avalanche waiting period / (length of the avalanche waiting period + length of the avalanche pause period). (Avalanche waiting period length + avalanche rest period length) / If the length of the avalanche waiting period is n, the slope is a / n, where n is 2 in this embodiment.

[0068] When the signal POUT reaches the threshold N2, as described above, avalanche waiting periods of a first length and avalanche multiplication pause periods of a second length (three times the first length in this embodiment) that is longer than the first length are alternately provided. Therefore, the slope of the signal POUT relative to the number of incident photons is a / 4. In general, the slope is a × length of the avalanche waiting period / (length of the avalanche waiting period + length of the avalanche pause period). (Avalanche waiting period length + avalanche rest period length) / The length of the avalanche wait period m Then, the slope is a / m, where m is 4 in this embodiment.

[0069] The correction process of the signal POUT is performed when the count value Nx is greater than the threshold value N1. In this embodiment, for count values ​​in which the slope of the signal POUT relative to the number of incident photons is in a range different from the slope a, the signal POUT is corrected to match the slope a.

[0070] The count value of the signal POUT corresponding to the number of incident photons Px (where P1 < Px < P2) is obtained as Nx1. The count value Nx1 before this correction is corrected to the count value Nx2 after correction as follows. Nx2 = n·Nx1 - (n - 1)·N1 ···(1) Here, in this embodiment, since n = 2, Nx2 = 2Nx1 - N1 ···(2) It becomes as follows.

[0071] Also, the count value of the signal POUT corresponding to the number of incident photons Py (where Py > P2) is obtained as Ny1. The count value Ny1 before this correction is corrected to the count value Ny2 after correction as follows. Ny2 = m·Ny1 - (m - n)·N2 - (n - 1)·N1 ···(3) Here, in this embodiment, since m = 4 and n = 2, Ny2 = 4Ny1 - 2N2 - N1 ···(4) It becomes as follows.

[0072] By correcting in this way, as shown in FIG. 6, a signal POUT corresponding to the relationship of slope a with respect to the number of incident photons can be obtained.

[0073] Note that the correction unit that performs this correction process may be the signal processing circuit 22 of the photoelectric conversion device shown in FIG. 1, or may be the output circuit 60. Also, a signal processing circuit provided outside the photoelectric conversion device may be the correction unit that performs this correction process.

[0074] In this way, the photoelectric conversion device of this embodiment can reduce the power consumption of the pixel by suppressing the number of avalanche multiplication times when high-intensity light is incident. Also, by correcting the signal POUT output by the pixel, a count value corresponding to the number of photons incident on the photodiode PD can be obtained.

[0075] In this embodiment, the length of the avalanche rest period is changed using two thresholds N1 and N2. This is not a limitation, and the number of thresholds may be one or more. When more thresholds are set, the slope of the signal POUT versus the number of incident photons shown in FIG. 6 becomes 1 / 2. n It is preferable to provide an avalanche waiting period and an avalanche rest period so that the following relationship is satisfied: This is because it makes it easier to perform the calculation for correcting the count value, as described with reference to FIG.

[0076] In this embodiment, as shown in FIG. 1, the configuration has been described in which all of the components of pixel 11 are provided on one semiconductor substrate. However, the present invention is not limited to this example, and a photodiode PD may be provided on a first semiconductor substrate, and a counter 16 may be provided on a second semiconductor substrate. A stacked sensor may also be formed by stacking the first and second semiconductor substrates. The pixel control circuit 12, selector 13, PD control circuit 14, and waveform shaping circuit 15 may be provided on either the first or second semiconductor substrate.

[0077] In another example, the photodiode PD is provided on a first semiconductor substrate, and the pixel control circuit 12, selector 13, PD control circuit 14, and waveform shaping circuit 15 are provided on a second semiconductor substrate. In this case, the photodiode PD on the first semiconductor substrate and the PD control circuit 14 on the second semiconductor substrate are connected via a connection node between the substrates. Furthermore, the photodiode PD on the first semiconductor substrate and the waveform shaping circuit 15 on the second semiconductor substrate are connected via another connection node.

[0078] [Second embodiment] The photoelectric conversion device of this embodiment will be described, focusing on the differences from the first embodiment.

[0079] 7 is a diagram showing the configuration of a pixel 11 of this embodiment. In this embodiment, the configuration of the PD control circuit 14 is different from that of the first embodiment.

[0080] In the PD control circuit of this embodiment, PMOS transistor 141 and PMOS transistor 142 are cascode-connected. A voltage Vq input to the gate of PMOS transistor 141 is a voltage that brings the source and drain of PMOS transistor 141 into a conductive state. PMOS transistor 142 is configured so that its parasitic capacitance is smaller than the parasitic capacitance of PMOS transistor 141. Typically, the size of PMOS transistor 142 is smaller than the size of PMOS transistor 141. To reduce the size of a transistor, for example, at least one of the gate length and gate width may be reduced.

[0081] In this embodiment, the parasitic capacitance of the PMOS transistor connected to the photodiode PD is set smaller than that of the PMOS transistor of the PD control circuit 14 in the first embodiment.

[0082] This makes it possible to speed up the recharge operation after the voltage Vcath drops due to avalanche multiplication. Therefore, compared to the first embodiment, it is possible to shorten the period from when avalanche multiplication occurs until avalanche multiplication becomes possible again. Therefore, it is possible to reduce photon count omissions, in which the count value does not increase even when photons are incident on the photodiode PD.

[0083] [Third embodiment] The present embodiment will be described, focusing on the differences from the first embodiment.

[0084] FIG. 8 is a diagram showing the configuration of a pixel 11 of this embodiment.

[0085] In the first embodiment, the selector 13 controls the avalanche waiting period and the idle period of the photodiode PD by controlling the PMOS transistor (recharge element) and the NMOS transistor of the PD control circuit 14. In this embodiment, the avalanche waiting period and the idle period of the photodiode PD are controlled by controlling the potential of the anode of the photodiode PD. Also, in this embodiment, the waveform shaping circuit 15 is an inverter circuit.

[0086] The operation of this embodiment can be the same as that of Embodiment 1. As a result, the photoelectric conversion device of this embodiment can also obtain the same effects as those of the photoelectric conversion device of Embodiment 1.

[0087] [Fourth embodiment] The present embodiment will be described, focusing on the differences from the first embodiment.

[0088] FIG. 9 is a diagram showing the configuration of a pixel 11 included in the photoelectric conversion device of this embodiment.

[0089] In the photoelectric conversion device of this embodiment, the PD control circuit of the pixel 11 has a selector 145 and a PMOS transistor 146. A voltage Vq input to the gate of the PMOS transistor 146 is a voltage that brings the source and drain of the PMOS transistor 146 into a conductive state.

[0090] The selector 145 receives the signal Pctrl from the selector 13. When the signal Pctrl is at a low level, the selector 145 outputs the voltage Vdd to the PMOS transistor 146. When the signal Pctrl is at a high level, the selector 145 outputs the voltage Vss to the PMOS transistor 146. Therefore, as in the first embodiment, the period when the signal Pctrl is at a low level is the avalanche standby period. Also, as in the first embodiment, the period when the signal Pctrl is at a high level is the avalanche multiplication pause period.

[0091] The operation of the photoelectric conversion device of this embodiment can be the same as that of FIG. 5 described in the first embodiment.

[0092] In this embodiment, the same effects as those of the photoelectric conversion device of the first embodiment can be obtained.

[0093] [Fifth embodiment] The present embodiment will be described, focusing on the differences from the first embodiment.

[0094] In the first embodiment, the pixel control circuit 12 is provided for each of the plurality of pixels 11. In the present embodiment, one pixel control circuit 12 is shared by the plurality of pixels 11.

[0095] 10 is a diagram showing the configuration of a pixel unit of a photoelectric conversion device of this embodiment. Multiple columns of pixels 11 arranged in one row share one pixel control circuit 12. The pixel control circuit 12 in the first row outputs signals P11, P12, and P13 to the multiple columns of pixels 11 in the corresponding row.

[0096] The signals P11, P12, and P13 are the same as the signals P1, P2, and P3, respectively, described in the first embodiment. The operation of the photoelectric conversion device of this embodiment can be the same as the operation of FIG. 5 described in the first embodiment.

[0097] In this way, in this embodiment, a single pixel control circuit 12 is shared by multiple pixels 11. This allows the number of pixel control circuits 12 to be reduced compared to the first embodiment, thereby reducing the circuit area.

[0098] In this embodiment, a single pixel control circuit 12 is shared by a plurality of pixels 11 arranged in one row and multiple columns, but the present invention is not limited to this example. As another example, a single pixel control circuit 12 may be shared by a plurality of pixels 11 arranged in multiple rows and one column. Furthermore, the pixel array may be divided into a plurality of blocks, each having a plurality of pixels 11 arranged in multiple rows and multiple columns, and a single pixel control circuit 12 may be shared by a plurality of pixels 11 included in one block.

[0099] The concept of this embodiment can also be applied to the second to fourth embodiments. That is, the pixel control circuit 12 described in each of the second to fourth embodiments may also be shared by a plurality of pixels 11.

[0100] [Sixth embodiment] This embodiment will be described, focusing on the differences from the fifth embodiment.

[0101] In the fifth embodiment, the signals output from the pixel control circuits 12 are signals P11 to P13, and signals of the same phase are output from the plurality of pixel control circuits 12. In the present embodiment, the plurality of pixel control circuits 12 output signals of different phases.

[0102] FIG. 11 is a diagram showing the configuration of a pixel unit of the photoelectric conversion device of this embodiment.

[0103] In this embodiment, when indicating a row position, (n) is added to the end of the reference numeral of a signal or component in the specification and drawings, indicating that the signal or component corresponds to the nth row.

[0104] The pixel control circuit 12(1) in the first row outputs signals P1(1) to P3(1) to the pixels 11 in the corresponding row and in multiple columns.

[0105] The pixel control circuit 12(2) in the second row outputs signals P1(2) to P3(2) to the pixels 11 in the multiple columns in the corresponding row.

[0106] The pixel control circuit 12(3) in the third row outputs signals P1(3) to P3(3) to the pixels 11 in the multiple columns in the corresponding row.

[0107] 12 is a diagram showing the operation of the pixel 11 of this embodiment. The signals shown in FIG. 12 correspond to the signals shown in FIG.

[0108] The signals P1(1), P1(2), and P1(3) are constant at a low level.

[0109] Signals P2(1), P2(2), and P2(3) have the same period. Signals P2(1) and P2(2) have opposite phases. Signals P2(1) and P2(3) are in-phase signals.

[0110] Signals P3(1), P3(2), and P3(3) are signals with the same period. Signals P3(2) and P3(1) are delayed in phase (by half a period of signal P2). Similarly, signal P3(3) is delayed in phase (by half a period of signal P2) relative to signal P3(2). Signal P3(3) is delayed in phase relative to signal P3(1) by one period of signal P2.

[0111] The avalanche current caused by avalanche multiplication causes voltage fluctuations at the node supplying voltage Vdd. As the number of pixels 11 in which avalanche multiplication occurs simultaneously increases, the potential fluctuations of voltage Vdd increase. This can delay the recharge operation of the PD control circuit 14 and cause other circuit elements to malfunction or degrade in operation accuracy.

[0112] In this embodiment, the signal P2(n) of the pixel control circuit 12(n) in one row and the signal P2(m) of the pixel control circuit 12(m) in another row are made to have different phases. This makes it possible to make the timing of the avalanche standby period different between the pixels 11 whose avalanche multiplication is controlled by the signal P2(n) and the pixels 11 whose avalanche multiplication is controlled by the signal P2(m). This makes it possible to reduce the number of pixels that simultaneously cause avalanche multiplication, thereby suppressing potential fluctuations in the voltage Vdd.

[0113] Similarly, the signal P3(n) of the pixel control circuit 12(n) in one row and the signal P3(m) of the pixel control circuit 12(m) in another row are made to have different phases, which makes it possible to make the timing of the avalanche standby period different between the pixel 11 whose avalanche multiplication is controlled by the signal P3(n) and the pixel 11 whose avalanche multiplication is controlled by the signal P3(m).

[0114] In this way, in the photoelectric conversion device of this embodiment, the phases of the signals output by one pixel control circuit 12 are made different from those of the other pixel control circuits 12. This makes it possible to reduce the number of pixels that simultaneously cause avalanche multiplication, thereby suppressing potential fluctuations in the voltage Vdd.

[0115] In this embodiment, as an example, the signal P2(2) is delayed by half a period relative to the signal P2(1), but the amount of signal delay can be selected arbitrarily.

[0116] Similarly, the delay amount of the signal P3(2) relative to the signal P3(1) can also be selected arbitrarily from amounts other than those in this embodiment.

[0117] [Seventh embodiment] An imaging system according to the seventh embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0118] The photoelectric conversion device 100 described in the first to sixth embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in imaging systems. Fig. 13 illustrates a block diagram of a digital still camera as an example of such systems.

[0119] 13 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any of the first to fifth embodiments, and converts the optical image formed by the lens 202 into image data.

[0120] The imaging system 200 also has a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 performs AD conversion to convert an analog signal output from the imaging device 201 into a digital signal. The signal processing unit 208 also performs various corrections and compressions as necessary to output image data. An AD conversion unit, which is part of the signal processing unit 208, may be formed on the semiconductor substrate on which the imaging device 201 is provided, or may be formed on a semiconductor substrate separate from the imaging device 201. The imaging device 201 and the signal processing unit 208 may also be formed on the same semiconductor substrate.

[0121] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be removable.

[0122] The imaging system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0123] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0124] As described above, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to sixth embodiments is applied.

[0125] [Eighth embodiment] An imaging system and a moving object according to an eighth embodiment of the present invention will be described with reference to Fig. 14. Fig. 14 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0126] FIG. 14A shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to sixth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0127] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0128] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 14(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0129] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0130] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0131] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0132] Furthermore, the imaging systems shown in the seventh and eighth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 13 and 14.

[0133] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0134] 12 Pixel control circuit 13 Selector (control circuit) 14 PD control circuit 15 Waveform generation circuit 16 Counters

Claims

1. an avalanche multiplication photodiode connected to receive the first voltage and the second voltage; a counter that counts pulses generated by the photodiode and holds the count value; a control circuit that controls the supply of the first voltage to the photodiode; a correction unit that corrects the count value output from the counter, the signal input to the control circuit has a first level at which the first voltage is supplied to the photodiode via the control circuit and a second level at which the first voltage is not supplied to the photodiode; When the count value output from the counter exceeds a threshold value, a slope of the count value relative to the number of photons incident on the photodiode is smaller than a slope a of the count value relative to the number of photons incident on the photodiode until the count value output from the counter reaches the threshold value, The photoelectric conversion device is characterized in that, when the count value output from the counter exceeds the threshold value, the correction unit corrects the slope of the count value relative to the number of photons incident on the photodiode to match the slope a for count values ​​that are in a range different from the slope a of the count value and the number of photons incident until the count value output from the counter reaches the threshold value.

2. a period from resetting the count value of the counter to reading out the count value of the counter includes a first period and a second period subsequent to the first period; the second period is a period after the count value reaches the threshold value, In the first period, a ratio of a length of the second level to a length of the first level is a first value; In the second period, a ratio of the length of the second level to the length of the first level is a second value; 2. The photoelectric conversion device according to claim 1, wherein the second value is greater than the first value.

3. During the first period, the signal input to the control circuit is maintained at the first level; 3. The photoelectric conversion device according to claim 2, wherein the signal input to the control circuit is set to the first level and the second level sequentially multiple times during the second period.

4. During the first period, the signal input to the control circuit is set to the first level and the second level sequentially multiple times; 3. The photoelectric conversion device according to claim 2, wherein the signal input to the control circuit is set to the first level and the second level sequentially multiple times during the second period.

5. a third period of time after the second period of time; the third period is a period after the count value reaches a second threshold value that is greater than the threshold value, During the third period, the signal input to the control circuit is set to the first level and the second level sequentially multiple times; 5. The photoelectric conversion device according to claim 2, wherein the length of the second level in the third period is longer than the length of the second level in the second period.

6. 4. The photoelectric conversion device according to claim 1, wherein the correction is performed according to the following formula (A): Nx2=n・Nx1-(n-1)・N1...(A) Nx2: the count value after correction n: (length of the period of the first level + length of the period of the second level) / length of the period of the first level after the count value reaches the threshold value Nx1: the count value before correction N1: the threshold value

7. the control circuit includes a recharge circuit; When the signal of the first level is input to the control circuit, a recharge operation is performed by the recharge circuit; 7. The photoelectric conversion device according to claim 1, wherein when the signal of the second level is input to the control circuit, the recharge operation by the recharge circuit is suspended.

8. the first voltage is a voltage supplied to the anode of the photodiode; the second voltage is a voltage supplied to the cathode of the photodiode; 8. The photoelectric conversion device according to claim 1, wherein the control circuit is configured to change the potential on the anode side of the photodiode.

9. the first voltage is a voltage supplied to the cathode of the photodiode; the second voltage is a voltage supplied to the anode of the photodiode; 8. The photoelectric conversion device according to claim 1, wherein the control circuit is configured to change the potential on the cathode side of the photodiode.

10. a plurality of pixels each including the photodiode; the control circuit includes a control signal generation unit, 10. The photoelectric conversion device according to claim 1, wherein the control signal generating section of the control circuit is commonly connected to the plurality of pixels.

11. the photodiode is disposed on a first semiconductor substrate, and the counter is disposed on a second semiconductor substrate; 11. The photoelectric conversion device according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are stacked.

12. The photoelectric conversion device according to any one of claims 1 to 11, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

13. A mobile object, The photoelectric conversion device according to any one of claims 1 to 11, a distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

Images