Negative voltage monitoring circuit and light receiving device

Abstract

[Problem] To achieve a highly accurate negative voltage monitoring circuit. [Solution] A negative voltage monitoring circuit (10) comprises a first voltage-dividing circuit (100), a first amplifying circuit (102), a second amplifying circuit (104), and an error determining circuit (108). The first voltage-dividing circuit (100) divides a power supply voltage and outputs a first voltage. The first voltage is input to a non-inverting input terminal of the first amplifying circuit (102), which negatively feeds back an output voltage. A second voltage is obtained by dividing a potential difference between the power supply voltage and a voltage to be monitored, which is applied to an anode of a light receiving element (30), and the second voltage is input to a non-inverting input terminal of the second amplifying circuit (104), which negatively feeds back an output voltage. The error determining circuit (108) outputs an error signal on the basis of a difference between the output of the first amplifying circuit (102) and the output of the second amplifying circuit (104).

Description

[Technical Field]

[0001] The present disclosure relates to a negative voltage monitoring circuit and a light receiving device. [Background technology]

[0002] The SPAD (Single Photon Avalanche Diode) used in ToF (Time of Flight) sensors requires a large negative voltage, such as -20V, to be applied to the anode side in order to generate avalanche amplification with high sensitivity. ToF sensors are mounted in various housings depending on the purpose, for example: When installed in automobiles, the power supply voltage of the sensor is monitored with high precision for functional safety. In this monitoring, the voltage cannot be read directly within the sensor due to issues such as the device's withstand voltage, so it is necessary to make the voltage positive by dividing it against a positive reference voltage using an externally mounted high-voltage resistor before inputting it to the sensor.

[0003] However, with this type of implementation, not only is it affected by variations in the positive voltage value, but errors in the gain of the voltage division ratio due to variations in the external resistors become dominant, making it impossible to obtain sufficient monitoring accuracy. Alternatively, to solve this problem, it is necessary to implement very high-precision external resistors, but such a configuration has the problem of being expensive. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 1-223360 Summary of the Invention [Problem to be solved by the invention]

[0005] This disclosure proposes a highly accurate negative voltage monitoring circuit. [Means for solving the problem]

[0006] According to one embodiment, the negative voltage monitoring circuit includes a first voltage dividing circuit, a first amplifier circuit, and a second amplifier circuit. The first voltage divider circuit divides a power supply voltage and outputs a first voltage. The first amplifier circuit receives the first voltage at its non-inverting input terminal and negatively feeds back the output voltage. The second amplifier circuit detects a voltage between the power supply voltage and a voltage to be monitored that is applied to the anode of the light receiving element. The second voltage obtained by dividing the potential difference is input to the non-inverting input terminal, and the output voltage is negatively fed back. The determination circuit outputs an error signal based on the difference between the output of the first amplifier circuit and the output of the second amplifier circuit.

[0007] The light receiving element may be a SPAD (Single Photon Avalanche Diode).

[0008] A negative voltage may be applied to the anode of the light receiving element when the element is in a light receiving state.

[0009] The negative voltage monitoring circuit may further include an error detection circuit that acquires a potential difference between the first amplifier circuit and the second amplifier circuit when no negative voltage is applied to the anode of the light receiving element.

[0010] The negative voltage monitoring circuit adjusts the voltage division ratio of the first voltage dividing circuit based on the output of the error detection circuit. The present invention may further include a voltage division ratio control circuit for controlling the voltage division ratio.

[0011] The voltage division ratio control circuit may output the controlled voltage division ratio to the error determination circuit.

[0012] The error determination circuit may make an error determination by comparing a voltage obtained by dividing the power supply voltage and amplifying it with the amplification factor of the first amplifier circuit using a voltage division ratio controlled by the voltage division ratio control circuit, a voltage obtained by dividing the power supply voltage and a predetermined negative voltage and amplifying it with the amplification factor of the second amplifier circuit, and a voltage output by the second amplifier circuit.

[0013] The error detection circuit may output binary information obtained by comparing the output of the first amplifier circuit and the output of the second amplifier circuit, and the voltage division ratio control circuit may control the voltage division ratio based on the binary information.

[0014] The voltage division ratio control circuit may control the voltage division ratio by controlling the resistance value of the first voltage division circuit. .

[0015] The error detection circuit converts the output of the first amplifier circuit into a digital signal and The output of the second amplifier circuit is converted into a digital signal and the binary information is compared with the result. The voltage division ratio control circuit may control the voltage division ratio based on the binary information.

[0016] The voltage division ratio control circuit may control the voltage division ratio by controlling the resistance value of the first voltage division circuit. .

[0017] a voltage difference between the power supply voltage and the monitored voltage is divided to output the second voltage; A second voltage dividing circuit may be further provided.

[0018] The first voltage dividing circuit, the first amplifier circuit, and the second amplifier circuit may be provided in two systems.

[0019] According to one embodiment, a photodetector includes any of the negative voltage monitoring circuits described above, and a second voltage divider circuit that divides the potential difference between the power supply voltage and a terminal to which a negative voltage is applied to output a second voltage, and the negative voltage monitoring circuit controls the voltage division ratio of the first voltage divider circuit to match the voltage division ratio of the second voltage divider circuit when no negative voltage is applied.

[0020] The light receiving device may further include a negative voltage generating circuit that generates a negative voltage and applies the generated negative voltage to a terminal to which the negative voltage is applied in the light receiving enabled state.

[0021] The error determination circuit may output the error signal when a voltage obtained by dividing the power supply voltage and the voltage generated by the negative voltage generation circuit is not within a predetermined voltage range. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a diagram showing an example of the arrangement of light receiving elements according to an embodiment. [Figure 2] FIG. 1 is a diagram schematically illustrating the configuration of a negative voltage monitoring circuit according to an embodiment. [Figure 3] FIG. 1 is a diagram schematically illustrating the configuration of a negative voltage monitoring circuit according to an embodiment. [Figure 4] FIG. 1 is a diagram schematically illustrating the configuration of a negative voltage monitoring circuit according to an embodiment. [Figure 5] 5 is a timing chart for controlling the voltage division ratio of the first voltage divider circuit according to one embodiment. [Figure 6] FIG. 3 is a circuit diagram showing an example of a first voltage dividing circuit according to an embodiment. [Figure 7] FIG. 1 is a diagram schematically illustrating the configuration of a negative voltage monitoring circuit according to an embodiment. [Figure 8] 5 is a timing chart for controlling the voltage division ratio of the first voltage divider circuit according to one embodiment. [Figure 9] FIG. 1 is a diagram schematically illustrating the configuration of a negative voltage monitoring circuit according to an embodiment. [Figure 10] FIG. 1 is a diagram illustrating a schematic layout of a negative voltage monitoring circuit according to an embodiment. [Figure 11] FIG. 1 is a diagram schematically illustrating a configuration of a light receiving device according to an embodiment. [Figure 12] FIG. 1 is a diagram schematically illustrating a configuration of a light receiving device according to an embodiment. [Figure 13] FIG. 1 is a diagram schematically illustrating a configuration of a light receiving device according to an embodiment. [Figure 14] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 15] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0024] FIG. 1 is a diagram illustrating a light receiving device that receives light using a negative voltage monitored by a negative voltage monitoring circuit according to the present disclosure. FIG. 1 is a diagram schematically illustrating a light receiving device including an element.

[0025] The light receiving device 1 includes a negative voltage monitoring circuit 10, a negative voltage generating circuit 20, a light receiving element 30, and a pixel circuit 32. The light receiving device 1 is provided in, for example, a ToF (Time of Flight) sensor, and is a device that converts an analog signal received by a light receiving element 30 into a digital signal and outputs the digital signal.

[0026] 1 is a schematic diagram, and detailed illustration of other elements that can fulfill the functions of the light receiving device 1 is omitted, but circuits for appropriately receiving light and outputting signals may be provided as appropriate. For example, the second voltage dividing circuit described later may include a negative voltage generating circuit 20 and a negative It may be provided between the voltage monitoring circuit 10 and outside the chip on which the negative voltage monitoring circuit 10 resides.

[0027] The negative voltage monitoring circuit 10 monitors whether the negative voltage applied to the light receiving element 30 in the light receiving device 1 is within a predetermined voltage range. If the negative voltage is not within the predetermined voltage range, the negative voltage monitoring circuit 10 outputs an error signal to notify other elements of the light receiving device 1 that the voltage is not being applied normally. To exert effort.

[0028] The negative voltage generating circuit 20 is a circuit that generates a negative voltage to be applied to the anode of the light receiving element 30. The configuration of this negative voltage generating circuit 20 is not particularly limited, and any circuit that can generate an appropriate negative voltage may be used.

[0029] The light receiving element 30 may be, for example, a photodiode, more specifically, an APD (Avalanche Photodiode) or a SPAD (Single Photon Avalanche Diode). The light receiving elements 30 are arranged in a two-dimensional array to form a light receiving pixel array, and this light receiving pixel array This light-receiving pixel array operates as the light-receiving region of, for example, a SiPM (Silicon Photomultiplier). When a photon is incident in the light-receiving state, the SPAD etc. To achieve adequate avalanche multiplication, a strong negative voltage must be applied to the anode.

[0030] The pixel circuit 32 is a circuit that appropriately converts the analog signal output from the light receiving element 30 into a digital signal and outputs the digital signal. The pixel circuit 32 may be any circuit that can appropriately convert the signal output from the light receiving element 30 and output the digital signal.

[0031] As a non-limiting example, the negative voltage monitoring circuit 10, the light receiving element 30, and the pixel circuit 32 are provided in the same chip. For example, the area surrounded by the dotted line in FIG. 1 is the same chip. exists in.

[0032] The negative voltage generation circuit 20 generates a strong negative voltage to be applied to the light receiving element 30, and this negative voltage is applied to the anode of the light receiving element 30. Such a voltage with a high absolute value needs to be monitored in consideration of functional safety. The negative voltage monitoring circuit 10 is a circuit for monitoring this voltage. On the other hand, elements to which such a strong negative voltage is applied are required to have high voltage resistance.

[0033] It is difficult to form an element with such a high voltage resistance within the chip on which the light receiving device 1 is mounted. Therefore, the negative voltage is appropriately divided outside the chip and input to the negative voltage monitoring circuit 10. The negative voltage monitoring circuit 10 monitors the voltage applied to the anode of the light receiving element 30 by monitoring this divided negative voltage.

[0034] (First embodiment) FIG. 2 is a diagram illustrating an example of the configuration of a negative voltage monitoring circuit 10 according to an embodiment. In FIG. 2, the right side of the dotted line indicates the inside of the chip, and the left side of the dotted line indicates the outside of the chip. The power supply voltage is also assumed to be properly connected in a range not shown.

[0035] For example, each amplifier circuit is appropriately connected to power supply voltages VDDA and VSSA. VDDA may be, for example, a voltage of approximately 3.6 V, and VSSA may be 0 V (ground voltage). Furthermore, VL may be a strong negative voltage of approximately −20 V when the light-receiving element 30 is in a light-receiving state, and 0 V (ground voltage) when the light-receiving element 30 is not in a light-receiving state. Note that in the following diagrams, the power supply voltage VSSA is set externally via a terminal, but this is not limiting and it may also be set as a ground voltage within the chip without using a terminal, for example, by being properly grounded.

[0036] The negative voltage monitoring circuit 10 includes a first voltage dividing circuit 100, a first amplifier circuit 102, a second amplifier circuit 104, an analog-to-digital converter (ADC 106) and an error determination circuit 108. The negative voltage monitoring circuit 10 detects a voltage applied to the anode of the light receiving element 30. The negative voltage monitoring circuit 10 converts the negative voltage received into a positive voltage by appropriately dividing it between the power supply voltage and the negative voltage monitoring circuit 10. The negative voltage monitoring circuit 10 determines whether this positive voltage falls within a predetermined voltage range and outputs an error signal if an abnormality is detected.

[0037] The first voltage dividing circuit 100 divides the power supply voltages VDDA and VSSA and outputs a first voltage. The circuit 100 has, for example, a plurality of resistors, and outputs a voltage from a node between the plurality of resistors. do.

[0038] The first amplifier circuit 102 has a non-inverting input terminal connected to the output of the first voltage divider circuit 100 and an inverting input terminal connected to its own output terminal. , the first voltage is amplified by a predetermined amplification factor and output.

[0039] The second amplifier circuit 104 has a non-inverting input terminal connected to a second voltage obtained by dividing the power supply voltage VDDA and the voltage VL applied to the anode of the light receiving element at a predetermined voltage division ratio by an external voltage divider circuit, and an inverting input terminal The output terminal of the second amplifier circuit 104 is connected to the output terminal. That is, the output voltage of the second amplifier circuit 104 is negatively fed back, and the second voltage is amplified by a predetermined amplification factor and output. This voltage VL is the voltage to be monitored in this disclosure, and is a negative voltage when the light receiving element 30 is in a state where it can receive light.

[0040] It is desirable that the amplification factor of the second amplifier circuit 104 is the same as that of the first amplifier circuit 102. If the amplification factors are different, the digital signal is controlled based on the amplification factor in the ADC 106 at the output destination. or a configuration in which the error determination circuit 108 determines an error based on the amplification factor. may be.

[0041] The ADC 106 is a circuit that converts an input analog signal into a digital signal and outputs the digital signal. The divided voltages, which are analog signals output by the first amplifier circuit 102 and the second amplifier circuit 104, are input to the ADC 106 and converted into digital signals. The ADC 106, for example, multiplexes these signals and outputs them to the error determination circuit 108. If necessary, the ADC 106 may convert the reference value of the input voltage into a power supply voltage inside the chip and output it. In this case, the ADC 106 has VDDB and VSSB are input as power supply voltages inside the chip, and a BGR (Band Gap Reference) that outputs this voltage value may be provided, and a level shifter may be provided as necessary. Such a configuration can also be shared with the configuration of a thermometer or the like within the chip, for example.

[0042] The error determination circuit 108 performs error determination based on the digital signal output from the ADC 106 and outputs the result. The error determination circuit 108 is, for example, an integrated circuit such as a register in a chip. If an error occurs in a module connected to the chip or in a necessary module outside the chip, an error signal is output.

[0043] The error determination circuit 108 detects, for example, the first amplifier circuit 102 and the second amplifier circuit 103 output from the ADC 106. The voltage applied to the non-inverting input terminal of the second amplifier circuit 104 is calculated based on the voltage difference between the first amplifier circuit 104 and the second amplifier circuit 104. The negative voltage monitoring circuit 10 determines whether the error determination circuit 108 or An error detection circuit (not shown) may be provided outside the error determination circuit 108, and this error detection circuit may detect the voltage difference between the first amplifier circuit 102 and the second amplifier circuit 104. In this state, the voltage output by the second amplifier circuit 104 is subtracted from the voltage output by the first amplifier circuit 102, and it is determined whether or not this voltage difference is within a predetermined range. If it is within the predetermined range, it is determined that a normal voltage is being applied, and no error signal is output; if it is not within the predetermined range, it is determined that an abnormal voltage is being applied, and an error signal is output.

[0044] As a pre-processing, the error determination circuit 108 applies a negative voltage to VL before the transition to the light receiving enabled state. Before the voltage is applied, the second voltage output from the external voltage dividing circuit and the voltage output from the first voltage dividing circuit 100 are mixed. The second voltage is compared with the first voltage output from the external voltage divider circuit 100. The second voltage is output from a voltage divider circuit external to the chip. This external voltage divider circuit is implemented, for example, by a manufacturer that incorporates the chip, separately from the chip manufacturing process. Even if the external voltage divider circuit is designed to have the same voltage division ratio as the first voltage divider circuit 100, there is a possibility that the voltage division ratio may differ. For this reason, this preprocessing is performed to obtain the effect of the difference in the voltage division ratio, and the effect of this difference in the voltage division ratio is reflected when generating the error signal.

[0045] As a pre-processing, the error determination circuit 108 detects whether the voltage VL is equal to the voltage VSSA. With the amplifiers 102 and 104 connected, the output of the first amplifier circuit 102 and the output of the second amplifier circuit 104 are compared. In an ideal state, the difference between these outputs would be 0. If the difference between these outputs is not 0, the difference between these outputs is stored as an offset voltage.

[0046] For example, after a negative voltage is applied to VL, the error determination circuit 108 subtracts this offset voltage from the output voltage of the ADC 106 to update the value.

[0047] Then, from the time when a negative voltage is applied to VL and the light receiving element 30 transitions to a state in which it is capable of receiving light, it is determined whether the negative voltage applied to VL is a normal value, and based on the determination result, an error signal is generated and output.

[0048] Components of the light receiving device inside or outside the chip may take action in the event of an abnormality based on this error signal. For example, if the negative voltage applied to VL is too strong, the application of the negative voltage may be stopped. For example, if the negative voltage applied to VL is too weak, the negative voltage may be increased. These are just examples, and the actions taken when an error occurs are not limited to these.

[0049] As described above, the negative voltage monitoring circuit 10 according to this embodiment can appropriately determine whether an appropriate negative voltage is being applied to the anode of the light receiving element 30 without having elements such as high-voltage resistance resistors inside the chip.

[0050] FIG. 3 is a diagram showing the configuration of a negative voltage monitoring circuit 10 according to a modified example. This is the case when elements such as high-voltage resistors can be provided inside the chip. As shown in this figure, if a high-voltage resistor that can withstand a certain voltage can be provided inside the chip, a second voltage divider circuit 110 that divides VDDA and VL may be provided inside the chip.

[0051] The second voltage divider circuit 110 is provided in the negative voltage monitor circuit 10 and divides VDDA and VL at a predetermined voltage division ratio and outputs the result. The error determination circuit 108 subtracts the offset voltage from the output voltage of the ADC 106. Based on the result of the subtraction and the predetermined voltage range, the error determination circuit 108 applies a negative voltage to VL. When a negative voltage is applied, it is determined whether or not this negative voltage is within a normal range, and an error signal is output if necessary.

[0052] In the following embodiments, if there is room for providing a high-voltage resistance or the like inside the chip, the negative voltage monitoring circuit 10 may be configured to include a second voltage dividing circuit 110 as shown in FIG.

[0053] (Second embodiment) In the second embodiment, the voltage division ratio of the first voltage divider circuit 100 in the chip is set to 0.05V when a negative voltage is applied. This paper describes a negative voltage monitoring circuit that controls the voltage division ratio in the absence of a negative voltage and detects errors using the controlled voltage division ratio.

[0054] 4 is a circuit diagram showing a schematic diagram of the negative voltage monitoring circuit 10 according to this embodiment. The circuit 10 further includes a voltage division ratio control circuit 112 in addition to the configuration shown in Fig. 2. Components with the same reference numerals perform the same operations as those shown in Fig. 2 unless otherwise specified, and therefore will not be described in detail. The same applies to the third embodiment described later.

[0055] The first voltage divider circuit 100 may be configured, for example, by a plurality of resistors, one of which is connected in parallel to divide the voltage, and may be configured as a voltage divider circuit whose voltage division ratio is variable by controlling the connection state of these resistors with a switch.

[0056] The voltage division ratio control circuit 112 is a circuit that generates a signal for controlling the voltage division ratio of the first voltage divider circuit 100 based on the amplified first voltage and the amplified second voltage output from the ADC 106, and outputs the signal to the first voltage divider circuit 100. The voltage division ratio control circuit 112 is a circuit that generates a signal for controlling the voltage division ratio of the first voltage divider circuit 100 based on the amplified first voltage and the amplified second voltage output from the ADC 106, and outputs the signal to the first voltage divider circuit 100. A cable signal Enc and a pulse signal ENa for turning on the ADC 106 are input. It outputs a signal that controls the voltage division ratio based on the timing when ENc is on. During this time, the voltage division ratio control circuit 112 controls the voltage division ratio of the first voltage divider circuit 100 to perform calibration. When ENc is in the OFF state, for example, the voltage division ratio control circuit 112 may stop operating, and at least the voltage division ratio of the first voltage divider circuit 100 is not controlled.

[0057] The first voltage dividing circuit 100 changes the resistance value in accordance with the control signal output from the voltage dividing ratio control circuit 112. The voltage division ratio control circuit 112 controls the voltage division ratio of the external voltage divider circuit 100 so that the voltage division ratio of the external voltage divider circuit 100 that outputs the second voltage is equal to the voltage division ratio of the first voltage divider circuit 100. and outputs a signal to control a switch that connects a resistor provided in the

[0058] 5 is a timing chart showing how voltage values ​​transition due to the operation of the voltage division ratio control circuit 112 according to one embodiment. The voltages V1, V2, and Ve shown in the timing chart are the output voltage of the first amplifier circuit 102, the output voltage of the second amplifier circuit 104, and the output voltage of the first amplifier circuit 106, respectively. VL represents the voltage obtained by subtracting the output of the second amplifier circuit 104 from the output of the light receiving element 30. ENc and ENa are the enable signals for turning on and off the calibration function and turning on the ADC 106, respectively, as described above. 1 indicates the enable signal for

[0059] First, at time t0, an enable signal ENc is input to turn on the calibration function. This ENc is kept in the ON state until the setting of the resistance value of the first voltage dividing circuit 100 is completed. The voltage division ratio of the first voltage divider circuit 100 is, for example, a ratio of the resistors connected in parallel as shown in FIG. The voltage division ratio is determined by whether or not to connect to the power supply, and the final voltage division ratio is determined by performing a binary search for this connection. ENc remains on until the time when the binary search for the switch to be controlled in the first voltage divider circuit 100 is fully completed. When ENc is on, for example, the voltage VL remains shorted with VSSA, i.e., no negative voltage is applied to VL.

[0060] In this state, the voltage division ratio control circuit 112 receives the energy Based on the pulse signal ENa, the first voltage divider circuit 100 controls a switch related to the voltage division ratio. ENa is input as a pulse signal at predetermined intervals, for example, at times t1, t2, t3, . . . , tn. The ADC 106 performs AD conversion based on this signal. In this embodiment, ENa is also input to the voltage division ratio control circuit 112, which acquires the voltage values ​​of voltages V1 and V2 and the voltage value of voltage V1, V2 to Ve based on this timing.

[0061] The voltage division ratio control circuit 112 includes an error detection circuit (not shown) for obtaining this voltage difference. The error detection circuit may include a digital signal representing the voltage of V2 output by the ADC 106. By calculating the difference between the signal and the digital signal representing the voltage of V1, the value of Ve is obtained as follows.

[0062] Ve can be expressed as follows using the voltage division ratio 1:k1 of the first voltage divider circuit 100 and the voltage division ratio 1:k2 of the voltage input to the second amplifier circuit 104. VDDA is a positive voltage, VSSA is a ground voltage, and VL is a ground voltage or a negative voltage. A is the ratio of each amplifier. This is the amplification factor in the circuit.

number

[0063] In equation (1), by setting k1 to the same ratio as k2, when VL becomes a negative voltage, the first term of V2 and V1 cancel each other out, and a positive voltage according to the voltage division ratio can be obtained as Ve. The voltage division ratio control circuit 112 controls the voltage division ratio of the first voltage divider circuit 100 so that this situation occurs. Therefore, the following operations are performed:

[0064] If V1=V2, that is, Ve=0, the voltage division ratio control circuit 112 ends the voltage division ratio control process.

[0065] If V1 < V2, i.e., Ve < 0, the voltage division ratio control circuit 112 increases the number of switches that are turned off in the first voltage divider circuit 100, thereby increasing V1 and controlling the difference between V1 and V2 to be smaller.

[0066] If V1 > V2, i.e., Ve > 0, the voltage division ratio control circuit 112 increases the number of switches turned on in the first voltage divider circuit 100 to lower V1 and reduce the difference between V1 and V2.

[0067] In the initial state of the first voltage divider circuit 100, half of the switches may be turned on and half may be turned off. However, this is not limiting, and the on / off states may be determined by any combination of switches as the initial state. Furthermore, the resistors whose connections are turned on / off by the switches may have the same resistance value. As another example, a combination of resistors having any resistance value that can represent multiple resistance values ​​by combination may be used.

[0068] In this case, in the example of FIG. 5, at time t1, V1<V2, so the voltage division ratio control circuit 112 calculates half the number n of switches that are currently turned off, n / 2 (if n is an odd number, then (n+1) / 2 or (2 - 1) / 2, the same applies below) is turned on to increase the positive voltage division ratio, thereby increasing V1.

[0069] At time t2, V1 > V2, so the voltage division ratio control circuit 112 turns off n / 2 switches, which is half the number n of the switches that are currently on, thereby lowering the positive voltage division ratio and lowering V1.

[0070] This operation continues until Ve = 0. Note that the number of controllable switches is M. 5 may be set to M / 2. Therefore, the number of times to perform calibration is determined to be a predetermined number, and calibration of the voltage division ratio by the voltage division ratio control circuit 112 is not performed until the predetermined number of AD conversions are completed. Alternatively, the voltage division ratio control circuit 112 may be configured to repeat the above operation until the absolute value of Ve becomes smaller than a predetermined voltage. In this manner, the voltage division ratio control circuit 112 controls the resistance value of the first voltage divider circuit 100 to appropriately change the voltage division ratio.

[0071] As shown in FIG. 4, the voltage division ratio of the first voltage divider circuit 100 is 1:k1, and the voltage division ratio between the external VDDA and VL is When the ratio is 1:k2 and VL=VSSA, the voltage division ratio control circuit 112 controls the voltage division ratio of the first voltage divider circuit 100 so that V1 is at an equivalent potential with V2 as the reference, and these voltage division ratios are equal (for example, For example, control it so that the ratio is 1:k to 1:k2.

[0072] After the control of the voltage division ratio of the first voltage divider circuit 100 is completed, ENc is transitioned to a state where calibration is not performed at time τ1. After an appropriate time has elapsed, the voltage VL applied to the anode of the light receiving element 30 is set to an appropriate negative voltage, whereby the light receiving element 30 transitions to a state where it can receive light.

[0073] In this case, the final voltage Verror of Ve can be expressed as follows:

number

[0074] The error determination circuit 108 may determine that an error has occurred if the potential difference between V1 and V2 falls outside a predetermined range based on equation (2) at the timing when a negative voltage is applied to VL. The error determination circuit 108 may use the value of k obtained from the voltage division ratio control circuit 112 for this determination. Based on this result, the error decision circuit 108 determines whether the error has occurred by using an appropriate configuration inside or outside the chip. For example, if −20 V is applied to VL as the default value, the final Verror is obtained using an appropriately set voltage division ratio based on equation (2), and an error determination is made based on this Verror.

[0075] For example, the error determination circuit 108 may determine whether the range of Verror is within a predetermined voltage range. As another example, the error determination circuit 108 may calculate Vmonitor based on the following formula and determine whether an error has occurred based on this Vmonitor:

number

[0076] As a non-limiting example, if VDDA = 3.6 [V], VSSA = 0 [V], and VL in the light-receiving enabled state = -20 [V], then 1:k1 = 1:12 may be used. In this case, Verror = 1.67 [V] is desirable, and the error determination circuit 108 determines that there is no error if the difference between V2 and V1 is within a predetermined voltage range from 1.67 [V], and determines that an error has occurred in the voltage applied to the anode of the light-receiving element 30 if it is outside this range. If the voltage division ratio in the external implementation deviates slightly from 1:12, appropriate control of k1 as described above allows for appropriate error determination.

[0077] 4 and 5 are shown as examples, and implementation is not limited to these. For example, in the state of FIG. 4, the voltage division ratio may change significantly by turning the switch on and off. High potential.

[0078] Fig. 6 is a diagram showing a first voltage divider circuit 100 for avoiding this state. As shown in Fig. 6, a resistor that fixes the voltage division ratio to a certain extent may be connected in series with a resistor that is turned on and off by a switch. In the initial state, half of the switches may be turned on, and the voltage division ratio may be set to 1:k1.

[0079] As described above, according to this embodiment, the voltage division ratio preset inside the chip and the voltage division ratio implemented outside the chip can be appropriately controlled to be equal by controlling the voltage division ratio of the first voltage divider circuit 100 inside the chip. A user of the light receiving device 1 implements an external voltage divider circuit so that the voltage division ratio between VDDA and VL is 1:k1. The voltage division ratio in the external implementation does not necessarily match the voltage division ratio inside the chip. The negative voltage monitoring circuit 10 according to this embodiment makes it possible to absorb the difference in voltage division ratio inside the chip, and to monitor the negative voltage in a way that properly reflects the voltage division ratio in the external implementation.

[0080] (Third embodiment) In the second embodiment, the voltage division ratio control circuit 112 is provided with an error detection circuit and calculates the voltage difference, but the implementation is not limited to this. For example, an ADC that acquires the error between the outputs of the first amplifier circuit 102 and the second amplifier circuit 104 may be provided separately.

[0081] FIG. 7 is a diagram illustrating an example of the negative voltage monitoring circuit 10 according to this embodiment. In addition to the above-described configuration, the first voltage dividing circuit 100 includes a 1-bit ADC 114. Similarly, the configuration shown in Fig. 6 may be used. Fig. 8 shows a timing diagram corresponding to the circuit of Fig. 7. It is a chart.

[0082] The 1-bit ADC 114 is a circuit that detects the difference between the output V1 of the first amplifier circuit 102 and the output V2 of the second amplifier circuit 104, and corresponds to the error detection circuit described above. The 1-bit ADC 114 has an input terminal connected to the output of the first amplifier circuit 102 and the output of the second amplifier circuit 104, and an output terminal connected to the voltage division ratio control circuit 112. The 1-bit ADC 114 compares the input voltages and outputs a signal according to the magnitude relationship. For example, the 1-bit ADC 114 outputs a Low signal if V1 <= V2, and outputs a High signal (binary) if V1 > V2.

[0083] The voltage division ratio control circuit 112 controls the voltage division ratio by controlling the resistance value of the first voltage divider circuit based on the binary signal output by the 1-bit ADC 114. In this embodiment, when the 1-bit ADC 114 outputs a High signal, the voltage division ratio control circuit 112 controls the resistance value of the first voltage divider circuit based on the binary signal output by the 1-bit ADC 114. A control signal for switching ON / OFF is output to the first voltage divider circuit 100. The first voltage divider circuit 100 corrects the voltage division ratio by switching the state of the connected resistor based on the control signal. The calibration operation of the voltage division ratio of each component is the same as that in the second embodiment. So, I won't go into detailed explanation here.

[0084] After the calibration is completed, when a negative voltage starts to be applied to the anode of the light receiving element 30, the error determination circuit 108 calculates the ADC voltages of the first amplifier circuit 102 and the second amplifier circuit 140 according to the equations (2) and (3). The error is determined by subtracting the output via 106. In this embodiment, Ve is set to 0 when an error occurs in the positive direction (V1 - V2 > 0). If an error occurs in the negative direction, the voltage will be, for example, ground voltage.

[0085] As described above, in this embodiment, as in the second embodiment, the chip can be easily accessed from outside. Therefore, the negative voltage applied to the anode of the light receiving element 30 can be appropriately converted to a voltage lower than the positive power supply voltage, and can be appropriately monitored. Even if a negative voltage divider circuit is provided outside the chip, proper monitoring can be achieved by appropriately controlling the voltage division ratio inside the chip. The voltage division ratio may be controlled by comparing the voltages and outputting a binary signal, and controlling the resistance value of the first voltage dividing circuit 100 as described in this embodiment.

[0086] (Variation) In each of the above-described embodiments, the case where one negative voltage monitoring circuit is provided has been described. However, the embodiment of the present disclosure is not limited to this. For example, a plurality of negative voltage monitoring circuits may be provided in the photodetector pixel of the photodetector device 1. Two negative voltage monitoring circuits may be provided on the north and south sides of the array.

[0087] 9 is a circuit diagram showing an example of a negative voltage monitoring circuit 10 having two systems of voltage dividing circuits. The negative voltage monitoring circuit 10 includes a first voltage dividing circuit 100N, a first amplifier circuit 102N, a second amplifier circuit 104N, and an ADC 106N. , and a voltage division ratio control circuit 112N, and a first voltage division circuit 100S, a first amplifier circuit 102S, a second amplifier circuit 104S, an ADC 106S, and a voltage division ratio control circuit 112S.

[0088] The explanation of each circuit is the same as in the previous embodiment, so the details are omitted. Fig. 9 shows, as an example, a negative voltage monitoring circuit 10 having elements of the second embodiment, but does not have elements of the first embodiment (for example, the voltage division ratio control circuit 112N / S). It may be a form having the elements of the third embodiment (for example, 1-bit ADC 114N / S).

[0089] As described above, by providing such a configuration near both ends of the light-receiving pixel array, it becomes possible to determine whether there is any bias in the applied negative voltage depending on the region where the light-receiving elements 30 are present. Furthermore, if a malfunction occurs in one system, it is possible to continue monitoring the negative voltage in the other system.

[0090] As described above, according to this embodiment, it is possible to provide redundancy for the elements that output the divided voltage of the negative voltage monitoring circuit. By providing such redundancy, it is possible to further improve safety in the event that there is a bias in the negative voltage between regions or a malfunction occurs in the voltage dividing circuit.

[0091] (Layout example) FIG. 10 is a diagram showing an example of the layout of the light-receiving pixel and the negative voltage monitoring circuit 10. The negative voltage monitoring circuit 10 described in the above embodiment is disposed in a chip including a light-receiving element. This chip may be formed by stacking multiple semiconductor substrates. For example, the chip may be formed by stacking a first substrate The light receiving element 30 in FIG. 1 may be disposed on the first substrate 34, and the other components may be disposed on the second substrate 36. The first substrate 34 and the second substrate 36 may be stacked and encapsulated in a chip as a single semiconductor device. For example, the light receiving element 30 in FIG. 1 may be disposed on the first substrate 34, and the other components may be disposed on the second substrate 36.

[0092] 10 may be used as part of a distance measuring sensor used in dToF (direct ToF) that includes the negative voltage monitoring circuit 10 disclosed above. This stacking will be described later with some examples.

[0093] The first substrate 34 may include a pad 340 and a light-receiving pixel array 342. Although other circuits are mounted on or within the same semiconductor substrate as appropriate, they are not shown or described here.

[0094] The pads 340 connect the stacked semiconductor substrates (the first substrate 34 and the second substrate 36) together, or For example, various signals and voltages are transmitted through this pad 340. The signal may be transmitted to and received from each semiconductor layer via the signal line.

[0095] The light-receiving pixel array 342 is an area in which the light-receiving elements 30 are arranged in an array, and a negative voltage is applied to the anodes of the light-receiving elements 30 .

[0096] The second substrate 36 includes a pad 360, a pixel circuit array 362, a failure detection circuit 364, a thermometer 366, and , a signal processing circuit 368 and the negative voltage monitoring circuit 10 described in each of the above embodiments. stomach.

[0097] The pad 360 is electrically connected to the pad 340 and transmits and receives signals between the first substrate 34 and the second substrate 36. Furthermore, like the pad 340, the pad 360 may transmit and receive signals to and from the outside of the chip, if necessary.

[0098] The pixel circuit array 362 is formed by arranging pixel circuits 32 in an array, which appropriately process and output signals output by the light receiving elements 30 arranged in the light receiving pixel array 342. A pixel circuit 32 may be provided for each light receiving element 30. As another example, a pixel circuit 32 may be provided for each predetermined number of light receiving elements 30, for example, in a form in which the pixel circuits 32 share a floating diffusion. The pixel circuits are appropriately electrically connected to one or more light receiving elements 30.

[0099] The negative voltage monitoring circuit 10 monitors the voltage obtained by dividing the negative voltage and the power supply voltage, thereby monitoring whether an appropriate negative voltage is being applied to the light receiving element 30. For this reason, the negative voltage monitoring circuit 10 is mounted in the periphery of the pixel circuit array 362.

[0100] The failure detection circuit 364 detects the failure of the light receiving element 30 or various circuits mounted on the same semiconductor layer. Detects a fault. If necessary, detects the fault location and outputs a fault signal to an external or internal component that requires it.

[0101] The thermometer 366 is a circuit that detects the temperature of the semiconductor layer in which the light-receiving pixel array 362 is provided. The negative voltage monitoring circuit 10 can share, for example, an ADC with the thermometer 366. As described above, even if the ADC 106 shown in FIG. 2 etc. is shared with the thermometer 366, The ADC 106 may also detect a power supply voltage input from an external source or a negative voltage in the negative voltage monitoring circuit 10 or the like. It also operates as a BGR that converts the signal voltage generated by the It may also be something that

[0102] The signal processing circuit 368 is a circuit that appropriately processes signals output from the pixel circuits 32 of the pixel circuit array 364 and generates signals to be used for control inside the chip or signals to be output outside the chip.

[0103] As shown in FIG. 10, the negative voltage monitoring circuit 10 may be provided in two systems, as described in the modified example. This can be done.

[0104] This semiconductor layer may be implemented as a semiconductor layer as shown below, as some non-limiting specific examples. However, it is not limited to these implementations and various implementations are possible. Furthermore, only representative circuit information is described, and other necessary circuits may be placed in appropriate positions as needed.

[0105] 11 shows an example of the formation of semiconductor layers of a light receiving device including a negative voltage monitoring circuit 10. The substrate 40 is a semiconductor substrate and includes a pixel region 400, a control circuit 402, and a logic circuit 404. As shown in FIG. 11, a pixel region 400, a control circuit 402, and a logic circuit 404 are mounted on the same substrate 40. It may be configured to be provided on the

[0106] The pixel region 400 is a region where, for example, the above-mentioned light-receiving pixel array 302 and the like are provided. Pixel circuits and the like that process signals from the light-receiving pixels may be provided appropriately in this pixel region 400. It may also be provided in another region of the substrate 40, not shown.

[0107] The control circuit 402 generates signals and the like necessary to control the light-receiving pixels and the like on the chip, The logic circuit 404 outputs the generated signals to the pixels and controls each component. Signal processing for appropriately processing the signal output from the light receiving element 30 provided in the pixel region 400 The logic circuit 404 may be provided with an A / D conversion circuit to convert the analog signal output from the light receiving element 30 into a digital signal and then perform signal processing, etc. In this case, the logic circuit 404 may be provided with an A / D conversion circuit or the like, in its input section, which is partly formed by a circuit that handles analog signals. As another example, The digital signal may be appropriately processed in the logic circuit 404 .

[0108] The logic circuit 404 includes, for example, an image processing circuit as part of the signal processing circuit. Also, at least a part of the signal processing circuit and image processing circuit may be implemented not on this chip but on a separate signal processing chip provided at a location separate from the substrate 40, or may be implemented in a separate processor. For example, the signal processing circuit 368 in FIG. It may be disposed as part of the logic circuit 404.

[0109] The negative voltage monitoring circuit 10 described in each of the above embodiments includes, for example, a control circuit 402 or a The logic circuit 404 may be mounted adjacent to or in a region close to the pixel region 400.

[0110] 12 is a diagram showing another example of mounting the light receiving device. As the substrates, a first substrate 42 and a second substrate 44 are provided. The first substrate 42 and the second substrate 44 have a laminated structure, and are appropriately made of Cu-Cu Signals can be transmitted and received through connections such as via holes. , a pixel region 400 and a control circuit 402 , and the second substrate 44 may be configured to include a logic circuit 404 .

[0111] FIG. 13 is a diagram showing yet another implementation example of a light receiving device. As substrates, a first substrate 42 and a second substrate 44 are provided. The first substrate 42 and the second substrate 44 have a stacked structure, and can transmit and receive signals to and from each other appropriately via connecting portions such as via holes. For example, if the first substrate 42 is The second substrate 44 may be configured to include a substrate region 400, a control circuit 402, and a logic circuit 404.

[0112] 11 to 13, a storage area for temporarily or non-temporarily storing data may be optionally provided. In addition to these substrates, a substrate for a storage area may be provided between the first substrate 42 and the second substrate 44 or further below the second substrate 44. Good too.

[0113] The stacked substrates may be connected to each other by via holes as described above, or by a method such as a micro-dump, etc. These substrates can be stacked by any method such as CoC (Chip on Chip), CoW (Chip on Wafer), or WoW (Wafer on Wafer).

[0114] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0115] 14 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 14, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units includes, for example, a CAN (Controller Interface In-vehicle communication networks that comply with any standard, such as IEEE 802.11b / g (Interconnect Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark) It may be a work.

[0116] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 14 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a storage unit 7690. Similarly, the other control units also include a microcomputer, a communication I / F, a storage unit, and the like.

[0117] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle. The drivetrain control unit 7100 also controls control devices such as an ABS (Antilock Brake System) or an ESC (Electronic Stability Control). It may also have a function as a device.

[0118] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0119] Body system control unit 7200 controls the operation of various devices mounted on the vehicle body in accordance with various programs. For example, body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to body system control unit 7200. Body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0120] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like provided in the battery device.

[0121] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0122] The environmental sensor may be, for example, at least one of a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting sunshine intensity, and a snow sensor for detecting snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may be provided as independent sensors or devices, or may be provided as a device in which a plurality of sensors or devices are integrated.

[0123] 15 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0124] 15 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0125] The vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, and corners of the vehicle 7900 and above the windshield inside the vehicle cabin may be, for example, ultrasonic sensors or radar devices. The vehicle exterior information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0126] Returning to FIG. 14 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. The outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, text on the road, etc. based on the received information. The outside-vehicle information detection unit 7400 may also perform environment recognition processing for recognizing rainfall, fog, road conditions, etc. based on the received information. The outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle based on the received information.

[0127] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, characters on the road, etc., based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0128] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the state of the driver is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing, based on the detection information input from the driver state detection unit 7510. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0129] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 in accordance with various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is realized by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that can operate the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information by gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by the passenger, etc., using the input unit 7800, and outputs the input signal to the integrated control unit 7600. By operating this input unit 7800, passengers and the like input various data to the vehicle control system 7000 and instruct processing operations.

[0130] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also include a magnetic storage device such as an HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, etc. Alternatively, the information may be realized by a memory device such as a magneto-optical memory device.

[0131] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication between various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (Long Term Evolution), or LTE-Advanced (LTE-A), or other wireless communication protocols such as wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to devices (e.g., application servers or control servers) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. The general-purpose communication I / F 7620 may also connect to terminals present near the vehicle (e.g., terminals of drivers, pedestrians, or stores, or machine-type communication (MTC) terminals) using, for example, P2P (Peer to Peer) technology.

[0132] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in a vehicle, and may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of a lower layer IEEE802.11p and an upper layer IEEE1609, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically supports V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication. Carry out your faith.

[0133] The positioning unit 7640 is, for example, a Global Navigation Satellite System (GNSS) satellite. GNSS signals from stars (e.g., G from GPS (Global Positioning System) satellites) The positioning unit 7640 receives a wireless signal (PS signal) and performs positioning, generating position information including the latitude, longitude, and altitude of the vehicle. The positioning unit 7640 may identify the current location by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0134] The beacon receiver 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiver 7650 may be included in the dedicated communication I / F 7630 described above.

[0135] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 establishes wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). The in-vehicle device I / F 7660 may also establish a connection terminal (and a cable, if necessary) not shown in the figure to connect to a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), or an MHL (Mobile High-Definition Multimedia Interface). A wired connection such as a Wi-Fi (Wireless LAN) or a Wi-Fi (Wireless LAN Link) may be established. The in-vehicle devices 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle devices 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0136] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0137] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for a driving force generating device, a steering mechanism, or a braking device based on acquired information inside and outside the vehicle, and output a control command to the drivetrain control unit 7100. For example, the microcomputer 7610 may control an ADAS (Advanced Driver Assistance System) including vehicle collision avoidance or impact mitigation, following driving based on a following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. The microcomputer 7610 may also perform cooperative control for the purpose of realizing the functions of a vehicle control system (Vehicle Control System). The microcomputer 7610 may also perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, or the like based on acquired information about the surroundings of the vehicle.

[0138] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0139] The audio / video output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle of information. In the example of FIG. 14 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may be other devices besides these devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. When the output device is an audio output device, the audio output device converts audio signals consisting of reproduced audio data or acoustic data into analog signals and audibly outputs the analog signals.

[0140] In the example shown in FIG. 14 , at least two control units connected via the communication network 7010 may be integrated into one control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In addition, in the above description, some or all of the functions performed by one control unit may be assigned to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0141] A computer program for realizing each function of information processing in the circuit can be implemented in any of the control units, etc. Also, a computer-readable recording medium storing such a computer program can be provided. The recording medium can be, for example, a magnetic disk, an optical disk, a magneto-optical disk, or a flash memory. Also, the computer program can be distributed, for example, via a network, without using a recording medium.

[0142] In the vehicle control system 7000 described above, the negative voltage monitoring circuit 10 according to the present embodiment can be implemented in the outside vehicle information detection unit 7420 of the application example shown in FIG.

[0143] At least some of the components of the negative voltage monitoring circuit 10 described above may be implemented in a module (for example, an integrated circuit module configured on a single die) for the outside-vehicle information detection unit 7420 shown in Fig. 14. Alternatively, the negative voltage monitoring circuit 10 may be implemented by multiple control units of the vehicle control system 7000 shown in Fig. 14.

[0144] The above-described embodiment may be modified as follows.

[0145] (1) a first voltage dividing circuit that divides a power supply voltage and outputs a first voltage; a first amplifier circuit having a non-inverting input terminal to which the first voltage is input and which negatively feeds back an output voltage; a second amplifier circuit, which receives a second voltage obtained by dividing a potential difference between the power supply voltage and a voltage to be monitored that is applied to the anode of the light receiving element, and inputs the second voltage to a non-inverting input terminal thereof, and which negatively feeds back an output voltage; an error determination circuit that outputs an error signal based on a difference between an output of the first amplifier circuit and an output of the second amplifier circuit; 1. A negative voltage monitoring circuit comprising:

[0146] (2) The light receiving element is a SPAD (Single Photon Avalanche Diode). The negative voltage monitoring circuit according to (1).

[0147] (3) a negative voltage is applied to the anode of the light receiving element in a light receiving state; A negative voltage monitoring circuit according to (1) or (2).

[0148] (4) When a negative voltage is not applied to the anode of the light-receiving element, the first amplifier circuit an error detection circuit that acquires a potential difference between the first amplifier circuit and the second amplifier circuit; The negative voltage monitoring circuit according to (3) further comprises:

[0149] (5) a voltage division ratio control circuit that controls the voltage division ratio of the first voltage divider circuit based on the output of the error detection circuit; The control circuit and The negative voltage monitoring circuit according to (4) further comprises:

[0150] (6) the voltage division ratio control circuit outputs a signal including information about the controlled voltage division ratio to the error determination circuit; (5) A negative voltage monitoring circuit according to (5).

[0151] (7) The error determination circuit compares the voltage obtained by dividing the power supply voltage with the voltage obtained by amplifying the divided voltage by the amplification factor of the first amplifier circuit, and the power supply voltage and a predetermined negative voltage, based on the voltage division ratio controlled by the voltage division ratio control circuit. The voltage obtained by dividing the voltage is compared with the voltage obtained by amplifying the voltage by the amplification factor of the second amplifier circuit, and an error is judged. To determine (6) A negative voltage monitoring circuit according to (6).

[0152] (8) the error detection circuit outputs binary information obtained by comparing the output of the first amplifier circuit with the output of the second amplifier circuit; the voltage division ratio control circuit controls the voltage division ratio based on the binary information. A negative voltage monitoring circuit according to any one of (5) to (7).

[0153] (9) the voltage division ratio control circuit controls the resistance value of the first voltage division circuit to control the voltage division ratio; (8) A negative voltage monitoring circuit according to (8).

[0154] (10) The error detection circuit converts the output of the first amplifier circuit into a digital signal and The output of the second amplifier circuit is converted into a digital signal and the binary information is compared with the result. , the voltage division ratio control circuit controls the voltage division ratio based on the binary information. A negative voltage monitoring circuit according to any one of (5) to (7).

[0155] (11) the voltage division ratio control circuit controls the resistance value of the first voltage division circuit to control the voltage division ratio; The negative voltage monitoring circuit according to (10).

[0156] (12) a voltage difference between the power supply voltage and the monitored voltage is divided to output the second voltage; a second voltage divider circuit; The negative voltage monitoring circuit according to any one of (1) to (11), further comprising:

[0157] (13) The first voltage dividing circuit, the first amplifier circuit, and the second amplifier circuit are provided in two systems. A negative voltage monitoring circuit according to any one of (1) to (12).

[0158] (14) (8) A negative voltage monitoring circuit according to the present invention; a second voltage is output by dividing a potential difference between the power supply voltage and a terminal to which a negative voltage is applied; a second voltage divider circuit; Equipped with The negative voltage monitoring circuit monitors the first voltage dividing circuit when no negative voltage is applied. controlling the voltage division ratio to match the voltage division ratio of the second voltage divider circuit; Light receiving device.

[0159] (15) a negative voltage generating circuit that generates a negative voltage and applies the generated negative voltage to a terminal to which the negative voltage is applied in a light-receiving state; Furthermore, the error determination circuit outputs the error signal when a voltage obtained by dividing the power supply voltage and the voltage generated by the negative voltage generation circuit is not within a predetermined voltage range. The light receiving device according to (14).

[0160] (16) The negative voltage monitoring circuit according to (10), a second voltage is output by dividing a potential difference between the power supply voltage and a terminal to which a negative voltage is applied; a second voltage divider circuit; Equipped with The negative voltage monitoring circuit monitors the first voltage dividing circuit when no negative voltage is applied. controlling the voltage division ratio to match the voltage division ratio of the second voltage divider circuit; Light receiving device.

[0161] (17) a negative voltage generating circuit that generates a negative voltage and applies the generated negative voltage to a terminal to which the negative voltage is applied in a light-receiving state; Furthermore, the error determination circuit outputs the error signal when a voltage obtained by dividing the power supply voltage and the voltage generated by the negative voltage generation circuit is not within a predetermined voltage range. The light receiving device according to (16).

[0162] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents. [Explanation of symbols]

[0163] 1: Photodetector, 10: Negative voltage monitoring circuit, 100: 1st voltage divider circuit, 102: first amplifier circuit; 104: second amplifier circuit; 106: ADC, 108: Error determination circuit, 110: second voltage divider circuit, 112: voltage division ratio control circuit; 114: 1bit ADC, 20: Negative voltage generation circuit; 30: Light receiving element, 32: pixel circuit, 34: First board, 340: Pad, 342: Light-receiving pixel array; 36: Second board, 360: Pad, 362: Pixel circuit array, 364: Fault detection circuit, 366: Thermometer, 368: Signal processing circuitry; 40: Substrate, 42: First board, 44: Second board, 400: pixel area, 402: control circuit, 404: Logic Circuit

Claims

1. a first voltage dividing circuit that divides a power supply voltage and outputs a first voltage; a first amplifier circuit having a non-inverting input terminal to which the first voltage is input and which negatively feeds back an output voltage; a second amplifier circuit, which receives a second voltage obtained by dividing a potential difference between the power supply voltage and a voltage to be monitored that is applied to the anode of the light receiving element, and inputs the second voltage to a non-inverting input terminal thereof, and which negatively feeds back an output voltage; an error determination circuit that outputs an error signal based on a difference between an output of the first amplifier circuit and an output of the second amplifier circuit; 1. A negative voltage monitoring circuit comprising:

2. The light receiving element is a SPAD (Single Photon Avalanche Diode).

2. The negative voltage monitoring circuit of claim 1.

3. a negative voltage is applied to the anode of the light receiving element in a light receiving state; 2. The negative voltage monitoring circuit of claim 1.

4. When a negative voltage is not applied to the anode of the light-receiving element, the first amplifier circuit an error detection circuit that acquires a potential difference between the first amplifier circuit and the second amplifier circuit; 4. The negative voltage monitoring circuit of claim 3, further comprising:

5. a voltage division ratio control circuit that controls the voltage division ratio of the first voltage divider circuit based on the output of the error detection circuit; The control circuit and 5. The negative voltage monitoring circuit of claim 4, further comprising:

6. the voltage division ratio control circuit outputs a signal including information about the controlled voltage division ratio to the error determination circuit; 6. The negative voltage monitoring circuit of claim 5.

7. The error determination circuit compares the voltage obtained by dividing the power supply voltage with the voltage division ratio controlled by the voltage division ratio control circuit, and the voltage obtained by amplifying the divided voltage by the amplification factor of the first amplifier circuit with the power supply voltage and a predetermined negative voltage. The voltage obtained by dividing the voltage is compared with the voltage obtained by amplifying the voltage by the amplification factor of the second amplifier circuit, and an error is judged. To determine 7. The negative voltage monitoring circuit of claim 6.

8. the error detection circuit outputs binary information obtained by comparing the output of the first amplifier circuit with the output of the second amplifier circuit; the voltage division ratio control circuit controls the voltage division ratio based on the binary information.

6. The negative voltage monitoring circuit of claim 5.

9. the voltage division ratio control circuit controls the resistance value of the first voltage division circuit to control the voltage division ratio; 9. The negative voltage monitoring circuit of claim 8.

10. The error detection circuit converts the output of the first amplifier circuit into a digital signal and The output of the second amplifier circuit is converted into a digital signal and the binary information is compared with the result. 、 the voltage division ratio control circuit controls the voltage division ratio based on the binary information.

6. The negative voltage monitoring circuit of claim 5.

11. the voltage division ratio control circuit controls the resistance value of the first voltage division circuit to control the voltage division ratio; 11. The negative voltage monitoring circuit of claim 10.

12. a voltage difference between the power supply voltage and the monitored voltage is divided to output the second voltage; a second voltage divider circuit; 10. The negative voltage monitoring circuit of claim 1, further comprising:

13. The first voltage dividing circuit, the first amplifier circuit, and the second amplifier circuit are provided in two systems.

2. The negative voltage monitoring circuit of claim 1.

14. a negative voltage monitoring circuit according to claim 8; a second voltage is output by dividing a potential difference between the power supply voltage and a terminal to which a negative voltage is applied; a second voltage divider circuit; Equipped with The negative voltage monitoring circuit monitors the first voltage dividing circuit when no negative voltage is applied. controlling the voltage division ratio to match the voltage division ratio of the second voltage divider circuit; Light receiving device.

15. a negative voltage generating circuit that generates a negative voltage and applies the generated negative voltage to a terminal to which the negative voltage is applied in a light-receiving state; Furthermore, the error determination circuit outputs the error signal when a voltage obtained by dividing the power supply voltage and the voltage generated by the negative voltage generation circuit is not within a predetermined voltage range.

15. The light receiving device according to claim 14.

16. a negative voltage monitoring circuit according to claim 10; a second voltage is output by dividing a potential difference between the power supply voltage and a terminal to which a negative voltage is applied; a second voltage divider circuit; Equipped with The negative voltage monitoring circuit monitors the first voltage dividing circuit when no negative voltage is applied. controlling the voltage division ratio to match the voltage division ratio of the second voltage divider circuit; Light receiving device.

17. a negative voltage generating circuit that generates a negative voltage and applies the generated negative voltage to a terminal to which the negative voltage is applied in a light-receiving state; Furthermore, the error determination circuit outputs the error signal when a voltage obtained by dividing the power supply voltage and the voltage generated by the negative voltage generation circuit is not within a predetermined voltage range.

17. The light receiving device according to claim 16.

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