Indication device

Abstract

To provide a display device including a link wiring.SOLUTION: A link wiring may electrically connect a display region in which a light-emitting element is located and a pad part located outside the display region. A power voltage supply line electrically connecting the display region and the pad part may be located on an upper interlayer insulation film covering the link wiring. At least one sealing dam is arranged on the upper interlayer insulation film between the display region and the pad part. The power voltage supply line includes a main wiring and an external connecting wiring. The main wiring is spaced apart from the sealing dam. The external connecting wiring connected to the main wiring and electricity may include a material different from the main wiring. Therefore, the display device may prevent occurrence of a metal foreign matter due to a step generated by the link wiring and damage to the light-emitting element due to the metal foreign matter.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a display device in which a display area and a pad section are electrically connected by link wiring. [Background technology]

[0002] Generally, a display device provides an image to a user. For example, a display device may include light-emitting elements disposed on a device substrate. Each light-emitting element may emit light exhibiting a particular color. For example, each light-emitting element may include a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode.

[0003] The device substrate may include a display area where light-emitting elements are located and a bezel area (or non-display area) located outside the display area. A pad unit for transmitting an externally applied signal to the display area may be arranged in the bezel area. For example, a link wiring electrically connecting the display area and the pad unit may be arranged on the bezel area of ​​the device substrate.

[0004] A power supply voltage supply line that supplies a power supply voltage to the display area for operating each light-emitting element may cross the link wiring. For example, the power supply voltage supply line may be disposed on an upper interlayer insulating film that covers the link wiring. However, the upper interlayer insulating film may have a step due to the link wiring. Because no organic insulating film is located around the sealing dam formed between the display area and the pad unit, a residual film may be generated around the sealing dam due to the step of the upper interlayer insulating film during the process of forming the power supply voltage supply line. The residual film generated during the process of forming the power supply voltage supply line, which is made of a conductive material, may evaporate / diffuse in a subsequent process. Therefore, in a display device, the residual film may deteriorate light-emitting elements formed after the power supply voltage supply line. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a display device that can prevent the generation of a residual film around a sealing dam located above a bezel area due to a process of forming a power supply voltage supply line.

[0006] The problems to be solved by the present invention are not limited to those described above. Problems not described in this specification will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] The display device according to the technical idea of ​​the present invention for achieving the above object includes an element substrate. The element substrate includes a display region and a bezel region. An upper planarization film is positioned above the display region. An upper interlayer insulating film is positioned between the element substrate and the upper planarization film. The upper interlayer insulating film extends above the bezel region. A first dam pattern is positioned on the upper interlayer insulating film in the bezel region. The first dam pattern is spaced apart from the upper planarization film. A light-emitting element is positioned above a pixel region of the display region. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked in order on the upper planarization film. Link wiring is arranged between the element substrate and the upper interlayer insulating film. Power supply voltage supply lines are arranged on the upper interlayer insulating film. The link wiring and the power supply voltage supply lines electrically connect between the display area and the pad portion in the bezel area. The power supply voltage supply lines include main wiring and external connection wiring. The main wiring is located outside the first dam. The external connection wiring is electrically connected to the main wiring. The external connection wiring located above the bezel area includes a different material from the main wiring.

[0008] A device protection layer may be located between the upper interlayer insulating film and the upper planarizing layer. Ends of the main wiring may be covered with the device protection layer. External connection wiring may be disposed on the device protection layer.

[0009] The first dam pattern may include the same material as the upper planarization film. The external connection wiring may include the same material as the first electrode of the light-emitting element. The external connection wiring may extend along the surface of the first dam pattern. A second dam pattern may be disposed on the first dam pattern. A portion of the external connection wiring located on the surface of the first dam pattern may be covered with the second dam pattern.

[0010] The power supply voltage supply line may include an external dummy pattern located between the upper interlayer insulating film and the first dam pattern, and the external connection wiring may be electrically connected to the external dummy pattern.

[0011] The external dummy pattern may include the same material as the main wiring. The power supply voltage supply line may extend in a first direction. The first dam pattern and the external dummy pattern may extend in a second direction. The second direction may be perpendicular to the first direction. The width of the external dummy pattern in the first direction may be greater than the width of the first dam pattern in the first direction.

[0012] An auxiliary dummy pattern may be disposed between the external dummy pattern and the first dam pattern. The auxiliary dummy pattern may include a material different from that of the external dummy pattern and the external connection wiring.

[0013] A lower planarization layer may be disposed between the upper interlayer insulating film and the upper planarization layer. The lower planarization layer may be spaced apart from the first dam pattern. An internal dummy wiring may be disposed between the lower planarization layer and the upper planarization layer. The main wiring may be electrically connected to the internal dummy wiring between the device substrate and the lower planarization layer.

[0014] A pixel driving circuit may be located between the pixel region of the element substrate and the lower planarization film. An intermediate electrode may be located between the lower planarization film and the upper planarization film in the pixel region. The intermediate electrode may be electrically connected to the pixel driving circuit and the light-emitting element. The intermediate electrode may include the same material as the internal dummy wiring.

[0015] A lower interlayer insulating film may be located between the element substrate and the upper interlayer insulating film. The link wiring may include a first link and a second link. The first link may be located between the element substrate and the lower interlayer insulating film. The second link may be located between the lower interlayer insulating film and the upper interlayer insulating film. The second link may be located between the first links. [Effects of the Invention]

[0016] A display device according to the technical concept of the present invention includes an upper interlayer insulating film located between a link wiring electrically connecting a display area and a pad section and a power supply voltage supply line, and a first dam pattern located on the upper interlayer insulating film between the display area and the pad section. The power supply voltage supply line includes a main wiring spaced apart from the first dam pattern and an external connection wiring electrically connected to the main wiring, and the external connection wiring may be made of a material different from that of the main wiring. That is, in a display device according to the technical concept of the present invention, after the conductive material for forming the main wiring is removed from the periphery of the first dam pattern, the external connection wiring electrically connected to the main wiring can be formed in a subsequent process. As a result, in a display device according to the technical concept of the present invention, the generation of residual film due to steps generated by the link wiring during the main wiring formation process can be prevented or reduced. Therefore, in a display device according to the technical concept of the present invention, deterioration of light-emitting elements due to residual film of conductive material can be prevented or reduced. Furthermore, in a display device according to the technical concept of the present invention, the energy and cost required for manufacturing can be reduced by process optimization. can be reduced. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing a circuit of a unit pixel region in the display device according to the embodiment of the present invention. [Figure 3] FIG. 2 is a diagram schematically illustrating a cross section of a pixel region in the display device according to the embodiment of the present invention. [Figure 4]FIG. 2 is an enlarged view of the K region in FIG. 1. [Figure 5] FIG. 5 is a cross-sectional view taken along line II' in FIG. 4. [Figure 6] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present invention. [Figure 7] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present invention. [Figure 8] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present invention. [Figure 9] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] The above-mentioned objectives, technical configurations, and effects of the present invention will be more clearly understood from the following detailed description taken in conjunction with the drawings illustrating embodiments of the present invention. The embodiments of the present invention are provided to enable the technical concept of the present invention to be fully conveyed to those skilled in the art, and the present invention is not limited to the embodiments described below and may be configured in other forms.

[0019] Furthermore, parts designated by the same reference numerals throughout the specification refer to the same components, and the lengths and thicknesses of layers or regions in the drawings may be exaggerated for convenience. Note that when a first component is described as being "on" a second component, this does not only mean that the first component is located above and in direct contact with the second component, but also includes cases where a third component is located between the first and second components.

[0020] Here, the terms "first," "second," etc. are used to describe various components and to distinguish one component from another. However, the first component and the second component may be arbitrarily named according to the convenience of those skilled in the art without departing from the technical spirit of the present invention.

[0021] The terms used in the present specification are merely used to describe specific embodiments and are not intended to limit the present invention. For example, elements referred to in the singular include a plurality of elements unless the context clearly dictates otherwise. Furthermore, in the present specification, terms such as "comprise" or "have" are intended to specify the presence of features, numbers, steps, operations, elements, parts, or combinations thereof described in the specification. It should be understood that this does not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof.

[0022] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. Terms defined in commonly used dictionaries should be interpreted as meanings consistent with the context of the relevant art, and should not be interpreted in an ideal or overly formal sense unless clearly defined in the specification of the present invention.

[0023] (Example) Fig. 1 is a diagram schematically illustrating a display device according to an embodiment of the present invention. Fig. 2 is a diagram illustrating a circuit of a unit pixel region in a display device according to an embodiment of the present invention. Fig. 3 is a diagram schematically illustrating a cross section of a pixel region in a display device according to an embodiment of the present invention. 1 to 3, a display device according to an embodiment of the present invention may include a display panel DP. The display panel DP may generate an image to be provided to a user. For example, the display panel DP may include a plurality of pixel areas PA. The plurality of pixel areas PA may be defined by the intersection of signal lines GL, DL, and PL.

[0024] Various signals may be provided to each pixel area PA via signal wiring GL, DL, and PL. For example, the signal wiring GL, DL, and PL may include a gate line GL that applies a gate signal to each pixel area PA, a data line DL that applies a data signal to each pixel area PA, and a voltage line PL that supplies a positive power supply voltage to each pixel area PA. The gate line GL is electrically connected to a gate driver GD, and the data line DL is electrically connected to a data driver. The voltage line PL may be electrically connected to a power supply unit.

[0025] The gate driver GD and the data driver may be controlled by a timing controller. For example, the gate driver GD may receive a clock signal, a reset signal, a start signal, an output enable signal, etc. from the timing controller, and the data driver may receive a digital video data source output enable signal, a source timing signal, etc. from the timing controller.

[0026] Each pixel area PA may embody a specific color. For example, a light-emitting element 300 and a pixel driving circuit DC electrically connected to the light-emitting element 300 may be disposed within each pixel area PA. The light-emitting element 300 and the pixel driving circuit DC of each pixel area PA may be located on an element substrate 100. The element substrate 100 may include an insulating material. For example, the element substrate 100 may include glass, plastic, or a flexible polymer film. The flexible polymer film may include any of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS).

[0027] The light-emitting element 300 may emit light exhibiting a particular color. For example, the light-emitting element 300 may include a first electrode 310, a second electrode 330, and a light-emitting layer 320 located between the first electrode 310 and the second electrode 330.

[0028] The first electrode 310 may include a conductive material. The first electrode 310 may include a material with high reflectivity. For example, the first electrode 310 may include metals such as aluminum (Al) and silver (Ag). The first electrode 310 may have a multi-layer structure. For example, the first electrode 310 may have a structure in which a reflective electrode made of metal is located between transparent electrodes made of a transparent conductive material such as ITO or IZO. Pure silver (Ag) reacting with oxygen or nitrogen may reduce reflectivity. Therefore, the first electrode 310 may be formed as an ITO / Ag / ITO stacked structure, or may be formed by adding impurities such as palladium (Pd) or copper (Cu).

[0029] The light-emitting layer 320 may generate light having a brightness corresponding to the voltage difference between the first electrode 310 and the second electrode 320. For example, the light-emitting layer 320 may include an emission material layer (EML) containing a light-emitting material. The light-emitting material may include an organic material, an inorganic material, or a hybrid material. For example, a display device according to an embodiment of the present invention may be an organic light-emitting display device containing an organic light-emitting material.

[0030] The light-emitting layer 320 may have a multi-layer structure. For example, the light-emitting layer 320 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL). Therefore, in a display device according to an embodiment of the present invention, the light-emitting efficiency of the light-emitting layer 320 may be improved.

[0031] The second electrode 330 may include a conductive material. The second electrode 330 may include a material different from that of the first electrode 310. The transmittance of the second electrode 330 may be greater than that of the first electrode 310. For example, the second electrode 330 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. Therefore, a display device according to an embodiment of the present invention may be a top emission type display device in which light generated by the light emitting layer 320 is emitted to the outside through the second electrode 330. However, display devices according to other embodiments of the present invention may be bottom emission type display devices in which the transmittance of the second electrode 330 is lower than that of the first electrode 330.

[0032] The pixel driving circuit DC may supply a driving current corresponding to a data signal to the light emitting element 300 for one frame in response to a gate signal. For example, the pixel driving circuit DC may include a first thin film transistor T1, a second thin film transistor T2, and a storage capacitor Cst. The first thin film transistor T1 and the second thin film transistor T2 may each be a PMOS transistor that is turned on by a low-level gate voltage, or an NMOS transistor that is turned on by a high-level gate voltage. Each pixel driving circuit DC may have a different number of thin film transistors T1, T2, and storage capacitors Cst. For example, each pixel driving circuit DC may have a 3T1C structure including three thin film transistors T1, T2 and one storage capacitor Cst, a 3T2C structure including three thin film transistors T1, T2 and one storage capacitor Cst, a 5T1C structure including five thin film transistors T1, T2 and one storage capacitor Cst, a 5T2C structure including five thin film transistors T1, T2 and two storage capacitors Cst, a 7T2C structure including seven thin film transistors T1, T2 and two storage capacitors Cst, etc.

[0033] The first thin film transistor T1 may include a first semiconductor pattern, a first gate electrode, a first source electrode, and a first drain electrode. The first thin film transistor T1 may transmit a data signal to the second thin film transistor T2 in response to a gate signal. For example, the first thin film transistor T1 may function as a gate electrode. The first gate electrode of the first thin film transistor T1 may be electrically connected to one of the gate lines GL, and the first source electrode may be electrically connected to one of the data lines DL.

[0034] The first semiconductor pattern may include a semiconductor material. For example, the first semiconductor pattern may include amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), or an oxide semiconductor. The oxide semiconductor may be formed from an oxide of a metal, such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), a metal combined with the metal, or an oxide of a metal combined with the metal. For example, the oxide semiconductor may include zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO). The first semiconductor pattern may include a first source region, a first channel region, and a first drain region. The first channel region may be located between the first source region and the first drain region. The resistance of the first source region may be less than the resistance of the first channel region, and the resistance of the first drain region may be less than the resistance of the first channel region. For example, the first source region and the first drain region may include conductive regions of an oxide semiconductor. The oxide semiconductor may be selectively doped by doping a pure polycrystalline silicon pattern with Group V or Group III impurity ions, such as phosphorus (P) or boron (B).

[0035] The first channel region may be a non-conductive region of the oxide semiconductor.

[0036] The first gate electrode may include a conductive material. For example, the first gate electrode may be a single layer or multiple layers of a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), neodymium (Nd), and tungsten (W). The first gate electrode may be disposed on the first semiconductor pattern. For example, the first gate electrode may overlap a first channel region of the first semiconductor pattern. The first source region and the first drain region of the first semiconductor pattern may be located outside the first gate electrode. The first gate electrode may be insulated from the first semiconductor pattern. For example, the first source region of the first semiconductor pattern may be electrically connected to the first drain region of the first semiconductor pattern by a gate signal. The first source electrode may be a single layer or multiple layers of a conductive material. For example, the first source electrode may include a metal such as aluminum (Al), gold (Au), neodymium (Nd), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode may include a material different from that of the first gate electrode. The first source electrode may be disposed on a layer different from that of the first gate electrode. For example, the first source electrode may be insulated from the first gate electrode. The first source electrode may be electrically connected to the first source region of the first semiconductor pattern.

[0037] The first drain electrode may be a single layer or multiple layers of a conductive material. For example, the first drain electrode may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode may include a different material from the first gate electrode. The first drain electrode may be disposed on a different layer from the first gate electrode. For example, the first drain electrode may be disposed on the same layer as the first source electrode. The first drain electrode may include substantially the same material as the first source electrode. The first drain electrode may be insulated from the first gate electrode. For example, the first drain electrode may be electrically connected to the first drain region of the first semiconductor pattern.

[0038] The second thin film transistor T2 may include at least a second semiconductor pattern 221, a second gate electrode 223, a second source electrode 225, and a second drain electrode 227. The second thin film transistor T2 may generate a driving current corresponding to a data signal. For example, the second thin film transistor T2 may function as a driving thin film transistor. The second gate electrode 223 of the second thin film transistor T2 is electrically connected to the first drain electrode, and the second source electrode 225 of the second thin film transistor T2 is electrically connected to one of the voltage lines PL. The light-emitting element 300 is electrically connected to the second thin film transistor T2. For example, the second drain electrode 227 may be electrically connected to the first electrode 310 of the light-emitting element 300, and the second electrode 330 of the light-emitting element 300 may be electrically connected to ground.

[0039] The second semiconductor pattern 221 may include a semiconductor material. For example, the second semiconductor pattern 221 may include amorphous silicon (a-Si), polycrystalline silicon (Poly-Si), or an oxide semiconductor. The oxide semiconductor may be formed from one of indium-gallium-zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), and indium gallium oxide (IGO). The second semiconductor pattern 221 may include a second channel region located between the second source region and the second drain region. The second channel region may have a higher resistance than the second source region and the second drain region. For example, the second source region and the second drain region may include conductive regions of an oxide semiconductor, and the second channel region may be a non-conductive region of the oxide semiconductor. The oxide semiconductor may be selectively doped by doping a pure polycrystalline silicon pattern with impurity ions of group V or group III, such as phosphorus (P) or boron (B).

[0040] The second semiconductor pattern 221 may be located on the same layer as the first semiconductor pattern. The second semiconductor pattern 221 may include substantially the same material as the first semiconductor pattern. The second semiconductor pattern 221 may be formed in the same process as the first semiconductor pattern. For example, the second semiconductor pattern 221 may be formed simultaneously with the first semiconductor pattern. The second gate electrode 223 may include a conductive material. For example, the second gate electrode 223 may be a single layer or multiple layers made of a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), neodymium (Nd), and tungsten (W), or an alloy thereof. The second gate electrode 223 may be located on the same layer as the first gate electrode. The second gate electrode 223 may include substantially the same material as the first gate electrode. For example, the second gate electrode 223 may be formed simultaneously with the first gate electrode.

[0041] The second gate electrode 223 may be located on the second semiconductor pattern 221. For example, the second gate electrode 223 may overlap with the second channel region of the second semiconductor pattern 221. The second source region and the second drain region of the second semiconductor pattern 221 are located outside the second gate electrode 223. The second gate electrode 223 may be insulated from the second semiconductor pattern 221. For example, the second channel region of the second semiconductor pattern 221 may have a conductivity corresponding to a voltage applied to the second gate electrode 223.

[0042] The second source electrode 225 may be a single layer or multiple layers made of a conductive material. For example, the second source electrode 225 may include a metal such as aluminum (Al), gold (Au), neodymium (Nd), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode 225 may include a different material from the second gate electrode 223. The second source electrode 225 may be disposed on a different layer from the second gate electrode 223. For example, the second source electrode 225 may be insulated from the second gate electrode 223. The second source electrode 225 is electrically connected to the second source region of the second semiconductor pattern 221.

[0043] The second source electrode 225 may be disposed on the same layer as the first source electrode. The second source electrode 225 may include substantially the same material as the first source electrode. The second source electrode 225 may be formed in the same process as the first source electrode. For example, the second source electrode 225 may be formed simultaneously with the first source electrode.

[0044] The second drain electrode 227 may be a single layer or multiple layers made of a conductive material. For example, the second drain electrode 227 may include a metal such as aluminum (Al), gold (Au), neodymium (Nd), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), or tungsten (W). The second drain electrode 227 may include a different material from the second gate electrode 223. The second drain electrode 227 may be located on a different layer from the second gate electrode 223. For example, the second drain electrode 227 may be disposed on the same layer as the second gate electrode 225. The second drain electrode 227 may include substantially the same material as the second source electrode 227. For example, the second drain electrode 227 may be insulated from the second gate electrode 223.

[0045] The second drain electrode 227 is electrically connected to the second drain region of the second semiconductor pattern 221 .

[0046] The second drain electrode 227 may be located on substantially the same layer as the first drain electrode. The second drain electrode 227 may include the same material as the first drain electrode. For example, the second drain electrode 227 may be formed simultaneously with the first drain electrode.

[0047] The storage capacitor Cst may sustain a signal applied to the second gate electrode 223 of the second thin film transistor T2 for one frame. For example, the storage capacitor Cst may be electrically connected between the second gate electrode 223 and the second drain electrode 227 of the second thin film transistor T2. The storage capacitor Cst may have a stacked structure of capacitor electrodes 231 and 232. For example, the storage capacitor Cst may include a first capacitor electrode 231 and a second capacitor electrode 232. At least one of the capacitor electrodes 231 and 232 may be formed using the same process as the formation of the first thin film transistor T1 and the second thin film transistor T2. For example, the first capacitor electrode 231 may include substantially the same material as the second gate electrode 223. The second capacitor electrode 232 may include a different material from the second source electrode 225 and the second drain electrode 227. For example, the second capacitor electrode 232 may be disposed on a different layer from the second source electrode 225 and the second drain electrode 227.

[0048] A number of insulating films 110, 120, 130, 140, 150, and 160 for preventing or reducing unnecessary electrical connections within each pixel region PA may be disposed on the device substrate 100. For example, a buffer insulating film 110, a gate insulating film 120, a lower interlayer insulating film 130, an upper interlayer insulating film 140, a device protective film 150, a lower planarizing film 160, an upper planarizing film 170, and a bank insulating film 180 may be disposed on the device substrate 100.

[0049] The buffer insulating film 110 may be disposed near the element substrate 100. The buffer insulating film 110 can prevent or reduce contamination by the element substrate 100 during the formation process of the pixel driving circuit DC located in each pixel region PA. For example, the upper surface of the element substrate 100 facing the pixel driving circuit DC in each pixel region PA may be completely covered by the buffer insulating film 110. The first thin film transistor T1, the second thin film transistor T2, and the storage capacitor Cst in each pixel region PA may be located on the buffer insulating film 110. The buffer insulating film 110 may include an insulating material. For example, the buffer insulating film 110 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer insulating film 110 may be formed as a single layer of an inorganic insulating film or as a multilayer. For example, the buffer insulating film 110 may be a single layer of silicon oxide (SiOx) or a single layer of silicon nitride (SiNx). The buffer insulating film 110 may have a multilayer structure. For example, the buffer insulating film 110 may have a structure in which at least one layer made of silicon oxide (SiOx), at least one layer made of silicon nitride (SiNx), and at least one layer made of amorphous silicon (a-Si) are alternately stacked.

[0050] The gate insulating film 120 may be located on the buffer insulating film 110. The gate insulating film 120 may insulate the first semiconductor pattern and the first gate electrode of the first thin film transistor T1 located in each pixel region PA and the semiconductor pattern 221 and the second gate electrode 223 of the second thin film transistor T2 located in each pixel region PA. For example, the gate insulating film 120 may cover the first semiconductor pattern and the second semiconductor pattern 221 in each pixel region PA. The first gate electrode and the second gate electrode 223 in each pixel region PA may be located on the gate insulating film 120. The first capacitor electrode 231 in each pixel region PA may be located on the gate insulating film 120. The gate insulating film 120 may include an insulating material. For example, the gate insulating film 120 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating film 120 may be a single layer or a multilayer including inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx).

[0051] The lower interlayer insulating film 130 and the upper interlayer insulating film 140 may insulate the source electrode 225 and the drain electrode 227 of each thin film transistor T1, T2 from the gate electrode 223 of the corresponding thin film transistor T1, T2. The upper interlayer insulating film 140 may be located on the lower interlayer insulating film 130. For example, the lower interlayer insulating film 130 may cover the first gate electrode and the second gate electrode 223 of each pixel region PA. The first capacitor electrode 231 of the storage capacitor Cst located in each pixel region PA may be covered by the lower interlayer insulating film 130. The first source electrode, the first drain electrode, the second source electrode 225, and the second drain electrode 227 of each pixel region PA may be located on the upper interlayer insulating film 140. The lower interlayer insulating film 130 and the upper interlayer insulating film 140 may include an insulating material. For example, the lower interlayer insulating film 130 and the upper interlayer insulating film 140 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower interlayer insulating film 130 and the upper interlayer insulating film 140 may each have a structure in which multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx) are stacked. For example, the lower interlayer insulating film 130 and the upper interlayer insulating film 140 may each include a layer made of silicon nitride (SiNx) containing hydrogen particles. The upper interlayer insulating film 140 may include a material different from that of the lower interlayer insulating film 130. Therefore, in a display device according to an embodiment of the present invention, the stability of the pixel driving circuit DC located in each pixel area PA can be improved. The second capacitor electrode 232 of each pixel area PA may be located between the lower interlayer insulating film 130 and the upper interlayer insulating film 140.

[0052] The element protective film 150 may be located on the upper interlayer insulating film 140. The element protective film 150 can prevent or reduce damage to the pixel driving circuit DC located in each pixel region PA due to external impact and moisture. For example, the first source electrode, the first drain electrode, the second source electrode 225, and the second drain electrode 227 of each pixel region PA may be covered by the element protective film 150. The element protective film 150 may include an insulating material. For example, the element protective film 150 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The element protective film 150 may be a single layer made of silicon oxide (SiOx), a single layer made of silicon nitride (SiNx), a single layer made of silicon oxide (SiOxNy), or a multilayer made of a stack of these layers.

[0053] The lower planarization film 160 and the upper planarization film 170 may be stacked in this order on the element protection film 150. For example, the lower planarization film 160 may be located between the element protection film 150 and the upper planarization film 170. The lower planarization film 160 and the upper planarization film 170 may eliminate steps due to the pixel driving circuits DC in each pixel area PA. For example, the upper surface of the upper planarization film 170 facing the element substrate 100 may be flat. The lower planarization film 160 and the upper planarization film 170 may include an insulating material. The lower planarization film 160 and the upper planarization film 170 may include a different material from that of the element protection film 150. For example, the lower planarization film 160 and the upper planarization film 170 may include an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, an unsaturated polyester resin, a polyphenylene resin, a polyphenylene sulfide resin, and benzocyclobutene. The upper planarization film 170 may include substantially the same material as the lower planarization film 160. The upper planarization film 170 is in direct contact with the upper surface of the lower planarization film 160 facing the device substrate 100. For example, the interface between the lower planarization film 160 and the upper planarization film 170 may not be recognized.

[0054] The light emitting element 300 of each pixel region PA may be located on the upper planarization film 170. For example, the first electrode 310, the light emitting layer 320, and the second electrode 330 of each pixel region PA may be sequentially stacked on the upper planarization film 170 located in the corresponding pixel region PA. The first electrode 310 of each pixel region PA may be in direct contact with the upper surface of the upper planarization film 170. As a result, in the display device according to the embodiment of the present invention, it is possible to prevent or reduce brightness deviation depending on the generation position of light emitted from each light emitting element 300.

[0055] Intermediate electrodes 510 may be disposed between the lower planarization film 160 and the upper planarization film 170. The intermediate electrodes 510 may include a conductive material. For example, the intermediate electrodes 510 may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first electrode 310 in each pixel region PA is electrically connected to the second drain electrode 227 in the corresponding pixel region PA through one of the intermediate electrodes 510. For example, each intermediate electrode 510 penetrates the lower planarization film 160 in each pixel region PA to directly contact the second drain electrode 227 in the corresponding pixel region PA, and the first electrode 310 in each pixel region PA penetrates the upper planarization film 170 in the corresponding pixel region PA to directly contact one of the intermediate electrodes 510.

[0056] The bank insulating film 180 may be located on the upper planarizing film 170. The bank insulating film 180 may expose at least a portion of the first electrode 310 located in each pixel region PA. The bank insulating film 180 may define a light-emitting region in each pixel region PA. For example, the bank insulating film 180 may cover the outer periphery of the first electrode 310 located in each pixel region PA. The light-emitting layer 320 and the second electrode 330 of each pixel region PA may be sequentially stacked on the partial region of the first electrode 310 exposed by the bank insulating film 180. The bank insulating film 180 may include an insulating material. For example, the bank insulating film 180 may include an organic insulating material. The bank insulating film 180 may include a different material from the upper planarizing film 170. A spacer may be disposed on the bank insulating film 180 to prevent or reduce damage due to contact with a deposition mask.

[0057] At least a portion of the light-emitting layer 520 in each pixel region PA may extend on the bank insulating film 160. For example, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) in each pixel region PA may be formed on the entire surface of the display area AA. This can improve process efficiency in the display device according to this embodiment of the present invention.

[0058] At least a portion of the light-emitting layer 320 in each pixel region PA may extend outside the pixel region PA. For example, at least one of the hole injection layer HIL, hole transport layer HTL, electron transport layer ETL, and electron injection layer EIL located in each pixel region PA may extend over the bank insulating film 180. At least one of the hole injection layer HIL, hole transport layer HTL, electron transport layer ETL, and electron injection layer EIL located in each pixel region PA may be formed simultaneously with the corresponding layer located in an adjacent pixel region PA. For example, at least one of the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) may be formed on the entire surface of the display region AA. This improves process efficiency in display devices according to embodiments of the present invention.

[0059] The voltage applied to the second electrode 330 in each pixel region PA may be the same as or similar to the voltage applied to the second electrode 330 in an adjacent pixel region PA. For example, a negative power supply voltage may be applied to the second electrode 330 in each pixel region PA. The second electrode 330 in each pixel region PA may be electrically connected to the second electrode 330 in the adjacent pixel region PA. The second electrode 330 in each pixel region PA may include substantially the same material as the second electrode 330 in the adjacent pixel region PA. For example, the second electrode 330 in each pixel region PA may be formed simultaneously with the second electrode 330 in the adjacent pixel region PA. The second electrode 330 in each pixel region PA may be in direct contact with the second electrode 330 in the adjacent pixel region PA. For example, the second electrode 330 in each pixel region PA may extend outside the pixel region PA. Therefore, in a display device according to an embodiment of the present invention, the process of forming the second electrode 330 in each pixel region PA may be simplified. Therefore, in a display device according to an embodiment of the present invention, process efficiency may be improved. Furthermore, in the display device according to the embodiment of the present invention, the brightness of the light emitted from the light emitting element 300 of each pixel area PA can be adjusted by a data signal applied to the pixel driving circuit DC of the pixel area PA.

[0060] An encapsulating unit 400 may be disposed on the light-emitting element 300 in each pixel region PA. The encapsulating unit 400 can prevent or reduce damage to the light-emitting element 300 due to external moisture, oxygen, and impact. For example, the light-emitting element 300 in each pixel region PA may be completely covered by the encapsulating unit 400. The encapsulating unit 400 may have a single-layer structure or a multi-layer structure. For example, the encapsulating unit 400 may include a single layer or sequentially stacked first encapsulating layer 410, second encapsulating layer 420, and third encapsulating layer 430 made of inorganic materials such as silicon nitride (SiNx) and aluminum oxide (AlOx). The first encapsulating layer 410 may be located on the second electrode 330 in each pixel region PA. The first encapsulating layer 410, second encapsulating layer 420, and third encapsulating layer 430 may include an insulating material. The second encapsulating layer 420 may include a different material from the first encapsulating layer 410 and the third encapsulating layer 430. For example, the first encapsulating layer 410 and the third encapsulating layer 430 may include an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx), and the second encapsulating layer 420 may include an organic insulating material. As a result, in the display device according to this embodiment, damage to the light emitting element 300 caused by external moisture, oxygen, and impact can be effectively prevented or reduced. Steps caused by the light emitting element 300 can be eliminated by the second encapsulating layer 420. For example, the upper surface of the encapsulating unit 400 facing the element substrate 100 on the pixel area PA may be a flat plane.

[0061] The display panel DP may include a display area AA in which the pixel area PA is located and a bezel area BZ located outside the display area AA. At least one of the gate driver GD, the data driver, the power supply unit, and the timing controller may be disposed on the bezel area BZ of the display panel DP. For example, a display device according to an embodiment of the present invention may be a GIP (Gate-In-Panel) type display device in which the gate driver GD is formed in the bezel area BZ of the display panel DP. However, in display devices according to other embodiments of the present invention, at least one of the gate driver GD, the data driver, the power supply unit, and the timing controller may be connected to the element substrate 100 using a TCP or COF method. A pad unit PAD may be disposed in the bezel area BZ. A signal applied from outside the element substrate 100 may be transmitted to the display area AA through the pad unit PAD. For example, at least one gate link wiring GLL electrically connecting the pad unit PAD to the gate driver GD and a data link wiring DLL electrically connecting the pad unit PAD to the display area AA may be disposed on the element substrate 100. Each data line DL may be electrically connected to one of the data link wirings DLL. For example, the data driver may apply a data line DL data signal to each pixel area PA via the pad unit PAD, the data link wiring DLL, and the data line DL.

[0062] FIG. 4 is an enlarged view of region K in FIG. 1. FIG. 5 is a cross-sectional view taken along line II' in FIG. 4. Referring to FIGS. 1 to 5, in a display device according to an embodiment of the present invention, an element substrate 100 may include a display area AA and a bezel area BZ. A pad PAD, a sealing dam 105, and a first power supply voltage supply line VDL may be arranged on the element substrate 100. The first power supply voltage supply line VDL may include a first wiring (or main wiring VL) and a second wiring (or external connection wiring OV). The main wiring VL may include a first end and a second end. The second end of the main wiring VL is electrically connected to the external connection wiring OV. The second end of the main wiring VL may not overlap the dam 105. The power supply voltage supply line VDL may further include a third wiring (e.g., an external dummy pattern VP) electrically connected to the external connection wiring OV. The external dummy pattern VP may overlap the dam 105.

[0063] The data link wiring DLL may include a first link LL1 and a second link LL2. The second link LL2 may be located between the first links LL1. The second link LL2 may include a different material from the first link LL1. The second link LL2 may be disposed on a different layer from the first link LL1. The data link wiring DLL may be formed using the process of forming the pixel driving circuit DC for each pixel area PA. For example, the first link LL1 may be formed simultaneously with the first capacitor electrode 231 for each pixel area PA, and the second link LL2 may be formed simultaneously with the second capacitor electrode 232 for each pixel area PA. The first link LL1 may include substantially the same material as the first capacitor electrode 231 for each pixel area PA, and the second link LL2 may include substantially the same material as the second capacitor electrode 232 for each pixel area PA. Therefore, in a display device according to an embodiment of the present invention, the area occupied by the data link wiring DLL can be reduced or minimized without reducing process efficiency.

[0064] In the display device according to the embodiment of the present invention, some of the insulating films 110, 120, 130, 140, 150, 160, 170, and 180 may extend over the bezel region BZ of the device substrate 100. For example, in the display device according to the embodiment of the present invention, the buffer insulating film 110, the gate insulating film 120, the lower interlayer insulating film 130, the upper interlayer insulating film 140, and the device protective film 150 may extend over the bezel region BZ of the device substrate 100. The first link LL1 may be located on the same layer as the first capacitor electrode 231 of each pixel region PA. For example, the first link LL1 may be located between the gate insulating film 120 and the lower interlayer insulating film 130. The second link LL2 may be located on the same layer as the second capacitor electrode 232 of each pixel region PA. For example, the second link LL2 may be located between the lower interlayer insulating film 130 and the upper interlayer insulating film 140. Therefore, in a display device according to one embodiment of the present invention, the first link LL1 and the second link LL2 of the data link wiring DLL arranged side by side can be insulated without reducing process efficiency. However, in display devices according to other embodiments of the present invention, the first link LL1 can be located on a different layer from the first capacitor electrode 231 of each pixel area PA, and the second link LL2 can be located on a different layer from the second capacitor electrode 232 of each pixel area PA.

[0065] At least one sealing dam 105 may be disposed on the bezel region BZ. The sealing dam 105 may block the flow of the second sealing layer 420, which is an organic insulating film. For example, the second sealing layer 420 may be formed within the region defined by the sealing dam 105. The sealing dam 105 may extend along the outer periphery of the display region AA. The sealing dam 105 may be disposed between the display region AA and the outer periphery gate driver GD. The sealing dam 105 may cross between the display region AA and the pad unit PAD. Therefore, in a display device according to an embodiment of the present invention, malfunction of the gate driver GD due to the second sealing layer 420 can be prevented or reduced. Furthermore, in a display device according to an embodiment of the present invention, the second sealing layer 420 can prevent or reduce distortion of a signal applied via the pad unit PAD. Therefore, the reliability of the display device according to this embodiment can be improved.

[0066] The sealing dam 105 may be formed using a process for forming insulating films 110, 120, 130, 140, 150, 160, 170, and 180 stacked on the device substrate 100. For example, the sealing dam 105 may include a first dam pattern 105a formed simultaneously with the upper planarization film 170 and a second dam pattern 105b formed simultaneously with the bank insulating film 180. The first dam pattern 105a may have substantially the same thickness as the upper planarization film 170. An upper surface of the second dam pattern 105b facing the device substrate 100 may be substantially flush with an upper surface of the bank insulating film 180 facing the device substrate 100. For example, the first dam pattern 105a may be covered with the second dam pattern 105b. The sealing dam 105 may be separated from the lower planarization film 160, the upper planarization film 170, and the bank insulating film 160. For example, the process of forming the sealing dam 105 may include removing the lower planarization film 160, the upper planarization film 170, and the bank insulating film 180 formed around the sealing dam 105. The lower planarization film 160, the upper planarization film 170, and the bank insulating film 180 may not be located around the sealing dam 105. Therefore, in a display device according to an embodiment of the present invention, the sealing dam 105 can effectively block the flow of the second sealing layer 420. The first sealing layer 410 and the third sealing layer 430 can extend outside the sealing dam 105. For example, outside the sealing dam 105 formed to surround the display area AA, the third sealing layer 430 can be in direct contact with the first sealing layer 410. In the display device according to the embodiment of the present invention, two sealing dams 105 are described as being disposed. However, in display devices according to other embodiments of the present invention, one sealing dam 105 or three or more sealing dams 105 may be disposed.

[0067] A first power supply voltage supply line VDL for applying a positive power supply voltage to the pixel driving circuit DC of each pixel area PA and a second power supply voltage supply line VSL for applying a negative power supply voltage to the second electrode 330 of each pixel area PA may be arranged on the bezel region BZ. The second power supply voltage supply line VSL may be electrically connected to the second electrode 330 outside the display area AA. For example, the second power supply voltage supply line VSL may extend along the bottom of the display area AA. The second power supply voltage supply line VSL may extend from outside the sealing dam 105. That is, in a display device according to an embodiment of the present invention, the second electrode 330 may be electrically connected to the second power supply voltage supply line VSL by penetrating only the first sealing layer 410 and the third sealing layer 430. Therefore, in a display device according to an embodiment of the present invention, the process of connecting the second electrode 330 to the second power supply voltage supply line VSL may be simplified.

[0068] The voltage line PL may be electrically connected to the first power supply voltage supply line VSL. For example, the first power supply voltage supply line VSL may electrically connect between the pad section PAD and the display area AA. The first power supply voltage supply line VSL may cross the sealing dam 105. For example, between the display area AA and the pad section PAD, the first power supply voltage supply line VSL may extend in a first direction, and the sealing dam 105 may extend in a second direction perpendicular to the first direction. The first power supply voltage supply line VSL may cross the data link wiring DLL. For example, the first power supply voltage supply line VSL may cross a plurality of first links LL1 and a plurality of second links LL2 between the display area AA and the pad section PAD.

[0069] The first power supply voltage supply line VSL may be insulated from the data link wiring DLL. For example, an upper interlayer insulating film 140 may be disposed between the second link LL2 of the data link wiring DLL and the first power supply voltage supply line VSL.

[0070] The lower interlayer insulating film 130 and the upper interlayer insulating film 140 may be located between the first link LL1 of the data link wiring DLL and the first power supply voltage supply line VDL. The first power supply voltage supply line VSL may include a main wiring VL, an external connection wiring OV, and an external dummy pattern VP.

[0071] The main wiring VL may be located on the same layer as the second source electrode 225 and the second drain electrode 227 of each pixel region PA. For example, the main wiring VL may be located between the upper interlayer insulating film 140 and the device protective film 150. The second source electrode 225 and the second drain electrode 227 of each pixel region PA may be located between the upper interlayer insulating film 140 and the device protective film 150. The main wiring VL may include the same material as the second source electrode 225 and the second drain electrode 227 of each pixel region PA. For example, the main wiring VL may be formed simultaneously with the second source electrode 225 and the second drain electrode 227 of each pixel region PA. The main wiring VL may be separated from the sealing dam 105. For example, the main wiring VL may be separated from the sealing dam 105 around the sealing dam 105. Ends of the main wiring VL may be covered by the device protective film 150.

[0072] The main wiring VL separated from the periphery of the sealing dam 105 may be electrically connected to the external connection wiring OV and the external dummy pattern VP. For example, the external dummy pattern VP may be located between the upper interlayer insulating film 140 and the sealing dam 105, and the external connection wiring OV may electrically connect the main wiring VL and the external dummy pattern 105. The external dummy pattern VP located below each sealing dam 105 may be separated from the external dummy pattern VP located below an adjacent sealing dam 105. For example, the external dummy patterns VP between the multiple sealing dams 105 may be connected by the external connection wiring OV. This reduces or minimizes the generation of residual conductive material around the sealing dam 105 in a display device according to an embodiment of the present invention. The external dummy pattern VP may include substantially the same material as the main wiring VL. For example, the external dummy pattern VP may be formed simultaneously with the main wiring VL.

[0073] The external connection wiring OV may include a different material from the main wiring VL and the external dummy pattern VP. The external connection wiring OV may be located on a different layer from the main wiring VL and the external dummy pattern VP. For example, the external connection wiring OV may include a region located above the device protective layer 150. The external connection wiring OV may be formed using the process of forming the light emitting device 300. For example, the external connection wiring OV may be formed simultaneously with the first electrodes 310 of each light emitting device 300. The external connection wiring OV may include substantially the same material as the first electrodes 310 of each light emitting device 300. Therefore, in a display device according to an embodiment of the present invention, subsequent processes for forming the external connection wiring OV may be performed at a relatively low temperature. That is, in a display device according to an embodiment of the present invention, even if a residual conductive material is left behind during the process of forming the external connection wiring OV, the residual conductive material may not evaporate during the subsequent process for forming the external connection wiring OV. Therefore, in a display device according to an embodiment of the present invention, deterioration of the light emitting device 300 due to the residual conductive material of the external connection wiring OV can be prevented or reduced.

[0074] The external connection wiring OV may be covered by the first sealing layer 410 and the third sealing layer 430. As a result, in a display device according to an embodiment of the present invention, it is possible to prevent or reduce external impact or moisture penetration through the external connection wiring OV. Therefore, in a display device according to an embodiment of the present invention, it is possible to improve the reliability and stability of the pixel driving circuit DC located in each pixel area PA.

[0075] The external connection wiring OV may be in direct contact with a portion of the upper surface of the main wiring VL facing the device substrate 100 and a portion of the upper surface of the external dummy pattern VP facing the device substrate 100. For example, a portion of the device protective film 150 located around the sealing dam 105 may be removed. For example, the sealing dam 105 may be in direct contact with the upper surface of the external dummy pattern VP facing the device substrate 100. Therefore, in the display device according to an embodiment of the present invention, the step interval due to the data link wiring DLL may be formed relatively wide. Therefore, in the display device according to an embodiment of the present invention, the residual conductive material film generated during the process of forming the external connection wiring OV may be reduced or minimized.

[0076] The external dummy pattern VP and the external connection wiring OV may have a shape extending in substantially the same direction as the sealing dam 105. For example, the external dummy pattern VP and the external connection wiring OV may be bar-shaped extending in the second direction. As shown in FIG. 4, the width W2 of the external dummy pattern VP in the first direction may be larger than the width W1 of the sealing dam 105 in the first direction. For example, the external connection wiring OV may be in direct contact with the external dummy pattern VP outside the sealing dam 105. The end of the external connection wiring OV around the sealing dam 105 may be covered with the second dam pattern 105b. This may simplify the process of connecting the external dummy pattern VP and the external connection wiring OV in a display device according to one embodiment of the present invention.

[0077] As a result, a display device according to an exemplary embodiment of the present invention may include a main wiring VL and an external connection wiring OV. The main wiring VL may be removed from the periphery of the sealing dam 105 located above the bezel region BZ, and the external connection wiring OV may be electrically connected to the main wiring VL. The external connection wiring OV may be formed simultaneously with the first electrode 310 of each pixel region PA. As a result, in a display device according to an exemplary embodiment of the present invention, the generation of a residual film of a conductive material for forming the main wiring VL around the sealing dam 105 can be prevented or reduced. Furthermore, in a display device according to an exemplary embodiment of the present invention, deterioration of the light emitting element 300 due to the residual film of the conductive material for forming the external connection wiring OV can be prevented or reduced. Therefore, in a display device according to an exemplary embodiment of the present invention, the generation of a residual film due to a step formed by the data link wiring DLL can be prevented or reduced. That is, in a display device according to an exemplary embodiment of the present invention, deterioration of the light emitting element 300 due to the residual film of the conductive material can be prevented or reduced.

[0078] In a display device according to an embodiment of the present invention, internal dummy wirings IV may be disposed between the lower planarization layer 160 and the upper planarization layer 170. The internal dummy wirings IV may include substantially the same material as the intermediate electrode 510. For example, the internal dummy wirings IV may be formed simultaneously with the intermediate electrode 510. The internal dummy wirings IV are electrically connected to the main wiring VL located between the device substrate 100 and the lower planarization layer 160. That is, in a display device according to an embodiment of the present invention, the internal dummy wirings IV between the sealing dam 105 and the display area AA may function as the first power supply voltage supply line VDL. Therefore, in a display device according to an embodiment of the present invention, a voltage drop with respect to a positive power supply voltage applied via the first power supply voltage supply line VDL may be reduced or minimized. Therefore, in a display device according to an embodiment of the present invention, brightness deviation due to a voltage drop may be prevented or reduced.

[0079] In the display device according to the embodiment of the present invention, the external connection wiring OV is described as being located outside the first dam pattern 105a. However, as shown in FIG. 6, in a display device according to another embodiment of the present invention, the external connection wiring OV may extend along the surface of the first dam pattern 105a. A portion of the external connection wiring OV located on the surface of the first dam pattern 105a may be covered by the second dam pattern 105b. Therefore, in the display device according to the other embodiment of the present invention, the stability of the positive power supply voltage applied via the first power supply voltage supply line VDL may be improved. Furthermore, in the display device according to the other embodiment of the present invention, the resistance of the first power supply voltage supply line VDL around the sealing dam 105 may be reduced or minimized. That is, in the display device according to the other embodiment of the present invention, an increase in the resistance of the first power supply voltage supply line VDL due to the main wiring VL being separated from the periphery of the sealing dam 105 may be prevented. Therefore, in the display device according to the other embodiment of the present invention, brightness deviation due to voltage drop may be effectively prevented or reduced.

[0080] In the display device according to one embodiment of the present invention, the external connection wiring OV is described as being connected to the external dummy pattern VP outside the sealing dam 105. However, in display devices according to other embodiments of the present invention, the external connection wiring OV and the external dummy pattern VP may be connected in various ways. For example, as shown in FIG. 7, in a display device according to another embodiment of the present invention, the external connection wiring OV between two first dam patterns 105a covering the ends of the external dummy pattern VP may be electrically connected to the external dummy pattern VP. The connection point between the external connection wiring OV and the external dummy pattern VP may be covered by a second dam pattern 105b. This allows for greater flexibility in the connection method between the external connection wiring OV and the external dummy pattern VP in display devices according to other embodiments of the present invention.

[0081] 7, in a display device according to another embodiment of the present invention, the sealing dam 105 may include a third dam pattern 105c located on the second dam pattern 105b. The third dam pattern 105c may include substantially the same material as the spacer formed on the bank insulating film 180. This allows for greater flexibility in the shape of the sealing dam 105 in the display device according to another embodiment of the present invention.

[0082] As shown in FIG. 7 , in a display device according to another embodiment of the present invention, the first power supply voltage supply line VDL may further include a fourth wiring (or an auxiliary dummy pattern AP). The auxiliary dummy pattern AP may be disposed on the external dummy pattern VP. An end of the auxiliary dummy pattern AP may be located on the element protective film 150 covering the end of the external dummy pattern VP. For example, the auxiliary dummy pattern AP may be disposed on substantially the same layer as the internal dummy wiring IV. The auxiliary dummy pattern AP may include the same material as the internal dummy wiring IV. For example, the auxiliary dummy pattern AP may be formed simultaneously with the internal dummy wiring IV. The external connection wiring OV is electrically connected to the external dummy pattern VP via the auxiliary dummy pattern AP. For example, the external connection wiring OV may be in direct contact with a portion of the auxiliary dummy pattern AP. This allows the external connection wiring OV and the external dummy pattern VP to be stably connected in the display device according to another embodiment of the present invention. Furthermore, in the display device according to another embodiment of the present invention, the resistance of the first power supply voltage supply line VDL around the sealing dam 105 can be reduced or minimized. Therefore, in the display device according to the other embodiment of the present invention, the voltage drop relative to the positive power supply voltage can be minimized.

[0083] 8 and 9 , in a display device according to another embodiment of the present invention, a gate driver located on a bezel region BZ of a device substrate 100 includes at least one circuit thin film transistor 290, and a first semiconductor pattern 211 of a first thin film transistor T1 and a second semiconductor pattern 221 of a second thin film transistor T2 located in each pixel region PA may be disposed on a layer different from the circuit semiconductor pattern 291 of the circuit thin film transistor 290. For example, in a display device according to another embodiment of the present invention, the circuit semiconductor pattern 291 may be disposed between a lower buffer film 110 and a lower gate insulating film 121, a circuit gate electrode 293 of the circuit thin film transistor 290 located on the lower gate insulating film 121 may be covered by a lower interlayer insulating film 131, and the first semiconductor pattern 211 of the first thin film transistor T1 and the second semiconductor pattern 221 of the second thin film transistor T2 may be disposed between an upper buffer film 141 located on the lower interlayer insulating film 130 and an upper gate insulating film 151 located on the upper buffer film 141. The circuit source electrode 295 and the circuit drain electrode 297 of the circuit thin film transistor 290 may be disposed on the same layer as the first source electrode 215 and the first drain electrode 217 of the first thin film transistor T1 located in each pixel area PA. For example, the circuit source electrode 295 and the circuit drain electrode 297 may be disposed on an upper interlayer insulating film covering the first gate electrode 213 and the second gate electrode 223 of each pixel area PA.

[0084] The first semiconductor pattern 211 and the second semiconductor pattern 221 in each pixel area PA may include a different material from the circuit semiconductor pattern 291. For example, the circuit semiconductor pattern 291 may include low temperature polysilicon (LTPS), and the first semiconductor pattern 211 and the second semiconductor pattern 221 in each pixel area PA may include an oxide semiconductor. Each pixel area PA may include a first light-shielding pattern 610 located between the device substrate 100 and the first semiconductor pattern 211, and a second light-shielding pattern 620 located between the device substrate 100 and the second semiconductor pattern 221. The first light-shielding pattern 610 is electrically connected to the first gate electrode 213. The second light-shielding pattern 620 is electrically connected to the second source electrode 225.

[0085] The first link LL1 may be located between the lower gate electrode 121 and the lower interlayer insulating film 131. The second link LL2 may be located between the lower interlayer saving film 131 and the upper buffer film 141. The main wiring VL of the first power supply voltage supply line VDL may be located between the upper gate insulating film 122 and the upper interlayer insulating film 132. The end of the main wiring VL around the sealing dam 105 and the end of the external dummy pattern VP may be covered by the upper interlayer insulating film 132. The external connection wiring OV may be located on the upper interlayer insulating film 132. Therefore, in the display device according to another embodiment of the present invention, the degree of freedom for the pixel driving circuit DC of each pixel area PA can be improved. [Explanation of symbols]

[0086] 100 Element substrate 105 Sealing Dam 105a First Dam Pattern 105b Second Dam Pattern 140 Upper interlayer insulating film 170 Upper planarization film 300 light-emitting elements 310 1st electrode LL1 Link 1 LL2 Second Link VDL First power supply voltage supply line IV Internal dummy wiring OV external connection wiring VP external dummy pattern VL main wiring

Claims

1. an element substrate including a display area including a pixel area for displaying an image and a bezel area in which no image is displayed; an upper planarization film located above the display region of the element substrate; an upper interlayer insulating film located between the element substrate and the upper planarizing film and extending over the display region and the bezel region of the element substrate; a first dam pattern located on the upper interlayer insulating layer in the bezel region and spaced apart from the upper planarization layer; a light emitting element located above the pixel region of the display area, the light emitting element including a first electrode located above the upper planarization film, a light emitting layer located above the first electrode, and a second electrode located above the light emitting layer; a pad portion located on the bezel region of the element substrate; a link wiring located between the element substrate and the upper interlayer insulating film, extending across the display area and the bezel area, and electrically connected to the pad portion; a power supply voltage supply line located on the upper interlayer insulating film and crossing the link wiring in the bezel area; Including, The power supply voltage supply line a main wiring including a first region electrically connected to the pad portion and a second region disposed between the element substrate and the upper interlayer insulating film; an external connection wiring disposed on the main wiring and electrically connected to the first region and the second region of the main wiring on the bezel region; Including, the second region of the main wiring is spaced apart from the first region of the main wiring; the first dam pattern is disposed between the first region and the second region of the main wiring; Display device.

2. the external connection wiring located on the bezel region includes a first material; The main wiring includes a second material different from the first material. The display device according to claim 1 .

3. a device protection layer disposed between the upper interlayer insulating layer and the upper planarization layer, each end of the first region and the second region of the main wiring is covered with the element protection film; The external connection wiring is located on the element protection film, and at least a portion of the element protection film is located between the external connection wiring and the upper interlayer insulating film. The display device according to claim 1 .

4. The display device of claim 1 , wherein the first dam pattern and the upper planarization layer include the same material.

5. The display device according to claim 4 , wherein the external connection wiring contains the same material as the first electrode of the light emitting element.

6. The display device according to claim 4 , wherein the external connection wiring extends along a surface of the first dam pattern.

7. a second dam pattern located on the first dam pattern, 7. The display device of claim 6, wherein a portion of the external connection wiring located on the surface of the first dam pattern is covered by the second dam pattern, and a portion of the external connection wiring is located between the first dam pattern and the second dam pattern.

8. the power supply line further includes an external dummy pattern located between the upper interlayer insulating film and the first dam pattern, The display device according to claim 1 , wherein the external connection wiring is electrically connected to the external dummy pattern.

9. the main wiring and the external dummy pattern each include a lower surface and an upper surface positioned farther from the element substrate than the lower surface; The display device according to claim 8 , wherein the external connection wiring directly contacts a part of the upper surface of the main wiring and a part of the upper surface of the external dummy pattern.

10. The display device of claim 8 , wherein the external dummy pattern includes the same material as the main wiring.

11. the power supply voltage supply line extends in a first direction; the first dam pattern and the external dummy pattern extend in a second direction perpendicular to the first direction; The display device according to claim 8 , wherein a width of the external dummy pattern in the first direction is larger than a width of the first dam pattern in the first direction.

12. further comprising an auxiliary dummy pattern located between the external dummy pattern and the first dam pattern, The display device according to claim 8 , wherein the auxiliary dummy pattern includes a material different from that of the external dummy pattern and the external connection wiring.

13. a lower planarization layer positioned between the upper interlayer insulating layer and the upper planarization layer and spaced apart from the first dam pattern; an internal dummy wiring located between the lower planarization film and the upper planarization film; further comprising The second region of the main wiring is electrically connected to the internal dummy wiring between the element substrate and the lower planarizing film. The display device according to claim 1 .

14. a pixel driving circuit located between the pixel region of the element substrate and the lower planarization film; an intermediate electrode located between the lower planarization film and the upper planarization film in the pixel region, the intermediate electrode being electrically connected to the pixel driving circuit and the light emitting element; further comprising The display device according to claim 13 , wherein the intermediate electrode contains the same material as the internal dummy wiring.

15. a lower interlayer insulating film disposed between the device substrate and the upper interlayer insulating film; the link wiring includes a first link located between the element substrate and the lower interlayer insulating film, and a second link located between the lower interlayer insulating film and the upper interlayer insulating film; The display device according to claim 1 , wherein the second links are located between the first links.

16. a display area for displaying an image; a bezel area surrounding the display area; a pad portion located within the bezel area; at least one sealing dam located within the bezel area and extending along an edge of the display area; a power supply voltage supply line electrically connected to the display area and the pad section; Including, The power supply voltage supply line a main wiring including a first region and a second region spaced apart from the first region; an external connection wiring electrically connected to the first region and the second region of the main wiring within the bezel region; Including, the external connection wiring and the at least one sealing dam are disposed on an element protection film that covers each end of the first region and the second region of the main wiring; the at least one sealing dam is disposed between the first region and the second region of the main wiring; Display device.

17. a substrate including a display area and a bezel area; a light-emitting element located on the display region of the substrate, emitting light to display an image in the display region, the light-emitting element including a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode; a pad portion located within the bezel area of ​​the substrate; a dam located within a bezel region of the substrate; a power supply voltage supply line extending from the display area to the pad section and supplying a power supply voltage from the pad section to the display area; Including, The power supply voltage supply line a first wiring including a first region and a second region spaced apart from the first region; a second wiring electrically connected to the first region and the second region of the first wiring; Including, the second wiring is disposed on an element protection film that covers at least one of the first wirings, the dam is disposed between the first region and the second region of the first wiring on the element protection film; Display device.

18. The display device according to claim 17 , wherein the second wiring includes a region that overlaps with the first region of the first wiring and a region that does not overlap with the first wiring.

19. The display device according to claim 18 , wherein the second wiring includes an area that does not overlap the dam.

20. a plurality of link wirings extending across the display area and the bezel area and electrically connected to the pad portion; an insulating film located between the plurality of link wirings and the power supply voltage supply line; further comprising the power supply voltage supply line crosses the plurality of link wirings in the bezel area; The display device according to claim 17.

21. The display device according to claim 20 , wherein the insulating film and the dam contain the same material.

22. The display device of claim 17 , wherein the second wiring includes a first material, and the first wiring includes a second material different from the first material.

23. The display device of claim 17 , further comprising a third wiring electrically connected to the second wiring.

24. The display device according to claim 23 , wherein the third wiring overlaps the dam.

25. further including a fourth wiring electrically connected to the third wiring, The display device according to claim 23 , wherein the fourth wiring is located between the dam and the third wiring.

26. the dam includes a first dam pattern located on the fourth wiring, and a second dam pattern located on a partial region of the second wiring overlapping the first dam pattern, the third wiring, and the fourth wiring; The display device of claim 25 , wherein the second dam pattern includes an area extending over the first dam pattern.

27. 18. The display device of claim 17, wherein the dam includes a first dam pattern and a second dam pattern, a portion of the second wiring overlaps the first dam pattern, and a portion of the second wiring is located between the first dam pattern and the second dam pattern.

Images