gaming machines

Abstract

To provide a game machine allowing for suitably mounting electronic components on a board.SOLUTION: A game machine includes a first decorative board 56. A connector, and plural compact chip components smaller than the connector are mounted on the first decorative board 56. The plural compact chip components are mounted in a side of a first mounting surface 84 as one plate surface of the first decorative board 56, and are not mounted in a second mounting surface side as a plate surface in a side opposite to the first mounting surface 84 in the first decorative board 56.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Pachinko machines, slot machines, and the like are known as types of gaming machines. These gaming machines are known to be configured so that a lottery is held when predetermined lottery conditions are met, and a bonus is awarded to the player depending on the result of the lottery. Furthermore, they are generally configured to provide effects that allow the player to predict or recognize the result of the lottery. These gaming machines are equipped with a circuit board on which electronic components for progressing the game and for executing effects are mounted.

[0003] Specifically, for example, a pachinko machine has a known configuration in which a lottery is held based on a game ball entering a ball entry section provided in the game area, a picture is displayed changing on the display surface of the display device, and if the lottery results in a winning result, a specific picture combination or the like is displayed in a final stop on the display surface, and the machine transitions to a special game state that is advantageous to the player. When the machine transitions to the special game state, for example, a ball entry device or the like provided in the game area starts opening and closing, and game balls are paid out based on the ball entering the ball entry device (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-170465 Summary of the Invention [Problem to be solved by the invention]

[0005] In gaming machines such as those exemplified above, electronic components must be suitably mounted on the circuit board, and there is still room for improvement in this regard.

[0006] The present invention has been made in consideration of the circumstances exemplified above, and aims to provide an amusement machine in which electronic components can be suitably mounted on a board. [Means for solving the problem]

[0007] In order to solve the above problem, the invention of claim 1 is a device in which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted. and is not used as a game board. In a gaming machine equipped with a predetermined board, the first predetermined electronic component is mounted on a first predetermined surface side, which is one surface of the predetermined substrate; the second predetermined electronic component is mounted on a second predetermined surface of the predetermined substrate opposite to the first predetermined surface, the second predetermined electronic component is not mounted in an area on the second predetermined plate surface behind an area on the first predetermined plate surface where the first predetermined electronic component is mounted, a specific electronic component larger than the second predetermined electronic component is mounted on the second predetermined surface side of the predetermined board, the specific electronic component is mounted on the second predetermined board surface in an area behind an area on the first predetermined board surface where the first predetermined electronic component is mounted, The second predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode, The predetermined substrate is a first predetermined connection portion to which the first predetermined electrode is electrically connected; a first predetermined wiring pattern drawn out from the first predetermined connection portion; a second predetermined connection portion to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn out from the second predetermined connection portion; It is equipped with The direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part. The invention described in claim 2 is a circuit board in which a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component are mounted. and is not used as a game board. In a gaming machine equipped with a predetermined board, the first predetermined electronic component is mounted on a first predetermined surface side, which is one surface of the predetermined substrate; the second predetermined electronic component is mounted on a second predetermined surface of the predetermined substrate opposite to the first predetermined surface, the second predetermined electronic component is not mounted in an area on the second predetermined plate surface behind an area on the first predetermined plate surface where the first predetermined electronic component is mounted, the predetermined substrate is provided with a predetermined substrate fixing portion for fixing the predetermined substrate, the second predetermined electronic component is not mounted in an area that is less than a predetermined distance from the predetermined board fixing portion, the first predetermined electronic component is mounted in an area less than the predetermined distance, The second predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode, The predetermined substrate is a first predetermined connection portion to which the first predetermined electrode is electrically connected; a first predetermined wiring pattern drawn out from the first predetermined connection portion; a second predetermined connection portion to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn out from the second predetermined connection portion; It is equipped with The direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part. [Effects of the Invention]

[0008] According to the present invention, it is possible to suitably mount electronic components on a substrate. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a front view of a pachinko machine according to a first embodiment. [Figure 2] FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. [Figure 3] FIG. 1 is an exploded perspective view showing the main components of a pachinko machine. [Figure 4] FIG. 2 is a front view showing the configuration of the game board. [Figure 5] FIG. 10 is an explanatory diagram for explaining the configuration for discharging game balls that have flowed down the game area. [Figure 6] FIG. 2 is a front view of the main control device. [Figure 7] This is a front view of the pachinko machine with the decorative cover and decorative substrate removed. [Figure 8] (a) A plan view showing the first mounting surface, which is the plate surface on one side of the first decorative substrate; (b) A plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of ​​a bypass capacitor mounted on the first decorative substrate; and (c) A plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of ​​a small chip resistor mounted on the first decorative substrate. [Figure 9] FIG. 8(b) is a cross-sectional view taken along line AA in FIG. 8(a). [Figure 10](a) A plan view showing the first mounting surface, which is the plate surface on one side of the second decorative substrate; (b) A plan view of the first mounting surface of the second decorative substrate showing an enlarged view of the peripheral area of ​​a bypass capacitor mounted on the second decorative substrate; and (c) A plan view of the first mounting surface of the second decorative substrate showing an enlarged view of the peripheral area of ​​a small chip resistor mounted on the second decorative substrate. [Figure 11] This is a wiring diagram of the first light-emitting circuit section in the first decorative substrate. [Figure 12] (a) is an oblique view of the first mounting surface side of the first decorative substrate showing an enlarged view of the bypass capacitor and its surroundings, and (b) is an oblique view of the first mounting surface side of the first decorative substrate showing an enlarged view of the small chip resistor and its surroundings. [Figure 13] (a) A plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of ​​the bypass capacitor; (b) An explanatory diagram for explaining the relationship between the pads in the peripheral area and the solder resist; (c) An explanatory diagram for explaining the possible movement patterns of the bypass capacitor; and (d) An explanatory diagram for explaining the possible movement patterns of the bypass capacitor in the comparative example. [Figure 14] (a) A plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the peripheral area of ​​the small chip resistor; (b) An explanatory diagram for explaining the relationship between the pads in the peripheral area and the solder resist; (c) An explanatory diagram for explaining the possible movement patterns of the small chip resistor; and (d) An explanatory diagram for explaining the possible movement patterns of the small chip resistor in the comparative example. [Figure 15] (a) is a plan view showing the second mounting surface of the first decorative substrate, and (b) is a plan view showing an enlarged view of the second mounting surface of the first decorative substrate showing the back side area of ​​the first light-emitting circuit section. [Figure 16] FIG. 1(a) is a cross-sectional view of a first decorative substrate, and FIG. 1(b) is a cross-sectional view of a first decorative substrate in a comparative example. [Figure 17] FIG. 2(a) is a plan view showing a first surface of the aggregate substrate, (b) is an explanatory diagram for explaining the valley division of the aggregate substrate, and (c) is an explanatory diagram for explaining the mountain division of the aggregate substrate. [Figure 18]FIG. 2A is a perspective view of a dividing jig used to divide the aggregate substrate, FIG. 2B is a front view of the dividing jig, and FIG. 2C is an explanatory view for explaining how the aggregate substrate is divided using the dividing jig. [Figure 19] FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. [Figure 20] This is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 21] 10 is a flowchart showing a main process executed by a main CPU. [Figure 22] 10 is a flowchart showing a timer interrupt process executed by the main CPU. [Figure 23] 10 is a flowchart showing a special chart special power control process executed by the main CPU. [Figure 24] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 25] (a) A plan view showing the first mounting surface of the first decorative substrate in the second embodiment, and (b) a plan view of the first mounting surface of the first decorative substrate showing an enlarged view of the surrounding area of ​​the bypass capacitor mounted on the first decorative substrate. [Figure 26] FIG. 10 is a plan view of a first light-emitting surface of a light-emitting substrate in a third embodiment. [Figure 27] FIG. 4 is a plan view of a second light-emitting surface of the light-emitting substrate. [Figure 28] 10(a) is a plan view of a first light-emitting surface of a light-emitting substrate in a fourth embodiment, and FIG. 10(b) is a plan view of the first light-emitting surface of the light-emitting substrate showing an enlarged view of the peripheral area of ​​a bypass capacitor. [Figure 29] 1(a) is a plan view of a second light-emitting surface of the light-emitting substrate, and FIG. 1(b) is a plan view of the second light-emitting surface of the light-emitting substrate showing an enlarged view of the area around the power supply terminal and the GND terminal. DETAILED DESCRIPTION OF THE INVENTION

[0010] First Embodiment A first embodiment of a pachinko machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a front view of the pachinko machine 10, and Figs. 2 and 3 are perspective views showing the main components of the pachinko machine 10 in an expanded form. For convenience, Fig. 2 omits the components within the gaming area of ​​the pachinko machine 10, and Fig. 3 omits the components of the main control device 60 (described later) on the rear side of the pachinko machine 10.

[0011] As shown in Figure 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so that it can rotate forward. The outer frame 11 is made up of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and the outer frame 11 may be attached to island equipment in the amusement hall.

[0012] 2 and 3, the gaming machine body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 can be rotated forward with the left side as the base end of rotation and the right side as the tip end of rotation when viewed from the front.

[0013] A front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side being the base end and the right side being the tip end when viewed from the front. A back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated rearward with the left side being the base end and the right side being the tip end when viewed from the front.

[0014] The gaming machine main body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine main body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states can be released by using an unlocking key to unlock the cylinder lock 17, which is exposed on the front of the pachinko machine 10.

[0015] <Front side configuration> Next, the configuration of the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 in the resin base 21.

[0017] <Game board configuration> Here, the configuration of the game board 24 will be described with reference to Fig. 4. Fig. 4 is a front view of the game board 24.

[0018] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies game balls stored in an upper tray 54a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] A plurality of large and small openings are formed in the game board 24, penetrating in the front-to-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a general symbol unit 38. There are four general winning openings 31 in total, and one of each of the others.

[0021] Even if a ball enters the through gate 35, no game balls will be paid out. On the other hand, if balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls will be paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball will be paid out; when one game ball enters the general winning opening 31, ten prize balls will be paid out; and when one game ball enters the special electric winning device 32, fifteen prize balls will be paid out.

[0022] The number of prize balls is arbitrary, and for example, the second actuation port 34 may be configured to have fewer prize balls than the first actuation port 33, or the second actuation port 34 may be configured to have more prize balls than the first actuation port 33.

[0023] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes etc. are discharged from the game area PA through the outlet 24a. Also, on the game board 24, a large number of nails 24b are planted to appropriately distribute and adjust the falling direction of the game balls, and various components such as windmills are also arranged.

[0024] Here, "entering" means that a gaming ball passes through a predetermined opening, and includes not only the case where the gaming ball passes through the opening and is discharged from the gaming area PA, but also the case where the gaming ball continues to flow down the gaming area PA without being discharged from the gaming area PA after passing through the opening. However, in the following explanation, in order to clearly distinguish from the gaming ball entering the outlet 24a, the gaming ball entering the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the through gate 35 will also be referred to as "winning."

[0025] The first actuation port 33 and the second actuation port 34 are united as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 open upward. Furthermore, the first actuation port 33 is at the top, and both actuation ports 33, 34 are aligned vertically. The second actuation port 34 is provided with a normal power device 34a serving as a guide piece made up of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

[0026] A through gate 35 is provided upstream of the second operating port 34 in the direction in which the gaming ball flows down. The through gate 35 has a through hole (not shown) that penetrates vertically, and a gaming ball that enters the through gate 35 flows down through the gaming area PA after winning. This allows a gaming ball that enters the through gate 35 to enter the second operating port 34.

[0027] Based on a win at the through gate 35, the normal power device 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the win at the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the game area PA, an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role release, the stop result corresponding to that result is displayed, and the variable display on the normal map display section 38a is terminated, the game transitions to the normal power open state. In the normal power open state, the normal power device 34a is opened in a predetermined manner.

[0028] The map display unit 38a is configured with a segment display in which a plurality of LED display segments are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device, etc. The image displayed variably on the map display unit 38a may be configured to variably display multiple types of letters, multiple types of symbols, multiple types of characters, or multiple types of colors that are switched between.

[0029] In the normal map unit 38, a normal map reserve display unit 38b is provided adjacent to the normal map display unit 38a. Up to four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display unit 38b.

[0030] A winning lottery is triggered by the entry into the first operating port 33 or the second operating port 34. The result of the lottery is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Specifically, the special symbol unit 37 includes a special symbol display unit 37a. The display area of ​​the special symbol display unit 37a is smaller than the display surface 41a of the symbol display unit 41. A winning lottery is triggered by a win through the first actuation port 33 or the second actuation port 34, and the special symbol display unit 37a displays a variable or predetermined symbol. The result corresponding to the lottery result is then displayed. The special symbol display unit 37a is configured as a segment display in which multiple LED display segments are arranged in a predetermined manner. However, this is not limited to this, and the special symbol display unit 37a may be configured as a liquid crystal display, an organic electroluminescence display, a cathode ray tube (CRT), a dot matrix display, or another type of display device. The symbols displayed on the special symbol display unit 37a may include a configuration in which multiple characters, symbols, characters, or colors are displayed.

[0032] In the special symbol unit 37, a special symbol reserve display unit 37b is provided adjacent to the special symbol display unit 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special symbol reserve display unit 37b.

[0033] More specifically, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

[0034] In the symbol display device 41, when a variable or predetermined display of symbols is performed in the special symbol display unit 37a based on a winning entry in the first actuation port 33 or a winning entry in the second actuation port 34, a variable or predetermined display of symbols is performed accordingly. For example, the display surface 41a of the symbol display device 41 has three symbol rows, an upper row, a middle row, and a lower row, as multiple display areas, and in each symbol row, main symbols numbered "1" through "9" are scrolled and displayed in ascending or descending order. In this scrolling display, scrolling of all symbol rows is first started, then switched from scrolling display to standby display in the order of the upper symbol row → the lower symbol row → the middle symbol row, and finally ended with a predetermined symbol being statically displayed in each symbol row. Then, in a game where the game result is a jackpot, a predetermined combination of symbols is displayed stationary on a predetermined pay line on the display surface 41a of the symbol display device 41. Specifically, if the most favorable jackpot result described below is obtained, the same odd numbered symbol combination will be displayed in a stopped state, if the low probability jackpot result described below is obtained, the same even numbered symbol combination will be displayed in a stopped state, and if the low prize high probability jackpot result described below is obtained, a symbol combination that is not the same symbol combination but would not be displayed in a stopped state if the low prize high probability jackpot result is not obtained will be displayed in a stopped state.

[0035] In addition, the symbol display device 41 not only displays effects triggered by winning a prize in the first actuation port 33 or the second actuation port 34, but also displays effects during the opening / closing execution mode to which it transitions after a winning jackpot. Furthermore, based on a prize in either actuation port 33, 34, display begins on the special symbol display unit 37a and the symbol display device 41, and one game session is played until a predetermined result is displayed and the game ends. Furthermore, the manner in which the symbols are displayed in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol rows, the direction of the symbol display in the symbol rows, the number of symbols in each symbol row, etc. can be changed as appropriate. Furthermore, the symbols displayed in the symbol display device 41 are not limited to the above-mentioned patterns; for example, a configuration in which only numbers are displayed as symbols may be used.

[0036] If a jackpot is won in a lottery based on a win through the first operating port 33 or the second operating port 34, the system transitions to an open / close execution mode in which a prize can be won in the special electric winning device 32. The special electric winning device 32 includes a large prize opening (not shown) that leads to the back side of the game board 24, and an open / close door 32a that opens and closes the large prize opening. The open / close door 32a is positioned in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open / close execution mode. The open / close execution mode is a mode that is transitioned to when a win is achieved. Note that while a prize can be won in the closed state, it may be configured to be less likely to win than in the open state.

[0037] <Configuration for discharging game balls> FIG. 5 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0038] As already explained, a gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the gaming area PA. In other words, a gaming ball that is launched from the gaming ball launching mechanism 27 and flows into the gaming area PA is discharged from the gaming area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the gaming board 24.

[0039] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, where they are collected by a discharge ball collection section (not shown). The game balls collected by the discharge ball collection section are then discharged to a ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage sections 42-48 is provided with various detection sensors 42a-48a for detecting gaming balls. These discharge passage sections 42-48 and detection sensors 42a-48a will be described below. As already explained, four general winning openings 31 are provided, and therefore, there are discharge passage sections 42-44 corresponding to each of the four general winning openings. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage section 42 corresponding to the leftmost general winning opening 31 and the second discharge passage section 43 corresponding to the general winning opening 31 adjacent to it on the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located midway along the first discharge passage section 42, and the second winning opening detection sensor 43a is provided so that its detection range is located midway along the second discharge passage section 43. A gaming ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a as it passes through the first discharge passage 42, and a gaming ball that enters the general winning opening 31 adjacent to it on the right is detected by the second winning opening detection sensor 43a as it passes through the second discharge passage 43. A third discharge passage 44 is provided for the two general winning openings 31 on the right, and is formed so that the two general winning openings 31 merge midway. The third discharge passage 44 has entrance-side regions corresponding to the two general winning openings 31, and these entrance-side regions merge midway to form a single exit-side region. A third winning opening detection sensor 44a is provided so that a detection range is located midway in the exit-side region of the third discharge passage 44. A gaming ball that enters either of the two general winning openings 31 on the right is detected by the third winning opening detection sensor 44a as it passes through the third discharge passage 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a position midway through the fourth discharge passage section 45, and a gaming ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a as it passes through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a position midway through the fifth discharge passage section 46, and a gaming ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a as it passes through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second operating port detection sensor 47a is provided so that its detection range exists at a midpoint of the sixth discharge passage section 47, and a gaming ball that enters the second operating port 34 is detected by the second operating port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that its detection range exists at a midpoint of the seventh discharge passage section 48, and a gaming ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

[0042] A gaming ball that is detected by one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the gaming area PA is detected by the gate detection sensor 49a.

[0043] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect gaming balls individually. The various detection sensors 42a-49a are electrically connected to a main control device 60 (described later), and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when not detecting a gaming ball, and output a HI level signal when detecting a gaming ball. However, this is not a limitation, and the relationship between HI and LOW may be reversed.

[0044] As shown in Fig. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 having the above-described configuration to the resin base 21. As shown in Fig. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of ​​the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of colorless and transparent glass, but is not limited to this and may be formed of colorless and transparent synthetic resin, or may be formed of colored and transparent as long as the game area PA is visible through the window panel 52 from the front of the pachinko machine 10.

[0045] Above the window 51, a pair of left and right speaker sections 53 are provided, which output sound effects according to the game status. Also, below the window 51, an upper bulge section 54 and a lower bulge section 55, which bulge toward the front, are arranged side by side. An upper tray 54a, which opens upward, is provided inside the upper bulge section 54, and a lower tray 55a, which also opens upward, is provided inside the lower bulge section 55. The upper tray 54a has the function of temporarily storing game balls dispensed from a dispensing device (described later) and guiding them in a row toward the game ball launching mechanism 27. The lower tray 55a also has the function of storing surplus game balls in the upper tray 54a.

[0046] As shown in FIG. 1, a first decorative substrate 56 is provided on the lower left side of the window portion 51 on the front surface of the front door frame 14, and a second decorative substrate 57 is provided approximately in the center of the upper left-right direction of the window portion 51. Each of the decorative substrates 56, 57 is equipped with a plurality of LED chips, and these decorative substrates 56, 57 produce light-emitting effects corresponding to the game status. The front door frame 14 is provided with a first decorative cover 58 that covers the front of the first decorative substrate 56 and a second decorative cover 59 that covers the front of the second decorative substrate 57. These decorative covers 58, 59 are made of a transparent or translucent resin that transmits light emitted from the LED chips, and bulge toward the front of the pachinko machine 10. Details of the decorative substrates 56, 57 and the decorative covers 58, 59 will be described later.

[0047] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0048] As shown in Fig. 2, a main control device 60 that mainly controls the game is mounted on the back of the inner frame 13 (specifically, the game board 24). Fig. 6 is a front view of the main control device 60.

[0049] <Configuration of main control device 60> As shown in FIG. 6, the main control device 60 is configured by housing a main control board 61 in a board box 60a. An MPU 62 is mounted on one of the board surfaces, which is the element mounting surface, of the main control board 61. The board box 60a is formed transparently so that the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be seen from outside the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 so that an opposing wall portion 60b of the board box 60a that faces the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a and the MPU 62 through the opposing wall portion 60b.

[0050] The board box 60a is formed by combining multiple case bodies 60c one behind the other. These multiple case bodies 60c are provided with connecting portions 60e that prevent the case bodies 60c from being separated and leave traces of the separation. The connecting portions 60e are arranged side by side along one side of the roughly rectangular board box 60a. This allows for the case bodies 60c to be prevented from being separated by destroying some of the connecting portions 60e, and then the case bodies 60c can be separated by reconnecting other connecting portions 60e. Furthermore, because the connecting portions 60e are destroyed when the case bodies 60c are separated, it is possible to visually check the connecting portions 60e to determine whether the case bodies 60c have been separated fraudulently. Furthermore, a sealing sticker 60f is attached to the side of the board box 60a opposite to the side on which the connecting portions 60e are arranged, so as to straddle the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the sealing sticker 60f is peeled off when the case bodies 60c are separated.

[0051] In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the gaming hall manager is inserted and turned ON to trigger an opportunity to change the setting state of the pachinko machine 10 within the range of "Setting 1" to "Setting 6," an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned ON, a reset button 68c which is operated to clear data in a main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c which notify the results of game history management. The setting state of the pachinko machine 10 is not limited to six levels from "Setting 1" to "Setting 6," and may be any number of levels.

[0052] The setting key insertion portion 68a, the update button 68b, the reset button 68c, and the first to third notification display devices 69a to 69c are all provided on the device mounting surface of the main control board 61. As already explained, the device mounting surface of the main control board 61 faces the opposing wall portion 60b of the board box 60a, but the setting key insertion portion 68a, the update button 68b, and the reset button 68c are not covered by the opposing wall portion 60b. In other words, the opposing wall portion 60b has separate openings in the areas facing the setting key insertion portion 68a, the update button 68b, and the reset button 68c. This allows the setting key to be inserted into the setting key insertion portion 68a, and the update button 68b and the reset button 68c to be pressed without the need to open the board box 60a.

[0053] By inserting a setting key into the setting key insertion portion 68a and rotating it in a predetermined direction, the setting key insertion portion 68a is turned on. In this state, by starting the supply of operating power to the pachinko machine 10 (i.e., by starting the supply of operating power to the MPU 62 of the main control device 60), the pachinko machine 10 enters a changeable state in which the setting state can be changed. In this state, each time the update button 68b is pressed once, the setting state of the pachinko machine 10 changes by one step in ascending order within the range of "Setting 1" to "Setting 6." Note that if the update button 68b is operated when the setting key is in the "Setting 6" state, the setting state is updated to "Setting 1." Furthermore, by rotating the setting key inserted into the setting key insertion portion 68a from the ON position in the direction opposite to the predetermined direction and returning it to its initial position, the setting key insertion portion 68a enters an OFF state. When the setting key insertion portion 68a enters an OFF state, the changeable state ends, and the game becomes playable with the setting values ​​at that time. In other words, after the changeable state has ended, the set value cannot be changed even if the update button 68b is operated.

[0054] The ON operation of the setting key insertion section 68a is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the setting value cannot be changed.

[0055] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the larger the value of "setting n" (n is an integer between "1" and "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in detail later, there are two winning / losing lottery modes that determine the probability of winning a jackpot result: a low probability mode in which the probability of winning is relatively low, and a high probability mode in which the probability of winning is relatively high, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

[0056] As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear the data, it is necessary to start the supply of operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The ON operation of the reset button 68c is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the data in the main RAM 65 cannot be cleared.

[0057] Each of the first to third alarm display devices 69a to 69c is a segment display with an array of seven LED display segments, but is not limited to this and may be a single light-emitting element of a multicolor type, a liquid crystal display device, or an organic electroluminescence (EL) display. Each of the first to third alarm display devices 69a to 69c is installed so that its display surface faces the direction in which the element mounting surface of the main control board 61 faces, and is covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed to be transparent, the display surfaces of the first to third alarm display devices 69a to 69c housed within the board box 60a can be seen from outside the board box 60a. Furthermore, as already explained, the main control device 60 is mounted on the back surface of the resin base 21 in the board box 60a so that the opposing wall portion 60b that faces the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to third alarm display devices 69a to 69c through the opposing wall portion 60b.

[0058] The display surface of the first notification display device 69a displays not only the numbers "0" through "9" but also various characters, including alphabetic characters. Meanwhile, the second notification display device 69b and the third notification display device 69c display the numbers "0" through "9." The results of game history management are reported using the first through third notification display devices 69a through 69c. In addition, when the setting state of the pachinko machine 10 is in a changeable state, in which it is possible to change the setting state, a value corresponding to the current setting value is displayed on the third notification display device 69c. The value corresponding to the setting value may be displayed on the first notification display device 69a or the second notification display device 69b. Alternatively, the setting value before the changeable state may be displayed on one of the first through third notification display devices 69a through 69c, and the current setting value may be displayed on another of the first through third notification display devices 69a through 69c.

[0059] An audio and light emitting control device 81 is provided above the main control device 60 on the back surface of the inner frame 13. The audio and light emitting control device 81 controls the sound output, light emission, and display control device 82 in accordance with instructions from the main control device 60. The audio and light emitting control device 81 also controls the light emission of the LED chips mounted on the first decorative substrate 56 and the second decorative substrate 57.

[0060] As shown in Figure 3, a rear pack unit 15 is installed to cover the rear side of the inner frame 13, including the main control device 60 and the audio / light emitting control device 81. The rear pack unit 15 includes a rear pack 72 formed from a transparent synthetic resin, and a dispensing mechanism section 73 and a control device assembly unit 74 are attached to the rear pack 72.

[0061] The payout mechanism 73 includes a tank 75 to which gaming balls supplied from the island equipment of the gaming hall are successively replenished, and a payout device 76 for paying out the gaming balls stored in the tank 75. The gaming balls paid out from the payout device 76 are discharged into the upper tray 54a or the lower tray 55a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

[0062] The control device aggregate unit 74 is equipped with a payout control device 77 having the function of controlling the payout device 76, and a power supply / launch control device 78 which generates and outputs the predetermined power required by the various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply / launch control device 78 are stacked one behind the other so that the payout control device 77 is at the rear of the pachinko machine 10.

[0063] FIG. 7 is a front view of the pachinko machine 10 with the decorative covers 58 and 59 and the decorative base plates 56 and 57 removed. As shown in FIG. 1, the first decorative cover 58 has cylindrical cover fixing bosses 58a-58c integrally formed at the upper, lower left, and lower right portions of the back surface of the first decorative cover 58, which extend rearward from the pachinko machine 10. The second decorative cover 59 also has cylindrical cover fixing bosses 59a and 59b integrally formed at the left and right portions of the back surface of the second decorative cover 59, which extend rearward from the pachinko machine 10. Screw holes (not shown) are formed at the ends of the raised ends of the cover fixing bosses 58a-58c, 59a, and 59b. As shown in FIG. 7, the front door frame 14 has through holes 14a-14e formed in correspondence with the cover fixing bosses 58a-58c, 59a, and 59b, penetrating the front door frame 14 from front to rear. As shown in FIG. 1, the first decorative cover 58 and the second decorative cover 59 are fixed to the front door frame 14 by screwing the cover fixing bosses 58a to 58c, 59a, 59b from the rear side of the front door frame 14.

[0064] <Configuration of decorative substrates 56 and 57> Next, the configuration of the decorative substrates 56 and 57 will be described.

[0065] Figure 8(a) is a plan view showing the first mounting surface 84, which is the plate surface on one side of the first decorative substrate 56, Figure 8(b) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged view of the peripheral area 86 of a bypass capacitor 85 mounted on the first decorative substrate 56, Figure 8(c) is a plan view of the first mounting surface 84 of the first decorative substrate 56 showing an enlarged view of the peripheral area 88 of a small chip resistor 87 mounted on the first decorative substrate 56, and Figure 9 is a cross-sectional view along line AA of Figure 8(a). In addition, Figure 10(a) is a plan view showing the first mounting surface 89, which is the plate surface on one side of the second decorative substrate 57, Figure 10(b) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged view of the peripheral area 98 of the bypass capacitor 97 mounted on the second decorative substrate 57, and Figure 10(c) is a plan view of the first mounting surface 89 of the second decorative substrate 57 showing an enlarged view of the peripheral area 102 of the small chip resistor 101 mounted on the second decorative substrate 57.

[0066] Decorative substrates 56 and 57 are four-layer substrates with alternating conductive and insulating layers. The insulating layers are made of a composite material such as a glass cloth substrate impregnated with thermosetting epoxy resin. The conductive layers are formed by etching copper foil plates placed above or below the insulating layers.

[0067] 9, the first decorative substrate 56 includes, as conductive layers, a first wiring layer 91 arranged on the first mounting surface 84 side of the first decorative substrate 56, and a second wiring layer 92 arranged on the second mounting surface 95 side, which is the other plate surface of the first decorative substrate 56. The first decorative substrate 56 also includes, as conductive layers arranged between the first wiring layer 91 and the second wiring layer 92, a GND plane layer 93 (ground plane layer or ground plane layer) and a power supply plane layer 94. Lands and wiring patterns are formed on the first wiring layer 91 and the second wiring layer 92 by etching a copper foil plate.

[0068] Although not shown, the second decorative board 57, like the first decorative board 56, has as conductive layers a first wiring layer arranged on the first mounting surface 89 side and a second wiring layer arranged on the second mounting surface side, which is the other plate surface of the second decorative board 57. Also, like the first decorative board 56, the second decorative board 57 has as conductive layers arranged between the first and second wiring layers a GND plane layer (ground plane layer or ground plane layer) and a power plane layer. Lands and wiring patterns are formed on the first and second wiring layers by etching copper foil plates.

[0069] 1, a stepped recess 56a is formed in the upper right part of the first decorative substrate 56, corresponding to the lower left part of the curved window portion 51. In addition, a notch 56b is formed in the lower left part of the first decorative substrate 56 to avoid the cover fixing boss 58b of the first decorative cover 58. By providing the notch 56b in the first decorative substrate 56, it is possible to install the first decorative substrate 56 in a wide area behind the first decorative cover 58 while avoiding the cover fixing boss 58b.

[0070] The first decorative substrate 56 is an irregularly shaped substrate having a stepped recess 56a and a notch 56b. The first decorative substrate 56 is not a rectangular or approximately rectangular substrate. As shown in Figure 8(a), the dimension of the first decorative substrate 56 in a first direction DR1 (the vertical direction in Figure 8(a)) is larger than the dimension of the first decorative substrate 56 in a second direction DR2 (the horizontal direction in Figure 8(a)) perpendicular to the first direction DR1.

[0071] As shown in Figure 10(a), the second decorative substrate 57 is shaped like a horizontally elongated, approximately ellipse. The second decorative substrate 57 is not a rectangular or approximately rectangular substrate. The dimension of the second decorative substrate 57 in the long axis direction LD (left-right direction in Figure 10(a)) is larger than the dimension of the second decorative substrate 57 in the short axis direction SD (up-down direction in Figure 10(a)).

[0072] As shown in Fig. 8(a), a protrusion 56c is provided at approximately the center in the vertical direction of the stepped recess 56a. Fixing through-holes 56d to 56g are formed on the upper left side of the first decorative board 56, the protrusion 56c, and the lower left and right sides thereof, penetrating the first decorative board 56 in the thickness direction to allow the first decorative board 56 to be fixed to the front surface of the front door frame 14 with screws. Also, as shown in Fig. 10(a), fixing through-holes 57a and 57b are formed on the left and right sides of the second decorative board 57, penetrating the second decorative board 57 in the thickness direction to allow the second decorative board 57 to be fixed to the front door frame 14 with screws.

[0073] As shown in FIG. 7, cylindrical board fixing bosses 103-108 are integrally formed on the front surface of the front door frame 14, to which decorative boards 56, 57 (FIGS. 8(a) and 10(a)) can be fixed. The board fixing bosses 103-108 stand upright from the front surface of the front door frame 14 towards the front of the pachinko machine 10, and screw holes 103a-108a are formed at the ends of the board fixing bosses 103-108 to allow the decorative boards 56, 57 to be screwed in. The decorative boards 56, 57 are screwed into the board fixing bosses 103-108 from the front of the pachinko machine 10, and are fixed to the front surface of the front door frame 14, as shown in FIG. 1, with the first mounting surfaces 84, 89 (FIGS. 8(a) and 10(a)) facing the front of the pachinko machine 10.

[0074] As already explained, the light emission control of the LED chips mounted on the decorative substrates 56, 57 and the sound output control of the speaker unit 53 are performed by the audio light emission control device 81 (Fig. 3). As shown in Fig. 8(a), the first decorative substrate 56 has a first connector 111 and a second connector 112 mounted on a second mounting surface 95 (Fig. 9), which is the plate surface opposite to the first mounting surface 84. Also, as shown in Fig. 10(a), the second decorative substrate 57 has a third connector 113, a fourth connector 114, and a fifth connector 115 mounted on a second mounting surface, which is the plate surface opposite to the first mounting surface 89.

[0075] A harness (not shown) that electrically connects the audio and light-emitting control device 81 (FIG. 3) and the first decorative substrate 56 is attached to the first connector 111. A harness (not shown) that electrically connects the first decorative substrate 56 and the second decorative substrate 57 is attached to the second connector 112 and the third connector 113. Furthermore, a harness (not shown) that electrically connects the second decorative substrate 57 and the pair of left and right speaker units 53 is attached to the fourth connector 114 and the fifth connector 115. The audio and light-emitting control device 81 outputs information to the first decorative substrate 56 for controlling the light emission of the LED chips mounted on the first decorative substrate 56. Furthermore, the audio and light-emitting control device 81 outputs information to the second decorative substrate 57 via the first decorative substrate 56 for controlling the light emission of the LED chips mounted on the second decorative substrate 57 and for controlling the sound output of the speaker unit 53.

[0076] As shown in FIG. 7, the front door frame 14 is formed with first to fifth connector insertion holes 14f to 14j that penetrate the front door frame 14 from front to back, corresponding to the first to fifth connectors 111 to 115 (FIGS. 8(a) and 10(a)). The decorative boards 56, 57 (FIGS. 8(a) and 10(a)) are fixed to the front door frame 14 with the connectors 111 to 115 inserted into the corresponding connector insertion holes 14f to 14j and exposed on the back side of the front door frame 14. Harnesses (not shown) are attached to and detached from the first to fifth connectors 111 to 115 from the back side of the front door frame 14.

[0077] As shown in Fig. 8(a), the first decorative substrate 56 is provided with a first light-emitting circuit section 121, a second light-emitting circuit section 122, and a third light-emitting circuit section 123. As shown in Fig. 10(a), the second decorative substrate 57 is provided with a fourth light-emitting circuit section 124. These light-emitting circuit sections 121 to 124 include circuits for controlling the light emission of a plurality of LED chips.

[0078] The specific configuration of the light-emitting circuit sections 121 to 124 will be described using the configuration of the first light-emitting circuit section 121 as an example.

[0079] Fig. 11 is a wiring diagram of the first light-emitting circuit unit 121 on the first decorative substrate 56. As shown in Fig. 11, the first light-emitting circuit unit 121 includes an LED driver 126, a bypass capacitor 85, 16 LED chips 127 to 142, and eight small chip resistors 87, 143 to 149. Although not shown, the second to fourth light-emitting circuit units 122 to 124 also include an LED driver, a bypass capacitor, multiple LED chips, and multiple small chip resistors. The number of LED chips included in each of the light-emitting circuit units 121 to 124 is arbitrary, and the number of small chip resistors included in each of the light-emitting circuit units 121 to 124 is determined depending on the connection between the LED driver and the LED chips.

[0080] 11, the LED driver 126 includes a power supply terminal 151, a clock terminal 152, a data terminal 153, a GND terminal 154 (ground terminal), and first to eighth output terminals 155 to 162. A wiring pattern 164 for inputting a clock signal received from the audio and light emission control device 81 is electrically connected to the clock terminal 152, and a wiring pattern 165 for inputting lighting control data received from the audio and light emission control device 81 is electrically connected to the data terminal 153. A second wiring pattern 172b for electrically connecting the LED driver 126 to the GND plane layer 93 (FIG. 9) is connected to the GND terminal 154, and a fourth wiring pattern 172d for supplying drive power to the LED driver 126 is electrically connected to the power supply terminal 151.

[0081] In this specification, a "terminal" refers to a linear metal portion (for example, the power supply terminal 151 and the GND terminal 154 (FIG. 8(b)) in the LED driver 126) provided on an electronic component (including small chip components described later) for electrical connection with a corresponding pad (or pad). In addition, an "electrode" in this specification, in a narrow sense, refers to a metal portion (for example, the first electrode 85a and the second electrode 85b (FIG. 8(b)) described later in the bypass capacitor 85) provided on an electronic component (including small chip components described later) for electrical surface connection with a corresponding pad (or pad), and does not include the above-mentioned "terminal." In contrast, in a broad sense, an "electrode" in this specification refers to a metal portion (for example, the first electrode 85a and the second electrode 85b (FIG. 8(b)) described later) provided on an electronic component (including small chip components described later) for electrical surface connection with a corresponding pad (or pad), and includes the above-mentioned "terminal."

[0082] The LED driver 126 controls the light emission of the LED chips 127-142 connected to the first to eighth output terminals 155-162 based on lighting control data received from the audio light emission control device 81. Two of the 16 LED chips 127-142 and one of the eight small chip resistors 87, 143-149 are electrically connected to each of the output terminals 155-162 of the LED driver 126. The small chip resistors 87, 143-149 are provided to limit the current flowing through the LED chips 127-142. The provision of the small chip resistors 87, 143-149 allows the LED chips 127-142 to be driven at an allowable current or less.

[0083] Fig. 12(a) is a perspective view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the bypass capacitor 85 and its periphery, and Fig. 12(b) is a perspective view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the small chip resistor 87 and its periphery. As shown in Fig. 12(a), the bypass capacitor 85 is a surface-mount chip capacitor, and more specifically, a multilayer ceramic capacitor in which a large number of dielectrics and electrodes are stacked. The bypass capacitor 85 is roughly a rectangular parallelepiped, and is provided with a pair of metal first and second electrodes 85a and 85b at both ends in the longitudinal direction.

[0084] The bypass capacitor 85 is a small chip component whose longitudinal dimension along a plane perpendicular to the thickness direction of the bypass capacitor 85 (hereinafter also referred to as the "longitudinal direction of the bypass capacitor 85") is 0.1 mm or more and 0.9 mm or less. In this specification, a small chip component is an electronic component whose longitudinal dimension (hereinafter also referred to as the "longitudinal direction of the small chip component") is 0.1 mm or more and 0.9 mm or less. By having the longitudinal dimension of the small chip component be 0.9 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be reduced. This allows a large area to be secured on the first decorative substrate 56 for mounting electronic components other than the small chip component. Furthermore, electronic components mounted between the first decorative substrate 56 and a substrate with a high density of electronic components can be standardized to small chip components. By having the longitudinal dimension of the small chip component be 0.1 mm or more, the mechanical strength of the connection points between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself can be prevented from being excessively reduced. Here, the connection points of the small chip component include the pads electrically connected to the electrodes of the small chip component, the solder fillets electrically connecting the electrodes and pads, and the wiring patterns extending from the pads. By having the longitudinal dimension of the small chip component be 0.1 mm or more, it is possible to prevent it from becoming difficult to visually check for missing small chip components. The longitudinal dimension of the small chip component is preferably 0.3 mm or more and 0.8 mm or less. By having the longitudinal dimension of the small chip component be 0.8 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be reduced. By having the longitudinal dimension of the small chip component be 0.3 mm or more, the mechanical strength of the connection points between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself can be increased. Furthermore, the process of checking for missing small chip components can be simplified.The longitudinal dimension of the small chip components is more preferably 0.4 mm or more and 0.7 mm or less.By having the longitudinal dimension of the small chip component be 0.7 mm or less, the area occupied by the small chip component on the first decorative substrate 56 can be further reduced. By having the longitudinal dimension of the small chip component be 0.4 mm or more, the mechanical strength of the connection point between the small chip component and the first decorative substrate 56 and the mechanical strength of the small chip component itself can be increased, reducing the possibility of damage to the connection point and the possibility of damage to the small chip component itself. Furthermore, by having the longitudinal dimension of the small chip component be 0.4 mm or more, the accuracy of visually checking for missing small chip components can be improved.

[0085] The bypass capacitor 85 is a small chip component having a longitudinal dimension of approximately 0.6 mm along a plane perpendicular to the thickness direction and a transverse dimension (hereinafter also referred to as the "transverse direction") along a plane perpendicular to the thickness direction and a thickness dimension of approximately 0.3 mm. Having a longitudinal dimension of the bypass capacitor 85 of 0.7 mm or less reduces the area occupied by the bypass capacitor 85 on the first decorative substrate 56. Having a longitudinal dimension of the bypass capacitor 85 of 0.4 mm or more increases the mechanical strength of the connection between the bypass capacitor 85 and the first decorative substrate 56 and of the bypass capacitor 85 itself, reducing the possibility of damage to the connection and the bypass capacitor 85 itself. Furthermore, having a longitudinal dimension of the bypass capacitor 85 of 0.4 mm or more increases the accuracy of visually checking for missing bypass capacitors 85. In addition, the bypass capacitor 85 may be configured so that its longitudinal dimension is smaller than 0.6 mm (for example, 0.4 mm), its lateral dimension is smaller than 0.3 mm (for example, 0.2 mm), or its thickness dimension is smaller than 0.3 mm (for example, 0.2 mm).

[0086] The first decorative substrate 56 is provided, on the first mounting surface 84 side, with a first pad 171a (or first pad) corresponding to the first electrode 85a of the bypass capacitor 85 and a second pad 171b (or second pad) corresponding to the second electrode 85b. The first pad 171a and the second pad 171b form a pair. Two wiring patterns 172a and 172b extend from the first pad 171a, and two wiring patterns 172c and 172d extend from the second pad 171b. These pads 171a and 171b and the wiring patterns 172a to 172d are integrally formed by etching a single copper foil plate.

[0087] The bypass capacitor 85 is mounted on the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 85a and 85b to the corresponding pads 171a and 171b. A solder fillet 173a is formed on the first pad 171a, electrically connecting the first electrode 85a to the first pad 171a, and a solder fillet 173b is formed on the second pad 171b, electrically connecting the second electrode 85b to the second pad 171b. The solder fillets 173a and 173b are formed by heating solder paste applied to the pads 171a and 171b to melt the solder and then cooling and solidifying it. In the longitudinal direction of the bypass capacitor 85, the first electrode 85a is fixed approximately at the center of the first pad 171a, and the second electrode 85b is fixed approximately at the center of the second pad 171b.

[0088] 8(b), a first wiring pattern 172a drawn from a first pad 171a connected to a first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93 (FIG. 9) through a via hole 174 provided in the first decorative substrate 56, and a second wiring pattern 172b drawn from the first pad 171a is electrically connected to a GND terminal 154 of the LED driver 126. Furthermore, a third wiring pattern 172c drawn from a second pad 171b electrically connected to a second electrode 85b of the bypass capacitor 85 is electrically connected to the power supply plane layer 94 (FIG. 9) through a via hole 175 provided in the first decorative substrate 56, and a fourth wiring pattern 172d drawn from the second pad 171b is electrically connected to a power supply terminal 151 of the LED driver 126. In this way, the first pad 171a is arranged between the GND terminal 154 of the LED driver 126 and the GND plane layer 93, and the second pad 171b is arranged between the power terminal 151 of the LED driver 126 and the power plane layer 94.

[0089] Bypass capacitor 85 is capable of storing electric charge, and reduces the peaks of noise components contained in the drive power supply of LED driver 126 by charging, and reduces the valleys of the noise components by discharging. In this way, bypass capacitor 85 absorbs the noise components contained in the drive power supply of LED driver 126.

[0090] By disposing the bypass capacitor 85 between the power supply terminal 151 of the LED driver 126 and the power supply plane layer 94, it is possible to reduce the impact of noise components contained in the driving power supplied from the audio and light-emitting control device 81 to the LED driver 126 on the LED driver 126. As shown in FIG. 8(b), the bypass capacitor 85 is disposed close to the power supply terminal 151 of the LED driver 126 so that no other electronic components, such as ICs, are present between the bypass capacitor 85 and the power supply terminal 151 of the LED driver 126. This increases the likelihood that noise components contained in the driving power supplied to the power supply terminal 151 of the LED driver 126 will be absorbed by the bypass capacitor 85 and reduces the likelihood that the LED driver 126 will malfunction due to the influence of the noise components. Because no other ICs are present between the bypass capacitor 85 and the power supply terminal 151, it is possible to absorb noise components generated by the LED driver 126 and prevent the noise components from causing malfunction of other ICs. Furthermore, since there are no other electronic components between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 are absorbed by the bypass capacitor 85, preventing the noise components from causing other electronic components to malfunction.

[0091] As shown in FIG. 12(b), the small chip resistor 87, like the bypass capacitor 85 (FIG. 12(a)), is a substantially rectangular parallelepiped and has a pair of metallic first and second electrodes 87a and 87b at both ends in the longitudinal direction. Like the bypass capacitor 85, the small chip resistor 87 is a small chip component whose longitudinal dimension along a plane perpendicular to the thickness direction of the small chip resistor 87 (hereinafter also referred to as the "longitudinal direction of the small chip resistor 87") is 0.1 mm or more and 0.9 mm or less. The small chip resistor 87 is a small chip component whose longitudinal dimension along a plane perpendicular to the thickness direction is approximately 0.6 mm, and whose lateral dimensions along the plane perpendicular to the thickness direction (hereinafter also referred to as the "lateral direction") and thickness direction dimensions are approximately 0.3 mm. By having the longitudinal dimension of the small chip resistor 87 be 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. By having the longitudinal dimension of the small chip resistor 87 be 0.4 mm or more, the mechanical strength of the connection point between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, reducing the possibility of damage to the connection point and the possibility of damage to the small chip resistor 87 itself. Furthermore, by having the longitudinal dimension of the small chip resistor 87 be 0.4 mm or more, the accuracy of visually checking whether or not there is a missing mounting of the small chip resistor 87 can be improved. Note that the longitudinal dimension of the small chip resistor 87 may be smaller than 0.6 mm (e.g., 0.4 mm), the lateral dimension of the small chip resistor 87 may be smaller than 0.3 mm (e.g., 0.2 mm), or the thickness dimension may be smaller than 0.3 mm (e.g., 0.2 mm).

[0092] The first decorative substrate 56 is provided, on the first mounting surface 84 side, with a first pad 176a (or first pad) corresponding to the first electrode 87a of the small chip resistor 87, and a second pad 176b (or second pad) corresponding to the second electrode 87b. The first pad 176a and the second pad 176b form a pair. One wiring pattern 181a extends from the first pad 176a, and one wiring pattern 181b extends from the second pad 176b. These pads 176a, 176b and wiring patterns 181a, 181b are integrally formed by etching a single copper foil plate.

[0093] The small chip resistor 87 is mounted on the first mounting surface 84 of the first decorative substrate 56 by soldering the electrodes 87a and 87b to the corresponding pads 176a and 176b. A solder fillet 177a is formed on the first pad 176a, electrically connecting the first electrode 87a to the first pad 176a, and a solder fillet 177b is formed on the second pad 176b, electrically connecting the second electrode 87b to the second pad 176b. The solder fillets 177a and 177b are formed by heating solder paste applied to the pads 176a and 176b to melt solder, which is then cooled and solidified. In the longitudinal direction of the small chip resistor 87, the first electrode 87a is fixed approximately at the center of the first pad 176a, and the second electrode 87b is fixed approximately at the center of the second pad 176b.

[0094] As shown in Fig. 8(c), the LED chip 142 is a surface-mounted chip component. The LED chip 142 is a roughly rectangular parallelepiped, and is provided with a pair of metal first and second electrodes 142a and 142b at both ends in the longitudinal direction. The first decorative substrate 56 is provided with a first copper pad 178a (or first pad) corresponding to the first electrode 142a, and a second copper pad 178b (or second pad) corresponding to the second electrode 142b. The first pad 178a and the second pad 178b form a pair.

[0095] The first wiring pattern 181a drawn from the first pad 176a of the small chip resistor 87 is electrically connected to the second pad 178b of the LED chip 142. In addition, the second wiring pattern 181b drawn from the second pad 176b of the small chip resistor 87 is electrically connected to the eighth output terminal 162 of the LED driver 126.

[0096] As described above, the decorative substrates 56, 57 are mounted with electronic components such as the connectors 111-115, the LED driver 126, the LED chips 127-142, the bypass capacitors 85, 97, and the small chip resistors 87, 101, 143-149. The external dimensions of the small chip components (the bypass capacitors 85, 97 and the small chip resistors 87, 101, 143-149) are smaller than those of the other electronic components, and the contact area between the electrodes and pads of the small chip components is smaller than the contact area between the electrodes and pads of the other electronic components. Therefore, the connection points between the small chip components and the decorative substrates 56, 57, among the various electronic components mounted on the decorative substrates 56, 57, have lower mechanical strength than the connection points between the other electronic components and the decorative substrates 56, 57. In this specification, the connection points between the small chip components and the decorative substrates 56, 57 include pads electrically connected to the electrodes of the small chip components, solder fillets electrically connecting the electrodes of the small chip components to the pads, and wiring patterns drawn from the pads. Specifically, the connection points between the bypass capacitor 85 and the first decorative substrate 56 include pads 171a, 171b electrically connected to the electrodes 85a, 85b of the bypass capacitor 85, solder fillets 173a, 173b electrically connecting the electrodes 85a, 85b of the bypass capacitor 85 to the pads 171a, 171b, and wiring patterns 172a-172d drawn from the pads 171a, 171b. In addition, the connection points between the small chip resistor 87 and the first decorative substrate 56 include pads 176a, 176b electrically connected to the electrodes 87a, 87b of the small chip resistor 87, solder fillets 177a, 177b electrically connecting the electrodes 87a, 87b of the small chip resistor 87 to the pads 176a, 176b, and wiring patterns 181a, 181b drawn out from the pads 176a, 176b.

[0097] The use of small chip components (bypass capacitors 85, 97 and small chip resistors 87, 101, 143-149) that are smaller than electronic components such as the LED driver 126 and LED chips 127-142 reduces the area occupied by the capacitors and resistors on the decorative substrates 56, 57. However, this can cause problems, such as increased susceptibility to damage to the connections between the small chip components and the decorative substrates 56, 57 when the decorative substrates 56, 57 are distorted, and increased susceptibility to damage to the small chip components themselves. In this specification, damage to the connections between the small chip components and the decorative substrates 56, 57 includes cracks in the solder fillets that electrically connect the electrodes of the small chip components to the pads (or pads), damage that causes the solder fillets to peel, damage that causes the pads to peel off from the decorative substrates 56, 57, and damage that causes the wiring patterns around the pads to peel off from the decorative substrates 56, 57. In this specification, damage to the small chip component itself includes damage that causes cracks in the small chip component and damage that destroys the internal structure of the small chip component (for example, the laminated structure of the bypass capacitors 85, 97).

[0098] Examples of situations in which distortion may occur in the decorative substrates 56, 57 with small chip components mounted thereon include when the decorative substrates 56, 57 are screwed to the front door frame 14, when a harness (not shown) is attached or detached to or from the connectors 111-115 mounted on the second mounting surface 95 of the decorative substrates 56, 57, and when electronic components such as the LED driver 126 and LED chips 127-142 mounted on the first decorative substrate 56 generate heat during use, causing thermal stress to act on the decorative substrates 56, 57. Furthermore, in a manufacturing method in which electronic components, including small chip components, are mounted on an aggregate substrate including multiple decorative substrates 56, 57 and then the aggregate substrate is divided to extract multiple decorative substrates 56, 57, distortion may also occur in the decorative substrates 56, 57 with small chip components mounted thereon when the aggregate substrate is divided. In these cases, bending stress may act on the decorative substrates 56, 57, as well as torsional stress.

[0099] FIG. 13(a) is a plan view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the peripheral region 182 (FIG. 8(b)) of the bypass capacitor 85, and FIG. 13(b) is an explanatory diagram for explaining the relationship between the pads 171a, 171b in the peripheral region 182 and the solder resist 222. FIG. 13(c) is an explanatory diagram for explaining a possible movement mode of the bypass capacitor 85 in this embodiment, and FIG. 13(d) is an explanatory diagram for explaining a possible movement mode of the bypass capacitor 85 in a comparative example. Note that in FIG. 13(b), the solder resist 222 is shown hatched.

[0100] As shown in FIG. 13(a), the first pad 171a and the second pad 171b corresponding to the first electrode 85a and the second electrode 85b of the bypass capacitor 85 are shaped in a substantially rectangular shape. As shown in FIG. 13(b), the first pad 171a and the second pad 171b have the same shape and size. The vertical dimension LA1 of the pads 171a and 171b is approximately 0.35 mm, which is larger than the lateral dimension (approximately 0.3 mm) of the bypass capacitor 85. Since the pair of pads 171a and 171b have the same shape and size, the amount of solder paste applied to the pair of pads 171a and 171b can be approximately the same. Note that the vertical dimension LA1 of the pads 171a and 171b may be the same as the lateral dimension of the bypass capacitor 85, or the vertical dimension LA1 of the pads 171a and 171b may be smaller than the lateral dimension of the bypass capacitor 85.

[0101] The horizontal dimension LA2 of the pads 171a and 171b is approximately 0.32 mm. The first pad 171a and the second pad 171b are spaced apart by a predetermined distance LA3 (specifically, approximately 0.28 mm) in the longitudinal direction (first direction DR1) of the bypass capacitor 85 (FIG. 13(a)). The distance (predetermined distance LA3) between the outer edge of the first pad 171a on the second pad 171b side and the outer edge of the second pad 171b on the first pad 171a side is set in the range of approximately 1 / 3 (0.2 mm) to approximately 1 / 2 (approximately 0.3 mm) of the longitudinal dimension of the bypass capacitor 85 (approximately 0.6 mm). This allows the bypass capacitor 85 to be mounted on the first decorative substrate 56 in such a manner that, in the longitudinal direction of the bypass capacitor 85, the first electrode 85a of the bypass capacitor 85 is positioned approximately in the center of the first pad 171a and the second electrode 85b is positioned approximately in the center of the second pad 171b.

[0102] The solder resist 222 is not applied between the first pad 171a and the second pad 171b. If the solder resist 222 were applied to a narrow region between the first pad 171a and the second pad 171b, there would be a higher probability of defective products in which part or all of the pads 171a, 171b would be covered with the solder resist 222 if there was a misalignment in the applied region of the solder resist 222. In contrast, the configuration in which the solder resist 222 is not applied between the first pad 171a and the second pad 171b prevents part or all of the pads 171a, 171b from being covered with the solder resist 222, and allows the solder paste to adhere to the entire areas of the pads 171a, 171b. This ensures the connection area between the first pad 171a and the first electrode 85a, thereby ensuring the mechanical strength of the connection point between the first pad 171a and the first electrode 85a, and also ensures the connection area between the second pad 171b and the second electrode 85b, thereby ensuring the mechanical strength of the connection point between the second pad 171b and the second electrode 85b.

[0103] As shown in Figure 13(a), the pair of pads 171a, 171b are spaced apart in a first direction DR1, which is the longitudinal direction of the bypass capacitor 85. Therefore, when the first decorative substrate 56 is transported to a reflow furnace in the reflow process, the first decorative substrate 56 is transported in a second direction DR2 perpendicular to the first direction DR1, so that heating of the solder paste applied to the pair of pads 171a, 171b can be started at approximately the same time.

[0104] The solder paste applied to the pads 171a and 171b is heated in a reflow furnace to become liquid molten solder. The molten solder floats and attracts the electrodes 85a and 85b of the bypass capacitor 85. The solder paste contains a flux component, and the molten solder flows over the pads 171a and 171b. Gas is also released from the molten solder. If the solder paste melts on one pad 171a of the pair of pads 171a and 171b before the solder paste on the other pad 171b, only one electrode 85a of the pair of electrodes 85a and 85b of the bypass capacitor 85 will be in contact with the molten solder, and the surface tension of the molten solder will disrupt the balance of forces acting on the electrodes 85a and 85b of the bypass capacitor 85. This makes it easier for the bypass capacitor 85 to rotate around an axis normal to the first decorative substrate 56, and also makes it easier for the bypass capacitor 85 to stand up substantially vertically on one of the pads 171a with one electrode 85a, a phenomenon known as "chip standing." If there is a difference in the timing at which the solder paste melts between the pair of pads 171a, 171b, the bypass capacitor 85 is more likely to rotate and chip standing will occur. In contrast, by transporting the first decorative substrate 56 in the second direction DR2 in the reflow process and starting to heat the solder paste applied to the pair of pads 171a, 171b substantially simultaneously, it is possible to align the timing at which the solder paste melts between the pair of pads 171a, 171b, and prevent the bypass capacitor 85 from rotating and chip standing.

[0105] As shown in FIG. 8(b), the bypass capacitor 85 is mounted on the first decorative substrate 56 with the longitudinal direction of the bypass capacitor 85 parallel to the first direction DR1. As shown in FIG. 8(c), the small chip resistor 87 is mounted on the first decorative substrate 56 with the longitudinal direction of the small chip resistor 87 parallel to the first direction DR1. Although not shown, the small chip resistors 143-149 are also mounted on the first decorative substrate 56 with the longitudinal directions of the small chip resistors 143-149 parallel to the first direction DR1. In this way, the small chip components (the bypass capacitor 85 and the small chip resistors 87, 143-149) are mounted on the first decorative substrate 56 with the longitudinal directions of the small chip components parallel to the first direction DR1.

[0106] 8(b) and 8(c), the spacing direction between the pads 171a, 171b corresponding to the electrodes 85a, 85b of the bypass capacitor 85 and the spacing direction between the pads 176a, 176b corresponding to the electrodes 87a, 87b of the small chip resistor 87 are the first direction DR1. The spacing direction between the pads 171a, 171b, 176a, 176b is the same for multiple small chip components. Therefore, by transporting the first decorative substrate 56 in a direction perpendicular to or substantially perpendicular to the common spacing direction (first direction DR1) during the reflow process, the timing at which heating of the solder paste applied to the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 begins can be synchronized, and the timing at which heating of the solder paste applied to the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 can be synchronized. This makes it possible to prevent the plurality of small chip components from rotating and the chips from standing up.

[0107] In the pads 171a, 171b corresponding to the electrodes 85a, 85b of the bypass capacitor 85, the temperature rise in the areas where the wiring patterns 172a-172d are drawn (the drawing positions of the wiring patterns 172a-172d) is more likely to be delayed compared to areas where the wiring patterns 172a-172d are not drawn because heat is more likely to escape to the wiring patterns 172a-172d. Furthermore, the temperature rise in the initial heating stage of the reflow process is more delayed for the first wiring pattern 172a and the third wiring pattern 172c, which are connected to the GND plane layer 93 or the power supply plane layer 94, which have a larger area than the pads 171a, 171b, compared to the second wiring pattern 172b and the fourth wiring pattern 172d, which are not connected to the GND plane layer 93 or the power supply plane layer 94. For this reason, the temperature rise in the first pad 171a where the first wiring pattern 172a connected to the GND plane layer 93 is drawn out tends to be slower than the temperature rise in the second wiring pattern 172b in the initial heating stage. Furthermore, the temperature rise in the second pad 171b where the third wiring pattern 172c connected to the power plane layer 94 is drawn out tends to be slower than the temperature rise in the fourth wiring pattern 172d in the initial heating stage. During the reflow process, the temperature distribution in the pads 171a and 171b in the initial heating stage varies depending on the number, drawing positions, and connection destinations of the wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b. Furthermore, the drawing direction of the wiring patterns 172a to 172d drawn out from the pair of pads 171a and 171b may also affect the temperature distribution in the pads 171a and 171b in the initial heating stage. Details will be described later, but in this embodiment, in the first decorative substrate 56, the number, drawing positions, connection destinations and drawing directions of wiring patterns 172a to 172d drawn out from the pair of pads 171a, 171b are set so that there is no difference in temperature distribution within the pads 171a, 171b between the pair of pads 171a, 171b during the initial heating stage.

[0108] 13(d), in the bypass capacitor 183 of the comparative example, a first wiring pattern 185a is drawn rightward from the right end of a first pad 184a (or the first pad), and a second wiring pattern 185b is drawn leftward from the left end of the first pad 184a. The first wiring pattern 185a of the comparative example is a wiring pattern electrically connected to the GND plane layer 93 (FIG. 9) through the via hole 174, similar to the first wiring pattern 172a of the embodiment already described. The second wiring pattern 185b of the comparative example is a wiring pattern electrically connected to the GND terminal 154 of the LED driver 126, similar to the second wiring pattern 172b of the embodiment already described. Furthermore, a third wiring pattern 185c is drawn downward from the lower end of the second pad 184b (or the second pad), and a fourth wiring pattern 185d is drawn leftward from the left end of the second pad 184b. The third wiring pattern 185c in the comparative example is a wiring pattern electrically connected to the power supply plane layer 94 (FIG. 9) through the via hole 175, similar to the third wiring pattern 172c of the present embodiment already described. The fourth wiring pattern 172d in the comparative example is a wiring pattern electrically connected to the power supply terminal 151 of the LED driver 126, similar to the fourth wiring pattern 172d of the present embodiment already described. In the first pad 184a, the temperature rise tends to be slower at the locations where the first wiring pattern 185a and the second wiring pattern 185b are drawn out (the right and left ends of the first pad 184a). In particular, the temperature rise tends to be slower at the location where the first wiring pattern 185a connected to the GND plane layer 93 is drawn out (the left end of the first pad 184a). Furthermore, in the second pad 184b, the temperature rise is likely to be slower in the initial stage of heating at the locations where the third wiring pattern 185c and the fourth wiring pattern 185d are drawn out (the lower end and left end of the second pad 184b). In particular, the temperature rise is likely to be slower at the location where the third wiring pattern 185c connected to the power supply plane layer 94 is drawn out (the lower end of the second pad 184b). For this reason, the temperature of the upper right part of the second pad 184b is likely to rise in the initial stage of heating in the reflow process.If the solder paste melts only on the upper right portion of the second pad 184b, as shown in FIG. 13(d), the bypass capacitor 183 may rotate with the upper right portion of the second pad 184b as the center of rotation and the normal direction of the first decorative substrate 56 as the axis of rotation, resulting in the bypass capacitor 183 being mounted on the first decorative substrate 56 in an inclined state. In this case, the connection area between the first pad 184a and the first electrode 183a by the solder fillet 186 is reduced, which may result in a poor connection. Furthermore, the rotation of the bypass capacitor 183 may result in the bypass capacitor 183 being mounted without electrical contact between the first pad 184a and the first electrode 183a. Furthermore, this may result in a chip-standing phenomenon, in which the bypass capacitor 183 stands up on the first pad 184a with only one electrode 183a. In this way, in the comparative example in which the wiring patterns 185a to 185d drawn from the first pad 184a and the second pad 184b are drawn out from different positions, mounting defects of the bypass capacitor 183 are likely to occur.

[0109] 13(a), in the first decorative substrate 56 of this embodiment, the first wiring pattern 172a is drawn rightward from the first pad 171a, and the third wiring pattern 172c is drawn rightward from the second pad 171b. Also, the second wiring pattern 172b is drawn leftward from the first pad 171a, and the fourth wiring pattern 172d is drawn leftward from the second pad 171b. In a configuration in which the same number (specifically, two) of wiring patterns 172a to 172d are drawn out from the first pad 171a and the second pad 171b, the direction (rightward) along which the side of the first pad 171a from which the first wiring pattern 172a is drawn out exists as viewed from the center of the first pad 171a is the same direction (rightward) as the direction (rightward) along which the side of the second pad 171b from which the third wiring pattern 172c is drawn out exists as viewed from the center of the second pad 171b, and the direction (leftward) along which the side of the first pad 171a from which the second wiring pattern 172b is drawn out exists as viewed from the center of the first pad 171a is the same direction (leftward) as the direction (leftward) along which the side of the second pad 171b from which the fourth wiring pattern 172d is drawn out exists as viewed from the center of the second pad 171b. This makes it possible to prevent a difference in temperature distribution between the pair of pads 171a and 171b in the initial heating stage of the reflow process, and also to prevent the bypass capacitor 85 from rotating and becoming a standing chip.

[0110] The first decorative substrate 56 is mounted with a plurality of capacitors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of small chip components, and in some of these capacitors, the direction in which the side of the first pad (or first pad) from which the first wiring pattern is drawn out exists when viewed from the center of the first pad (or first pad) electrically connected to the first electrode of the capacitor is different from the direction in which the side of the second pad (second pad) from which the third wiring pattern is drawn out exists when viewed from the center of the second pad (second pad) electrically connected to the second electrode of the capacitor. In bypass capacitor 85, which is a small chip component, the direction in which the side of first pad 171a from which first wiring pattern 172a is drawn exists is the same as the direction in which the side of second pad 171b from which third wiring pattern 172c is drawn exists as viewed from the center of second pad 171b, and the direction in which the side of first pad 171a from which second wiring pattern 172b is drawn exists is the same as the direction (leftward) in which the side of second pad 171b from which fourth wiring pattern 172d is drawn exists as viewed from the center of second pad 171b, thereby preventing rotation of bypass capacitor 85 and chip standing.

[0111] 8(b), in the first pad 171a, the lead-out position of the first wiring pattern 172a electrically connected to the GND plane layer 93 (FIG. 9) through a via hole 174 is approximately the center in the vertical direction at the right end of the first pad 171a, and in the second pad 171b, the lead-out position of the third wiring pattern 172c electrically connected to the power supply plane layer 94 (FIG. 9) through a via hole 175 is approximately the center in the vertical direction at the right end of the second pad 171b. The GND plane layer 93 has a larger area than the first pad 171a, and the power supply plane layer 94 has a larger area than the second pad 171b.

[0112] In a configuration in which the first pad 171a is electrically connected to the GND plane layer 93, which has a larger area than the first pad 171a, via the first wiring pattern 172a, and the second pad 171b is electrically connected to the power supply plane layer 94, which has a larger area than the second pad 171b, via the third wiring pattern 172c, the direction (rightward) of the side from which the first wiring pattern 172a is drawn out, of the four sides of the first pad 171a, as viewed from the center of the first pad 171a, is the same direction (rightward) as the direction (rightward) of the side from which the third wiring pattern 172c is drawn out, of the four sides of the second pad 171b, as viewed from the center of the second pad 171b. This reduces the possibility of a difference in temperature distribution occurring within the pair of pads 171a, 171b, in the initial heating stage of the reflow process.

[0113] As shown in FIG. 13A, the width of the first wiring pattern 172a extending rightward from the right end of the first pad 171a is substantially the same as the width of the third wiring pattern 172c extending rightward from the right end of the second pad 171b. This reduces the likelihood of a difference in temperature distribution within the pair of pads 171a and 171b during the initial heating stage of the reflow process, compared to a configuration in which the widths of the wiring patterns 172a and 172c are different. Furthermore, the width of the second wiring pattern 172b extending leftward from the left end of the first pad 171a is substantially the same as the width of the fourth wiring pattern 172d extending leftward from the left end of the second pad 171b. This reduces the likelihood of a difference in temperature distribution within the pair of pads 171a and 171b during the initial heating stage of the reflow process, compared to a configuration in which the widths of the wiring patterns 172b and 172d are different.

[0114] As already explained, the first wiring pattern 172a electrically connected to the GND plane layer 93 is drawn out from the right end of the first pad 171a, so the right side of the first pad 171a is more likely to experience a slower temperature rise than the left side of the first pad 171a in the initial stage of heating. Also, the third wiring pattern 172c connected to the power supply plane layer 94 is drawn out from the right end of the second pad 171b, so the right side of the second pad 171b is more likely to experience a slower temperature rise than the left side of the second pad 171b in the initial stage of heating. The number of wiring patterns 172a and 172c drawn out from the first pad 171a is the same as the number of wiring patterns 172b and 172d drawn out from the second pad 171b. Furthermore, the direction of the side of the four sides of the first pad 171a from which the first wiring pattern 172a is drawn, as viewed from the center of the first pad 171a, is the same as the direction of the side of the four sides of the second pad 171b from which the third wiring pattern 172c is drawn, as viewed from the center of the second pad 171b, and the direction of the side of the four sides of the first pad 171a from which the second wiring pattern 172b is drawn, as viewed from the center of the first pad 171a, is the same as the direction of the side of the four sides of the second pad 171b from which the fourth wiring pattern 172d is drawn, as viewed from the center of the second pad 171b. This makes it possible to balance the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b. 13(c), even if only the left portion of the solder paste melts first in the pair of pads 171a, 171b, the movement of the bypass capacitor 85 is made parallel, preventing rotation of the bypass capacitor 85. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a, and also to suppress the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b.

[0115] FIG. 14(a) is a plan view of the first mounting surface 84 of the first decorative substrate 56, showing an enlarged view of the peripheral region 187 (FIG. 8(c)) of the small chip resistor 87, and FIG. 14(b) is an explanatory diagram illustrating the relationship between the pads 176a, 176b in the peripheral region 187 and the solder resist 222. FIG. 14(c) is an explanatory diagram illustrating a possible movement mode of the small chip resistor 87 in this embodiment, and FIG. 14(d) is an explanatory diagram illustrating a possible movement mode of the small chip resistor 191 in the comparative example. Note that in FIG. 14(b), the solder resist 222 is shown hatched.

[0116] As shown in FIG. 14(a), the first pad 176a and the second pad 176b corresponding to the first electrode 87a and the second electrode 87b of the small chip resistor 87 are shaped in a substantially rectangular shape. As shown in FIG. 14(b), the first pad 176a and the second pad 176b have the same shape and size. The vertical dimension LB1 of the pads 176a and 176b is approximately 0.35 mm, which is larger than the short-side dimension (approximately 0.3 mm) of the small chip resistor 87. Because the pair of pads 176a and 176b have the same shape and size, the amount of solder paste applied to the pair of pads 176a and 176b can be made substantially the same. The vertical dimension LB1 of the pads 176a, 176b may be the same as the dimension of the small chip resistor 87 in the short direction, or may be smaller than the dimension of the small chip resistor 87 in the short direction.

[0117] The horizontal dimension LB2 of the pads 176a, 176b is approximately 0.32 mm. The first pad 176a and the second pad 176b are spaced apart by a predetermined distance LB3 (specifically, approximately 0.28 mm) in the longitudinal direction (first direction DR1) of the small chip resistor 87 (FIG. 14(a)). The distance (predetermined distance LB3) between the outer edge of the first pad 176a on the second pad 176b side and the outer edge of the second pad 176b on the first pad 176a side is set in the range of approximately 1 / 3 (0.2 mm) to approximately 1 / 2 (approximately 0.3 mm) of the dimension of the small chip resistor 87 in the longitudinal direction (approximately 0.6 mm). This allows the small chip resistor 87 to be mounted on the first decorative substrate 56 in such a manner that, in the longitudinal direction of the small chip resistor 87, the first electrode 87a of the small chip resistor 87 is positioned approximately in the center of the first pad 176a and the second electrode 87b is positioned approximately in the center of the second pad 176b.

[0118] The solder resist 222 is not applied between the first pad 176a and the second pad 176b. If the solder resist 222 were applied to the narrow region between the first pad 176a and the second pad 176b, there would be a higher probability of defective products in which part or all of the pads 176a, 176b would be covered with the solder resist 222 if there was a misalignment in the applied region of the solder resist 222. In contrast, the configuration in which the solder resist 222 is not applied between the first pad 176a and the second pad 176b prevents part or all of the pads 176a, 176b from being covered with the solder resist 222, and allows the solder paste to adhere to the entire areas of the pads 176a, 176b. This ensures the connection area between the first pad 176a and the first electrode 87a, thereby ensuring the mechanical strength of the connection point between the first pad 176a and the first electrode 87a, and also ensures the connection area between the second pad 176b and the second electrode 87b, thereby ensuring the mechanical strength of the connection point between the second pad 176b and the second electrode 87b.

[0119] As shown in FIG. 14(d), in the small chip resistor 191 of the comparative example, a first wiring pattern 193a is drawn rightward from the right end of the first pad 192a (or first pad), and a second wiring pattern 193b is drawn leftward from the left end of the second pad 192b (or second pad). The first wiring pattern 193a of the comparative example, like the first wiring pattern 181a of the present embodiment already described, is a wiring pattern electrically connected to the second electrode 142b (FIG. 8(c)) of the LED chip 142. The second wiring pattern 193b of the comparative example, like the second wiring pattern 181b of the present embodiment already described, is a wiring pattern electrically connected to the eighth output terminal 162 of the LED driver 126. The right side of the first pad 192a, from which the first wiring pattern 193a is drawn, is more likely to experience a delayed temperature rise during the initial heating stage of the reflow process compared to the left side, from which no wiring pattern is drawn. Furthermore, the temperature rise of the left side of the second pad 192b, from which the second wiring pattern 193b is drawn, tends to be slower in the initial heating stage than the right side, from which the wiring pattern is not drawn. Therefore, in the initial heating stage, only the left side of the solder paste in the first pad 192a and only the right side of the solder paste in the second pad 192b tend to melt. As shown in FIG. 14(d), the normal direction of the first decorative substrate 56 acts as the axis of rotation for the small chip resistor 191, which may result in the small chip resistor 191 being mounted on the first decorative substrate 56 in an inclined state. If the small chip resistor 191 is mounted in an inclined state, the connection area between the first pad 184a and the first electrode 183a via the solder fillet 194 will be reduced, and the connection area between the second pad 184b and the second electrode 183b via the solder fillet 195 will be reduced. Furthermore, there is a possibility that the small chip resistor 191 may be mounted in a state where the first pad 192a and the first electrode 191a are not in electrical contact due to rotation of the small chip resistor 191. Furthermore, it becomes easy for the small chip resistor 191 to stand up on the first pad 192a with one electrode 191a standing up.In this way, in the comparative example in which the lead-out positions of the wiring patterns 193a and 193b are different for the pair of pads 192a and 192b, mounting defects of the small chip resistor 191 are likely to occur.

[0120] 14(a), in the first decorative substrate 56 of this embodiment, the first wiring pattern 181a is drawn out rightward from the right end of the first pad 176a, and the second wiring pattern 181b is drawn out rightward from the right end of the second pad 176b. The drawing position of the first wiring pattern 181a is approximately the center in the vertical direction at the right end of the first pad 176a, and the drawing position of the second wiring pattern 181b is approximately the center in the vertical direction at the right end of the second pad 176b. In a configuration in which the same number of wiring patterns 181a, 181b (specifically, one) are drawn out from the first pad 176a and the second pad 176b, the direction (rightward) of the side from which the first wiring pattern 181a is drawn out, as viewed from the center of the first pad 176a, of the four sides of the first pad 176a, is the same direction as the direction (rightward) of the side from which the second wiring pattern 181b is drawn out, as viewed from the center of the second pad 176b, of the four sides of the second pad 176b. This makes it possible to prevent differences in temperature distribution within the pair of pads 176a, 176b during the initial heating stage of the reflow process, and to prevent rotation and chip standing of the miniature chip resistor 87.

[0121] The first decorative substrate 56 is mounted with a plurality of resistors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components, and in some of these resistors, the direction in which a first wiring pattern is drawn out, as viewed from the center of a first pad (or first pad) electrically connected to a first electrode of the resistor, is different from the direction in which a second wiring pattern is drawn out, as viewed from the center of a second pad (or second pad) electrically connected to a second electrode of the resistor, is. In the small chip resistor 87, which is a small chip component, the direction in which a first wiring pattern 181a is drawn out, as viewed from the center of the first pad 176a, is the same as the direction in which a second wiring pattern 181b is drawn out, as viewed from the center of the second pad 176b. This prevents rotation of the small chip resistor 87 and chip standing.

[0122] The right end of the first pad 176a is where the first wiring pattern 181a is drawn out, so the temperature rise there is more likely to be delayed than the left end of the first pad 176a in the initial stage of heating. The right end of the second pad 176b is where the second wiring pattern 181b is drawn out, so the temperature rise there is more likely to be delayed than the left end of the second pad 176b in the initial stage of heating. The number of wiring patterns 181a drawn out from the first pad 176a is the same as the number of wiring patterns 181b drawn out from the second pad 176b. The direction (rightward) of the side from which the first wiring pattern 181a is drawn out, as viewed from the center of the first pad 176a, of the four sides of the first pad 176a, is the same direction as the direction of the side from which the second wiring pattern 181b is drawn out, as viewed from the center of the second pad 176b. This makes it possible to balance the force acting on the first electrode 87a of the miniature chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the miniature chip resistor 87 due to the surface tension of the molten solder on the second pad 176b. Therefore, even if only the left portion of the solder paste on the pair of first pad 176a and second pad 176b melts first, as shown in FIG. 14(c), the movement of the miniature chip resistor 87 is made parallel, and rotation of the miniature chip resistor 87 can be prevented. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 177a between the first pad 176a and the first electrode 87a, and to suppress the degree of reduction in the connection area due to the solder fillet 177b between the second pad 176b and the second electrode 87b.

[0123] As already explained, the first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected to the second pad 178b electrically connected to the second electrode 142b of the LED chip 142 via the first wiring pattern 181a (see FIG. 8(c)). Also, as already explained, the second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected to a pad (or pad, not shown) electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)) via the second wiring pattern 181b. As shown in FIGS. 8(a) and 8(c), the second pad 178b connected to the first pad 176a is located above, and the pad (or pad, not shown) corresponding to the eighth output terminal 162 connected to the second pad 176b is located to the upper left. When viewed in a direction of one axis (second direction DR2 in FIGS. 8A and 8C) including the direction in which the second wiring pattern 181b is drawn from the second pad 176b (rightward in FIGS. 8A and 8C), the location to which the second wiring pattern 181b is connected in the pad (not shown) corresponding to the eighth output terminal 162 is located in the opposite direction from the direction in which the second wiring pattern 181b is drawn from the second pad 176b. The second wiring pattern 181b is drawn from the second pad 176b in the same direction (rightward) as the direction in which the first wiring pattern 181a is drawn from the first pad 176a, and then routed in the opposite direction from the second pad 176b when viewed in the direction of the one axis (second direction DR2).

[0124] Even in a configuration in which the second wiring pattern 181b is connected to a connection destination at a location that is opposite to the direction in which the second wiring pattern 181b is drawn from the second pad 176b, with the second pad 176b as the reference, when viewed in one axis direction (second direction DR2), the second wiring pattern 181b is drawn from the second pad 176b in the same direction as the direction in which the first wiring pattern 181a is drawn from the first pad 176a. This reduces the possibility of a difference in temperature distribution occurring within the pair of first pad 176a and second pad 176b in the initial heating stage of the reflow process.

[0125] 14(a), the width of the first wiring pattern 181a drawn rightward from the right end of the first pad 176a is substantially the same as the width of the second wiring pattern 181 drawn rightward from the right end of the second pad 176b. Therefore, compared to a configuration in which the widths of the wiring patterns 181a and 181b drawn from the pads 176a and 176b are different, the possibility of a difference in temperature distribution occurring within the pair of pads 176a and 176b in the initial heating stage of the reflow process is reduced.

[0126] As already explained with reference to Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is parallel to the first direction DR1 (the longitudinal direction of the first decorative substrate 56). Therefore, compared to when the small chip components are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is perpendicular to the first direction DR1 (the longitudinal direction of the first decorative substrate 56), the maximum value of stress that can act on the connection points between the small chip components and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 is reduced, and the maximum value of stress that can act on the small chip components themselves is reduced.

[0127] As described above, the first decorative substrate 56 is equipped with a plurality of capacitors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components. Some of these capacitors are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the capacitors is not parallel to the first direction DR1. The small chip components are protected by being mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is perpendicular to the first direction DR1.

[0128] 10(b), the bypass capacitor 97 is mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the bypass capacitor 97 is parallel to the longitudinal axis direction LD of the second decorative substrate 57. Also, as shown in FIG. 10(c), the small chip resistor 101 is mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the small chip resistor 101 is parallel to the longitudinal axis direction LD of the second decorative substrate 57. In this way, the small chip components (the bypass capacitor 97 and the small chip resistor 101) are mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the small chip components is parallel to the longitudinal axis direction LD of the second decorative substrate 57. Therefore, compared to when the small chip components are mounted on the second decorative substrate 57 in such a manner that the longitudinal direction of the small chip components is perpendicular to the longitudinal axis direction LD of the second decorative substrate 57, when distortion occurs in the second decorative substrate 57, the maximum value of stress that can act on the connection points between the small chip components and the second decorative substrate 57 is reduced, and the maximum value of stress that can act on the small chip components themselves is reduced.

[0129] 8(b), on the first decorative substrate 56, the first wiring pattern 172a drawn from the first pad 171a and the third wiring pattern 172c drawn from the second pad 171b extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (one of the short-side directions of the bypass capacitor 85). Furthermore, the second wiring pattern 172b drawn from the first pad 171a and the fourth wiring pattern 172d drawn from the second pad 171b extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (the other of the short-side directions of the bypass capacitor 85). In this way, the wiring patterns 172a to 172d drawn from the pads 171a and 171b of the bypass capacitor 85 extend in a direction perpendicular to the longitudinal direction of the bypass capacitor 85 (the short-side direction). The wiring patterns 172a to 172d drawn out from the pads 171a and 171b of the bypass capacitor 85 may extend in a direction substantially perpendicular to the longitudinal direction of the bypass capacitor 85.

[0130] As already explained, the pads 171a, 171b and the wiring patterns 172a-172d are integrally formed, and the electrodes 85a, 85b of the bypass capacitor 85 are fixed to the pads 171a, 171b by solder fillets 173a, 173b. If the wiring patterns 172a-172d drawn from the pads 171a, 171b are configured to extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when a force acting on the first decorative substrate 56 that bends the first decorative substrate 56 about a folding line extending in a direction perpendicular or substantially perpendicular to the longitudinal direction acts on the first decorative substrate 56, the connection between the bypass capacitor 85 and the first decorative substrate 56 is likely to be damaged, and the bypass capacitor 85 itself is likely to be damaged. Furthermore, with this configuration, stress acting around the bypass capacitor 85 due to distortion of the first decorative substrate 56 is likely to be transmitted to the bypass capacitor 85 itself, making the bypass capacitor 85 more likely to be damaged. In contrast, by configuring the wiring patterns 172a-172d drawn out from the pads 171a, 171b to extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 85, the maximum value of stress that can act on the connection point between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 is reduced, and the maximum value of stress that can act on the bypass capacitor 85 itself when distortion occurs in the first decorative substrate 56 is reduced. This makes it possible to prevent damage to the connection point between the bypass capacitor 85 and the first decorative substrate 56, and also to prevent damage to the bypass capacitor 85 itself.

[0131] As described above, first decorative substrate 56 is mounted with a plurality of capacitors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components, and in some of these capacitors, the wiring patterns extending from pads (or pads) electrically connected to the electrodes of the capacitors are extended in a direction different from the direction perpendicular or substantially perpendicular to the longitudinal direction of the capacitor. Bypass capacitor 85, which is a small chip component, is protected by a configuration in which wiring patterns 172a to 172d extending from pads 171a and 171b extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of bypass capacitor 85.

[0132] As already explained, the wiring patterns 181a, 181b drawn from the pads 176a, 176b of the small chip resistor 87 extend in the second direction DR2 (the short-side direction of the small chip resistor 87) perpendicular to the longitudinal direction of the small chip resistor 87. Also, as already explained, the small chip resistor 87 is electrically connected to the wiring patterns 181a, 181b by solder fillets 177a, 177b that electrically contact the electrodes 87a, 87b and the pads 176a, 176b. If the wiring patterns 181a, 181b drawn from the pads 176a, 176b were configured to extend in a direction parallel to the longitudinal direction of the small chip resistor 87, stress acting around the bypass capacitor 85 due to distortion of the first decorative substrate 56 would be more likely to be transmitted to the bypass capacitor 85 itself, making the bypass capacitor 85 more likely to be damaged. In contrast, by configuring the wiring patterns 181a, 181b drawn out from the pads 176a, 176b of the small chip resistor 87 to extend in a direction perpendicular to the longitudinal direction of the small chip resistor 87 (the short direction of the small chip resistor 87) or in a direction approximately perpendicular to the longitudinal direction of the small chip resistor 87, it is possible to reduce the maximum value of stress that can act on the small chip resistor 87. This makes it possible to prevent damage to the connection between the small chip resistor 87 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56.

[0133] As described above, the first decorative substrate 56 is mounted with a plurality of resistors (not shown) whose longitudinal dimensions along a plane perpendicular to the thickness direction are larger than those of the small chip components, and in some of these resistors, the wiring patterns extending from the pads (or pads) electrically connected to the electrodes of the resistors are extended in a direction different from the direction perpendicular or substantially perpendicular to the longitudinal direction of the resistor. The small chip resistor 87, which is a small chip component, is protected by a configuration in which the wiring patterns 181a, 181b extending from the pads 176a, 176b extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the small chip resistor 87.

[0134] As shown in Figures 8(a) to 8(c), in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (Figure 11)) are mounted only on the first mounting surface 84 side, and are not mounted on the second mounting surface 95 side. In the configuration in which the small chip components are concentrated on the first mounting surface 84 side in the first decorative substrate 56, the LED chips 127 to 142 (Figure 11) and the LED driver 126 are also mounted on the first mounting surface 84.

[0135] FIG. 15(a) is a plan view showing the second mounting surface 95 of the first decorative substrate 56, and FIG. 15(b) is a plan view of the second mounting surface 95 of the first decorative substrate 56, showing an enlarged view of the backside region 205 of the first light-emitting circuit section 121. As shown in FIG. 15(b), no small chip components are mounted in an LED backside corresponding region 201 of the second mounting surface 95. The LED backside corresponding region 201 is an area of ​​the second mounting surface 95 located on the backside of the region where the LED chips 127-142 (FIG. 9) are mounted on the first mounting surface 84 (FIG. 8(a)), and an area within 1 mm from the outer edge of the second mounting surface 95. Since no small chip components are mounted in the region of the second mounting surface 95 located on the backside of the region where the LED chips 127-142 are mounted on the first mounting surface 84, the influence of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED chips 127-142 on the small chip components is reduced. The LED backside corresponding area 201 is an area that is repeatedly heated by the heat generated when the LED chips 127-142 are driven, and is an area that is prone to distortion due to the heat of the first decorative substrate 56. If small chip components were mounted in the LED backside corresponding area 201, repeated light-emitting effects on the first decorative substrate 56 could cause thermal stress to accumulate at the connection points between the small chip components and the first decorative substrate 56, as well as thermal stress to accumulate in the small chip components themselves. In contrast, by mounting the small chip components in a manner that avoids the LED backside corresponding area 201, damage to the connection points between the small chip components and the first decorative substrate 56, which could be caused by repeated light-emitting effects on the first decorative substrate 56, and damage to the small chip components themselves can be prevented.

[0136] As shown in FIG. 15(b), no small chip components are mounted in the driver backside corresponding region 202 of the second mounting surface 95. The driver backside corresponding region 202 is the region of the second mounting surface 95 located behind the region on the first mounting surface 84 (FIG. 8(a)) where the LED driver 126 (FIG. 8(a)) is mounted and the region where the pads (or pads) corresponding to the terminals of the LED driver 126 are provided, and the region within 1 mm from the outer edge of the region of the second mounting surface 95. Since no small chip components are mounted in the region of the second mounting surface 95 located behind the region on the first mounting surface 84 where the LED driver 126 is mounted, the impact of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED driver 126 on the small chip components is reduced. The driver backside corresponding region 202 is an area that is repeatedly heated by the heat generated when the LED driver 126 is driven, and is an area where the first decorative substrate 56 is prone to distortion due to heat. If small chip components are mounted in the driver backside corresponding area 202, repeated light-emitting effects on the first decorative substrate 56 may cause thermal stress loads to accumulate at the connection points between the small chip components and the first decorative substrate 56, and may also cause thermal stress loads to accumulate in the small chip components themselves. In contrast, by mounting the small chip components in a manner that avoids the driver backside corresponding area 202, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56, which may be caused by repeated light-emitting effects on the first decorative substrate 56, and it is also possible to prevent damage to the small chip components themselves.

[0137] 8(a) to 8(c), on the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

[0138] 8(a) to 8(c), on the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

[0139] As shown in Figures 8(a) to 8(c), on the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143 to 149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a to 211d. The through-hole peripheral areas 211a to 211d are areas that are less than 5 mm away from the outer edges of the fixing through-holes 56d to 56g. When the first decorative substrate 56 is fixed to the front door frame 14 with screws, a force that causes distortion in the first decorative substrate 56 may act on the through-hole peripheral areas 211a to 211d. By positioning the small chip components at least 5 mm away from the outer edge of the fixing through holes 56d to 56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56 due to distortion of the first decorative substrate 56 that may occur near the fixing through holes 56d to 56g when the first decorative substrate 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

[0140] 8(a), the fixing through holes 56d to 56g are provided at the corners of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d to 56g are provided near the center of the first decorative substrate 56, the area of ​​the first decorative substrate 56 in which small chip components cannot be mounted is reduced.

[0141] As already explained, the fixing through-holes 56e are provided in the protruding portions 56c of the stepped recesses 56a, which allows the first decorative substrate 56 to be stably fixed to the front door frame 14 while ensuring an area in which small chip components can be mounted.

[0142] In a configuration in which small chip components are concentrated on the first mounting surface 84, as shown in FIG. 15(a), the connectors 111, 112 are concentrated on the second mounting surface 95. As shown in FIG. 8(a), the small chip components are arranged on the first mounting surface 84 so as to avoid the connector backside corresponding regions 203, 204. The connector backside corresponding regions 203, 204 are regions of the first mounting surface 84 located on the back side of the region in which the connectors 111, 112 are mounted on the second mounting surface 95 (FIG. 15(a)), and regions that are less than 5 mm away from the outer edge of the region of the first mounting surface 84. Since small chip components are not mounted in the region of the first mounting surface 84 located on the back side of the region in which the connectors 111, 112 are mounted on the second mounting surface 95, the impact of stress that may act on the first decorative substrate 56 when attaching or detaching a harness to the connectors 111, 112 on the small chip components is reduced. The connector backside corresponding areas 203, 204 are areas that are likely to be subjected to tensile stress when a harness (not shown) is attached to the connectors 111, 112, and are also areas that are likely to be subjected to compressive stress when the harness is removed from the connectors 111, 112. If small chip components are mounted in the connector backside corresponding areas 203, 204, stress may be applied to the connection points between the small chip components and the first decorative substrate 56 when the harness is attached to or detached from the connectors 111, 112, and stress may be applied to the small chip components themselves. In contrast, by arranging the small chip components to avoid the connector backside corresponding areas 203, 204, damage to the connection points between the small chip components and the first decorative substrate 56 and damage to the small chip components themselves are prevented when the harness is attached to or detached from the connectors 111, 112.

[0143] As shown in FIG. 8(a), the LED driver 126 is disposed in an area including an area less than 10 mm from the outer edge of the first decorative substrate 56, while the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are disposed 10 mm or more away from the outer edge of the first decorative substrate 56. As already explained, the connection points between the small chip components and the first decorative substrate 56, among the various electronic components mounted on the first decorative substrate 56, have lower mechanical strength than the connection points between other electronic components and the first decorative substrate 56. By disposing the small chip components 10 mm or more away from the outer edge of the first decorative substrate 56, the possibility of the connection points between the small chip components and the first decorative substrate 56 being damaged when a worker's hand touches the small chip components when handling the first decorative substrate 56 is reduced, and the possibility of the small chip components themselves being damaged is also reduced.

[0144] In a configuration in which small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d and areas less than 10 mm away from the outer edge of the first decorative substrate 56, the fixing through holes 56d-56g are provided in areas less than 10 mm away from the outer edge of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d-56g are provided at positions 10 mm or more away from the outer edge of the first decorative substrate 56, a larger area is secured on the first decorative substrate 56 in which small chip components can be mounted.

[0145] As shown in FIG. 8(b), an outline silk 213 that allows the mounting position of the LED driver 126 to be identified and an identification silk 214 (indicated as "IC1") that allows the mounted electronic component to be identified as the LED driver 126 are provided around the LED driver 126 on the first decorative substrate 56. Also, as shown in FIG. 8(c), an outline silk 215 that allows the mounting position of the LED chip 142 to be identified and an identification silk 216 (indicated as "LED16") that allows the mounted electronic component to be identified as the LED chip 142 are provided around the LED chip 142. As shown in FIG. 9, the first wiring layer 91 is covered with a solder resist 222. The outline silk 213 and the identification silk 214 are printed in a manner that convexly extends from the first mounting surface 84. The outline silk 213, 215 and the identification silk 214, 216 are printed before the electronic components are mounted on the first decorative substrate 56.

[0146] After mounting electronic components including small chip components on the first decorative substrate 56, when visually checking that no electronic components have been omitted, the worker can determine whether the electronic components have been mounted in the correct positions by comparing the locations of the outline silks 213, 215 with the locations of the mounted electronic components (LED driver 126 and LED chip 142). In addition, the worker can determine the types of mounted electronic components (LED driver 126 and LED chip 142) based on the display contents of the identification silks 214, 216.

[0147] As shown in FIG. 8( b), only an identification silkscreen 217 (labeled "C1") is provided around the bypass capacitor 85 to confirm that the mounted electronic component is the bypass capacitor 85, and no outline silkscreen is provided to identify the location of the bypass capacitor 85. As previously explained, the external dimensions (length, width, and height) of the bypass capacitor 85 are smaller than those of electronic components other than small chip components (such as the LED driver 126 and LED chips 127-142). For this reason, if the outline silkscreen of the bypass capacitor 85 is printed on the first decorative substrate 56, there is a risk that a worker may mistakenly believe that the bypass capacitor 85 is installed based on the outline silkscreen, even though in fact the bypass capacitor 85 has not been installed after the electronic components have been mounted. In contrast, by not providing an outline silkscreen around the bypass capacitor 85, it is easier to identify any missing bypass capacitors 85 after the electronic components have been mounted. Furthermore, by providing the identification silk 217 around the bypass capacitor 85, it is possible to identify that the component mounted around the identification silk 217 is the bypass capacitor 85.

[0148] As already explained, the external dimensions of the miniature chip resistor 87, like the external dimensions of the bypass capacitor 85, are smaller than the external dimensions of electronic components other than miniature chip components. As shown in FIG. 8(c), only an identification silk 218 (marked "R8") is provided around the miniature chip resistor 87 to confirm that the mounted electronic component is a miniature chip resistor 87, and no outline silk is provided to confirm the mounting position of the miniature chip resistor 87. This makes it easier to identify any missing mounting of the miniature chip resistor 87. Furthermore, by providing the identification silk 218 around the miniature chip resistor 87, it is possible to identify that the electronic component mounted around the identification silk 218 is a miniature chip resistor 87. Note that when an automatic mounting device is used to mount electronic components on the first decorative substrate 56, the automatic mounting device mounts the electronic components by coordinate control from a reference position on the first decorative substrate 56, so that the mounting position of the small chip component will not be shifted even if an outline silk is not provided around the small chip component.

[0149] The character size of the identification silk 217, 218 provided around the small chip components (bypass capacitor 85 and small chip resistor 87) is the same as the character size of the identification silk 214, 216 provided around the electronic components (LED driver 126 and LED chip 142) that are larger than the small chip components. This makes it easy to visually check the identification silk 217, 218 provided around the small chip components.

[0150] FIG. 16(a) is a cross-sectional view of the first decorative substrate 56 of this embodiment, and FIG. 16(b) is a cross-sectional view of a first decorative substrate 224 of a comparative example. As already explained, the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 are spaced apart by approximately 0.28 mm in the longitudinal direction of the bypass capacitor 85. Also, as already explained, no solder resist 222 is applied between the first pad 171a and the second pad 171b (see FIG. 16(a)). In the process of applying solder paste to the first decorative substrate 56, the first mounting surface 84 and the second mounting surface 95 (FIG. 9) of the first decorative substrate 56 are masked by a metal mask 226 having openings formed therein. The metal mask 226 is, for example, a thin metal plate having a thickness of approximately 150 μm. The metal mask 226 has openings that penetrate the metal mask 226 in the thickness direction at positions corresponding to the pads (or pads) of the first decorative substrate 56. The solder paste is applied onto the pads through the openings in the metal mask 226. The uniform thickness of the metal mask 226 allows the solder paste to be applied evenly to each pad.

[0151] As shown in FIG. 16(b), the outer silks 225a and 225b are convex relative to the surface of the solder resist 222. Therefore, if the outer silks 225a and 225b are provided around the small chip components (the bypass capacitor 85 and the small chip resistor 87 (FIGS. 8(b) and 8(c))), the outer silks 225a and 225b will be present between the first mounting surface 84 and the metal mask 226, increasing the distance between the first mounting surface 84 and the metal mask 226. In this configuration, the solder paste 227 may find its way into the gap between the first pad 171a and the second pad 171b, potentially electrically connecting the first pad 171a and the second pad 171b. In particular, when applying solder paste 221 continuously to multiple first decorative substrates 56, the solder paste 221 that accumulates around the edges of the openings in the metal mask 226 tends to flow around to the back side of the openings, making it easier for the first pads 171a and second pads 171b to be electrically connected. In contrast, in this embodiment, as shown in FIG. 16(a), no outline silk is provided around the small chip components. This prevents the first mounting surface 84 and the metal mask 226 from being too far apart and also prevents soldering defects caused by the solder paste 221 getting between the pads 171a and 171b. Furthermore, it also prevents parts of the small chip components from resting on the outline silk, which could cause soldering defects.

[0152] Next, a method for manufacturing the decorative substrates 56 and 57 will be described.

[0153] One possible method for efficiently manufacturing the first decorative substrate 56 is to mount electronic components on an aggregate substrate (a printed wiring board before electronic components are mounted) including multiple first decorative substrates 56, and then divide the aggregate substrate to simultaneously extract multiple first decorative substrates 56 with the electronic components mounted. Another possible method for efficiently manufacturing the second decorative substrate 57 is to mount electronic components on an aggregate substrate (a printed wiring board before electronic components are mounted) including multiple second decorative substrates 57, and then divide the aggregate substrate to simultaneously extract multiple second decorative substrates 57 with the electronic components mounted. Manufacturing the decorative substrates 56, 57 using these methods can reduce the number of times the electronic component mounting process is performed, and can improve the manufacturing efficiency of the decorative substrates 56, 57, compared to manufacturing the decorative substrates 56, 57 with electronic components mounted one by one. Below, methods for manufacturing the decorative substrates 56, 57 will be described using an example of an efficient method for manufacturing the first decorative substrate 56.

[0154] Fig. 17(a) is a plan view showing the first plate surface 268 which is the plate surface on one side of the aggregate substrate 231, Fig. 17(b) is an explanatory diagram for explaining valley division in which the aggregate substrate 231 is divided so that the first plate surface 268 has a valley shape (concave), and Fig. 17(c) is an explanatory diagram for explaining mountain division in which the aggregate substrate 231 is divided so that the first plate surface 268 has a mountain shape (convex). Note that, in reality, each of the first decorative substrates 56 included in the aggregate substrate 231 has multiple electronic components mounted thereon and wiring patterns and the like formed thereon, but in Figs. 17(a) to 17(c) they are illustrated in a simplified manner to avoid complicating the drawings.

[0155] The aggregate substrate 231 is a four-layer substrate having a structure in which conductive layers and insulating layers are alternately laminated, similar to the already-described decorative substrates 56 and 57. As shown in Fig. 17(a), the aggregate substrate 231 is produced by cutting out a portion of a substantially square printed wiring board by a router process or the like, in which a drill-shaped cutting tool (router) with blades on the side is rotated while processing, and by forming dividing grooves 232-247 and slits 251-258 in the printed wiring board.

[0156] The aggregate substrate 231 is divided into four first decorative substrates 56 and seven throw-away substrates 261 to 267 by dividing grooves 232 to 247 and slits 251 to 258. The process of forming the dividing grooves 232 to 247 and the slits 251 to 258 in the aggregate substrate 231 is carried out before electronic components are mounted on the aggregate substrate 231. The aggregate substrate 231 is divided using the dividing grooves 232 to 247 and the slits 251 to 258.

[0157] The dividing grooves 232-247 are formed linearly by cutting the aggregate substrate 231 using, for example, a disk-shaped blade rotating at high speed. The dividing grooves 232-247 have a V-shaped cross section that reduces the thickness of the aggregate substrate 231, with the bottoms of the dividing grooves 232-247 being the thinnest parts. The areas of the aggregate substrate 231 where the dividing grooves 232-247 are formed have lower mechanical strength than areas where the dividing grooves 232-247 are not formed. Therefore, by dividing the aggregate substrate 231 using the dividing grooves 232-247 as base points, the stress acting on the first decorative substrate 56 when dividing the aggregate substrate 231 can be reduced. This reduces stress that may act on the connection points between the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149) and the first decorative substrate 56 when dividing the aggregate substrate 231, and also reduces stress that may act on the small chip components themselves. It is also possible to prevent the base points of division from shifting from the division grooves 232 to 247. The cross-sectional shape of the division grooves 232 to 247 is not limited to a V-shape. The cross-sectional shape of the division grooves 232 to 247 may be rectangular or U-shaped, as long as it allows the aggregate substrate 231 to be easily separated by an external force.

[0158] Because the dividing grooves 232-247 are formed in a straight line, the stress that may act on the first decorative substrate 56 when the aggregate substrate 231 is divided is reduced compared to a configuration in which the dividing grooves 232-247 are formed in a curved line.

[0159] In this embodiment, the dividing grooves 232-247 are formed only on the first plate surface 268 side of the aggregate substrate 231 in order to make it easier to distinguish between the first plate surface 268 and the second plate surface 269 (FIG. 17(b)), which is the plate surface opposite to the first plate surface 268, thereby improving the workability of the substrate dividing process. The slits 251-258 are formed, for example, by the above-mentioned router processing. The slits 251-258 are in the shape of long, narrow slots and are formed wider than the dividing grooves 232-247.

[0160] 17(a), a vertically long, approximately rectangular central discarded substrate 261 is provided in the center of the left-right direction of the aggregate substrate 231. A pair of first decorative substrates 56 are provided on the left side of the central discarded substrate 261, with dividing grooves 232, 233 between them, and another pair of first decorative substrates 56 are provided on the right side of the central discarded substrate 261, with dividing grooves 234, 235 between them. The four first decorative substrates 56 are flush, and the first mounting surfaces 84 of these first decorative substrates 56 are on the first plate surface 268 side of the aggregate substrate 231.

[0161] As already explained, the first decorative substrates 56 have a stepped recess 56a and a cutout 56b formed therein. In the lower left first decorative substrate 56, the stepped recess 56a is provided on the side of the central discarded substrate 261, and the cutout 56b is provided on the side of the left discarded substrate 263, which will be described later. In the upper left first decorative substrate 56, the stepped recess 56a is provided on the side of the left discarded substrate 263, and the cutout 56b is provided on the side of the central discarded substrate 261. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. A cutout is made between these stepped recesses 56a, and the stepped recesses 56a are not connected to each other.

[0162] In the first decorative substrate 56 at the bottom right, the stepped recess 56a is provided on the side of the right-side discarded substrate 266, which will be described later, and the cutout 56b is provided on the side of the central discarded substrate 261. In the first decorative substrate 56 at the top right, the stepped recess 56a is provided on the side of the central discarded substrate 261, and the cutout 56b is provided on the side of the right-side discarded substrate 266. The stepped recesses 56a of the pair of first decorative substrates 56 face each other. A cutout is made between these stepped recesses 56a, and the stepped recesses 56a are not connected to each other.

[0163] To the left of the central discarded substrate 261, a lower left discarded substrate 262, a vertically elongated, approximately rectangular left discarded substrate 263, and an upper left discarded substrate 264 are provided on the lower, left, and upper sides of the pair of first decorative substrates 56. The lower left discarded substrate 262 is connected to the left side discarded substrate 263 and the central discarded substrate 261 via dividing grooves 236 and 237, and the upper left discarded substrate 264 is connected to the left side discarded substrate 263 and the central discarded substrate 261 via dividing grooves 238 and 239. A slit 251 is formed between the lower left discarded substrate 262 and the upper left first decorative substrate 56, so that the lower left discarded substrate 262 and the upper left first decorative substrate 56 are not connected. In addition, a slit 252 is formed between the upper left discarded substrate 264 and the upper right first decorative substrate 56, so that the upper left discarded substrate 264 and the upper right first decorative substrate 56 are not connected. The left-side throw-away substrate 263 is connected to the lower left first decorative substrate 56 and the upper left first decorative substrate 56 via dividing grooves 240, 241.

[0164] To the right of the central discarded substrate 261, a lower right discarded substrate 265, a vertically elongated, approximately rectangular right discarded substrate 266, and an upper right discarded substrate 267 are provided below, to the right, and above the pair of first decorative substrates 56. The lower right discarded substrate 265 is connected to the central discarded substrate 261 and the right right discarded substrate 266 via dividing grooves 242 and 243, and the upper right discarded substrate 267 is connected to the central discarded substrate 261 and the right right discarded substrate 266 via dividing grooves 244 and 245. A slit 253 is formed between the lower right discarded substrate 265 and the lower left first decorative substrate 56, so the lower right discarded substrate 265 and the lower left first decorative substrate 56 are not connected. In addition, a slit 254 is formed between the upper right discarded substrate 267 and the lower right first decorative substrate 56, so the upper right discarded substrate 267 and the lower right first decorative substrate 56 are not connected. The right-side throw-away substrate 266 is connected to the lower left first decorative substrate 56 and the lower right first decorative substrate 56 via dividing grooves 246, 247.

[0165] In this way, the discarded substrates 262-267 are provided around the entire periphery of the aggregate substrate 231, and the four first decorative substrates 56 are surrounded by the discarded substrates 262-267. This makes it possible to handle the aggregate substrate 231 after mounting electronic components without touching the electronic components mounted on the first decorative substrates 56. This prevents the electronic components from being damaged by the worker's hands coming into contact with the electronic components. The number of first decorative substrates 56 included in the aggregate substrate 231 is not limited to "4". The aggregate substrate 231 may include more than "4" (for example, "6"), or may include less than "4" (for example, "2"),

[0166] A pair of first decorative substrates 56 are provided on the left side of the central discarded substrate 261 with their stepped recesses 56a facing each other, and a pair of first decorative substrates 56 are provided on the right side of the central discarded substrate 261 with their stepped recesses 56a facing each other, thereby reducing the vertical dimension of the aggregate substrate 231 including the four first decorative substrates 56.

[0167] Next, the manufacturing process of the decorative substrates 56, 57 will be described using the manufacturing process of the first decorative substrate 56 as an example.

[0168] In the manufacturing process of the first decorative board 56, first, with the second board surface 269 (the second mounting surface 95 side, see FIG. 17(b)) of the aggregate board 231 facing upward, the following steps are performed: a solder application process in which solder paste is applied to pads (or pads) provided on the second board surface 269 of the aggregate board 231; an adhesive application process in which adhesive for fixing the connectors is applied; a component mounting process in which connectors 111, 112 (FIG. 8(a)) are mounted on the second board surface 269 side of the aggregate board 231 using an automatic mounting device (not shown); a reflow process in which the aggregate board 231 is transported to a reflow furnace and heated; and a cooling process in which the aggregate board 231 is cooled to room temperature. As a result, the connectors 111, 112 are mounted on the second board surface 269 side of the aggregate board 231. The adhesive hardens to prevent the connectors 111, 112 from falling off during the second reflow process.

[0169] Thereafter, with the first plate surface 268 of the aggregate substrate 231 facing upward, the following steps are performed: a solder application process in which solder paste is applied onto lands provided on the first plate surface 268 side (first mounting surface 84 side) of the aggregate substrate 231, a component mounting process in which electronic components including small chip components are mounted on the first plate surface 268 side of the aggregate substrate 231 using an automatic mounting device (not shown), a reflow process in which the aggregate substrate 231 is transported to a reflow furnace and heated, a cooling process in which the aggregate substrate 231 is cooled to room temperature, a substrate dividing process in which the aggregate substrate 231 is divided after the electronic components have been mounted, and a mounting confirmation process in which the first decorative substrate 56 is visually checked for any missing electronic components. As a result, the electronic components including small chip components are mounted on the first plate surface 268 side of the aggregate substrate 231.

[0170] 17(a), the left-side throw-away board 263 and the right-side throw-away board 266 have first mounting reference holes 271 and second mounting reference holes 272 formed therein, penetrating the aggregate board 231 in the thickness direction. The first mounting reference holes 271 are used to align the aggregate board 231 in the component mounting process of mounting electronic components on the first board surface 268, and the second mounting reference holes 272 are used to align the aggregate board 231 in the component mounting process of mounting electronic components on the second board surface 269. After aligning the aggregate board 231, the automatic mounting device uses coordinate control to set the small chip components on the first decorative board 56 so that the electrodes of the small chip components are placed on the solder paste applied to the corresponding pads (or pads).

[0171] Known methods for dividing the aggregate substrate 231 include a method in which an operator manually divides the aggregate substrate 231, and a method in which the aggregate substrate 231 is mechanically cut using a press or the like. Of these, by adopting the manual division method, it becomes possible to flexibly handle multiple types of aggregate substrates while keeping equipment costs down.

[0172] Possible methods for dividing the aggregate substrate 231 include valley division, in which the aggregate substrate 231 is divided using the dividing grooves 232 to 247 as base points so that the first plate surface 268 on which the small chip components are collected has a valley shape (concave), and mountain division, in which the aggregate substrate 231 is divided using the dividing grooves 232 to 247 as base points so that the first plate surface 268 has a mountain shape (convex). In the substrate dividing step, as shown in Fig. 17(b), the aggregate substrate 231 is divided using valley division, in which the dividing grooves 232 to 247 are used as base points so that the first plate surface 268 has a valley shape (concave), and a plurality of first decorative substrates 56 (specifically, four) are taken out.

[0173] As already explained, in the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149) are concentrated on the first mounting surface 84 side. In the aggregate substrate 231, the small chip components are concentrated on the first plate surface 268 side (first mounting surface 84 side), and are not mounted on the second plate surface 269 side (second mounting surface 95 side). Also, as already explained, the connection points between the small chip components and the first decorative substrate 56 have lower mechanical strength than the connection points between other electronic components and the first decorative substrate 56. When the aggregate substrate 231 is split in half as shown in FIG. 17(c), the force that can act on the first plate surface 268 side (first mounting surface 84 side) of the aggregate substrate 231 is tensile stress, and the force that can act on the second plate surface 269 side (second mounting surface 95 side) is compressive stress. On the other hand, when the aggregate substrate 231 is split into valleys as shown in Figure 17(b), the force that can act on the first plate surface 268 side (first mounting surface 84 side) of the aggregate substrate 231 is compressive stress, and the force that can act on the second plate surface 269 side (second mounting surface 95 side) is tensile stress.

[0174] Stresses generated when dividing the aggregate substrate 231 act more strongly on the convex (mountain) surface than on the concave (valley) surface. By dividing the aggregate substrate 231 into valleys so that the first surface 268 (the first mounting surface 84) on which the small chip components are concentrated has a concave (valley) shape, stresses that may act on the connections between the small chip components and the first decorative substrate 56 during division of the aggregate substrate 231 can be reduced, as well as stresses that may act on the small chip components themselves. This reduces the likelihood of damage to the connections between the small chip components and the first decorative substrate 56, as well as the possibility of damage to the small chip components themselves. By reducing the likelihood of poor contact between the small chip components during the substrate division process, the manufacturing efficiency of the first decorative substrate 56 can be improved.

[0175] Among the small chip components, the multilayer ceramic capacitors used as bypass capacitors 85 are vulnerable to tensile stress, and when tensile stress acts on bypass capacitors 85, cracks are likely to occur in bypass capacitors 85 themselves. By dividing aggregate substrate 231 into valleys so that first plate surface 268 (first mounting surface 84) on which small chip components including bypass capacitors 85 are collected has a valley shape (concave), the force that may act on bypass capacitors 85 is converted into compressive stress, and tensile stress can be prevented from acting on bypass capacitors 85. This reduces the possibility that bypass capacitors 85 themselves will be damaged when aggregate substrate 231 is divided.

[0176] As already explained, by dividing the aggregate substrate 231 using the dividing grooves 232-247 as base points, it is possible to minimize the stress that may act on the connection points between the small chip components and the first decorative substrate 56, and also to minimize the stress that may act on the small chip components. On the other hand, if the dividing base points are shifted from the dividing grooves 232-247, these stresses will increase. A dividing jig is used to prevent the dividing base points from shifting from the dividing grooves 232-247 and to improve the workability of the substrate dividing process.

[0177] Fig. 18(a) is a perspective view of a dividing jig 281 used to divide the aggregate substrate 231 in this embodiment, Fig. 18(b) is a front view of the dividing jig 281, and Fig. 18(c) is an explanatory diagram for explaining how the aggregate substrate 231 is divided using the dividing jig 281. As shown in Fig. 18(a), the dividing jig 281 includes a thin metal blade 282 that comes into contact with the division grooves 232 to 247 and serves as a fulcrum when dividing the aggregate substrate 231, and a base 283 that supports the thin blade 282. The base 283 includes a resin base portion 283a molded in the shape of a horizontally elongated rectangular parallelepiped, and a rectangular parallelepiped upright portion 283b that is integrally formed and stands up from a plate surface on one side of the base portion 283a.

[0178] The thin blade 282 includes a plate-shaped cutting edge 282a and a flange 282b. The flange 282b is fixed to the base 283 by screwing it to the upright portion 283b. The cutting edge 282a protrudes upward from the upper flat surface of the upright portion 283b and extends in the longitudinal direction of the upright portion 283b.

[0179] A protrusion 283c is integrally formed at approximately the center in the longitudinal direction of the standing portion 283b to assist in aligning the collective substrate 231 with the blade portion 282a so that the blade portion 282a abuts against the dividing grooves 232-247. The protrusion 283c protrudes upward from the upper flat surface of the standing portion 283b with a larger protrusion dimension than the blade portion 282a. As shown in FIG. 17(a), recesses 284 and 285 are provided between the pair of first decorative substrates 56 on the right side of the left-side discarded substrate 263 and the left side of the central discarded substrate 261, allowing the protrusion 283c to be inserted therethrough. In addition, recesses 286 and 287 are provided between the pair of first decorative substrates 56 on the right side of the central discarded substrate 261 and the left side of the right-side discarded substrate 266, allowing the protrusion 283c to be inserted therethrough.

[0180] As shown in FIG. 18(c), the worker holds the first surface 268 (first mounting surface 84) of the collective substrate 231 facing downward, and fixes one of the center throwaway substrate 261, the left throwaway substrate 263, and the right throwaway substrate 266 (the center throwaway substrate 261 in FIG. 18(c)) on the upright portion 283b. At this time, by inserting the protrusions 283c into the recesses 284-287 (FIG. 17(a)) provided in the throwaway substrates 261, 263, and 266, it is possible to easily create a state in which the dividing grooves 232-247, which serve as the base points for dividing, are in contact with the blade portion 282a. In this state, by applying a downward force to the second surface 269 and pushing downward the portion protruding to the right from the upright portion 283b, the collective substrate 231 can be divided into valleys using the dividing grooves 232-247 as base points, with the first surface 268 forming a valley shape (concave).

[0181] For example, the worker first divides the aggregate substrate 231 (FIG. 17(a)) into a first unit including a pair of first decorative substrates 56 on the left side, a lower-left discard substrate 262, a left-side discard substrate 263, and an upper-left discard substrate 264, and a second unit including a pair of first decorative substrates 56 on the right side, a central discard substrate 261, a lower-right discard substrate 265, a right-side discard substrate 266, and an upper-right discard substrate 267. Then, in the first unit, the pair of first decorative substrates 56 and the left-side discard substrate 263 are separated, thereby removing two first decorative substrates 56. Furthermore, in the second unit, the pair of first decorative substrates 56 and the central discard substrate 261 are separated, and the pair of first decorative substrates 56 and the right-side discard substrate 266 are separated, thereby removing two first decorative substrates 56. The order in which the aggregate substrate 231 is divided to remove the four first decorative substrates 56 is arbitrary.

[0182] With the blade portion 282a in contact with the dividing grooves 232 to 247 that serve as the base points for division, the aggregate substrate 231 is divided into valleys using the blade portion 282a as a fulcrum, thereby preventing the base points for division from shifting from the dividing grooves 232 to 247. This minimizes stress that may act on the connection points between the small chip components and the first decorative substrate 56 when dividing the aggregate substrate 231, and also minimizes stress that may act on the small chip components themselves.

[0183] Because the aggregate substrate 231 is split into valleys by pushing the second mounting surface 95 downward, it is easier for the worker to apply force to split the aggregate substrate 231, compared to a configuration in which the aggregate substrate 231 is split into valleys by pulling the second mounting surface 95 upward. Also, in the center discarded substrate 261, the left discarded substrate 263, and the right discarded substrate 266, recesses 284 to 287 (FIG. 17(a)) are provided between the pair of first decorative substrates 56, making it possible to fix the aggregate substrate 231 to the splitting jig 281 while preventing an increase in stress acting on the electronic components mounted on the first decorative substrates 56.

[0184] As already explained with reference to FIG. 8(a), the first decorative substrate 56 is provided with fixing through-holes 56d-56g, and the small chip components are arranged avoiding the through-hole peripheral areas 211a-211d. Therefore, as shown in FIG. 18(c), when the first plate surface 268 (first mounting surface 84) is facing downward and one of the central discarded substrate 261, the left discarded substrate 263, and the right discarded substrate 266 is fixed to the upright portion 283b, a downward force is applied to the second plate surface 269 to push downward the portion protruding from the upright portion 283b to divide the aggregate substrate 231, the vicinity of the fixing through-holes 56d-56g can be selected as the location to be pushed downward. This minimizes the stress that may act on the small chip components mounted on the first plate surface 268 side (first mounting surface 84 side).

[0185] As already explained, the division grooves 232 to 247 are formed only on the first plate surface 268 side of the collective substrate 231, and are not formed on the second plate surface 269 side. Therefore, the worker simply sets the collective substrate 231 in the dividing jig 281 with the plate surface on which the division grooves 232 to 247 are formed (first plate surface 268) facing downward, reducing the possibility of the collective substrate 231 being accidentally divided into two.

[0186] As shown in FIG. 17(a), the 16 dividing grooves 232-247 in the aggregate substrate 231 extend in the first direction DR1. The extending directions of these dividing grooves 232-247 are parallel to one another. As already explained with reference to FIGS. 8(a) to 8(c), the small chip components (the bypass capacitor 85 and the small chip resistors 87, 143-149 (FIG. 11)) are mounted on the first decorative substrate 56 in such a manner that the longitudinal direction of the small chip components is parallel to the 16 dividing grooves 232-247 in the aggregate substrate 231. Therefore, compared to a configuration in which the longitudinal direction of the small chip components is perpendicular to the extending direction of the dividing grooves 232-247, stress that may act on the connection points between the small chip components and the first decorative substrate 56 when the aggregate substrate 231 is divided using the dividing grooves 232-247 as base points is reduced, and stress that may act on the small chip components themselves is also reduced.

[0187] As shown in FIG. 17(a), slits 255-258 are provided in the aggregate substrate 231 at locations corresponding to the area where the bypass capacitor 85 is mounted. As already explained, the slits 255-258 are elongated holes, and are formed wider than the dividing grooves 233, 234, 240, and 247. When the aggregate substrate 231 is divided into valleys using the dividing grooves 232-247 as base points, the stress that may act around the slits 255-258 is smaller than the stress that may act around the dividing grooves 232-247. By providing the slits 255-258 at locations corresponding to the mounting area of ​​the bypass capacitor 85, the stress that may act on the connection points between the bypass capacitor 85 and the first decorative substrate 56 when the aggregate substrate 231 is divided is reduced, and the stress that may act on the bypass capacitor 85 itself is also reduced.

[0188] As shown in FIGS. 8(a) and 8(b), the bypass capacitor 85 is disposed closer to the stepped recess 56a than the LED driver 126. As already explained with reference to FIG. 17(a), the dividing grooves 233, 234, 240, and 247 are not provided on the stepped recess 56a side of the aggregate substrate 231. By disposing the bypass capacitor 85 on the opposite side of the dividing grooves 233, 234, 240, and 247 across the LED driver 126, stress that may act on the connection between the bypass capacitor 85 and the first decorative substrate 56 when the aggregate substrate 231 is divided about the dividing grooves 233, 234, 240, and 247 can be reduced, as well as stress that may act on the bypass capacitor 85 itself. This reduces the possibility of damage to the connection between the bypass capacitor 85 and the first decorative substrate 56 when the aggregate substrate 231 is divided, and also reduces the possibility of damage to the bypass capacitor 85 itself.

[0189] As already explained with reference to Figures 8(b) and 8(c), the spacing direction between the pads 171a, 171b corresponding to the electrodes 85a, 85b of the bypass capacitor 85 and the spacing direction between the pads 176a, 176b corresponding to the electrodes 87a, 87b of the small chip resistor 87 are the first direction DR1. By transporting the assembly substrate 231 in a direction perpendicular to or substantially perpendicular to the common spacing direction (first direction DR1) (second direction DR2) during the reflow process, it is possible to synchronize the timing at which heating of the solder paste applied to the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 begins, and it is also possible to synchronize the timing at which heating of the solder paste applied to the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 begins. This prevents rotation of the multiple small chip components and chip standing. 17(a), an identification mark 288 is provided on the first surface 268 side of the left-side throwaway substrate 263, allowing the transport direction of the collective substrate 231 in the reflow process to be confirmed. Although not shown, an identification mark is also provided on the second surface 269 side of the left-side throwaway substrate 263, allowing the transport direction of the collective substrate 231 in the reflow process to be confirmed. This reduces the possibility that the worker will make a mistake in the transport direction of the collective substrate 231.

[0190] As already explained with reference to FIG. 8(a), in a configuration in which the LED driver 126 is arranged in an area including an area less than 10 mm from the outer edge of the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are arranged 10 mm or more away from the outer edge of the first decorative substrate 56. As already explained, the connection points between the small chip components and the first decorative substrate 56, among the various electronic components mounted on the first decorative substrate 56, have lower mechanical strength than the connection points between other electronic components and the first decorative substrate 56. In addition, the area within 10 mm from the outer edge of the first decorative substrate 56 is an area that may be located near the dividing grooves 232-247 (FIG. 17) in the aggregate substrate 231 (FIG. 17), and is also an area where force may be applied to split the aggregate substrate 231 into valleys. By arranging the small chip components at a distance of 10 mm or more from the outer edge of the first decorative substrate 56, the maximum value of stress that can act on the connection points between the small chip components and the first decorative substrate 56 when the aggregate substrate 231 is divided is reduced, and the maximum value of stress that can act on the small chip components themselves is also reduced.

[0191] <Electrical configuration of pachinko machine 10> FIG. 19 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0192] The main control device 60 comprises a main control board 61 which is responsible for the main control of the game, and a power outage monitoring board 67 which monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 has a main CPU 63 which is an arithmetic processing device including a control unit and an arithmetic unit, as well as a main ROM 64 and a main RAM 65. In addition to the above elements, the MPU 62 also has built-in interrupt circuits, timer circuits, data input / output circuits, various counter circuits such as random number generators, etc.

[0193] The main ROM 64 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0194] The main RAM 65 is a memory (i.e., a volatile memory means) that requires an external power supply to retain data, such as SRAM or DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible and takes less time to read data than the main ROM 64 when compared for the same data capacity. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0195] The main CPU 63 executes a process for managing the game history. The main CPU 63 grasps the ball entry history of game balls into the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and grasps the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 according to the grasped ball entry history. The main CPU 63 also grasps the occurrence frequency of the opening / closing execution mode and the high frequency support mode, which will be described later.

[0196] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply / launch control device 78 having the function of supplying operating power, and operating power is supplied to the MPU 62 via the power outage monitoring board 67.

[0197] Various sensors, such as the ball entry detection sensors 42a-49a, are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a include the first prize entry detection sensor 42a, the second prize entry detection sensor 43a, the third prize entry detection sensor 44a, the special electric current detection sensor 45a, the first operation port detection sensor 46a, the second operation port detection sensor 47a, the outlet detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 determines whether a ball has entered each entry area. In addition, the main CPU 63 executes various lotteries based on whether a ball has entered the first operation port 33, and also executes various lotteries based on whether a ball has entered the second operation port 34.

[0198] The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position. The main CPU 63 then determines whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b has been pressed. The main CPU 63 then determines whether the update button 68b has been pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c has been pressed. The main CPU 63 then determines whether the reset button 68c has been pressed based on the detection result from the sensor.

[0199] The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio / light emitting control device 81. A prize ball command is output to the payout control device 77, for example, when a gaming ball enters a prize ball entry section among the entry sections, where the occurrence of the ball entry corresponds to the payout of the gaming ball. Various commands such as a variation command, a type command, and an opening command are output to the audio / light emitting control device 81.

[0200] The output side of the MPU 62 is connected to a special power drive unit 32b that opens and closes the opening / closing door 32a of the special power winning device 32, a normal power drive unit 34b that opens and closes the normal power device 34a of the second operating port 34, a special power unit 37, and a normal power unit 38. Incidentally, the special power unit 37 is provided with a special power display unit 37a and a special power reserve display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal power unit 38 is provided with a normal power display unit 38a and a normal power reserve display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 controls the drive of various drive units and various display units through these driver circuits.

[0201] That is, in the opening / closing execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power device 34a is won, the main CPU 63 executes drive control of the normal power drive unit 34b so that the normal power device 34a is opened and closed. Also, during each game round, the main CPU 63 executes display control of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power device 34a is to be opened is clearly displayed, the main CPU 63 executes display control of the normal chart display unit 38a. In addition, when a prize is won at the first operating port 33 or the second operating port 34, or when a changing display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart reserve display unit 37b, and when a prize is won at the through gate 35, or when a changing display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart reserve display unit 38b.

[0202] The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The first to third notification display devices 69a to 69c display the results of game history management. When the setting state of the pachinko machine 10 is changed, the third notification display device 69c displays the current setting value. The first to third notification display devices 69a to 69c are display-controlled by the main CPU 63.

[0203] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the stable DC voltage of 24 volts, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0204] The power supply and launch control device 78 is connected to a commercial power source (external power source) in, for example, an amusement hall. Based on the external power supplied from the commercial power source, the power supply and launch control device 78 generates the necessary operating power for the main control board 61, the payout control device 77, and other components, and supplies the generated operating power to them. The power supply and launch control device 78 is provided with a power supply unit for power outages, such as a backup capacitor, so that even when the power supply to the pachinko machine 10 is turned off, the power supply unit for power outages supplies power for memory retention to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply and launch control device 78 also controls the launch of the game ball launching mechanism 27, which is activated when predetermined launch conditions are met. The payout mechanism 73 is also provided with a power switch, as already explained. Turning the power switch ON starts the supply of operating power to the pachinko machine 10, and turning the power switch OFF stops the supply of operating power to the pachinko machine 10.

[0205] The audio and light-emitting control device 81 drives and controls the speaker unit 53 provided on the front door frame 14 based on various commands received from the main control device 60. As already explained, the audio and light-emitting control device 81 also controls the light emission of the LED chips 127-142 mounted on the first decorative substrate 56 and the LED chips mounted on the second decorative substrate 57. Furthermore, the audio and light-emitting control device 81 controls the display control device 82. The display control device 82 performs display control of the pattern display device 41 based on commands received from the audio and light-emitting control device 81.

[0206] <Electrical configuration for performing various lotteries in the main CPU 63> Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

[0207] During play, the master CPU 63 uses various counter information to determine whether a jackpot occurs, set the display of the special symbol display unit 37a, set the symbol display of the symbol display unit 41, and set the display of the normal symbol display unit 38a. Specifically, as shown in FIG. 20, the master CPU 63 uses a hit random number counter C1 used to determine whether a jackpot occurs, a jackpot type counter C2 used to determine the type of jackpot, a reach random number counter C3 used to determine whether a reach occurs when the symbol display unit 41 changes due to a miss, a random number initial value counter CINI used to set the initial value of the hit random number counter C1, and a change type counter CS used to determine the display duration of the special symbol display unit 37a and the symbol display unit 41. Furthermore, the master CPU 63 uses a normal power feature release counter C4 used to determine whether the normal power feature 34a of the second operating port 34 is set to a normal power release state. The counters C1-C3, CINI, CS, and C4 are provided in the various counter area 65b of the master RAM 65.

[0208] Each counter C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching its maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

[0209] The reserve storage area 65a comprises a reserve area RE and an execution area AE. The reserve area RE comprises a first reserve area RE1, a second reserve area RE2, a third reserve area RE3 and a fourth reserve area RE4, and a combination of numerical information of the win random number counter C1, the jackpot type counter C2 and the reach random number counter C3 is stored as reserve information in one of the reserve areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

[0210] In this case, when multiple consecutive wins occur in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in chronological order from the first hold area RE1 to the second hold area RE2 to the third hold area RE3 to the fourth hold area RE4. By providing four hold areas RE1 to RE4 in this way, up to four winning histories of game balls entering the first actuation port 33 or the second actuation port 34 can be reserved and stored.

[0211] The number of items that can be stored on hold is not limited to four and can be any number, such as two, three, five or more, or it can be singular.

[0212] The execution area AE is an area for moving each piece of numerical information stored in the first holding area RE1 of the holding area RE when the variable display of the special chart display section 37a begins, and when one game round starts, a win / loss determination is made based on the various numerical information stored in the execution area AE.

[0213] Each of the counters will now be described in detail.

[0214] First, the normal power accessory opening counter C4 will be described. The normal power accessory opening counter C4 is configured to be incremented by one in sequence within a range of, for example, 0 to 250, and to return to "0" after reaching the maximum value. The normal power accessory opening counter C4 is periodically updated, and is stored in the normal power reserve area 65c of the main RAM 65 when a gaming ball enters the through gate 35. Then, at a predetermined timing, a lottery is held to determine whether or not to control the normal power accessory 34a to the open state based on the value of the stored normal power accessory opening counter C4.

[0215] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power device 34a differs from one another. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 is opened per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the same manner into the game area PA.

[0216] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power device opening counter C4 is the same (for example, 4 / 5 in both), but in the high-frequency support mode, the number of times the normal power device 34a opens when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for each opening is set to be longer.In this case, if the normal power opening state is won in the high-frequency support mode and the normal power device 34a opens multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each opening.Furthermore, in the high-frequency support mode, the minimum time ensured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0217] As described above, in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into first actuation port 33 is higher than in second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in first actuation port 33. When a winning entry into second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

[0218] The configuration for increasing the frequency of normal power release per unit time in the high-frequency support mode compared to the low-frequency support mode is not limited to the above, and may be configured to increase the probability of winning the normal power release state in the normal power release lottery, for example. In addition, in a configuration in which multiple types of reserved time (e.g., the time of variable display executed by the normal power display unit 38a based on winning at the through gate 35) are available for the period between one normal power release lottery and the next, the high-frequency support mode may be configured to be more likely to select a shorter reserved time or to have a shorter average reserved time than the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of the following conditions: increasing the number of releases, lengthening the open time, shortening the reserved time between one normal power release lottery and the next, shortening the average reserved time, and increasing the winning probability.

[0219] As already explained, the pachinko machine 10 has setting states "Setting 1" to "Setting 6." The opening frequency and opening mode of the normal power device 34a in the low-frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high-frequency support mode are also the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low-frequency support mode and the high-frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low-frequency support mode, or the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the low-frequency support mode. In addition, the higher the set value, the higher the frequency of opening of the normal power device 34a in the high frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the high frequency support mode.

[0220] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to increment by one within a range of, for example, 0 to 7999, and return to "0" after reaching a maximum value. In particular, when the winning random number counter C1 completes one cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 7999). The winning random number counter C1 is periodically updated, and is stored in the reserve storage area 65a of the main RAM 65 when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0221] The random number value that results in a jackpot win is stored as a hit / miss table in the main ROM 64. As shown in Fig. 19, the main ROM 64 is provided with a hit / miss table storage area 64a. The hit / miss table storage area 64a stores, as hit / miss tables, a low-probability hit / miss table for the low-probability mode and a high-probability hit / miss table for the high-probability mode.

[0222] The low-probability hit / miss table is provided in one-to-one correspondence with the setting states of "setting 1" to "setting 6." That is, there is a low-probability hit / miss table for setting 1 that is referenced when the setting state of the pachinko machine 10 is "setting 1," a low-probability hit / miss table for setting 2 that is referenced when the setting state of the pachinko machine 10 is "setting 2," a low-probability hit / miss table for setting 3 that is referenced when the setting state of the pachinko machine 10 is "setting 3," a low-probability hit / miss table for setting 4 that is referenced when the setting state of the pachinko machine 10 is "setting 4," a low-probability hit / miss table for setting 5 that is referenced when the setting state of the pachinko machine 10 is "setting 5," and a low-probability hit / miss table for setting 6 that is referenced when the setting state of the pachinko machine 10 is "setting 6."

[0223] These low probability tables are set so that the higher the setting value, the higher the probability of winning a jackpot. Specifically, when the low probability table for setting 1 is referenced, the jackpot result occurs at 1 in 320, when the low probability table for setting 2 is referenced, the jackpot result occurs at approximately 1 in 308, when the low probability table for setting 3 is referenced, the jackpot result occurs at approximately 1 in 278, when the low probability table for setting 4 is referenced, the jackpot result occurs at approximately 1 in 286, when the low probability table for setting 5 is referenced, the jackpot result occurs at approximately 1 in 276, and when the low probability table for setting 6 is referenced, the jackpot result occurs at approximately 1 in 267. As a result, when the setting state of the pachinko machine 10 is set at a higher value, the jackpot result is more likely to occur in the low probability mode, which is advantageous for the player.

[0224] On the other hand, only one type of high-probability table is provided so that it is common to all settings, from "Setting 1" to "Setting 6." The high-probability table is set to have a higher probability of winning a jackpot than the low-probability table, regardless of the setting, from "Setting 1" to "Setting 6." Specifically, when the high-probability table is referenced, the jackpot result occurs at approximately 1 / 30. This makes it possible to make the high-probability mode more advantageous than the low-probability mode, regardless of the setting of the pachinko machine 10. Furthermore, even in the lowest setting, "Setting 1," the high-probability mode can be set, thereby increasing the probability of winning a jackpot compared to the low-probability mode of the highest setting, "Setting 6." Furthermore, it is possible to prevent advantages or disadvantages depending on the setting of the pachinko machine 10 for the high-probability mode, and it is also possible to reduce the storage capacity required to pre-store the high-probability table in the main ROM 64.

[0225] The jackpot type counter C2 is configured to be incremented by 1 in sequence within a range of 0 to 29, and to return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically, and is stored in the reserve storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0226] A plurality of jackpot results are set in this pachinko machine 10. These plurality of jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning / losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the normal power device 34a of the second operating port 34 after the opening and closing execution mode ends.

[0227] As the manner of opening and closing control of the special power winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special power winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds of play are played up to the upper limit.

[0228] A round game is a game that continues until one of the following conditions is met: a predetermined upper limit duration has elapsed, or a predetermined upper limit number of game balls have entered the special electric winning device 32. Furthermore, the number of rounds in the open / close execution mode triggered by a jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the upper limit for the number of rounds is set to 15.

[0229] Furthermore, in this pachinko machine 10, a plurality of types are set for one opening mode of the special electric winning device 32, with different opening durations from when the special electric winning device 32 is opened until when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

[0230] In this pachinko machine 10, when the launch operation device 28 is operated by a player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the play area PA every 0.6 seconds. The upper limit for the number of balls required to complete a round game is set to nine. In this case, the long-time mode among the above-mentioned release modes sets the release duration to a time longer than the product of the game ball launch cycle and one round game. On the other hand, the short-time mode sets the release duration to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when a single release is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of prizes in one round game. When a single release is performed in the short-time mode, it is expected that the special electric winning device 32 will not win, or that only one prize will be won, even if one is won.

[0231] In the high frequency winning mode, the special power winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special power winning device 32 is opened once in each round of play in a short time mode.

[0232] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of rounds of play in one round in the high frequency winning mode and low frequency winning mode are not limited to the above values ​​and are arbitrary, as long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

[0233] 19, the main ROM 64 is provided with an allocation table storage area 64b. The allocation table storage area 64b stores an allocation table in which the allocation destination of the jackpot result for the jackpot type counter C2 is set. In the allocation table, a low probability jackpot result, a low prize winning high probability jackpot result, and a most advantageous jackpot result are set as the allocation destination of the jackpot result in the event of a jackpot result.

[0234] A low probability jackpot result is a jackpot result in which the opening / closing execution mode becomes a high frequency winning mode, and after the opening / closing execution mode ends, the winning / losing lottery mode becomes a low probability mode and the support mode becomes a high frequency support mode. However, this high frequency support mode will transition to a low frequency support mode if the number of games played after the transition reaches the termination reference number (specifically, 100 times).

[0235] A low-prize, high-probability jackpot result is a jackpot result in which the open / close execution mode becomes a low-frequency win mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0236] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0237] In relation to the above game states, the normal game state refers to a state in which the win / lose lottery mode is a low probability mode and the support mode is a low frequency support mode, rather than the open / close execution mode. Also, a low-prize, high-probability jackpot result may not be set as a game result. In addition, in the open / close execution mode in a low-prize, high-probability jackpot result, the number of rounds of play may be fewer than in the case of a low-probability jackpot result and a most favorable jackpot result.

[0238] In the distribution table, of the values ​​of the jackpot type counter C2 from "0 to 29", "0 to 9" corresponds to a low probability jackpot result, "10 to 14" corresponds to a low probability jackpot result with a high probability of winning, and "15 to 29" corresponds to the most favorable jackpot result.

[0239] Only one type of allocation table is provided so that it is common to any of the setting states of "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage in the allocation pattern of the jackpot result from depending on the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity required to previously store the allocation table in the main ROM 64.

[0240] The allocation of jackpot results may be different depending on the settings of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of entering a high-probability mode after a jackpot result. Also, the higher the setting value, the lower the probability of being allocated to a low-prize, high-probability jackpot result, or the higher the setting value, the higher the probability of being allocated to a low-prize, high-probability jackpot result. In this case, the higher the setting value, the higher the probability of the high-frequency winning mode opening / closing execution mode occurring.

[0241] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to increment by one within a range of, for example, 0 to 238, and return to "0" after reaching a maximum value. In the present pachinko machine 10, an expectation effect is set as one type of display effect in the symbol display device 41. In a gaming machine equipped with a symbol display device 41 capable of displaying varying symbols, in which the final stop result in a game round resulting in a predetermined jackpot result is a prize-related result, the expectation effect refers to a display state that makes the player believe that the variable display state is likely to result in the prize-related result from the start of the variable display of symbols on the symbol display device 41 until the stop result is derived and displayed. Specifically, the prize-related result is the display of a combination of symbols with the same number on one of the pay lines.

[0242] There are two types of expectation effects: a reach display and a notice display that is set to anticipate the occurrence of a reach display or a corresponding result before the reach display occurs.

[0243] The reach display includes a display state in which a reach symbol combination is displayed by stopping the display of symbols in some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, a variable display of symbols is performed in the remaining symbol rows. Also included are a reach effect in which, in a state in which a reach symbol combination is displayed as described above, a variable display of symbols is performed in the remaining symbol rows, and a reach effect is performed by displaying predetermined characters or the like as a moving image on the background screen, and a reach effect in which a reach symbol combination is displayed in a reduced size or is not displayed, and then a predetermined character or the like is displayed as a moving image on almost the entire display surface 41a.

[0244] The preview display includes a mode in which a character is displayed separately from the symbols on the symbol row when symbols are displayed variably in all symbol rows or when symbols are displayed variably in some symbol rows after the display of the variable symbols on the display surface 41a of the symbol display device 41 has started. It also includes a mode in which the background screen is displayed in a predetermined mode different from its previous mode, or a mode in which the symbols on the symbol row are displayed in a predetermined mode different from their previous mode. Such a preview display can occur in both game rounds when a reach display is made and when a reach display is not made, but is set to occur with a higher probability when a reach display is made than when a reach display is not made.

[0245] The reach display is executed regardless of the value of the reach random number counter C3 in a game in which the same symbol combination is finally stopped and displayed. Also, in a game in which a jackpot result is reached and the same symbol combination is not stopped and displayed, the reach display is not executed regardless of the value of the reach random number counter C3. Also, in a game in which a miss result is reached, the reach display is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0246] On the other hand, the decision on whether to display a notice is not made by the main control device 60 but by the audio and light emitting control device 81. In this case, the audio and light emitting control device 81 executes a lottery process for the notice display so as to satisfy at least one of the conditions that a notice display is more likely to occur in a game round corresponding to a jackpot result than a game round corresponding to a loss result, and that a notice display with a low occurrence rate is more likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed by the symbol display device 41.

[0247] Here, the probability of a reach display occurring in a game that results in a loss is the same regardless of the setting state of "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage from arising depending on the setting state of the pachinko machine 10 regarding the probability of a reach display occurring in a game that results in a loss. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a loss.

[0248] Next, the variation type counter CS will be explained. The variation type counter CS is configured to be incremented by 1 in sequence within a range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variation type counter CS is used in determining the display duration in the special symbol display unit 37a and the display duration of the symbol in the symbol display device 41 in the main CPU 63. The variation type counter CS is updated once each time the timer interrupt process described below is executed, and is also repeatedly updated within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special symbol display unit 37a and at the start of the variation of the symbol by the symbol display device 41.

[0249] <Regarding the processing configuration of the main CPU 63> Next, we will explain each process executed to progress the game by the main CPU 63. The processes of the main CPU 63 are roughly divided into main processing that is started when the power is turned on, and timer interrupt processing that is started periodically (every 4 millisecond period in this embodiment).

[0250] <Main processing> First, the main processing will be described with reference to the flowchart of FIG.

[0251] In the main process, first, a power-on wait process is executed (step S101). In this power-on wait process, for example, the main process is started and then a predetermined wait time (specifically, 1 second) elapses before proceeding to the next process. During the execution period of this power-on wait process, the operation start and initial setting of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

[0252] Thereafter, it is determined whether the setting key insertion unit 68a has been turned on (step S103). If the setting key insertion unit 68a has not been turned on (step S103: NO), it is determined whether the reset button 68c has been pressed (step S104). If the reset button 68c has been pressed (step S104: YES), each area of ​​the main RAM 65 is cleared to "0" except for the area in which setting value information indicating the setting state of the pachinko machine 10 is set, and the areas cleared to "0" are initialized (step S105). In other words, if the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning on the setting key insertion unit 68a, the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 was stopped, and the clearing process of the main RAM 65 is executed, and the memory area where the clearing process was executed is initialized. This makes it possible to initialize other areas of the main RAM 65 without changing the setting values. In step S105, various registers of the main CPU 63 are also cleared to "0" and then initialized.

[0253] If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power outage process is executed normally, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, that is, the validity of the stored data (step S107). If the process of step S105 is executed or if a positive determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

[0254] If a negative determination is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is executed. The operation prohibition process is released by executing an all-clear process (step S115) described later.

[0255] If the determination is affirmative in all of steps S106 to S108, a power-on setting process is executed (step S110). In the power-on setting process, a predetermined area of ​​the main RAM 65, such as the initialization of the power outage flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81.

[0256] The main CPU 63 is configured to periodically execute timer interrupt processing, but when the main processing starts, the timer interrupt processing is prohibited. This state in which the timer interrupt processing is prohibited is released when the processing of step S110 is completed and before the processing of step S111 is executed, and the execution of the timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 starts, the power-on setting processing of step S110 ends and the timer interrupt processing is not executed until before the processing of step S111 starts. Therefore, the processing for progressing the game in the main CPU 63 is not started until this situation occurs.

[0257] Thereafter, the process proceeds to the remaining process of steps S111 to S114. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S111 to S114. In this respect, the remaining process of steps S111 to S114 can be said to be non-periodic processing that is executed non-periodically.

[0258] In the remaining process, first, in step S111, interrupt prohibition is set to prohibit the occurrence of timer interrupt processing. In the following step S112, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S113, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, current numerical information is read from the corresponding counter in the main RAM 65, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each counter is cleared to "0". Thereafter, in step S114, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted. After the processing of step S114 is executed, the process returns to step S111, and the processing of steps S111 to S114 is repeated.

[0259] On the other hand, if the setting key insertion section 68a is turned ON (step S103: YES), an all-clear process is executed (step S115). In the all-clear process, all areas of the main RAM 65, including the areas in which information on setting values ​​indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0", and initial settings are made for the areas cleared to "0". In other words, when an operation to change the setting state of the pachinko machine 10 is performed, even if the reset button 68c is not pressed, all areas of the main RAM 65 are cleared to "0", and initial settings are made for the storage areas for which the clear process was executed. In addition, in step S115, various registers of the main CPU 63 are also cleared to "0", and then initial settings are made. However, without being limited to this, the configuration may be such that even if an operation to change the setting state of the pachinko machine 10 is being performed, if the reset button 68c is not pressed, the full clear process of the main RAM 65 is not executed, and the full clear process is executed if an operation to change the setting state of the pachinko machine 10 is being performed and the reset button 68c is pressed.

[0260] Thereafter, in step S116, a setting value update process is executed, and then the process proceeds to step S110. In the setting value update process (step S116), first, "1" is set to a setting value counter provided in the main RAM 65. The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting "1" to the setting value counter, when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the setting value up to that point. Thereafter, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the setting value, the manager of the gaming hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c. Thereafter, the update execution process is executed.

[0261] In the update execution process, provided that the setting key insertion section 68a has not been turned OFF, it is determined whether the update button 68b has been pressed once. If the update button 68b has been pressed once, the value of the setting value counter in the main RAM 65 is incremented by one. If the value of the setting value counter after the increment exceeds "6," the setting value counter is set to "1." As a result, the setting value is updated to the next higher setting each time the update button 68b is pressed once. If the setting value counter is set to "6," the setting value returns to "1." In the update execution process, if the setting value counter value is updated, the third notification display device 69c is controlled to display a number corresponding to the setting value counter value in the main RAM 65. By checking the third notification display device 69c, the gaming hall manager can understand the setting status of the pachinko machine 10 after pressing the update button 68b. In the setting value update process (step S116), the update execution process is repeatedly executed until the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the display of the setting value on the third notification display device 69c is terminated, and the setting value update process is terminated.

[0262] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart in Fig. 22. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

[0263] In the timer interrupt process, first, a power outage information storage process is executed (step S201). In the power outage information storage process, it is monitored whether a power outage signal corresponding to the occurrence of a power outage has been received from the power outage monitoring board 67, and if a power outage has been identified, a power outage process is executed and then an infinite loop is entered. In the power outage process, the power outage flag in the main RAM 65 is set to "1", and a checksum is calculated and stored.

[0264] Then, a lottery random number update process is executed (step S202). In the lottery random number update process, the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4 are updated. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power feature release counter C4, and the read numerical information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, it is cleared to "0." Then, in step S203, a random number initial value update process is executed as in step S112, and a variable counter update process is executed as in step S113 in step S204.

[0265] Thereafter, a fraud detection process is executed to monitor whether or not a predetermined event set as a target for fraudulent use has occurred (step S205). In this fraud detection process, the occurrence of multiple types of events is monitored, and if a predetermined event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S206, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S206, the process from step S207 onwards is executed.

[0266] In step S207, port output processing is executed. In the port output processing, if output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to that output information to the various drive units 32b, 34b. For example, if information to switch the special power winning device 32 to an open state is set, output of a drive signal to the special power drive unit 32b is started, and if information to switch to a closed state is set, output of the drive signal is stopped. Also, if information to switch the normal power device 34a of the second operating port 34 to an open state is set, output of a drive signal to the normal power drive unit 34b is started, and if information to switch to a closed state is set, output of the drive signal is stopped.

[0267] Then, a read process is executed (step S208). In the read process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in subsequent processes.

[0268] Thereafter, the ball entry detection process is executed (step S209). In the ball entry detection process, the signals received from the ball entry detection sensors 42a to 49a are read, and based on the read results, it is determined whether or not a ball has entered the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, the second operating hole 34, and the through gate 35.

[0269] Thereafter, a timer update process is executed (step S210) for collectively updating the numerical information of the multiple types of timer counters provided in the main RAM 65. In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtraction type timer counters and the addition type timer counters.

[0270] Thereafter, a launch control process is executed to control the launch of gaming balls (step S211). While the launch operation to the launch operation device 28 continues, one gaming ball is launched at a predetermined launch cycle of 0.6 seconds. In the following step S212, as an input status monitoring process, based on the information read in the reading process of step S208, a disconnection check is performed for each ball entry detection sensor 42a-49a and an opening check is performed for the gaming machine main body 12 and the front door frame 14.

[0271] Thereafter, a special symbol special power control process is executed to control the execution of a game round and the execution of the open / close execution mode (step S213). The special symbol special power control process will be described in detail later.

[0272] Then, a normal map normal power control process is executed (step S214). In the normal map normal power control process, if a winning entry has occurred in the through gate 35, a process is executed to acquire the reserved information on the normal map side, and if the reserved information on the normal map side is stored, an opening judgment is made for the reserved information, and further, a process is executed to perform a normal map performance triggered by the opening judgment. Also, based on the result of the opening judgment, a process is executed to open and close the normal power role 34a of the second operating port 34. In this case, if the support mode is the low frequency support mode, a corresponding process is executed, and if the support mode is the high frequency support mode, a corresponding process is executed. Also, if the opening / closing execution mode is selected, the support mode immediately before will be the low frequency support mode even if it was the high frequency support mode.

[0273] In the following step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to reflect the increase or decrease in the number of reserved information related to the special map display unit 37a in the special map reserved display unit 37b, and output information is set to reflect the increase or decrease in the number of reserved information related to the ordinary map display unit 38a in the ordinary map reserved display unit 38b. Also, in step S215, based on the processing results of the immediately preceding steps S213 and S214, output information is set to update the display contents of the special map display unit 37a, and output information is set to update the display contents of the ordinary map display unit 38a.

[0274] Thereafter, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S216). Also, a payout output process is executed to set the prize ball command as an output target (step S217). Also, an external information setting process is executed to control the start and end of the output of an external signal according to the processing results of the various processes executed in this timer interrupt process (step S218). Thereafter, a management process is executed to display information corresponding to the ball entry results in the game area PA on the first to third notification display devices 69a to 69c (step S219), and this timer interrupt process is terminated.

[0275] <Special diagram special electric control processing> Next, the special picture special power control process in step S213 will be described with reference to the flowchart of FIG.

[0276] First, a process for acquiring reserved information is executed (step S301). In the process for acquiring reserved information, it is determined whether a winning has occurred in the first actuation port 33 or the second actuation port 34. If a winning has occurred, it is determined whether the number of reserved balls in the reserved ball storage area 65a is less than the upper limit ("4" in this embodiment). If the number of reserved balls is less than the upper limit, the number of reserved balls is incremented by one, and the numerical information of the winning random number counter C1, the jackpot type counter C2, and the reach random number counter C3 updated in the previous step S202 is stored in the first reserved area among the empty reserved areas RE1 to RE4 in the reserved ball area RE. Note that if a winning has occurred in both the first actuation port 33 and the second actuation port 34 at the same time, the process for acquiring the reserved information is executed multiple times within the range of one execution of the process for acquiring reserved information. Furthermore, if new reserved information is acquired, a corresponding acquisition command is sent to the sound and light-emitting control device 81. When the audio / light emitting control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to display content corresponding to the increase in pending information items.

[0277] Thereafter, the information of the special picture special power counter provided in the main RAM 65 is read (step S302), and the special picture special power address table provided in the main ROM 64 is read (step S303). Then, a start address corresponding to the information of the special picture special power counter is obtained from the special picture special power address table (step S304), and the process jumps to the process indicated by the obtained start address among the processes of steps S306 to S312 (step S305). The special picture special power counter is a counter that allows the main CPU 63 to grasp which of the various processes of steps S306 to S312 should be executed, and the special picture special power address table has the start address of the program for executing the processes of steps S306 to S312 set in correspondence with the numerical information of the special picture special power counter.

[0278] In step S306, a special chart change start process is executed. Fig. 24 is a flowchart showing the special chart change start process.

[0279] In the special chart change start process, if the number of reserved information items stored in the reserved area RE is one or more (step S401: YES), a data setting process is executed (step S402). In the data setting process, the number of reserved items is first subtracted by one, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, a process is executed to shift the data stored in each of the reserved areas RE1 to RE4 of the reserved area RE. This data shift process shifts the data stored in the first reserved area RE1 to the fourth reserved area RE4 sequentially to the lower areas. Specifically, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, and the fourth reserved area RE4 to the third reserved area RE3, and then the fourth reserved area RE4 is cleared to "0." At this time, a shift command is sent to the audio and light-emitting control device 81 to acknowledge that the data in the reserved areas has been shifted. When the audio / light emitting control device 81 receives this command, it updates the image displayed on the pattern display device 41, which indicates the number of pending information items, to a display content corresponding to the reduction in pending information items.

[0280] After the data setting process is executed, the win / loss table is read from the win / loss table storage area 64a of the main ROM 64 (step S403). As already explained, the win / loss table storage area 64a stores the low-probability win / loss table for setting 1 to the low-probability win / loss table for setting 6 and the high-probability win / loss table as win / loss tables. In step S403, first, the current win / loss lottery mode is determined by reading information indicating the win / loss lottery mode from the main RAM 65. If it is the high-probability mode, the high-probability win / loss table is read from the win / loss table storage area 64a. On the other hand, if it is the low-probability mode, the setting state of the pachinko machine 10 is determined by reading the value of the setting value counter in the main RAM 65. Then, the low-probability win / loss table corresponding to the determined setting value is read from the win / loss table storage area 64a.

[0281] Thereafter, the winning / losing table read in step S403 is referenced to execute the winning / losing determination process (step S404). In the winning / losing determination process, it is determined whether or not the winning / losing determination information stored in the execution area AE, i.e., the numerical information related to the winning random number counter C1, matches the jackpot numerical information set in the winning / losing table read in step S403.

[0282] If the result of the win / loss determination process is a jackpot winning result (step S405: YES), an allocation determination process is executed (step S406). In the allocation determination process, information for allocation determination from the information stored in the execution area AE, i.e., numerical information related to the jackpot type counter C2, is read out. Then, by referring to the allocation table provided in the allocation table storage area 64b of the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out corresponds to. Specifically, it is determined which jackpot result it corresponds to: a low-probability jackpot result, a low-prize-winning high-probability jackpot result, or a most advantageous jackpot result.

[0283] Thereafter, a stop result setting process for the jackpot result is executed (step S407). Specifically, information on the form of the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the form of the pattern to be stopped and displayed on the special symbol display unit 37a is set differently for each type of jackpot result.

[0284] Thereafter, a flag set process corresponding to the distribution determination result is executed (step S408). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S408, the flag corresponding to the result of the distribution determination process in step S406 is set to "1".

[0285] On the other hand, if it is determined in step S405 that the result is not a jackpot, a stop result setting process for a loss result is executed (step S409). Specifically, information on the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for a loss result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern pattern selected in this case is different from the information on the pattern pattern selected in the case of a jackpot result.

[0286] After executing either the process of step S408 or step S409, a process for determining the duration of the game round is executed (step S410). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is determined whether or not a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation results in a low probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. Also, if neither of the jackpot results are obtained and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

[0287] If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. Incidentally, the duration of the game round that can be obtained by reference to the reach non-occurrence duration table is different from the duration of the game round that can be obtained by reference to the reach occurrence duration table.

[0288] The duration of game plays when a reach does not occur is set so that the greater the number of reserved information stored in the reserved area RE, the shorter the duration of game plays. Furthermore, the non-reach duration table is set so that a shorter duration of game plays is selected when the support mode is in high-frequency support mode than when it is in low-frequency support mode, when the number of reserved information is the same. However, this is not limited to this, and the duration of game plays may not vary depending on the number of reserved information or the support mode, or the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of game plays when a reach occurs. Furthermore, separate duration tables may be set for various jackpot results, miss reach results, and miss results without a reach occurrence. In this case, the duration of game plays is allocated according to each game result.

[0289] Then, the information on the duration of the game acquired in step S410 is set in the special symbol special power timer counter provided in the main RAM 65 (step S411). The numerical information set in the special symbol special power timer counter is updated in the timer update process (step S210). Incidentally, as a performance for a game, the variable display of the pattern on the special symbol display unit 37a and the variable display of the pattern on the pattern display device 41 are performed, and when each of these variable displays is completed, the stop result of that game is displayed (in the pattern display device 41, a predetermined combination of patterns is waiting on the active line) and the final stop is displayed for the final stop period (for example, 0.5 seconds). In this case, the duration of the game acquired in step S410 is the total time for one game.

[0290] Thereafter, the variation command and the type command are transmitted to the audio and light emitting control device 81 (step S412). The variation command includes information on the duration of the game rounds. Here, as described above, the duration of the game rounds acquired by referring to the non-reach duration table is different from the duration of the game rounds acquired by referring to the reach occurrence duration table. Therefore, even if the variation command does not include information on whether or not a reach has occurred, the audio and light emitting control device 81 can determine whether or not a reach has occurred from the information on the duration of the game rounds. In this regard, it can be said that the variation command includes information indicating whether or not a reach has occurred. Note that the variation command may also include information directly indicating whether or not a reach has occurred. Furthermore, the type command includes information on the game result.

[0291] When the sound and light emission control device 81 receives the variation command and the type command from the main CPU 63, it causes the decorative boards 56, 57, the speaker unit 53, and the symbol display device 41 to execute the effect for the game round. In this case, the effect for the game round is executed in a manner corresponding to the contents of the variation command and the type command. In addition, the symbol display device 41 displays a variation of the symbol as the effect for the game round, and when the effect for the game round ends, a combination of symbols corresponding to the results of the win / loss determination process and the allocation determination process is displayed in a stopped state.

[0292] Thereafter, the display of the changing pattern in the special pattern display unit 37a is started (step S413). Then, the special pattern special power counter is incremented by 1 (step S414), and the special pattern change start process is terminated. When the special pattern change start process is executed, the numerical information of the special pattern special power counter is "0". By adding "1" in step S414, the numerical information of the special pattern special power counter becomes "1".

[0293] Returning to the explanation of the special symbol special power control process (FIG. 23), in step S307, special symbol variation process is executed. In the special symbol variation process, it is determined whether or not it is during the duration of the game round and before the final stop display, and if it is before the final stop display, a process is executed to regularly change the display mode of the image in the special symbol display unit 37a. When it is time to display the final stop, the numerical information of the special symbol special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special symbol variation process to that corresponding to the special symbol determination process. Note that in this embodiment, a final stop command is not sent from the main CPU 63 to the audio and light emission control device 81.

[0294] In step S308, a special symbol determination process is executed. In the special symbol determination process, the display mode of the image on the special symbol display unit 37a is set to a display mode corresponding to the lottery result of the current game round. In addition, in the special symbol determination process, it is determined whether the final stop period has elapsed, and if the period has elapsed, it is determined whether a transition to the opening and closing execution mode will occur. If a transition to the opening and closing execution mode does not occur, the numerical information of the special symbol special power counter is cleared to "0." If a transition to the opening and closing execution mode occurs, the numerical information of the special symbol special power counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special symbol determination process to that corresponding to the special power start process.

[0295] In step S309, the special power start process is executed. If the process for starting the opening period in the current opening / closing execution mode has not yet been executed in the special power start process, the process for setting the opening period is executed. An opening command is also sent to the audio / light emitting control device 81. Upon receiving the opening command, the audio / light emitting control device 81 causes the decorative boards 56 and 57, the speaker unit 53, and the symbol display device 41 to execute an opening effect. If the opening period has elapsed, a start process is executed to start the first round of play. In this start process, the special power winning device 32 is set to an open state and the end conditions for the round of play are set. When setting this end condition, the upper limit of the duration for which the special power winning device 32 is to remain open in the current first round of play is set, and the upper limit of the number of game balls that can win the special power winning device 32 in the current first round of play is set in the winning number counter provided in the main RAM 65.

[0296] In step S310, special line open processing is executed. In the special line open processing, it is determined whether the end condition for the round game has been met. If the end condition has been met, the special line winning device 32 is closed. Then, if the round game that has just finished is not the last round game executed, the numerical information of the special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line closed processing. If the round game that just finished is the last round game executed, the numerical information of the special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line end processing.

[0297] In step S311, special line closed processing is executed. In the special line closed processing, it is determined whether or not the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. If the interval period has elapsed, the special line winning device 32 is set to an open state and the end conditions for the round of play are set. Then, by subtracting 1 from the numerical information of the special chart special line counter, the numerical information of the counter is updated from that corresponding to the special line closed processing to that corresponding to the special line open processing.

[0298] In step S312, special call termination processing is executed. In the special call termination processing, if the processing to start the ending period in this opening / closing execution mode has not yet been executed, the ending period (for example, 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. By receiving the ending command, the sound and light emission control device 81 causes the decorative boards 56, 57, speaker unit 53, and pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win / lose lottery mode and support mode after the end of the opening / closing execution mode are set to modes corresponding to the jackpot result that triggered the start of this opening / closing execution mode.

[0299] According to the present embodiment described above in detail, the following excellent effects are achieved.

[0300] On the first decorative substrate 56, the same number (specifically, two) of wiring patterns 172a to 172d are drawn out from a pair of pads 171a, 171b corresponding to a pair of electrodes 85a, 85b of the bypass capacitor 85. The direction (rightward) of the four sides of the first pad 171a from which the first wiring pattern 172a is drawn out is the same as the direction (rightward) of the four sides of the second pad 171b from which the third wiring pattern 172c is drawn out as viewed from the center of the second pad 171b. Furthermore, the direction (leftward) of the four sides of the first pad 171a from which the second wiring pattern 172b is drawn out is the same as the direction (leftward) of the four sides of the second pad 171b from which the fourth wiring pattern 172d is drawn out as viewed from the center of the second pad 171b. This makes it possible to prevent a difference in temperature distribution between the pair of pads 171a and 171b in the initial heating stage of the reflow process, and also to prevent the bypass capacitor 85 from rotating and becoming a standing chip.

[0301] The bypass capacitor 85 is a small chip component with a longitudinal dimension of approximately 0.6 mm and lateral and thickness dimensions of approximately 0.3 mm. By having the longitudinal dimension of the bypass capacitor 85 along a plane perpendicular to the thickness direction be 0.7 mm or less, the area occupied by the bypass capacitor 85 on the first decorative substrate 56 can be reduced. By having the longitudinal dimension of the bypass capacitor 85 be 0.4 mm or more, the mechanical strength of the connection between the bypass capacitor 85 and the first decorative substrate 56 and the mechanical strength of the bypass capacitor 85 itself can be increased, reducing the possibility of damage to the connection and the bypass capacitor 85 itself. Furthermore, by having the longitudinal dimension of the bypass capacitor 85 be 0.4 mm or more, the accuracy of visually checking for missing bypass capacitors 85 can be improved.

[0302] In a configuration in which the same number of wiring patterns 181a, 181b (specifically, one) are drawn out from a pair of pads 176a, 176b corresponding to a pair of electrodes 87a, 87b of a miniature chip resistor 87, the direction (rightward) of the side from which the first wiring pattern 181a is drawn out of the four sides of the first pad 176a as viewed from the center of the first pad 176a is the same direction (rightward) as the direction (rightward) of the side from which the second wiring pattern 181b is drawn out of the four sides of the second pad 176b as viewed from the center of the second pad 176b. This prevents differences in temperature distribution within the pair of pads 176a, 176b during the initial heating stage of the reflow process, and prevents rotation of the miniature chip resistor 87 and chip standing.

[0303] Like the bypass capacitor 85, the small chip resistor 87 is a small chip component whose longitudinal dimension along a plane perpendicular to the thickness direction of the component (the longitudinal dimension of the small chip resistor 87) is 0.1 mm or more and 0.9 mm or less. The small chip resistor 87 is a small chip component whose longitudinal dimension is approximately 0.6 mm and whose lateral and thickness dimensions are approximately 0.3 mm. Since the longitudinal dimension of the small chip resistor 87 is 0.7 mm or less, the area occupied by the small chip resistor 87 on the first decorative substrate 56 can be reduced. Since the longitudinal dimension of the small chip resistor 87 is 0.4 mm or more, the mechanical strength of the connection between the small chip resistor 87 and the first decorative substrate 56 and the mechanical strength of the small chip resistor 87 itself can be increased, reducing the possibility of damage to the connection and the possibility of damage to the small chip resistor 87 itself. Furthermore, by making the longitudinal dimension of the small chip resistor 87 0.4 mm or more, it is possible to improve the accuracy of visually checking whether or not there is any missing mounting of the small chip resistor 87.

[0304] The first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is electrically connected to the GND plane layer 93, which has a larger area than the first pad 171a, via the first wiring pattern 172a, and the second pad 171b corresponding to the second electrode 85b of the bypass capacitor 85 is electrically connected to the power supply plane layer 94, which has a larger area than the second pad 171b, via the third wiring pattern 172c. The direction (rightward) of the side from which the first wiring pattern 172a is drawn out, among the four sides of the first pad 171a, as viewed from the center of the first pad 171a, is the same direction (rightward) as the direction (rightward) of the side from which the third wiring pattern 172c is drawn out, among the four sides of the second pad 171b, as viewed from the center of the second pad 171b. This reduces the possibility of differences in temperature distribution occurring within the pair of pads 171a, 171b, during the initial heating stage of the reflow process.

[0305] The width of the first wiring pattern 172a extending from the first pad 171a corresponding to the first electrode 85a of the bypass capacitor 85 is substantially the same as the width of the third wiring pattern 172c extending from the second pad 171b corresponding to the second electrode 85b. This reduces the possibility of a difference in temperature distribution within the pair of pads 171a and 171b during the initial heating stage of the reflow process, compared to a configuration in which the widths of the wiring patterns 172a and 172c are different. Furthermore, the width of the second wiring pattern 172b extending from the first pad 171a is substantially the same as the width of the fourth wiring pattern 172d extending from the second pad 171b. This reduces the possibility of a difference in temperature distribution within the pair of pads 171a and 171b during the initial heating stage of the reflow process, compared to a configuration in which the widths of the wiring patterns 172b and 172d are different.

[0306] The width of the first wiring pattern 181a drawn from the first pad 176a corresponding to the first electrode 87a of the small chip resistor 87 is approximately the same as the width of the second wiring pattern 181 drawn from the second pad 176b corresponding to the second electrode 87b. Therefore, compared to a configuration in which the widths of the wiring patterns 181a, 181b drawn from the pads 176a, 176b are different, the possibility of a difference in temperature distribution occurring within the pair of pads 176a, 176b in the initial heating stage of the reflow process is reduced.

[0307] Because the number and positions of the wiring patterns 172a-172d drawn from the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 are the same, it is possible to balance the force acting on the first electrode 85a of the bypass capacitor 85 due to the surface tension of the molten solder on the first pad 171a and the force acting on the second electrode 85b of the bypass capacitor 85 due to the surface tension of the molten solder on the second pad 171b. Therefore, even if only the left portion of the solder paste melts first on the pair of pads 171a, 171b, the bypass capacitor 85 moves in a parallel movement, preventing rotation of the bypass capacitor 85. This makes it possible to suppress the degree of reduction in the connection area due to the solder fillet 173a between the first pad 171a and the first electrode 85a, and to suppress the degree of reduction in the connection area due to the solder fillet 173b between the second pad 171b and the second electrode 85b.

[0308] Because the number and lead-out positions of the wiring patterns 181a, 181b drawn out from the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the miniature chip resistor 87 are standardized, it is possible to balance the force acting on the first electrode 87a of the miniature chip resistor 87 due to the surface tension of the molten solder on the first pad 176a and the force acting on the second electrode 87b of the miniature chip resistor 87 due to the surface tension of the molten solder on the second pad 176b. Therefore, even if only the left side portions of the solder paste on the pair of first pad 176a and second pad 176b melt first, the movement of the miniature chip resistor 87 is kept parallel, and rotation of the miniature chip resistor 87 can be prevented. This makes it possible to suppress the degree of reduction in the connection area between the first pad 176a and the first electrode 87a due to the solder fillet 177a, and also to suppress the degree of reduction in the connection area between the second pad 176b and the second electrode 87b due to the solder fillet 177b.

[0309] The small chip components (bypass capacitors 85 and small chip resistors 87) are mounted on the first decorative substrate 56 with their longitudinal directions parallel to the first direction DR1. The dimension of the first decorative substrate 56 in the first direction DR1 is greater than the dimension of the first decorative substrate 56 in a second direction DR2 perpendicular to the first direction DR1. If the small chip components are mounted on the first decorative substrate 56 with their longitudinal directions perpendicular to the first direction DR1, when a force that bends the first decorative substrate 56 about a boundary line extending in the first direction DR1 acts on the first decorative substrate 56, stress that may damage the connection points between the small chip components and the first decorative substrate 56 may act on the small chip components themselves. In contrast, by configuring the small chip components so that their longitudinal directions are perpendicular to the first direction DR1 and mounted on the first decorative substrate 56, the maximum value of stress that can act on the connection points between the small chip components and the first decorative substrate 56 is reduced, and the maximum value of stress that can act on the small chip components is also reduced. Therefore, damage to the connection points between the small chip components and the first decorative substrate 56 is prevented, and damage to the small chip components themselves is also prevented.

[0310] The small chip components (bypass capacitors 97 and small chip resistors 101) are mounted on the second decorative substrate 57 so that their longitudinal directions are parallel to the long axis direction LD. The dimension of the second decorative substrate 57 in the long axis direction LD is greater than the dimension of the second decorative substrate 57 in the short axis direction SD, which is perpendicular to the long axis direction LD. If the small chip components are mounted on the second decorative substrate 57 so that their longitudinal directions are perpendicular to the long axis direction LD, when a force that bends the second decorative substrate 57 about a boundary line extending in the long axis direction LD acts on the second decorative substrate 57, stress that may damage the connection points between the small chip components and the second decorative substrate 57 may be applied, and stress that may damage the small chip components themselves may be applied. In contrast, by mounting the small chip components on the second decorative substrate 57 so that the longitudinal direction of the small chip components is perpendicular to the long axis direction LD, the maximum value of stress that can act on the connection points between the small chip components and the second decorative substrate 57 is reduced, and the maximum value of stress that can act on the small chip components is also reduced. Therefore, damage to the connection points between the small chip components and the second decorative substrate 57 is prevented, and damage to the small chip components themselves is also prevented.

[0311] Electrodes 85a and 85b of the bypass capacitor 85 are fixed to pads 171a and 171b by solder fillets 173a and 173b. The pads 171a and 171b and wiring patterns 172a to 172d are integrally formed by etching a copper foil plate. The wiring patterns 172a to 172d drawn out from the pads 171a and 171b extend in a direction perpendicular to or substantially perpendicular to the longitudinal direction of the bypass capacitor 85 (the short-side direction). If the wiring patterns 172a-172d drawn from the pads 171a, 171b are configured to extend in a direction parallel to the longitudinal direction of the bypass capacitor 85, when distortion of the first decorative substrate 56 occurs in a direction in which the first decorative substrate 56 is bent from a boundary line perpendicular or substantially perpendicular to the long side direction of the bypass capacitor 85 as a base point, stress that may damage the connection between the bypass capacitor 85 and the first decorative substrate 56 may act on the connection, and stress that may damage the bypass capacitor 85 itself may act on the bypass capacitor 85. In contrast, by configuring the wiring patterns 172a-172d drawn from the pads 171a, 171b to extend in a direction perpendicular or substantially perpendicular to the longitudinal direction of the bypass capacitor 85, it is possible to reduce the maximum value of stress that may act on the connection between the bypass capacitor 85 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56, and also to reduce the maximum value of stress that may act on the bypass capacitor 85 itself.

[0312] The electrodes 87a and 87b of the small chip resistor 87 are fixed to the pads 176a and 176b by solder fillets 177a and 177b. The pads 176a and 176b and the wiring patterns 181a and 181b are integrally formed by etching a copper foil plate. The wiring patterns 181a and 181b drawn from the pads 176a and 176b extend in a direction perpendicular to or substantially perpendicular to the longitudinal direction of the small chip resistor 87 (the short side direction). If the wiring patterns 181a, 181b drawn out from the pads 176a, 176b are configured to extend in a direction parallel to the longitudinal direction of the small chip resistor 87, when a bending stress acts on the first decorative substrate 56 so as to bend the first decorative substrate 56 at a boundary of a line perpendicular or approximately perpendicular to the long side direction of the small chip resistor 87, there is a risk that stress will act on the connection point between the small chip resistor 87 and the first decorative substrate 56, causing the connection point to be damaged, and there is also a risk that stress will act on the small chip resistor 87 itself, causing the small chip resistor 87 to be damaged. In contrast, by configuring the wiring patterns 181a, 181b drawn out from the pads 176a, 176b to extend in a direction perpendicular or approximately perpendicular to the longitudinal direction of the small chip resistor 87, the maximum amount of stress that can act on the connection point between the small chip resistor 87 and the first decorative substrate 56 when distortion occurs in the first decorative substrate 56 can be reduced, and the maximum amount of stress that can act on the small chip resistor 87 itself can be reduced.

[0313] The first pad 176a electrically connected to the first electrode 87a of the small chip resistor 87 is electrically connected via the first wiring pattern 181a to the second pad 178b electrically connected to the second electrode 142b of the LED chip 142 (see FIG. 8(c)). Furthermore, the second pad 176b electrically connected to the second electrode 87b of the small chip resistor 87 is electrically connected via the second wiring pattern 181b to a pad (not shown) electrically connected to the eighth output terminal 162 (FIG. 11) of the LED driver 126 (FIG. 8(a)). When viewed in a direction of one axis (second direction DR2 in FIGS. 8A and 8C) including the direction in which the second wiring pattern 181b is drawn from the second pad 176b (rightward in FIGS. 8A and 8C), the location to which the second wiring pattern 181b is connected in the pad (not shown) corresponding to the eighth output terminal 162 is located in the opposite direction from the direction in which the second wiring pattern 181b is drawn from the second pad 176b. The second wiring pattern 181b is drawn from the second pad 176b in the same direction (rightward) as the direction in which the first wiring pattern 181a is drawn from the first pad 176a, and then routed in the opposite direction from the second pad 176b when viewed in the direction of the one axis (second direction DR2). Even in a configuration in which the second wiring pattern 181b is connected to a connection destination at a location that is opposite to the direction in which the second wiring pattern 181b is drawn from the second pad 176b, with the second pad 176b as the reference, when viewed in one axis direction (second direction DR2), the second wiring pattern 181b is drawn from the second pad 176b in the same direction as the direction in which the first wiring pattern 181a is drawn from the first pad 176a. This reduces the possibility of a difference in temperature distribution occurring within the pair of first pad 176a and second pad 176b in the initial heating stage of the reflow process.

[0314] The pair of pads corresponding to the pair of electrodes of the small chip component are identical in shape and size. Therefore, the amount of solder paste applied to the pair of pads during the solder application process can be made uniform, and the amount of molten solder generated on the pair of pads can also be made uniform. This allows for a balance between the force acting on the first electrode of the small chip component due to the surface tension of the molten solder on the first pad and the force acting on the second electrode of the small chip component due to the surface tension of the molten solder on the second pad. This prevents the small chip component from rotating and standing up.

[0315] The bypass capacitor 85 is mounted on the first decorative substrate 56 so that the longitudinal direction of the bypass capacitor 85 is parallel to the first direction DR1. A pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 are spaced apart in the longitudinal direction of the bypass capacitor 85. The small chip resistor 87 is mounted on the first decorative substrate 56 so that the longitudinal direction of the small chip resistor 87 is parallel to the first direction DR1. A pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 are spaced apart in the longitudinal direction of the small chip resistor 87. In this way, the spacing direction of the pair of pads 176a, 176b is common in multiple small chip components (bypass capacitors 85 and small chip resistors 87). Therefore, by transporting the first decorative substrate 56 in a direction perpendicular or substantially perpendicular to the common separation direction in the reflow process, it is possible to synchronize the timing at which heating of the solder paste applied to the pair of pads 171a, 171b corresponding to the pair of electrodes 85a, 85b of the bypass capacitor 85 starts, and it is also possible to synchronize the timing at which heating of the solder paste applied to the pair of pads 176a, 176b corresponding to the pair of electrodes 87a, 87b of the small chip resistor 87 starts. This makes it possible to prevent rotation of the multiple small chip components and the occurrence of chip standing.

[0316] In a configuration in which small chip components (bypass capacitors 85 and small chip resistors 87) are concentrated on the first mounting surface 84 of the first decorative substrate 56, the connectors 111, 112 are mounted only on the second mounting surface 95 of the first decorative substrate 56. On the first mounting surface 84, the small chip components are arranged to avoid the connector backside corresponding areas 203, 204 (the area of ​​the first mounting surface 84 corresponding to the area on the second mounting surface 95 where the connectors 111, 112 are mounted and the surrounding area). This reduces the maximum tensile stress that can act on the connection points between the small chip components and the first decorative substrate 56 when attaching a harness to the connectors 111, 112, and also reduces the maximum tensile stress that can act on the small chip components themselves. Furthermore, when removing the harness from the connectors 111, 112, it reduces the maximum compressive stress that can act on the connection points between the small chip components and the first decorative substrate 56, and also reduces the maximum compressive stress that can act on the small chip components themselves.

[0317] In the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are positioned at a distance of 5 mm or more from the outer edges of the fixing through holes 56d-56g. No small chip components are mounted in the through hole peripheral areas 211a-211d. By positioning the small chip components at a distance of 5 mm or more from the outer edges of the fixing through holes 56d-56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56 due to distortion of the first decorative substrate 56 that may occur near the fixing through holes 56d-56g when the first decorative substrate 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

[0318] No small chip components are mounted in the LED backside corresponding area 201 on the second mounting surface 95 of the first decorative substrate 56. The LED backside corresponding area 201 is the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED chips 127-142 are mounted, and is within 1 mm of the outer edge of the area of ​​the second mounting surface 95. By not mounting small chip components in the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED chips 127-142 are mounted, the impact of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED chips 127-142 on the small chip components is reduced. By mounting the small chip components away from the LED backside corresponding area 201, damage to the connections between the small chip components and the first decorative substrate 56 caused by repeated lighting effects on the first decorative substrate 56 can be prevented, and damage to the small chip components themselves can also be prevented.

[0319] No small chip components are mounted in the driver backside corresponding area 202 of the second mounting surface 95. The driver backside corresponding area 202 is an area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED driver 126 is mounted and where the pads corresponding to the terminals of the LED driver 126 are provided, and is an area within 1 mm from the outer edge of the area of ​​the second mounting surface 95. By not mounting small chip components in the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED driver 126 is mounted and where the pads corresponding to the terminals of the LED driver 126 are provided, the impact of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED driver 126 on the small chip components is reduced. Mounting the small chip components away from the driver backside corresponding area 202 prevents damage to the connections between the small chip components and the first decorative substrate 56 due to repeated lighting effects on the first decorative substrate 56, and also prevents damage to the small chip components themselves.

[0320] On the first decorative substrate 56, the small chip components (bypass capacitor 85 and small chip resistor 87) are arranged at a distance of 1 mm or more from the outer edge of the LED chip 142. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to minimize the effect of thermal stress on the connection points between the small chip components and the first decorative substrate 56, and it is also possible to minimize the effect of thermal stress on the small chip components themselves. Furthermore, by arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED chip 142, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

[0321] On the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87) are arranged at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126. By arranging the small chip components at a distance of 1 mm or more from the outer edge of the LED driver 126 and the pads corresponding to the terminals of the LED driver 126, it is possible to prevent the connection points between the small chip components and the first decorative substrate 56 from being damaged by thermal stress, and it is also possible to prevent the small chip components themselves from being damaged by thermal stress.

[0322] In the first decorative substrate 56, the small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through hole peripheral areas 211a-211d. The through hole peripheral areas 211a-211d are areas that are less than 5 mm away from the outer edges of the fixing through holes 56d-56g. By arranging the small chip components at least 5 mm away from the outer edges of the fixing through holes 56d-56g, it is possible to prevent damage to the connection points between the small chip components and the first decorative substrate 56 due to distortion of the first decorative substrate 56 that may occur near the fixing through holes 56d-56g when the first decorative substrate 56 is screwed to the front door frame 14, and it is also possible to prevent damage to the small chip components themselves.

[0323] On the first mounting surface 84, the small chip components are arranged to avoid the connector backside corresponding regions 203, 204. The connector backside corresponding regions 203, 204 are regions of the first mounting surface 84 located behind the region on the second mounting surface 95 where the connectors 111, 112 are mounted, and regions that are less than 5 mm away from the outer edge of the region of the first mounting surface 84. Since small chip components are not mounted in the region of the first mounting surface 84 located behind the region on the second mounting surface 95 where the connectors 111, 112 are mounted, the impact of stress that may act on the first decorative substrate 56 when attaching or detaching a harness to the connectors 111, 112 on the small chip components is reduced. Since the small chip components are arranged to avoid the connector backside corresponding regions 203, 204, damage to the connection points between the small chip components and the first decorative substrate 56 and damage to the small chip components themselves are prevented when attaching or detaching a harness to the connectors 111, 112.

[0324] The LED driver 126 is disposed in an area less than 10 mm from the outer edge of the first decorative substrate 56, while the small chip components (bypass capacitor 85 and small chip resistors 87, 143-149 (FIG. 11)) are disposed 10 mm or more away from the outer edge of the first decorative substrate 56. Among the various electronic components mounted on the first decorative substrate 56, the connection points between the small chip components and the first decorative substrate 56 have lower mechanical strength than the connection points between other electronic components and the first decorative substrate 56. By disposing the small chip components 10 mm or more away from the outer edge of the first decorative substrate 56, the possibility of damage to the connection points between the small chip components and the first decorative substrate 56 due to a worker's hand touching the small chip components when handling the first decorative substrate 56 is reduced, and the possibility of damage to the small chip components themselves is also reduced. Furthermore, when the aggregate substrate 231 is divided, the maximum value of stress that can act on the connection points between the small chip components and the first decorative substrate 56 is reduced, and the maximum value of stress that can act on the small chip components themselves is also reduced.

[0325] In a configuration in which small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are arranged to avoid the through-hole peripheral areas 211a-211d and areas less than 10 mm away from the outer edge of the first decorative substrate 56, the fixing through holes 56d-56g are provided in areas less than 10 mm away from the outer edge of the first decorative substrate 56. Therefore, compared to a configuration in which the fixing through holes 56d-56g are provided at positions 10 mm or more away from the outer edge of the first decorative substrate 56, a larger area is secured on the first decorative substrate 56 in which small chip components can be mounted.

[0326] A bypass capacitor 85 is disposed between the power supply terminal 151 of the LED driver 126 and the power supply plane layer 94. This reduces the effect on the LED driver 126 of noise components contained in the driving power supplied from the audio and light-emitting control device 81 to the LED driver 126. The bypass capacitor 85 is disposed close to the power supply terminal 151 so that no other electronic components, such as ICs, are present between the bypass capacitor 85 and the power supply terminal 151. This increases the likelihood that noise components contained in the driving power supplied to the power supply terminal 151 of the LED driver 126 will be absorbed by the bypass capacitor 85 and reduces the likelihood that the LED driver 126 will malfunction due to the influence of the noise components. Because no other ICs are present between the bypass capacitor 85 and the power supply terminal 151, noise components generated by the LED driver 126 are absorbed by the bypass capacitor 85, preventing the noise components from causing malfunction of other ICs. Furthermore, since there are no other electronic components between the bypass capacitor 85 and the power supply terminal 151, the noise components generated by the LED driver 126 are absorbed by the bypass capacitor 85, preventing the noise components from causing other electronic components to malfunction.

[0327] Only an identification silk 217 (marked "C1") is provided around the bypass capacitor 85 to confirm that the mounted electronic component is the bypass capacitor 85; no outline silk is provided to identify the location of the bypass capacitor 85. The external dimensions (length, width, and height) of the bypass capacitor 85 are smaller than those of electronic components other than small chip components (such as the LED driver 126 and LED chips 127-142). Therefore, if the outline silk of the bypass capacitor 85 is printed on the first decorative board 56, there is a risk that a worker may mistakenly believe that the bypass capacitor 85 is installed by looking only at the outline silk, even though the bypass capacitor 85 is actually missing after the electronic components are mounted. In contrast, by not providing an outline silk around the bypass capacitor 85, it is easier to identify the missing bypass capacitor 85 after the electronic components are mounted. Furthermore, the identification silk 217 around the bypass capacitor 85 makes it possible to identify that the component mounted around the identification silk 217 is the bypass capacitor 85.

[0328] The external dimensions of the miniature chip resistor 87, like those of the bypass capacitor 85, are smaller than those of electronic components other than miniature chip components. Only an identification silk 218 (marked "R8") is provided around the miniature chip resistor 87 to enable confirmation that the mounted electronic component is a miniature chip resistor 87, and no outline silk is provided to enable confirmation of the mounting position of the miniature chip resistor 87. This makes it easier to identify any missing miniature chip resistors 87. Furthermore, by providing the identification silk 218 around the miniature chip resistor 87, it becomes possible to identify that the electronic component mounted around the identification silk 218 is a miniature chip resistor 87.

[0329] Because the outer silks 225a and 225b are convex relative to the surface of the solder resist 222, if the outer silks 225a and 225b are provided around the small chip components (bypass capacitors 85 and small chip resistors 87), the outer silks 225a and 225b will be present between the first mounting surface 84 and the metal mask 226, increasing the distance between the first mounting surface 84 and the metal mask 226. In this configuration, there is a risk that the solder paste 227 will find its way into the gaps between the first pads 171a and the second pads 171b, electrically connecting the first pads 171a and the second pads 171b. In particular, when the solder paste 221 is applied continuously to multiple first decorative substrates 56, the solder paste 221 accumulated at the edges of the openings in the metal mask 226 will easily find its way behind the openings, easily electrically connecting the first pads 171a and the second pads 171b. In contrast, in this embodiment, no outline silk is provided around the small chip components. This prevents the distance between the first mounting surface 84 and the metal mask 226 from becoming too large, and also prevents soldering defects caused by the solder paste 221 getting between the pads 171a and 171b. It also prevents parts of the small chip components from resting on the outline silk, which could cause soldering defects.

[0330] The LED backside corresponding area 201 on the second mounting surface 95 of the first decorative substrate 56 where no small chip components are mounted is not limited to the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 (FIG. 8(a)) where the LED chips 127-142 (FIG. 9) are mounted, or the area within 1 mm from the outer edge of the second mounting surface 95. The LED backside corresponding area 201 may also be the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED chips 127-142 are mounted, or the area within 2 mm from the outer edge of the second mounting surface 95. This further reduces the impact on the small chip components of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED chips 127-142. This reduces the possibility of damage to the connection between the small chip components and the first decorative substrate 56 caused by repeated light-emitting effects on the first decorative substrate 56, as well as the possibility of damage to the small chip components themselves.

[0331] The driver backside corresponding area 202 on the second mounting surface 95 of the first decorative substrate 56, where no small chip components are mounted, is not limited to the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 (FIG. 8(a)) where the LED driver 126 (FIG. 8(a)) is mounted and the area where the pads corresponding to the terminals of the LED driver 126 are provided, or the area within 1 mm from the outer edge of the area of ​​the second mounting surface 95. The driver backside corresponding area 202 may also be the area of ​​the second mounting surface 95 located behind the area on the first mounting surface 84 where the LED driver 126 is mounted and the area where the pads corresponding to the terminals of the LED driver 126 are provided, or the area within 2 mm from the outer edge of the area of ​​the second mounting surface 95. This further reduces the impact on the small chip components of thermal stress that may act on the first decorative substrate 56 due to heat generated by the LED driver 126. Therefore, the possibility of the connection point between the small chip component and the first decorative substrate 56 being damaged due to the repeated execution of the light-emitting effect on the first decorative substrate 56 can be reduced, and the possibility of the small chip component itself being damaged can also be reduced.

[0332] In the first decorative substrate 56, the through-hole peripheral areas 211a-211d where small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (FIG. 11)) are not mounted are not limited to areas less than 5 mm away from the outer edges of the fixing through holes 56d-56g. The through-hole peripheral areas 211a-211d may be areas less than 7 mm away from the outer edges of the fixing through holes 56d-56g. This reduces the possibility of damage to the connections between the small chip components and the first decorative substrate 56 due to distortion of the first decorative substrate 56 that may occur near the fixing through holes 56d-56g when the first decorative substrate 56 is screwed to the front door frame 14, and also reduces the possibility of damage to the small chip components themselves. The through-hole peripheral areas 211a-211d may be areas less than 4 mm away from the outer edges of the fixing through holes 56d-56g. This reduces the stress acting on the connection point between the small chip components and the first decorative substrate 56 and the stress acting on the small chip components themselves when the first decorative substrate 56 is screwed to the front door frame 14, while ensuring a large area on the first decorative substrate 56 where small chip components can be mounted.

[0333] On the first mounting surface 84 of the first decorative substrate 56, the connector backside corresponding areas 203, 204 where small chip components are not mounted are not limited to areas of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95 (FIG. 15(a)) or areas that are less than 5 mm away from the outer edge of the area of ​​the first mounting surface 84. The connector backside corresponding areas 203, 204 may also be areas of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95 or areas that are less than 7 mm away from the outer edge of the area of ​​the first mounting surface 84. This reduces the possibility of damage to the connection points between the small chip components and the first decorative substrate 56 when attaching or detaching a harness to the connectors 111, 112, and also reduces the possibility of damage to the small chip components themselves. Furthermore, the connector backside corresponding areas 203, 204 may be areas of the first mounting surface 84 located on the back side of the area where the connectors 111, 112 are mounted on the second mounting surface 95, and areas that are less than 4 mm away from the outer edge of the area of ​​the first mounting surface 84. This reduces the stress acting on the connection points between the small chip components and the first decorative substrate 56 and on the small chip components themselves when attaching or detaching a harness to the connectors 111, 112, while ensuring a large area on the first decorative substrate 56 where small chip components can be mounted.

[0334] The area near the outer edge of the first decorative substrate 56 where small chip components (bypass capacitors 85 and small chip resistors 87, 143-149 (Figure 11)) are not mounted is not limited to an area less than 10 mm from the outer edge of the first decorative substrate 56. The area near the outer edge of the substrate where small chip components are not mounted may also be an area less than 12 mm from the outer edge of the first decorative substrate 56. This reduces the possibility of damage to the connections between the small chip components and the first decorative substrate 56 due to a worker's hand touching the small chip components when handling the first decorative substrate 56, and also reduces the possibility of damage to the small chip components themselves. Furthermore, when an aggregate substrate 231 including multiple first decorative substrates 56 is divided to remove the first decorative substrates 56, it is possible to reduce stress that may act on the connections between the small chip components and the first decorative substrate 56 when the aggregate substrate 231 is divided, and also to reduce stress acting on the small chip components themselves. Furthermore, the area near the outer edge of the board where small chip components are not mounted may be an area that is less than 8 mm away from the outer edge of the first decorative board 56. This reduces the possibility of damage to the connection between the small chip components and the first decorative board 56 and to the small chip components themselves, while ensuring a large area on the first decorative board 56 where small chip components can be mounted.

[0335] &l...

Claims

1. A gaming machine having a predetermined board mounted with a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component and not used as a gaming board, the first predetermined electronic component is mounted on a first predetermined surface side, which is one surface of the predetermined substrate; the second predetermined electronic component is mounted on a second predetermined surface of the predetermined substrate opposite to the first predetermined surface, the second predetermined electronic component is not mounted on an area of ​​the second predetermined plate surface on the rear side of an area on the first predetermined plate surface where the first predetermined electronic component is mounted, a specific electronic component larger than the second predetermined electronic component is mounted on the second predetermined plate surface side of the predetermined substrate, the specific electronic component is mounted on the second predetermined board surface in an area behind an area on the first predetermined board surface where the first predetermined electronic component is mounted, the second predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode, The predetermined substrate is a first predetermined connection portion to which the first predetermined electrode is electrically connected; a first predetermined wiring pattern drawn out from the first predetermined connection portion; a second predetermined connection portion to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn out from the second predetermined connection portion; It is equipped with A gaming machine characterized in that the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same direction as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part.

2. A gaming machine having a predetermined board mounted with a first predetermined electronic component and a second predetermined electronic component smaller than the first predetermined electronic component and not used as a gaming board, the first predetermined electronic component is mounted on a first predetermined surface side, which is one surface of the predetermined substrate; the second predetermined electronic component is mounted on a second predetermined surface of the predetermined substrate opposite to the first predetermined surface, the second predetermined electronic component is not mounted on an area of ​​the second predetermined plate surface on the rear side of an area on the first predetermined plate surface where the first predetermined electronic component is mounted, the predetermined substrate is provided with a predetermined substrate fixing portion for fixing the predetermined substrate, the second predetermined electronic component is not mounted in an area that is less than a predetermined distance from the predetermined board fixing portion, the first predetermined electronic component is mounted in an area less than the predetermined distance, the second predetermined electronic component includes a pair of electrodes, that is, a first predetermined electrode and a second predetermined electrode, The predetermined substrate is a first predetermined connection portion to which the first predetermined electrode is electrically connected; a first predetermined wiring pattern drawn out from the first predetermined connection portion; a second predetermined connection portion to which the second predetermined electrode is electrically connected; a second predetermined wiring pattern drawn out from the second predetermined connection portion; It is equipped with A gaming machine characterized in that the direction in which the side of the first predetermined connection part from which the first predetermined wiring pattern is drawn exists when viewed from the center of the first predetermined connection part is the same direction as the direction in which the side of the second predetermined connection part from which the second predetermined wiring pattern is drawn exists when viewed from the center of the second predetermined connection part.

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