gaming machines

Abstract

To provide a game machine capable of updating an appropriate random number value.SOLUTION: A first random number value and a second random number value are composed of the same two bytes, and the first random number value is used for determining whether control is performed to an advantageous state and is managed by increasing an update speed as compared with the second random number value. A performance control CPU 120 performs a variation start action of a decorative pattern during a reservation shift display following start of a variation display, and does not start a scroll display of a decorative pattern until completion of a shift display for switching a first reservation display 002SG101 displayed in a first display area from the left in a special pattern reservation storage display area 5U in an active display area 5F as an active display 002SG103. A common shift display can be performed in execution of a variable display on the basis of a first kind of variation pattern designation command and in execution of a variable display on the basis of a second kind of variation pattern designation command.SELECTED DRAWING: Figure 10-12

Description

[Technical Field]

[0001] The present invention relates to a gaming machine capable of playing a game. [Background technology]

[0002] There are gaming machines such as pachinko machines that manage various random numbers using hardware random numbers and software random numbers (for example, Patent Document 1). There are also gaming machines that variably display multiple types of decorative identification information (decorative patterns) in response to the variably displayed specific identification information (special patterns) (for example, see Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6124313 [Patent Document 2] Japanese Patent Application Laid-Open No. 2017-86392 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is room for improving the marketability of gaming machines having the functions and configurations of Patent Documents 1 and 2.

[0005] The present invention has been made in view of the above circumstances, and aims to provide a gaming machine with improved marketability. [Means for solving the problem]

[0006] In order to achieve the above object, the gaming machine according to the present invention comprises: A gaming machine that can variably display identification information including first identification information and second identification information, and can be controlled to an advantageous state that is advantageous to a player, The display of the identification information can be variably performed based on a plurality of types of variable display patterns including a predetermined variable display pattern, Includes a first presentation mode and a second presentation mode In the performance mode, a plurality of types of background images including a first background image and a second background image can be switched and displayed; In the first presentation mode, The background image Corresponding to the first performance mode From the first background image Corresponding to the first performance mode When switching to the second background image, Corresponding to the first performance mode A background fade-out display is performed by gradually increasing the transparency of the first background image, and Corresponding to the first performance mode A background fade-in display can be performed by gradually decreasing the transparency of the second background image, In the second presentation mode, when the background image is switched from the first background image corresponding to the second presentation mode to the second background image corresponding to the second presentation mode, a background fade-out display is executed in which the transparency of the first background image corresponding to the second presentation mode is gradually increased, and a background fade-in display is executed in which the transparency of the second background image corresponding to the second presentation mode is gradually decreased, In the first presentation mode and the second presentation mode, the region in which the identification information is variably displayed includes at least a first region and a second region; when starting the variable display of the identification information, starting the variable display of the first identification information in the first area and starting the variable display of the second identification information in the second area; a first identification information fade-out display can be performed by gradually increasing the transparency of the first identification information in the first area when variable display of the first identification information is started, and a second identification information fade-out display can be performed by gradually increasing the transparency of the second identification information in the second area when variable display of the second identification information is started, when terminating the variable display of the identification information, decelerating the variable display of the first identification information in the first area and decelerating the variable display of the second identification information in the second area; When the variable display of the first identification information is slowed down, a first identification information fade-in display can be performed in which the transparency of the first identification information is gradually decreased in the first area, and when the variable display of the second identification information is slowed down, a second identification information fade-in display can be performed in which the transparency of the second identification information is gradually decreased in the second area, at least In the first presentation mode The first identification information is faded out; or In the first presentation mode The second identification information fade-out display In the first presentation mode The background fade-out display Specific timing is feasible, At least one of the first identification information fade-out display in the second presentation mode or the second identification information fade-out display in the second presentation mode and the background fade-out display in the second presentation mode can be executed at a predetermined timing; The length of the execution period of the fade-out display of the first identification information in the first presentation mode and the length of the execution period of the fade-out display of the second identification information in the first presentation mode are the same, The length of the execution period of the fade-out display of the first identification information in the second presentation mode and the length of the execution period of the fade-out display of the second identification information in the second presentation mode are common, The duration of the background fade-out display in the first presentation mode is longer than the duration of the first identification information fade-out display in the first presentation mode and the duration of the second identification information fade-out display in the first presentation mode; The duration of the background fade-out display in the second presentation mode is longer than the duration of the first identification information fade-out display in the second presentation mode and the duration of the second identification information fade-out display in the second presentation mode; When the specific identification information is variably displayed in the predetermined variable display pattern, the fade-out display of the first identification information in the first presentation mode and the fade-out display of the second identification information in the first presentation mode can be executed over a first execution period, When the specific identification information is variably displayed in the predetermined variable display pattern, the fade-out display of the first identification information in the second presentation mode and the fade-out display of the second identification information in the second presentation mode can be executed over a second execution period different from the first execution period, A predetermined number of pending displays corresponding to variable displays that have not yet started can be updated and displayed up to the upper limit. the identification information includes a character representation, As the variable display of the identification information, a scroll action and a pre-start action in which the character display moves before the start of the scroll action can be executed, The pre-start action is executed after the pending display is updated. It is characterized by: [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a front view of a pachinko gaming machine. [Figure 2] FIG. 2 is a configuration diagram showing various control boards and the like. [Figure 3] FIG. 10 is a diagram showing an example of a random number for gaming. [Figure 4] 10 is a flowchart showing a main process for game control. [Figure 5] 10 is a flowchart showing an example of a timer interrupt process for game control. [Figure 6] 10 is a flowchart illustrating an example of a special symbol process. [Figure 7] A diagram showing an example of the configuration of a special pattern process jump table. [Figure 8] 10 is a flowchart showing a main process for performance control. [Figure 9] 10 is a flowchart showing an example of a performance control process. [Figure 10-1] FIG. 2 is a diagram showing an example of the configuration of a game control microcomputer. [Figure 10-2] FIG. 10 is a diagram illustrating an example of an address map. [Figure 10-3] 10A and 10B are diagrams illustrating examples of main setting of addresses included in a function setting register area. [Figure 10-4] 10A and 10B are diagrams illustrating examples of main setting of addresses included in a function control register area. [Figure 10-5] A diagram for explaining an example of settings for gaming random numbers. [Figure 10-6] FIG. 10 is a diagram for explaining a random number update period. [Figure 10-7] 10 is a flowchart illustrating an example of a power supply start response process. [Figure 10-8] FIG. 10 is a diagram illustrating an example of the configuration of a function setting register stored value table. [Figure 10-9] FIG. 10 is a diagram illustrating an example of the configuration of an RWM access protection register. [Figure 10-10] 10 is a flowchart illustrating an example of a power-off process. [Figure 10-11] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-12] 10 is a flowchart illustrating an example of a random number update process. [Figure 10-13] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-14] 10 is a flowchart illustrating an example of an initial value change random number update process. [Figure 10-15] 10 is a flowchart illustrating an example of an initial value determination random number update process. [Figure 10-16] 10 is a flowchart showing an example of a start port switch passing process. [Figure 10-17] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-18] 10 is a flowchart showing an example of a normal special symbol processing. [Figure 10-19] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-20] 10 is a flowchart showing an example of a special symbol determination process. [Figure 10-21] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-22]10 is a flowchart showing an example of a special symbol information setting process. [Figure 10-23] A flowchart showing an example of a jackpot information data selection process. [Figure 10-24] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-25] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-26] 10 is a flowchart showing an example of a variation pattern setting process. [Figure 10-27] This is a flowchart showing an example of a winning fluctuation pattern type table selection process. [Figure 10-28] This is a flowchart showing an example of a process for selecting a fluctuation pattern type table when a winning combination is lost. [Figure 10-29] A diagram for explaining an example of the configuration of a fluctuation pattern type allocation table. [Figure 10-30] FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. [Figure 10-31] FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. [Figure 10-32] FIG. 10 is a diagram illustrating an example of the configuration of a fluctuation pattern allocation table. [Figure 10-33] 10 is a flowchart showing an example of normal symbol process processing. [Figure 10-34] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 10-35] 10 is a flowchart illustrating an example of a gate switch passing process. [Figure 10-36] 10 is a flowchart showing an example of normal processing for normal symbols. [Figure 10-37] FIG. 10 is a diagram for explaining an example of use of a data configuration. [Figure 11] 1 is a front view showing a gaming machine according to a first embodiment. [Figure 12] FIG. 1 is a configuration diagram showing various control boards and the like installed in a pachinko gaming machine. [Figure 13] FIG. 10 is a diagram illustrating an example of a performance control command. [Figure 14] FIG. 2 is an explanatory diagram showing each random number. [Figure 15] FIG. 10 is an explanatory diagram showing a display result determination table. [Figure 16] (A) is an explanatory diagram showing the jackpot type determination table, and (B) is an explanatory diagram of the jackpot type. [Figure 17] FIG. 10 is an explanatory diagram of a fluctuation pattern. [Figure 18] FIG. 10 is an explanatory diagram of a fluctuation pattern determination table. [Figure 19] FIG. 2 is an explanatory diagram showing a game control data storage area. [Figure 20] (A) is an explanatory diagram showing the data holding area for performance control, and (B) is an explanatory diagram showing the command buffer received at the time of starting winning. [Figure 21] 10 is a flowchart showing an example of a game control main process. [Figure 22] 10 is a flowchart showing an example of a timer interrupt process for game control. [Figure 23] 10 is a flowchart illustrating an example of a special symbol process. [Figure 24] 10 is a flowchart showing an example of a start winning determination process. [Figure 25] 10 is a flowchart showing an example of a normal special symbol processing. [Figure 26] 10 is a flowchart showing an example of a performance control main process. [Figure 27] 10 is a flowchart showing an example of a performance control process. [Figure 28] 10 is a flowchart illustrating an example of a variable display start setting process. [Figure 29] This is a diagram for explaining decorative patterns and small patterns. [Figure 30] (A1) and (A2) are figures showing the first presentation mode, (B1) and (B2) are figures showing the second presentation mode, (C1) and (C2) are figures showing the third presentation mode, and (D1) and (D2) are figures showing the fourth presentation mode. [Figure 31](A1) and (A2) are diagrams showing the relationship between the variable display area and the decorative symbols in the first presentation mode, and (B1) and (B2) are diagrams showing the relationship between the variable display area and the decorative symbols in the second presentation mode. [Figure 32] (C1) and (C2) are diagrams showing the relationship between the variable display area and the decorative pattern in the third performance mode, (D1) and (D2) are diagrams showing the relationship between the variable display area and the decorative pattern in the fourth performance mode, and (E) is a diagram for explaining the variable display of the decorative pattern and the small pattern. [Figure 33] 1A is a diagram showing the decorative pattern change start action, (B) is a diagram showing the change stop action, and (C) is a diagram showing the loop action. [Figure 34] 10A is a diagram comparing various decorative pattern actions and periods of lamp light emission control, and FIG. 10B is a diagram showing an example of loop lamp light emission control. [Figure 35] (A1) to (A4) and (B1) to (B4) are diagrams illustrating an example of the operation of the hold display. [Figure 36] A diagram showing the flow of variable display of decorative patterns in the first presentation mode. [Figure 37] This is a diagram showing the flow of variable display of decorative patterns following Figure 36. [Figure 38] A diagram showing the flow of variable display of decorative patterns in the second presentation mode. [Figure 39] This is a diagram showing the flow of variable display of decorative patterns following Figure 38. [Figure 40] FIG. 39 is a diagram showing details of the flow of variable display of the decorative patterns in FIG. 38. [Figure 41] FIG. 10 is a diagram showing the flow of variable display of decorative patterns as Modification 1. [Figure 42] FIG. 42 is a diagram showing the flow of variable display of decorative patterns following FIG. 41. [Figure 43] A diagram showing the flow of variable display of decorative patterns in the third presentation mode. [Figure 44] FIG. 10 is a diagram for explaining how the decorative pattern appears. [Figure 45] A diagram showing the flow of variable display of decorative patterns in the fourth presentation mode. [Figure 46]FIG. 10 is a diagram showing the flow of the stopped display of decorative symbols in the first presentation mode (second presentation mode). [Figure 47] This is a diagram showing the flow of the decorative pattern stop display following Figure 46. [Figure 48] (A) to (G) are diagrams showing the flow of the stop display of decorative symbols when the number of reserved memories is three in the first presentation mode (second presentation mode). [Figure 49] 10A and 10B are diagrams showing the flow of the stopped display of decorative symbols in the fourth presentation mode (third presentation mode). [Figure 50] (A1) is a diagram showing a first background image, (A2) is a diagram showing a first predetermined background image, and (B) is a diagram explaining a change in background. [Figure 51] A diagram showing the flow of background changes in the first presentation mode. [Figure 52] This is a timing chart showing the flow of each part of the variable display in the first presentation mode. [Figure 53] This is a timing chart showing the flow of each part of the variable display in the second presentation mode. [Figure 54] This is a timing chart showing the flow of each part of the variable display in the third and fourth presentation modes. [Figure 55] (A) is a timing chart showing the state of each part at the start of variable display in the first presentation mode, (B) is the second presentation mode, and (C) is the third and fourth presentation modes. [Figure 56] FIG. 10 is a diagram showing an example of the operation of a customer waiting demo performance. [Figure 57] This figure shows an example of operation when a start winning occurs during a customer waiting demo performance. [Figure 58] A diagram showing the flow of pseudo-consecutive announcements. [Figure 59] (A) is a diagram showing an example of the pseudo consecutive number of times displayed and the pattern color, (B) is a diagram showing the types of pseudo consecutive number of times displayed and the pattern color, and (C) is a diagram showing the pseudo consecutive number of times display color determination table. [Figure 60] FIG. 10 is a diagram showing the flow of reach effects. [Figure 61]FIG. 61 is a diagram showing the flow of reach effects following FIG. 60. [Figure 62] 10A to 10C are diagrams showing examples of the operation of each part in reach performance. [Figure 63] A diagram showing the flow of the SP reach presentation. [Figure 64] This is a diagram showing the flow of the SP reach presentation following Figure 63. [Figure 65] FIG. 10 is a diagram showing an example of the operation of each part in the SP reach performance. [Figure 66] (A1) to (A7) are diagrams showing a second modification of the present invention. [Figure 67] 10(A) to 10(D) are diagrams showing a third modified example of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] (Basic explanation) First, the basic configuration and control of the pachinko gaming machine 1 will be described.

[0009] (Configuration of Pachinko Machine 1) Figure 1 is a front view of a pachinko gaming machine 1, showing the layout of the main components. The pachinko gaming machine (gaming machine) 1 is broadly composed of a gaming board (gauge board) 2 that forms the gaming board surface, and a gaming machine frame (base frame) 3 that supports and fixes the gaming board 2. A gaming area is formed on the gaming board 2, and gaming balls, which serve as gaming media, are shot into this gaming area by a predetermined ball shooting device.

[0010] A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the gaming board 2. In the example shown in FIG. 1, they are provided on the right side of the gaming area. The first special symbol display device 4A and the second special symbol display device 4B can each variably display special symbols as multiple types of special identification information. Special symbols are also called "special symbols." The variable display of special symbols is also called "special symbol game." Both the first special symbol display device 4A and the second special symbol display device 4B are configured using 7-segment LEDs or the like. Special symbols are represented by numbers "0" to "9," symbols indicating "-," or other arbitrary lighting patterns. The special symbols may include a pattern in which all LEDs are turned off.

[0011] The "variable display" of special symbols refers to, for example, the variable display of multiple types of special symbols. For other symbols, such as special symbols, small symbols, and regular symbols, "variable display" also refers to the variable display of multiple types of symbols. Special symbols are also called decorative symbols or ornamental symbols. Variable displays are also called variable displays, or simply "variations." Variations include updating multiple symbols, scrolling multiple symbols, and deforming, enlarging, or reducing one or more symbols. Variations may include flashing a symbol. In the variable display of special symbols or regular symbols, multiple types of special symbols or regular symbols are displayed in a variable manner. In the variable display of special symbols, multiple symbols are scrolled or updated, or one or more symbols are deformed, enlarged, or reduced. In the variable display of any symbol, a predetermined symbol is displayed as a static display. A static display is also called a derived display, or simply "derivation." The symbol that finally stops and is displayed in a variable display is also called the final stop symbol or the confirmed symbol. The symbol that finally stops in a special symbol game is also called the confirmed special symbol. The display result of the variable display includes the display result of the special symbol, and is also called the variable display result. The display result of the special symbol is also called the special symbol display result. The execution time of the variable display includes the special symbol change time, which is the change time of the special symbol, and is also called the variable display time. The special symbol change time can be set to a different time corresponding to the change pattern of the special symbol, of which multiple patterns are prepared in advance.

[0012] The special pattern variably displayed on the first special pattern display device 4A is also called the "first special pattern." The special pattern variably displayed on the second special pattern display device 4B is also called the "second special pattern." A special pattern game using the first special pattern is also called the "first special pattern game." A special pattern game using the second special pattern is also called the "second special pattern game." There may be only one type of special pattern display device that variably displays special patterns.

[0013] A normal symbol display 20 is provided at a predetermined position on the game board 2. In the example shown in FIG. 1, it is provided on the left side of the play area. The normal symbol display 20 can variably display normal symbols as multiple types of normal identification information different from special symbols. Normal symbols are also called "normal symbols." The variable display of normal symbols is also called "normal symbol game." The normal symbol display 20 is configured using 7-segment LEDs, etc. Normal symbols are represented by numbers "0" to "9," symbols indicating "-," or other arbitrary lighting patterns. Normal symbols may include a pattern in which some or all of the multiple LEDs are lit, or a pattern in which all of the multiple LEDs are turned off. The final stop symbol in a normal symbol game is also called a confirmed normal symbol. The display result of the normal symbol is also called a normal symbol display result. The execution time during which the normal symbol is variably displayed in a normal symbol game is also called a normal symbol fluctuation time. The normal symbol variation time can be set to different times in accordance with the normal symbol variation pattern, of which multiple patterns are prepared in advance.

[0014] An image display device 5 is provided near the center of the play area on the game board 2. The image display device 5 may be configured using a mechanism capable of forming any image, such as an LCD (liquid crystal display), organic EL (electroluminescence), dot matrix LED, projector and screen, stereoscopic image projection device, or any other device. The image display device 5 is capable of displaying various effect images. Furthermore, the image display device 5 is not limited to effect images, and can display any control-related image such as an inspection image or a setting image.

[0015] For example, on the screen of the image display device 5, variable display of effect symbols can be performed in synchronization with the first special symbol game and the second special symbol game. The effect symbols are display symbols that indicate numbers or the like, and are multiple types of decorative identification information different from special symbols and normal symbols. On the screen of the image display device 5 shown in FIG. 1, "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R are provided, respectively. Variable display of effect symbols is performed, for example, by vertically scrolling or updating the effect symbols in synchronization with the first special symbol game or the second special symbol game. Synchronization of the variable display may be achieved as long as the timing at which the symbol variation begins and the timing at which the variation ends and the symbol is finally displayed are consistent for different types of symbols. The final stopped symbol in the variable display of effect symbols is also referred to as the determined effect symbol, determined decorative symbol, or determined decorative symbol. The variable display of the effect pattern is synchronized with the first special pattern game and the second special pattern game, so the variable display time of the effect pattern is the same as the special pattern change time.

[0016] The screen of the image display device 5 may be provided with a display area capable of displaying effect images corresponding to a pending display and an active display. A pending display is a display corresponding to a variable display that has not yet been executed and is on hold. An active display is a display corresponding to a variable display that is being executed. The pending display and the active display are also collectively referred to as a variable display-compatible display that corresponds to a variable display. A display area that displays a pending display is also referred to as a pending display area. A display area that displays an active display is also referred to as an active display area. The number of variable displays that are on hold is also referred to as the number of pending memories. The number of pending memories corresponding to the first special symbol game is also referred to as the first number of pending memories. The number of pending memories corresponding to the second special symbol game is also referred to as the second number of pending memories. The sum of the first number of pending memories and the second number of pending memories is also referred to as the total number of pending memories.

[0017] Above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. 1, there are provided a first reserve indicator 25A and a second reserve indicator 25B, each comprising a plurality of LEDs. The first reserve indicator 25A displays the first reserve memory number by the number of lit LEDs. The second reserve indicator 25B displays the second reserve memory number by the number of lit LEDs. Above the normal symbol display device 20 shown in FIG. 1, there is provided a normal symbol reserve indicator 25C, comprising a plurality of LEDs. The normal symbol reserve indicator 25C displays the normal symbol reserve number by the number of lit LEDs. The normal symbol reserve number is the reserve memory number corresponding to the normal symbol game.

[0018] Below the image display device 5 are provided a winning ball device 6A and a variable winning ball device 6B. The winning ball device 6A forms a first starting winning opening that is always kept in a constant open state, allowing game balls to enter, for example, by a predetermined ball receiving member. The variable winning ball device 6B forms a second starting winning opening that can be switched between a closed state and an open state by a normal electric device solenoid 81 shown in FIG. 2 as a normal electric device. The variable winning ball device 6B is equipped with, for example, an electric tulip-type device with a pair of movable wings. When the normal electric device solenoid 81 is in the off state, the movable wings are in a vertical position, causing the second starting winning opening to be in a closed state where game balls cannot enter, or in a normal open state where game balls have difficulty entering. When the normal electric accessory solenoid 81 is on, the variable winning ball device 6B tilts the movable wing piece to an open state in which the second starting winning port can receive game balls or to an expanded open state in which the second starting winning port can easily receive game balls. The open state in which the second starting winning port can receive game balls or the expanded open state in which the second starting winning port can easily receive game balls is also referred to as the first variable state. The closed state in which the second starting winning port cannot receive game balls or the normal open state in which the second starting winning port cannot easily receive game balls is also referred to as the second variable state. Note that the variable winning ball device 6B is not limited to devices equipped with an electric tulip-shaped accessory as long as it can be changed between the first variable state and the second variable state.

[0019] The entry of a gaming ball into the first start entry port formed by the winning ball device 6A is also referred to as a first start entry. The entry of a gaming ball into the second start entry port formed by the variable winning ball device 6B is also referred to as a second start entry. A gaming ball entering the first start entry port is detected by the first start entry port switch 22A shown in FIG. 2. A gaming ball entering the second start entry port is detected by the second start entry port switch 22B shown in FIG. 2. Upon the occurrence of a first start entry, a predetermined number of prize balls, for example, three, are paid out, and the first reserved memory count can be updated to increment by one. However, if the first reserved memory count has reached its upper limit, the first reserved memory count will not be updated even if a first start entry occurs. When the first reserved memory count is incremented by one, the first start condition is met, and a first special symbol game in which special symbols are variably displayed by the first special symbol display device 4A becomes playable. When a second start winning occurs, a predetermined number of prize balls, for example, three balls, are paid out, and the second reserved memory count can be updated to increment by 1. However, if the second reserved memory count has reached its upper limit, the second reserved memory count will not be updated even if a second start winning occurs. When the second reserved memory count is incremented by 1, the second start condition is met, and a second special symbol game can be played in which the second special symbol display device 4B variably displays special symbols.

[0020] General prize openings 10, which are always kept in a constant open state by a predetermined ball receiving member, are provided at predetermined positions on the game board 2. In the example shown in Figure 1, general prize openings 10 are provided in two locations on the lower left of the game area. When a game ball enters one of the general prize openings 10, a predetermined number of prize balls, for example 10, are paid out.

[0021] In the play area formed by the playboard 2, a first path and a second path are provided as paths along which game balls flow down. The first path is mainly provided in the area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in the area to the right of the image display device 5 when viewed from the front. The area to the left of the image display device 5 is also referred to as the left play area or left play area. The area to the right of the image display device 5 is also referred to as the right play area or right play area. The left play area and the right play area may be separated, for example, by the end face of the image display device 5 in the play area or the arrangement of game nails. Firing a game ball toward the left play area to make it flow down the first path is also referred to as a left hit. Firing a game ball toward the right play area to make it flow down the second path is also referred to as a right hit. The first path is also referred to as a left hit path. The second path is also referred to as a right hit path. The first path and the second path may be configured by separate paths, or may be paths that are partially shared.

[0022] In response to the operation of a ball operating handle provided on the ball launching device, a gaming ball is launched from the ball launching device and launched into the gaming area. When the gaming ball launched into the gaming area is guided to the left gaming area and flows down the first path, it is guided, for example, along the arrangement of gaming nails, making it impossible or difficult to guide it to the second path in the right gaming area. When the gaming ball launched into the gaming area is guided to the right gaming area and flows down the second path, it is guided, for example, along the arrangement of gaming nails, making it impossible or difficult to guide it to the first path in the left gaming area.

[0023] The winning ball device 6A is provided on the first path in the left-side game area, allowing game balls flowing down the first path to enter. The variable winning ball device 6B is provided on the second path in the right-side game area, allowing game balls flowing down the second path to enter. Note that the variable winning ball device 6B may also be configured to allow game balls flowing down the first path in the left-side game area to enter. The variable winning ball device 6B may also be positioned so that game balls flowing down the second path in the right-side game area have an easier time entering than game balls flowing down the first path in the left-side game area.

[0024] The second path in the right-side game area is provided with a passing gate 41 and a special variable winning ball device 50. The passing gate 41 forms a passing area through which game balls can pass. Game balls that pass through the passing gate 41 are detected by the gate switch 21 shown in FIG. 2. Based on the game ball passing through the passing gate 41, the number of normal reserved memories can be added and updated, and variable display of normal symbols by the normal symbol display device 20 can be executed as a normal symbol game. The passing gate 41 can be configured as a normal symbol activation port through which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol activation port switch that can detect game balls that have entered the normal symbol activation port.

[0025] The special variable prize ball device 50 functions as a special electric device, forming a large prize opening that can be switched between a closed and an open state by a large prize opening solenoid 82. A guide passage with a width in the front-to-back direction sufficient for game balls to pass through is formed at the top of the special variable prize ball device 50. This guide path slopes downward from right to left, with walls provided on both sides of the extended passage, the front and back. A role entrance serving as the large prize opening is formed in the center of the guide passage. In the special variable prize ball device 50, a movable member 52 that can move in the front-to-back direction is provided as a large prize opening opening / closing member at a position where the large prize opening can be opened and closed. In the special variable prize ball device 50, a fixed member 53 that forms a fixed passage is provided in the portion of the guide passage where the large prize opening is not formed.

[0026] The movable member 52 is driven by a large prize opening solenoid 82 and can move back and forth to open and close the special device entrance, which serves as the large prize opening. In the special variable prize ball device 50, game balls that enter the device through the large prize opening are detected by a count switch 23. A V prize area 51, which serves as a specific area, is provided inside the special variable prize ball device 50 as a prize area through which game balls can pass. A normal area different from the V prize area 51 is also provided inside the special variable prize ball device 50. A plate-shaped distribution member is provided above the V prize area 51 as a V prize opening opening / closing member, which can switch the V prize area 51 between an open state and a closed state. The distribution member is driven by a specific area solenoid 83 and can move back and forth to open and close the V prize area 51. When the V prize area 51 is in the open state, game balls can pass through it, and when it is in the closed state, game balls cannot pass through it. A gaming ball that passes through the V winning area 51 is detected by the specific area switch 24. A gaming ball that does not pass through the V winning area 51 passes through the normal area. Both the gaming ball that passes through the V winning area 51 and the gaming ball that does not pass through the V winning area 51 but passes through the normal area are detected by the discharge port switch 26 and then discharged to the outside of the special variable winning ball device 50.

[0027] In addition to the above features, the surface of the gaming board 2 is provided with a windmill that changes the direction and speed of the gaming balls as well as numerous obstacle nails. At the bottom of the gaming area, an outlet is provided for gaming balls that do not enter any of the winning holes. Speakers 8L and 8R for playing and outputting sound effects and the like are provided at the top left and right positions of the gaming machine frame 3, and gaming effect lamps 9 for lighting up the effects are provided around the periphery of the gaming area. The gaming effect lamps 9 are configured to include LEDs. A movable body 32 that operates according to the effects is provided at a predetermined position on the gaming board 2.

[0028] A ball operation handle is provided at the lower right position of the gaming machine frame 3, which is operated by a player or the like to launch gaming balls toward the playing area using the ball launching device. The ball operation handle is also called an operation knob. At a predetermined position on the gaming machine frame 3 below the playing area, a ball supply tray is provided that holds gaming balls dispensed as prize balls or gaming balls loaned from a predetermined ball lending machine so that they can be supplied to the ball launching device. The ball supply tray is also called the upper tray. Below the upper tray is a prize ball storage tray into which prize balls dispensed when the upper tray is full flow down and are stored. The prize ball storage tray is also called the lower tray.

[0029] A stick controller 31A and a push button 31B are provided at predetermined positions on the gaming machine frame 3 below the gaming area. The stick controller 31A can be held by a player and tilted, and is provided with a trigger button that the player can push and pull. Operations on the stick controller 31A are detected by a controller sensor unit 35A shown in FIG. 2. The push button 31B can be pressed by a player. Operations on the push button 31B are detected by a push sensor 35B shown in FIG. 2. In the pachinko gaming machine 1, the stick controller 31A and the push button 31B are used as detection means for detecting actions such as player operations, but other detection means may also be used.

[0030] (Outline of game progress) The game ball is launched toward the game area by the player's rotation of the ball-hitting control handle provided on the pachinko game machine 1. When the game ball passes through the passage gate 41, a normal game is initiated by the normal symbol display device 20. Note that if the previous normal game is still being played, the normal game based on the passage of the game ball through the passage gate 41 cannot be immediately played. Therefore, the normal game based on the passage is suspended up to a predetermined upper limit, such as "4." In the normal game, if a specific normal symbol, such as a normal winning symbol, is displayed as a fixed normal symbol, the display result of the normal symbol is "normal winning." In contrast, if a normal symbol other than a normal winning symbol, such as a normal losing symbol, is displayed as a fixed normal symbol, the display result of the normal symbol is "normal losing." In the case of a "normal winning," opening control is performed to place the variable winning ball device 6B in an open state or an expanded open state for a predetermined period of time. At this time, the second starting winning port is in an open state or an expanded open state.

[0031] When a gaming ball passes through and enters the first start entry opening formed in the winning ball device 6A, the first special symbol game can be initiated by the first special symbol display device 4A. When a gaming ball passes through and enters the second start entry opening formed in the variable winning ball device 6B, the second special symbol game can be initiated by the second special symbol display device 4B. Note that even if a gaming ball enters the start entry opening and a start entry occurs during a period when a special symbol game is being played or during a period when the game is controlled to a jackpot game state or a small jackpot game state, the special symbol game based on the start entry cannot be immediately executed. Therefore, the special symbol game based on the start entry is suspended up to a predetermined upper limit, such as "4." In the special symbol game, when a specific special symbol, such as a jackpot symbol, is displayed as a fixed special symbol, the display result of the special symbol is a "jackpot." In contrast, when a predetermined special pattern, such as a small win pattern, different from a jackpot pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern will be "small win." Also, when a special pattern, such as a loss pattern, different from a jackpot pattern or a small win pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern will be "miss." Furthermore, when a special pattern, such as a time-saving pattern, different from a jackpot pattern, a small win pattern, or a loss pattern, is stopped and displayed as the confirmed special pattern, the display result of the special pattern may be "time-saving." The special pattern may not include a time-saving pattern. In other words, the display result of the special pattern may not include "time-saving."

[0032] In a special game, once the special symbol display results in a "jackpot," the game enters a jackpot gaming state, which is advantageous to the player. In the jackpot gaming state, the special variable prize ball device 50 can open in a predetermined manner. This open state continues until either a predetermined period of time, such as 29 seconds or 1.8 seconds, has elapsed, or until the number of game balls entering the jackpot reaches a predetermined number, whichever comes first. The predetermined period during which the jackpot opening can be controlled to an open state is the maximum period during which the jackpot opening can be opened in one round, also referred to as the maximum opening period. In the jackpot gaming state, one cycle in which the jackpot opening is open is called a round or round play. In the jackpot gaming state, such rounds can be repeated until a predetermined maximum number of times, such as 15 or 2 times, is reached. In the jackpot gaming state, the player can win prize balls by entering game balls into the jackpot opening. Therefore, the jackpot gaming state is an advantageous state for the player. The more rounds there are in the jackpot gaming state, and the longer the upper limit open period, the more advantageous it is for the player.

[0033] When the display result of a special symbol indicates a "jackpot," multiple jackpot types are included. For example, the opening mode of the jackpot slot, such as the number of rounds or the maximum opening period, and the game state after the jackpot game state ends, such as normal mode, time-saving mode, or probability variable mode, are set to multiple different settings, and a jackpot type is specified corresponding to each setting. The multiple jackpot types may include some or all of the jackpot types that offer many prize balls, jackpot types that offer few prize balls, or jackpot types that offer almost no prize balls, or may include jackpot types with similar numbers of prize balls that can be obtained. Controlling the jackpot game state based on the display result of a special symbol indicating a "jackpot" is also called a pattern jackpot, a special symbol jackpot, a variable display jackpot, or a direct hit jackpot.

[0034] In a special game, once the display result of the special symbol indicates a "small win," the game is controlled to a small win gaming state. In the small win gaming state, the large prize opening formed in the special variable prize ball device 50 can be opened in a predetermined opening mode. For example, in the small win gaming state, the large prize opening may be opened in the same opening mode as in the large prize gaming state for certain jackpot types. The large prize opening may be opened in the same opening mode by sharing the same number of openings and opening period. Alternatively, in the small win gaming state, the large prize opening may be opened in a different opening mode from the large prize opening in the jackpot gaming state. As with the jackpot type, multiple small win types may be included when the display result of the special symbol indicates a "small win." The jackpot type and small win type are also collectively referred to as the win type. The operation of opening and closing the large prize opening in the small win gaming state is also referred to as the start operation. When in the small win gaming state, the special variable winning ball device 50's role entrance, which serves as the large winning opening, is opened, and when the gaming ball passes through the V winning area 51 and is detected by the specific area switch 24, the conditions for a big win are met, and control becomes possible to the big win gaming state. When in the small win gaming state, the gaming ball passes through the V winning area 51, causing a V winning, and the game is controlled to the big win gaming state, this is also called a small win via big win.

[0035] After the jackpot game state ends, the game state can be controlled to a time-saving state or a probability variable state depending on the type of jackpot. Furthermore, in a special symbol game, after the display result of the special symbol becomes "time-saving," the game state is not controlled to the jackpot game state but is controlled to a time-saving state. The time-saving state is a game state in which the second special symbol game by the second special symbol display device 4B is more likely to be executed than in the normal state. A game state in which the second special symbol game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second start winning hole than in the normal state. Control of whether the game ball is more likely to pass through the second start winning hole is also called base control. Base control in the normal state is also called normal base control or low base control. Base control in the time-saving state includes high base control. In addition to high base control, the time-saving state may also include medium base control. The medium base control is a base control that makes it easier for the game ball to pass through the second start winning hole than the low base control, but makes it harder for the game ball to pass through the second start winning hole than the high base control. The game state in which the medium base control is performed is also called the medium base state. The game state in which the high base control is performed is also called the high base state. The high base control is also called the high opening control.

[0036] In the normal state, the medium base state, and the high base state, it is possible to display a time-saving symbol as a result of displaying a special symbol. However, in the medium base state and the high base state, even if a time-saving symbol is displayed as a result of displaying a special symbol, base control based on the time-saving symbol is not performed, and new control to transition to the medium base state or the high base state is not initiated. In the time-saving state, it is possible to perform time-saving control that shortens the average variable display time more than in the normal state. For this reason, the time-saving state is also called the time-shortening state.

[0037] The time-saving state, which increases the fluctuation efficiency of special symbols, especially the second special symbol, is considered a special state that is advantageous to players and distinct from the jackpot gaming state. When the gaming state is a probability variable state, in addition to time-saving control, probability variable control is possible, which increases the probability that the display result of the special symbol will be a "jackpot" compared to the normal state. As a result, the probability variable state is also referred to as a probability variable state. The probability variable state not only increases the fluctuation efficiency of special symbols but also makes it easier to achieve a "jackpot," so it is considered a special state that is advantageous to players and distinct from the jackpot gaming state. The time-saving state and probability variable state continue until one of the predetermined termination conditions is met first, such as the execution of a predetermined number of special symbol games or the transition to the next jackpot gaming state. The termination condition, which is the execution of a predetermined number of special symbol games, is also referred to as a count-cut state. A count-cut time-saving state is also referred to as a count-cut time-cut state. A count-cut probability variable state is also referred to as a count-cut probability variable state.

[0038] The normal game state is a game state that is not included in advantageous states such as a jackpot game state that are advantageous to the player, predetermined states such as a small jackpot game state, or special states such as a time-saving state or a probability variable state. The normal state is a game state in which the probability that the display result in a normal game will be a "normal hit" and the probability that the display result in a special game will be a "jackpot" are controlled to be the same as the initial setting state of the pachinko game machine 1. The initial setting state of the pachinko game machine 1 is the control state after the initial setting process is performed without performing the predetermined recovery process after power-on, such as when a system reset is performed.

[0039] The state in which probability variable control is being executed is also called a high probability state, and the state in which probability variable control is not being executed is also called a low probability state. The state in which time-saving control is being executed is also called a high base state, and the state in which time-saving control is not being executed is also called a low base state. Combining these, the time-saving state is also called a low probability high base state, the probability variable state is a high probability high base state, and the normal state is a low probability low base state. The high probability state and low base state are also called a high probability low base state. Note that the pachinko gaming machine 1 may not include a probability variable state as a gaming state.

[0040] After the small win gaming state ends, there are cases where the game state is controlled to a big win gaming state based on the occurrence of a V win, and cases where a V win does not occur and the gaming state before the small win gaming state is changed remains unchanged. However, if the display result of the special game is a "small win" and a predetermined number of special games are executed in the count cutoff, the control of the time-saving state and the probability variable state may end and the game returns to the normal state. Note that the pachinko gaming machine 1 may not include a small win gaming state as a gaming state. In other words, the display result of the special pattern may not include a "small win."

[0041] The game state may be controlled to the time-saving state when a time-saving condition based on the number of times the variable display is executed is established. Such a time-saving state is also called a rescue time-saving state. The time-saving condition may be established when, after the power to the pachinko game machine 1 is turned on, after a jackpot occurs, or after the display result of the special game becomes "time-saving," a new jackpot game state or control to the time-saving state is not performed even if the variable display is executed a specific number of times.

[0042] (Progress of the production, etc.) The pachinko gaming machine 1 can execute various effects in accordance with the progress of the game. These effects include effects that notify the progress of the game and effects that add excitement to the game. These effects may include displaying various effect images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, vibrating the stick controller 31A or the push button 31B, or a combination of some or all of these, and may be executed using any effect device.

[0043] Effects that can be executed in accordance with the progress of the game include variable display of effect symbols. In response to the start of the first or second special symbol game, variable display of effect symbols begins in the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R on the screen of the image display device 5. When the determined special symbol that will be the display result in the first or second special symbol game is displayed in a static state, the determined effect symbol that will be the display result is displayed in a static state in the variable display of effect symbols. The determined effect symbol is composed of a combination of three effect symbols corresponding to the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R. During the period from the start to the end of the variable display of effect symbols, the display mode of the variable display of effect symbols may become a "reach" mode. A "reach" mode refers to a mode in which the effect symbols that have stopped on the screen of the image display device 5 constitute part of a jackpot combination, and the effect symbols that have not yet stopped continue to change. When the display mode of the variable display of the performance pattern becomes a reach mode, it is also said that a reach has been achieved.

[0044] A reach effect can be executed in response to the variable display of the effect symbols becoming a reach state. The pachinko gaming machine 1 can execute multiple types of reach effects so that the probability that the display result of the variable display will be a "jackpot" varies when the effect state differs. The "jackpot" probability corresponding to the effect state is also called the jackpot reliability or jackpot expectation. Reach effects include, for example, normal reach and super reach, which has a higher jackpot reliability than normal reach. In addition, depending on the execution time of the reach effect, it may also include short reach and long reach, which has a longer execution time than short reach.

[0045] When the display result of the special symbols is a "jackpot," a fixed effect symbol that corresponds to a predetermined jackpot combination is displayed as a static effect symbol on the screen of the image display device 5. As an example, the same effect symbols, such as a symbol showing the number "7," are displayed statically on a predetermined active line in the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R. In the case of a "probability jackpot" in which the game is controlled to a probability variable state after the jackpot gaming state ends, odd-numbered effect symbols, such as a symbol showing the number "7," may be displayed statically. In the case of a "non-probability jackpot" in which the game is not controlled to a probability variable state after the jackpot gaming state ends, even-numbered effect symbols, such as a symbol showing the number "6," may be displayed statically. A "non-probability jackpot" is also called a "normal jackpot." In this case, odd-numbered effect symbols are also called probability variable symbols. Even-numbered effect symbols are also called non-probability variable symbols or normal symbols. After a non-variable symbol has reached a reach state, an advancement effect may be executed that ultimately results in a "variable big win."

[0046] When the display result of the special pattern is a "small win," a fixed effect pattern that is a predetermined small win combination is displayed as a stopped effect pattern display result on the screen of the image display device 5. As an example, the same effect pattern, such as an effect pattern showing a number other than "7," may be displayed stopped on a predetermined effective line in the "left," "center," and "right" effect pattern display areas 5L, 5C, and 5R. A common fixed effect pattern may be displayed stopped when the display result of the special pattern is a "big win" and when it is a "small win."

[0047] When the display result of the special pattern is a "miss," there are cases where the display result is a static display without the variable display of the effect pattern becoming a reach state. In this case, the display result of the effect pattern is a static display of the confirmed effect pattern of a non-reach combination. A display result in which the confirmed effect pattern of a non-reach combination is stopped without becoming a reach state is also called a non-reach miss. When the display result of the special pattern is a "miss," there are cases where the variable display of the effect pattern becomes a reach state, and the display result is stopped after the reach effect is executed. In this case, the display result of the effect pattern is a static display of the confirmed effect pattern of a reach combination that is not a big win combination or a small win combination. A display result in which the confirmed effect pattern of a reach combination is stopped after becoming a reach state is also called a reach miss.

[0048] The effects that the pachinko gaming machine 1 can execute include variable display compatible displays such as reserved displays and active displays. In addition, for example, a preview effect that predicts the jackpot reliability can be executed during the variable display of the effect pattern. The preview effect may include a variable preview effect that predicts the jackpot reliability corresponding to the currently executed variable display, and a pre-read preview effect that predicts the jackpot reliability corresponding to the pre-execution variable display whose execution is on hold. The pre-read preview effect may be capable of executing a change effect that changes the display mode of a variable display compatible display such as a reserved display or active display to a mode that is different from the normal mode.

[0049] On the screen of the image display device 5, it may be possible to temporarily stop the effect symbols during the variable display of the effect symbols, and then resume the variable display, thereby executing a pseudo consecutive effect that makes one variable display appear as if it were multiple variable displays. The pseudo consecutive effect may be set so that the reliability of a jackpot is higher when the effect symbols are temporarily stopped and then the variable display is resumed many times than when the number of times is small. In the variable display of the effect symbols, there may be cases where the pseudo consecutive effect is executed before the reach state is reached, and cases where the pseudo consecutive effect is executed after the reach state is reached. In addition, in the variable display of the effect symbols, it may be possible to execute pseudo consecutive effects at multiple times.

[0050] During control of the jackpot gaming state, a jackpot effect can be executed to notify the player of the jackpot gaming state. The jackpot effect may include an effect to notify the number of rounds and an upgrade effect that suggests or notifies the player that the advantage of the jackpot gaming state will improve. During control of the small win gaming state, a small win effect can be executed to notify the player of the small win gaming state. By executing a common effect during control of the jackpot gaming state and during control of the small win gaming state, it may be possible to make it impossible or difficult for the player to recognize whether the current gaming state is a jackpot gaming state or a small win gaming state.

[0051] In a non-play state where a special game or the like is not being executed and a game is not in progress, a demonstration effect image can be displayed on the screen of the image display device 5. A demonstration effect image is also called a demo image. The display of a demo image is also called a demo display. The effect produced by the demo display is also called a customer waiting demo effect.

[0052] (Board configuration) The pachinko gaming machine 1 is equipped with a main board 11, a performance control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, and the like, as shown in Fig. 2. In addition, various other boards are arranged on the back of the pachinko gaming machine 1, such as a payout control board, an information terminal board, and a firing control board.

[0053] The main board 11 is the main control board and has the function of controlling the progress of the game in the pachinko gaming machine 1. The progress of the game includes the execution of various games and transitions between game states, such as the execution of special games with reserved game management, the execution of regular games with reserved game management, big win game state, small win game state, time-saving state, and probability variable state. The main board 11 is equipped with a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

[0054] The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer and can be configured with a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number circuit 104, and an I / O (Input / Output port) 105. Some or all of the ROM 101, RAM 102, and random number circuit 104 may be external to the game control microcomputer 100, or may be built into the game control microcomputer 100. The switch circuit 110 receives detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100. The various switches for game ball detection include, for example, a gate switch 21, start port switches such as a first start port switch 22A and a second start port switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a gaming ball has passed or entered and the switch has been turned on. The transmission of the detection signal indicates that the gaming ball has passed or entered. The solenoid circuit 111 can supply solenoid drive signals from the game control microcomputer 100 to the normal electric role solenoid 81, the big prize opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

[0055] The ROM 101 included in the game control microcomputer 100 is a non-volatile storage device that stores computer programs and data used for game control. The data stored in the ROM 101 includes table data constituting tables used for variable patterns, presentation control commands, and various other settings, judgments, and decisions. The RAM 102 included in the game control microcomputer 100 is a temporary storage device that provides a work area used for game control and a stack for saving data. The RAM 102 may be a backup RAM that stores data so that some or all of the memory contents can be restored within a predetermined period of time even if the power supply to the pachinko gaming machine 1 is interrupted. The RAM 102 is also referred to as RWM (Read / Write Memory). The work area of ​​the RAM 102 includes memory areas for storing various data used for game control, such as counters, timers, buffers, and storage areas for various codes and numerical values. The CPU 103 included in the game control microcomputer 100 can control the progress of the game in the pachinko game machine 1 by executing processing corresponding to the program stored in the ROM 101.

[0056] The random number circuit 104 provided in the game control microcomputer 100 counts updatable numerical data indicating various random number values ​​used when controlling the progress of a game. The random numbers used when controlling the progress of a game are also called game random numbers. Some or all of the game random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by the CPU 103.

[0057] 3 shows an example of a gaming random number. The gaming random number includes a random number MR1-1 for determining a special symbol, a random number MR1-2 for a winning symbol, a random number MR1-3 that is the initial value for the winning symbol, a random number MR2-1 for a normal winning symbol, a random number MR2-2 that is the initial value for the normal winning symbol, a random number MR3-1 for a normal symbol variation pattern, a random number MR3-2 for selecting a losing effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern.

[0058] The random number MR1-1 for determining special symbols is used to determine the display result of the special symbol, such as whether the display result of the special symbol is a "jackpot" or a "small jackpot." The random number MR1-2 for the winning symbol is used to select a confirmed special symbol from multiple special symbols, such as a jackpot symbol when the display result of the special symbol is a "jackpot," or a small jackpot symbol when the display result of the special symbol is a "small jackpot." The random number MR1-3, which serves as the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for the normal winning symbol is used to select a confirmed normal symbol from multiple normal symbols to be displayed when the display result of the variable display of normal symbols is a "normal jackpot." The random number MR2-2, which serves as the initial value for the normal winning symbol, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the normal symbol variation pattern as one of several patterns prepared in advance. The random number MR3-2 for selecting a miss effect is used to select whether or not the variable display of the effect pattern will be in a reach mode when the display result of the special symbol is a "miss." The random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbol. The variation pattern type of the special symbol is a group that pre-classifies the variation patterns of the special symbol based on, for example, the presentation mode during the variable display of the effect pattern, and may be configured to include one or more variation patterns. The random number MR3-4 for the variation pattern is used to select the variation pattern of the special symbol.

[0059] When making various judgments and decisions based on random number values, such as numerical data indicating the value of a gaming random number, the CPU 103 reads and refers to various tables from the ROM 101. Even when random number values ​​are not used, the CPU 103 may read and refer to necessary tables from the ROM 101 to make various judgments, decisions, settings, and the like.

[0060] The I / O 105 provided in the game control microcomputer 100 includes an input port to which various signals are input and an output port to which various signals are output. The various signals input to the input port of the I / O 105 may include detection signals from various switches transmitted via the switch circuit 110. The various signals output from the output port of the I / O 105 may include signals for controlling the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first reserve indicator 25A, the second reserve indicator 25B, the normal reserve indicator 25C, etc., and solenoid drive signals for driving the normal electric role solenoid 81, the large prize opening solenoid 82, the specific area solenoid 83, etc.

[0061] The main board 11 transmits presentation control commands corresponding to the progress of the game to the presentation control board 12 as part of the operation of controlling the progress of the game by the game control microcomputer 100. The presentation control commands are commands that specify or notify the progress of the game. The presentation control commands output from the main board 11 are relayed by the relay board 15 and supplied to the presentation control board 12. The presentation control commands may include commands that specify various determination results on the main board 11, such as the display result of the special game, the type of win, and the variation pattern; commands that specify the status of the game, such as the start and end of the variable display, the opening status of the big prize slot, the occurrence of a win, the number of reserved memories, and the game status; and commands that specify the occurrence of an error.

[0062] The performance control board 12 is a sub-control board independent of the main board 11, and has the function of receiving performance control commands and controlling performances based on the received performance control commands. The performances that can be controlled by the performance control board 12 include various performances according to the progress of the game, such as driving the movable body 32, as well as various notifications such as error notifications and notifications of power outage recovery. The performance control board 12 includes a performance control CPU 120, a ROM 121, a RAM 122, a display control unit 123, a random number circuit 124, and an I / O 125.

[0063] The performance control CPU 120 executes a program stored in ROM 121 to perform processing for controlling the execution of performance together with the display control unit 123. This processing is for realizing the various functions of the performance control board 12, and includes determining the performance to be executed. The performance control CPU 120 uses various data stored in ROM 121, such as data from various tables, and also uses RAM 122 as its main memory. The performance control CPU 120 may instruct the display control unit 123 to execute a performance based on detection signals from the controller sensor unit 35A and the push sensor 35B. The detection signal here is a signal that is output when an operation by a player is detected, and may be a signal that appropriately indicates the content of the operation.

[0064] The display control unit 123 includes a VDP (Video Display Processor), CGROM (Character Generator ROM), VRAM (Video RAM), etc., and controls the execution of mainly display-related effects based on instructions to execute effects from the effect control CPU 120. The display control unit 123 displays effect images on the screen of the image display device 5 by supplying a video signal corresponding to the effect to be executed to the image display device 5. The display control unit 123 also supplies a sound designation signal to the audio control board 13 and a lamp signal to the lamp control board 14. The sound designation signal designates the sound to be output from the speakers 8L and 8R. The lamp signal designates the on / off state of the game effect lamp 9. The supply of the sound designation signal and the lamp signal enables the audio output from the speakers 8L and 8R and the on / off state of the game effect lamp 9 in synchronization with the display of the effect image. The display control unit 123 may be capable of supplying a signal for operating the movable body 32 to a motor or solenoid of the movable body 32, or to a driver circuit that drives the movable body 32. A driver board for driving the movable body 32 may be provided separately from the performance control board 12.

[0065] The random number circuit 124 counts updatable numerical data indicating various random number values ​​used when controlling the execution of various performances. Random numbers used when controlling the execution of performances are also called performance random numbers. The performance random numbers may be updated by software such as a computer program executed by the performance control CPU 120. When making various judgments and decisions based on random number values, such as numerical data indicating the values ​​of performance random numbers, the performance control CPU 120 reads and references various tables from ROM 121. Even when random number values ​​are not used, the performance control CPU 120 may read and reference the necessary tables from ROM 121 to make various judgments, decisions, settings, etc.

[0066] The I / O 125 includes an input port for receiving, for example, performance control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I / O 125 may include an input terminal for a detection signal supplied from the controller sensor unit 35A and an input terminal for a detection signal supplied from the push sensor 35B. The output port of the I / O 125 may include an output terminal for a video signal supplied to the image display device 5, an output terminal for a sound designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14.

[0067] The sound control board 13 is equipped with various circuits for driving the speakers 8L and 8R, and drives the speakers 8L and 8R based on a sound designation signal from the display control unit 123, causing the speakers 8L and 8R to output the sound designated by the sound designation signal. The lamp control board 14 is equipped with various circuits for driving the game effect lamps 9, and drives the game effect lamps 9 based on a lamp signal from the display control unit 123, turning the game effect lamps 9 on or off in the manner designated by the lamp signal. In this way, the sound output from the speakers 8L and 8R and the turning on and off of the game effect lamps 9 can be controlled based on signals from the display control unit 123. Note that the performance control CPU 120 may perform some or all of the control of the sound output and the turning on and off of the lamps, such as supplying the sound designation signal and lamp signal, and the control of the movable body 32, such as supplying a signal to operate the movable body 32. Boards other than the main board 11, such as the performance control board 12, the audio control board 13, and the lamp control board 14, are also called sub-boards. As in the configuration example shown in Fig. 2, multiple sub-boards may be provided for different functions, or, unlike the configuration example shown in Fig. 2, one sub-board may be configured to have multiple functions.

[0068] The power supply board 17 can supply power from an AC power source, such as an external power source of 100V AC, such as a commercial power source, to electrical components including various control boards such as the main board 11 and the performance control board 12. The power supply board 17 includes, for example, a rectifier circuit for converting AC to DC, and a power supply circuit for converting a predetermined DC voltage to a specific DC voltage (e.g., 12V DC or 5V DC). The pachinko gaming machine 1 can switch between power-on and power-off by operating the power switch 91. The switch circuit 110 of the main board 11 receives a reset signal, a power-off signal, and a clear signal from the power supply board 17 and transmits them to the game control microcomputer 100. The reset signal is an operation stop signal for stopping control circuits such as the game control microcomputer 100, and can be output using any of a power supply monitoring circuit, a watchdog timer built-in IC, and a system reset IC. The power-off signal is turned off when the predetermined power supply voltage used in the pachinko gaming machine 1 exceeds a predetermined value, and is turned on when the period during which the predetermined power supply voltage is below the predetermined value continues for a power-off reference time or longer. The clear signal is turned on in response to, for example, pressing the clear switch 92 provided on the power supply board 17.

[0069] (operation) Next, the operation (action) of the pachinko gaming machine 1 will be described.

[0070] (Main operations of the main board 11) First, we will explain the main operations of the main board 11. When power supply to the pachinko gaming machine 1 starts, the game control microcomputer 100 starts up, and the CPU 103 executes main processing for game control.

[0071] FIG. 4 is a flowchart showing the game control main process P_MAIN executed by the CPU 103 on the main board 11. When the game control main process P_MAIN shown in FIG. 4 starts, the CPU 103 executes a power supply start response process P_POWER_ON (step S1) and then executes an RWM check process P_RWM_CHK (step S2). The power supply start response process P_POWER_ON in step S1 can execute initial settings of the game control microcomputer 100 in response to the start of power supply to the pachinko gaming machine 1. The initial settings of the game control microcomputer 100 may include initialization of output ports, setting of interrupt vectors, setting of internal device registers, and setting of specific registers. The RWM check process P_RWM_CHK in step S2 includes a checksum calculation process. The checksum data obtained as a result of the process is compared with the data stored in the checksum buffer. If the two data match, the contents stored in the RAM 102 are determined to be normal.

[0072] Next, it is determined whether a predetermined recovery condition is met (step S3). The recovery condition can be met when the clear signal corresponding to the operation of the clear switch 92 is in the OFF state, normal stored data is present in the checksum buffer, and the stored contents of the RAM 102 serving as the backup RAM are normal. When the power to the pachinko gaming machine 1 is turned on, if the clear switch 92 provided on the power supply board 17, for example, is pressed, an ON clear signal is input to the gaming control microcomputer 100. If such an ON clear signal is input, it is determined in step S3 that the recovery condition is not met. The checksum buffer stores checksum data calculated in the checksum calculation process when the backup monitoring timer measures the backup judgment time during the previous power outage. If the time value of the backup monitoring timer does not match a specific value corresponding to the backup judgment time, it is determined in step S3 that the recovery condition is not met. The backup data may be data stored in the gaming work area of ​​the RAM 102 serving as the backup RAM for gaming control. In step S3, it is determined whether or not the recovery conditions can be met based on the results of checking or inspecting the presence or absence of backup data and data errors by the RWM check process P_RWM_CHK in step S2.

[0073] If the recovery condition is met (Step S3; Yes), the backup setting process P_BACKUP_SET is executed (Step S4). The backup setting process P_BACKUP_SET uses a backup command transmission table to enable the performance control commands corresponding to the time of backup to be sent from the main board 11 to the performance control board 12. The backup setting process P_BACKUP_SET also clears the process codes, timers, counters, and flags specified by the backup setting table, making them initializeable.

[0074] If the recovery condition is not met (step S3; No), the initialization setting process P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET enables clear data to be transferred to the game work area, which is the work area in RAM 102. This initializes the game work area in RAM 102. Then, the initialization setting process P_INIT_SET uses the initialization command transmission table to enable transmission of the corresponding performance control command at the time of initialization from the main board 11 to the performance control board 12. The initialization setting process P_INIT_SET also clears the buffers, timers, pointers, and counters specified by the initialization setting table, thereby enabling them to be initialized.

[0075] Then, the control start setting process P_STACON is executed (step S6). The control start setting process P_STACON may include a wait process. The wait process executes a loop process and waits until a set waiting time has elapsed, thereby ensuring that sub-boards such as the performance control board 12 can be started. The control start setting process P_STACON may also include a specific count command transmission process or a command transmission process for chip individual number information. The specific count command transmission process enables a performance control command specifying the count value of a specific count counter to be transmitted from the main board 11 to the performance control board 12 when the power is turned on. The specific count counter is provided at a predetermined address in RAM 102 and is sufficient as long as it can count the remaining number of times until the number of executions of the variable display reaches a specific number corresponding to the time-saving condition. The command transmission process for chip individual number information enables a performance control command specifying the stored value of a chip individual number register to be transmitted from the main board 11 to the performance control board 12. The chip individual number register is included in the built-in register of the game control microcomputer 100, and may be any register capable of storing a different value assigned to each chip as the chip individual number.

[0076] The control start setting process P_STACON may include a startup out-of-area process. The startup out-of-area process is executed by reading a program stored in the non-game program area of ​​the ROM 101 in response to startup due to the start of power supply to the pachinko gaming machine 1. The startup out-of-area process may be, for example, a performance display RWM initial value setting process. The performance display RWM initial value setting process enables setting of an initial value for initial display by a 7-segment LED constituting the performance display monitor. The performance display monitor may be mounted on, for example, the main board 11 and may be capable of displaying information related to the setting value and the base. The setting value can be changed to one of multiple levels, such as six levels, when the pachinko gaming machine 1 is in a setting change state in which the settings can be changed, enabling setting of the probability that the display result of the special pattern will be a "jackpot." The base is calculated by dividing the number of prize balls paid out when a game ball passes through each prize slot, such as the starting prize slot, the general prize slot, and the large prize slot, by the number of game balls launched into the game area.

[0077] Following the control start setting process P_STACON in step S6, a timer interrupt counter is set (step S7). In step S7, a PTC counter output value is set so that a periodic timer interrupt occurs at predetermined intervals, such as every 4 ms (milliseconds). The game control main process P_MAIN then enters a loop. In this loop, interrupt prohibition is set (step S8), a random number update process P_TFINIT for initial value determination is executed (step S9), and an out-of-loop region process P_REGOUT is executed (step S10). Then, interrupt permission is set (step S11), and the process returns to step S8. Then, when the interrupt permission state is enabled, the CPU 103 is enabled to execute timer interrupt processing each time an interrupt request signal is input from the PTC to the CPU 103. This allows the CPU 103 to execute timer interrupt processing each time a predetermined time, such as every 4 ms, has elapsed.

[0078] Fig. 5 is a flowchart showing an example of the timer interrupt process P_PCT for game control. In the timer interrupt process P_PCT shown in Fig. 5, the power-off process P_POWER_OFF is executed (step S51). Next, it is determined whether the misconduct monitoring flag is "0" (step S52). When a magnetism is detected by the magnet sensor or when a radio wave is detected by the frame radio wave sensor, the misconduct monitoring flag is set to "1" corresponding to the ON state. In all other cases, the misconduct monitoring flag is set to "0" corresponding to the OFF state.

[0079] If the fraudulent activity monitoring flag is "1" (step S52; No), the game stop process P_GAME_STOP is executed (step S53). The game stop process P_GAME_STOP is simply a process that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and if it is in the off state, the execution of the payout process in the payout control board is stopped.

[0080] If the fraudulent activity monitoring flag is "0" (step S52; Yes), the switch processing P_SW is executed (step S54), the switch error notification processing P_CON_CHK is executed (step S55), the random number update processing P_RANDOM is executed (step S56), and the initial value determination random number update processing P_TFINIT is executed (step S57). In addition, the special symbol process processing P_TPROC is executed (step S58), the normal symbol process processing P_FPROC is executed (step S59), the information output processing P_JYOUHOU is executed (step S60), the prize ball processing P_PAY is executed (step S61), and the display processing P_HYOUZI is executed (step S62). Furthermore, other timer interrupt corresponding processing is executed (step S63). After that, the interrupt permission is set (step S64), and then the timer interrupt processing P_PCT is terminated.

[0081] The power-off processing P_POWER_OFF in step S51 judges the power confirmation signal transmitted from the power supply board 17, enabling checksum calculation processing and the like to be executed when power is turned off. The switch processing P_SW in step S54 judges the state of the input port, enabling updating of the switch-on buffer and the like. The switch error notification processing P_CON_CHK in step S55 can update the count value of a sensor-on counter specified, for example, by a switch error notification judgment table, and when the count value reaches a sensor abnormality error judgment value, enables error notification display. The random number update processing P_RANDOM in step S56 enables software random numbers among the game random numbers to be updated by software. The random number update processing P_TFINIT for initial value determination in step S57 enables software to update the game random numbers used as random number initial values.

[0082] The special symbol process P_TPROC in step S58 includes processes related to the variable display of special symbols and game states, such as managing the execution and reservation of special symbol games, controlling the jackpot and small jackpot game states, and controlling game states. The normal symbol process P_FPROC in step S59 includes processes related to the variable display of normal symbols and the state control of the second start winning slot, such as managing the execution and reservation of normal symbol games based on the detection signal from the gate switch 21 and controlling the opening and closing of the variable winning ball device 6B based on a "normal symbol win." The information output process P_JYOUHOU in step S60 sets an information output signal. The information output signal is a signal corresponding to information such as jackpot information, start information, and probability fluctuation information supplied to, for example, a hall management computer installed outside the pachinko gaming machine 1. The jackpot information indicates the number of jackpots that have occurred. The start information indicates the number of start wins. The probability fluctuation information indicates the number of times the game has entered the probability variable state. The prize ball processing P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. The prize ball command output counter addition process uses a prize ball number table to determine whether a switch is on, and when on is detected, updates the prize ball command output counter and the winning information output counter. The prize ball control process selects a process corresponding to the prize ball process code and controls the payout of prize balls based on the detection of game balls. The display process P_HYOUZI in step S62 sets the display for the first reserve indicator 25A, second reserve indicator 25B, regular reserve indicator 25C, and various other status indicator lights.

[0083] FIG. 6 is a flowchart showing an example of processing that can be executed in step S58 of FIG. 5 as the special symbol process P_TPROC. In the special symbol process P_TPROC, the CPU 103 sets a first start winning corresponding flag (step S101). The first start winning corresponding flag is set by executing a logical operation instruction or the like to reflect the state of the first start winning port switch 22A contained in the switch-on buffer in the flag register of the CPU 103. At this time, a zero flag in the flag register being in the on state indicates that the first start winning corresponding flag is in the off state. Conversely, a zero flag being in the off state indicates that the first start winning corresponding flag is in the on state. Next, a transfer instruction for setting a table pointer is issued to set the first start winning corresponding table (step S102). Then, it is determined whether the first start winning corresponding flag is on (step S103). When the first start winning corresponding flag is on (step S103; Yes), the start port switch passing process P_TZU_ON is executed (step S104).

[0084] If the first start winning corresponding flag is off in response to step S103 (step S103; No), or after the start winning switch passing process P_TZU_ON in step S104, the second start winning corresponding flag is set (step S105). The second start winning corresponding flag is set by executing a logical operation instruction or the like to reflect the state of the second start winning switch 22B contained in the switch-on buffer in the flag register of the CPU 103. At this time, the zero flag in the flag register being on indicates that the second start winning corresponding flag is off. Conversely, the zero flag being off indicates that the second start winning corresponding flag is on. Next, the second start winning corresponding table is set by a transfer instruction for setting the table pointer (step S106). After that, it is determined whether the second start winning corresponding flag is on (step S107). When the second start winning corresponding flag is on (step S107; Yes), the start port switch passing process P_TZU_ON is executed (step S108).

[0085] The start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102 to update the first reserved memory number and the total reserved memory number by adding 1 if the first reserved memory number is less than the upper limit, extracts a random number MR1-1 for determining a special symbol, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern, stores them in their respective random number buffers, and then transfers them to the first special symbol reserve buffer. Also, using the first reserved memory information designation command transmission table, a first reserved memory information designation command that specifies the first reserved memory number can be transmitted from the main board 11 to the performance control board 12. Then, a value indicating "1" is stored in the start port winning buffer as the start port winning designation value.

[0086] The start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106 to update the second reserved memory number and the total reserved memory number by adding 1 if the second reserved memory number is less than the upper limit, extracts the random number MR1-1 for determining the special symbol, the random number MR3-2 for selecting a miss effect, the random number MR3-3 for selecting a variation pattern type, and the random number MR3-4 for the variation pattern, stores them in their respective random number buffers, and then transfers them to the second special symbol reserve buffer. Also, using the second reserved memory information designation command transmission table, the second reserved memory information designation command that specifies the second reserved memory number can be transmitted from the main board 11 to the performance control board 12. Then, a value indicating "2" is stored in the start port winning buffer as the start port winning designation value.

[0087] A common start port switch passing process P_TZU_ON can be executed in steps S104 and S108. Meanwhile, the start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102, while the start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106. In this way, the common start port switch passing process P_TZU_ON is executed using different start port winning tables. Therefore, different data settings and controls are possible when the gaming ball enters the first start port and when it enters the second start port, using the common process. Note that the start port switch passing process P_TZU_ON may include a winning performance process using the extracted gaming random number.

[0088] If the second start winning flag is off in step S107 (step S107; No), or after the start gate switch passing process P_TZU_ON in step S108, a transfer command for setting a pointer sets a special symbol process processing jump table (step S109). The special symbol process processing jump table is an address management table that selects and executes processing corresponding to the read value of the special symbol process code. The special symbol process code can be updated to any of 00[H] to 0B[H] in accordance with the progress of game control in the pachinko gaming machine 1, and is also called a special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] can also indicate a binary number.

[0089] Following step S109, a transfer command for reading stored data is used to load the special symbol process code (step S110). Next, the 2-byte data selection process P_ABXEXEC is executed (step S111) to obtain the address of the process selected corresponding to the special symbol process code. The obtained address is set in a pointer. After this, a subroutine call command is issued to execute the process pointed to by the pointer (step S112), making it possible to execute the process selected corresponding to the special symbol process code. When the selected process is completed and a return command is issued to return to the special symbol process process P_TPROC, the special symbol process process P_TPROC is also completed, and a return command is issued to return to the timer interrupt process P_PCT for game control.

[0090] FIG. 7 shows a configuration example TT01 of a special symbol process processing jump table used in the special symbol process processing P_TPROC. The special symbol process processing jump table is configured by including table data that can set the address of the process selected corresponding to the special symbol process code in an internal register of the CPU 103 used as a pointer. The special symbol process processing jump table of the configuration example TT01 includes special symbol normal processing P_TNORMAL when the special symbol process code is 00 [H], special symbol fluctuation processing P_TSTART when the special symbol process code is 01 [H], special symbol stop processing P_TSTOP when the special symbol process code is 02 [H], small win opening pre-processing P_TLFAN when the special symbol process code is 03 [H], small win opening mid-processing P_TLOPEN when the special symbol process code is 04 [H], small win opening post-processing P_TLCLSF when the special symbol process code is 05 [H], and ... It includes table data that can set address values ​​corresponding to the small win discharge ball waiting process P_TLOUT when the other pattern process code is 06 [H], the small win end process P_TLEND when the special pattern process code is 07 [H], the pre-opening process P_TINT for the large prize opening when the special pattern process code is 08 [H], the opening process P_TOPEN for the large prize opening when the special pattern process code is 09 [H], the post-opening process P_TCLSF for the large prize opening when the special pattern process code is 0A [H], and the big win end process P_TEND when the special pattern process code is 0B [H] in the pointer.

[0091] The normal special symbol processing P_TNORMAL determines whether to start a special symbol game based on the presence or absence of stored reserved information, determines the special symbol display result using the random number MR1-1 for special symbol determination, determines the fixed special symbol to be displayed in the variable special symbol display, and determines the special symbol variation pattern. The special symbol display result includes "jackpot," "minor jackpot," "miss," etc., and if it is determined to be a "jackpot," it determines to control the game to a jackpot game state that is advantageous to the player. Furthermore, if the special symbol display result is a "jackpot," it determines which of several jackpot game states with different degrees of advantage to the player will be controlled to, depending on the jackpot symbol that becomes the fixed special symbol. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether to control to an advantageous state that is advantageous to the player, and can determine which of a plurality of types of advantageous states with different degrees of advantage to the player to control to. Furthermore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine to one of a plurality of types of variation patterns.

[0092] The special symbol change process P_TSTART measures the elapsed time since the special symbol began to change on the first special symbol display device 4A or the second special symbol display device 4B, and makes it possible to determine whether the special symbol change time corresponding to the change pattern has elapsed. The special symbol stop process P_TSTOP measures the elapsed time since the special symbol stopped changing on the first special symbol display device 4A or the second special symbol display device 4B, and makes it possible to determine whether the symbol stop time has elapsed. The symbol stop time may be set as the time for stopping the display of the special symbol when it is determined that the special symbol change time has elapsed in the special symbol change process P_TSTART. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are made according to the special symbol display result. For example, if the special pattern display result is a "big hit", the special pattern process code can be updated to 08 [H], if the special pattern display result is a "small hit", the special pattern process code can be updated to 03 [H], and if the special pattern display result is a "miss", the special pattern process code can be updated to 00 [H].

[0093] The small win opening pre-processing P_TLFAN, small win opening mid-processing P_TLOPEN, small win opening post-processing P_TLCLSF, small win discharge ball waiting process P_TLOUT, and small win end process P_TLEND are processes for controlling the progress of the game in the small win game state. The large prize opening pre-processing P_TINT, large prize opening mid-processing P_TOPEN, large prize opening post-processing P_TCLSF, and big win end process P_TEND are processes for controlling the progress of the game in the big win game state.

[0094] (Major operations of the performance control board 12) Next, we will explain the main operations of the performance control board 12. When the performance control board 12 receives a supply of power supply voltage from the power supply board 17 or the like, the performance control CPU 120 starts up and executes the performance control main process.

[0095] FIG. 8 is a flowchart showing the performance control main process S_MAIN executed by the performance control CPU 120 in the performance control board 12. When the performance control main process S_MAIN shown in FIG. 8 starts, the performance control CPU 120 executes a performance control initialization process S_INIT (step S71). The performance control initialization process S_INIT includes clearing RAM 122, setting various initial values, and setting registers for the timer circuit mounted on the performance control board 12. Next, an initial operation control process S_SYOKI is executed (step S72). The initial operation control process S_SYOKI enables control of the initial operation of the movable body 32, such as control to drive the movable body 32 to return it to its initial position and control to perform predetermined operation checks. Then, it is determined whether a timer interrupt flag is on (step S73). The timer interrupt flag is set to the on state every time a predetermined time, such as 2 ms (milliseconds), elapses based on the register setting for the timer circuit. Since the timer interrupt flag is off (step S73; No), step S73 is repeated and the process waits.

[0096] When the timer interrupt flag is on (step S73; Yes), the timer interrupt flag is cleared to the off state (step S74), and a command analysis process S_COMMAND is executed (step S75), a performance control process S_CPROC is executed (step S76), a performance random number update process S_RANDOM is executed (step S77), and a performance output process S_OUT is executed (step S78). Then, other timer interrupt response processes are executed (step S79), and the process returns to step S73.

[0097] The command analysis process S_COMMAND in step S75 enables the reading of the performance control commands stored in the performance control command receiving buffer and the setting and control corresponding to the read performance control commands. By executing the command analysis process S_COMMAND, the performance control CPU 120 can update the stored data indicating the flag status, the stored data in the register, and other stored data in the work area of ​​the RAM 122 in response to the performance control commands transmitted from the main board 11. The performance control process S_CPROC in step S76 enables the control of the execution of performances using various performance devices, including, for example, the display of performance images on the screen of the image display device 5, the audio output from the speakers 8L and 8R, the lighting or extinguishing of decorative light sources such as the game effect lamp 9 and decorative LEDs, and the drive control of the movable body 32. The control content of the performances using various performance devices only needs to be judged, determined, and set based on the performance control commands transmitted from the main board 11 and the results of processing by the performance control CPU 120. The performance random number updating process S_RANDOM in step S77 enables at least a part of the performance random numbers used on the performance control board 12 side to be updated by executing a program as software.

[0098] Fig. 9(A) is a flowchart showing an example of processing that can be executed in step S76 shown in Fig. 8 as the performance control process processing S_CPROC. The performance control CPU 120 executes the look-ahead performance setting processing S_SAKI_SET in the performance control process processing (step S151). The look-ahead performance setting processing S_SAKI_SET enables judgment, decision, and setting regarding the execution of the look-ahead preview performance, for example, based on the performance control command at the time of the start winning transmitted from the main board 11. In addition, the look-ahead performance setting processing S_SAKI_SET makes it possible to update the hold display based on the number of hold memories specified from the performance control command.

[0099] After the look-ahead effect setting process S_SAKI_SET in step S151, a effect control process jump table is set by a transfer command that sets a pointer (step S152). The effect control process jump table is an address management table that selects and makes executable a process corresponding to the read value of the effect control process code. The effect control process code can be updated and set to any of 00[H] to 0A[H] in accordance with the progress of effect control in the pachinko gaming machine 1, and is also called the effect process code. The effect control process code is loaded by a transfer command that reads out stored data (step S153). The address of the process to be selected corresponding to the effect control process code thus acquired is set in the effect control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected corresponding to the effect control process code becomes executable.

[0100] 9(B) shows an example of the configuration TT02 of the performance control process jump table used in the performance control process S_CPROC. The performance control process jump table includes table data that can set the address of the process selected corresponding to the performance control process code in a register used as a performance control pointer. The effect control process processing jump table of configuration example TT02 includes table data that can set address values ​​corresponding to the following in the effect control pointer: waiting for a change pattern command when the effect control process code is 00 [H], effect pattern change start processing when the effect control process code is 01 [H], effect pattern change in progress processing when the effect control process code is 02 [H], effect pattern change stop processing when the effect control process code is 03 [H], small win display processing when the effect control process code is 04 [H], small win open processing when the effect control process code is 05 [H], small win end effect processing when the effect control process code is 06 [H], big win display processing when the effect control process code is 07 [H], round processing when the effect control process code is 08 [H], post-round processing when the effect control process code is 09 [H], and big win end effect processing when the effect control process code is 0A [H].

[0101] The waiting-for-reception process for a variation pattern command determines whether a variation pattern designation command transmitted from the game control microcomputer 100 on the main board 11 has been received. If it is determined that a variation pattern designation command has been received, the presentation control process code is updated to 01 [H], which corresponds to the presentation pattern variation start process. If it is determined that a variation pattern designation command has not been received, the demo display can be controlled. The presentation pattern variation start process enables the start of a variation-time presentation corresponding to a special game. For example, in response to the variation pattern command transmitted from the main board 11, it enables the selection of a presentation pattern to be used to control the variation-time presentation and the start of updating the presentation process timer that measures the presentation execution time. The presentation pattern variation process controls the switching timing of each presentation element that constitutes the presentation pattern and determines whether the presentation execution time has elapsed based on the timing value of the presentation process timer. If it is determined that the presentation execution time has elapsed, the presentation control process code is updated to 03 [H], which corresponds to the presentation pattern variation stop process. The effect pattern change stop process enables control of the end of the effect during change and control of the display of the effect result corresponding to the determined special pattern based on the establishment of the end condition of the effect during change, such as the elapse of the effect execution time or the reception of a effect pattern determination command. At this time, the effect control process code is updated and various settings are made according to the display result of the variable display. For example, if the display result of the variable display is a "big hit," the effect control process code can be updated to 07 [H], if the display result of the variable display is a "small hit," the effect control process code can be updated to 04 [H], and if the display result of the variable display is a "miss," the effect control process code can be updated to 00 [H].

[0102] The small win display process, small win opening process, and small win end effect process are processes for controlling the progress of effects corresponding to the small win game state. The big win display process, round process, post-round process, and big win end effect process are processes for controlling the progress of effects corresponding to the big win game state.

[0103] (Variations of basic explanations, etc.) The pachinko gaming machine 1 is not limited to the configuration, functions, processing, and operation described in the basic description and other explanations, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not need to have all the technical features described in the embodiments, but may have some of the configuration described in the embodiments so as to solve at least one problem in the prior art. When a subordinate concept is described in the embodiments, an invention of a generic concept using homologous or similar matters, or an invention of a generic concept using common properties, is included in the present invention, and may have some of the structure or characteristics described in the embodiments so as to solve at least one problem in the prior art.

[0104] The pachinko game machine 1 may be a payout type game machine that pays out a predetermined number of game media as a prize when a prize is won, or it may be an enclosed type game machine that encloses game media and awards points when a prize is won.

[0105] The display during the variable display of the special symbol may be, for example, only one type of symbol, such as a symbol indicating "-", and the variable display may be such that this symbol is repeatedly displayed and turned off. One type of symbol may be displayed during the variable display, and this symbol may not be displayed when the variable display is stopped. For example, the display result may be a non-display state in which the symbol indicating "-" is not displayed and no special symbol is displayed.

[0106] The pachinko gaming machine 1 may be configured to change the probability of winning a jackpot and the payout rate in response to multiple setting values. For example, in the normal special symbol processing of the special symbol process, the probability of winning a jackpot and the payout rate may be changed by using a different jackpot determination value for each setting value. As a specific example, the setting values ​​are divided into six levels, from 1 to 6, with 6 representing the highest probability of winning a jackpot, and the probability of winning a jackpot decreasing as the value decreases in the order of 6, 5, 4, 3, 2, and 1. In this case, setting 6 as the setting value provides the highest advantage to the player, and the advantage gradually decreases as the value decreases in the order of 6, 5, 4, 3, 2, and 1. If the probability of winning a jackpot changes depending on the setting value, the payout rate may also change depending on the setting value. While the probability of winning a jackpot remains constant regardless of the setting value, the number of rounds in a jackpot game state may change depending on the setting value. The pachinko gaming machine 1 may be configured to be able to set one of a plurality of setting values ​​that differ in the degree of advantage to the player. The setting value set in the pachinko gaming machine 1 may be notified by a setting value designation command being sent from the main board 11 to the effect control board 12. During execution of the variable display, a setting suggestion effect may be executed that suggests the setting value in the pachinko gaming machine 1 at a predetermined rate. The suggestion regarding the setting value in the pachinko gaming machine 1 is not limited to suggesting the setting value in the pachinko gaming machine 1, and may, for example, suggest whether the setting value in the pachinko gaming machine 1 has been changed. The setting suggestion effect may suggest the likelihood of a jackpot through any effect, and may also suggest the setting value in the pachinko gaming machine 1.

[0107] Instead of some or all of the suggestions regarding the control of the jackpot gaming state, or together with some or all of the suggestions regarding the control of the jackpot gaming state, suggestions regarding the control of a state that is advantageous to the player, different from the jackpot gaming state, may be made. For example, a suggestion regarding a probability variable state that is controlled after the jackpot gaming state ends may be made. In addition, suggestions regarding a state in which any game value that is advantageous to the player is awarded as an advantageous state may be made, depending on whether or not it is controlled.

[0108] The invention relating to gaming machines is not limited to pachinko gaming machines 1, but can also be applied to slot machines as appropriate. A slot machine can execute a game in which medals are inserted, a predetermined bet amount is set, multiple types of symbols are rotated in response to the player's operation of a control lever, and when the symbols are stopped in response to the player's operation of a stop button, a predetermined number of medals is paid out to the player if a specific combination of symbols is formed. In a slot machine, advantageous states that are advantageous to the player may include, for example, one or more of so-called bonuses, such as a big bonus, regular bonus, RT, AT, ART, and CZ.

[0109] The programs and data for realizing various controls, including the progress of the game and the execution of the effects, may be distributed and provided to a computer device included in a gaming machine such as the pachinko gaming machine 1 via a removable recording medium, or may be distributed and provided by being pre-installed in a storage device of the computer device. Also, the gaming machine may have a communication processing unit that can be connected to an external device on a network via a communication line or the like, and distribute and provide the programs and data by downloading them from the external device. The execution of the game and effects may also be executable by inserting a removable recording medium, or by temporarily storing the programs and data downloaded via a communication line or the like in internal memory, or by directly executing them using hardware resources of an external device on a network connected via a communication line or the like, or by exchanging data with another computer device or the like via a network.

[0110] When comparing various percentages, such as the decision percentage of a process or data, or the execution percentage of a performance, expressions such as "high," "low," or "different" may include cases where one is a percentage of "0%" or "100%." ​​For example, for one decision result or execution content, a percentage of "0%" may include cases where there is no decision or execution, or a percentage of "100%" may include cases where there is always a decision or execution.

[0111] (Explanation about feature part 01AK) FIG. 10-1 shows an example of the configuration of a game control microcomputer 100 with respect to the characteristic section 01AK. The game control microcomputer 100 with the characteristic section 01AK includes, in addition to a ROM 101, a RAM 102, and a CPU 103, an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, an address decode circuit 137, a free-running counter 138, and a serial communication circuit 139. The random number circuit 104 shown in FIG. 2 includes a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I / O 105 shown in FIG. 2 includes a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

[0112] The external bus interface 131 is a bus interface that has an interface function between the external bus and internal bus of the chips that make up the game control microcomputer 100, and a function for controlling the direction of the address bus, data bus, and various control signals. For example, the external bus interface 131 may be connected to an external memory or external input / output device external to the game control microcomputer 100, and may be capable of sending and receiving address signals, data signals, various control signals, and the like to and from these external devices. The external bus interface 131 may include an internal resource access control circuit that controls access from external devices to the internal data of the game control microcomputer 100.

[0113] The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the external control clock terminal EXC. A control clock generated by a control clock generation circuit provided in the game control microcomputer 100 may be input to the external control clock terminal EXC. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. The internal system clock SCLK can also be output from the system clock output terminal CLKO to the outside of the game control microcomputer 100. Alternatively, the internal system clock SCLK may be restricted from being output to the outside of the game control microcomputer 100, making it difficult to externally identify the operating state of the game control microcomputer 100.

[0114] The unique information storage circuit 133 can store, for example, multiple types of unique information that become internal information of the game control microcomputer 100. For example, the unique information storage circuit 133 may store a ROM code, a chip individual number, and an ID number as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from data stored in a predetermined area of ​​the ROM 101. The chip individual number and ID number are numbers assigned to the game control microcomputer 100 when it is manufactured and represent different values ​​for each chip. The chip individual number may be readable by a user program such as a game program, while the ID number may be set to be unreadable by the user program. The unique information storage circuit 133 may be included in a predetermined area of ​​the ROM 101 or in an internal register of the game control microcomputer 100.

[0115] The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. Resets that can be controlled by the reset controller 134 include a system reset and a user reset. A system reset occurs when the input signal to the external system reset terminal XSRST remains low for a certain period of time. A user reset occurs due to a specific factor, such as a timeout signal from the watchdog timer 134A or an IAT (Independent Autonomous Travel) prohibition. The reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to a monitoring time and can count down by periodically decrementing the timer value by one. When the timer value reaches "0" and a timeout occurs, the watchdog timer 134A can output a timeout signal to reset the game control microcomputer 100 and restart it. This allows the watchdog timer 134A to measure the monitoring time and reset the game control microcomputer 100 when it determines that the monitoring time has elapsed. The watchdog timer 134A can be set to enable or disable operation according to, for example, a game program.

[0116] The interrupt controller 135 can control various interrupt requests generated inside and outside the game control microcomputer 100. Interrupts that can be controlled by the interrupt controller 135 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that can be accepted unconditionally even when the CPU 103 is in an interrupt disabled state, and is generated when the input signal of the external non-maskable interrupt terminal XNMI (also used as input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt that can be enabled or disabled for acceptance of interrupt requests by a setting command of the CPU 103, and multiple interrupts can be executed by setting priority levels. The maskable interrupt INT may be generated by any or all of a number of different types of interrupt factors, including the input signal of the external maskable interrupt terminal XINT (also used as input port PI5) being at a low level for a certain period of time, a timeout occurring in the timer circuit 136, or the storage of numerical data indicating a random number value in the random number value register by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B.

[0117] The timer circuit 136 includes a PTC (Programmable Timer Counter) as a timer counter corresponding to the three channels PTC0 to PTC2, and enables real-time interrupt generation and time measurement. Each of the channels PTC0 to PTC2 of the timer circuit 136 uses a count clock generated based on the internal system clock SCLK, and it is sufficient if it can update the timer value in response to a signal change in the count clock, such as the falling edge when the clock signal changes from high level to low level.

[0118] The address decode circuit 137 can decode various signals obtained from each functional block inside the game control microcomputer 100, and can output a chip select signal, which is a decoded signal for an external device. The chip select signal selectively enables the internal circuit of the game control microcomputer 100 or an external device serving as a peripheral device, enabling access from the CPU 103. The output terminal that the address decode circuit 137 can use may be a multi-function terminal that can selectively output a parallel output signal from the POP 105B, a serial transmission signal from the serial communication circuit 139, a clock output signal from the clock circuit 132, and the chip select signal generated by the address decode circuit 137.

[0119] The free-running counter 138 includes counter circuits corresponding to four channels FRC0 to FRC3, and can update its count value independently of the operation of the CPU 103. Each of the channels FRC0 to FRC3 of the free-running counter 138 can be activated by an independent update clock, and its operation can be stopped or changed, for example, according to a game program. The count value of the free-running counter 138 can be stored in a hard latch register in response to a latch signal transmitted from an input terminal that serves as a latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program, for example.

[0120] The serial communication circuit 139 includes serial communication units corresponding to three channels SCU0, SCU1, and STU2, enabling communication with external devices via serial communication. Each of the channels SCU0, SCU1, and STU2 of the serial communication circuit 139 can process communication data in, for example, full-duplex, asynchronous, or standard NRZ (Non Return to Zero) format. The channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transmitting / receiving circuit capable of bidirectionally transmitting and receiving serial data with an external circuit. The channel STU2 of the serial communication circuit 139 is included in a second channel transmitting circuit capable of only unidirectionally transmitting serial data with an external circuit. For example, the channel SCU0 of the serial communication circuit 139 is used for data communication with the dispensing control board. The channel SCU1 of the serial communication circuit 139 is used for data communication with the performance control board 12. Instead of the channel SCU1 of the serial communication circuit 139, the channel STU2 of the serial communication circuit 139 may be used for data communication with the performance control board 12.

[0121] The 16-bit random number circuit 104A includes random number generation units corresponding to four channels RL0-RL3, each of which operates independently to generate random numbers ranging from 0 to 65535 using numerical data representing 16-bit pseudo-random numbers. The maximum value of the random numbers generated by each of channels RL0-RL3 of the 16-bit random number circuit 104A can be set to any value between 256 and 65535. Setting such a maximum value allows for initial setup to select a random number activation method so that the numerical data representing the random number starts updating. Alternatively, each of channels RL0-RL3 of the 16-bit random number circuit 104A can be initially set to select a random number activation method so that it is automatically activated when the gaming control microcomputer 100's operating mode transitions from security mode to user mode. The 16-bit random number circuit 104A can update the random number MR1-1 for determining special symbols using channel RL0, and the random number MR3-2 for selecting a losing effect using channel RL2.

[0122] The 8-bit random number circuit 104B includes random number generation units corresponding to four channels RS0 to RS3, each of which operates independently to generate random numbers ranging from 0 to 255 using numerical data representing 8-bit pseudo-random numbers. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value between 16 and 255. Setting such a maximum value allows for initial setup to select a random number startup method so that updating of the numerical data representing the random number value begins. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B may be initially set to select a random number startup method so that it is automatically started when the operating mode of the game control microcomputer 100 transitions from security mode to user mode. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the type of variation pattern using channel RS1, can update the random number MR3-4 for the variation pattern using channel RS2, and can update the random number MR3-1 for the normal pattern variation pattern using channel RS3.

[0123] The PIP 105A incorporates, for example, an 8-bit wide input-only port, allowing various signals to be input from outside the game control microcomputer 100. The PIP 105A can use input terminals corresponding to the input ports PI0 to PI7. The input port PI5 uses a multi-function terminal that can also be used as the external maskable interrupt terminal XINT. The input port PI6 uses a multi-function terminal that can also be used as the external non-maskable interrupt terminal XNMI. The input port PI7 uses a multi-function terminal that can also be used as the receiving terminal of channel SCU0 in the serial communication circuit 139. The POP 105B incorporates, for example, an 11-bit wide output-only port, allowing various signals to be output to outside the game control microcomputer 100. The POP 105B can supply parallel output signals corresponding to the output ports PO0 to PO7 and PO10 to PO12 to the address decode circuit 137.

[0124] FIG. 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in FIG. 10-2, the area of ​​addresses 0000[H] to 3FFF[H] is allocated to ROM 101 and includes a game program area, a game data area, a non-game program area, a non-game data area, a ROM comment area, a program management area, and other unused areas. The area of ​​addresses F000[H] to F3FF[H] is allocated to RAM 102 and includes a game work area, a game stack area, a non-game work area, a non-game stack area, and other unused areas. The area of ​​addresses FE00[H] to FEBF[H] is a function setting register area allocated to the built-in register of the game control microcomputer 100. The area of ​​addresses FF00[H] to FFFF[H] is a function control register area allocated to the built-in register of the game control microcomputer 100.

[0125] In the ROM 101, the game program area can store a game program, which is a computer program related to the progress of a game. The game data area can store game data used by the game program. The non-game program area can store a non-game program, which is a computer program related to control and processing other than the progress of a game. The non-game data area can store non-game data used by the non-game program. These programs and data stored in the ROM 101 are designed and created in advance by the manufacturer of the pachinko gaming machine 1, which is the user of the game control microcomputer 100. Therefore, the game program and non-game program are included in the user program. The game data and non-game data are included in the user data.

[0126] The memory area of ​​ROM 101 is provided with a game program area capable of storing game programs related to the progress of a game, and a non-game program area for control and processing unrelated to the progress of a game, and the area before the non-game program area to which a later address is assigned is an unused area with a memory area equal to or larger than the boundary byte number, for example, 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of a game, and the non-game program area capable of storing non-game programs related to control and processing unrelated to the progress of a game, facilitating the design and management of the programs and data stored in ROM 101.

[0127] The memory area of ​​ROM 101 is provided with a game program area capable of storing a game program related to the progress of a game, and a game data area capable of storing game data used by the game program, each of which is separately provided, and the area before the game data area to which a later address is assigned of the game program area and the game data area is an unused area with a memory area of ​​more than the boundary byte number, for example, 16 bytes. This makes it easy to identify the game program area capable of storing a game program related to the progress of a game, and the game data area capable of storing game data used by the game program, facilitating the design and management of the programs and data stored in ROM 101.

[0128] The ROM 101 has a storage area that includes a non-game program area capable of storing non-game programs related to control and processing unrelated to game progress, and a non-game data area capable of storing non-game data used by the non-game programs, which are arranged adjacent to each other. The area behind the non-game program area assigned an earlier address is the non-game data area, and the area in front of the non-game data area assigned a later address is the non-game program area. This allows the non-game program area capable of storing non-game programs related to control and processing unrelated to game progress and the non-game data area capable of storing non-game data used by the non-game programs to be located in storage areas assigned consecutive addresses, enhancing integration and facilitating the design and management of the programs and data stored in the ROM 101. An unused area of ​​storage space equal to or greater than the boundary byte number may be provided between the non-game program area and the non-game data area to make it easier to identify the non-game program area and the non-game data area.

[0129] In the storage areas of the ROM 101, data indicating a value of "0" may be stored in all unused storage areas. This makes it easy to distinguish between the game program area and game data area, the non-game program area and non-game data area, and the unused storage areas. Furthermore, if invalid data is stored in an unused storage area, this data can be easily detected. Note that data indicating a value of "1" may be stored in all unused storage areas. In other words, data indicating the same value may be stored in all unused storage areas. This makes it easy to distinguish between multiple types of storage areas, and to easily detect invalid stored data.

[0130] In RAM 102, the game work area can be used as a work area when CPU 103 executes a game program. The game stack area can be used as a stack area when CPU 103 executes a game program. The non-game work area can be used as a work area when CPU 103 executes a non-game program. The non-game stack area can be used as a stack area when CPU 103 executes a non-game program.

[0131] The game program area and game data area provided in the storage area of ​​ROM 101, and the game work area and game stack area provided in the storage area of ​​RAM 102 are included in the storage area for game control. The non-game program area and non-game data area provided in the storage area of ​​ROM 101, and the non-game work area and non-game stack area provided in the storage area of ​​RAM 102 are included in the storage area for non-game control.

[0132] The ROM comment area provided in the storage area of ​​the ROM 101 stores data indicating any program-specific information, such as the program title, version, etc. The program management area provided in the storage area of ​​the ROM 101 can store setting information required for the internal settings of the game control microcomputer 100 so that the CPU 103 can execute game programs and non-game programs.

[0133] 10-3 shows a main setting example AKA01 of an address included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is the first area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, and the serial communication circuit 139.

[0134] In the setting example AKA01, the setting values ​​of the WDT start register at address FE1A[H] and the WDT clear register at addresses FE1B[H] to FE1C[H] are invalid values ​​corresponding to unused states. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. As the setting value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to an enabled state for the maskable interrupt IR0. As the setting values ​​of the registers related to channel PTC0 of the timer circuit 136 at addresses FE01[H] to FE03[H] are valid values, the timekeeping function using channel PTC0 of the timer circuit 136 is set to an enabled state. As the setting values ​​of the registers related to channels PTC1 and PTC2 of the timer circuit 136 at addresses FE04[H] to FE09[H] are invalid values ​​corresponding to unused states, the timekeeping function using channels PTC1 and PTC2 of the timer circuit 136 is set to an unused state.

[0135] The set values ​​of the registers at addresses FE0A[H] to FE11[H] relating to channels SCU0 and SCU1 of the serial communication circuit 139 are valid, so that the serial communication function using channels SCU0 and SCU1 of the serial communication circuit 139 is set to an available state. The set values ​​of the registers at addresses FE12[H] to FE14[H] relating to channel STU2 of the serial communication circuit 139 are invalid, so that the serial communication function using channel STU2 of the serial communication circuit 139 is set to an unused state.

[0136] When the register settings at addresses FE2C[H] to FE2E[H] related to the input ports of PIP 105A are valid values, the signal input function using each input port is set to an enabled state. When the register settings at addresses FE36[H] to FE4A[H] related to the random number circuit 104 include valid and invalid values, the random number generation function using the random number circuit 104 is set to an enabled state for channels corresponding to valid values, and to an unused state for channels corresponding to invalid values. For example, of the four channels RL0 to RL3 in the 16-bit random number circuit 104A, channels RL0 and RL2, whose corresponding maximum value setting register settings are valid values, have their random number generation function set to an enabled state, while channels RL1 and RL3, whose corresponding maximum value setting register settings are invalid values, have their random number generation function set to an unused state. Furthermore, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, channels RS1 to RS3 whose corresponding maximum value setting registers have valid settings have their random number generation functions set to an available state, and channel RS0 whose corresponding maximum value setting register has an invalid setting has its random number generation function set to an unused state.

[0137] In this way, it is sufficient that the various circuits included in the game control microcomputer 100 can be set to either an enabled state or an unused state for the various functions using the respective circuits in accordance with the setting values ​​in the function setting register area. The function setting register area is not limited to the various circuits included in the game control microcomputer 100, and may be a first area for setting any function.

[0138] 10-4 shows a main setting example AKA02 of the address included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area is a second area for function control using various circuits included in the game control microcomputer 100, such as the RAM 102, the random number circuit 104, the PIP 105A, and the serial communication circuit 139.

[0139] In the setting example AKA02, the RWM access protect register at address FF00[H] corresponds to a setting value of 00[H] or 01[H], enabling function control to prohibit or permit access to the RWM RAM 102. The internal information register at address FF01[H] is set to an invalid value corresponding to unused status, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as an abnormality in the random number update status, an abnormality in the frequency of the random number update clock, a system reset occurrence, a WDT timeout occurrence, or an IAT occurrence, but in this embodiment it is not used in an unused state.

[0140] Each register at addresses FF25[H] to FF28[H] can store a setting value used to control the serial communication function when the serial communication function using channel SCU0 of the serial communication circuit 139 is available. Each register at addresses FF29[H] to FF2C[H] can store a setting value used to control the serial communication function when the serial communication function using channel SCU1 of the serial communication circuit 139 is available.

[0141] Each register with addresses FF60[H] to FF67[H] can store random numbers that can be acquired using the soft latch random number acquisition function of the 16-bit random number circuit 104A. Of these, the RL0 soft latch random number register with addresses FF60[H] to FF61[H] can store random numbers that can be generated by channel RL0 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by the soft latch. The RL1 soft latch random number register with addresses FF62[H] to FF63[H] can store random numbers that can be generated by channel RL1 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by the soft latch. The RL2 soft latch random number register with addresses FF64[H] to FF65[H] can store random numbers that can be generated by channel RL2 of the 16-bit random number circuit 104A when numerical data indicating the value is acquired by the soft latch. The RL3 soft latch random number register at addresses FF66[H] to FF67[H] can store random numbers that can be generated by channel RL3 provided in the 16-bit random number circuit 104A when numerical data indicating the value of the random number is acquired by the soft latch.

[0142] Each register at addresses FF68[H] to FF6B[H] can store random numbers that can be acquired using the soft latch random number acquisition function of the 8-bit random number circuit 104B. Of these, the RS0 soft latch random number register at address FF68[H] can store random numbers that can be generated by channel RS0 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS1 soft latch random number register at address FF69[H] can store random numbers that can be generated by channel RS1 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS2 soft latch random number register at address FF6A[H] can store random numbers that can be generated by channel RS2 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS3 soft latch random number register at address FF6B[H] can store the random numbers that can be generated by channel RS3 provided in the 8-bit random number circuit 104B when the numeric data indicating the value of the random number is acquired by the soft latch.

[0143] The RL0 hard latch random number registers "0" at addresses FF88[H] to FF89[H] and "1" at addresses FF98[H] to FF99[H] can store random numbers generated by channel RL0 of the 16-bit random number circuit 104A when the numeric data representing the random number is acquired by the hard latch. The RL0 hard latch random number register includes multiple storage areas corresponding to multiple register numbers, allowing different hard latch conditions to be set for the storage areas of different register numbers. For example, the RL0 hard latch random number register "0" corresponding to register number "0" can establish a hard latch condition when the game ball detection signal from the first start gate switch 22A is in the ON state. In contrast, the RL0 hard latch random number register "1" corresponding to register number "1" can establish a hard latch condition when the game ball detection signal from the second start gate switch 22B is in the ON state. As a result, the RL0 hard latch random number register number "0" can be stored when the numerical data indicating the value of the random number MR1-1 for determining a special symbol, which is obtained in response to the occurrence of a first start winning, is acquired by the hard latch.The RL0 hard latch random number register number "1" can be stored when the numerical data indicating the value of the random number MR1-1 for determining a special symbol, which is obtained in response to the occurrence of a second start winning, is acquired by the hard latch.

[0144] The registers with addresses FFF0[H] to FFF2[H] and FF35[H] can store signal values ​​input to each input port, corresponding to whether the signal input function using the input port of the PIP 105A is enabled. Of these, the input port number "0" register with address FFF0[H] can store a signal value input to the input port with port number "0" provided in the PIP 105A. The input port number "1" register with address FFF1[H] can store a signal value input to the input port with port number "1" provided in the PIP 105A. The input port number "2" register with address FFF2[H] can store a signal value input to the input port with port number "2" provided in the PIP 105A. The input port number "3" register with address FF35[H] can store a signal value input to the input port with port number "3" provided in the PIP 105A.

[0145] In this way, it is sufficient that the various circuits included in the game control microcomputer 100 are capable of controlling their respective operating states in accordance with the values ​​stored in the function control register area, etc. Furthermore, the various circuits included in the game control microcomputer 100 may be capable of updating the values ​​stored in the function control register area in accordance with their respective operating states, etc. The function control register area is not limited to the various circuits included in the game control microcomputer 100, but may also be a second area for controlling any function.

[0146] Figure 10-5 is a diagram for explaining a setting example in this embodiment for the gaming random numbers shown in Figure 3. The gaming random numbers shown in Figure 3 can be classified into random numbers used to determine the display result in the variable display of special symbols, random numbers used to determine the display result in the variable display of normal symbols, and random numbers used to determine the display mode in the variable display of special symbols and normal symbols, depending on their respective uses.

[0147] FIG. 10-5(A) shows a setting example AKA11 of a gaming random number used to determine the display result in the variable display of special symbols. The gaming random numbers in setting example AKA11 include a random number MR1-1 for determining special symbols, a random number MR1-2 for a winning symbol, and a random number MR1-3 serving as the initial value for the winning symbol. For example, the random number MR1-1 for determining special symbols can be used to determine whether the special symbol display result is a "big win" or a "small win." The random number MR1-2 for the winning symbol can be used to determine the designated value for the big win symbol or the designated value for the small win symbol corresponding to the confirmed special symbol when the special symbol display result is a "big win" or a "small win." The random number MR1-3 serving as the initial value for the winning symbol can be used to set the initial value of the random number MR1-2.

[0148] The range of random number MR1-1 is the range of values ​​within which random number MR1-1 can be updated, from "0" to "65535." The magnitude of random number MR1-1 is the total number of random values ​​included in the update range of random number MR1-1, which is "65536," corresponding to the range of random number MR1-1, from "0" to "65535." Because the magnitude of random number MR1-1 is "65536," the total number of random values ​​included in the update range is not a prime number. The number of bytes of numeric data used to update the value of random number MR1-1 is "2." The maximum value of random number MR1-1 is set by initializing a register provided corresponding to the 16-bit random number circuit 104A. The random number MR1-1 is updated by hardware update using the 16-bit random number circuit 104A. The update condition for random number MR1-1 is the system clock input to the 16-bit random number circuit 104A. The acquisition conditions for the random number MR1-1 include a hard latch corresponding to the start winning and a software readout to the random number buffer corresponding to the start winning. The period of the random number MR1-1 is 4.369 [ms].

[0149] The range of random number MR1-2 is the range of values ​​within which random number MR1-2 can be updated, from "0" to "199." The size of random number MR1-2 is the total number of random values ​​included in the update range of random number MR1-2, which is "200," corresponding to the range of "0" to "199" for random number MR1-2. Since the size of random number MR1-2 is "200," the total number of random values ​​included in the update range is not a prime number. The number of bytes of numerical data used to update the value of random number MR1-2 is "1." The maximum value of random number MR1-2 is set by setting an immediate value in the program code. The method for updating random number MR1-2 is software update SA1. The update condition for random number MR1-2 is a timer interrupt after a predetermined time has elapsed. The acquisition condition for random number MR1-2 is reading by software corresponding to the start winning. The period of random number MR1-2 is 800 [ms].

[0150] The range of random number MR1-3 is the range of values ​​within which random number MR1-3 can be updated, and is the same as random number MR1-2, from "0" to "199." The magnitude of random number MR1-3 is the total number of random values ​​included in the update range of random number MR1-3, and is the same as random number MR1-2, "200," corresponding to the range of random number MR1-3, "0" to "199." Since random number MR1-3 has a magnitude of "200," the total number of random values ​​included in the update range is not a prime number. The number of bytes of numerical data used to update the value of random number MR1-3 is "1." The method for setting the maximum value of random number MR1-3 is by setting an immediate value in the program code. The method for updating random number MR1-3 is software update SA2. The update conditions for random number MR1-3 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is standby processing within the main processing P_MAIN for game control. The condition for obtaining the random numbers MR1-3 is that the random numbers MR1-2 have completed one cycle. The period of the random numbers MR1-3 is indefinite due to the update conditions.

[0151] FIG. 10-5(B) shows a setting example AKA12 of a gaming random number used to determine the display result in the variable display of a normal symbol. The gaming random number in setting example AKA12 includes a random number MR2-1 for the normal symbol and a random number MR2-2 that serves as the initial value for the normal symbol. For example, the random number MR2-1 for the normal symbol can be used to determine the normal symbol designation value corresponding to the confirmed normal symbol as the display result of the normal symbol. The random number MR2-2 that serves as the initial value for the normal symbol can be used to set the initial value of the random number MR1-2.

[0152] The range of random number MR2-1 is the range of values ​​within which random number MR2-1 can be updated, from "0" to "198." The magnitude of random number MR2-1 is the total number of random values ​​included in the update range of random number MR2-1, which is "199," corresponding to the range of "0" to "198" for random number MR2-1. Since the magnitude of random number MR2-1 is "199," the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR2-1 is "1." The maximum value of random number MR2-1 is set by immediate value setting in program code. The method for updating random number MR2-1 is software update SA1. The update condition for random number MR2-1 is a timer interrupt upon the passage of a predetermined time. The acquisition condition for random number MR2-1 is a software readout in response to a gaming ball passing through a passing gate 41, which can be configured as a normal symbol activation port. The period of the random number MR2-1 is 796 [ms].

[0153] The range of random number MR2-2 is the range of values ​​within which random number MR2-2 can be updated, and is the same as random number MR2-1, from "0" to "198." The magnitude of random number MR2-2 is the total number of random values ​​included in the update range of random number MR2-2, and is the same as random number MR2-1, "199," corresponding to the range of random number MR2-2, "0" to "198." Since random number MR2-2 has a magnitude of "199," the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR2-2 is "1." The method for setting the maximum value of random number MR2-2 is by setting an immediate value in the program code. The method for updating random number MR2-2 is software update SA2. The update conditions for random number MR2-2 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is standby processing within the main processing P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is indefinite due to the update condition.

[0154] FIG. 10-5(C) shows a setting example AKA13 of a gaming random number used to determine the display mode for the variable display of special and normal symbols. The gaming random numbers in setting example AKA13 include a random number MR3-1 for a normal symbol variation pattern, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern. For example, the random number MR3-1 for a normal symbol variation pattern can be used to determine a normal symbol variation pattern corresponding to the variable display of a normal symbol. The random number MR3-2 for selecting a miss effect can be used to determine a variable display mode corresponding to the variable display of a special symbol whose special symbol display result is "miss." The random number MR3-3 for selecting a variation pattern type can be used to select a variation pattern type corresponding to the variable display of a special symbol. The random number MR3-4 for a variation pattern can be used to determine a variation pattern corresponding to the variable display of a special symbol.

[0155] The range of random number MR3-1 is the range of values ​​within which random number MR3-1 can be updated, from "0" to "232." The magnitude of random number MR3-1 is the total number of random values ​​included in the update range of random number MR3-1, which is "233," corresponding to the range of "0" to "232" of random number MR3-1. Since the magnitude of random number MR3-1 is "233," the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-1 is "1." The maximum value of random number MR3-1 is set by initializing a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-1 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for random number MR3-1 is the system clock input to the 8-bit random number circuit 104B. The acquisition condition for random number MR3-1 is the start of fluctuation in the variable display of normal symbols. The period of the random number MR3-1 is 0.249 [ms].

[0156] The range of random number MR3-2 is the range of values ​​within which random number MR3-2 can be updated, and is "0" to "65518." The magnitude of random number MR3-2 is the total number of random values ​​included in the update range of random number MR3-2, and is "65519," which corresponds to the range of random number MR3-2, "0" to "65518." Since the magnitude of random number MR3-2 is "65519," the total number of random values ​​included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-2 is "2." The maximum value of random number MR3-2 is set by initializing a register provided corresponding to the 16-bit random number circuit 104A. The random number MR3-2 is updated by hardware update using the 16-bit random number circuit 104A. The update condition for random number MR3-2 is the system clock input to the 16-bit random number circuit 104A. The condition for obtaining the random number MR3-2 is to read it into the random number buffer by software that corresponds to the start winning. The period of the random number MR3-2 is 139.774 [ms].

[0157] The range of random number MR3-3 is the range of values ​​within which random number MR3-3 can be updated, which is "0" to "240." The magnitude of random number MR3-3 is the total number of random values ​​included in the update range of random number MR3-3, which is "241," corresponding to the range of "0" to "240" for random number MR3-3. Since the magnitude of random number MR3-3 is "241," the total number of random values ​​included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-3 is "1." The maximum value of random number MR3-3 is set by initializing a register provided corresponding to 8-bit random number circuit 104B. The random number MR3-3 is updated by hardware update using 8-bit random number circuit 104B. The update condition for random number MR3-3 is the system clock input to 8-bit random number circuit 104B. The condition for obtaining the random number MR3-3 is to read it into the random number buffer by software that corresponds to the start winning. The period of the random number MR3-3 is 0.257 [ms].

[0158] The range of random number MR3-4 is the range of values ​​within which random number MR3-4 can be updated, from "0" to "250." The magnitude of random number MR3-4 is the total number of random values ​​included in the update range of random number MR3-4, and is "251," which corresponds to the range of random number MR3-4, from "0" to "250." Since random number MR3-4 has a magnitude of "251," the total number of random values ​​included in the update range is a prime number. The number of bytes of numeric data used to update the value of random number MR3-4 is "1." The maximum value of random number MR3-4 is set by initializing a register provided corresponding to the 8-bit random number circuit 104B. The random number MR3-4 is updated by hardware update using the 8-bit random number circuit 104B. The update condition for random number MR3-4 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining the random numbers MR3-4 are to read them into the random number buffer by software that corresponds to the start winning. The period of the random numbers MR3-4 is 0.268 [ms].

[0159] The software update SA1, which is a method for updating random numbers MR1-2 and MR2-1, can be updated by adding 1 to the previous value each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0," the minimum random number value. If the updated value matches the initial random number value, the corresponding initial random number is used to set the current random number value and stored as the new initial random number value. For example, if the updated value for random number MR1-2 matches the initial random number value, the current random number value is set using random number MR1-3, which is the initial value for the winning symbol, and the random number value is stored as the new initial random number value. If the updated value for random number MR2-1 matches the initial random number value, the current random number value is set using random number MR2-2, which is the initial value for the winning normal symbol, and the random number value is stored as the new initial random number value.

[0160] Software update SA2, which is a method for updating random numbers MR1-3 and MR2-2, can update the previous value by adding 1 each time the software update process is executed. At this time, if the updated value exceeds the maximum random number value, it is changed to "0", the minimum random number value. In this case, unlike software update SA1, no initial random number value is used, so the updated value will be either the previous value plus 1, or the minimum random number value, "0".

[0161] FIG. 10-6 is a diagram illustrating a random number update period when a random number value is updated using the 16-bit random number circuit 104A or the 8-bit random number circuit 104B included in the random number circuit 104. Here, the random numbers that can be generated by the channels RL0 to RL4 provided in the 16-bit random number circuit 104A are referred to as 16-bit random numbers RLn. The random numbers that can be generated by the channels RS0 to RS4 provided in the 8-bit random number circuit 104B are referred to as 8-bit random numbers RSn. The period in which the 16-bit random numbers RLn that can be updated by the 16-bit random number circuit 104A complete one cycle is determined by different relational expressions depending on whether the maximum value of the 16-bit random numbers RLn is a specific maximum value expressed using a power of two. The period in which the 8-bit random numbers RSn that can be updated by the 8-bit random number circuit 104B complete one cycle is determined by different relational expressions depending on whether the maximum value of the 8-bit random numbers RSn is a specific maximum value expressed using a power of two.

[0162] FIG. 10-6(A) shows a 16-bit random number period setting example AKA21 for the 16-bit random number circuit 104A. The 16-bit random number period is the period for which the 16-bit random number RLn, which can be updated by the 16-bit random number circuit 104A, completes one cycle. In the 16-bit random number period setting example AKA21, if the maximum value of the 16-bit random number RLn corresponds to 2-1 when m = 9 to 16, the period for which the 16-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., the count clock period. The value obtained by adding 1 to the maximum value, i.e., the magnitude of the 16-bit random number RLn, is a linear function with the variable being the magnitude of the 16-bit random number RLn. On the other hand, if the maximum value of the 16-bit random number RLn does not correspond to 2-1 when m = 9 to 16, the period for which the 16-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., 32 times the count clock period. The value obtained by adding 1 to the maximum value, i.e., the value is a linear function with the magnitude of the 16-bit random number RLn as a variable. In this way, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

[0163] FIG. 10-6(B) shows an example AK22 of setting an 8-bit random number period in the 8-bit random number circuit 104B. The 8-bit random number period is the period in which the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, completes one cycle. In the example AK22 of setting an 8-bit random number period, if the maximum value of the 8-bit random number RSn corresponds to 2-1 when m = 5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., the count clock period. The value obtained by adding 1 to the maximum value, i.e., the magnitude of the 8-bit random number RSn, is a linear function with the variable being the magnitude of the 8-bit random number RSn. In contrast, if the maximum value of the 8-bit random number RSn does not correspond to 2-1 when m = 5 to 8, the period in which the 8-bit random number sequence completes one cycle is proportional to the inverse of the count clock frequency, i.e., 16 times the count clock period. The value obtained by adding 1 to the maximum value, i.e., the value becomes a linear function with the magnitude of the 8-bit random number RSn as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

[0164] Figure 10-6(C) shows a comparative example AKA23 of random number values ​​that can be updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B. The 16-bit random number circuit 104A can update the random number values ​​corresponding to the random number MR1-1 for determining a special symbol and the random number MR3-2 for selecting a losing effect. The 8-bit random number circuit 104B can update the random number values ​​corresponding to the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for a variation pattern.

[0165] The random number MR1-1 has a maximum value of "65535", which corresponds to 2m-1 when m = 16. This results in a period of 4.369 [ms], and an update rate of 15,000 [times / ms]. The random number MR3-2 has a maximum value of "65518", which does not correspond to 2m-1 when m = 9 to 16. This results in a period of 139.774 [ms], and an update rate of 469 [times / ms]. The random number MR3-3 has a maximum value of "240", which does not correspond to 2m-1 when m = 5 to 8. This results in a period of 0.257 [ms], and an update rate of 938 [times / ms]. The maximum value of random number MR3-4 is "250", which does not correspond to 2m-1 when m is set to any value between 5 and 8. As a result, the period of random number MR3-4 is 0.268 [ms], and the update rate at this time is 938 [times / ms].

[0166] Thus, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include the random number MR1-1 for determining special symbols and the random number MR3-2 for selecting a losing effect. Both random numbers MR1-1 and MR3-2 have a specific number of bytes for their numeric data: 2 bytes. Since the size of random number MR1-1 is 65536 and the size of random number MR3-2 is 65519, if the total number of random numbers included in the update range of random number MR1-1 is a specific number, the total number of random numbers included in the update range of random number MR3-2 is a predetermined number smaller than the specific number. Since the update rate of random number MR1-1 is 15,000 times / ms and the update rate of random number MR3-2 is 469 times / ms, the update rate of random number MR1-1 is faster than that of random number MR3-2. This suppresses random number synchronization and enables appropriate random number updating.

[0167] Furthermore, the gaming random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR3-2 for selecting a losing effect. The gaming random numbers that can be updated by the 8-bit random number circuit 104B include a random number MR3-3 for selecting a variation pattern type and a random number MR3-4 for a variation pattern. The total number of random numbers included in the update range of each of these random numbers MR3-2 to MR3-4 is a prime number. The update rate of the random number MR3-2 is 469 times / ms, while the update rate of the random numbers MR3-3 and MR3-4 is 938 times / ms. In other words, the update rate of the random numbers MR3-3 and MR3-4 is twice the update rate of the random number MR3-2, which is an integer multiple of 2. Therefore, if random number MR3-2 is the first random number value and random numbers MR3-3 and MR3-4 are the second random number values, the first random number value has an update speed of the first speed, and the second random number value has an update speed of the second speed, which is an integer multiple of the first speed. The update range of random number MR3-2 is "0" to "65518," the update range of random number MR3-3 is "0" to "240," and the update range of random number MR3-4 is "0" to "250." Therefore, the total number of random numbers included in each update range is different for the first random number value and the second random number value, and the total number of random numbers included in both update ranges is a prime number. This prevents synchronization of random number values ​​and enables appropriate random number updating.

[0168] The CPU 103 includes multiple registers, such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and general-purpose registers including an accumulator. The index register, flag register, and general-purpose register may be provided as a main register and a sub-register. The registers included in the main register and the sub-register, and the stack pointer may be provided so as to be able to configure multiple register banks. The multiple register banks may include a first register bank for use within an area available when executing a game program, and a second register bank for use outside the area available when executing a non-game program. This eliminates the need to save and restore values ​​stored in general-purpose registers, etc., to and from the stack area when switching between executing a game program and a non-game program, for example, thereby preventing an increase in the amount of program memory and processing load.

[0169] The program counter, also called the PC register, is used to store the address value of the next instruction to be executed by the CPU 103. The value stored in the program counter is counted up sequentially each time an instruction is executed, and the address value of the branch destination of a branch instruction is set therein. The interrupt register, also called the I register, can store the upper address value of the interrupt vector table. The value stored in the I register is set in response to the start of power supply to the pachinko gaming machine 1.

[0170] The stack pointer, also known as the SP register, can hold address values ​​corresponding to game stack areas and non-game stack areas. The value stored in the stack pointer can specify a destination address for saving and holding stored values ​​or immediate values ​​in predetermined registers, including the program counter, or in registers designated by instructions, in response to interrupt occurrence, execution of a PUSH instruction, or execution of a subroutine call instruction such as a CALL instruction, CALLF instruction, or RST instruction. Upon saving, the value is updated to indicate the top address of the storage area holding the stored value. The value stored in the stack pointer can also specify a read address for restoring the saved register value in response to the end of interrupt processing, execution of a POP instruction, or the end of subroutine processing. Upon this restoration, the value is updated to indicate the address corresponding to the read value. The stack pointer can also be set to the stored value or immediate value of a register designated by a load instruction such as an LD instruction.

[0171] The index registers include the IX register and the IY register, each with two bytes of storage capacity capable of storing 16-bit data. The accumulator is also called the A register. Other general-purpose registers include multiple registers, such as the B register, C register, D register, E register, H register, and L register, each with one byte of storage capacity capable of storing 8-bit data. The B register and the C register can be used as the BC register of a pair of registers capable of storing 16-bit data. The D register and the E register can be used as the DE register of a pair of registers capable of storing 16-bit data. The H register and the L register can be used as the HL register of a pair of registers capable of storing 16-bit data.

[0172] The internal registers of CPU 103 can update stored values ​​in response to calculation instructions and transfer instructions executed by CPU 103, and are used to specify program addresses, data addresses, or built-in register addresses provided in the game control microcomputer 100, and to hold calculation data and transfer data.

[0173] In the game control microcomputer 100, the instruction set for causing the CPU 103 to execute a program is composed of transfer instructions such as load instructions, subroutine call instructions, jump instructions, other operation instructions including arithmetic operation instructions and logical operation instructions, input / output instructions, etc. Computer programs such as game programs and non-game programs that can be executed by the CPU 103 are prepared in advance as program codes that describe these various instructions, and are stored in the ROM 101.

[0174] The load instruction is a transfer instruction that can be used to store and set data read from a memory area or an internal device area of ​​ROM 101 or RAM 102 in an internal register of CPU 103, to write and store a value stored in an internal register of CPU 103 in a memory area or an internal device area of ​​RAM 102, and to set or store a numerical value specified by an operand as an immediate value in an internal register of CPU 103 or a memory area or an internal device area of ​​RAM 102. The target to which data is transferred by a load instruction can be specified according to the instruction code and operand, and generally includes the source and destination of the data. However, if an immediate value is specified by the operand, the source of the data is not included.

[0175] Load instructions include a normal LD ​​instruction, a special LDQ instruction, a special LDF instruction, and a special ICPLD instruction. The normal LD ​​instruction is also called a normal transfer instruction. The special LDQ instruction is also called a first special transfer instruction. The special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

[0176] The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both a high-order address and a low-order address when transferring data to a storage area or an internal device area of ​​ROM 101 or RAM 102. Furthermore, when transferring data to a storage area or an internal device area of ​​ROM 101 or RAM 102, the LD instruction, which is a normal transfer instruction, can transfer data by specifying the destination or source address using the pointer by using a pair register such as the HL register as a pointer.

[0177] The LDQ instruction, which is the first special transfer instruction, can transfer data by specifying only the lower address using the Q register, a special register included in the internal registers of the CPU 103. A value indicating the upper address is preset in the Q register, and by combining this with the lower address specified by the LDQ instruction, it is possible to specify the destination or source address and transfer data.

[0178] The LDQ instruction, which is the first special transfer instruction, can transfer data using a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the value stored in the Q register, the amount of program code may actually be larger than the normal LD ​​instruction. Therefore, it is sufficient to be able to transfer data using the LDQ instruction, which is the first special transfer instruction, in response to processes that require various data to be transferred multiple times to the game work area at addresses F000[H] to F0D7[H], the function setting register area at addresses FE00[H] to FEBF[H], or the function control register area at addresses FF00[H] to FFFF[H].

[0179] The LDF command, which is the second special transfer command, can transfer data by specifying only the lower address of data stored in a specific address range. The specific address range is, for example, the range of addresses 1200[H] to 1DFF[H]. Therefore, by setting the game data area of ​​ROM 101 to be included in this specific address range in advance and combining it with the lower address specified by the LDF command, the address of the transfer source can be specified and data can be transferred. Note that since the game data area of ​​ROM 101 is read-only and not writable, the address of the game data area cannot be specified as the transfer destination address.

[0180] The LDF instruction, which is the second special transfer instruction, can transfer data using a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, since the specific address range is fixed by specification, it is sufficient to set a storage area for frequently used data, such as the game data area of ​​ROM 101, to be included in the specific address range and to be able to transfer data using the LDF instruction, which is the second special transfer instruction.

[0181] The ICPLD instruction, which is the third special transfer instruction, compares the update target value with a comparison judgment value, and updates the update target value by adding 1 if the update target value is less than the comparison judgment value, whereas it changes the update target value to the minimum value, "0," if the update target value is equal to or greater than the comparison judgment value. The update target value may be the value indicated by the stored data at the address pointed to by the pointer, or may be the value stored in a register. The comparison judgment value may be the value stored in a register, or may be the value indicated by the operand of the ICPLD instruction.

[0182] In this way, the third special transfer instruction, the ICPLD instruction, is a single comparison and addition instruction that includes comparing the update target value with the comparison judgment value, adding 1 to the update target value if the comparison result is less than the comparison judgment value, and changing the update target value to the minimum value if the comparison result is greater than or equal to the comparison judgment value.

[0183] Setting a stored value in an internal register of the CPU 103 using an immediate value or the like based on an operand of a transfer command is also referred to as "setting." Reading stored data from the game data area of ​​the ROM 101 or the game work area of ​​the RAM 102 and storing it in an internal register of the CPU 103 is also referred to as "loading." Storing a stored value in an internal register of the CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of ​​the RAM 102 is also referred to as "storing."

[0184] Figure 10-7 is a flowchart showing an example of the power supply start response processing P_POWER_ON. The power supply start response processing P_POWER_ON is included in the processing that can be called from the main processing P_MAIN for game control shown in Figure 4, and can be executed in step S1 in response to the start of power supply in the pachinko gaming machine 1. When the CPU 103 executes the power supply start response processing P_POWER_ON, it disables interrupts (step AKS1) and then sets the in-area stack pointer initial value to the stack pointer (step AKS2). The in-area stack pointer initial value may be address F200[H], which is the final address of the gaming stack area plus 1, corresponding to the initial state in which no saved data is stored in the gaming stack area.

[0185] Following step AKS2, a connection confirmation signal ON output value is set by a transfer instruction for setting an internal register of CPU 103 (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is ON, and may be, for example, 00[H]. At this time, a function control register upper address is set in the Q register by a transfer instruction for setting a Q register included in the internal register of CPU 103 (step AKS4). The function control register upper address is a value FF[H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. After the function control register upper address is set in this way, a transfer instruction using the upper address indicated by the value stored in the Q register stores the connection confirmation signal ON output value (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set to the upper address of the function control register area by step AKS4. Therefore, by using a transfer command for writing to a memory area at a specified address, such as a special 2-byte LDQ command specifying a lower address, the connection confirmation signal ON output value set in step AKS3 can be stored in the function control register at the specified address in the function control register area. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. As a result, the connection confirmation signal transmitted from the main board 11 to the dispensing control board is set to the ON state.

[0186] When the connection confirmation signal is set to the ON state in step AKS5, the SCU0 command register clear output value is stored by a transfer instruction using the upper address indicated by the value stored in the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register was set to the upper address of the function control register area in step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU0 command register clear output value can be stored in the function control register at the specified address in the function control register area by a transfer instruction for writing to a memory area at a specified address, such as a 3-byte special LDQ instruction that specifies the lower address and the SCU0 command register clear output value. In step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register located at address FF28[H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This causes the serial communication function using channel SCU0 of the serial communication circuit 139 to be controlled to its initial state.

[0187] After step AKS6, the SCU1 command register clear output value is stored by a transfer instruction using the upper address indicated by the value stored in the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register was set to the upper address of the function control register area in step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU1 command register clear output value can be stored in the function control register at the specified address in the function control register area by a transfer instruction for writing to a memory area at a specified address, such as a 3-byte special LDQ instruction specifying the lower address and the SCU0 command register clear output value. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register located at address FF2C[H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This causes the serial communication function using channel SCU1 of the serial communication circuit 139 to be controlled to its initial state.

[0188] When these serial communication functions are controlled to the initial state, a transfer command for setting the internal registers of the CPU 103 sets the interrupt vector table upper address (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of ​​the ROM 101. The interrupt vector table stores the top address at a table position corresponding to the interrupt order for, for example, the timer interrupt process P_PCT for game control, which is executed in response to the occurrence of a timer interrupt. Such an interrupt vector table upper address is set in the I register by a transfer command for setting the internal registers of the CPU 103 (step AKS9).

[0189] After step AKS9, the value stored in the Q register is updated by subtracting 1 (step AKS10). The value stored in the Q register was set to the upper address of the function control register area in step AKS4. When this value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. After the function control registers in the function control register area are set, the function setting registers in the function setting register area are made configurable. At this time, a transfer instruction for setting a pointer is used to set a function setting register storage value table address (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of ​​ROM 101. Then, a transfer instruction for reading the stored data at the address pointed to by the pointer is used to load the processing count (step AKS12). Furthermore, a function setting register store instruction is used to set the function setting register storage value table (step AKS13). The function setting register store instruction may be an instruction to specify a function setting register by the data stored at the address obtained by adding 1 to the address pointed to by the pointer, to store the function setting register setting value indicated by the data stored at the address obtained by adding 2 to the address pointed to by the pointer in the specified function setting register, to add 2 to the value stored in the pointer, and to subtract 1 from the number of processes, repeating this process until the number of processes becomes 0. In this way, the function setting register can be initialized.

[0190] When the initial setting of the function setting register is completed in step AKS13, an access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to, for example, 01 [H] by a transfer instruction for setting an internal register of the CPU 103. Such an access permission output value is stored in the RWM access protect register by a transfer instruction for writing to a memory area at the top address in the function setting register area. The RWM access protect register enables function control to allow access to the RAM 102, which is the RWM, in response to the setting of the access permission output value 01 [H]. Therefore, by storing the access permission output value in the RWM access protect register in step AKS14, access to the RAM 102 is permitted in response to the start of power supply to the pachinko gaming machine 1.

[0191] After step AKS14, the upper address of the gaming work area, which serves as the work area of ​​RAM 102, is set in the Q register (step AKS15), and the power supply start response process P_POWER_ON is then terminated. Thus, after access to RAM 102 is permitted in step AKS14, a value F0[H] indicating the upper address of the gaming work area in RAM 102 is set in the Q register. After step AKS15, when the LDQ instruction, which is the first special transfer instruction, is executed, the value F0[H] stored in the Q register can be used as the upper address of the transfer destination or transfer source without being specified by an operand. This reduces the program size for processing using the gaming work area in RAM 102, thereby improving the marketability of the gaming machine.

[0192] FIG. 10-8 shows a configuration example AKT01 of a function setting register storage value table used in the power supply start response process P_POWER_ON. In the power supply start response process P_POWER_ON, for example, using the function setting register storage table whose address is set in step AKS11, the number of processes is loaded in step AKS12, and the stored values ​​of each function setting register are stored by a function setting register store command in step AKS13. The function setting register storage value table of configuration example AKT01 stores a value of 18 [H] indicating the number of processes at a starting address of 1200 [H]. In step AKS12, this table data is read and loaded into an internal register of the CPU 103. Thereafter, the function setting register store command in step AKS13 sequentially reads table data that combines the lower addresses and stored values ​​of the function setting registers, making it possible to store the stored values ​​in the function setting registers corresponding to each lower address.

[0193] In the function setting register storage value table of configuration example AKT01, the table data is configured so that the stored value of a function setting register with a smaller value indicating a lower address can be set first, and the stored value of a function setting register with a larger value indicating a lower address can be set later. As a result, in the function setting register area, the stored values ​​of each function setting register are set in the order of the stored value of the function setting register closest to the first address being set first, and the stored value of the function setting register closest to the last address being set last. This makes it easier to design and manage the data indicating the stored values ​​of the function setting registers, and improves the marketability of the gaming machine.

[0194] The 16-bit random number circuit 104A corresponds to the four channels RL0 to RL3 and can start updating from the channel whose maximum value setting register has been set to a value indicating the maximum random number value. The 8-bit random number circuit 104B corresponds to the four channels RS0 to RS3 and can start updating from the channel whose maximum value setting register has been set to a value indicating the maximum random number value. The function setting register area of ​​the setting example AKA01 shown in Figure 10-3 includes an RL0 maximum value setting register at addresses FE3F[H] to FE40[H], an RL1 maximum value setting register at addresses FE41[H] to FE42[H], an RL2 maximum value setting register at addresses FE43[H] to FE44[H], and an RL3 maximum value setting register at addresses FE45[H] to FE46[H], which are provided corresponding to the four channels RL0 to RL3 of the 16-bit random number circuit 104A. This function setting register area includes an RS0 maximum value setting register at address FE47[H], an RS1 maximum value setting register at address FE48[H], an RS2 maximum value setting register at address FE49[H], and an RS3 maximum value setting register at address FE4A[H], which correspond to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. The function setting register storage value table of configuration example AKT01 is configured so that, of these maximum value setting registers, the stored value of the RL0 maximum value setting register is set first, then the stored value of the RL2 maximum value setting register, then the stored value of the RS1 maximum value setting register, then the stored value of the RS2 maximum value setting register, and finally the RS3 maximum value setting register. Therefore, updating of channel RL0 in the 16-bit random number circuit 104A starts first, updating of channel RL2 in the 16-bit random number circuit 104A starts next, updating of channel RS1 in the 8-bit random number circuit 104B starts next, updating of channel RS2 in the 8-bit random number circuit 104B starts next, and updating of channel RS3 in the 8-bit random number circuit 104B starts last. In this way, since updating starts in order from the random number value for which the maximum random number value is set, the uncertainty of the random number value is increased depending on the timing at which the update of the random number value is started, reducing the processing load and enabling appropriate updating of the random number value.

[0195] The power supply start response process P_POWER_ON is included in processes that can be called from the game control main process P_MAIN, which is a startup process executed upon the start of power supply to the pachinko gaming machine 1. Using the function setting register storage value table of the example configuration AKT01, it is possible to set stored values ​​in the function setting register area, which serves as a storage area for functions. Since the maximum value of the random numbers updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start response process P_POWER_ON can be executed as a maximum value setting process. The 16-bit random number circuit 104A can update a first random number value consisting of 16 bits corresponding to a specific number of bytes (2 bytes). The 8-bit random number circuit 104B can update a second random number value consisting of 8 bits corresponding to a specific number of bytes (1 byte) smaller than the specific number of bytes. When the power supply start response process P_POWER_ON is executed, the function setting register stored value table of the configuration example AKT01 is used to set the maximum random number value of the first random number value that can be updated by the 16-bit random number circuit 104A, and then set the maximum random number value of the second random number value that can be updated by the 8-bit random number circuit 104B. In this way, by setting the first random number value of a specific number of bytes and then setting the second random number value of a predetermined number of bytes, the first random number value and the second random number value can be stably updated, making it possible to update the random number values ​​appropriately.

[0196] Figure 10-9 shows an example of the configuration of the RWM access protection register. The RWM access protection register is provided at address FF00[H] in the configuration example AKA02 of the function control register area shown in Figure 10-4. The value stored in the RWM access protection register will be different depending on whether access to the RAM 102, which is the RWM, is permitted or prohibited.

[0197] Figure 10-9(A) shows an example of the bit configuration of the RWM access protection register. The RWM access protection register can store 8-bit data RAP with bit numbers "0" to "7", and bit data RAP0 with bit number "0" can be set to 0[B] or 1[B]. In contrast, bit data from bit number "1" to bit number "7" are always set to 0[B] and are fixed values ​​that are never set to "1".

[0198] FIG. 10-9(B) is a diagram for explaining an example of use of bit data RAP of the RWM access protection register. In the bit data RAP, bit data RAP0 with bit number "0" is an RWM access control bit, and setting it to 0[B] prohibits access to the RWM, and setting it to 1[B] allows access to the RWM. In response to the start of power supply to the pachinko gaming machine 1, bit data RAP0 with bit number "0" is set to its initial value of 0[B]. This makes it possible to prohibit access to the RAM 102, which serves as the RWM, in response to the start of power supply to the pachinko gaming machine 1.

[0199] Figure 10-10 is a flowchart showing an example of power-off processing P_POWER_OFF. The power-off processing P_POWER_OFF is included in processing that can be called from the timer interrupt processing P_PCT for game control shown in Figure 5, and can be executed in step S51 each time a timer interrupt occurs. When the power-off processing P_POWER_OFF is executed, the CPU 103 sets a backup monitoring timer address by a transfer command for setting a pointer (step AKS31). The backup monitoring timer address is the address of the backup monitoring timer provided in the game work area of ​​the RAM 102.

[0200] Input port number "3" is input (step AKS32). Input port number "3" is an input port to which "3" is assigned as the port number, and includes a power supply check signal input bit. Therefore, a logical AND operation is performed using the input data of input port number "3" and the check data corresponding to the bit position of the power supply check signal input bit. At this time, it is determined whether the power supply check signal input bit is "0" or not depending on whether the zero flag is on or not (step AKS33). When the power supply check signal input bit's bit value is 0 [B] corresponding to "0", it indicates that the power supply check signal is in the off state, and when the bit value is 1 [B] corresponding to "1", it indicates that the power supply check signal is in the on state.

[0201] If the power supply confirmation signal input bit is "1" and not "0" (step AKS33; No), backup monitoring timer clear data is stored by a transfer instruction that can update the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing the clear data in the backup monitoring timer, when the power supply confirmation signal is in the ON state, the backup monitoring timer can be cleared in response to a state other than power-off determination being made.

[0202] If the power supply confirmation signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the backup monitoring timer is updated by adding 1 to the time count (step AKS35). The backup monitoring timer is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AKS36). Then, a calculation return command (step AKS37) that can compare the time count by the backup monitoring timer with the judgment value corresponding to the backup judgment time is used to confirm that the backup monitoring timer does not indicate the backup judgment time (step AKS38). This calculation return command corresponds to a zero flag that is turned off when the time count by the backup monitoring timer and the judgment value corresponding to the backup judgment time are different, thereby terminating the power-off process and enabling a return to the special symbol process. Thus, if the backup monitoring timer does not indicate the backup judgment time (step AKS38; Yes), the power-off process is terminated.

[0203] If the backup monitoring timer indicates the backup determination time in response to step AKS38 (step AKS38; No), a checksum calculation process P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 may be common to the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main processing P_MAIN for game control shown in FIG. 4. By executing a common checksum calculation process in response to the start and stop of power supply to the pachinko gaming machine 1 in this way, it becomes possible to determine whether recovery using backup data is possible based on whether the memory contents in the game work area of ​​RAM 102 are retained unchanged. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer command for writing to the memory area at the address pointed to by the pointer (step AKS40).

[0204] After step AKS40, an exclusive OR instruction is used to set clear data to the output value data (step AKS41). This exclusive OR instruction calculates the exclusive OR of the stored values ​​of a single register, resulting in the exclusive OR of all bit values ​​being the same. This allows the stored value to be initialized to clear data of 00[H]. This clear data is stored in the RWM access protect register by a transfer instruction to write it to the memory area at the top address in the function setting register area (step AKS42). The RWM access protect register enables function control to prohibit access to the RAM 102, which is the RWM, in response to the setting of the clear data, 00[H]. Therefore, by storing the clear data in the RWM access protect register in step AKS42, access to the RAM 102 is prohibited in response to a power outage in the pachinko gaming machine 1.

[0205] After step AKS42, output port numbers "0" to "10" are cleared (step AKS43). The output port numbers "0" to "10" are the output ports with port numbers "0" to "10," and are all the output ports in the game control microcomputer 100. Therefore, in step AKS43, all the output ports in the game control microcomputer 100 are set to a clear state in response to the stop of power supply to the pachinko gaming machine 1. At this time, a transfer command for setting an internal register of the CPU 103 sets a connection confirmation signal OFF output value (step AKS44). The connection confirmation signal OFF output value is a value indicating that the connection confirmation signal is in an OFF state, and may be, for example, 01 [H]. Such a connection confirmation signal OFF output value is stored in the output port number "1" register by a transfer command for writing it to a memory area at a specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to an OFF state.

[0206] Following step AKS45, a PTC0 interrupt inhibit output value is set by a transfer instruction for setting an internal register of the CPU 103 (step AKS46). The PTC0 interrupt inhibit output value is an output value for inhibiting the occurrence of a timer interrupt using channel PTC0 of the timer circuit 136. This PTC0 interrupt inhibit output value is stored in the PTC0 control register by a transfer instruction for writing to a function setting register at a specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the timing function using channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt inhibit output value set in step AKS46 is stored in the PTC0 control register, and thereby the timer interrupt for game control is inhibited in response to the stop of power supply to the pachinko gaming machine 1.

[0207] When the setting corresponding to the lapse of the backup determination time is made, the process transitions to a standby state by executing a loop process. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether the power supply confirmation signal input bit is "0" (step AKS49). If the power supply confirmation signal is in the OFF state and the power supply confirmation signal input bit is "0" (step AKS49; Yes), the loop process returning to step AKS48 continues. In this way, in response to an interruption in the power supply to the pachinko gaming machine 1, the standby state is maintained until operation is stopped due to a power outage, thereby making it possible to prevent inconvenient changes to stored data and runaway processing by the CPU 103.

[0208] If the power check signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), the power failure recovery vector table address is set to the stack pointer (step AKS50), and then the power failure processing P_POWER_OFF is terminated by an interrupt return instruction. The power failure recovery vector table address is the address of the power failure recovery vector table provided in the game program area of ​​ROM 101. The interrupt return instruction can use the stack pointer as a pointer to set the data stored in the memory area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the data stored in the memory area indicated by the address specified by the stored value of the stack pointer is set to the lower byte of the program counter, and the data stored in the memory area indicated by the address specified by the value obtained by adding 1 to the stored value of the stack pointer is set to the upper byte of the program counter.

[0209] 10-11 is a diagram illustrating an example of the data structure related to the power-off process P_POWER_OFF. In the power-off process P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves checksum data using a checksum buffer. Furthermore, step AKS50 sets a vector table address for power-off recovery, enabling the game control program to be executed from the beginning if the pachinko gaming machine 1 does not stop operating after a power-off is detected and normal power supply is resumed. In this way, the power-off process P_POWER_OFF uses the backup monitoring timer, checksum buffer, and power-off recovery vector table to enable control when the power supply to the pachinko gaming machine 1 is stopped.

[0210] Figure 10-11(A) shows a configuration example AKB01 of a memory area that serves as a backup data area. The backup data area of ​​configuration example AKB01 can store backup setting data used when backing up stored data in the game work area of ​​RAM102. This backup data area includes a backup monitoring timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the starting address of the game work area, and address F0DE[H] is the last address of the game work area. In this way, by providing a backup data area at the starting address and last address of the game work area, it is possible to properly back up stored data in the game work area of ​​RAM102.

[0211] Figure 10-11(B) shows an example of a power-off recovery vector table, AKT11. The power-off recovery vector table of the example AKT11 can specify a return address from the power-off process in response to an interrupt return command when normal power supply is resumed. The power-off recovery vector table contains, as table data, the lower address designation data 00[H] stored at address 0016[H] in the game program area of ​​ROM 101 and the upper address designation data 00[H] stored at address 0017[H] in the game program area of ​​ROM 101. In step AKS50 of the power-off process P_POWER_OFF, data indicating address 0016[H] is set in the stack pointer as the power-off recovery vector table address. Then, an interrupt return command sets the program counter to 0000[H], restoring the process and enabling the game control main process P_MAIN to be executed from the beginning.

[0212] 10-12 is a flowchart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the processes that can be called from the timer interrupt process P_PCT for game control shown in FIG. 5, and can be executed in step S56 in response to the occurrence of a periodic timer interrupt after a predetermined time has elapsed, such as 4 ms. On the other hand, the random number update process P_RANDOM is not included in the processes that can be called from the main process P_MAIN for game control shown in FIG. 4, and is not executed in the loop process that is repeated until a timer interrupt occurs after step S7. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt after a predetermined time has elapsed, it is not included in the second process that can be repeatedly executed until the first process is executed. Furthermore, although the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, it cannot be called and executed in the standby process as a repeated loop process in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1 after startup processes such as the power supply start response process P_POWER_ON in step S1.

[0213] The random number update process P_RANDOM uses internal registers of the CPU 103, such as the B register, the DE register, and the HL register, to update the numerical data indicating the values ​​of the random number MR1-2 for the winning symbol and the random number MR2-1 for the winning normal symbol. The random number MR1-2 for the winning symbol is used to determine the confirmed special symbol that results in the display of the special symbol in the special symbol game, which is a variable display of special symbols on the first special symbol display device 4A or the second special symbol display device 4B. The random number MR2-1 for the winning normal symbol is used to determine the confirmed normal symbol that results in the display of the normal symbol in the normal symbol game, which is a variable display of normal symbols on the normal symbol display device 20. The random number update process P_RANDOM can update the respective random number values ​​using the B register, the DE register, and the HL register, which are common internal registers, when updating the random number MR1-2 for the winning symbol and when updating the random number MR2-1 for the winning normal symbol.

[0214] When the CPU 103 executes the random number update process P_RANDOM, it sets the random number counter address for the winning symbol by a transfer command for setting the HL register used as a random number pointer (step AKS61). The random number counter address for the winning symbol is the address of the random number counter for the winning symbol provided in the game work area of ​​RAM 102. The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, the random number MR1-2 for the winning symbol can be set as the random number value to be updated by storing the address of the random number counter for the winning symbol in the random number pointer by the LDQ command.

[0215] Following step AKS61, a transfer instruction for setting register B, which is used as the random number maximum register, is used to set a random number maximum value corresponding to the random number maximum determination value for the winning symbol (step AKS62). The random number maximum register can store the maximum value that the random number value to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning symbol, the maximum value included in the update range of random number MR1-2, such as C7[H] corresponding to "199", is stored in the random number maximum register by the LD instruction. This allows the maximum random number value of random number MR1-2, which was set as the random number value to be updated in step AKS61, to be set.

[0216] Following step AKS62, a transfer instruction for setting the DE register used as an initial value pointer sets the random number initial value data buffer address for the winning symbol (step AKS63). The random number initial value data buffer address for the winning symbol is the address of the random number initial value data buffer for the winning symbol provided in the game work area of ​​RAM 102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and setting the stored value makes it possible to obtain and change the random number initial value. In step AKS63, the LDQ instruction is used to store the address of the random number initial value data buffer for the winning symbol in the initial value pointer, thereby making the random number initial value obtainable and changeable corresponding to the random numbers MR1-2 set as the random numbers to be updated in step AKS61. Next, a subroutine call instruction is used to execute the initial value change random number update process P_RANCP (step AKS64). The initial value change random number update process P_RANCP in step AKS64 enables updating of the random numbers MR1-2 for winning symbols, which are the random number values ​​to be updated, and changing of the random number initial values, based on the settings in steps AKS61 to AKS63.

[0217] After the initial value change random number update process P_RANCP in step AKS64, a transfer instruction for setting the HL register used as a random number pointer sets the random number counter address for the normal symbol (step AKS65). The random number counter address for the normal symbol is the address of the random number counter for the normal symbol provided in the game work area of ​​RAM 102. In step AKS65, the address of the random number counter for the normal symbol is stored in the random number pointer by the LDQ instruction, so that the random number MR2-1 for the normal symbol can be set as the random number value to be updated.

[0218] Following step AKS65, a transfer instruction for setting the B register used as the random number maximum register is used to set a random number maximum value corresponding to the random number maximum judgment value for the normal symbol (step AKS66). In step AKS66, for the random number MR2-1 for the normal symbol, the maximum value included in the update range of the random number MR2-1, such as C6 [H] corresponding to the maximum value "198", is stored in the random number maximum register by the LD instruction. This allows the random number maximum value of the random number MR2-1 that was set as the random number value to be updated in step AKS65 to be set.

[0219] Following step AKS66, a transfer instruction for setting the DE register used as an initial value pointer is used to set the random number initial value data buffer address for the normal symbol (step AKS67). The random number initial value data buffer address for the normal symbol is the address of the random number initial value data buffer for the normal symbol provided in the game work area of ​​RAM 102. In step AKS67, the LDQ instruction is used to store the address of the random number initial value data buffer for the normal symbol in the initial value pointer, thereby setting the random number initial value for the random number MR2-1 set as the random number value to be updated in step AKS65 to be obtainable and changeable. Next, a subroutine call instruction common to step AKS64 is used to execute the initial value change random number update process P_RANCP (step AKS68). The initial value change random number update process P_RANCP of step AKS68 enables updating of the random number MR2-1 for the normal winning symbol, which is the random number value to be updated, and changing of the random number initial value, based on the settings in steps AKS65 to AKS67.

[0220] 10-13 is a diagram for explaining an example of the use of data configuration related to the random number update process P_RANDOM. In the random number update process P_RANDOM, the initial value change random number update process P_RANCP of step AKS64 is executed using the random number counter for winning symbols whose address is set in the random number pointer in step AKS61 and the random number initial value data buffer for winning symbols whose address is set in the initial value pointer in step AKS63. In addition, in the random number update process P_RANDOM, the initial value change random number update process P_RANCP of step AKS68 is executed using the random number counter for winning normal symbols whose address is set in the random number pointer in step AKS65 and the random number initial value data buffer for winning normal symbols whose address is set in the initial value pointer in step AKS67. The random number counter for winning symbols is provided in the random number buffer area for special symbols and can store numerical data corresponding to the random numbers MR1-2 for winning symbols. The random number initial value data buffer for the winning symbol is provided in the random number data area for the winning symbol and can store numerical data corresponding to the random number initial value of the random number MR1-2. The random number counter for the normal winning symbol is provided in the random number data area for the winning symbol and can store numerical data corresponding to the random number MR2-1 for the normal winning symbol. The random number initial value data buffer for the normal winning symbol is provided in the random number data area for the winning symbol and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM enables software to update the random numbers MR1-2 and MR2-1 using the random number initial value data buffer for the winning symbol provided in the random number data area for the winning symbol, the random number counter for the normal winning symbol, the random number initial value data buffer for the normal winning symbol, and the random number counter for the winning symbol provided in the random number buffer area for the special symbol.

[0221] 10-13(A) shows a configuration example AKB11 of a random number data area for a winning symbol. The winning symbol random number data area of ​​the configuration example AKB11 includes a random number initial value data buffer for a winning symbol at address F050[H], a winning symbol initial value random number counter at address F051[H], a random number counter for a normal winning symbol at address F052[H], a random number initial value data buffer for a normal winning symbol at address F053[H], and a normal winning symbol initial value random number counter at address F054[H]. Of these, the address F050[H] of the random number initial value data buffer for the winning symbol is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, the address F052[H] of the random number counter for the normal symbol is set to the random number pointer by step AKS65 of the random number update process P_RANDOM, and the address F053[H] of the random number initial value data buffer for the normal symbol is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The winning symbol initial value random number counter can store numerical data corresponding to the random numbers MR1-3 which are the initial values ​​for the winning symbol. The normal symbol initial value random number counter can store numerical data corresponding to the random numbers MR2-2 which are the initial values ​​for the normal symbol.

[0222] Figure 10-13(B) shows a configuration example AKB12 of the special symbol random number buffer area. The special symbol random number buffer area of ​​configuration example AKB12 includes a special symbol determination random number buffer at address F07F[H], a winning symbol random number counter at address F081[H], a variation pattern type selection random number buffer at address F082[H], a variation pattern random number buffer at address F083[H], and a losing effect selection random number buffer at address F084[H]. Of these, the winning symbol random number counter address F081[H] is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The special symbol determination random number buffer can store numerical data corresponding to the special symbol determination random number MR1-1 obtained from the 16-bit random number circuit 104A. The random number buffer for selecting a variation pattern type can store numerical data corresponding to the random number MR3-3 for selecting a variation pattern type obtained from the 8-bit random number circuit 104B. The random number buffer for variation patterns can store numerical data corresponding to the random number MR3-4 for variation patterns obtained from the 8-bit random number circuit 104B. The random number buffer for selecting a losing effect can store numerical data corresponding to the random number MR3-2 for selecting a losing effect obtained from the 16-bit random number circuit 104A.

[0223] FIG. 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in FIG. 10-12, and can be executed in step AKS64 after the settings for the random number MR1-2 for the winning symbol are made in steps AKS61 to AKS63, and can be executed in step AKS68 after the settings for the random number MR2-1 for the normal winning symbol are made in steps AKS65 to AKS67. Such initial value change random number update process P_RANCP makes it possible to update the value of the random number MR1-2 using numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. Also, the initial value change random number update process P_RANCP makes it possible to update the value of the random number MR2-1 using numerical data corresponding to the random number MR2-1 for the normal winning symbol in step AKS68.

[0224] When the CPU 103 executes the initial value change random number update process P_RANCP, it first executes a compare and add instruction (step AKS101). This compare and add instruction uses the stored data at the address indicated by the stored value of the HL register, which is a random number pointer, as the update target value, and the stored value of the B register, which is a random number maximum register, as the comparison judgment value, and can be executed by a single ICPLD instruction, which is a third special transfer instruction. The stored value of the HL register, which is a random number pointer, indicates the address of the random number counter in which numerical data corresponding to the update target random number value is stored. The stored value of the B register, which is a random number maximum register, indicates the random number maximum value set corresponding to the update target random number value. If the count value of the random number counter indicating the update target random number value is less than the stored value of the random number maximum register, the count value of the random number counter is updated to increment by 1, thereby incrementing the update target random number value by 1. On the other hand, if the count value of the random number counter indicating the update target random number value is equal to or greater than the stored value of the random number maximum register, the random number counter is cleared and initialized to "0", thereby changing the update target random number value to the minimum random number value. Therefore, the compare and add instruction in step AKS101 is a single instruction that includes comparing the random number value to be updated with the maximum random number value, incrementing the random number value to be updated by 1 if the comparison result is less than the maximum random number value, and changing the random number value to the minimum random number value if the comparison result is greater than or equal to the maximum random number value. In this way, when updating the random number value to be updated using the initial value change random number update process P_RANCP, a single compare and add instruction is executed first. By executing such a single compare and add instruction first, it is possible to suppress the occurrence of malfunctions and update the random number value appropriately.

[0225] When the compare and add instruction is executed in step AKS101, a transfer instruction for reading stored data is used to load the random number value pointed to by the random number pointer (step AKS102). The random number pointer and the initial value pointer are also exchanged (step AKS103). The random number value loaded in step AKS102 is then compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether the compared random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number value to be updated. Therefore, in step AKS104, after the compare and add instruction in step AKS101 is executed, the random number value to be updated after being updated by the compare and add instruction is compared with the random number initial value.

[0226] If the random number value corresponding to step AKS105 is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the comparison and addition instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated will indicate the updated random number value to be updated. Then, when the initial value change random number update process P_RANCP ends due to the judgment result of step AKS105, the stored value of the random number counter indicating the updated random number value to be updated is stored as the current random number value. Therefore, in step AKS105, if the updated random number value to be updated does not match the random number initial value, the initial value change random number update process P_RANCP ends, allowing the updated random number value to be stored as the current random number value.

[0227] If the random number value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer in step AKS105 (step AKS105; No), the initial value random number counter pointed to when the value stored in the initial value pointer is incremented by 1 is loaded (step AKS106). In the configuration example AKB11 of the winning symbol random number data area shown in FIG. 10-13(A), the winning symbol initial value random number counter is provided in the next address F051[H] when 1 is incremented from the address F050[H] where the winning symbol random number initial value data buffer is provided. In addition, the normal symbol winning symbol initial value random number counter is provided in the next address F054[H] when 1 is incremented from the address F053[H] where the normal symbol winning symbol random number initial value data buffer is provided. Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the winning symbol, the count value of the initial value random number counter for the winning symbol is read out. Also, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the winning symbol, the count value of the initial value random number counter for the normal winning symbol is read out. In this way, in step AKS106, the count value of the initial value random number counter can be read out as the random number value for the initial value.

[0228] When the initial value random number counter is loaded in step AKS106, the count value of the initial value random number counter read thereby is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 can store the count value of the initial value random number counter as the current random number value to be updated. Therefore, if the result of the determination in step AKS105 is that the updated random number value to be updated matches the random number initial value, step AKS107 can store the initial value random number value read in step AKS106 as the current random number value.

[0229] Following step AKS107, the count value of the initial value random number counter read in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), and then the initial value change random number update process P_RANCP ends. Because the value stored in the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, step AKS108 allows the count value of the initial value random number counter to be stored as a new random number initial value. Therefore, if the updated random number value to be updated matches the random number initial value as determined in step AKS105, step AKS107 stores the random number value for the initial value as the current random number, and step AKS108 allows the random number value for the initial value read in step AKS106 to be stored as the new random number initial value. In this way, setting a new random number initial value increases the uncertainty of the random number value, and storing it as the current random number value also prevents an increase in data volume, enabling appropriate random number updating.

[0230] The random number update process P_RANDOM shown in Figure 10-12 executes the initial value change random number update process P_RANCP in step AKS64 after setting the random number value to be updated, the maximum random number value, and the initial random number value for the random numbers MR1-2 for the winning symbols in steps AKS61 to AKS63. The initial value change random number update process P_RANCP makes it possible to update the random number value to be updated and change the initial random number value based on the settings for the random number value to be updated, the maximum random number value, and the initial random number value. The initial value change random number update process P_RANCP in step AKS64 makes it possible to update the random numbers MR1-2 for the winning symbols that are set as the random number value to be updated in step AKS61 using the maximum random number set in step AKS62 and the initial random number set in step AKS63. In addition, the initial value change random number update process P_RANCP in step AKS64 enables the change of the random number initial value when the value of the random number MR1-2 for the winning symbol set as the random number value to be updated in step AKS61 matches the random number initial value set in step AKS63. In this way, by updating the set random number value to be updated, it becomes possible to update the random number value appropriately.

[0231] The random number update process P_RANDOM executes the initial value change random number update process P_RANCP in step AKS68 after setting the update target random number value, maximum random number value, and initial random number value for the random number MR2-1 for the normal symbol per win symbol in steps AKS65 through AKS67. The initial value change random number update process P_RANCP in step AKS68 enables the update of the random number MR2-1 for the normal symbol per win symbol set as the update target random number value in step AKS65 using the maximum random number value set in step AKS66 and the initial random number value set in step AKS67. Furthermore, the initial value change random number update process P_RANCP in step AKS68 enables the change of the initial random number value for the random number MR2-1 for the normal symbol per win symbol set as the update target random number value in step AKS65 when that value matches the initial random number value set in step AKS67. In this way, appropriate random number value updates are possible by updating the set update target random number value, etc. Furthermore, by updating the set random number value to be updated or changing the initial random number value, it becomes possible to update the random number value appropriately.

[0232] The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol, which is used to determine the display result of the special symbol, through a first update process consisting of steps AKS61 to AKS64, and can update the random number MR2-1 for the winning normal symbol, which is used to determine the display result of the normal symbol, through a second update process consisting of steps AKS65 to AKS68. The random number MR1-2 for the winning symbol is updated as the first random number value through steps AKS61 to AKS64, and then the random number MR2-1 for the winning normal symbol is updated as the second random number value through steps AKS65 to AKS68. The determined special symbol, which is the display result of the special symbol, corresponds to the maximum number of times the large prize opening is opened in the jackpot gaming state. The determined special symbol, which is the display result of the special symbol, may also correspond to whether or not the game is controlled to a probability variable state after the jackpot gaming state ends, or the maximum number of times the variable display can be performed in the time-saving state after the jackpot gaming state ends. In contrast, the confirmed normal symbol, which is the display result of the normal symbol, corresponds to the opening time and number of times the second large prize opening is opened. Therefore, the display result of the special symbol attracts more attention from players than the display result of the normal symbol. By updating the random number MR1-2 as the first random number value and then updating the random number MR2-1 as the second random number value using the random number update process P_RANDOM, which is a specific update process, the first random number value used to determine the display result that attracts the player's attention is updated before the second random number value, thereby suppressing the occurrence of malfunctions and enabling appropriate random number updates.

[0233] In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2 that will be the first random value value, and steps AKS65 to AKS68 can update the random number MR2-1 that will be the second random value value. The initial value change random number update process P_RANCP of step AKS64 can be called and executed in response to the random number MR1-2 that will be the first random value value, and the initial value change random number update process P_RANCP of step AKS68 can be called and executed in response to the random number MR2-1 that will be the second random value value. In this way, the random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 that will be the first random value value and the random number MR2-1 that will be the second random value value, making their initial values ​​changeable by calling the initial value change random number update process P_RANCP, which is a common update process, in response to the first random value value and the second random value value. The initial value change random number update process P_RANCP, which serves as a common update process, prevents an increase in program capacity, stably updates the first random number value and the second random number value, and enables appropriate random number value updates.

[0234] In the random number update process P_RANDOM, steps AKS61 to AKS64, which make the random number MR1-2, which will be the first random value value, updatable, constitute the first update process, and steps AKS65 to AKS68, which make the random number MR2-1, which will be the second random value value, updatable, constitute the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM updates the random number MR1-2, which will be the first random value value, and the random number MR2-1, which will be the second random value value, and makes their initial values ​​changeable by calling the initial value change random number update process P_RANCP as a common update process in both the first and second update processes. The initial value change random number update process P_RANCP, which serves as a common update process, prevents an increase in program capacity, stably updates the first random number value and the second random number value, and enables appropriate random number value updates.

[0235] In the random number update process P_RANDOM, steps AKS61 to AKS64, which make the random number MR1-2, which will be the first random number value, updatable, constitute the first update process, and steps AKS65 to AKS68, which make the random number MR2-1, which will be the second random number value, updatable, constitute the second update process. The first and second update processes use the HL, B, and DE registers of CPU 103, which are common internal storage means, to make the random numbers MR1-2, which will be the first random number value, and the random number MR2-1, which will be the second random number value, updatable. In this way, the first and second random number values ​​can be stably updated using the common internal storage means, enabling appropriate random number updating.

[0236] In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP in step AKS64, steps AKS61 to AKS63 store reference information such as the random number counter address for the winning symbol, the random number maximum judgment value for the winning symbol, and the random number initial value data buffer address for the winning symbol in the HL register, B register, and DE register of the CPU 103, which is internal storage means. Also, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP in step AKS68, steps AKS65 to AKS67 store reference information such as the random number counter address for the normal symbol winning symbol, the random number maximum judgment value for the normal symbol winning symbol, and the random number initial value data buffer address for the normal symbol winning symbol in the HL register, B register, and DE register of the CPU 103, which is internal storage means. The instruction used to update random number MR1-2, which becomes the first random number value in step AKS61, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS65, are common instructions in that they set the HL register of CPU 103, and step AKS61 sets the random number counter address for the winning symbol, but step AKS65 sets the random number counter address for the winning symbol for the normal symbol, so different reference information can be set. The instruction used to update random number MR1-2, which becomes the first random number value, in step AKS62, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS66, are common instructions in that they set the B register of CPU 103, and step AKS62 sets the random number maximum value corresponding to the winning symbol random number maximum judgment value, but step AKS66 sets the random number maximum value corresponding to the winning symbol random number maximum judgment value, so different reference information can be set.The instruction used to update random number MR1-2, which becomes the first random number value in step AKS63, and the instruction used to update random number MR2-1, which becomes the second random number value in step AKS67, are common instructions in that they set the DE register of CPU 103. Step AKS63 sets the random number initial value data buffer address for the winning symbol, while step AKS67 sets the random number initial value data buffer address for the winning symbol and the normal symbol, so different reference information can be set. These steps AKS61 to AKS63 and steps AKS65 to AKS67 make it possible to set different reference information using common instructions, such as the LD instruction and the LDQ instruction, which are transfer instructions for setting the internal registers of CPU 103. Then, steps AKS64 and AKS68 call and execute the initial value change random number update process P_RANCP using a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is a specific update process, the instruction used to update the random number MR1-2, which becomes the first random number value, and the instruction used to update the random number MR2-1, which becomes the second random number value, are the same. By making it possible to update the random number MR1-2, which becomes the first random number value, and the random number MR2-1, which becomes the second random number value, using the common instruction, it becomes possible to stably update the first random number value and the second random number value, and to update the random number values ​​appropriately.

[0237] The random number update process P_RANDOM enables updating of the random number MR1-2, which will be the first random value, through steps AKS61 to AKS64, which is the first update process, and enables updating of the random number MR2-1, which will be the second random value, through steps AKS65 to AKS68, which is the second update process. Steps AKS64 and AKS68 then call and execute the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP shown in Figure 10-14 first executes a single compare and add instruction, so that the compare and add instruction can be executed first both when updating the random number MR1-2 as the first random value and when updating the random number MR2-1 as the second random value. By executing this compare and add instruction first, it is possible to prevent errors from occurring in the first or second random value, and to update the random values ​​appropriately.

[0238] The initial value change random number update process P_RANCP, when executed in step AKS64 of the random number update process P_RANDOM, can update the random number MR1-2 for the winning symbol, and can change the random number initial value corresponding to the random number MR1-2 for the winning symbol using the random number MR1-3 that becomes the initial value for the winning symbol. Also, the initial value change random number update process P_RANCP, when executed in step AKS68 of the random number update process P_RANDOM, can update the random number MR2-1 for the winning normal symbol, and can change the random number initial value corresponding to the random number MR2-1 for the winning normal symbol using the random number MR2-2 that becomes the initial value for the winning normal symbol. Therefore, the random number MR1-3 serving as the initial value for the winning symbol is a first initial value random number value used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR1-2 for the winning symbol, which becomes the first random number value, when the initial value change random number update process P_RANCP is executed in step AKS64 of the random number update process P_RANDOM. The random number MR2-2 serving as the initial value for the winning normal symbol is a second initial value random number value used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR2-1 for the winning normal symbol, which becomes the second random number value, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM.

[0239] Figure 10-15 is a flowchart showing an example of the initial value determination random number update process P_TFINIT. The initial value determination random number update process P_TFINIT is included in the process that can be called from the game control main process P_MAIN shown in Figure 4, and can be executed in step S9 of the loop process that is repeated after step S7 until a timer interrupt occurs. The initial value determination random number update process P_TFINIT is also included in the process that can be called from the game control timer interrupt process P_PCT shown in Figure 5, and can be executed in step AKS57 in response to the occurrence of a periodic timer interrupt upon the lapse of a predetermined time, such as 4 ms. Therefore, the initial value determination random number update process P_TFINIT is included in a first process that can be executed in response to a timer interrupt upon the lapse of a predetermined time, and a second process that can be repeatedly executed until the first process is executed. Furthermore, the initial value determination random number update process P_TFINIT can be called and executed in the game control timer interrupt process P_PCT that controls the progress of the game, and can also be called and executed by step S9 included in the standby process as a repeated loop process after startup processes such as the power supply start response process P_POWER_ON in step S1 in the game control main process P_MAIN that is executed based on the start of power supply in the pachinko gaming machine 1. In this way, the initial value determination random number update process P_IFINIT is included in processes that can be executed in response to periodic timer interrupts as an initial value random number update process, and is also included in processes that can be repeatedly executed irregularly. This makes the update period and update speed of the initial value random number variable indefinite, thereby increasing the uncertainty of the initial value random number variable and enabling appropriate random number value update.

[0240] When the CPU 103 executes the initial value determination random number update process P_TINIT, it sets the winning symbol initial value random number counter address using a transfer instruction for setting a pointer (step AKS81). The winning symbol initial value random number counter address is address F051[H] assigned to the winning symbol initial value random number counter in the configuration example AKB11 of the winning symbol random number data area shown in FIG. 10-13(A). When the pointer is set in this manner, the count value of the winning symbol initial value random number counter can be updated within the update range of "0" to "199" using a comparison and addition instruction (step AKS82). This comparison and addition instruction can be executed by a single ICPLD instruction, which is the third special transfer instruction, with the stored data at the address pointed to by the pointer as the update target value and the immediate value specified by the operand as the comparison and judgment value. The stored value of the pointer indicates the address of the random number counter where numerical data corresponding to the update target initial value random number is stored. The immediate value specified by the operand indicates the maximum random number value for the initial value that is set corresponding to the random number value for the initial value to be updated. If the count value of the random number counter indicating the random number value for the initial value to be updated is less than the maximum random number value for the initial value, the count value of the random number counter is updated to increment by 1, thereby incrementing the random number value for the initial value to be updated by 1. On the other hand, if the count value of the random number counter indicating the random number value for the initial value to be updated is equal to or greater than the value stored in the maximum random number register for the initial value, the random number counter is cleared and initialized to "0", thereby changing the random number value for the initial value to be updated to the minimum random number value. Therefore, the compare and add instruction of step AKS82 is a single instruction that includes: setting the random number MR1-3, which is the initial value for the winning symbol, to the random number value for the update target initial value, comparing the random number value for the update target initial value with the maximum random number value for the initial value, incrementing the random number value for the update target initial value by 1 if the comparison result is less than the maximum random number value for the initial value, and changing the random number value for the update target initial value to the minimum random number value if the comparison result is equal to or greater than the maximum random number value for the initial value. Note that the compare and add instruction is not limited to the ICPLD instruction in which the address of the stored data indicating the update target value is specified by a pointer, and may also be, for example, an ICPLDQ instruction in which the upper address is set using the Q register and the lower address is set using the immediate value specified by the first operand of the compare and add instruction.In this case, the immediate value specified by the second operand of the compare-and-add instruction is set as the comparison judgment value. By using such a compare-and-add instruction to update the random value for the initial value to be updated, it is possible to prevent malfunctions and update the random value appropriately.

[0241] After step AKS82, a transfer command for setting a pointer is used to set the address of the initial value random number counter for the normal symbol (step AKS83). The address of the initial value random number counter for the normal symbol is address F054[H] assigned to the initial value random number counter for the normal symbol in the configuration example AKB11 of the random number data area for the winning symbol shown in FIG. 10-13(A). When the pointer is set in this way, a comparison and addition command is used to make the count value of the initial value random number counter for the normal symbol updatable within the update range of "1" to "198" (step AKS84), and the initial value determination random number update process P_TFINIT is completed. The comparison and addition command of step AKS84 may be the same comparison and addition command as step AKS82. However, in the comparison and addition instruction of step AKS84, the random number MR2-2, which is the initial value for the normal symbol per symbol, is set as the random number value for the update target initial value, so the immediate value specified by the operand indicating the maximum random number value for the initial value is set to a value different from that of the comparison and addition instruction of step AKS82. Therefore, the comparison and addition instruction of step AKS84 is a single instruction that includes setting the random number MR2-2, which is the initial value for the normal symbol per symbol, to the random number value for the update target initial value, comparing the random number value for the update target initial value with the maximum random number value for the initial value, incrementing the random number value for the update target initial value by 1 if the result of the comparison is less than the maximum random number value for the initial value, and changing the random number value for the update target initial value to the minimum random number if the result of the comparison is greater than or equal to the maximum random number value for the initial value. By updating the random number value for the update target initial value using such a comparison and addition instruction, the occurrence of malfunctions can be suppressed and appropriate random number value updating can be achieved.

[0242] The random number update process for determining initial values ​​P_TFINIT updates the random number MR1-3 that will be the initial value for the winning symbol in steps AKS81 and AKS82 as an update of the random number value for the first initial value. At the same time, the random number update process for determining initial values ​​P_TFINIT updates the random number MR2-2 that will be the initial value for the winning symbol in steps AKS83 and AKS84 as an update of the random number value for the second initial value. The random number MR1-3 that will be the initial value for the winning symbol is the first random number value used when changing the random number initial value when the random number value to be updated is the random number MR1-2 for the winning symbol, which is the first random number value. The random number MR2-2 that will be the initial value for the winning symbol in the normal symbol is the second random number value used when changing the random number initial value when the random number value to be updated is the random number MR2-1 for the winning symbol, which is the second random number value. Steps AKS81 and AKS82 of the random number update process for determining initial values ​​P_TFINIT are first initial value update processes that can update the random number values ​​for the first initial values. Steps AKS83 and AKS84 of the random number update process for determining initial values ​​P_TFINIT are second initial value update processes that can update the random number values ​​for the second initial values. By updating the random number values ​​for the first initial values ​​and the random number values ​​for the second initial values ​​in this way, it is possible to update the random number values ​​appropriately so as to reliably increase the uncertainty of the first random number values ​​and the second random number values.

[0243] Further, the initial value determination random number update process P_TFINIT updates the random number MR1-3 which will be the initial value for the winning symbol as the first initial value random number value in steps AKS81 and AKS82, and then updates the random number MR2-2 which will be the initial value for the winning symbol as the second initial value random number value in steps AKS83 and AKS84. Therefore, the initial value determination random number update process P_TFINIT updates the random number MR1-3 which will be the initial value for the winning symbol as the first initial value random number value in steps AKS81 and AKS82 which are the first initial value update process, and then updates the random number MR2-1 which will be the initial value for the winning symbol as the second initial value random number value in steps AKS83 and AKS84 which are the second initial value update process.

[0244] FIG. 10-16 is a flowchart showing an example of the start port switch passing process P_TZU_ON. The start port switch passing process P_TZU_ON is included in the processes that can be called from the special symbol process process P_TPROC shown in FIG. 6, and can be executed in step S104 if the first start winning corresponding flag is on in step S103, and can be executed in step S108 if the second start winning corresponding flag is on in step S107. When the CPU 103 executes the start port switch passing process P_TZU_ON, it sets the start port winning memory counter address by a transfer command for setting a pointer (step AKS201). The start port winning memory counter address is the address of the first start port winning memory counter or the second start port winning memory counter provided in the game work area of ​​RAM 102. In step AKS201, a different address in the game work area can be specified corresponding to the first or second starting gate winning table set by the special symbol process P_TPROC. For example, the upper address F0[H] of the game work area, which serves as the working area, is set to the upper byte of the pointer by a transfer command, and the lower address of the starting gate winning memory counter stored in the first or second starting gate winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. As a result, the value indicating the address of the first or second starting gate winning memory counter is stored in the internal register of CPU 103, which serves as the pointer. Next, the starting gate winning memory counter is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AKS202).

[0245] After step AKS202, it is determined whether the count value of the start port winning memory counter is equal to or greater than the counter maximum value (step AKS203). For example, a comparison return instruction can compare the value loaded in step AKS202 with a counter maximum value such as "4." If the value is equal to or greater than the counter maximum value (step AKS203; Yes), the start port switch passing processing P_TZU_ON ends and returns to the special symbol process processing P_TPROC. On the other hand, if the value is less than the counter maximum value (step AKS203; No), the count value of the start port winning memory counter is updated by adding 1 (step AKS204). In this case, an arithmetic and logic operation instruction that increments the stored data at the address pointed to by the pointer can update the count value of the first start port winning memory counter or the second start port winning memory counter by adding 1.

[0246] After step AKS204, the special symbol determination buffer address is set as the transfer destination (step AKS205). The special symbol determination buffer address is the address of the first special symbol determination buffer included in the first special symbol reserve buffer or the second special symbol determination buffer included in the second special symbol reserve buffer provided in the game work area of ​​RAM 102. In step AKS205, different addresses in the game work area can be specified corresponding to the first start port winning table or the second start port winning table set by the special symbol process processing P_TPROC and the count value of the first start port winning counter or the second start port winning counter loaded in step AKS202.

[0247] The first special symbol reserve buffer is a first reserve memory buffer including a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first loss effect selection buffer, and is secured as a plurality of memory areas, for example, five memory areas corresponding to buffer numbers "0" to "4," corresponding to when the variable display of the first special symbol is being executed and the number of first reserve memories that have not yet been executed. The second special symbol reserve buffer is a second reserve memory buffer including a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second loss effect selection buffer, and is secured as a plurality of memory areas, for example, five memory areas corresponding to buffer numbers "0" to "4," corresponding to when the variable display of the second special symbol is being executed and the number of second reserve memories that have not yet been executed.

[0248] In step AKS205, the value corresponding to the buffer size of the first reserved memory buffer or the second reserved memory buffer is multiplied by the count value of the start port winning counter, and the multiplied value is added to the lower address of the first reserved memory buffer or the second reserved memory buffer with buffer number "1". By setting this added value to the transfer destination pointer, the special symbol determination buffer address can be set to the transfer destination.

[0249] Following step AKS205, the RL0 hard latch random number register address is set (step AKS206). The RL0 hard latch random number register address is the address of the RL0 hard latch random number register provided in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by a transfer command, and the lower address of the RL0 hard latch random number register stored in the first start port winning table or the second start port winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. The first start port winning table stores the lower address of the RL0 hard latch random number register with buffer number "0." The second start port winning table stores the lower address of the RL0 hard latch random number register with buffer number "1." As a result, different addresses are stored in the internal register of CPU 103 that serve as pointers as the addresses of the RL0 hard latch random number register for the first start port winning and the second start port winning.

[0250] After step AKS206, the RL0 hard latch random number register is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AK207). The value stored in the RL0 hard latch random number register thus obtained is stored in the special symbol determination random number buffer by a transfer command to write it to a memory area at a specified address in the game work area of ​​RAM 102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, numerical data indicating the value of the special symbol determination random number MR1-1 is extracted, and the value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

[0251] After step AKS208, the RL2 soft latch random number register is loaded by a transfer command to read stored data from a memory area at a specified address in the function control register area (step AKS209). The value stored in the RL2 soft latch random number register obtained at this time is stored in the random number buffer for selecting a losing effect by a transfer command to write it to a memory area at a specified address in the game work area of ​​RAM 102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random number register in the random number buffer for selecting a losing effect, numerical data indicating the value of the random number MR3-2 for selecting a losing effect is extracted, and the value of the random number MR3-2 can be stored in the random number buffer for selecting a losing effect.

[0252] After step AKS210, the RS1 soft latch random number register is loaded by a transfer command to read the stored data from the memory area of ​​the specified address in the function control register area (step AKS211). The value stored in the RS1 soft latch random number register acquired at this time is stored in the random number buffer for selecting a variation pattern type by a transfer command to write it to the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS212). In this way, by storing the numerical data acquired from the RS1 soft latch random number register in the random number buffer for selecting a variation pattern type, numerical data indicating the value of the random number MR3-3 for selecting a variation pattern type is extracted, and the value of the random number MR3-3 can be stored in the random number buffer for selecting a variation pattern type.

[0253] After step AKS212, the RS2 soft latch random number register is loaded by a transfer command to read the stored data from the memory area of ​​the specified address in the function control register area (step AKS213). The stored value of the RS2 soft latch random number register acquired at this time is stored in the random number buffer for fluctuation patterns by a transfer command to write it to the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS214). In this way, by storing the numerical data acquired from the RS2 soft latch random number register in the random number buffer for fluctuation patterns, numerical data indicating the value of the random numbers MR3-4 for fluctuation patterns is extracted, and the value of the random numbers MR3-4 can be stored in the random number buffer for fluctuation patterns.

[0254] Following step AKS214, a block transfer is performed from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer includes a special symbol determination random number buffer in which the value of random number MR1-1 is stored in step AKS208, a loss effect selection random number buffer in which the value of random number MR3-2 is stored in step AKS210, a variation pattern type selection random number buffer in which the value of random number MR3-3 is stored in step AKS212, and a variation pattern random number buffer in which the value of random number MR3-4 is stored in step AKS214. In step AKS215, the address of the special symbol determination random number buffer is set as the transfer source, and a value corresponding to the buffer size of the random number buffer is set as the number of transfers. The special symbol determination buffer address, which is the transfer destination, is set in step AKS205. Based on these settings, by executing a block transfer command, the value of each random number temporarily stored in the random number buffer can be stored as new reserved information in the first reserved memory buffer or the second reserved memory buffer.

[0255] Once the new memory information is stored in step AKS215, it is determined whether the winning effect conditions are met (step AKS216). The winning effect conditions may be preset as conditions that enable the execution of the pre-reading effect. For example, if the starting gate winning designation value is "2," it is determined that the winning effect conditions are met. Also, if the starting gate winning designation value is "1," it is determined that the winning effect conditions are met if the time-saving function flag is "0" corresponding to the non-time-saving state, and the special symbol process code is less than 03 [H] corresponding to the non-small win or big win game state. If it is determined that the winning effect conditions are met (step AKS216; Yes), the winning effect processing P_GAME_CHK is executed (step AKS217). The winning effect processing P_GAME_CHK includes determining whether the special symbol has been hit, selecting the effect designation value corresponding to the determination result, and enabling the winning effect command to be sent.

[0256] If it is determined in step AKS216 that the winning effect conditions are not met (step AKS216; No), or after the winning effect processing in step AKS217 is executed, a transfer command for setting a pointer is issued to set the effect memory information designation command transmission table address (step AKS218). The effect memory information designation command transmission table address is the address of the effect memory information designation command transmission table stored in the game data area of ​​ROM 101. Then, by executing command set processing P_COM_SET (step AKS219), it becomes possible to transmit the first effect memory information designation command or the second effect memory information designation command as the start winning command. The first effect memory information designation command is a performance control command that designates the first reserved memory number indicated by the count value of the first starting gate winning memory counter. The second effect memory information designation command is a performance control command that designates the second reserved memory number indicated by the count value of the second starting gate winning memory counter. In this way, the command set processing P_COM_SET in step AKS219 allows the performance control command, which becomes the command at the time of the initial winning, to be sent from the main board 11 to the performance control board 12.

[0257] Following step AKS219, a transfer command for setting a pointer is used to set the start port winning buffer memory counter address (step AKS220). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of ​​RAM 102. In this manner, the count value of the start port winning buffer memory counter whose address has been set is updated by incrementing it by 1 (step AKS221). Furthermore, a composite transfer command for setting a register or pointer is used to update the pointer corresponding to the start port winning buffer memory counter (step AKS222). For example, the count value of the start port winning buffer memory counter after update in step AKS221 is loaded into an internal register of CPU 103, and the stored value of the pointer is updated by incrementing it by 1, thereby storing a value indicating the starting address of the start port winning buffer in the pointer. Furthermore, the count value of the loaded start port winning buffer memory counter is added to the stored value of the pointer, thereby making it possible to identify the storage area of ​​the buffer number to be updated in the start port winning buffer.

[0258] After updating the pointer in step AKS222, a start port winning designation value is loaded (step AKS223). The start port winning designation value can be set to "1" indicating a first start port winning or "2" indicating a second start port winning, corresponding to the first start port winning table or the second start port winning table set by the special symbol process processing P_TPROC. In step AKS223, a transfer command for reading table data from the first start port winning table or the second start port winning table is issued, making it possible to acquire the start port winning designation value. The acquired start port winning designation value is stored in the start port winning buffer by a transfer command for writing it to the memory area of ​​the address pointed to by the pointer (step AKS224), and the start port switch passing processing P_TZU_ON is terminated.

[0259] Figure 10-17 is a diagram illustrating an example of the data structure used in the start gate switch pass process P_TZU_ON. In the start gate switch pass process P_TZU_ON, various settings and controls are performed using the first start gate winning table set in step S102 or the second start gate winning table set in step S106 of the special symbol process process P_TPROC shown in Figure 6. For example, the first start gate winning memory counter and the second start gate winning memory counter, whose counts can be updated in step AKS204, are provided in the special symbol control data area and can store data corresponding to the first and second reserved memory numbers. The start gate winning buffer memory counter, whose counts can be updated in AKS221, and the start gate winning buffer, in which the start gate winning designation value is stored in AKS224, are provided in the start gate winning buffer area and can store the total number of first and second start gate winnings and the order of occurrence. In addition, in the command set process P_COM_SET in step AKS219, the first effect storage information designation command transmission table or the second effect storage information designation command transmission table whose address is set in step AKS218 is used.

[0260] In this way, the start port switch passing processing P_TZU_ON enables control of the special pattern game, which is a variable display of special patterns, using the first start port winning table or the second start port winning table, the first start port winning memory counter or the second start port winning memory counter provided in the special pattern control data area, the start port winning buffer memory counter or the start port winning buffer provided in the start port winning buffer area, and the first effect memory information designation command sending table or the second effect memory information designation command sending table.

[0261] 10-17(A1) shows a configuration example AKT21 of the first start port winning table. The first start port winning table of the configuration example AKT21 is configured to include table data indicating the lower address of the first start port winning memory counter, the lower address of the RL0 hard latch random number register number "0", the lower address of the first special symbol determination buffer number "1", the address of the first performance memory information designation command transmission table, and the start port winning designation value "1".

[0262] The first start gate winning memory counter is located in the game work area of ​​RAM 102 and can store data corresponding to the first reserved memory number. The RL0 hard latch random number register number "0" is the RL0 hard latch random number register with register number "0" located in the function control register area. It can acquire and store numerical data indicating the value of the special symbol determination random number MR1-1, which can be generated by channel RL0 of the 16-bit random number circuit 104A. The first special symbol determination buffer number "1" is the first special symbol determination buffer included in the first reserved memory buffer with buffer number "1" in the first special symbol reservation buffer. The first effect memory information designation command transmission table is stored in the game data area of ​​ROM 101 and is used when transmitting the first effect memory information designation command that specifies the first reserved memory number. The start gate winning designation value "1" is a designated value that identifiably indicates that a first start win has occurred.

[0263] 10-17(A2) shows a configuration example AKT22 of the second start port winning table. The second start port winning table of the configuration example AKT22 is configured to include table data indicating the lower address of the second start port winning memory counter, the lower address of the RL0 hard latch random number register number "1", the lower address of the second special symbol determination buffer number "1", the address of the second performance memory information designation command transmission table, and the start port winning designation value "2".

[0264] The second start gate winning memory counter is located in the game work area of ​​RAM 102 and can store data corresponding to the second reserved memory number. The RL0 hard latch random number register number "1" is the RL0 hard latch random number register with register number "1" located in the function control register area. It can acquire and store numerical data indicating the value of the special symbol determination random number MR1-1, which can be generated by channel RL0 of the 16-bit random number circuit 104A. The second special symbol determination buffer number "1" is the second special symbol determination buffer included in the second reserved memory buffer with buffer number "1" in the second special symbol reservation buffer. The second effect memory information designation command transmission table is stored in the game data area of ​​ROM 101 and is used when transmitting the second effect memory information designation command that specifies the second reserved memory number. The start gate winning designation value "2" is a designated value that can identify the occurrence of a second start win.

[0265] Figure 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of ​​the configuration example AKB21 can store various data related to control by the special symbol process P_TPROC, such as the special symbol game, which is a variable display of special symbols, and the small win game state and big win game state that can be controlled based on the display result. This special symbol control data area includes a special symbol process timer at address F030[H], a win flag at address F032[H], a special symbol process code at address F033[H], a first start port winning memory counter at address F034[H], a big win symbol determination buffer at address F035[H], a small win symbol determination buffer at address F036[H], a large prize port winning number counter at address F037[H], a large prize port opening count counter at address F038[H], a large prize port opening pattern timer at address F039[H], a large prize port opening pattern table pointer at address F03B[H], a demo display flag at address F03D[H], and a second start port winning memory counter at address F099[H].

[0266] The special symbol process timer can store a time value corresponding to the control time by the special symbol process processing P_TPROC. The special symbol process code can specify the processing selected in the special symbol process processing P_TPROC. The first start port winning memory counter can store a count value corresponding to the first reserved memory number. The jackpot symbol determination buffer can store data corresponding to the jackpot symbol designated value. The jackpot symbol designated value is a designated value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "jackpot", and makes it possible to set the type of jackpot game state. The small jackpot symbol determination buffer can store data corresponding to the small jackpot symbol designated value. The small jackpot symbol designated value is a designated value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "small jackpot", and makes it possible to set the type of alcohol in the small jackpot game state. The large prize opening number counter can store a count value corresponding to the number of game balls that have passed through the large prize opening formed by the special variable prize ball device 50. The large prize opening number counter can store a count value corresponding to the number of times the large prize opening has been opened in a small prize game state or a big prize game state. The large prize opening pattern timer can store a time value corresponding to the remaining time for controlling the large prize opening to an open state in a small prize game state or a big prize game state. The large prize opening pattern table pointer can specify a storage address in the large prize opening pattern table in which the opening time of the large prize opening is set. The demo display flag can store a flag value corresponding to an on or off state depending on whether a demonstration display is being executed. The second start opening memory counter can store a count value corresponding to the second reserved memory number.

[0267] Figure 10-17 (B2) shows a configuration example AKB22 of the start port winning buffer area. The start port winning buffer area of ​​configuration example AKB22 can store various data related to the first start winning and second start winning that occur when the gaming ball enters the first start winning port or the second start winning port. This start port winning buffer area includes a start port winning buffer memory counter at address F0BA[H] and start port winning buffer numbers "0" to "8" at addresses F0BB[H] to F0C3[H].

[0268] The start port winning buffer memory counter can store a count value corresponding to the number of valid start port winning designation values ​​stored in the start port winning buffer area. Therefore, the count value of the start port winning buffer memory counter indicates the total number of first start winnings and second start winnings. The start port winning buffer numbers "0" to "8" are start port winning buffers assigned buffer numbers "0" to "8", and can store start port winning designation values ​​in the order in which the first start winnings and second start winnings occurred. As a result, the stored information in the start port winning buffer indicates the order in which the first start winnings and second start winnings occurred.

[0269] Figure 10-17 (C1) shows an example configuration AKT23 of the first effect memory information designation command transmission table. The first effect memory information designation command transmission table of the example configuration AKT23 is configured to include table data indicating the upper byte of the first effect memory information designation command and the reference designation value of the first start port winning memory counter. The command set processing P_COM_SET of step AKS219 enables the first effect memory information designation command to be transmitted when the first effect memory information designation command transmission table is used. The first effect memory information designation command can set the lower byte corresponding to the count value of the first start port winning memory counter. By transmitting such a first effect memory information designation command, the first pending memory number can be notified to the effect control board 12.

[0270] Figure 10-17 (C2) shows an example configuration AKT24 of the second effect memory information designation command transmission table. The second effect memory information designation command transmission table of the example configuration AKT24 is configured to include table data indicating the upper byte of the second effect memory information designation command and the reference designation value of the second start port winning memory counter. The command set processing P_COM_SET of step AKS219 enables the second effect memory information designation command to be transmitted when the second effect memory information designation command transmission table is used. The second effect memory information designation command can set the lower byte corresponding to the count value of the second start port winning memory counter. By transmitting such a second effect memory information designation command, the second reserved memory number can be notified to the effect control board 12.

[0271] The start gate switch passing process P_TZU_ON shown in Figure 10-16 stores the value stored in the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a losing effect in step AKS210, thereby enabling the extraction of numerical data indicating the value of the random number MR3-2 for selecting a losing effect. The start gate switch passing process P_TZU_ON also stores the value stored in the RS1 soft latch random number register loaded in step AKS211 in the random number buffer for selecting a variation pattern type in step AKS212, thereby enabling the extraction of numerical data indicating the value of the random number MR3-3 for selecting a variation pattern type. The start gate switch passing process P_TZU_ON also stores the value stored in the RS2 soft latch random number register loaded in step AKS213 in the random number buffer for a variation pattern in step AKS214, thereby enabling the extraction of numerical data indicating the value of the random number MR3-4 for a variation pattern. Here, if the random number MR3-2 for selecting a losing effect is the first random number value, the random number MR3-3 for selecting a variation pattern type is the second random number value, and the random number MR3-4 for the variation pattern is the third random number value, the start port switch passing process P_TZU_ON is executed in response to the occurrence of a starting winning, so the first random number value, the second random number value, and the third random number value can be extracted when the common extraction condition of the occurrence of a starting winning is met. The random number MR3-2 for selecting a losing effect is included in the game random numbers that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for the variation pattern are included in the game random numbers that can be updated by the 8-bit random number circuit 104B, and the total number of random numbers included in the update range for both is a prime number. The update rate of random number MR3-2 is 469 times / ms, while the update rate of random numbers MR3-3 and MR3-4 is 938 times / ms. In other words, the update rate of random numbers MR3-3 and MR3-4 is an integer multiple of twice the update rate of random number MR3-2.The update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-4 is "0" to "250", so the total number of random values ​​included in each update range is different, and the total number of random values ​​included in each update range is a prime number. In this way, when the update rates of the second random number value and the third random number value are integer multiples of the update rate of the first random number value, the total number of random value values ​​included in each update range is different, and the total number of random value values ​​included in each update range is a prime number. This prevents synchronization between the first random number value, the second random number value, and the third random number value, enabling appropriate random number updating.

[0272] FIG. 10-18 is a flowchart showing an example of the special symbol normal processing P_TNORMAL. The special symbol normal processing P_TNORMAL is included in the processing that can be called from the special symbol process processing P_TPROC shown in FIG. 6, and can be executed in step S112 when the special symbol process code loaded in step S110 is 00[H]. When the special symbol normal processing P_TNORMAL is executed, the CPU 103 sets the start port winning buffer memory counter address by a transfer command for setting a pointer (step AKS241). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of ​​RAM 102. In this way, it is determined whether the count value of the start port winning buffer memory counter whose address has been set is "0" (step AKS242). For example, an arithmetic jump instruction that branches processing depending on whether the stored data at the address pointed to by the pointer is 00[H] corresponding to "0" or not makes it possible to execute different processing contents depending on whether the count value of the start port winning buffer storage counter is "0" or other than "0."

[0273] If the count value of the start port winning buffer memory counter is not "0" in response to step AKS242 (step AKS242; No), the count value of the start port winning buffer memory counter is updated to subtract 1 (step AKS243). Also, a block transfer for shifting the start port winning buffer is performed (step AKS244). In step AKS244, the destination address is set to the lower address BB[H] of start port winning buffer number "0", the source address is set to the lower address BC[H] of start port winning buffer number "1", and the number of transfers is set to "8", which is the buffer size of the start port winning buffer. Then, by executing a block transfer command, the memory contents in the start port winning buffer can be transferred and shifted one unit at a time to the previous buffer. Then, the memory area of ​​start port winning buffer number "8" can be initialized by clearing it.

[0274] Following step AKS244, a transfer command for setting a table pointer is used to set a second special symbol determination control table address (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of ​​ROM 101. At this time, a start port winning check process is executed to determine whether the start port winning designation value is "1" (step AKS246). For example, in the start port winning check process, if the start port winning designation value is "1," the zero flag is turned on, and if the start port winning designation value is "2," the zero flag is turned off. After this start port winning check process is executed, a jump command is used to branch the process depending on whether the zero flag is off, allowing different processing to be executed depending on whether the start port winning designation value is "1" or "2."

[0275] If the start gate winning designation value is "1" in response to step AKS246 (step AKS246; Yes), a transfer command for setting a table pointer is used to set a first special symbol determination control table address (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of ​​ROM 101. In step AKS247, a transfer command for setting a table pointer is used to overwrite the value of the table pointer. Thus, in the special symbol normal processing P_TNORMAL, after the second special symbol determination control table address is set in step AKS245, the start gate winning designation value corresponds to "1" in step AKS246, and the first special symbol determination control table address is overwritten and reset in step AKS247. This reduces the program capacity required for table setting when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, thereby improving the marketability of the pachinko gaming machine 1. In addition, when the frequency of use of the second special pattern determination control table is higher than the frequency of use of the first special pattern determination control table, processing using a jump command as a branch command can be simplified, making it easier to check at the design stage and improving the marketability of the pachinko game machine 1.

[0276] If the starting port winn...

Claims

[Claim 1] A gaming machine that can variably display identification information including first identification information and second identification information, and can be controlled to an advantageous state that is advantageous to a player, The display of the identification information can be variably performed based on a plurality of types of variable display patterns including a predetermined variable display pattern, In a presentation mode including a first presentation mode and a second presentation mode, a plurality of types of background images including a first background image and a second background image can be switched and displayed; In the first presentation mode, when the background image is switched from the first background image corresponding to the first presentation mode to the second background image corresponding to the first presentation mode, a background fade-out display is executed in which the transparency of the first background image corresponding to the first presentation mode is gradually increased, and a background fade-in display is executed in which the transparency of the second background image corresponding to the first presentation mode is gradually decreased, In the second presentation mode, when the background image is switched from the first background image corresponding to the second presentation mode to the second background image corresponding to the second presentation mode, a background fade-out display is executed in which the transparency of the first background image corresponding to the second presentation mode is gradually increased, and a background fade-in display is executed in which the transparency of the second background image corresponding to the second presentation mode is gradually decreased, In the first presentation mode and the second presentation mode, the region in which the identification information is variably displayed includes at least a first region and a second region; when starting the variable display of the identification information, starting the variable display of the first identification information in the first area and starting the variable display of the second identification information in the second area; a first identification information fade-out display can be performed by gradually increasing the transparency of the first identification information in the first area when variable display of the first identification information is started, and a second identification information fade-out display can be performed by gradually increasing the transparency of the second identification information in the second area when variable display of the second identification information is started, When terminating the variable display of the identification information, the variable display of the first identification information is slowed down in the first area, and the variable display of the second identification information is slowed down in the second area; When the variable display of the first identification information is slowed down, a first identification information fade-in display can be executed in which the transparency of the first identification information is gradually decreased in the first area, and when the variable display of the second identification information is slowed down, a second identification information fade-in display can be executed in which the transparency of the second identification information is gradually decreased in the second area, At least one of the first identification information fade-out display in the first presentation mode or the second identification information fade-out display in the first presentation mode and the background fade-out display in the first presentation mode can be executed at a specific timing, At least one of the first identification information fade-out display in the second presentation mode or the second identification information fade-out display in the second presentation mode and the background fade-out display in the second presentation mode can be executed at a predetermined timing, The length of the execution period of the fade-out display of the first identification information in the first presentation mode and the length of the execution period of the fade-out display of the second identification information in the first presentation mode are the same, The length of the execution period of the fade-out display of the first identification information in the second presentation mode and the length of the execution period of the fade-out display of the second identification information in the second presentation mode are common, a duration of the background fade-out display in the first presentation mode is longer than a duration of the first identification information fade-out display in the first presentation mode and a duration of the second identification information fade-out display in the first presentation mode; a duration of the background fade-out display in the second presentation mode is longer than a duration of the first identification information fade-out display in the second presentation mode and a duration of the second identification information fade-out display in the second presentation mode; When the specific identification information is variably displayed in the predetermined variable display pattern, the fade-out display of the first identification information in the first presentation mode and the fade-out display of the second identification information in the first presentation mode can be executed over a first execution period, When the specific identification information is variably displayed in the predetermined variable display pattern, the fade-out display of the first identification information in the second presentation mode and the fade-out display of the second identification information in the second presentation mode can be executed over a second execution period different from the first execution period, A predetermined number of pending displays corresponding to variable displays that have not yet started can be updated and displayed up to the upper limit. the identification information includes a character representation, As the variable display of the identification information, a scroll action and a pre-start action in which the character display moves before the start of the scroll action can be executed, The pre-start action is executed after the pending display is updated. A gaming machine characterized by:

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