Processing circuit, wireless communication circuit and semiconductor integrated circuit

Abstract

To reduce noises based on a clock signal.SOLUTION: A processing circuit includes: a clock generation circuit that generates a first clock signal having a frequency higher than that of a reference clock signal on the basis of the reference clock signal and a division ratio; a division and delay circuit that divides the first clock signal on the basis of a phase shift setting signal and the division ratio, and generates a second clock signal including a frequency lower than that of the first clock signal so as to have a first phase difference from the reference clock signal by delaying; an analog-digital conversion circuit that converts an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; a digital signal processing circuit that executes processing in accordance with the digital signal on the basis of the second clock signal; and a control circuit that generates the conversion trigger signal so as to have the same period as that of the second clock signal on the basis of the division ratio and the first clock signal.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a processing circuit, a wireless communication circuit, and a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 describes a wireless communication device having a communication unit capable of transmitting and receiving short-range communication radio waves, and a conversion unit that converts a received signal generated in response to reception of the short-range communication radio waves based on a first reference signal to an intermediate frequency. The generation unit generates a transmission signal used to transmit the short-range communication radio waves based on a second reference signal having a frequency different from the first reference signal. The supply unit is capable of switching between supplying the first reference signal to the conversion unit and supplying the second reference signal to the generation unit.

[0003] Patent Document 2 describes an analog-to-digital conversion circuit having a first circuit that generates an analog voltage based on a sampled analog signal and a digital code, and a clock generation circuit that generates a first clock signal. A comparison circuit receives the analog voltage output by the first circuit and outputs a digital signal based on the first clock signal. A DAC control circuit generates a digital code based on the digital output of the comparison circuit. The clock generation circuit varies the delay period from the end of sampling of the analog signal to the start of generation of the first clock signal for each sampling of the analog signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2018 / 207499 [Patent Document 2] Japanese Patent Application Publication No. 2018-152768 Summary of the Invention [Problem to be solved by the invention]

[0005] Since wireless communication devices receive weak radio waves, they are sensitive to even slight noise, and are prone to deterioration of reception sensitivity due to noise.

[0006] The object of the present invention is to be able to reduce noise due to clock signals. [Means for solving the problem]

[0007] The wireless communication circuit has a mixer circuit that mixes a received signal with a third clock signal generated based on a reference clock signal, a second clock generation circuit that generates the third clock signal based on the reference clock signal so that the third clock signal has a higher frequency than the reference clock signal, and a processing circuit that inputs an analog signal based on an output signal of the mixer circuit, wherein the processing circuit has a first clock generation circuit that generates a first clock signal having a higher frequency than the reference clock signal based on the reference clock signal and a frequency setting signal, and a second clock generation circuit that divides and delays the first clock signal based on a phase shift setting signal and the frequency setting signal to generate a first clock signal having a first phase difference from the reference clock signal and the same frequency as the reference clock signal. an analog-to-digital conversion circuit that converts the analog signal into a digital signal based on the first clock signal and a conversion trigger signal that indicates a sampling period and a conversion period; a digital signal processing circuit that performs processing according to the digital signal based on the second clock signal; and a control circuit that generates the conversion trigger signal based on the frequency setting signal and the first clock signal so that it has the same period as the second clock signal, wherein the second clock generation circuit is a decimal division or fractional division phase-locked loop circuit that has a delta-sigma modulation circuit that is driven at a phase different from that of at least one of the analog-to-digital conversion circuit and the digital signal processing circuit. [Effects of the Invention]

[0008] Noise due to the clock signal can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a wireless communication circuit according to a first comparative example. [Figure 2] FIG. 2 is a timing chart showing an example of a clock signal, a conversion trigger signal, an internal state of the analog-to-digital converter circuit, and output data of the analog-to-digital converter circuit. [Figure 3] FIG. 3 is a diagram showing the phase relationship between the reference clock signal and the clock signal. [Figure 4] FIG. 4 is a diagram illustrating an example of the configuration of a wireless communication circuit according to a second comparative example. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a semiconductor integrated circuit according to this embodiment. [Figure 6] FIG. 6 is a diagram showing the phase relationship of clock signals. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of a frequency divider circuit, a frequency divider and delay circuit, and an ADCC. [Figure 8] FIG. 8 is a timing chart showing an example of the operation of the frequency divider circuit, the frequency divider and delay circuit, and the ADCC. [Figure 9] 9A and 9B are timing charts showing examples of clock signals and currents. [Figure 10]10A and 10B are timing charts showing an example of the operation of the wireless communication circuit. DETAILED DESCRIPTION OF THE INVENTION

[0010] FIG. 1 is a diagram showing an example of the configuration of a wireless communication circuit 101 according to a first comparative example. The wireless communication circuit 101 is used, for example, in an electronic toll collection system (ETC: Electric Toll Collection System). ETC is a payment system for tolls on toll roads, and is installed throughout Japan. A dedicated short-range communication (DSRC) system makes the automatic collection technology of ETC (two-way communication technology between an on-board unit and roadside) available in various fields. SR C is expected to be used in areas such as parking lot management, logistics management, and gasoline payment.

[0011] DSRC is a wireless communication system that uses the 5.8 GHz band and is specified in the ARIB STD-T75 standard. Two modulation methods are used: ASK and π / 4 shift QPSK. ASK modulation uses a split-phase coded 2048 kbaud modulated signal, with a signal transmission speed of 1024 kbps. QPSK modulation uses a quadrature phase-shift keyed 2048 kbaud modulated signal, with a signal transmission speed of 4096 kbps. Because the symbol rate is 2048 kbaud in both ASK and QPSK, the wireless communication circuit 101 can be shared and can be implemented to support both modulation methods.

[0012] In the wireless communication circuit 101, it is desirable to implement signal processing that can be realized digitally using logic circuits whenever possible. This is because the processing results of digital circuits are deterministic, and various problems that arise when implemented using analog circuits, such as individual differences in characteristics due to manufacturing variations, characteristic degradation due to device noise, and temperature drift of characteristics, can be eliminated. In the past, when the scale of digital signal processing increased, there were constraints on scale and speed. However, as manufacturing processes have evolved and lithography has shrunk, constraints on logic scale have rapidly decreased.

[0013] One of the important components of the wireless communication circuit 101 is the analog-to-digital converter (ADC) 115. The analog-to-digital converter 115 for digitizing analog signals is placed at the boundary between the analog signal processing circuit and the digital signal processing circuit. The analog-to-digital converter 115 converts the input signal into a digital code that corresponds to the magnitude of the signal voltage.

[0014] An antenna 102 and an oscillator circuit 103 are connected to the wireless communication circuit 101. The wireless communication circuit 101 is a receiving circuit, and includes a low noise amplifier circuit (LNA) 111, a quadrature mixer circuit 112, a bandpass filter circuit 113, a variable gain amplifier circuit (VGA) 114, an analog-to-digital converter circuit 115, and a demodulator circuit 116.

[0015] Furthermore, the wireless communication circuit 101 includes a phase shift circuit 117 , a phase-locked loop (PLL) circuit 118 , a phase-locked loop circuit 123 , a frequency divider circuit 127 , and an analog-to-digital conversion controller (ADCC) 128 .

[0016] The antenna 102 receives radio waves wirelessly and outputs the received signal to the low-noise amplifier circuit 111. The received signal is an ASK-modulated or QPSK-modulated signal. The low-noise amplifier circuit 111 amplifies the received signal received by the antenna 102 and outputs the amplified received signal to the quadrature mixer circuit 112.

[0017] Oscillator circuit 103 generates reference clock signal CK1. Reference clock signal CK1 is, for example, 32.768 MHz. Phase-locked loop circuit 118 generates clock signal CK2 based on reference clock signal CK1. The frequency of clock signal CK2 is offset by the intermediate frequency with respect to the frequency of the received signal. For example, when a 5800 MHz channel is selected using quadrature mixer circuit 112 with an intermediate frequency of 3.072 MHz, the frequency of clock signal CK2 is 5803.072 MHz or 5796.928 GHz. In this way, a decimal division (fractional division) phase-locked loop circuit 118 is used to generate clock signal CK2 whose frequency is not an integer ratio to the frequency of reference clock signal CK1.

[0018] The phase-locked loop circuit 118 includes a phase detection circuit (phase comparison circuit) 119, a voltage-controlled oscillator (VCO) 120, a frequency divider circuit 121, and a delta-sigma modulation circuit 122. The phase detection circuit 119 detects the phase difference between a reference clock signal CK1 and a clock signal CK5 and outputs a voltage based on the phase difference to the voltage-controlled oscillator circuit 120. The voltage-controlled oscillator circuit 120 generates a clock signal CK2 having a frequency based on the voltage. The delta-sigma modulation circuit 122 controls the frequency divider circuit 121 based on the clock signal CK5. The frequency divider circuit 121, under the control of the delta-sigma modulation circuit 122, outputs a clock signal CK5, which is a fractional division of the clock signal CK2, to the phase detection circuit 119. The frequency ratio between the clock signals CK2 and CK5 is a decimal (fractional). Therefore, the frequency ratio between the clock signals CK1 and CK2 is also a decimal (fractional). The phase-locked loop circuit 118 performs feedback control so that the phase difference between the clock signals CK1 and CK5 approaches zero, and generates the clock signal CK2.

[0019] The phase shift circuit 117 shifts the phase of the clock signal CK2 to output a 0° clock signal and a 90° clock signal to the quadrature mixer circuit 112. The 0° clock signal and the 90° clock signal have a phase difference of 90° from each other.

[0020] The quadrature mixer circuit 112 mixes (multiplies) the received signal output by the low-noise amplifier circuit 111 with the 0° clock signal, and mixes (multiplies) the received signal output by the low-noise amplifier circuit 111 with the 90° clock signal.The quadrature mixer circuit 112 then outputs an I signal (in-phase signal) obtained by mixing the received signal with the 0° clock signal, and a Q signal (quadrature signal) obtained by mixing the received signal with the 90° clock signal.

[0021] The bandpass filter circuit 113 removes unnecessary frequency components from the I and Q signals output by the quadrature mixer circuit 112, and outputs the I and Q signals after the removal of the unnecessary frequency components. The variable gain amplifier circuit 114 amplifies the I and Q signals output by the bandpass filter circuit 113, and outputs the amplified I and Q signals to the analog-to-digital converter circuit 115.

[0022] For example, if the intermediate frequency is 3.072 MHz and the dedicated frequency bandwidth for short-range communication is 4.4 MHz, the analog-to-digital conversion circuit 115 will convert a signal with a maximum frequency of 3.072 MHz + 4.4 MHz / 2 = 5.272 MHz. Therefore, if the sample rate of the analog-to-digital conversion circuit 115 is set to 32.768 MHz, for example, conversion can be performed at a sample rate that is sufficiently high for the signal frequency.

[0023] For example, in CMOS technology nodes with gate lengths of 90 nanometers or greater, it is reasonable to employ a successive approximation analog-to-digital conversion circuit as the analog-to-digital conversion circuit 115. When performing analog-to-digital conversion of a single point on an analog signal, the successive approximation analog-to-digital conversion circuit 115 first samples the charge corresponding to the analog signal voltage and then performs a binary search to obtain, for example, a 12-bit digital value. In other words, the successive approximation analog-to-digital conversion circuit 115 requires a clock signal CK3 with a frequency, for example, 20 times the sample rate. Therefore, the phase-locked loop circuit 123 generates the clock signal CK3 by multiplying the reference clock CK1 by 20. For example, the frequency of the reference clock signal CK1 is 32.768 MHz, and the frequency of the clock signal CK3 is 655.36 MHz. In this way, an integer-dividing phase-locked loop circuit 123 is used to generate the clock signal CK3 with a frequency that is an integer ratio (20 times) of the frequency of the reference clock signal CK1.

[0024] The phase-locked loop circuit 123 includes a phase detection circuit 124, a voltage-controlled oscillation circuit 125, and a frequency divider circuit 126. The phase detection circuit 124 detects the phase difference between the reference clock signal CK1 and the clock signal CK6, and outputs a voltage based on the phase difference to the voltage-controlled oscillation circuit 125. The voltage-controlled oscillation circuit 125 generates a clock signal CK3 having a frequency based on the voltage. The frequency divider circuit 126 divides the frequency of the clock signal CK3 by 20 and outputs the resulting clock signal CK6 to the phase detection circuit 124. The frequency ratio between the clock signals CK3 and CK6 is 20 times. Therefore, the frequency ratio between the clock signals CK1 and CK3 is also 20 times. The phase-locked loop circuit 123 performs feedback control so that the phase difference between the clock signals CK1 and CK6 approaches 0, and generates the clock signal CK3.

[0025] The frequency divider circuit 127 divides the frequency of the clock signal CK3 by 20 to generate a clock signal CK4, which is output to the demodulation circuit 116. For example, the frequency of the clock signal CK3 is 655.36 MHz. The frequency of the clock signal CK4 is 1 / 20 the frequency of the clock signal CK3, for example, 32.768 MHz. Furthermore, the frequency divider circuit 127 repeatedly counts a count value from 0 to 19 based on the clock signal CK3, and outputs the count value to the ADCC 128.

[0026] The ADCC 128 is an analog-to-digital conversion controller that outputs a conversion trigger signal STC to the analog-to-digital conversion circuit 115 based on the clock signal CK3 and the count value of the frequency divider circuit 127. The conversion trigger signal STC is a signal that indicates a sampling period and a conversion period for analog-to-digital conversion.

[0027] Based on the clock signal CK3 and the conversion trigger signal STC, the analog-to-digital converter 115 converts the analog signal output by the variable gain amplifier circuit 114 into a digital signal. Specifically, the analog-to-digital converter 115 converts the analog I and Q signals output by the variable gain amplifier circuit 114 into digital I and Q signals.

[0028] Based on the clock signal CK4, the demodulation circuit 116 performs ASK demodulation processing or QPSK demodulation processing on the digital I and Q signals output by the analog-digital conversion circuit 115 to restore the data. The demodulation circuit 116 must operate in synchronization with the analog-digital conversion circuit 115, and therefore receives as input a clock signal CK4 generated by dividing the clock signal CK3 of the analog-digital conversion circuit 115 by, for example, 20. The analog-digital conversion circuit 115 and the demodulation circuit 116 operate according to logic that starts from the edge of the clock signal CK3, and therefore a synchronous relationship between the analog-digital conversion circuit 115 and the demodulation circuit 116 is maintained.

[0029] 2 is a timing chart showing an example of clock signal CK3, conversion trigger signal STC, the internal state of analog-to-digital conversion circuit 115, output data D[11:0] of analog-to-digital conversion circuit 115, and clock signal CK4. The period of conversion trigger signal STC is 20 times the period of clock signal CK3. The period of clock signal CK4 is the same as the period of conversion trigger signal STC and is 20 times the period of clock signal CK3.

[0030] The high-level period of the conversion trigger signal STC indicates the sampling period, and the low-level period indicates the conversion period. The analog-to-digital conversion circuit 115 receives the clock signal CK3 and the conversion trigger signal STC. When the conversion trigger signal STC is asserted, the analog-to-digital conversion circuit 115 starts sampling the analog signal in cycle 0 at the rising edge of the next clock signal CK3 (cycle 0 in the diagram). Next, when the conversion trigger signal STC is negated, the analog-to-digital conversion circuit 115 ends sampling the analog signal in cycle 0 at the rising edge of the next clock signal CK3 (cycle 4 in the diagram) and starts a binary search for analog-to-digital conversion. The binary search is determined bit by bit from the most significant bit of the 12-bit binary code D11 to D0.

[0031] The internal state in Figure 2 shows that the 12-bit binary code is judged sequentially from D11 to D0, which includes the states of D5R and D2R. D5R and D2R each indicate a redundant judgment, a process for remedying any judgment errors that have occurred up to that point. A typical cause of a judgment error is a settling failure of the analog-to-digital conversion circuit 115 caused by parasitic inductance in the package of the wireless communication circuit 101. When the analog-to-digital conversion circuit 115 completes the binary search in cycle 20, it updates the output data D[11:0] of the analog-to-digital conversion circuit 115 at the rising edge of the next clock signal CK3.

[0032] The clock signal CK4 is a clock signal obtained by dividing the clock signal CK3 by 20 using the frequency divider circuit 127, and is supplied to the demodulator circuit 116. The demodulator circuit 116 is driven by the rising edge of the clock signal CK4. The conversion trigger signal STC and the clock signal CK4 have the same period, but the number of cycles in their high-level and low-level periods differ. Therefore, the ADCC 128 generates the conversion trigger signal STC based on the count value of the 20-counter inside the frequency divider circuit 127. The wiring between the ADCC 128 and the frequency divider circuit 127 indicates that the ADCC 128 references the count value of the frequency divider circuit 127.

[0033] 3 is a diagram showing the phase relationship between reference clock signal CK1 and clock signal CK4. The frequencies of clock signals CK1 and CK4 are the same, for example, 32.768 MHz. In the case of the wireless communication circuit 101 of FIG. 1, the phase relationship between reference clock signal CK1 and clock signal CK4 is not deterministic. There are 20 possible phases of clock signal CK4, based on reference clock signal CK1.

[0034] The clock signal CK4 is a clock signal obtained by dividing the clock signal CK3 by the frequency divider circuit 127. The clock signal CK3 is a clock signal generated by the phase-locked loop circuit 123 based on the reference clock signal CK1. Therefore, the phase of the clock signal CK4 relative to the reference clock signal CK1 changes each time the wireless communication circuit 101 is started, depending on initial conditions such as the timing at which the wireless communication circuit 101 is reset and device noise. Because the clock signal CK4 and the internal state of the analog-digital conversion circuit 115 are synchronized, there are 20 possible phase relationships between the reference clock signal CK1 and the operations of the analog-digital conversion circuit 115 and the demodulation circuit 116. Therefore, the receiving sensitivity of the wireless communication circuit 101 changes for each of the 20 possible phase relationships.

[0035] Therefore, for example, if defective products are to be screened out before shipping in order to guarantee performance in the field, the wireless communication circuit 101 must be tested for 20 different phase relationships, which increases the shipping test cost.

[0036] Fig. 4 is a diagram showing an example configuration of a wireless communication circuit 101 according to a second comparative example for solving the problem of the uncertain phase relationship between clock signals CK1 and CK4. The wireless communication circuit 101 in Fig. 4 is obtained by removing the frequency divider circuit 127 from the wireless communication circuit 101 in Fig. 1. Below, differences between the wireless communication circuit 101 in Fig. 4 and the wireless communication circuit 101 in Fig. 1 will be described.

[0037] The frequency divider circuit 126 divides the frequency of the clock signal CK3 by 20 to generate a clock signal CK4, which is output to the phase detector circuit 124 and the demodulator circuit 116. For example, the frequency of the clock signal CK3 is 655.36 MHz, and the frequency of the clock signal CK4 is 32.768 MHz. The phase detector circuit 124 outputs a voltage indicating the phase difference between the clock signals CK1 and CK4 to the voltage-controlled oscillator circuit 125. The phase-locked loop circuit 123 performs feedback to bring the phase difference between the clock signals CK1 and CK4 closer to zero, so that in a steady state, the phases of the clock signals CK1 and CK4 match.

[0038] Furthermore, the frequency divider circuit 126 repeatedly counts a count value between 0 and 19 based on the clock signal CK3 and outputs the count value to the ADCC 128. The ADCC 128 outputs a conversion trigger signal STC to the analog-to-digital converter circuit 115 based on the clock signal CK3 and the count value of the frequency divider circuit 126. This synchronizes the sampling of the analog-to-digital converter circuit 115 and the processing of the demodulator circuit 116. The relationship between the clock signal CK4 and the conversion trigger signal STC is the same as in FIG. 2.

[0039] The phase-locked loop circuit 123 controls the phase difference between the clock signals CK1 and CK4 to approach 0, so the phase relationship between the clock signals CK1 and CK4 is always the same. Therefore, the wireless communication circuit 101 in Fig. 4 can solve the problem of the uncertain phase relationship between the clock signals CK1 and CK4 in the wireless communication circuit 101 in Fig. 1.

[0040] A decimal division type phase-locked loop circuit 118 is used to tune to receive channel frequencies spaced at 5 MHz intervals, for example. A decimal division type (fractional division type) phase-locked loop circuit 118 requires a delta-sigma modulation circuit 122 and has a relatively large logic scale. The delta-sigma modulation circuit 122 is driven by the feedback clock signal CK5 input to the phase detection circuit 119, and as a result, it operates in synchronization with the 32.768 MHz of the reference clock signal CK1.

[0041] That is, the delta-sigma modulation circuit 122, the analog-to-digital conversion circuit 115, and the demodulation circuit 116 are driven by the rising edge of the reference clock signal CK1, which has a frequency of, for example, 32.768 MHz.

[0042] The delta-sigma modulation circuit 122, analog-to-digital conversion circuit 115, and demodulation circuit 116, which operate in synchronization with the 32.768 MHz reference clock signal CK1, emit harmonics that are integer multiples of 32.768 MHz. Therefore, for example, in short-range communication, the delta-sigma modulation circuit 122, analog-to-digital conversion circuit 115, and demodulation circuit 116 generate harmonic noise around 32.768 MHz × 177 = 5799.936 GHz, which is injected into the receiving section (e.g., quadrature mixer circuit 112) of the wireless communication circuit 101 and degrades the receiving sensitivity of the 5800 MHz channel of the wireless communication circuit 101.

[0043] The amount of charge that demodulation circuit 116 draws from the power supply during the period of 32.768 MHz clock signal CK4 changes from moment to moment depending on the processing content and can be considered noise. The amount of charge that delta-sigma modulation circuit 122 draws from the power supply during the period of 32.768 MHz clock signal CK5 is different each time depending on the internal state of delta-sigma modulation circuit 122, so it is not periodic and should be considered noise.

[0044] When sampling, the analog-to-digital conversion circuit 115 subtracts charge from the preceding variable gain amplifier circuit 114. The amount of charge subtracted at this time depends on the amount of charge sampled immediately before and the voltage currently being converted, and can therefore be considered noise.

[0045] High-frequency components of noise generated by the delta-sigma modulation circuit 122, analog-to-digital conversion circuit 115, and demodulation circuit 116, which are synchronized with the reference clock signal CK1, travel through various paths to become noise in the receiving section of the wireless communication circuit 101. There are various paths through which this noise can travel to the receiving section of the wireless communication circuit 101, including via power supply wiring, via a signal path, via spatial coupling, and via a silicon substrate. However, in the case of an SoC in which all components of the wireless communication circuit 101 are integrated on a single silicon die, there is a limit to how much coupling between the above three clock synchronization circuits and the receiving section of the wireless communication circuit 101 can be reduced, which becomes a major factor in degrading the receiving sensitivity of the wireless communication circuit 101. An embodiment for solving this problem will be described below.

[0046] 5 is a diagram showing an example of the configuration of a semiconductor integrated circuit 500 according to this embodiment. The semiconductor integrated circuit 500 includes a wireless communication circuit 101, an antenna 102, an oscillator circuit 103, and a processing circuit 505. The processing circuit 505 is, for example, a microcontroller, a DSP (Digital Signal Processor), or a central processing unit (CPU).

[0047] With the miniaturization of silicon CMOS processes, wireless communication circuits 101 can be integrated onto a single silicon die. The scope of application also extends to short-range communications. For example, a semiconductor integrated circuit 500 for short-range communications includes a 5.8 GHz band quadrature mixer circuit 112, a demodulation circuit 116, a processing circuit (microcontroller) 505 that controls the system, and a flash memory, and is realized in the form of an SoC.

[0048] 5 is obtained by removing the frequency divider circuit 126 from the wireless communication circuit 101 in FIG. 4 and adding a frequency divider and delay circuit 502, a nonvolatile memory 503, and a frequency divider circuit 504.

[0049] The wireless communication circuit 101 is connected to an antenna 102, an oscillator circuit 103, and a processing circuit 505. The wireless communication circuit 101 includes a low-noise amplifier circuit 111, a quadrature mixer circuit 112, a band-pass filter circuit 113, a variable gain amplifier circuit 114, a phase shift circuit 117, a phase-locked loop circuit 118, and a processing circuit 501. The processing circuit 501 includes an analog-to-digital converter circuit 115, a demodulator circuit 116, a phase-locked loop circuit 123, an ADCC 128, a frequency division and delay circuit 502, and a non-volatile memory 503.

[0050] The antenna 102, low-noise amplifier circuit 111, quadrature mixer circuit 112, band-pass filter circuit 113, variable gain amplifier circuit 114, analog-to-digital conversion circuit 115, and demodulation circuit 116 are the same as those in Figures 1 and 4. The phase shift circuit 117 and phase-locked loop circuit 118 are also the same as those in Figures 1 and 4.

[0051] The nonvolatile memory 503 stores a phase shift setting value (phase shift setting signal) PSHIFT and a division ratio (frequency setting signal) N. The phase shift setting value PSHIFT and the division ratio N can store different values ​​for each manufactured individual wireless communication circuit 101. The nonvolatile memory 503 outputs the phase shift setting value (phase shift setting signal) PSHIFT to the frequency division and delay circuit 502, and outputs the division ratio (frequency setting signal) N to the frequency divider circuit 504. The phase shift setting value PSHIFT is a setting value that indicates the phase difference between the reference clock signal CK1 and the clock signal CK4. The division ratio N is the division ratio of the frequency divider circuit 504. The division ratio N is the frequency ratio of the clock signal CK3 to the clock signal CK6, i.e., the frequency ratio of the clock signal CK3 to the reference clock signal CK1.

[0052] The phase-locked loop circuit 123 includes a phase detection circuit 124, a voltage-controlled oscillation circuit 125, and a frequency divider circuit 504. The phase-locked loop circuit 123 is a clock generation circuit that generates a clock signal CK3 having a higher frequency than the reference clock signal CK1 based on a reference clock signal CK1 and a frequency division ratio N.

[0053] The phase detection circuit 124 detects the phase difference between the reference clock signal CK1 and the clock signal CK6 and outputs a voltage based on the phase difference to the voltage-controlled oscillator circuit 125. The voltage-controlled oscillator circuit 125 generates a clock signal CK3 having a frequency based on the detected voltage. The frequency divider circuit 504 divides the clock signal CK3 by N based on the division ratio N stored in the nonvolatile memory 503, and outputs the resulting clock signal CK6 to the phase detection circuit 124. For example, if the division ratio N is 20, the frequency divider circuit 504 divides the clock signal CK3 by 20 to generate the clock signal CK6. The frequency ratio of the clock signal CK3 to the clock signal CK6 is N times. Therefore, the frequency ratio of the clock signal CK3 to the reference clock signal CK1 is also N times. The phase-locked loop circuit 123 performs feedback control so that the phase difference between the clock signals CK1 and CK6 approaches zero, thereby generating the clock signal CK3. In a steady state, the phases of the clock signals CK1 and CK6 are identical to each other.

[0054] For example, the frequencies of the reference clock signal CK1 and the clock signal CK6 are 32.768 MHz. When the division ratio N is 20, the frequency of the clock signal CK3 is 655.36 MHz. The division ratio N is a frequency setting value for setting the frequency of the clock signal CK3.

[0055] Furthermore, the frequency divider circuit 504 repeatedly counts a count value CNT from 0 to N-1 based on the clock signal CK3, and outputs the count value CNT to the ADCC 128 and the frequency divider and delay circuit 502.

[0056] 6, the frequency division and delay circuit 502 divides the frequency of the clock signal CK3 by N and delays it based on the phase shift setting value PSHIFT and frequency division ratio N stored in the nonvolatile memory 503 and the count value CNT of the frequency division circuit 504, thereby generating a clock signal CK4 having a lower frequency than the clock signal CK3 so as to have a phase difference with the reference clock signal CK1. The count value CNT of the frequency division circuit 504 is a count value between 0 and N-1 based on the frequency division ratio N.

[0057] For example, the frequency of the reference clock signal CK1 is 32.768 MHz. When the division ratio N is 20, the frequency of the clock signal CK3 is 655.36 MHz. The frequency of the clock signal CK4 is the same as the frequency of the reference clock signal CK1, 32.768 MHz.

[0058] The phase shift setting value PSHIFT is a value from 0 to N-1. When the frequency division ratio N is 20, the phase shift setting value PSHIFT is a value from 0 to 19. The phase difference of the clock signal CK4 with respect to the clock signal CK1 varies depending on the phase shift setting value PSHIFT.

[0059] When the phase shift setting value PSHIFT is 0, the phase difference of the clock signal CK4 with respect to the clock signal CK1 is 0. When the phase shift setting value PSHIFT is 1, the phase difference of the clock signal CK4 with respect to the clock signal CK1 is one cycle of the clock signal CK3. When the phase shift setting value PSHIFT is 2, the phase difference of the clock signal CK4 with respect to the clock signal CK1 is two cycles of the clock signal CK3. As described above, the clock signal CK4 is phase-shifted with respect to the clock signal CK1 by the number of cycles of the clock signal CK3 according to the phase shift setting value PSHIFT.

[0060] The ADCC 128 is an analog-to-digital conversion controller (control circuit), and generates a conversion trigger signal STC based on the count value CNT of the frequency divider circuit 504, the phase shift setting value PSHIFT, and the clock signal CK3, so that the conversion trigger signal STC has the same period as the clock signal CK4 and the same phase as the clock signal CK4, as shown in FIG. 8.

[0061] The conversion trigger signal STC has the same period as the clock signal CK4. Furthermore, the conversion trigger signal STC has the same phase as the clock signal CK4 based on the phase shift setting value PSHIFT. For example, as in FIG. 6, when the phase shift setting value PSHIFT is 0, the conversion trigger signal STC has a phase difference of 0 with respect to the clock signal CK1. When the phase shift setting value PSHIFT is 1, the conversion trigger signal STC has a phase difference of 1 cycle of the clock signal CK3 with respect to the clock signal CK1. When the phase shift setting value PSHIFT is 2, the conversion trigger signal STC has a phase difference of 2 cycles of the clock signal CK3 with respect to the clock signal CK1. The conversion trigger signal STC does not have to have the same phase as the clock signal CK4, and may have a constant phase difference.

[0062] The ADCC 128 outputs a conversion trigger signal STC to the analog-to-digital conversion circuit 115. As shown in Fig. 2, the conversion trigger signal STC is a signal that indicates a sampling period and a conversion period for analog-to-digital conversion. A high-level period of the conversion trigger signal STC indicates a sampling period, and a low-level period indicates a conversion period.

[0063] The analog-to-digital conversion circuit 115 converts the analog I and Q signals into digital I and Q signals based on the clock signal CK3 and the conversion trigger signal STC. Specifically, the analog-to-digital conversion circuit 115 samples the analog signal during the sampling period indicated by the conversion trigger signal STC, and performs a binary search for analog-to-digital conversion during the conversion period indicated by the conversion trigger signal STC.

[0064] The demodulation circuit 116 is a digital signal processing circuit, and executes processing according to the digital signal output by the analog-digital conversion circuit 115, based on the clock signal CK4. Specifically, the demodulation circuit 116 performs ASK demodulation processing or QPSK demodulation processing on the digital I signal and Q signal output by the analog-digital conversion circuit 115, based on the clock signal CK4, to restore data. The demodulation circuit 116 then outputs the restored data to the processing circuit 505 as an output signal of the wireless communication circuit 101. The processing circuit 505 performs various processes on the output signal of the demodulation circuit 116.

[0065] As described above, the delta-sigma modulation circuit 122 is driven by the rising edge of the reference clock signal CK1. On the other hand, as described above, the analog-to-digital conversion circuit 115 is driven by the rising edge of the conversion trigger signal STC. The demodulation circuit 116 is driven in synchronization with the clock signal CK4.

[0066] The frequency divider and delay circuit 502 generates a clock signal CK4 having a phase difference with respect to the reference clock signal CK1 based on the phase shift setting value PSHIFT. The ADCC 128 generates a conversion trigger signal STC having a phase difference with respect to the reference clock signal CK1 based on the phase shift setting value PSHIFT. The phase difference between the reference clock signal CK1 and the conversion trigger signal STC is the same as the phase difference between the reference clock signal CK1 and the clock signal CK4.

[0067] Therefore, the clock signal CK4 and the conversion trigger signal STC can be made to have different phases with respect to the reference clock signal CK1. This allows the drive timing of the analog-to-digital conversion circuit 115 and the demodulation circuit 116 to differ from the drive timing of the delta-sigma modulation circuit 122. The wireless communication circuit 101 can reduce noise and suppress deterioration of reception sensitivity.

[0068] The wireless communication circuit 101 can arbitrarily set the relationship between the drive phase of the delta-sigma modulation circuit 122 synchronized with the reference clock signal CK1 and the drive phases of the analog-to-digital conversion circuit 115 and the demodulation circuit 116 synchronized with the clock signal CK4, depending on the phase shift setting value PSHIFT.

[0069] The phase difference between the clock signal CK4 and the reference clock signal CK1 may be different from the phase difference between the conversion trigger signal STC and the reference clock signal CK1.

[0070] 7 is a diagram showing an example of the configuration of the frequency divider circuit 504, frequency division and delay circuit 502, and ADCC 128 of FIG. 5. The frequency divider circuit 504 has a selector 701, a register 702, a subtractor 703, a selector 704, and a register 705. The frequency divider and delay circuit 502 has an adder 706, a remainder calculator 707, a selector 708, and a register 709. The ADCC 128 has the adder 706, a remainder calculator 707, a selector 710, and a register 711. The frequency divider and delay circuit 502 and the ADCC 128 share the adder 706 and the remainder calculator 707.

[0071] FIG. 8 is a timing chart showing an example of the operation of the frequency divider circuit 504, the frequency division and delay circuit 502, and the ADCC 128 in FIG.

[0072] Selector 701, register 702, and subtractor 703 constitute a counter that counts a count value CNT. In the initial state, selector 701 outputs N-1 to register 702 as count value CNT1. When division ratio N is 20, selector 701 outputs count value CNT1 of 19. When a rising edge of clock signal CK3 is input, register 702 holds N-1 input from selector 701 and outputs the held N-1 as count value CNT.

[0073] The subtractor 703 subtracts 1 from the count value CNT and outputs the result to the selector 701. If the count value CNT is 19, the subtractor 703 outputs 18. Because the count value CNT is not 0, the selector 701 outputs 18 output by the subtractor 703 to the register 702. When the rising edge of the clock signal CK3 is input to the register 702, the register 702 holds the 18 input from the selector 701 and outputs the held 18 as the count value CNT.

[0074] As described above, when the count value CNT is not 0, the selector 701 outputs the output value of the subtractor 703 to the register 702, and when the count value CNT is 0, the selector 701 outputs N-1 to the register 702. When a rising edge of the clock signal CK3 is input, the register 702 holds the value input from the selector 701 and outputs the held value as the count value CNT. As a result, each time a rising edge of the clock signal CK3 is input to the register 702, the count value CNT is decremented, and is repeated in the order of 19, 18, 17, . . ., 0, 19, 18, . . . The counter of the frequency divider circuit 504 is a binary counter that completes one cycle in 20 cycles.

[0075] The selector 704 and register 705 are logic circuits for generating the clock signal CK6. The selector 704 outputs 1 to the register 705 when the count value CNT is equal to or greater than N / 2, and outputs 0 to the register 705 when the count value CNT is less than N / 2. When a rising edge of the clock signal CK3 is input, the register 705 holds the output value of the selector 704 and outputs the held output value as the clock signal CK6. The clock signal CK6 is the clock signal CK3 divided by N.

[0076] If N / 2 is not an integer, the selector 704 may output 1 or 0 depending on whether the count value CNT is equal to or greater than an integer obtained by rounding off, rounding down, or rounding up the decimal point of N / 2. The selector 704 may also output 1 or 0 depending on whether the count value CNT is equal to or greater than a fixed value (for example, 10).

[0077] The adder 706 outputs a value CNT+PSHIFT obtained by adding the count value CNT and the phase shift setting value PSHIFT. The phase shift setting value PSHIFT is, for example, 2. The remainder calculator 707 outputs the remainder obtained when the output value CNT+PSHIFT of the adder 706 is divided by the division ratio N as shown in the following equation, as the count value CNT2. Here, % indicates a remainder calculation. CNT2=(CNT+PSHIFT)%N

[0078] A selector 708 and a register 709 generate a clock signal CK4 based on the count value CNT2. If the count value CNT2 is equal to or greater than N / 2, the selector 708 outputs a 1 to the register 709. If the count value CNT2 is less than N / 2, the selector 708 outputs a 0 to the register 709. When a rising edge of the clock signal CK3 is input, the register 709 holds the output value of the selector 708 and outputs the held output value as the clock signal CK4. The clock signal CK4 is obtained by shifting the phase of the clock signal CK6 by a phase shift setting value PSHIFT and has the same period as the clock signal CK6. The phase-locked loop circuit 123 performs feedback to bring the phase difference between the clock signals CK1 and CK6 closer to 0. In a steady state, the phases of the clock signals CK1 and CK6 are the same, so the clock signal CK4 is obtained by shifting the phase of the clock signal CK1 by a phase shift setting value PSHIFT.

[0079] That is, the adder 706 and the remainder calculator 707 function as a phase shift setting circuit that sets the phase difference between the clock signals CK6 and CK4, i.e., the phase difference between the clock signals CK1 and CK4, based on the phase shift setting value PSHIFT.

[0080] If N / 2 is not an integer, the selector 708 may output 1 or 0 depending on whether the count value CNT2 is equal to or greater than an integer obtained by rounding off, rounding down, or rounding up the decimal point of N / 2. The selector 708 may also output 1 or 0 depending on whether the count value CNT2 is equal to or greater than a fixed value (for example, 10).

[0081] The selector 710 and register 711 generate a conversion trigger signal STC based on the count value CNT2. If the count value CNT2 is 16 or greater, the selector 710 outputs 1 to the register 711, and if the count value CNT2 is less than 16, the selector 710 outputs 0 to the register 711. When a rising edge of the clock signal CK3 is input, the register 711 holds the output value of the selector 710 and outputs the held output value as the conversion trigger signal STC. The phase of the conversion trigger signal STC is the same as that of the clock signal CK4, and is obtained by shifting the phase of the clock signal CK6 by the phase shift setting value PSHIFT. The period of the conversion trigger signal STC is the same as that of the clock signals CK6 and CK4. The phase-locked loop circuit 123 performs feedback to bring the phase difference between the clock signals CK1 and CK6 closer to 0, and in the steady state, the phases of the clock signals CK1 and CK6 match each other, so the conversion trigger signal STC is a signal in which the phase of the clock signal CK1 is shifted by the phase shift setting value PSHIFT.

[0082] That is, the adder 706 and the remainder calculator 707 function as a phase shift setting circuit that sets the phase difference between the clock signal CK6 and the conversion trigger signal STC, i.e., the phase difference between the clock signal CK1 and the conversion trigger signal STC, based on the phase shift setting value PSHIFT.

[0083] 7, the adder 706 and the remainder calculator 707 are shared by the frequency division and delay circuit 502 and the ADCC 128, so the phase of the conversion trigger signal STC is the same as the phase of the clock signal CK4, but this is not limited to this. For example, by providing circuit blocks for the adder 706 and the remainder calculator 707 separately for the frequency division and delay circuit 502 and the ADCC 128 and configuring the adder 706 of at least one of the circuit blocks to further add a constant offset value to the phase shift setting value PSHIFT, the phase of the conversion trigger signal STC and the phase of the clock signal CK4 can be made different.

[0084] 9(A) and (B) are timing charts showing examples of clock signals CK1, CK4, currents IDD1, IDD4, and currents IDD1+IDD4. Current IDD1 represents the current flowing through the delta-sigma modulation circuit 122 driven by the phase of clock signal CK1. Current IDD4 represents the current flowing through the analog-to-digital conversion circuit 115 and demodulation circuit 116 driven by the phase of clock signal CK4. Current IDD1+IDD4 represents the sum of current IDD1 and current IDD4. Current waveforms of currents IDD1 and IDD4 are approximated by sawtooth waves. For simplicity, the amplitudes of current IDD1 and current IDD4 are assumed to be equal to each other.

[0085] 9A is a timing chart for when the phase of clock signal CK4 relative to reference clock signal CK1 is 0°, and is a timing chart for the wireless communication circuit 101 according to the second comparative example of FIG. 4. The phase difference between reference clock signal CK1 and clock signal CK4 is 0°.

[0086] Fig. 9(B) is a timing chart when the phase of the clock signal CK4 relative to the reference clock signal CK1 is 180°, and is a timing chart for the wireless communication circuit 101 according to the present embodiment shown in Fig. 5. The phase difference between the reference clock signal CK1 and the clock signal CK4 can be set by the phase shift setting value PSHIFT and is 180°.

[0087] The current IDD1+IDD4 in Figure 9(B) has half the amplitude and half the period of the current IDD1+IDD4 in Figure 9(A). When the reference clock signal CK1 and the clock signal CK4 are 32.768 MHz, the 177th harmonic of 32.768 MHz approximately matches the 5800 MHz channel for short-range communications.

[0088] Therefore, in the wireless communication circuit 101 of FIG. 4 corresponding to FIG. 9(A), when harmonics are injected into the receiving section (for example, quadrature mixer circuit 112), noise occurs, degrading the receiving sensitivity. Since the amplitude of the nth harmonic of a sawtooth wave is 1 / n, if the amplitude of the 1st harmonic is 1, the amplitude of the 177th harmonic is 1 / 177. The receiving section of the wireless communication circuit 101 is a circuit that processes a weak signal input from the antenna 102, and is therefore sensitive to even slight noise injection. Therefore, the receiving sensitivity of the wireless communication circuit 101 of FIG. 4 corresponding to FIG. 9(A) is degraded.

[0089] In the wireless communication circuit 101 of Figure 5 corresponding to Figure 9(B), it is assumed that the amplitudes of current IDD1 and current IDD4 are equal to each other. In this case, the current waveform of current IDD1 + IDD4 becomes a sawtooth wave of 32.768 MHz × 2 = 65.536 MHz, and the nth harmonic does not collide with the 5800 MHz channel. Therefore, the wireless communication circuit 101 of Figure 5 corresponding to Figure 9(B) does not suffer from degradation in reception sensitivity.

[0090] 9A and 9B are explained using the simplified model as described above. In reality, the currents IDD1 and IDD4 are not sawtooth waves but are more complex. The amplitudes of the currents IDD1 and IDD4 are not the same. Therefore, the wireless communication circuit 101 of FIG. 5 does not necessarily completely eliminate the effects of harmonic noise, for example, at 5800 MHz. However, the wireless communication circuit 101 of FIG. 5 can mitigate the sensitivity degradation caused by the synchronization circuits for the reference clock signal CK1 and the clock signal CK4 by adjusting the phase shift setting value PSHIFT and setting an optimal phase shift setting value PSHIFT.

[0091] As described above, the wireless communication circuit 101 of FIG. 5 can control harmonic noise and suppress deterioration of receiving sensitivity by driving the delta-sigma modulation circuit 122, the analog-to-digital conversion circuit 115, and the demodulation circuit 116 at different phases.

[0092] Figures 10(A) and (B) are timing charts showing an example of the operation of the wireless communication circuit 101 of Figure 5. Figures 10(A) and (B) are timing charts showing an example of the clock signal CK3, the conversion trigger signal STC, the internal state of the analog-to-digital conversion circuit 115, and the current IDD10 or IDD11.

[0093] 10A is a timing chart when the division ratio N is 20. The period of the conversion trigger signal STC is 20 times the period of the clock signal CK3. The high-level period of the conversion trigger signal STC indicates the sampling period Ts1 of the analog-to-digital conversion circuit 115. During the sampling period Ts1, the analog-to-digital conversion circuit 115 acquires the charge of the analog signal.

[0094] The low level period of the conversion trigger signal STC indicates the conversion period Tc1 of the analog-to-digital conversion circuit 115. During the conversion period Tc1, the analog-to-digital conversion circuit 115 searches for a digital value corresponding to the amount of charge of the acquired analog signal.

[0095] The sum of the sampling period Ts1 and the conversion period Tc1 corresponds to 20 cycles of the clock signal CK3. The selector 710 in FIG. 7 outputs 0 when the count value CNT2 is less than 16. Therefore, the conversion period Tc1 corresponds to 16 cycles of the clock signal CK3. Therefore, the sampling period Ts1 corresponds to 4 (=20-16) cycles of the clock signal CK3. The analog-to-digital conversion circuit 115 performs analog-to-digital conversion at a sampling rate of 20 cycles (32.768 MHz).

[0096] The current IDD10 is a current that flows through the analog-to-digital conversion circuit 115 when the division ratio N is 20. The current IDD10 has a peak at the start of the sampling period Ts1 and a peak at the start of the conversion period Tc1. At the start of the sampling period Ts1, the analog-to-digital conversion circuit 115 initializes its internal circuitry and acquires the charge of the analog signal, so the current IDD10 has a peak. Furthermore, at the start of the conversion period Tc1, the analog-to-digital conversion circuit 115 switches the capacitance element corresponding to the most significant bit, so the current IDD10 has a peak. As a result, the current IDD10 has two peaks.

[0097] 10B is a timing chart when the division ratio N is 30. The period of the conversion trigger signal STC is 30 times the period of the clock signal CK3. The high-level period of the conversion trigger signal STC indicates the sampling period Ts2 of the analog-digital conversion circuit 115. During the sampling period Ts2, the analog-digital conversion circuit 115 acquires the charge of the analog signal.

[0098] The low level period of the conversion trigger signal STC indicates the conversion period Tc2 of the analog-to-digital conversion circuit 115. During the conversion period Tc2, the analog-to-digital conversion circuit 115 searches for a digital value corresponding to the amount of charge of the acquired analog signal.

[0099] The sum of the sampling period Ts2 and the conversion period Tc2 corresponds to 30 cycles of the clock signal CK3. The selector 710 in FIG. 7 outputs 0 when the count value CNT2 is less than 16. Therefore, the conversion period Tc2 corresponds to 16 cycles of the clock signal CK3. Therefore, the sampling period Ts2 corresponds to 14 (=30-16) cycles of the clock signal CK3. The analog-to-digital conversion circuit 115 performs analog-to-digital conversion at a sampling rate of 30 cycles (32.768 MHz).

[0100] The current IDD11 is a current that flows through the analog-to-digital conversion circuit 115 when the division ratio N is 30. Like the current IDD10, the current IDD11 has a peak at the start of the sampling period Ts2 and a peak at the start of the conversion period Tc2.

[0101] The period of the conversion trigger signal STC in Fig. 10(B) is the same as the period of the conversion trigger signal STC in Fig. 10(A). The period of the clock signal CK3 in Fig. 10(B) is 20 / 30 times the period of the clock signal CK3 in Fig. 10(A).

[0102] The conversion periods Tc1 and Tc2 are constant at 16 cycles regardless of the division ratio N. The frequency of the clock signal CK3 changes depending on the division ratio. The frequencies of the clock signal CK4 and the conversion trigger signal STC are constant regardless of the division ratio N.

[0103] In the successive approximation type analog-to-digital converter 115, it is reasonable to set the number of cycles in the conversion periods Tc1 and Tc2 to a fixed value (for example, 16 cycles) regardless of the division ratio N. The reason for this is that the conversion periods Tc1 and Tc2 require the highest logical speed, so the logic needs to be simple. Therefore, the conversion periods Tc1 and Tc2 are set to a simple logic with a fixed cycle regardless of the division ratio N.

[0104] 10(A), the sampling period Ts1 is short relative to the conversion period Tc1, and the two peaks of the current IDD10 are close to each other, with a narrow interval between them. As a result, the current IDD10 generates an n-th harmonic of 32.768 MHz. Since the analog-to-digital conversion circuit 115 is located closest to a noise-sensitive receiving unit (e.g., the quadrature mixer circuit 112), noise synchronous with the conversion trigger signal STC can have a significant impact.

[0105] Therefore, as shown in Figure 10(B), the sampling period Ts2 and the conversion period Tc 2By making the number of cycles of the current IDD11 approximately the same and widening the interval between the two peaks of the current IDD11 so that the two peaks are spaced apart from each other, the current IDD11 can reduce the integer multiple harmonics of 32.768 MHz.

[0106] To realize the timing of FIG. 10(B), Zhou Regardless of the ratio N, the frequency of the conversion trigger signal STC is maintained at a constant value of 32.768 MHz, and the ratio between the sampling period Ts2 and the conversion period Tc2 is changed according to the division ratio N. When the division ratio N in FIG. 10(A) is 20, the sampling period Ts1 is 4 cycles and the conversion period Tc1 is 16 cycles. When the division ratio N in FIG. 10(B) is 30, the sampling period Ts 2 is 14 cycles, and the conversion period Tc 2 is 16 cycles.

[0107] 7, the ADCC 128 generates the conversion trigger signal STC by changing the ratio between the sampling period and the conversion period while maintaining the same cycle as that of the clock signal CK4 based on the division ratio N. The ADCC 128 generates the conversion trigger signal STC by changing the number of cycles of the sampling period while fixing the number of cycles of the conversion period, based on the division ratio N, using the cycle (period) of the clock signal CK3 as a reference.

[0108] The wireless communication circuit 101 can change the frequency of the clock signal CK3 for operating the analog-to-digital conversion circuit 115 according to the division ratio N while maintaining the frequencies of the clock signal CK4 and the conversion trigger signal STC at 32.768 MHz.

[0109] The wireless communication circuit 101 can arbitrarily set the division ratio N stored in the nonvolatile memory 503. As shown in Figures 10(A) and 10(B), the conversion trigger signal STC has a fixed low-level period of, for example, 16 cycles and a high-level period of N-16 cycles. This allows the wireless communication circuit 101 to change the sampling period indicated by the high level of the conversion trigger signal STC, thereby reducing integer-multiple harmonic noise in the 32.768 MHz channel.

[0110] The examples in FIGS. 10A and 10B illustrate the effect using a simplified model. In reality, the process is more complicated, as with the phase shift setting value PSHIFT described above. However, the wireless communication circuit 101 can use the phase shift setting value PSHIFT to adjust the phase difference between the reference clock signal CK1 and the clock signal CK4 and the conversion trigger signal STC, and to adjust the ratio of the high-level period (sampling period) to the low-level period (conversion period) of the conversion trigger signal STC. The phase shift setting value PSHIFT can set the phase difference between the reference clock signal CK1 and the clock signal CK4 and the conversion trigger signal STC. The division ratio N can adjust the ratio of the high-level period to the low-level period of the conversion trigger signal STC. This allows the wireless communication circuit 101 to reduce noise and improve reception performance by setting optimal values ​​for the phase shift setting value PSHIFT and the division ratio N after manufacturing.

[0111] The optimum values ​​may change if the transistor characteristics are biased in one direction during the manufacture of the wireless communication circuit 101. In such a case, the optimum values ​​of the phase shift setting value PSHIFT and the frequency division ratio N are calculated for each manufactured wireless communication circuit 101, and the optimum values ​​of the phase shift setting value PSHIFT and the frequency division ratio N are stored in the nonvolatile memory 503. This makes it possible to realize a wireless communication circuit 101 with good characteristics and an improved manufacturing yield.

[0112] According to this embodiment, the wireless communication circuit 101 can suppress deterioration of reception sensitivity by not only reducing noise using the phase shift setting value PSHIFT but also further reducing noise using the frequency division ratio N. Furthermore, it is possible to reduce the cost of testing the function and performance of the wireless communication circuit 101 while reducing the impact of noise caused by the delta-sigma modulation circuit 122, the analog-to-digital conversion circuit 115, and the demodulation circuit 116 on the operation of the reception unit of the wireless communication circuit 101.

[0113] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0114] 101 Wireless communication circuit 102 Antenna 103 Oscillator Circuit 111 Low noise amplifier circuit 112 Quadrature Mixer Circuit 113 Bandpass filter circuit 114 Variable Gain Amplifier Circuit 115 Analog-to-digital conversion circuit 116 Demodulation Circuit 117 Phase Shift Circuit 118 Phase Locked Loop Circuit 119 Phase Detector Circuit 120 Voltage Controlled Oscillator Circuit 121 Frequency divider circuit 122 Delta-Sigma Modulation Circuit 123 Phase Locked Loop Circuit 124 Phase detection circuit 125 Voltage Controlled Oscillator Circuit 126 frequency divider circuit 128 ADCC 500 Semiconductor Integrated Circuits 501 Processing circuit 502 Divider and Delay Circuit 503 Non-volatile memory 504 frequency divider circuit 505 Processing Circuit

Claims

1. a mixer circuit that mixes the received signal with a third clock signal generated based on the reference clock signal; a second clock generation circuit that generates the third clock signal based on the reference clock signal so as to have a higher frequency than the reference clock signal; a processing circuit that receives an analog signal based on the output signal of the mixer circuit, The processing circuitry a first clock generation circuit that generates a first clock signal having a higher frequency than the reference clock signal based on the reference clock signal and a frequency setting signal; a frequency division and delay circuit that divides and delays the first clock signal based on a phase shift setting signal and the frequency setting signal to generate a second clock signal that has a first phase difference with the reference clock signal and the same frequency as the reference clock signal; an analog-to-digital conversion circuit that converts the analog signal into a digital signal based on the first clock signal and a conversion trigger signal that indicates a sampling period and a conversion period; a digital signal processing circuit that executes processing according to the digital signal based on the second clock signal; a control circuit that generates the conversion trigger signal based on the frequency setting signal and the first clock signal so that the conversion trigger signal has the same cycle as the second clock signal; The second clock generation circuit is a decimal division or fractional division phase-locked loop circuit having a delta-sigma modulation circuit that is driven at a phase different from that of at least one of the analog-to-digital conversion circuit and the digital signal processing circuit.

2. 2. The wireless communication circuit according to claim 1, wherein the control circuit generates the conversion trigger signal by changing a ratio between the sampling period and the conversion period based on the frequency setting signal while maintaining the same period as that of the second clock signal.

3. 3. The wireless communication circuit according to claim 1, wherein the control circuit generates the conversion trigger signal so as to have a second phase difference with respect to the reference clock signal, based on the phase shift setting signal.

4. The wireless communication circuit according to claim 3 , wherein the second phase difference is the same as the first phase difference.

5. the frequency division and delay circuit has a first phase shift setting circuit that sets the first phase difference based on the phase shift setting signal; the control circuit has a second phase shift setting circuit that sets the second phase difference based on the phase shift setting signal; 5. The wireless communication circuit according to claim 3, wherein the first and second phase shift setting circuits are provided as circuits shared by the frequency division and delay circuit and the control circuit.

6. the first clock generation circuit is a phase-locked loop circuit having a frequency divider circuit; 6. The wireless communication circuit according to claim 1, wherein the frequency setting signal is a signal indicating a frequency division ratio of the frequency divider circuit.

7. the frequency divider circuit counts a count value based on the first clock signal; the frequency division and delay circuit generates the second clock signal based on the count value; The wireless communication circuit according to claim 6 , wherein the control circuit generates the conversion trigger signal based on the count value.

8. 8. The wireless communication circuit according to claim 1, wherein the first phase difference is 180 degrees.

9. 9. The wireless communication circuit according to claim 1, wherein the number of cycles in the conversion period is constant regardless of the frequency setting signal.

10. the frequency of the first clock signal varies in response to the frequency setting signal; 10. The wireless communication circuit according to claim 1, wherein the frequency of the second clock signal is constant regardless of the frequency setting signal.

11. 11. The wireless communication circuit according to claim 1, wherein the digital signal processing circuit is a demodulation circuit that performs demodulation processing on the digital signal.

12. a mixer circuit that mixes the received signal with a third clock signal generated based on the reference clock signal; a second clock generation circuit that generates the third clock signal based on the reference clock signal so as to have a higher frequency than the reference clock signal; a first processing circuit to which an analog signal based on the output signal of the mixer circuit is input; a second processing circuit that processes an output signal of the first processing circuit; The first processing circuit a first clock generation circuit that generates a first clock signal having a higher frequency than the reference clock signal based on the reference clock signal and a frequency setting signal; a frequency division and delay circuit that divides and delays the first clock signal based on a phase shift setting signal and the frequency setting signal to generate a second clock signal that has a first phase difference with the reference clock signal and the same frequency as the reference clock signal; an analog-to-digital conversion circuit that converts the analog signal into a digital signal based on the first clock signal and a conversion trigger signal that indicates a sampling period and a conversion period; a digital signal processing circuit that executes processing according to the digital signal based on the second clock signal; a control circuit that generates the conversion trigger signal based on the frequency setting signal and the first clock signal so that the conversion trigger signal has the same cycle as the second clock signal; The semiconductor integrated circuit is a decimal division or fractional division phase-locked loop circuit having a delta-sigma modulation circuit that is driven at a phase different from that of at least one of the analog-to-digital conversion circuit and the digital signal processing circuit.

13. a clock generation circuit that generates a first clock signal having a higher frequency than the reference clock signal based on a reference clock signal and a frequency setting signal; a frequency division and delay circuit that divides and delays the first clock signal based on a phase shift setting signal and the frequency setting signal to generate a second clock signal that has a first phase difference with the reference clock signal and the same frequency as the reference clock signal; an analog-to-digital conversion circuit that converts an analog signal into a digital signal based on the first clock signal and a conversion trigger signal that indicates a sampling period and a conversion period; a digital signal processing circuit that executes processing according to the digital signal based on the second clock signal; a control circuit that generates the conversion trigger signal based on the frequency setting signal and the first clock signal so as to have the same period as the second clock signal; a second clock generation circuit that generates a third clock signal based on the reference clock signal so as to have a higher frequency than the reference clock signal, and supplies the third clock signal to an analog signal processing circuit that generates the analog signal; and The second clock generation circuit is a processing circuit having a second control circuit that is driven in a phase different from that of at least one of the analog-to-digital conversion circuit and the digital signal processing circuit.

14. 14. The processing circuit according to claim 13, wherein the control circuit generates the conversion trigger signal by changing a ratio between the sampling period and the conversion period based on the frequency setting signal while maintaining the same period as the second clock signal.

15. 15. The processing circuit according to claim 13, wherein the control circuit generates the conversion trigger signal to have a second phase difference with respect to the reference clock signal based on the phase shift setting signal.

16. the clock generation circuit is a phase-locked loop circuit having a frequency divider circuit, 16. The processing circuit according to claim 13, wherein the frequency setting signal is a signal indicating a frequency division ratio of the frequency divider circuit.

17. The processing circuit according to any one of claims 13 to 16, wherein the first phase difference is 180°.

18. 18. The processing circuit according to claim 13, wherein the number of cycles in the conversion period is constant regardless of the frequency setting signal.

19. the frequency of the first clock signal varies in response to the frequency setting signal; 19. The processing circuit according to claim 13, wherein the frequency of the second clock signal is constant regardless of the frequency setting signal.

20. 20. The processing circuit according to claim 13, wherein the digital signal processing circuit is a demodulation circuit that performs demodulation processing on the digital signal.

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