Integrated circuits and power supply circuits

Abstract

To provide an integrated circuit and a power supply circuit with which it is possible to improve a power factor.SOLUTION: Provided is an integrated circuit including an inductor to which a rectified voltage corresponding to an AC voltage is applied, and a transistor that controls an inductor current flowing in the inductor, the integrated circuit switching the transistor of a power supply circuit that generates an output voltage of the desired level from the AC voltage. The integrated circuit comprises: a first terminal to which a voltage corresponding to the AC voltage is applied, and to which a first capacitor is connected; a drive circuit that turns the transistor on when a prescribed condition is satisfied, and turns the transistor off, on the basis of a feedback voltage corresponding to the output voltage and a voltage corresponding to the AC voltage, so that the period in which the transistor is turned on is progressively shortened as the voltage level that corresponds to the AC voltage becomes higher; and a discharge circuit that discharges the first capacitor before a second timing at which the transistor is turned on after a first timing at which the transistor is turned off.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power supply circuit. [Background technology]

[0002] Conventionally, in power supply circuits that output a DC voltage of a target level from an AC power supply to a load, integrated circuits that control the on-period of a transistor according to the phase angle of the rectified voltage have been used (see, for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 11-98820 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-115105 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-94697 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, such an integrated circuit is provided with a terminal to which a voltage corresponding to the rectified voltage is applied. However, if a surge protection capacitor is connected to the terminal to which a voltage corresponding to the rectified voltage is applied, the integrated circuit may not be able to properly control the on-period of the transistor, resulting in a deterioration in power factor.

[0005] The present invention provides an integrated circuit and a power supply circuit that can improve the power factor. [Means for solving the problem]

[0006] In order to solve the above problem, a first aspect of the present invention provides an integrated circuit for switching the transistor of a power supply circuit that generates an output voltage of a target level from the AC voltage, the integrated circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor. The integrated circuit comprises: a first terminal to which a voltage corresponding to the AC voltage is applied and to which a first capacitor is connected; a drive circuit that turns on the transistor when a predetermined condition is satisfied, and turns off the transistor based on a feedback voltage corresponding to the output voltage and a voltage corresponding to the AC voltage so that the higher the level of the voltage corresponding to the AC voltage, the shorter the period for which the transistor is turned on; and a discharge circuit that discharges the first capacitor from a first timing at which the transistor is turned off to a second timing at which the transistor is turned on.

[0007] In a second aspect of the present invention, there is provided a power supply circuit that generates an output voltage of a target level from an AC voltage, the power supply circuit comprising: an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor that controls an inductor current flowing through the inductor; and an integrated circuit that switches the transistor. The integrated circuit includes: a first terminal to which a voltage corresponding to the AC voltage is applied and to which a first capacitor is connected; a drive circuit that turns on the transistor when a predetermined condition is satisfied, and turns off the transistor based on a feedback voltage corresponding to the output voltage and a voltage corresponding to the AC voltage so that the higher the level of the voltage corresponding to the AC voltage, the shorter the period for which the transistor is turned on; and a discharge circuit that discharges the first capacitor from a first timing at which the transistor is turned off to a second timing at which the transistor is turned on. [Effects of the Invention]

[0008] It is possible to provide an integrated circuit and a power supply circuit that can improve the power factor.

[0009] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows an example of the configuration of an AC-DC converter 11a. [Figure 2] An example of the configuration of the power factor correction IC 28a is shown. [Figure 3] 1 shows an example of the configuration of the oscillator circuit 55a. [Figure 4] An example of the configuration of the discharge circuit 41 is shown. [Figure 5] 10 shows an example of an operating waveform of the discharge circuit 41. [Figure 6] 1 shows an example of main waveforms of voltage and current of an AC-DC converter 11a using a power factor correction IC 28a including a discharge circuit 41. [Figure 7] 10 shows an example of a waveform for explaining the influence of the operation of the discharge circuit 41 on the voltage Vh. [Figure 8] 10 shows an example of main waveforms of voltage and current in the AC-DC converter 11a when the power factor correction IC 28a does not have a discharge circuit 41. [Figure 9] 1 shows an example of the configuration of a power supply device 10. [Figure 10] An example of the configuration of the AC-DC converter 11b is shown. [Figure 11] An example of the configuration of the power factor correction IC 28b is shown. [Figure 12] An example of the configuration of the power factor correction IC 28c is shown below. [Figure 13] An example of the configuration of the oscillation circuit 55b is shown. [Figure 14] 1 shows an example of main waveforms of voltage and current in an AC-DC converter 11a having a power factor correction IC 28c. [Figure 15] An example of the configuration of the AC-DC converter 15 is shown. [Figure 16] An example of the configuration of the power factor correction IC 110a is shown. [Figure 17] An example of the configuration of the discharge circuit 46 is shown. [Figure 18] An example of the configuration of the AC-DC converter 11c is shown. [Figure 19] An example of the configuration of the power factor correction IC 110b is shown. [Figure 20] An example of the configuration of the power factor correction IC 110c is shown. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. Furthermore, identical or equivalent components, members, etc. shown in each drawing are given the same reference numerals, and redundant explanations will be omitted as appropriate.

[0012] In this specification, the term "connection" is used, and unless otherwise specified, "connection" means "electrical connection." In this specification, when a voltage or signal has a high logic level, it is referred to as an "H" level, and when the logic level is a low logic level, it is referred to as an "L" level.

[0013] Figure 1 shows an example of the configuration of an AC-DC converter 11a. The AC-DC converter 11a is a boost chopper-type power supply circuit that generates an output voltage Vout at a target level from an AC voltage Vac of a commercial power supply. The output voltage Vout generated by the AC-DC converter 11a is used to drive a load 12.

[0014] The load 12 is, for example, a DC-DC converter or an electronic device that operates on a DC voltage.

[0015] The AC-DC converter 11a includes an input line filter 21, a full-wave rectifier circuit 22, capacitors 23, 27, 32, 36, and 37, a transformer 24, resistors 25, 33 to 35, diodes 26, 30, and 31, a power factor correction IC 28a, and an NMOS transistor 29.

[0016] ===Input to full-wave rectifier circuit 22=== The AC power supply 20 is a commercial AC power supply for supplying an AC voltage Vac to the input line filter 21. The AC voltage Vac is, for example, a voltage of 100 to 277 V and a frequency of 50 to 60 Hz.

[0017] The input line filter 21 removes noise from the AC voltage Vac and supplies the input voltage Vin to the full-wave rectifier circuit 22. The input line filter 21 is provided between nodes N1 and N2 to which the AC voltage Vac is applied and the full-wave rectifier circuit 22 (described later). In this embodiment, the current at the nodes N1 and N2 to which the AC voltage Vac is applied is referred to as the input current Iin.

[0018] ===Configuration from full-wave rectifier circuit 22 to load 12=== The full-wave rectifier circuit 22 full-wave rectifies the input voltage Vin and applies the rectified voltage Vrec to a capacitor 23 and a main coil L1 of a transformer 24.

[0019] The capacitor 23 smoothes the rectified voltage Vrec supplied from the full-wave rectifier circuit 22 .

[0020] The transformer 24 has a main coil L1 through which an inductor current IL flows and an auxiliary coil L2 magnetically coupled to the main coil L1. In this embodiment, the auxiliary coil L2 is wound so that the voltage generated in the auxiliary coil L2 has the opposite polarity to the voltage generated in the main coil L1. The auxiliary coil L2 is connected to a terminal ZCD of a power factor correction IC 28a (described later) via a resistor 25. A voltage Vzcd corresponding to the current flowing through the auxiliary coil L2 is applied to the terminal ZCD.

[0021] The main coil L1, together with the diode 26, the capacitor 27, and the NMOS transistor 29, constitutes a boost chopper circuit. As a result, the charging voltage of the capacitor 27 is boosted to a DC output voltage Vout and supplied to the load 12.

[0022] The power factor correction IC (Integrated Circuit; IC) 28a is an integrated circuit that controls the switching of the NMOS transistor 29 so that the level of the output voltage Vout becomes a target level (for example, 400 V) while improving the power factor of the AC-DC converter 11a.

[0023] The power factor correction IC 28a has terminals FB, COMP, OUT, VH, and ZCD. Note that the power factor correction IC 28a is also provided with terminals other than the five terminals FB, COMP, OUT, VH, and ZCD described above, but these are omitted here for convenience.

[0024] The NMOS transistor 29 is a transistor for controlling the power to the load 12 of the AC-DC converter 11a. In this embodiment, the NMOS transistor 29 is used as a so-called switching element, but is not limited to this. For example, other transistors such as a PMOS transistor or a bipolar transistor may also be used as the switching element.

[0025] The gate electrode of the NMOS transistor 29 is connected to the terminal OUT so as to be driven by the signal Vdr from the terminal OUT.

[0026] The diodes 30 and 31 are connected in front of the full-wave rectifier circuit 22, and constitute a full-wave rectifier circuit that applies a voltage Vh obtained by full-wave rectifying the input voltage Vin to a terminal VH of the power factor correction IC 28a.

[0027] The anode of the diode 30 is connected to the non-grounded line upstream of the full-wave rectifier circuit 22. On the other hand, the anode of the diode 31 is connected to the grounded line upstream of the full-wave rectifier circuit 22. The cathodes of the diodes 30 and 31 are connected to the terminal VH of the power factor correction IC 28a. Note that the voltages at the cathodes of the diodes 30 and 31 may be divided and the divided voltage may be applied to the terminal VH of the power factor correction IC 28a.

[0028] A capacitor 32 is connected to the terminal VH to protect the power factor correction IC 28a from high-voltage noise (surge) such as lightning discharge. As an example, the capacitor 32 has a capacitance of 100 pF. However, the capacitance of the capacitor 32 may vary depending on the withstand voltage of the power factor correction IC 28a.

[0029] The resistors 33 and 34 form a voltage divider circuit that divides the output voltage Vout and generates a feedback voltage Vfb that is used when the power factor correction IC 28a switches the NMOS transistor 29. The feedback voltage Vfb generated at the node to which the resistors 33 and 34 are connected is applied to the terminal FB of the power factor correction IC 28a.

[0030] The resistor 35 and the capacitors 36 and 37 are elements for phase compensation of the power factor correction IC 28a. The resistor 35 and the capacitor 36 are connected in series between the terminal COMP and the ground, and the capacitor 37 is connected in parallel with them.

[0031] The main coil L1 corresponds to an "inductor." Furthermore, the terminal VH corresponds to a "first terminal," and the voltage Vh applied to the terminal VH corresponds to a "voltage according to an AC voltage." The capacitor 32 connected to the terminal VH corresponds to a "first capacitor." Furthermore, the NMOS transistor 29 corresponds to a "transistor."

[0032] Moreover, the terminal COMP corresponds to a "second terminal", and the capacitor 36 or 37 connected to the terminal COMP corresponds to a "second capacitor".

[0033] ==Power Factor Correction IC28a== Fig. 2 shows an example of the configuration of a power factor correction IC 28a. The power factor correction IC 28a includes a drive circuit 40a, a discharge circuit 41, and a load determination circuit 42. For convenience, terminals are depicted in Fig. 2 at different positions than in Fig. 1, but the wiring, elements, etc. connected to each terminal are the same in Figs. 1 and 2.

[0034] The drive circuit 40a outputs a signal Vdr to drive the NMOS transistor 29. As will be described in detail later, the drive circuit 40a turns on the NMOS transistor 29 when the inductor current IL becomes substantially zero, and turns off the NMOS transistor 29 when the oscillation voltage Vr becomes the voltage Vcomp.

[0035] The discharge circuit 41 discharges the capacitor 32 connected to the terminal VH while the drive circuit 40a keeps the NMOS transistor 29 off.

[0036] The load determination circuit 42 determines whether the load 12 is lightly loaded or not based on a voltage Vcomp and a reference voltage Vref1, which will be described later. Specifically, the load determination circuit 42 determines that the load 12 is not lightly loaded when the voltage Vcomp is higher than the reference voltage Vref1, and determines that the load 12 is lightly loaded when the voltage Vcomp is lower than the reference voltage Vref1. The load determination circuit 42 is a comparator that compares the voltage Vcomp with the reference voltage Vref1 applied to the terminal COMP, and outputs a signal Ven according to the comparison result.

[0037] Furthermore, the load 12 being "lightly loaded" means that the current flowing through the load 12 is equal to or less than a predetermined value (e.g., 100 mA), and the load 12 being "not lightly loaded" means that the current flowing through the load 12 is greater than a predetermined value (e.g., 100 mA).

[0038] ===Details of drive circuit 40a=== The drive circuit 40 a includes a zero current detection circuit 50 , a delay circuit 51 , a turn-on timer circuit 52 , an OR circuit 53 , a voltage divider circuit 54 , an oscillation circuit 55 a , an error voltage generation circuit 56 , a comparator 57 , an SR flip-flop 58 , and a buffer circuit 59 .

[0039] The zero current detection circuit 50 is a circuit that detects, based on the voltage Vzcd of the terminal ZCD, that the current value of the inductor current IL has reached a "current value Ia" indicating almost zero (hereinafter, for convenience, "almost zero" may be simply referred to as "0"). Note that, when the zero current detection circuit 50 of this embodiment detects that the current value of the inductor current IL is the "current value Ia" which is almost zero, it outputs an "H" level signal Vz. Note that the zero current detection circuit 50 is configured to include a comparator (not shown) that compares the voltage Vzcd with a predetermined voltage of the auxiliary coil L2 when the inductor current IL reaches the "current value Ia".

[0040] When the zero current detection circuit 50 outputs the "H" level signal Vz, the delay circuit 51 delays the signal Vz by a predetermined time and outputs a pulse signal Vp2.

[0041] If an "H" level drive signal Vp1 (described later) is not output for a predetermined turn-on period after an "H" level signal Vz is input, the turn-on timer circuit 52 outputs an "H" level pulse signal Vp3.

[0042] When the delay circuit 51 outputs a high-level pulse signal Vp2 or the turn-on timer circuit 52 outputs a high-level pulse signal Vp3, the OR circuit 53 outputs a high-level set signal Ss.

[0043] The voltage divider circuit 54 generates a voltage Vhdiv by dividing a voltage Vh obtained by full-wave rectifying the input voltage Vin. The voltage divider circuit 54 includes resistors 61 and 62. One end of the resistor 61 is connected to the terminal VH, and the other end is connected to one end of the resistor 62. The other end of the resistor 62 is grounded. As a result, a voltage Vhdiv is generated at the node to which the resistors 61 and 62 are connected. For example, the resistance value of the resistor 61 is 100 MΩ, and the resistance value of the resistor 62 is 1 MΩ. The resistor 61 corresponds to a "first resistor," and the resistor 62 corresponds to a "second resistor."

[0044] When the inductor current IL becomes smaller than the current value Ia and the drive signal Vp1 is at the "H" level, the oscillator circuit 55a outputs an oscillation voltage Vr whose amplitude gradually increases at a predetermined slope based on the voltage Vh. The oscillator circuit 55a is connected to a node between the resistors 61 and 62.

[0045] The error voltage generating circuit 56 is a transconductance amplifier that generates an error current Ie in accordance with the error between a reference voltage Vref2 corresponding to the target level of the output voltage Vout and the feedback voltage Vfb. The error voltage generating circuit 56 of this embodiment charges the capacitors 36 and 37 with the error current Ie. As a result, a voltage Vcomp is generated at the terminal COMP.

[0046] The comparator 57 is a circuit that compares the oscillation signal Vr with a voltage Vcomp that corresponds to the feedback voltage Vfb. Specifically, the voltage Vcomp is applied to the inverting input terminal of the comparator 57, and the oscillation voltage Vr is applied to the non-inverting input terminal of the comparator 57. Therefore, when the level of the oscillation voltage Vr is lower than the level of the voltage Vcomp, the comparator 57 outputs a reset signal Sr at an "L" level, and when the level of the oscillation voltage Vr becomes higher than the level of the voltage Vcomp, the comparator 57 outputs a reset signal Sr at an "H" level.

[0047] When the OR circuit 53 outputs a high-level set signal Ss, the SR flip-flop 58 outputs a high-level drive signal Vp1. On the other hand, when the comparator 57 outputs a high-level reset signal Sr, the SR flip-flop 58 outputs a low-level drive signal Vp1.

[0048] The buffer circuit 59 drives the NMOS transistor 29 based on the drive signal Vp1. Specifically, the buffer circuit 59 turns on the NMOS transistor 29 based on the drive signal Vp1 at an “H” level, and turns off the NMOS transistor 29 based on the drive signal Vp1 at an “L” level.

[0049] Regarding the inductor current IL, the current value Ia corresponds to a "predetermined value." The voltage Vcomp applied to the terminal COMP corresponds to an "error voltage." The load determination circuit 42 corresponds to a "determination circuit." The SR flip-flop 58 corresponds to a "drive signal output circuit."

[0050] ===Oscillator circuit 55a=== 3 shows an example of the configuration of the oscillation circuit 55a. The oscillation circuit 55a includes a charge / discharge circuit 70, a buffer circuit 71, and capacitors 72 and 73.

[0051] The charge / discharge circuit 70 is a circuit that charges and discharges a capacitor 72 to generate an oscillation voltage Vr with a predetermined slope, and includes a constant current source 74 that outputs a constant current Iramp0, an inverter 75, and an NMOS transistor 76.

[0052] The buffer circuit 71 outputs a bias voltage Vramp0 to the capacitor 72 based on the divided voltage Vhdiv. The buffer circuit 71 operates as a so-called voltage follower.

[0053] The NMOS transistor 76 is turned off when the inductor current IL becomes nearly zero and an "H" level drive signal Vp1 is input to the inverter 75. When the NMOS transistor 76 is turned off, the capacitor 72 is charged by the current Iramp0 from the constant current source 74. Meanwhile, the capacitor 73 is charged so as to maintain the bias voltage Vramp0 from the buffer circuit 71.

[0054] Therefore, the oscillation voltage Vr is the voltage of the capacitor 73 (i.e., the bias voltage Vramp0) plus the voltage of the capacitor 72. Therefore, when the drive signal Vp1 at the "H" level is input to the charge / discharge circuit 70, the oscillation voltage Vr gradually rises from the bias voltage Vramp0 at a predetermined gradient.

[0055] On the other hand, the NMOS transistor 76 is turned on when the drive signal Vp1 at the "L" level is input to the inverter 75. When the NMOS transistor 76 is turned on, the capacitor 72 is discharged. In this case, the charge accumulated in the capacitor 72 is extracted to ground via a transistor (not shown) in the output stage of the buffer circuit 71, the NMOS transistor 76, etc. When the capacitor 72 is discharged, the oscillation voltage Vr becomes the bias voltage Vramp0.

[0056] Although the charge / discharge circuit 70 uses the NMOS transistor 76 as an element for charging and discharging the capacitor 72, other switching elements such as a PMOS transistor or a bipolar transistor may also be used.

[0057] ===Discharge circuit 41=== 4 shows an example of the configuration of the discharge circuit 41 in FIG. 2. When the load 12 is not a light load, the discharge circuit 41 discharges the capacitor 32 from the time when the NMOS transistor 29 is turned off to the time when the NMOS transistor 29 is turned on. When the load 12 is a light load, the discharge circuit 41 stops discharging the capacitor 32. The discharge circuit 41 includes a resistor 80, an NMOS transistor 81, and a control circuit 82a.

[0058] Resistor 80 is an element that adjusts the value of the current that flows between the drain and source of NMOS transistor 81 (i.e., the discharge current of capacitor 32), and is connected to terminal VH. Resistor 80 has a resistance value that is smaller than the resistance values ​​of resistors 61 and 62 of voltage-dividing circuit 54 in FIG. 2. As an example, if resistor 61 has a resistance value of 100 MΩ and resistor 62 has a resistance value of 1 MΩ, resistor 80 is 100 kΩ. This ensures that the charge in capacitor 32 can be extracted reliably while NMOS transistor 29 is off.

[0059] The NMOS transistor 81 functions as a switch that draws out to ground the charge stored in the capacitor 32 connected to the terminal VH. The NMOS transistor 81 discharges the capacitor 32 when the voltage Vdch applied to the gate electrode is at the “H” level, and stops discharging the capacitor 32 when the voltage Vdch is at the “L” level.

[0060] The drain electrode of the NMOS transistor 81 is connected to the other end of the resistor 80, and the source electrode of the NMOS transistor 81 is connected to a ground line Lgnd that serves as the ground potential. That is, the NMOS transistor 81 is provided between the resistor 80 and the ground line Lgnd.

[0061] ===Control circuit 82a=== 4 controls the on / off of the NMOS transistor 81 so that the capacitor 32 is discharged for a predetermined period Ta (for example, 3 μsec, which is shorter than the general off time of 10 μsec) when the NMOS transistor 29 is turned off if the load 12 is not a light load. Note that the control circuit 82a stops discharging the capacitor 32 if the load 12 is a light load.

[0062] Specifically, when the signal Ven is at the "H" level (indicating that the load 12 is not lightly loaded), the control circuit 82a turns on the NMOS transistor 81 for a predetermined period Ta after the drive signal Vp1 at the "L" level is input. Note that the control circuit 82a turns off the NMOS transistor 81 if the pulse-like signal Vz at the "H" level is input even before the period Ta has elapsed. Furthermore, the control circuit 82a turns off the NMOS transistor 81 when the signal Ven is at the "L" level (indicating that the load 12 is lightly loaded). Here, the control circuit 82a includes a timer circuit 85a and an AND circuit 86.

[0063] The timing circuit 85a counts the period Ta from the timing when the NMOS transistor 29 in Fig. 1 is turned off based on the drive signal Vp1 at the "L" level. The timing circuit 85a outputs the signal Vtm at the "H" level during the period Ta, and outputs the signal Vtm at the "L" level during other periods.

[0064] Furthermore, a signal Vz is input to the timer circuit 85a. The timer circuit 85 of this embodiment is designed to output a signal Vtm of an “L” level when a pulse-like signal Vz of an “H” level indicating that the inductor current IL has become 0 is input, regardless of whether the period Ta has elapsed or not.

[0065] This allows the timer circuit 85a to prevent the capacitor 32 from being discharged after the NMOS transistor 29 is turned on, thereby preventing the operation of the discharge circuit 41 from affecting the operation of the power factor correction IC 28a when the NMOS transistor 29 is turned on.

[0066] The timer circuit 85a may be designed to output a low-level signal Vtm when the drive signal Vp1 changes to a high level to turn on the NMOS transistor 29 before the period Ta has elapsed. In other words, the timer circuit 85a may output a low-level signal Vtm based on a high-level drive signal Vp1.

[0067] The AND circuit 86 turns on the NMOS transistor 81 when the load 12 is not light and during the period Ta after the NMOS transistor 29 is turned off, and turns off the NMOS transistor 81 during other periods. Specifically, the AND circuit 86 calculates the logical sum of the signals Ven and Vtm, and outputs a high-level signal Vdch when both the signals Ven and Vtm are high. The AND circuit 86 outputs a low-level signal Vdch in all other cases.

[0068] The resistor 80 corresponds to a “third resistor,” and the NMOS transistor 81 corresponds to a “switch.” The period Ta corresponds to a “predetermined period.”

[0069] ===Operation waveform of discharge circuit 41=== Fig. 5 shows an example of the operating waveforms of the discharge circuit 41. Fig. 5 shows the waveforms of the main signals in the discharge circuit 41. Note that the diagram starts from a state where, at an initial time, the current flowing through the load 12 is large and the voltage Vcomp is higher than the reference voltage Vref1.

[0070] At time t1, the buffer circuit 59 in FIG. 2 changes the signal Vdr output to the gate electrode of the NMOS transistor 29 to the "H" level.

[0071] At time t2, when the oscillation voltage Vr output from the oscillation circuit 55a reaches the voltage Vcomp from the error voltage generation circuit 56, the comparator 57 outputs a signal Ss to turn off the NMOS transistor 29. This causes the buffer circuit 59 to change the level of the signal Vdr it outputs to the "L" level.

[0072] The timing circuit 85a changes the level of the signal Vtm it outputs to the “H” level from the timing when the NMOS transistor 29 is turned off. The discharge circuit 41 changes the voltage Vdch applied to the gate electrode of the NMOS transistor 81 to the “H” level from the timing when the NMOS transistor 29 is turned off, and starts discharging the capacitor 32.

[0073] At time t3, a period Ta has elapsed since the discharge circuit 41 started discharging the capacitor 32. In response to this, the timer circuit 85a changes the level of the signal Vtm that it outputs to the “L” level, and the discharge circuit 41 changes the voltage Vdch that it applies to the gate electrode of the NMOS transistor 81 to the “L” level, thereby stopping the discharge of the capacitor 32.

[0074] After time t3, the inductor current IL becomes 0, and at time t4 after a predetermined delay period has elapsed, the buffer circuit 59 turns on the NMOS transistor 29. Thereafter, the operation from time t1 until the NMOS transistor 29 is turned on again is repeated.

[0075] Here, as the load 12 gradually becomes lighter, the current flowing through the load decreases, and the output voltage Vout increases. As a result, the error current Ie output by the error voltage generating circuit 56 decreases, and the voltage Vcomp applied to the terminal COMP decreases. At time t5, the voltage Vcomp applied to the terminal COMP reaches the reference voltage Vref1.

[0076] At time t6, in response to the voltage Vcomp becoming lower than the reference voltage Vref1, the load determination circuit 42 outputs the signal Ven at the "L" level, indicating that the load 12 is lightly loaded. After that, the AND circuit 86 outputs the "L" level regardless of the level of the signal Vtm. Therefore, the discharge circuit 41 does not perform a discharge operation until the level of the signal Ven becomes the "H" level again.

[0077] In this way, when the load 12 is lightly loaded, the discharge circuit 41 stops the discharge operation of the capacitor 32. As a result, when the load 12 is lightly loaded, the power consumption of the AC-DC converter 11a can be reduced. Therefore, the discharge circuit 41 of this embodiment realizes a reduction in power consumption according to the load state.

[0078] ===Operating waveforms of AC-DC converter 11a=== FIG. 6 shows an example of main waveforms of voltage and current of an AC-DC converter 11a using a power factor correction IC 28a including a discharge circuit 41.

[0079] At time t10, the phase angle of voltage Vh obtained by full-wave rectifying AC voltage Vac is 0 degrees, and the level of divided voltage Vhdiv obtained by dividing voltage Vh is lowest. The buffer circuit 71 in FIG. 3 outputs divided voltage Vhdiv as bias voltage Vramp0. Therefore, bias voltage Vramp0 begins to rise in response to the rise in divided voltage Vhdiv.

[0080] At time t11, when the inductor current IL becomes less than approximately zero, the delay circuit 51 in FIG. 2 outputs a high-level pulse signal Vp2. Then, the SR flip-flop 58 outputs a high-level drive signal Vp1, causing the power factor correction IC 28a to turn on the NMOS transistor 29. Note that the bias voltage Vramp0 is higher than it was at time t10.

[0081] When the NMOS transistor 29 turns on, the charge / discharge circuit 70 starts charging the capacitor 72 with the constant current Iramp0. The oscillation voltage Vr then becomes the sum of the bias voltage Vramp0 output by the buffer circuit 71 and the voltage of the capacitor 73. At this time, the oscillation voltage Vr gradually rises at a predetermined slope because the capacitor 72 is charged with the constant current Iramp0.

[0082] At time t12, when the oscillation voltage Vr reaches the voltage Vcomp, the comparator 57 outputs a high-level reset signal Sr, which causes the SR flip-flop 58 to output a low-level drive signal Vp1, causing the power factor correction IC 28a to turn off the NMOS transistor 29.

[0083] When the NMOS transistor 29 turns off, the charge / discharge circuit 70 discharges the capacitor 72, and the oscillation voltage Vr becomes the bias voltage Vramp 0. Then, from time t12 to time t13, the power factor correction IC 28a repeatedly drives the NMOS transistor 29 in the same manner.

[0084] When the NMOS transistor 29 is turned off, the discharge circuit 41 discharges the capacitor 32 during the period Ta. As a result, when the rectified voltage Vrec (and the input voltage Vin) has a low phase angle and the absolute value of the rectified voltage Vrec is small, the voltage Vh applied to the terminal VH to which the capacitor 32 is connected becomes a low voltage similar to the rectified voltage Vrec. When charge is not extracted from the capacitor 32, the voltage Vh may not decrease even when the rectified voltage Vrec has a low phase angle. This will be described in detail later with reference to FIG. 8.

[0085] Furthermore, from time t12 to time t13, bias voltage Vramp0 rises in accordance with the rise in divided voltage Vhdiv. This means that the starting point (offset voltage from 0 V) ​​of oscillation voltage Vr, which rises after NMOS transistor 29 is turned on, rises. Therefore, the time it takes for oscillation voltage Vr output by oscillation circuit 55a to rise and reach voltage Vcomp gradually shortens, and accordingly the on-period of NMOS transistor 29 gradually shortens.

[0086] At time t13, the power factor correction IC 28a turns on the NMOS transistor 29, and at time t14, the power factor correction IC 28a turns off the NMOS transistor 29. The on period of the NMOS transistor 29 from time t13 to time t14 is shorter than the on period of the NMOS transistor 29 from time t11 to time t12. This is because the voltage level of the bias voltage Vramp0 (i.e., the divided voltage Vhdiv), which changes depending on the level of the voltage Vh, is higher from time t13 to time t14 than from time t11 to time t12.

[0087] Therefore, the power factor correction IC 28a controls the NMOS transistor 29 so that the on-period of the NMOS transistor 29 becomes shorter as the level of the voltage Vh becomes higher and becomes longer as the level of the voltage Vh becomes lower. From time t14 to time t15, the power factor correction IC 28a repeatedly drives the NMOS transistor 29 in the same manner. Also, from time t14 to time t15, the bias voltage Vramp0 decreases in accordance with the decrease in the divided voltage Vhdiv. Therefore, from time t14 onwards, the on-period of the NMOS transistor 29 gradually becomes longer.

[0088] At time t15, the phase angle of the voltage Vh obtained by full-wave rectifying the AC voltage Vac is 180 degrees, and the level of the divided voltage Vhdiv obtained by dividing the voltage Vh is the lowest.

[0089] As described above, the power factor correction IC 28a lengthens the on-period of the NMOS transistor 29 when the absolute value of the AC voltage Vac is small, thereby allowing a large amount of inductor current IL to flow in the region where the AC voltage Vac has a low phase angle. This allows the power factor correction IC 28a to suppress the occurrence of a "dead angle," which is a phenomenon in which the input current Iin stops flowing when the absolute value of the AC voltage Vac is small.

[0090] Furthermore, by the buffer circuit 71 changing the bias voltage Vramp0, it is possible to change the ON period of the NMOS transistor 29 regardless of the influence of noise components of the voltage Vcomp due to switching noise of the NMOS transistor 29 or the like.

[0091] A "high phase angle" of the input current Iin and AC voltage Vac means that the angle is in the range of, for example, 90±10+180n degrees, i.e., (80 to 100)+180n degrees. On the other hand, a "low phase angle" means that the angle is in the range of, for example, 0±10+180n degrees, i.e., (-10 to +10)+180n degrees, where n is an integer.

[0092] Furthermore, the power factor correction IC 28a of this embodiment is provided with a discharge circuit 41, which discharges the charge accumulated in the capacitor 32 while the NMOS transistor 29 is off. As a result of the discharge of the capacitor 32 by the discharge circuit 41, the waveform of the voltage Vh becomes similar to that of the rectified voltage Vrec in accordance with the phase angle. Therefore, the power factor correction IC 28a can suppress the occurrence of a dead angle when the rectified voltage Vrec (and the input voltage Vin) are in a low phase, thereby improving the power factor and total harmonic distortion (THD).

[0093] 6, only a few pulses of the drive signal Vp1 are shown to facilitate understanding of the operation of the power factor correction IC 28a of the embodiment shown in FIG. 2. However, the switching frequency of the NMOS transistor 29 is, for example, several kHz, which is sufficiently higher than the frequency of the AC voltage Vac, which is 50 to 60 Hz. Therefore, in reality, a large number of drive signals Vp1 are included in one cycle of the AC voltage Vac.

[0094] The timing when the power factor correction IC 28a turns off the NMOS transistor 29 (times t12, t14, etc.) corresponds to the "first timing," and the timing when the power factor correction IC 28a turns on the NMOS transistor 29 (times t11, t13, etc.) corresponds to the "second timing."

[0095] ===Effect of operation of discharge circuit 41 on voltage Vh=== 7 shows an example of a waveform for explaining the effect of the operation of the discharge circuit 41 on the voltage Vh. The following explanation focuses on a specific switching period (from time t31 to time t34) of the NMOS transistor 29. However, the voltage Vh changes in the same way in other switching periods of the NMOS transistor 29.

[0096] 7 shows a waveform in the case where the load determination circuit 42 determines that the load 12 is not a light load throughout the entire period in the figure. Therefore, during this period, the discharge circuit 41 operates while the NMOS transistor 29 is off.

[0097] From time t30 to time t31, the buffer circuit 59 in FIG.

[0098] At time t31, the buffer circuit 59 changes the signal Vdr to the “L” level to turn off the NMOS transistor 29. From this timing, the control circuit 82a in FIG. 4 switches the signal Vdch output to the gate electrode of the NMOS transistor 81 to the “H” level.

[0099] As a result, the NMOS transistor 81 turns on, and the charge stored in the capacitor 32 is drawn to ground through the resistor 80 and the NMOS transistor 81. At this time, the voltage Vh applied to the terminal VH decreases according to a time constant determined mainly by the capacitance value of the capacitor 32 and the resistance value of the resistor 80. Here, the on-resistance value of the NMOS transistor 81 is designed to be sufficiently smaller than the resistance value of the resistor 80.

[0100] At time t32, after a period Ta has elapsed since time t31, the control circuit 82a switches the signal Vdch to the "L" level. Between time t31 and time t32, the voltage Vh decreases due to the discharge of the discharge circuit 41. At time t32, the discharge of the discharge circuit 41 stops, and the voltage Vh increases from time t32 onwards.

[0101] At time t33, voltage Vh rises until it assumes a waveform similar to that of rectified voltage Vrec. In this way, after discharge circuit 41 stops discharging capacitor 23, voltage Vh rises until it returns to a waveform similar to that of rectified voltage Vrec before NMOS transistor 29 turns on.

[0102] At time t34, the buffer circuit 59 changes the signal Vdr to the “H” level to turn on the NMOS transistor 29. After that, the same operations as those from time t31 to time t34 are repeated, except that the phase angle between the rectified voltage Vrec and the voltage Vh changes.

[0103] If the power factor correction IC does not include the discharge circuit 41, the accumulation of charge in the capacitor 32 may cause the voltage Vh to have a waveform that is not similar to the waveform of the rectified voltage Vrec. The discharge circuit 41 discharges the capacitor 32 before the NMOS transistor 29 turns on, thereby maintaining the voltage Vh in a waveform similar to the rectified voltage Vrec. How this eliminates the dead angle will be explained below with reference to FIG. 8.

[0104] ===Waveform without discharge circuit 41=== FIG. 8 shows an example of main waveforms of voltage and current in the AC-DC converter 11a when the power factor correction IC 28a does not include the discharge circuit 41.

[0105] At time t40, the phase angle of the rectified voltage Vrec is 0 degrees, and at time t46, the phase angle of the rectified voltage Vrec is 180 degrees. Without the discharge circuit 41, even when the rectified voltage Vrec is in the range where the phase angle is low, charge may remain in the capacitor 32 connected to the terminal VH. As a result, the voltage Vh applied to the terminal VH does not decrease even in the range where the rectified voltage Vrec is in the low phase angle, and the waveform of the voltage Vh becomes DC-like.

[0106] 8, the operation of each circuit in the power factor correction IC without the discharge circuit 41 from time t41 to t45 is the same as the operation of each circuit from time t11 to t15. However, because the voltage Vh has a DC-like waveform, the difference between the time from time t41 to time t42 when the oscillation voltage Vr rises to voltage Vcomp and the time from time t43 to time t44 is small.

[0107] 8, the waveform of voltage Vh is not similar to the waveform of rectified voltage Vrec as in FIG. 6, and the period during which NMOS transistor 29 is turned on does not change according to the phase angle of rectified voltage Vrec.

[0108] In this case, when the rectified voltage Vrec is in the low phase angle range, the period during which the NMOS transistor 29 is turned on cannot be extended. Furthermore, when the rectified voltage Vrec is in the low phase angle range, the level of the rectified voltage Vrec is low, and the input current Iin is small. As a result, a dead angle occurs where the input current Iin is nearly zero in the low phase angle range.

[0109] In this way, if the capacitor 32 is provided but the discharge circuit 41 is not provided, a dead angle occurs in the range where the input current Iin has a low phase angle, which may deteriorate the power factor and total harmonic distortion of the power supply circuit.

[0110] On the other hand, when the discharge circuit 41 is provided, the waveform of the voltage Vh becomes similar to the waveform of the rectified voltage Vrec, and therefore the on period of the NMOS transistor 29 becomes longer in the range where the rectified voltage Vrec has a low phase angle. Therefore, in the range where the rectified voltage Vrec has a low phase angle, the inductor current IL becomes large, and the charge stored in the capacitor 23 is drawn out by the inductor current IL.

[0111] As a result, even if the rectified voltage Vrec has a low phase angle, the input current Iin flows, the dead angle is eliminated, and the power factor and total harmonic distortion of the power supply circuit are improved.

[0112] <<Variation 1>> 9 shows an example of the configuration of power supply device 10. Power supply device 10 is composed of AC-DC converter 11b, DC-DC converter 13, and load 14. In power supply device 10 of this embodiment, AC-DC converter 11b is connected to load 14 via DC-DC converter 13, which communicates with AC-DC converter 11b.

[0113] The AC-DC converter 11b generates an output voltage Vout1 from an AC voltage Vac from an AC power supply 20 that is applied to nodes N1 and N2.

[0114] The DC-DC converter 13 generates an output voltage Vout2 from the output voltage Vout1 applied to the nodes N3 and N4. The DC-DC converter 13 is, for example, an LLC current resonance type converter that generates an output voltage Vout2 of a target level from the voltage Vout1.

[0115] DC-DC converter 13 detects whether load 14 is in a light load state or not based on a voltage corresponding to the power consumption of load 14. Furthermore, DC-DC converter 13 outputs signal Sig indicating the state of load 14 based on the detection result. For example, DC-DC converter 13 outputs signal Sig with different pulse widths when load 14 is in a light load state and when load 14 is not in a light load state.

[0116] This allows AC-DC converter 11b to perform different operations according to the state of load 14 in response to signal Sig from DC-DC converter 13, which is an external circuit outside AC-DC converter 11b.

[0117] The load 14 is connected to the nodes N5 and N6 and receives the output voltage Vout2. The load 14 is, for example, an electronic device that operates on a DC voltage.

[0118] ==Configuration of AC-DC Converter 11b== 10 shows an example of the configuration of AC-DC converter 11b. AC-DC converter 11b includes input line filter 21, full-wave rectifier circuit 22, capacitors 23, 27, 32, 36, and 37, transformer 24, resistors 25, 33 to 35, diodes 26, 30, and 31, a power factor correction IC 28b, and NMOS transistors 29 and 38.

[0119] Here, in AC-DC converter 11b, components that are assigned the same reference symbols as those in AC-DC converter 11a correspond to the same components. The following mainly describes the differences between AC-DC converter 11b and AC-DC converter 11a.

[0120] The node to which load 12 was connected in AC-DC converter 11a corresponds to nodes N3 and N4 to which output voltage Vout1 is applied in AC-DC converter 11b and to which DC-DC converter 13 is connected.

[0121] The power factor correction IC 28b has terminals FB, COMP, OUT, VH, and ZCD, similar to the power factor correction IC 28a. The terminal FB is connected to a node to which the resistors 33 and 34 are connected, and an NMOS transistor 38 is also connected to the terminal FB.

[0122] The NMOS transistor 38 is provided between the terminal FB and ground and changes the feedback voltage Vfb at the terminal FB to a ground voltage (corresponding to the "L" level of the feedback voltage Vfb) during the pulse width of the signal Sig. Based on the period Tb (described later) during which the terminal FB is at the ground voltage, a signal corresponding to the pulse width of the signal Sig is input to the terminal FB. In other words, the feedback voltage Vfb input to the terminal FB changes during the period Tb during which the feedback voltage Vfb is at the "L" level, thereby transmitting information about the load state of the load 14. Note that a different switching element, such as a bipolar transistor, may be used instead of the NMOS transistor 38. The feedback voltage Vfb input to the terminal FB and changing during the period Tb during which the feedback voltage Vfb is at the "L" level according to the pulse width of the signal Sig corresponds to a "load determination signal."

[0123] ===Configuration of Power Factor Correction IC28b=== 11 shows an example of the configuration of a power factor correction IC 28b. The power factor correction IC 28b includes a drive circuit 40a, a discharge circuit 41, and a signal detection circuit 43. For convenience, the terminals are depicted in different positions in FIG. 11 than in FIG. 10, but the wiring, elements, etc. connected to each terminal are the same in FIGS. 10 and 11. The power factor correction IC 28b differs from the power factor correction IC 28a in that it does not include a load determination circuit 42 but includes a signal detection circuit 43.

[0124] In the power factor correction IC 28b, components that are assigned the same reference numerals as those in the power factor correction IC 28a correspond to the same components. The following mainly describes the differences between the power factor correction IC 28b and the power factor correction IC 28a.

[0125] The signal detection circuit 43 reads the state of the load 14 according to the period during which the feedback voltage Vfb is at ground voltage, and changes the level of the signal Ven according to the state of the load 14. Specifically, if the period during which the feedback voltage Vfb is at ground voltage is longer than a predetermined period Tb, the signal detection circuit 43 outputs a signal Ven at an “H” level indicating that the load 14 is not a light load. On the other hand, if the period during which the feedback voltage Vfb is at ground voltage is shorter than the predetermined period Tb, the signal detection circuit 43 outputs a signal Ven at an “L” level indicating that the load 14 is a light load. This allows the signal detection circuit 43 to output the same signal Ven as the load determination circuit 42.

[0126] In this embodiment, the NMOS transistor 38 and the signal detection circuit 43 are connected to the terminal FB, and the signal detection circuit 43 detects the state of the load 14 according to the pulse width of the signal Sig and outputs the signal Ven. In this way, by detecting the state of the load 14 using the existing terminal FB, the AC-DC converter 11b and the DC-DC converter 13 can operate in coordination without providing a dedicated terminal for communication. This makes it easier to achieve a reduction in the size of the power supply device 10. The terminal FB corresponds to the "third terminal."

[0127] As described above, the power factor correction IC 28b can also discharge the capacitor 32 based on the signal Sig according to the load state of the load 14. The discharge circuit 41 discharges the capacitor 32 when the load 14 is lightly loaded, and stops discharging when the load 14 is lightly loaded.

[0128] Therefore, the power consumption of the power factor correction IC 28b is reduced when the load 14 is lightly loaded. Furthermore, when the load 14 is not lightly loaded, the power factor correction IC 28b can make the voltage Vh similar to the rectified voltage Vrec. Therefore, the power factor correction IC 28b can suppress the occurrence of a dead angle when the rectified voltage Vrec is in a low phase, and can improve the power factor and total harmonic distortion.

[0129] In this embodiment, the NMOS transistor 38 and the signal detection circuit 43 are connected to the terminal FB. However, the power factor correction IC 28b may include another dedicated terminal, and the signal detection circuit 43 may be connected to the dedicated terminal. In this case, for example, the NMOS transistor 38 may not be provided, and information on the state of the load 14 may be transmitted by the level of the signal Sig input from the terminal, rather than by the pulse width of the signal Sig. The signal detection circuit 43 may detect the level of the signal Sig and output a signal Ven according to the load state. In this case, the signal Sig itself corresponds to the "load determination signal."

[0130] <<Variation 2>> ==Configuration of Power Factor Correction IC28c== 12 shows an example of the configuration of the power factor correction IC 28c. The power factor correction IC 28c may be included in the AC-DC converter 11a in FIG. 1 in place of the power factor correction IC 28a.

[0131] The power factor correction IC 28c includes a drive circuit 40b, a discharge circuit 41, and a load determination circuit 42. The power factor correction IC 28c differs from the power factor correction IC 28a in that it includes the drive circuit 40b.

[0132] Here, in the power factor correction IC 28c, components that are assigned the same reference symbols as those in the power factor correction IC 28a correspond to the same components. The following mainly describes the differences between the power factor correction IC 28c and the power factor correction IC 28a.

[0133] The drive circuit 40b includes a zero current detection circuit 50, a delay circuit 51, a voltage dividing circuit 54, an oscillation circuit 55b, an error voltage generating circuit 56, a comparator 57, an SR flip-flop 58, and a buffer circuit 59.

[0134] 13, the oscillator circuit 55b of this embodiment outputs a ramp-shaped oscillator voltage Vr with a smaller slope as the phase angle of the rectified voltage Vrec decreases, and outputs an oscillator voltage Vr with a larger slope as the phase angle of the rectified voltage Vrec increases, depending on the level of the voltage Vh. As a result, the shorter the phase angle of the rectified voltage Vrec, the longer the period until the oscillator voltage Vr reaches the voltage Vcomp, and the longer the on-period of the NMOS transistor 29. Furthermore, the shorter the phase angle of the rectified voltage Vrec, the shorter the on-period of the NMOS transistor 29.

[0135] ==Operation of drive circuit 40b== In this embodiment, the drive circuit 40b operates as follows. ===NMOS transistor 29 turns from on to off=== The oscillator circuit 55b supplies an oscillator voltage Vr having a gradually increasing ramp waveform. When the oscillator voltage Vr from the oscillator circuit 55b reaches the voltage Vcomp, the comparator 57 outputs a signal Sr of "H" level.

[0136] In response to the high-level signal Sr, the SR flip-flop 58 outputs a low-level drive signal Vp1. In response to the low-level drive signal Vp1, the buffer circuit 59 outputs a low-level signal Vdr that turns off the NMOS transistor 29.

[0137] ===NMOS transistor 29 changes from off to on=== When the NMOS transistor 29 in FIG. 1 is turned off, the inductor current IL flowing through the main coil L1 decreases. When the inductor current IL becomes zero, the zero current detection circuit 50 detects that the current value of the inductor current IL is zero based on the voltage Vzcd. A high-level signal Vz is output.

[0138] Based on the high-level signal Vz, the SR flip-flop 58 outputs a high-level drive signal Vp1 that turns on the NMOS transistor 29. The buffer circuit 59 outputs a high-level signal Vdr in response to the high-level drive signal Vp1 that turns on the NMOS transistor 29.

[0139] ==Configuration of oscillator circuit 55b== 13 shows an example of the configuration of the oscillator circuit 55b, which includes a current source 91, an inverter 92, a bipolar transistor 93, and a capacitor 94.

[0140] The current source 91 is a current source that supplies a current Iramp1 having a current value proportional to the voltage Vhdiv applied to the terminal VH.

[0141] The inverter 92 switches the level of the voltage applied to the base electrode of the bipolar transistor 93 in response to the drive signal Vp1 to turn on and off the bipolar transistor 93. Specifically, when the inductor current IL becomes substantially zero and an "H" level drive signal Vp1 that turns on the NMOS transistor 29 is input, the inverter 92 turns off the bipolar transistor 93. On the other hand, when an "L" level drive signal Vp1 that turns off the NMOS transistor 29 is input, the inverter 92 turns on the bipolar transistor 93.

[0142] When the bipolar transistor 93 is turned off, the current Iramp1 from the current source 91 charges the capacitor 94. As a result, a voltage having a rising ramp waveform is output as the oscillation voltage Vr. Here, the current value of the current Iramp1 is proportional to the absolute value of the voltage Vhdiv, which is proportional to the absolute value of the rectified voltage Vrec. Therefore, the oscillation circuit 55b outputs an oscillation voltage Vr with a smaller slope as the phase angle of the rectified voltage Vrec decreases, and a larger slope as the phase angle of the input voltage increases.

[0143] On the other hand, when the drive signal Vp 1 of “L” level is input, the bipolar transistor 93 is turned on, and the charge stored in the capacitor 94 is extracted via the bipolar transistor 93 .

[0144] Instead of the bipolar transistor 93, other transistors such as an NMOS transistor or a PMOS transistor may be used.

[0145] ==Operating waveforms of AC-DC converter 11a including power factor correction IC 28c== 14 shows an example of the main waveforms of voltage and current in the AC-DC converter 11a including the power factor correction IC 28c. At time t50, the phase angle of the rectified voltage Vrec is 0 degrees, and at time t57, the phase angle of the rectified voltage Vrec is 180 degrees. The operation of the power factor correction IC 28c during this period will be described below.

[0146] At time t51, the SR flip-flop 58 in Fig. 12 outputs a high-level drive signal Vp1, and the buffer circuit 59 outputs a high-level signal Vdr that turns on the NMOS transistor 29. In response to the high-level drive signal Vp1, the bipolar transistor 93 in Fig. 13 turns off, and the current source 91 supplies a current Iramp1 that corresponds to the level of the voltage Vhdiv. This charges the capacitor 94, and the oscillator circuit 55b outputs a ramp-shaped oscillation voltage Vr whose slope corresponds to the level of the voltage Vhdiv.

[0147] At time t52, when the oscillation voltage Vr reaches the voltage Vcomp, the comparator 57 outputs a high-level signal Sr. This causes the SR flip-flop 58 to output a low-level drive signal Vp1, and the buffer circuit 59 outputs a low-level signal Vdr to turn off the NMOS transistor 29. From this timing, the AND circuit 86 in FIG. 4 applies a high-level voltage Vdch to the gate electrode of the NMOS transistor 81 in response to the low-level drive signal Vp1. This causes the discharge circuit 41 to start discharging the capacitor 32.

[0148] At time t53, when the timer circuit 85a in FIG. 4 times the period Ta, the AND circuit 86 outputs the signal Vdch at the “L” level, and the discharge circuit 41 stops discharging the capacitor 32.

[0149] At time t54, when the inductor current IL flowing through the main coil L1 of the transformer 24 becomes 0 and switches to negative, a positive current flows through the auxiliary coil L2, and a positive voltage Vzcd is input to the S input of the SR flip-flop 58. This causes the SR flip-flop 58 to output an "H" level drive signal Vp1, and the buffer circuit 59 outputs an "H" level signal Vdr that turns on the NMOS transistor 29. After this, the operations from time t51 to time t54 are repeated.

[0150] At time t55, the power factor correction IC 28c turns on the NMOS transistor 29, and at time t56, the power factor correction IC 28c turns off the NMOS transistor 29. The on period of the NMOS transistor 29 from time t55 to time t56 is shorter than the on period of the NMOS transistor 29 from time t51 to time t52.

[0151] This is because, in the period from time t55 to time t56, current source 91 supplies a larger current Iramp1 than in the period from time t51 to time t52, depending on the level of voltage Vhdiv. As a result, the charge stored in capacitor 94 increases, and the slope of the ramp-shaped oscillation voltage Vr output by oscillation circuit 55b also increases. As a result, in the period from time t55 to time t56, oscillation voltage Vr rises to voltage Vcomp more quickly than in the period from time t51 to time t52.

[0152] Therefore, like the power factor correction ICs 28a and 28b, the power factor correction IC 28c turns on the NMOS transistor 29 for a longer period as the rectified voltage Vrec has a lower phase angle and the level of voltage Vh becomes lower. On the other hand, the power factor correction IC 28c turns on the NMOS transistor 29 for a shorter period as the rectified voltage Vrec has a higher phase angle and the level of voltage Vh becomes higher. This allows the power factor correction IC 28c to also eliminate the dead angle and improve the power factor and total harmonic distortion of the power supply circuit.

[0153] ===Power Factor Correction IC Variants=== In the power factor correction ICs 28a and 28b, the slope of the oscillation voltage Vr is kept constant, and the offset voltage of the rising edge of the oscillation voltage Vr is increased as the phase angle of the rectified voltage Vrec decreases, thereby lengthening the period until the oscillation voltage Vr reaches the voltage Vcomp.In addition, in the power factor correction IC 28c, the slope of the oscillation voltage Vr is decreased as the phase angle of the rectified voltage Vrec decreases, thereby lengthening the period until the oscillation voltage Vr reaches the voltage Vcomp.

[0154] As a further modification, the slope of the oscillation voltage Vr is kept constant, and the period until the oscillation voltage Vr rises and reaches the voltage Vcomp can be lengthened by making the voltage Vcomp higher as the phase angle becomes lower and lower as the phase angle becomes higher. Such a voltage Vcomp can be generated, for example, by inverting the voltage Vh (or voltage Vhdiv) and then level-shifting it.

[0155] Even in a power factor correction IC having a circuit or element that generates such voltage Vcomp, by providing a discharge circuit 41 at terminal VH, it is possible to generate voltage Vcomp that changes according to the phase angle. Therefore, an AC-DC converter including this power factor correction IC can also eliminate the dead angle and improve the power factor and total harmonic distortion.

[0156] ===Other embodiments=== <<Power Factor Correction IC110a>> 15 shows an example of the configuration of AC-DC converter 15. AC-DC converter 15 is a boost chopper type power supply circuit similar to AC-DC converter 11a. In AC-DC converter 15, a coil 100 and a power factor correction IC 110a are used instead of the transformer 24 and the power factor correction IC 28a of AC-DC converter 11a in FIG. 1, respectively.

[0157] The coil 100 is an element that constitutes a boost chopper circuit, similar to the main coil L1 in FIG.

[0158] The power factor correction IC 110a is an integrated circuit that turns on the NMOS transistor 29 at predetermined intervals (i.e., fixed intervals). As shown in FIG. 16, the power factor correction IC 110a includes a load determination circuit 42, a drive circuit 45a, and a discharge circuit 46.

[0159] The drive circuit 45a turns on the NMOS transistor 29 at predetermined intervals, and when the oscillation voltage Vr reaches the voltage Vcomp, turns off the NMOS transistor 29. The drive circuit 45a includes a voltage divider circuit 54, an oscillation circuit 55a, an error voltage generation circuit 56, a comparator 57, an SR flip-flop 58, a buffer circuit 59, and a clock oscillation circuit 200.

[0160] 2, the configuration of the drive circuit 45a is the same except for the clock oscillation circuit 200 that turns on the NMOS transistor 29 at predetermined intervals. Therefore, only the clock oscillation circuit 200 will be described here.

[0161] The clock oscillation circuit 200 outputs a signal CLK that goes high every predetermined period, so that the NMOS transistor 29 is turned on every predetermined period and turned off when the oscillation voltage Vr reaches the voltage Vcomp.

[0162] When the NMOS transistor 29 is turned on, if the inductor current IL flowing through the coil 100 is positive (current value greater than zero), the AC-DC converter 15 (power factor correction circuit) operates in the continuous current mode.

[0163] On the other hand, if the inductor current IL flowing through the coil 100 resonates after becoming zero when the NMOS transistor 29 is turned on, the AC-DC converter 15 (power factor correction circuit) operates in discontinuous current mode. Note that the resonance of the inductor current IL occurs based on, for example, the parasitic capacitance of the coil 100 and the NMOS transistor 29.

[0164] 4, the discharge circuit 46 discharges the capacitor 32 connected to the terminal VH while the NMOS transistor 29 is turned off. As shown in FIG. 17, the discharge circuit 46 includes a resistor 80, an NMOS transistor 81, and a control circuit 82b.

[0165] The control circuit 82b is a circuit similar to the control circuit 82a of FIG.

[0166] The timer circuit 85b measures the period Ta from the timing when the NMOS transistor 29 is turned off based on the drive signal Vp1 at the "L" level. The timer circuit 85b outputs the signal Vtm at the "H" level during the period Ta, and outputs the signal Vtm at the "L" level during other periods. In this embodiment, the period Ta is shorter than the period during which the signal CLK is at the "L" level.

[0167] Even when such a power factor correction IC 110a is used, it is possible to eliminate the dead angle of the AC-DC converter 15 and improve the power factor and total harmonic distortion, similar to the power factor correction IC 28a.

[0168] <<Power Factor Correction IC110b>> Fig. 18 shows an example of the configuration of an AC-DC converter 11c. The AC-DC converter 11c is a boost chopper type power supply circuit similar to the AC-DC converter 11b shown in Fig. 10 used in the power supply device 10 of Fig. 9. In the AC-DC converter 11c, a coil 100 and a power factor correction IC 110b are used instead of the transformer 24 and the power factor correction IC 28b of the AC-DC converter 11b.

[0169] The power factor correction IC 110b is an integrated circuit that periodically turns on the NMOS transistor 29. As shown in FIG.

[0170] Even when such a power factor improvement IC 110b is used, the dead angle of the AC-DC converter 11c can be eliminated, and the power factor and total harmonic distortion can be improved.

[0171] <<Power Factor Correction IC110c>> 20 is a diagram illustrating an example of a power factor correction IC 110c. The power factor correction IC 110c can be used in the AC-DC converter 15, for example, in place of the power factor correction IC 110a.

[0172] The power factor correction IC 110c is an integrated circuit that turns on the NMOS transistor 29 at predetermined intervals, and includes a load determination circuit , a drive circuit 45b, and a discharge circuit .

[0173] The drive circuit 45b turns on the NMOS transistor 29 at predetermined intervals, and when the oscillation voltage Vr reaches the voltage Vcomp, turns off the NMOS transistor 29. The drive circuit 45b includes a voltage divider circuit 54, an oscillation circuit 55b, an error voltage generation circuit 56, a comparator 57, an SR flip-flop 58, a buffer circuit 59, and a clock oscillation circuit 200.

[0174] In the drive circuit 45b, an oscillator circuit 55b is used instead of the oscillator circuit 55a of the drive circuit 45a in FIG.

[0175] Therefore, even when such a power factor improvement IC 110c is used, the dead angle of the AC-DC converter 15 can be eliminated, and the power factor and total harmonic distortion can be improved.

[0176] ==Summary== The AC-DC converters 11a to 11c and 15 and the power factor correction ICs 28a to 28c and 110a to 110c of this embodiment have been described above.

[0177] The power factor correction ICs 28a to 28c each include a terminal VH to which a voltage Vh is applied and to which a capacitor 32 is connected, a drive circuit 40a or 40b that turns on an NMOS transistor 29 when an inductor current IL becomes smaller than a predetermined value Ia, and turns off the NMOS transistor based on a feedback voltage Vfb and the voltage Vh so that the period during which the NMOS transistor 29 is on becomes shorter as the level of the voltage Vh becomes higher, and a discharge circuit 41 that discharges the capacitor from the time the NMOS transistor is turned off to the time the NMOS transistor is turned on.

[0178] As a result, the discharge circuit 41 can discharge the capacitor 32 during the off-period of the NMOS transistor 29 without affecting the operation of the power factor correction ICs 28a-28c during the on-period of the NMOS transistor 29. The operation of the discharge circuit 41 maintains a waveform similar to that of the rectified voltage Vrec. In this case, the power factor correction ICs 28a-28c can control the on-period of the NMOS transistor 29 based on the voltage Vh so that the on-period of the NMOS transistor 29 becomes longer as the phase angle of the rectified voltage Vrec becomes shorter. As a result, the power factor correction ICs 28a-28c can suppress the occurrence of dead angles at low phase angles of the rectified voltage Vrec, improving the power factor and total harmonic distortion.

[0179] In addition, the same effect can be obtained even if power factor improvement ICs 110a to 110c that operate the power factor improvement circuit in continuous current mode or discontinuous current mode are used instead of power factor improvement ICs 28a to 28c that operate the power factor improvement circuit in critical current mode.

[0180] The discharge circuit 41 discharges the capacitor 32 for a period Ta from the timing when the NMOS transistor 29 is turned off.

[0181] This allows the discharge circuit 41 to discharge the capacitor 32 during the period in which the NMOS transistor 29 is turned off.

[0182] The discharge circuit 41 stops discharging the capacitor 32 when it detects that the inductor current IL has reached a predetermined value Ia.

[0183] This stops the discharge of the capacitor 32 before the timing at which the NMOS transistor 29 is turned on. Therefore, the discharge operation of the discharge circuit 41 can be prevented from affecting the operation of the power factor correction ICs 28a to 28c while the NMOS transistor 29 is on.

[0184] Furthermore, in the power factor correction ICs 28a to 28c, when the inductor current IL becomes smaller than the predetermined value Ia, the NMOS transistor 29 is turned on. Therefore, in this case, "a predetermined condition is satisfied" corresponds to, for example, the inductor current IL becoming smaller than the predetermined value Ia.

[0185] Furthermore, in the power factor correction ICs 110a to 110c, when the signal CLK goes to "H" level at predetermined intervals, the NMOS transistor 29 is turned on. Therefore, in this case, "a predetermined condition is satisfied" corresponds to, for example, the signal CLK going to "H" level at predetermined intervals.

[0186] The drive circuits 40a, 40b include an error voltage generation circuit 56 that generates a voltage Vcomp corresponding to the difference between the feedback voltage Vfb and a reference voltage Vref1, oscillation circuits 55a, 55b that output an oscillation voltage Vr corresponding to the level of the voltage Vh, an SR flip-flop 58 that outputs a drive signal Vp1 that turns on the NMOS transistor 29 when the inductor current IL becomes smaller than a predetermined value Ia and that outputs a drive signal Vp1 that turns off the NMOS transistor 29 when the oscillation voltage Vr becomes the voltage Vcomp, and a buffer circuit 59 that turns the NMOS transistor 29 on and off based on the drive signal Vp1.

[0187] As a result, in the drive circuits 40a and 40b, when the waveform of the voltage Vh is kept similar to the waveform of the rectified voltage Vrec, the lower the phase angle of the rectified voltage Vrec, the longer the on period of the NMOS transistor 29.

[0188] The drive circuits 40a and 40b include a voltage divider circuit 54 including a resistor 61 having one end connected to the terminal VH and a resistor 62 having one end connected to the other end of the resistor 61, and the oscillator circuit 55a is connected to a node between the resistors 61 and 62.

[0189] This allows the oscillation circuit 55a to generate the oscillation voltage Vr based on the voltage Vhdiv divided by the voltage divider circuit .

[0190] The discharge circuit 41 also includes a resistor 80 connected to the terminal VH, an NMOS transistor 81 provided between the resistor 80 and the ground line Lgnd, and a control circuit 82.

[0191] This allows for the realization of a discharge circuit 41 that discharges the capacitor 32 for an appropriate period of time.

[0192] The resistance value of the resistor 80 is smaller than the resistance value of the resistor 61 and the resistance value of the resistor 62 .

[0193] As a result, even when the voltage dividing circuit 54 is provided, the discharge circuit 41 can discharge the capacitor 32 during a sufficiently short period of time while the NMOS transistor 29 is off.

[0194] In addition, the oscillator circuit 55a outputs an oscillation voltage Vr having an offset voltage according to the level of the voltage Vh so that the on-period of the NMOS transistor 29 becomes shorter when the level of the voltage Vh becomes higher and the on-period of the NMOS transistor 29 becomes longer when the level of the voltage Vh becomes lower.

[0195] As a result, the power factor correction ICs 28a and 28b make the on-period of the NMOS transistor at low phase angles of the rectified voltage Vrec longer than at high phase angles, thereby eliminating the dead angle of the input current Iin and improving the power factor and total harmonic distortion.

[0196] In addition, the oscillation circuit 55b outputs an oscillation voltage Vr having a slope according to the level of the voltage VH such that the on-period of the NMOS transistor 29 becomes shorter when the level of the voltage Vh becomes higher and the on-period of the NMOS transistor 29 becomes longer when the level of the voltage Vh becomes lower.

[0197] In this way, even when using the oscillator circuit 55b that supplies the oscillation voltage Vr having a slope corresponding to the level of the voltage Vh, the power factor correction IC 28c can control the on-period of the NMOS transistor 29 according to the phase angle of the rectified voltage Vrec. This eliminates the dead angle of the input current Iin at low phase angles of the rectified voltage Vrec, improving the power factor and total harmonic distortion.

[0198] The power factor correction ICs 28a, 28c are connected to the output of the error voltage generating circuit 56 and include a terminal COMP to which the capacitor 32 is connected, and a load determination circuit 42 that determines whether the load 12 is in a light load state or not based on the voltage Vcomp applied to the terminal COMP. The discharge circuit 41 stops discharging the capacitor 32 when the load 12 is in a light load state, and discharges the capacitor 32 between the time when the NMOS transistor 29 is turned off and the time when the NMOS transistor 29 is turned on when the load 12 is not in a light load state.

[0199] As a result, in the power supply circuit including the power factor correction ICs 28a to 28c, the power factor and total high frequency distortion are improved, and the standby power consumption when the load 12 is lightly loaded can also be reduced.

[0200] The power factor correction IC 28b also has a terminal FB to which a signal corresponding to the pulse width of the signal Sig, which is output from the DC-DC converter 13, an external circuit, and indicates the state of the load 14, is input. When a signal indicating that the load 14 is in a light load state is input, the discharge circuit 41 stops discharging the capacitor 32, and when a signal indicating that the load 14 is not in a light load state is input, the discharge circuit 41 discharges the capacitor 32 from the time when the NMOS transistor 29 is turned off to the time when the NMOS transistor 29 is turned on.

[0201] As a result, by using the existing terminal FB to detect the state of the load 14, the AC-DC converter 11b and the DC-DC converter 13 can operate in coordination without providing a dedicated terminal for communication. Also, in a power supply circuit including the power factor correction IC 28b, the power factor and total harmonic distortion are improved, and standby power when the load 14 is lightly loaded can be reduced.

[0202] Furthermore, the AC-DC converters 11a and 11b each include one of the power factor correction ICs 28a to 28c.

[0203] This improves the power factor and total harmonic distortion in the power supply circuit including AC-DC converters 11a and 11b.

[0204] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that the technical scope of the present invention may include forms incorporating such modifications and improvements and their equivalents without departing from the spirit of the invention.

[0205] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0206] 10 Power supply 11a, 11b, 11c, 15 AC-DC converter 12 Load 13 DC-DC converter 14 Load 20 AC power supply 21 Input Line Filter 22 Full wave rectifier circuit 23 Capacitor 24 Transformer 25 Resistance 26 Diode 27 Capacitor 28a~28c,110a~110c Power Factor Correction IC 29 NMOS transistor 30 Diode 31 Diode 32 capacitor 33~35 Resistance 36,37 Capacitor 40a, 40b, 45a, 45b Drive circuit 41,46 discharge circuit 42 Load judgment circuit 50 Zero current detection circuit 51 Delay Circuit 52 Turn-on timer circuit 53 OR circuit 54 Voltage divider circuit 55a, 55b Oscillator circuit 56 Error voltage generation circuit 57 Comparator 58 SR Flip-Flop 59 Buffer Circuit 61,62 Resistance 70 Charge / discharge circuit 71 Buffer circuit 72,73 Capacitor 74 Constant current source 75 inverter 76 NMOS transistors 80 Resistance 81 NMOS transistor 82a, 82b control circuit 85a,85b Clock circuit 86 AND circuit 91 Current source 92 Inverter 93 Bipolar Transistor 94 Capacitor 100 coils 200 Clock Oscillator Circuit

Claims

1. An integrated circuit for switching a transistor in a power supply circuit that generates an output voltage of a target level from an AC voltage, the integrated circuit comprising: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and a transistor that controls an inductor current flowing through the inductor, the integrated circuit comprising: a first terminal to which a voltage corresponding to the AC voltage is applied and to which a first capacitor is connected; a drive circuit that turns on the transistor when a predetermined condition is satisfied, and turns off the transistor based on a feedback voltage corresponding to the output voltage and a voltage corresponding to the AC voltage, such that the period during which the transistor is turned on becomes shorter as the level of the voltage corresponding to the AC voltage becomes higher; a discharge circuit that discharges the first capacitor from a first timing at which the transistor is turned off to a second timing at which the transistor is turned on; Equipped with Integrated circuit.

2. 10. The integrated circuit of claim 1, the discharge circuit discharges the first capacitor for a predetermined period from the first timing. Integrated circuit.

3. 3. An integrated circuit according to claim 1 or claim 2, The drive circuit turns on the transistor when the inductor current becomes smaller than a predetermined value. Integrated circuit.

4. 4. An integrated circuit according to claim 3, the discharge circuit stops discharging the first capacitor when it is detected that the inductor current has reached the predetermined value. Integrated circuit.

5. 3. An integrated circuit according to claim 1 or claim 2, The drive circuit turns on the transistor at predetermined intervals. Integrated circuit.

6. 4. An integrated circuit according to claim 3, The drive circuit an error voltage generating circuit that generates an error voltage according to the difference between the feedback voltage and a reference voltage; an oscillation circuit that outputs an oscillation voltage corresponding to a voltage level corresponding to the AC voltage when the inductor current becomes smaller than the predetermined value; a drive signal output circuit that outputs a drive signal to turn on the transistor when the inductor current becomes smaller than the predetermined value, and outputs a drive signal to turn off the transistor when the oscillation voltage becomes the error voltage; a buffer circuit that turns on and off the transistor based on the drive signal; Including, Integrated circuit.

7. 7. An integrated circuit according to claim 6, the drive circuit includes a voltage divider circuit including a first resistor having one end connected to the first terminal and a second resistor having one end connected to the other end of the first resistor; the oscillator circuit is connected to a node between the first resistor and the second resistor; Integrated circuit.

8. 8. An integrated circuit according to claim 7, The discharge circuit includes: a third resistor connected to the first terminal; a switch provided between the third resistor and a ground line; a control circuit for controlling the on / off of the switch; Including, Integrated circuit.

9. 9. An integrated circuit according to claim 8, a resistance value of the third resistor is smaller than a resistance value of the first resistor and a resistance value of the second resistor; Integrated circuit.

10. 7. An integrated circuit according to claim 6, The oscillator circuit comprises: outputting the oscillation voltage having an offset voltage corresponding to the level of the voltage corresponding to the AC voltage such that the ON period of the transistor becomes shorter when the level of the voltage corresponding to the AC voltage becomes higher, and the ON period of the transistor becomes longer when the level of the voltage corresponding to the AC voltage becomes lower; Integrated circuit.

11. 7. An integrated circuit according to claim 6, The oscillator circuit comprises: outputting the oscillation voltage having a gradient according to the level of the voltage according to the AC voltage such that the ON period of the transistor becomes shorter when the level of the voltage according to the AC voltage becomes higher, and the ON period of the transistor becomes longer when the level of the voltage according to the AC voltage becomes lower; Integrated circuit.

12. 9. An integrated circuit according to claim 8, a second terminal connected to the output of the error voltage generating circuit and to which a second capacitor is connected; a determination circuit that determines whether a load state of the power supply circuit is light or not based on the error voltage applied to the second terminal; Equipped with The discharge circuit includes: When the load state is a light load, discharging of the first capacitor is stopped, and when the load state is not a light load, discharging the first capacitor from the first timing to the second timing. Integrated circuit.

13. 9. An integrated circuit according to claim 8, a third terminal to which a load determination signal that is output from an external circuit outside the integrated circuit and indicates a load state of the power supply circuit is input; The discharge circuit includes: When the load determination signal indicating that the load state is a light load is input, the discharging of the first capacitor is stopped, and when the load determination signal indicating that the load state is not a light load is input, the first capacitor is discharged from the first timing to the second timing. Integrated circuit.

14. A power supply circuit that generates an output voltage of a target level from an AC voltage, an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor for controlling an inductor current flowing through the inductor; an integrated circuit for switching the transistor; Equipped with The integrated circuit comprises: a first terminal to which a voltage corresponding to the AC voltage is applied and to which a first capacitor is connected; a drive circuit that turns on the transistor when a predetermined condition is satisfied, and turns off the transistor based on a feedback voltage corresponding to the output voltage and a voltage corresponding to the AC voltage, such that the period during which the transistor is turned on becomes shorter as the level of the voltage corresponding to the AC voltage becomes higher; a discharge circuit that discharges the first capacitor from a first timing at which the transistor is turned off to a second timing at which the transistor is turned on; Including, power circuit.

15. 15. The power supply circuit of claim 14, The drive circuit turns on the transistor when the inductor current becomes smaller than a predetermined value. power circuit.

16. 15. The power supply circuit of claim 14, The drive circuit turns on the transistor at predetermined intervals. power circuit.

Images