Adaptive replay of packets on peripheral interface links

Abstract

A system, method and circuitry are provided for adaptive replay of data link packets in a peripheral interface. In a computer system, a data link layer conforming to a peripheral interface protocol of a device includes a replay buffer memory for supporting both sequential replay and selective replay in response to packet errors. In response to detecting an erroneous packet, the receiver determines an adaptive threshold for selecting a replay mode based on a set of link operating parameters, and then selects between the selective replay mode and the sequential replay mode by comparing the fill level of the replay buffer to the determined adaptive threshold for that packet error.

Description

[Technical Field]

[0001] The present disclosure relates generally to data link layer communications over peripheral interfaces, and more particularly to using adaptive replay to dynamically select among replay modes to handle packet errors. [Background technology]

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard widely used in computer systems to connect various components and peripherals, such as data storage devices. As data transfer rates continue to increase, maintaining reliable communication between devices becomes increasingly challenging. PCIe incorporates error detection and correction mechanisms, including packet replay, to ensure data integrity. However, traditional replay methods can lead to inefficient bandwidth utilization and increased latency, especially when only a small portion of the transmitted data is affected by errors. For example, selective replay of packets can often be more efficient than sequential replay of all packets, but selective replay can be constrained by the size of the replay buffer on the receiving side of the PCIe interface's data link layer. In some operating conditions, it can be advantageous to proactively select between selective and sequential replay. As computing systems demand higher performance and lower latency, there is an increasing need for more advanced and adaptive techniques for managing packet replay in PCIe communications.

[0003] Therefore, there remains a need for more advanced and adaptive techniques for managing data link packet replay in PCIe communications that can improve bandwidth utilization and reduce latency while maintaining data integrity. Summary of the Invention

[0004] Various aspects are described for adaptive replay of data link packets in a peripheral interface. More particularly, the replay logic dynamically determines an adaptive threshold based on link operating parameters and selects between selective replay and sequential replay modes by comparing a replay buffer fill level to the adaptive threshold, enabling efficient handling of packet errors while optimizing buffer usage and system performance.

[0005] One general aspect includes a device including a peripheral interface configured to connect to a host system using a peripheral interface protocol, the peripheral interface protocol including a data link layer configured to transmit and receive data link packets, the peripheral interface including a replay buffer memory configured to store received data link packets following an erroneous packet to support a selective replay mode, and replay logic configured to: determine errors in the data link packets received via the peripheral interface, dynamically determine an adaptive threshold for selecting a replay mode based on a set of link operational parameters, select a replay mode selected from the selective replay mode for requesting retransmission of only the erroneous data link packet and the sequential replay mode for requesting retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet based on comparing a fill level of the replay buffer memory to the adaptive threshold, and transmit a replay request to the host system based on the selected replay mode.

[0006] Implementations may include one or more of the following features: The replay logic may be further configured to: store error-free sequential data link packets received after the erroneous data link packet in a replay buffer memory in response to a selective replay mode; sequentially transmit transaction layer content from the error-free version of the erroneous data link packet and the error-free sequential data link packets in the replay buffer memory in response to receiving an error-free version of the erroneous data link packet from the host system; and clear the error-free sequential data link packets from the replay buffer memory in response to a sequential replay mode; The replay logic may be further configured to discard sequential data link packets received after the erroneous data link packet in response to receiving the error-free version of the erroneous data link packet and retransmitted sequential data link packets received after the error-free version of the erroneous data link packet in response to receiving the error-free version of the erroneous data link packet and retransmitted sequential data link packets received after the error-free version of the erroneous data link packet in response to receiving the error-free version of the erroneous data link packet and retransmitted sequential data link packets The replay buffer memory may have a buffer size corresponding to a total number of data link packets that can be stored in the replay buffer memory at one time, the fill level may correspond to a current number of data link packets stored in the replay buffer memory due to pending selective replay requests, the adaptive threshold may correspond to a maximum fill level that is less than the buffer size of the replay buffer memory, and the replay logic may be further configured to periodically determine the adaptive threshold from a plurality of maximum fill levels based on a set of link operational parameters. The peripheral interface protocol may support a flow control mode configured to change the memory size and format of the data link packets, and the replay logic may be further configured to determine that the flow control mode is active, determine the fill level of the replay buffer memory based on the memory size and format of the data link packets in the flow control mode, and dynamically determine the adaptive threshold based on the flow control mode.The replay logic may be further configured to, in response to each detection of an erroneous data link packet, recalculate the adaptive threshold based on a current set of link operational parameters to dynamically determine an adaptive threshold for the erroneous data link packet. The replay logic may be further configured to dynamically determine the adaptive threshold by processing the set of link operational parameters through a statistical model including the set of link operational parameters and corresponding weighting factors configured to balance the likelihood of successfully recovering the erroneous data link packet and data link layer latency. The set of link operational parameters may include at least one link connection parameter selected from a current link speed, a number of lanes, and a bit error rate for the current link speed and number of lanes. The set of link operational parameters may include at least one link workload parameter selected from a current data link packet workload amount, a host system historical workload amount, and a predicted workload amount. The peripheral interface protocol may support a skip ordered set mode configured to periodically resynchronize the data link layer by introducing idle time between fixed-period transaction layer packet processing, the link set of operating parameters may include a counter for the fixed-period transaction layer packet processing, and dynamically determining the adaptive threshold in response to the skip ordered set mode may include compensation for the predicted idle time based on the counter. The device may be a data storage device including a non-volatile storage medium configured to store data for a host system and a peripheral interface connector configured to connect to a peripheral interface bus for storage communication with the host system using the peripheral interface protocol.

[0007] Another general aspect includes a computer-implemented method including receiving data link packets from a host system via a peripheral interface using a peripheral interface protocol; determining errors in the data link packets received via the peripheral interface; dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operational parameters; selecting a replay mode selected from a selective replay mode for requesting retransmission of only the erroneous data link packet and a sequential replay mode for requesting retransmission of the erroneous data link packet and subsequent data link packets transmitted after the erroneous data link packet based on comparing a fill level of a replay buffer memory to the adaptive threshold; and sending a replay request to the host system based on the selected replay mode.

[0008] Implementations may include one or more of the following features: The computer-implemented method may include storing, in a replay buffer memory, error-free sequential data link packets received after the erroneous data link packet in response to a selective replay mode; sequentially transmitting transaction layer content from the error-free version of the erroneous data link packet and the error-free sequential data link packets in the replay buffer memory in response to receiving the error-free version of the erroneous data link packet from the host system; and clearing the error-free sequential data link packets from the replay buffer memory. The computer-implemented method may include discarding, in response to a sequential replay mode, sequential data link packets received after the erroneous data link packet; and sequentially transmitting transaction layer content from the error-free version of the erroneous data link packet and the retransmitted sequential data link packets in response to receiving the error-free version of the erroneous data link packet and the retransmitted sequential data link packets received after the error-free version of the erroneous data link packet. The computer-implemented method may include periodically determining an adaptive threshold from a plurality of maximum fill levels based on a set of link operating parameters, wherein the replay buffer memory has a buffer size corresponding to a total number of data link packets that can be stored in the replay buffer memory at one time, the fill level corresponding to a current number of data link packets stored in the replay buffer memory for pending selective replay requests, and the adaptive threshold corresponding to a maximum fill level that is less than the buffer size of the replay buffer memory.The computer-implemented method may include determining that a flow control mode is active, where the peripheral interface protocol supports a flow control mode configured to change a memory size and format of data link packets; determining a fill level of a replay buffer memory based on the memory size and format of data link packets in the flow control mode; and dynamically determining an adaptive threshold based on the flow control mode. The computer-implemented method may include recalculating the adaptive threshold based on a current set of link operational parameters in response to each detection of an erroneous data link packet to dynamically determine the adaptive threshold for the erroneous data link packet. The computer-implemented method may include processing the set of link operational parameters through a statistical model consisting of the set of link operational parameters and corresponding weighting factors configured to balance the likelihood of successfully recovering the erroneous data link packet against data link layer latency. The set of link operational parameters may include at least one link connection parameter selected from a current link speed, a number of lanes, and a bit error rate for the current link speed and number of lanes. The set of link operational parameters may include at least one link workload parameter selected from a current data link packet workload amount, a host system historical workload amount, and a predicted workload amount. The peripheral interface protocol may support a skip ordered set mode configured to periodically resynchronize the data link layer by introducing idle time between fixed periods of transaction layer packet processing, and the link set of operational parameters may include a counter for the fixed periods of transaction layer packet processing, and dynamically determining the adaptive threshold in response to the skip ordered set mode includes compensating for the predicted idle time based on the counter.

[0009] Yet another general aspect includes a peripheral interface circuit including a data link layer configured to receive data link packets from a host system; a replay buffer memory configured to store received data link packets following an erroneous packet to support a selective replay mode; means for determining errors in the data link packets received from the host system; means for dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operational parameters; means for selecting a replay mode selected from a selective replay mode for requesting retransmission of only the erroneous data link packet based on comparing a fill level of the replay buffer memory to the adaptive threshold; and a sequential replay mode for requesting retransmission of the erroneous data link packet and any subsequent data link packets transmitted after the erroneous data link packet; and means for transmitting a replay request to the host system based on the selected replay mode.

[0010] Various embodiments advantageously apply the teachings of peripheral bus interfaces for computer peripherals to improve the functionality of computer systems that include those peripheral devices. Various embodiments overcome or at least reduce problems previously encountered in computer systems that use peripheral interfaces, and therefore include operation that is more reliable and / or efficient than other computing systems. That is, various embodiments disclosed herein include hardware and / or software capable of improving the link latency and reliability of peripheral interfaces, such as by selecting between selective and sequential replay modes using adaptive thresholds based on link operating parameters. Accordingly, the embodiments disclosed herein provide various improvements to storage networks and / or storage systems.

[0011] It should be understood that the language used in this disclosure has been chosen primarily for readability and instructional purposes, and is not intended to limit the scope of the subject matter disclosed herein. [Brief explanation of the drawings]

[0012] [Figure 1] 1 illustrates a schematic diagram of a system for data storage and communication using a peripheral interface with an adaptive replay mode selector at the data link layer. [Figure 2] 1 illustrates a schematic diagram of a system for data communications focusing on transmit and receive components of a data link layer that supports adaptive replay mode selection. [Figure 3] 1 illustrates a schematic diagram of a data link layer receiver circuit for managing data packet replay in a peripheral interface of a computing device. [Figure 4] 1 is a flowchart of an exemplary method for dynamically selecting a replay mode at a data link layer of a receiver in a PCIe system. [Figure 5] 1 is a flowchart of an exemplary method for handling packet replay at a data link layer of a transmitter in a PCIe system. [Figure 6] 1 is a flowchart of an example method for determining parameters related to a replay buffer in a peripheral interface of a computing device based on a flow control mode. [Figure 7] 10 is a flowchart of an example method for adjusting an adaptive threshold for a packet replay mode based on a skip ordered set mode. [Figure 8] 1 is a flowchart of an example method for determining an adaptive threshold for packet replay in a peripheral interface of a computing device. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present disclosure relates to an adaptive replay system for peripheral interfaces. In some examples, the adaptive replay system may dynamically select between selective and sequential replay modes to handle packet errors in data link layer communications. The adaptive replay system may utilize a set of link operational parameters to determine an adaptive threshold for selecting the appropriate replay mode.

[0014] The peripheral interface can connect the device to a host system using a peripheral interface protocol. The peripheral interface protocol can include a data link layer configured to transmit and receive data link packets. The replay buffer memory can be implemented to support a selective replay mode to store received data link packets following an erroneous packet.

[0015] The replay logic can be configured to determine errors in data link packets received via the peripheral interface. The replay logic can dynamically determine an adaptive threshold for selecting a replay mode based on a set of link operational parameters. For example, the link operational parameters can include a current link speed, a number of lanes, a bit error rate, a current workload, and historical behavior of the host system.

[0016] The replay logic can select a replay mode by comparing the fill level of the replay buffer memory with an adaptive threshold, and the replay modes can include a selective replay mode for requesting retransmission of only the erroneous data link packet and a sequential replay mode for requesting retransmission of the erroneous data link packet and any subsequent data link packets transmitted after the erroneous data link packet.

[0017] The adaptive replay system can periodically recalculate the adaptive thresholds based on current link operating parameters. This dynamic approach can allow the system to adapt to changing conditions and error patterns, potentially improving overall system performance and reliability. Peripheral interface protocols can support additional features that can affect adaptive threshold determination. For example, flow control modes can be supported that can vary the memory size and format of data link packets, and / or skip ordered set modes can be supported that can define processing periods and scheduled idle periods to support data link layer resynchronization. The replay logic can adjust its calculations based on the active flow control mode and / or skip ordered set mode.

[0018] The adaptive replay system can be implemented in a variety of devices that utilize a peripheral interface. For example, the system may be embedded in a data storage device, network interface card, or other computer peripheral that communicates with a host system using a peripheral interface protocol such as PCIe.

[0019] FIG. 1 illustrates an embodiment of an exemplary data storage system 100 having multiple data storage devices 120 interconnected by a peripheral interface bus 108. While certain exemplary features are shown, various other features are not shown for the sake of brevity and to avoid obscuring relevant aspects of the exemplary embodiments disclosed herein. To that end, by way of non-limiting example, the data storage system 100 includes one or more data storage devices 120 (also sometimes referred to as information storage devices, storage devices, disk drives, or drives). In some embodiments, the storage devices 120 may be configured in server or storage array blades or similar storage units for use in a data center storage rack or chassis. The storage devices 120 may interface with one or more hosts 102 and provide data storage and retrieval capabilities for or through those host systems. In some embodiments, the storage devices 120 may be configured in a storage hierarchy that includes storage nodes, storage controllers, and / or other intermediate components between the storage devices 120 and the hosts 102. For example, each storage device may include a peripheral interface circuit and corresponding peripheral interface connector for connecting to the peripheral interface bus 108, and one or more intermediate systems or components may act as host systems and / or root complexes for peripheral interface bus communications.

[0020] In the illustrated embodiment, several storage devices 120 are attached to a common peripheral interface bus 108 for host communication. For example, the storage devices 120 may include several drives arranged in a storage array, such as storage devices sharing a common rack, unit, or blade in a data center, or solid-state drives (SSDs) in an all-flash array. In some embodiments, the storage devices 120 may share a backplane network, a network switch, and / or other hardware and software components accessed via the peripheral interface bus 108. For example, the storage devices 120 may connect to the peripheral interface bus 108 through multiple physical port connections that define physical channels, link channels, and other logical channels for establishing communication with different components and subcomponents to establish communication channels to the host 102. In some embodiments, the peripheral interface bus 108 may be configured as a storage interface bus and may provide the primary host interface for storage device management and host data transfer.

[0021] In some embodiments, storage devices 120 may be configured for peer communication between themselves via the peripheral interface bus 108, with or without the assistance of the host 102. For example, storage devices 120 may be configured for direct memory access using one or more protocols, such as non-volatile memory express (NVMe), remote direct memory access (RDMA), NVMe over fabric (NVMeoF), etc., to provide command messaging and data transfer between storage devices using a high-bandwidth storage interface and the storage interface bus 108. In these cases, storage devices 120 may be configured to act as both an initiator device and an endpoint device for peripheral interface communications, allowing one storage device to act as a host system to initiate communications with another storage device via the peripheral interface bus 108.

[0022] In some embodiments, data storage devices 120 are or include solid-state drives (SSDs). Each data storage device 120.1-120.n may include a non-volatile memory (NVM) or device controller 130 based on computational resources (processors and memory) and multiple NVM or media devices 140 (e.g., one or more NVM devices, such as one or more flash memory devices) for data storage. In some embodiments, individual data storage devices 120 of one or more data storage devices include one or more NVM controllers, such as a flash controller or channel controller (e.g., for a storage device having NVM devices in multiple memory channels). In some embodiments, data storage devices 120 may each be packaged within a housing, such as a multi-part sealed housing, having a defined form factor and ports and / or connectors for interconnecting with peripheral interface bus 108.

[0023] In some embodiments, an individual data storage device 120 can include a single media device, while in other embodiments, an individual data storage device 120 includes multiple media devices that provide non-volatile storage media for storing host data. In some embodiments, the media device includes NAND flash memory or NOR flash memory. In some embodiments, data storage device 120 may include one or more hard disk drives (HDDs). In some embodiments, data storage device 120 can include a flash memory device, which includes one or more flash memory dies, one or more flash memory packages, one or more flash memory channels, etc. However, in some embodiments, one or more of data storage devices 120 may have other types of non-volatile data storage media (e.g., phase change random access memory (PCRAM), resistive random access memory (ReRAM), spin transfer torque random access memory (STT-RAM), magnetoresistive random access memory (MRAM), etc.).

[0024] In some embodiments, each storage device 120 includes a device controller 130 that includes one or more processing units (sometimes referred to as a CPU or processor or microprocessor or microcontroller) configured to execute instructions in one or more programs. In some embodiments, the one or more processors are shared by one or more components within, and possibly beyond, the device controller's functionality. Media device 140 is typically coupled to device controller 130 via a connection that communicates commands in addition to data, and optionally communicates metadata, error correction information, and / or other information in addition to data values ​​stored in and read from media device 140. Media device 140 may include any number (i.e., one or more) memory devices, including, but not limited to, non-volatile semiconductor memory devices such as flash memory devices.

[0025] In some embodiments, media device 140 in storage device 120 is divided into several addressable, individually selectable blocks, sometimes called erase blocks. In some embodiments, an individually selectable block is the smallest-sized erasable unit in a flash memory device. In other words, each block contains the smallest number of memory cells that can be erased simultaneously (i.e., in a single erase operation). Each block is usually further divided into multiple pages and / or wordlines, with each page or wordline typically being the smallest individually accessible (readable) instance within a block. In some embodiments (e.g., using some types of flash memory), however, the smallest individually accessible unit of a data set is a sector or codeword, which is a subunit of a page. That is, a block contains multiple pages, each page contains multiple sectors or codewords, and each sector or codeword is the smallest unit of data for reading data from a flash memory device.

[0026] A data unit can describe any size allocation of data, such as a host block, data object, sector, page, multi-plane page, erase / programming block, media device / package, etc. A storage location can include a physical and / or logical location on the storage device 120 and can be described and / or assigned at different levels of granularity depending on the storage medium, storage device / system configuration, and / or context. For example, a storage location may be assigned with a host logical block address (LBA) data unit size and addressability for host read / write purposes, but in other contexts may be managed as a page with storage device addressing managed in a media flash translation layer (FTL). A media segment can include a physical storage location on the storage device 120, and a physical storage location can also correspond to one or more logical storage locations. In some embodiments, a media segment can include a contiguous series of physical storage locations, such as contiguous data units on a storage medium, and in the case of a flash memory device, can correspond to one or more media erase or programming blocks. A logical data group can include multiple logical data units, which can be grouped on a logical basis regardless of storage location, such as a data object, file, or other logical data structure composed of multiple host blocks.

[0027] A host system 102, or an individual host in a system having multiple hosts, may be any suitable computing device, such as a computer, a computer server, a laptop computer, a tablet device, a netbook, an Internet kiosk, a personal digital assistant, a mobile phone, a smartphone, a gaming device, or any other computing device. A host system 102 may also be referred to as a host, a client, or a client system. In some embodiments, a host system 102 is a server system, such as a server system in a data center, or a storage system, such as a storage array in a data center. In some embodiments, one or more host systems 102 are one or more host devices distinct from a storage controller or storage node that houses multiple storage devices 120. One or more host systems 102 may be configured to store and access data on multiple storage devices 120.

[0028] Host system 102 may include one or more central processing units (CPUs) 104 for executing computational operations or instructions to access storage device 120 via peripheral interface bus 108. In some embodiments, CPU 104 may include a host processor and may be associated with operating memory 106 for executing both storage operations and a storage interface protocol compatible with peripheral interface bus 108 and storage device 120. In some embodiments, memory 106 may include one or more dynamic random access memory (DRAM) devices used by storage device 120 for storage and transfer of commands, control parameters, and / or host data. In some embodiments, storage device 120 may be configured for direct memory access (DMA), such as using a remote direct memory access (RDMA) protocol, via peripheral interface bus 108 to access and use host memory buffers allocated for that storage device. Memory 106 may also include an operating system (not shown), firmware, and / or software applications for performing various functions of host system 102. In some configurations, memory 106 may include a host basic input / output system (BIOS) 106.1 for establishing basic communications between components of host system 102 during boot-up. In some embodiments, host BIOS 106.1 may be configured to establish communications to storage device 120 via peripheral interface bus 108 during boot-up.

[0029] In some configurations, the peripheral interface bus 108 may interface with a common bus shared by other components of the host system 102, such as the CPU 104 and memory 106. In other configurations, the host system 102 may include an interface port for connecting to the peripheral interface bus 108. For example, the host system 102 may include a peripheral bus interface 108.1 for physically connecting to the peripheral interface bus 108. The host 102, the peripheral interface bus 108, and / or the storage interface unit may include a root complex 110 for a peripheral interface protocol that manages connections and communications over the peripheral interface bus 108 using a peripheral interface switch 112. For example, the root complex 110 may be configured as a PCIe root complex that connects the CPU and memory subsystem to a PCIe switch fabric comprised of various endpoints that may include storage devices 120, the host system 102, and other devices connected to the peripheral interface bus 108. In some embodiments, the host system 102 may provide processor and memory resources to support the root complex 110. From the perspective of the storage device 120, the peripheral interface bus 108, sometimes referred to as the host interface bus, provides a host data path between the storage device 120 and the host 102, as well as other endpoints that can function as a host system to initiate communications over the peripheral interface bus 108.

[0030] The system 100 may include a peripheral interface protocol 150 configured to connect the peripheral interface bus 108 and various endpoints connected to the peripheral interface bus 108, such as the host 102 and the storage devices 120, for storage communications. The peripheral interface protocol 150 may be based on a transaction layer 152, a data link layer 154, and a physical layer 156. The transaction layer 152 may be responsible for processing higher-level protocol operations, such as read and write requests, and may manage the flow of transaction layer packets (TLPs) between the host 102 and the storage devices 120.1, 120.2, 120.n. The transaction layer 152 may handle TLP formation, routing, ordering, and flow control. The data link layer 154 may be responsible for reliable data transfer for the transaction layer 152 via the physical layer 156. For example, the data link layer 154 may map the contents of a transaction layer packet to a data link packet for transmission via the physical layer 156. The data link layer 154 may incorporate a replay mode selector 154.1 that can be configured to dynamically select between different replay modes for handling packet errors. The data link layer 154 manages data link packets (DLLPs) and may implement error detection and correction mechanisms to ensure accurate transfer of transaction layer data between the sender and receiver of the data link layer 154 at corresponding endpoints. The physical layer 156 may be responsible for the actual transmission and reception of data over the physical media of the peripheral interface bus 108. In some cases, the physical layer 156 may include a peripheral interface connector 156.1 for each endpoint that connects to the peripheral interface bus 108 and the conductors and switches therein. The physical layer 156 may handle tasks such as signal coding, timing, and electrical specifications for data transmission.

[0031] In some embodiments, data storage system 100 includes one or more processors, one or more types of memory, a display, and / or other user interface components such as a keyboard, a touchscreen display, a mouse, a trackpad, and / or any number of supplemental devices for adding functionality. In some embodiments, data storage system 100 does not have a display or other user interface components.

[0032] Referring to FIG. 2, a block diagram of a system 200 for data communications is shown, focusing particularly on the data link layer of a peripheral interface protocol. System 200 can include a transaction layer 206, a data link layer transmit circuit 202, a data link layer receive circuit 204, and a physical layer 208. Devices that implement a peripheral interface protocol, such as PCIe endpoints, can include both a transmit component and a receive component, although any given transaction is between the transmit portion of one device and the receive portion of another device. Additionally, more complex peripheral interface bus connections can include intervening components, such as switches and corresponding route complexes, to route packets between multiple endpoints.

[0033] The data link layer transmit circuit 202 may process transaction layer content 214, including transaction layer packet (TLP) information 216, received from the transaction layer 206. For example, the transaction layer 206 may determine the transaction layer packet for the destination endpoint and generate corresponding transmit data 212 (TLP packet payload) and packet information 210 (TLP packet header and parameters for TLP packet processing). In some configurations, the peripheral interface protocol may implement a flow control mode, such as FLIT in PCIe. For example, the transaction layer content 214 may be formatted as 236 bytes of TLP information 216. Note that data link packets may not have a one-to-one mapping with transaction layer packets, and more or less transaction layer packets may fit in a data link packet depending on the relative size and consistency of the transaction layer packet versus the data link packet. The data link layer may be based on transmitting sequential data link packets for transaction layer content 214 over physical layer 208 and receiving and reassembling the sequential data link packets at data link layer receive 204 to return corresponding transaction layer content 252 to transaction layer 206 at the receiving device. Transaction layer content 214 may then be processed through data link packet (DLP) formatter 218 to wrap TLP information 216 for transmission according to a link layer protocol. For example, DLP formatter 218 may add a DLP header and error checking data to TLP information 216 to obtain data link packet 220. In some configurations, data link packet 220 may include an additional 6-byte DLP parameter 222, such as a 2-byte DLP header and a 4-byte cyclic redundancy check code (CRC) for a 242-byte DLP or FLIT packet. The DLP 220 is passed to a physical layer transmitter 224 and sent over a peripheral interface bus to the destination endpoint (through whatever switches and route complexes may be needed to get there).

[0034] In some protocols, the data link layer may generate additional packets to maintain reliable link communications, such as acknowledgments and replay requests, as well as flow control and power management messages. These management packets for the data link layer are sometimes referred to as data link layer packets (DLLPs) 226. DLLPs 226 may include DLP parameter data 228, such as message type and information. These DLPs 226 may also receive DLP parameters 222 (header and CRC) from the DLP formatter 218 before being transmitted via the physical layer transmitter 224. DLPs 226 containing flow control information may receive their flow control information 238 from a corresponding data link layer receiver 204, which may include a receiver at the destination endpoint and / or an intermediate receiver such as a switch.

[0035] In some configurations, the data link layer transmit circuit 202 may include a transmit replay or retry buffer 232 for storing data that may require retransmission. The transmit retry buffer 232 may be configured to store a variable number of transaction layer packets for replay in response to a replay request from the data link layer receive circuit 204, depending on current operating conditions and protocol settings. In some configurations, the transmit retry buffer 232 may be sized and managed to store all transaction layer packet information 216 for TLPs that have been transmitted but not acknowledged via the corresponding DLLP. The data link layer transmit circuit 202 may use a multiplexer 230 with path selection logic to select between new TLPs received from the transaction layer 206 and replays of TLPs from the transmit retry buffer 232. For example, the multiplexer 230 may select replay packets from the transmit retry buffer 232 in a first-in, first-out (FIFO) selection when a replay request is pending to help clear old TLPs from the transmit replay buffer 232. In some configurations, the storage interface protocol may also support no-operation (NOP) data packets from transaction layer 206 as no-operation data content 234 and corresponding TLP information 236. These TLPs may be treated similarly to normal TLPs, but may be given different priorities via multiplexer 230. In some instances, NOP data packets may be sent when no other packets are available to be sent to help maintain link connectivity and operating parameters.

[0036] On the receive side, the data link layer receive circuit 204 can process incoming data link packets 242 received via the physical layer receiver 240 from a transmitter in another device, such as a host system or another endpoint. The data link packets 242 can include TLP information 216 and DLP parameters 222 corresponding to the TLP information 244 and DLP parameters 246 transmitted by the transmit side and can be subject to any transmission-induced errors. The DLP processor 248 can analyze the DLP 242 and use the DLP parameters 246 for packet identification and error detection. For example, the DLP header can identify the DLP packet and its contents, and the CRC can be used to determine whether one or more errors exist in the data link packet. Data link packets that do not contain errors can have the DLP parameters removed and be stored in the receive replay or retry buffer 250. For example, TLP or FLIT data corresponding to the original 236 bytes in the transaction layer content 214 and TLP information 216 can be stored in the receive retry buffer 250 as a corresponding DLP unit. An erroneous data link packet can generate a replay request that is sent back to the transmitter in the DLLP. The replay mode selector 260 can dynamically and adaptively select whether selective replay mode or sequential replay mode is used for the replay request, as further described with respect to FIG. 3. The erroneous data link packet may be discarded, and the handling of previous and / or subsequent sequential packets associated with the same TLP may be determined by the selected replay mode.

[0037] Error-free packets are received and aggregated in receive retry buffer 250. Transaction layer content 252 corresponding to TLP information 244 may be reassembled into a TLP and returned to transaction layer 206 as received data 254 (transaction packet payload) and packet information (transaction packet parameters) for further processing. When a TLP is completed and returned to transaction layer 206, an acknowledgment for that TLP may be sent to the transmitter using a DLLP, enabling both data link transmit circuitry 202 and data link layer receive circuitry 204 to clear the corresponding transaction layer content from their respective transmit retry buffers 232 and receive retry buffers 250. DLP processor 248 may also update flow control information 238 and send a corresponding flow control DLLP to the transmitter.

[0038] FIG. 3 schematically illustrates selected modules of a data link layer receive circuit 300 configured to dynamically adjust an adaptive threshold for selecting between replay modes. For example, the data link layer receive circuit 300 may embody some of the data link layer functions described with respect to FIGS. 1 and 2 for a peripheral interface, such as a PCIe interface through which a data storage device communicates with a host system. An endpoint device including the receive circuit 300 may include other elements from FIGS. 1 and 2 to support broader functionality for transmitting, receiving, and managing flow control and other features of the peripheral interface and the peripheral interface protocol it implements. For example, the receive circuit 300 may also include components such as an interface to a physical layer receiver, a DLP processor, TLP logic for reassembling TLP packets from error-free data link packets in the receive replay buffer 350 or another receive buffer, flow control logic, and connections to transmit circuitry components such as a DLP generator for transmitting replay requests and acknowledgments.

[0039] The receiving circuit 300 may include a bus 310 interconnecting at least one processor 312, at least one memory 314, and other components of the receiving circuit 300. The bus 310 may include one or more conductors that enable communication between components of the receiving circuit 300 and / or other components of a peripheral interface. The processor 312 may include any type of processor or microprocessor that interprets and executes instructions or operations, and may include multiple processors or processor cores configured to operate alone or in combination. The memory 314 may include random access memory (RAM) or another type of dynamic storage device that stores information and instructions for execution by the processor 312, and / or read-only memory (ROM) or another type of static storage device that stores static information and instructions for use by the processor 312. The memory 314 may include one or more memory devices, and may include memory devices of different types and configurations. In some configurations, some or all of the other components in the receiving circuit 300 may be instantiated within the memory 314 for execution by the processor 312. For example, parameter registers 360 and replay buffer 350 may be embodied in data structures allocated in memory 314, and replay logic 320 and data link state machine 380 may be instantiated by sets of instructions and data structures in memory 314 that are executed by processor 312 to perform the described functions. In some configurations, one or more components may be instantiated in hardware circuits that have their own logic and memory circuits for performing the described functions, and processor 312 and memory 314 may provide coordination and management of the functions performed by those hardware circuits via bus 310.

[0040] The receive circuit 300 may include a replay logic circuit 320, which comprises logic for processing errors detected in received data link packets, managing the capacity of the replay buffer 350, and dynamically selecting between replay modes depending on detected packet errors. The replay logic circuit 320 may include an error detector 322 for identifying errors in received data packets. For example, the error detector 322 may extract a CRC value from each DLP and perform a CRC check on the received DLP to determine whether errors caused by transmission are present in the DLP. The error detector 322 may include CRC processing logic that determines, based on the payload size (FLIT data) and the CRC code added by the transmitter, whether a packet contains an error and requires replay to successfully return the TLP data in that DLP.

[0041] The receive circuit 300 may include a replay mode selector 324 within the replay logic 320 configured to determine whether to use sequential replay mode 326 or selective replay mode 328 based on various factors. In some configurations, the receive circuit may include a static threshold for selecting between sequential replay mode 326 and selective replay mode 328. For example, the receive circuit 300 may default to selective replay mode 326 until the fill level of the replay buffer 350 meets a static threshold for triggering sequential replay mode 328. While using a static threshold may allow the receiver to utilize both modes, it does not optimize their use due to the dynamic nature of data link connections and changing workloads of peripheral interfaces. Therefore, the replay mode selector 324 may be configured with a dynamic model for determining adaptive thresholds that adjust periodically based on a set of link operating parameters. For example, the statistics engine 330 may implement one or more statistical models for varying adaptive thresholds in response to changing link operating conditions and current and / or predicted workloads. In some configurations, the statistics engine 330 may calculate a new adaptive threshold each time an erroneous packet is detected by the error detector 322. The replay logic 320 may recalculate the adaptive threshold 330.1 based on the current set of link operating parameters to dynamically determine the adaptive threshold for each erroneous data link packet. For example, whenever the error detector 322 identifies a packet error, the statistics engine 330 may analyze the current link speed 364, number of lanes 366, bit error rate 368, and other relevant parameters to recalculate the appropriate adaptive threshold 330.1 for that particular error instance. In other configurations, threshold adaptation may be triggered based on a periodic schedule, such as time, number of packets, skip ordered set (SKPOS) resynchronization, or another operating period. Other trigger conditions are also possible, such as based on a bit error rate (BER) threshold, a link speed change threshold, etc.

[0042] The sequential replay mode 326 may include a conventional link replay mode configured to resume the sequence of DLPs for current and future TLPs without storing TLP data from error-free DLPs in sequence in the replay buffer 350. This mode may be used when the replay buffer 350 is full or otherwise unavailable, and may be selectively used to allow clearing of previous packet errors already requested using the selective replay mode 328. The sequential replay mode may be triggered in response to an error detection by the error detector 322, such as when a packet is received that fails an integrity check using an error detection mechanism such as a CRC. An error notification may be provided to the transmitter by sending a replay request indicating that the entire TLP (which may include multiple DLPs) should be retransmitted. Upon receiving the replay request, the transmitting device may find the TLP in its transmit replay buffer and generate a DLP to retransmit the TLP sequence. When the receiving device receives the erroneous packet (and any other retransmitted DLPs to complete the TLP), the TLPs may be reassembled and returned to the transaction layer, while an acknowledgment is sent by the receiver to the transmitter.

[0043] Selective replay mode 328 can include selective replay of only erroneous DLPs to avoid retransmission of other DLPs in a TLP sequence. Selective replay mode can be based on storing error-free DLPs in replay buffer 350 to enable selection and rearrangement of DLPs to complete a TLP. Selective replay mode 328 can be initiated based on selection by error detector 322 and replay mode selector 324. A replay request sent to the transmitter can indicate selective replay mode and identify the erroneous DLP packet. The transmitting device retransmits only the requested packet. Receive circuit 300 continues to receive and process good packets received after the erroneous packet in the sequence of DLPs (and the corresponding sequence of TLPs). Selective replay mode 328 reorders and uses replay buffer 350 as a buffer to store good packets until the erroneous packet is retransmitted by the transmitter and received without error. The receiving device acknowledges the resulting completion of the retransmitted packet and / or TLP passed up to the transaction layer.

[0044] The statistical engine 330 within the replay logic 320 may be configured with one or more statistical models for determining an adaptive threshold 330.1. The adaptive threshold 330.1 may include a threshold that, when met, triggers a change in replay mode from selective replay mode 328 to sequential replay mode 326, and may trigger a return to selective replay mode when the threshold is no longer met. For example, the adaptive threshold 330.1 may correspond to a fill level of the replay buffer 350, more specifically, a maximum fill level, above which sequential replay mode is selected to reduce pressure on the replay buffer 350. The adaptive threshold 330.1 may vary between a range of maximum fill level values ​​that are less than the total capacity of the replay buffer 350. The adaptive threshold 330.1 may correspond to a maximum fill level that is less than the buffer size of the replay buffer memory 350. For example, for a given period of operation, adaptive threshold 330.1 may be set to 80% of total buffer size 362 and then adapt to allow for variable amounts of buffer headroom as link operating parameters change. In some configurations, fill level and adaptive threshold 330.1 may be incremented in steps corresponding to the packet size of error-free packets held in replay buffer 350. For example, FLIT size may be used and number of packets may be used to represent capacity, fill level, and / or adaptive threshold 330.1.

[0045] The statistical model used by the statistics engine 330 can be based on a set of link operational parameters 330.2. For example, the statistics engine 330 may be configured for a set of link operational parameters representing link conditions and workload, which may be correlated to determine that thresholds should be adapted to changing conditions. In some configurations, the statistics engine 330 can determine, request, or access operational parameter values ​​for the operational parameters 330.2 from parameter registers 360. The parameter registers 360 may include a combination of link connection parameters, such as current link speed 364, number of lanes 366, and bit error rate 368, and link workload parameters, such as current workload 370 and host workload history 372. In a simple statistical model, each selected operational parameter may be included as a term in the model, and each term may include an associated operator and weighting coefficient 330.3 to represent the relationships and trade-offs between the different parameters. In some configurations, the statistics engine 330 may be configured to balance a completion target 330.4 for determining the likelihood that an erroneous packet (and / or the TLP or TLP sequence it contributes to) will be successfully replayed and received without error with a latency target 330.5 for determining a change in data link layer latency based on a change in replay mode. In some configurations, the completion target 330.4 may be based on a completion risk threshold, such as a 90% chance of recovering the erroneous packet on the next attempt, and the latency target 330.5 may be based on an acceptable latency change threshold, such as a 5% increase in link latency. FLIT compensation 330.6 may include factors within the statistical model or logic within the statistics engine 330 that are responsive to enabling flow control modes and concomitant changes in packet size and format and their impact on the replay buffer 350, as well as reordering or completion logic for the corresponding TLP.SKPOS Compensation 330.7 may include factors in the statistical models or logic in the Statistics Engine 330 responsive to enabling Skip Ordered Set mode and associated processing periods and idle times to provide predictable interruptions in DLP packet processing and support catch-up on error backlogs. Statistics Engine 330 may be configured to compensate for any number or combination of operating parameters and / or operating modes that affect link operation.

[0046] The replay logic 320 may include a replay request interface 332 for initiating packet retransmission via a replay request to the transmitting device, such as initiating a DLP message identifying the erroneous packet and the requested replay mode. The replay logic 320 may include reorder logic 334 for reassembling DLP and TLP sequences in response to error-free packets stored in the replay buffer 350 and / or received in response to the replay request, and returning completed TLPs to the transaction layer in response to error-free versions of the erroneous packets that were the subject of the replay request. The replay logic 320 may include an acknowledgement interface 336 for confirming successful transmission, such as initiating a DLP message indicating that a DLP packet was received without error and / or that a TLP completed without error. The replay logic 320 may include a buffer monitor 338 for tracking the status of the replay buffer 350 and, more specifically, for determining the current fill level based on the error-free packets stored in the replay buffer 350 awaiting completion of their sequences and return of the corresponding TLPs to the transaction layer. The replay logic 320 may be configured to select a replay mode based on comparing the fill level of the replay buffer memory 350 to an adaptive threshold. For example, the buffer monitor 338 may track the current fill level of the replay buffer 350, and the replay mode selector 324 may compare this fill level to an adaptive threshold 330.1 to determine whether to use sequential replay mode 326 or selective replay mode 328.

[0047] Replay buffer memory 350 may include one or more memory devices configured to store data link packets 352.1, 352.2, 352.3, through 352.n. Replay buffer memory 350 may be configured as a FIFO buffer with a total capacity based on the allocated device memory size and the packet size of packets 352. In some configurations, replay buffer 350 may be indexed to enable packet reordering based on the intended sequential order (as determined at the transmitter), which may be expressed in a header parameter of the DLP and / or TLP mapping data. Replay buffer memory 350 may be configured to store error-free received data link layer packets following an erroneous packet to support selective replay mode and sequential packet reassembly when an erroneous, corrected packet is received. In some configurations, replay buffer memory 350 may have a buffer size corresponding to the total number of data link packets that can be stored in replay buffer memory 350 at one time. For example, buffer size 362 stored in parameter register 360 may indicate the maximum capacity of replay buffer memory 350. The fill level of replay buffer memory 350 may correspond to the current number of data link packets stored in replay buffer memory 350 due to pending selective replay requests. Buffer monitor 338 may track this fill level in real time as packets are added to and removed from replay buffer memory 350.

[0048] Parameter registers 360 may include one or more memory devices configured to store various link operational parameters. Exemplary link operational parameters that may be included in parameter registers 360 include replay buffer size 362, current link speed 364, number of lanes 366, BER 368 (for the current link speed and number of lanes), current data link packet workload 370, host system history 372 (historical workload for a particular host system / transmitter), FLIT mode indicator 374, and SKPOS counter 376. Some or all of these parameters may be used by replay logic 320 to determine adaptive threshold 330.1 and dynamically select between replay modes. For example, statistics engine 330 may model link latency and error probability using a set of link operational parameters including link connection parameters selected from link speed 364, lanes 366, and BER 368. In another example, statistics engine 330 may use a set of link operational parameters including workload 370, link workload parameters selected from host history 372, and / or a predicted workload amount based on the current workload, host history, and a predictive model that extrapolates changes in the current workload over future periods. In some configurations, one or more of the parameter values ​​in parameter registers 360 may be determined by data link state machine 380. For example, data link state machine 380 may monitor link speed 364, lane attachment 366, BER 368, current workload, and various modes (including FLIT and SKPOS modes) to maintain link operation at a desired performance level. In some configurations, parameter registers 360 may include a set of memory registers associated with data link state machine 380 and / or other functions within or connected to receive circuit 300 that may be updated and accessed to provide the current value of each parameter.

[0049] In some configurations, the replay logic 320 may be configured to determine when a flow control mode is active. For example, the FLIT mode 374 parameter in the parameter register 360 may indicate whether a flow control mode such as FLIT (flow control unit) is currently in use. When FLIT mode is active, the replay logic 320 may adjust its calculations and decision-making processes to account for the different packet sizes and formats used in FLIT mode. The statistics engine 330 may use various compensation mechanisms to fine-tune the adaptive threshold 330.1. For example, the FLIT compensation 330.6 may adjust its calculations to account for the specific characteristics of FLIT mode when it is active.

[0050] Similarly, SKPOS compensation 330.7 can modify the threshold based on the frequency and timing of Skip Ordered Sets indicated by SKPOS counter 376. Replay mode selector 324 can consider the SKPOS time window or distance from the current packet processing window. In some configurations, SKP OSs are periodic markers inserted into the data stream to maintain synchronization between the transmitter and receiver, introducing idle time to allow for data link layer resynchronization. Parameter register 360 can include SKPOS counter 376 to track the timing and frequency of these SKP OS occurrences. SKPOS counter 376 can provide information about the timing of Skip Ordered Sets, which can affect packet transmission patterns. Replay mode selector 324 can use this information to adjust its replay mode selection strategy. SKPOS compensation 330.7 can use the value from SKPOS counter 376 to adjust adaptive threshold 330.1 or to influence replay mode selection. For example, if the SKPOS counter 376 indicates that a SKP OS is imminent, the replay logic 320 can adjust its decision-making process to avoid initiating a sequential replay operation that may conflict with the next SKP OS. If a packet error occurs near the next SKP OS window, the replay mode selector 324 can increase the adaptive threshold 330.1 and rely on the idle time provided by the SKP OS resynchronization to receive a packet retransmission before the next processing window begins, rather than aborting sequential replay.

[0051] 4 shows a flowchart of a method 400 for dynamically selecting a replay mode in a PCIe system. Method 400 may be performed by a receiving circuit in a data storage device or other peripheral device connected to a host system via a PCIe interface. Method 400 may provide efficient handling of packet errors while optimizing buffer usage and system performance. In general, method 400 may dynamically select between selective replay mode and sequential replay mode based on a replay buffer fill level and an adaptive threshold.

[0052] A packet may be received from a transmitter at block 410. For example, the receiving circuit may accept a data link packet from a host system via a PCIe interface.

[0053] Errors in the received packet may be determined at block 412. For example, the receiving circuitry may perform a cyclic redundancy check on the received packet to detect any transmission errors.

[0054] An adaptive threshold may be determined at block 414. For example, the receive circuitry may calculate the threshold based on current link operating parameters such as link speed, number of lanes, and bit error rate.

[0055] The fill level of the replay buffer may be determined at block 416. For example, the receiving circuit may check the memory allocation in its replay buffer memory used to store good packets awaiting replay of erroneous packets during selective replay.

[0056] A determination may be made based on whether the fill level meets a threshold at block 418. For example, the receiving circuit may compare the current replay buffer fill level to the calculated adaptive threshold.

[0057] If the fill level does not meet the threshold, selective replay mode may be selected at block 420. For example, the receiving circuit may choose to use selective replay if sufficient buffer space is available.

[0058] A replay request for the erroneous packet may be sent in block 422. For example, the receiving circuitry may send a Data Link Layer Packet (DLLP) to the host system requesting retransmission of the particular erroneous packet and specifying a selective replay mode.

[0059] Sequential packets may be stored in a replay buffer at block 424. For example, the receive circuitry may continue to accept and buffer subsequent error-free packets while waiting for retransmission of the erroneous packet.

[0060] The replay packet may be received without error at block 426. For example, the receiving circuitry may accept the retransmitted packet from the host system and verify its integrity to confirm an error-free version.

[0061] The transaction layer content from the replay packets and stored packets may be sent to the transaction layer at block 428. For example, the receiving circuitry may forward one or more transaction layer packets corresponding to the corrected packet sequence, including error-free versions of the erroneous packets, to a higher protocol layer for further processing.

[0062] At block 430, the transmitted packets may be cleared from the replay buffer. For example, the receiving circuitry may remove successfully processed packets from the buffer to free up space.

[0063] Sequential replay mode may be selected if the fill level meets a threshold, which may include equaling or exceeding an adaptive threshold, at block 440. For example, the receiving circuit may choose to use sequential replay if buffer space is limited and operating conditions suggest that selective replay is unlikely to be successful or more efficient.

[0064] A replay request for the erroneous packet may be sent at block 442. For example, the receiving circuitry may send a DLLP to the host system requesting a retransmission starting with the erroneous packet.

[0065] Successive packets after the error may be discarded at block 444. For example, the receiving circuitry may ignore any subsequent packets received after detecting the error.

[0066] The replay packet may be received without error at block 446. For example, the receiving circuitry may accept the retransmitted packet from the host system and verify its integrity.

[0067] The transaction layer content from the replay packet may be sent to the transaction layer at block 448. For example, the receiving circuitry may forward the transaction layer packet corresponding to the corrected packet to a higher protocol layer for further processing.

[0068] At block 450, transaction layer content from sequential packets may be received and transmitted to the transaction layer. For example, the receiving circuitry may accept and forward the remaining retransmitted packet sequence, including content from the corrected packet, and / or to complete one or more subsequent transaction layer packets.

[0069] 5 shows a flowchart of a method 500 for handling packet replay at the data link layer of a transmitter in a PCIe system. Method 500 may be performed by transmitter circuitry within a data storage device or other peripheral device connected to a host system via a PCIe interface. Method 500 may provide efficient handling of packet errors by dynamically selecting between selective and sequential replay modes. In general, method 500 may provide a structured approach to error handling in data transmission and allow flexibility in selecting the most appropriate replay mode based on the particular circumstances of the error.

[0070] The packet may be sent to a receiver at block 510. For example, the transmit circuit may transmit the data link packet to a host system via a PCIe interface.

[0071] A replay request may be received at block 512. For example, the transmit circuit may receive a Data Link Layer Packet (DLLP) from the host system indicating that an error occurred in the transmission of a previously transmitted packet.

[0072] The particular packet in error may be determined at block 514. For example, the transmit circuitry may analyze the replay request to identify which packet needs to be retransmitted based on a data link packet identifier from the header of the erroneous packet.

[0073] The replay mode to be used may be determined in block 516. For example, the transmit circuitry may determine the replay mode parameter value from a replay request set by the receiver that detected the error.

[0074] A determination may be made as to whether selective replay should be used at block 518. For example, the transmit circuit may determine whether the value of the replay mode parameter indicates selective replay mode or sequential replay mode.

[0075] If selective replay is indicated, the packet sequence may be interrupted in block 520. For example, the transmit circuitry may pause the current transmit sequence to prepare to retransmit a particular packet that has an error.

[0076] The erroneous packet may be retransmitted out of sequence at block 522. For example, the transmit circuitry may remove the erroneous packet from its transmit buffer and transmit it immediately, regardless of its original position in the sequence.

[0077] The packet sequence may be resumed from the point of interruption in block 524. For example, after a retransmitted packet, the transmit circuitry may return to transmitting packets in the ongoing sequence of new packets without repeating the packets that followed the originally retransmitted packet.

[0078] If selective replay is not indicated, the current packet sequence may be terminated in block 530. For example, the transmit circuitry may stop the ongoing transmission and prepare to retransmit all packets from the point of the error.

[0079] The erroneous packet may be retransmitted at block 532. For example, the transmit circuitry may remove the erroneous packet from its transmit buffer and begin retransmission from this point.

[0080] The packet sequence may be restarted from the packet that was in error at block 534. For example, the transmit circuitry may continue to transmit all subsequent packets in the sequence, effectively retransmitting a portion of the data stream beginning with the erroneous packet and continuing forward.

[0081] 6 illustrates a flowchart of a method 600 for determining parameters associated with a replay buffer in a peripheral interface of a computing device based on a flow control mode. Method 600 may be performed by replay logic in a data storage device or other peripheral device connected to a host system via a peripheral interface. Method 600 may provide accurate determination of replay buffer parameters that account for variations in packet size and format due to flow control mode. In general, method 600 may dynamically adjust replay buffer parameters to optimize error handling and data transmission efficiency in different flow control scenarios.

[0082] The buffer size of the replay buffer may be determined in block 610. For example, the replay logic may access a parameter register to retrieve the total memory allocated to the replay buffer.

[0083] At block 612, the flow control mode may be determined. For example, the replay logic may check the current status of the peripheral interface protocol to identify whether a particular flow control mode, such as FLIT (Flow Control Unit) mode, is active.

[0084] In block 614, packet size and format and replay buffer packet capacity may be determined based on the flow control mode. For example, if FLIT mode is active, the replay logic may calculate new packet sizes and formats according to the FLIT specifications and then determine how many of these packets can be stored in the replay buffer.

[0085] In block 616, the fill level of the replay buffer may be determined based on the packet size and format of the current flow control mode. For example, the replay logic may count the number of packets currently stored in the replay buffer and multiply that by the packet size to calculate the current occupancy of the buffer.

[0086] 7 shows a flowchart of a method 700 for adjusting adaptive thresholds for packet replay mode based on skip ordered set mode. Method 700 can be performed by replay logic in a data storage device or other peripheral device connected to a host system via a peripheral interface. Method 700 can provide optimized adaptive threshold adjustments that account for periodic resynchronization events at the data link layer. Generally, method 700 can dynamically adjust adaptive thresholds based on processing duration and expected idle time to improve the efficiency of packet replay decisions.

[0087] The skip ordered set mode may be determined at block 710. For example, the replay logic may check the current status of the peripheral interface protocol to identify whether the skip ordered set mode is active.

[0088] Processing periods and idle times for resynchronization may be determined in block 712. For example, the replay logic may retrieve configured values ​​for fixed periods of transaction layer packet processing and scheduled or predicted idle times between those periods.

[0089] Packets may be received from a transmitter at block 714. For example, the replay logic may accept incoming data link packets from a host system via a peripheral interface.

[0090] A counter for the processing period may be incremented at block 716. For example, the replay logic may update an internal counter that tracks progress within the current processing period.

[0091] A current count into idle may be determined at block 718. For example, the replay logic may calculate the remaining time or packet count before the next scheduled idle period based on the current counter value and the known processing period duration.

[0092] At block 720, the adaptive threshold may be adjusted based on the current count into idle. For example, the replay logic may modify the adaptive threshold for selecting between replay modes, potentially increasing the threshold as the system approaches an idle period to take advantage of the next resynchronization opportunity.

[0093] 8 illustrates a flowchart of a method 800 for determining an adaptive threshold for packet replay in a peripheral interface of a computing device. Method 800 may be performed by replay logic in a data storage device or other peripheral device connected to a host system via the peripheral interface. Method 800 may result in dynamically adjusted adaptive thresholds that optimize selection between replay modes based on current system conditions. Generally, method 800 may analyze various system parameters and historical data to calculate adaptive thresholds that balance efficient error handling and system performance.

[0094] A statistical model may be determined in block 810. For example, the replay logic may select or configure a statistical model that incorporates relevant system parameters and their relationships for threshold calculation.

[0095] A completion target may be determined at block 812. For example, the replay logic may set a target percentage for successful packet transmission completion based on system requirements and historical performance data.

[0096] A latency target may be determined at block 814. For example, the replay logic may establish a maximum tolerable latency for packet retransmissions to maintain overall system responsiveness.

[0097] Parameter types and weighting factors may be determined in block 816. For example, the replay logic may identify key system parameters such as link speed and bit error rate and assign appropriate weighting factors to each based on their relative importance in the statistical model.

[0098] Packet errors may be detected at block 820. For example, the replay logic may identify cyclic redundancy check (CRC) failures in received data link layer packets.

[0099] The current link speed may be determined in block 822. For example, the replay logic may query the physical layer to obtain the current operating speed of the peripheral interface link.

[0100] The number of lanes may be determined in block 824. For example, the replay logic may examine the current link configuration to identify the number of active lanes in the peripheral interface connection.

[0101] A bit error rate may be determined in block 826. For example, the replay logic may calculate or look up the current bit error rate based on recent transmission statistics.

[0102] The packet workload amount may be determined at block 828. For example, the replay logic may measure the current rate of packet transmission and reception on the peripheral interface.

[0103] A host historical workload amount may be determined at block 830. For example, the replay logic may access stored data regarding the historical workload patterns of the connected host system.

[0104] A predicted workload amount may be determined at block 832. For example, the replay logic may use machine learning algorithms or statistical analysis to predict the expected workload based on current trends and historical data.

[0105] An adaptive threshold may be calculated based on the collected parameters and factors at block 834. For example, the replay logic may input all determined values ​​into a statistical model to calculate a new adaptive threshold for selecting between replay modes specifically for packets detected in error.

[0106] While at least one exemplary embodiment has been presented in the foregoing detailed description of the present technology, it should be understood that numerous variations are possible. It should also be understood that the one or more exemplary embodiments are examples and are in no way intended to limit the scope, applicability, or configuration of the present technology. Rather, the foregoing detailed description provides those skilled in the art with a convenient road map for implementing exemplary embodiments of the present technology, and it should be understood that various modifications can be made in the function and / or arrangement of elements described in the exemplary embodiments without departing from the scope of the present technology, as set forth in the appended claims and their legal equivalents.

[0107] As will be appreciated by those skilled in the art, various aspects of the present technology may be embodied as a system, method, or computer program product. Accordingly, some aspects of the present technology may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or a combination of hardware and software aspects, all of which may be referred to generally herein as circuits, modules, systems, and / or networks. Furthermore, various aspects of the present technology may take the form of a computer program product embodied in one or more computer-readable medium(s) having computer-readable program code embodied thereon.

[0108] Any combination of one or more computer-readable media may be utilized. The computer-readable medium may be a computer-readable signal medium or a physical computer-readable storage medium. The physical computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, crystalline, polymeric, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Non-limiting examples of physical computer-readable storage media may include, but are not limited to, an electrical connection including one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, an optical fiber, a compact disc read-only memory (CD-ROM), an optical processor, a magnetic processor, or the like, or any suitable combination of the above. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain and / or store a program or data for use by or in connection with an instruction execution system, apparatus, or device.

[0109] Computer code embodied on a computer-readable medium may be transmitted using any suitable medium, including, but not limited to, wireless, wired, fiber optic cable, radio frequency (RF), etc., or any suitable combination of the above. Computer code for performing operations of aspects of the present technology may be written in any static language, such as the C programming language or other similar programming languages. The computer code may execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the latter scenario, the remote computing device may be connected to the user's computing device via any type of network or communication system, including, but not limited to, a local area network (LAN) or a wide area network (WAN), a converged network, or a connection to an external computer (e.g., via the Internet using an Internet Service Provider).

[0110] Various aspects of the present technology may be described above with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, systems, and computer program products. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing device (processor) of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to generate a machine, such that the instructions, executable via the processing device or other programmable data processing apparatus, create means for performing the operations / functions specified in the flowchart and / or block diagram blocks.

[0111] Some computer program instructions may also be stored on a computer-readable medium that can instruct a computer, other programmable data processing apparatus, or other device to operate in a particular manner, and the instructions stored on the computer-readable medium may create an article of manufacture including instructions that implement the operations / functions specified in the flowchart and / or block diagram blocks. Some computer program instructions may also be loaded onto a computing device, other programmable data processing apparatus, or other device to cause a series of operational steps to be executed on the computing device, other programmable apparatus, or other device to create a computer-implemented process, such that the instructions executed by the computer or other programmable apparatus provide one or more processes for implementing the operations / functions specified in the flowchart and / or block diagram blocks.

[0112] The flowcharts and / or block diagrams in the above figures may illustrate the architecture, functionality, and / or operation of possible implementations of apparatuses, systems, methods, and / or computer program products according to various aspects of the present technology. In this regard, blocks in the flowcharts or block diagrams may represent modules, segments, or portions of code, which may comprise one or more executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative aspects, some functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the operations involved. It should also be noted that blocks of the block diagrams and / or flowchart diagrams, or combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system, or a combination of dedicated hardware and computer instructions, capable of performing one or more specified operations or functions.

[0113] While one or more aspects of the present technology have been shown and described in detail, those skilled in the art will appreciate that modifications and / or adaptations to various aspects may be made without departing from the scope of the present technology as set forth in the following claims.

Claims

1. 1. A device comprising a peripheral interface configured to connect to a host system using a peripheral interface protocol, comprising: the peripheral interface protocol comprises a data link layer configured to send and receive data link packets; The peripheral interface is a replay buffer memory configured to store received data link packets following an erroneous packet to support a selective replay mode; and a replay logic circuit, the replay logic circuit comprising: determining errors in data link packets received via the peripheral interface; dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operating parameters; based on comparing the fill level of the replay buffer memory to the adaptive threshold; the selective replay mode for requesting retransmission of only the erroneous data link packets; a sequential replay mode for requesting retransmission of the erroneous data link packet and any subsequent data link packets transmitted after the erroneous data link packet; The device is configured to send a replay request to the host system based on the selected replay mode.

2. The replay logic circuit In response to the selective replay mode: storing error-free sequential data link packets received after the erroneous data link packet in the replay buffer memory; responsive to receiving an error-free version of the erroneous data link packet from the host system, sequentially transmitting transaction layer content from the error-free version of the erroneous data link packet and the error-free sequential data link packet in the replay buffer memory; clearing the error-free sequential data link packets from the replay buffer memory; In response to the sequential replay mode, discarding subsequent data link packets received after the erroneous data link packet; 10. The device of claim 1, further configured to: in response to receiving the error-free version of the erroneous data link packet and a retransmitted sequential data link packet that was received after the error-free version of the erroneous data link packet, sequentially transmit transaction layer content from the error-free version of the erroneous data link packet and the retransmitted sequential data link packet.

3. the replay buffer memory has a buffer size corresponding to a total number of data link packets that can be stored in the replay buffer memory at one time; the fill level corresponds to a current number of data link packets stored in the replay buffer memory due to pending selective replay requests; the adaptive threshold corresponds to a maximum fill level that is less than the buffer size of the replay buffer memory; the replay logic is further configured to periodically determine the adaptive threshold from a plurality of maximum fill levels based on the set of link operating parameters. The device of claim 1 .

4. the peripheral interface protocol supports a flow control mode configured to change a packet size and format of the data link packets; The replay logic circuit determining that the flow control mode is active; determining the fill level of the replay buffer memory based on the packet size of the data link packets in the flow control mode; and further configured to dynamically determine the adaptive threshold based on the flow control mode. The device of claim 3.

5. 10. The device of claim 1, wherein the replay logic is further configured to, upon each detection of an erroneous data link packet, recalculate the adaptive threshold based on a current set of link operating parameters to dynamically determine the adaptive threshold for that erroneous data link packet.

6. The replay logic circuit the set of link operational parameters; a weighting factor configured to balance the probability of successfully recovering the erroneous data link packet with data link layer latency, the weighting factor being set corresponding to each of the parameters included in the set of link operational parameters; 10. The device of claim 1, further configured to dynamically determine the adaptive threshold by processing the set of link operating parameters through a statistical model comprising:

7. The set of link operational parameters comprises: Your current link speed and The number of lanes and and a bit error rate for the current link speed and number of lanes.

8. The set of link operational parameters comprises: the current data link packet workload amount; host system historical workload volume; 10. The device of claim 1, further comprising at least one link workload parameter selected from: a predicted workload amount; and

9. the peripheral interface protocol supports a skip ordered set mode configured to periodically resynchronize the data link layer by introducing idle time between transaction layer packet processing of a fixed duration; the set of link operational parameters includes a counter for transaction layer packet processing for the fixed period; dynamically determining the adaptive threshold in response to the skip order set mode includes compensating for a predicted idle time based on the counter. The device of claim 1 .

10. the device is a data storage device; a non-volatile storage medium configured to store data for the host system; 10. The device of claim 1, further comprising: a peripheral interface connector configured to connect to a peripheral interface bus for storage communication with the host system using the peripheral interface protocol.

11. 1. A computer-implemented method comprising: receiving a data link packet from a host system via a peripheral interface using a peripheral interface protocol; determining errors in data link packets received via the peripheral interface; dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operating parameters; based on comparing the fill level of the replay buffer memory with the adaptive threshold; a selective replay mode for requesting retransmission of only the erroneous data link packets; a sequential replay mode for requesting retransmission of the erroneous data link packet and any subsequent data link packets transmitted after the erroneous data link packet; sending a replay request to the host system based on the selected replay mode; A method comprising:

12. In response to the selective replay mode: storing error-free sequential data link packets received after the erroneous data link packet in the replay buffer memory; responsive to receiving an error-free version of the erroneous data link packet from the host system, sequentially transmitting transaction layer content from the error-free version of the erroneous data link packet and the error-free sequential data link packet in the replay buffer memory; clearing the error-free sequential data link packets from the replay buffer memory; In response to the sequential replay mode, discarding subsequent data link packets received after the erroneous data link packet; 12. The computer-implemented method of claim 11, further comprising: in response to receiving the error-free version of the erroneous data link packet and a retransmitted sequential data link packet that was received after the error-free version of the erroneous data link packet, sequentially transmitting transaction layer content from the error-free version of the erroneous data link packet and the retransmitted sequential data link packet.

13. and periodically determining the adaptive threshold from a plurality of maximum fill levels based on the set of link operational parameters; the replay buffer memory has a buffer size corresponding to a total number of data link packets that can be stored in the replay buffer memory at one time; the fill level corresponds to a current number of data link packets stored in the replay buffer memory due to pending selective replay requests; the adaptive threshold corresponds to a maximum fill level that is less than the buffer size of the replay buffer memory.

12. The computer-implemented method of claim 11.

14. determining that a flow control mode is active, the peripheral interface protocol supporting the flow control mode configured to modify a packet size and format of the data link packets; determining the fill level of the replay buffer memory based on the packet size of the data link packets in the flow control mode; dynamically determining the adaptive threshold based on the flow control mode; The computer-implemented method of claim 13 further comprising:

15. Upon each detection of an erroneous data link packet, 12. The computer-implemented method of claim 11, further comprising recalculating the adaptive threshold based on a current set of link operating parameters to dynamically determine the adaptive threshold for the erroneous data link packets.

16. the set of link operational parameters; a weighting factor configured to balance the probability of successfully recovering the erroneous data link packet with data link layer latency, the weighting factor being set corresponding to each of the parameters included in the set of link operational parameters; processing the set of link operational parameters through a statistical model comprising: The computer-implemented method of claim 11 further comprising:

17. The set of link operational parameters comprises: Your current link speed and The number of lanes and and a bit error rate for the current link speed and number of lanes.

18. The set of link operational parameters comprises: the current data link packet workload amount; host system historical workload volume; 12. The computer-implemented method of claim 11, further comprising at least one link workload parameter selected from: a predicted workload amount; and

19. the peripheral interface protocol supports a skip ordered set mode configured to periodically resynchronize the data link layer by introducing idle time between transaction layer packet processing of a fixed duration; the set of link operational parameters includes a counter for transaction layer packet processing for the fixed period; dynamically determining the adaptive threshold in response to the skip order set mode includes compensating for a predicted idle time based on the counter.

12. The computer-implemented method of claim 11.

20. A peripheral interface circuit, a data link layer configured to receive data link packets from a host system; a replay buffer memory configured to store received data link packets following an erroneous packet to support a selective replay mode; means for determining errors in data link packets received from the host system; means for dynamically determining an adaptive threshold for selecting a replay mode based on a set of link operating parameters; based on comparing the fill level of the replay buffer memory to the adaptive threshold; the selective replay mode for requesting retransmission of only the erroneous data link packets; a sequential replay mode for requesting retransmission of the erroneous data link packet and any subsequent data link packets transmitted after the erroneous data link packet; means for transmitting a replay request to the host system based on the selected replay mode; A peripheral interface circuit comprising:

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