Display board and method for manufacturing the same, display device

Abstract

A display substrate and its manufacturing method, and a display device, the display substrate includes a plurality of display units, the display unit includes a display area and a transparent area, the display area includes a first power supply line and a second power supply line in a first direction, a first scanning signal line, a second scanning signal line, a second scanning connection line, and a first scanning connection line in a second direction, the second scanning connection line and the second scanning signal line are connected to form a first ring structure, the display area further includes a third scanning connection line, and the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to form a second ring structure, orthogonal projections of the first ring structure, the first power supply line, and the second power supply line on a base substrate do not overlap, and orthogonal projections of the second ring structure, the first power supply line, and the second power supply line on the base substrate do not overlap.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority of a Chinese patent application with the application number 202121504315.1, filed with the CNIPA on June 30, 2021, and the priority of a Chinese patent application with the application number 2021109448352, filed with the CNIPA on August 17, 2021, the content of which is incorporated herein by reference.

[0002] Examples of the present disclosure relate to the display technology field, but are not limited thereto, and particularly relate to a display substrate and its manufacturing method, and a display device.

Background Art

[0003] An Organic Light Emitting Diode (abbreviated as OLED) is an active light - emitting display device, Autonomous light emission and has advantages such as ultra - thin, wide viewing angle, high brightness, high contrast, low power consumption, and extremely high response speed. Depending on the driving method, OLEDs can be divided into two types: Passive Matrix (PM) driving type and Active Matrix (AM) driving type. Here, AMOLED is a current driver, and each sub - pixel is controlled using an independent Thin Film Transistor (TFT), and each sub - pixel can drive light emission continuously and independently.

[0004] As display technology advances, OLED technology is increasingly being applied to transparent displays. Transparent displays are a distinctive and important field of display technology, referring to the display of images in a transparent state. Viewers can not only see the image inside the display device but also the scenery behind it, enabling virtual reality (VR), augmented reality (AR), and 3D display functions. In transparent displays employing AMOLED technology, each pixel is typically divided into a display area and a transparent area. Pixel driving circuits and light-emitting elements are provided in the display area to realize image display, while light transmission is achieved in the transparent area. [Overview of the project] [Means for solving the problem]

[0005] The following is an overview of the topic, which will be explained in detail in the main text. This overview is not intended to limit the scope of protection of the patent claims.

[0006] Embodiments of the present disclosure provide a display substrate comprising a base substrate and a plurality of display units provided on the base substrate, wherein each display unit comprises a display area and a transparent area, the display area comprises a plurality of subpixels, the display area is provided with a first power line and a second power line in a first direction, the first power line and the second power line extend in a second direction, the display area is provided with a first scan signal line, a second scan signal line, a second scan connection line and a first scan connection line in the second direction, and the second scan connection line and the second scan signal line are connected to each other to form a first ring structure As a result, the display area has a third scanning connection line between the first scanning signal line and the first scanning connection line, and the third scanning connection line, the first scanning connection line and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, the orthographic projection of the first ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate, and the orthographic projection of the second ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate.

[0007] In an exemplary embodiment, the orthographic projection on the base substrate of the first ring structure does not overlap with the orthographic projection on the base substrate of the second ring structure, and the orthographic projection on the base substrate of the second ring structure encloses the orthographic projection on the base substrate of the first ring structure.

[0008] In an exemplary embodiment, in a direction perpendicular to the display substrate, the subpixel comprises a drive circuit layer provided on the base substrate and a light-emitting structure layer provided on the side of the drive circuit layer away from the base substrate, the drive circuit layer comprises a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer, the first conductive layer comprises a compensation signal line and a first electrode plate, the semiconductor layer comprises an active layer of a plurality of transistors, and the second conductive layer comprises a first scanning signal line, a second scanning signal line, a first scanning connection line, a second scanning connection line, a second electrode plate, and a plurality of transistors The third conductive layer comprises a gate electrode, the first power line, the second power line, the third scanning connection line, the data signal line, and the source and drain electrodes of a plurality of transistors. The orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the first electrode plate on the base substrate overlap, thereby forming a first capacitor. The second scanning connection line and the second scanning signal line are connected to each other to form an integrated structure, and the third scanning connection line is electrically connected to the first scanning connection line and the first scanning signal line, respectively, via through-holes.

[0009] In an exemplary embodiment, at least one subpixel comprises a first transistor, a second transistor, a third transistor, and a first capacitor, the first capacitor comprising a first plate and a second plate, the gate electrode of the first transistor electrically connected to the first scan signal line, the first pole of the first transistor electrically connected to the data signal line, the second pole of the first transistor electrically connected to the gate electrode of the second transistor, the first pole of the second transistor electrically connected to the first power line, the second pole of the second transistor electrically connected to the first pole of an organic electroluminescent diode, the gate electrode of the third transistor electrically connected to the second scan signal line, the first pole of the third transistor electrically connected to the compensation signal line, the second pole of the third transistor electrically connected to the second pole of the second transistor, the second pole of the organic electroluminescent diode electrically connected to the second power line, the first plate electrically connected to the second pole of the second transistor, and the second plate electrically connected to the gate electrode of the second transistor.

[0010] In an exemplary embodiment, the plurality of subpixels include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, wherein in the first direction, the first subpixel and the second subpixel are arranged alternately to form a first row, the third subpixel and the fourth subpixel are arranged alternately to form a second row, in the second direction, the first subpixel and the third subpixel are arranged alternately to form a first column, and the second subpixel and the fourth subpixel are arranged alternately to form a second column, the first scan connection line and the second scan connection line are located at the first subpixel and the second subpixel, and the first scan signal line and the second scan signal line are located at the third subpixel and the fourth subpixel.

[0011] In an exemplary embodiment, at least one subpixel comprises a first transistor, a second transistor, and a third transistor, the first transistor comprising a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor comprising a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, the third transistor comprising a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, and the region where the second scan signal line and the third active layer in the third and fourth subpixels overlap is the The third gate electrode in the third and fourth subpixels is defined as the third gate electrode in the first and second subpixels. The region where the second scanning connection line and the third active layer in the first and second subpixels overlap is defined as the third gate electrode in the first and second subpixels. The region where the first scanning signal line and the first active layer in the third and fourth subpixels overlap is defined as the first gate electrode in the third and fourth subpixels. The region where the first scanning connection line and the first active layer in the first and second subpixels overlap is defined as the first gate electrode in the first and second subpixels.

[0012] In an exemplary embodiment, at least one of the display regions further comprises a compensation signal line extending in a second direction, the first gate electrode, second gate electrode, and third gate electrode in the first and second subpixels being mirror-symmetric with respect to the vertical axis, and the first gate electrode, second gate electrode, and third gate electrode in the third and fourth subpixels being mirror-symmetric with respect to the vertical axis, the vertical axis being the compensation signal line.

[0013] In an exemplary embodiment, the compensation signal line is provided with compensation connection lines protruding in a first direction and in the opposite direction to the first direction, the compensation connection lines being located at positions where the first subpixel and the third subpixel are adjacent, and where the second subpixel and the fourth subpixel are adjacent, and the compensation connection lines are electrically connected to the third source electrode of the third transistor via a through-hole.

[0014] In an exemplary embodiment, the third active layer in the first to fourth subpixels is located close to the compensation connection line, and there is an overlapping region between the orthographic projection of the base substrate of the third active layer and the orthographic projection of the base substrate of the compensation connection line.

[0015] In an exemplary embodiment, the third active layer in the first subpixel and the third active layer in the third subpixel are connected to each other in an integrated structure, and the third active layer in the second subpixel and the third active layer in the fourth subpixel are connected to each other in an integrated structure.

[0016] In an exemplary embodiment, at least one of the subpixels further comprises a first capacitor, the first capacitor comprising a first plate and a second plate positioned opposite each other, and the second gate electrode is provided across the second active layer and connected to the second plate to form an integral structure.

[0017] In an exemplary embodiment, the first electrode plate in the first subpixel has a first aperture on the side close to the third subpixel and away from the second subpixel; the first electrode plate in the second subpixel also has a first aperture on the side close to the fourth subpixel and away from the first subpixel; the first electrode plate in the third subpixel has a second aperture on the side close to the first subpixel and close to the fourth subpixel; the first electrode plate in the fourth subpixel also has a second aperture on the side close to the second subpixel and close to the third subpixel; the first active layer in the first and second subpixels is located near the first aperture; and the first active layer in the third and fourth subpixels is located near the second aperture.

[0018] In an exemplary embodiment, at least one of the subpixels further comprises a second capacitor, the second capacitor comprising a second plate and a third plate positioned opposite each other, wherein there is an overlap region between the orthographic projection of the third plate on the base substrate and the orthographic projection of the second plate on the base substrate, and the third plate is electrically connected to the first plate via through holes.

[0019] Embodiments of the present disclosure further provide a display device comprising the above-described display substrate.

[0020] Embodiments of the present disclosure further provide a method for manufacturing a display substrate, wherein a plurality of display units are formed on a base substrate, each display unit comprising a display area and a transparent area, the display area is provided with a first power line and a second power line in a first direction, the first power line and the second power line extend in a second direction, the display area is provided with a first scan signal line, a second scan signal line, a second scan connection line and a first scan connection line in the second direction, the second scan connection line and the second scan signal line are connected to each other to form a first ring structure, and the display area comprises the A third scanning connection line is provided between the first scanning signal line and the first scanning connection line, and the third scanning connection line, the first scanning connection line and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, the orthographic projection of the first ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate, and the orthographic projection of the second ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate.

[0021] Other embodiments can be understood after reading and understanding the attached drawings and detailed descriptions.

[0022] The drawings are intended to provide a better understanding of the technical proposal of this disclosure, and constitute part of the specification, and are used to illustrate the technical proposal of this disclosure together with the embodiments of this disclosure, and are not intended to limit the technical proposal of this disclosure. [Brief explanation of the drawing]

[0023] [Figure 1] FIG. 1 is a schematic structural diagram of a display device. [Figure 2] FIG. 2 is a schematic plan view of a display substrate. [Figure 3] FIG. 3 is a schematic cross-sectional view of a display substrate. [Figure 4] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit. [Figure 5] FIG. 5 is a schematic structural diagram of a display panel according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 6 is an equivalent circuit diagram of a pixel driving circuit in four sub-pixels shown in FIG. 5. [Figure 7] FIG. 7 is a schematic diagram after a first conductive layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic cross-sectional view of the AA region in FIG. 7. [Figure 9] FIG. 9 is a schematic diagram after a semiconductor layer pattern is formed according to an exemplary embodiment of the present disclosure. [[ID=X]] [Figure 10] FIG. 10 is a schematic cross-sectional view of the AA region in FIG. 9. [Figure 11] FIG. 11 is a schematic diagram after a second conductive layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic cross-sectional view of the AA region in FIG. 11. [Figure 13] FIG. 13 is a schematic diagram after a third insulating layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic cross-sectional view of the AA region in FIG. 13. [Figure 15] FIG. 15 is a schematic diagram after a third conductive layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic cross-sectional view of the AA region in FIG. 15. [Figure 17] FIG. 17 is a schematic diagram after a planarization layer pattern is formed according to an exemplary embodiment of the present disclosure. [Figure 18]Figure 18 is a schematic diagram of the cross-sectional structure of region AA in Figure 17. [Figure 19] Figure 19 is a schematic diagram of an exemplary embodiment of the present disclosure after the first transparent conductive layer pattern has been formed. [Figure 20] Figure 20 is a schematic diagram of the cross-sectional structure of region AA in Figure 19. [Figure 21] Figure 21 is a schematic diagram of an exemplary embodiment of the present disclosure after the anode pattern has been formed. [Figure 22] Figure 22 is a schematic diagram of the cross-sectional structure of region AA in Figure 21. [Figure 23] Figure 23 is a schematic diagram of an exemplary embodiment of the present disclosure after the first pixel definition layer pattern has been formed. [Figure 24] Figure 24 is a schematic diagram of the cross-sectional structure of region AA in Figure 23. [Figure 25] Figure 25 is a schematic diagram of an exemplary embodiment of the present disclosure after an organic light-emitting layer pattern has been formed. [Figure 26] Figure 26 is a schematic diagram of an exemplary embodiment of the present disclosure after the cathode pattern has been formed. [Figure 27] Figure 27 is a schematic diagram of a short-circuit fault point and laser repair method for a display board according to an exemplary embodiment of the present disclosure. [Figure 28] Figure 28 is a schematic diagram of another example embodiment of a display board short-circuit fault and laser repair method according to the present disclosure. [Modes for carrying out the invention]

[0024] To clarify the purpose, technical proposals, and merits of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments may be carried out in multiple different forms. The methods and content may be transformed into various forms without deviating from the spirit and scope of this disclosure, so as can be easily understood by those skilled in the art. Accordingly, this disclosure should not be construed as being limited to the embodiments described below. Embodiments and features in these embodiments can be combined in any way, as long as they do not conflict.

[0025] The proportions in the drawings in this disclosure may, but are not limited to, be used as reference in actual processes. For example, the aspect ratio of the channels, the thickness and pitch of each film layer, and the width and pitch of each signal line can be adjusted as needed. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the quantities shown in the drawings, and the drawings described in this disclosure are schematic diagrams of the structure. One method of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0026] In this specification, ordinal numbers such as "1st," "2nd," and "3rd" are established to avoid confusion of constituent elements and are not intended to limit them in terms of quantity.

[0027] In this specification, for convenience, descriptions indicating directional or positional relationships, such as “center,” “top,” “bottom,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to describe the positional relationships of components with reference to the drawings. However, this is merely for the sake of simplicity in describing this specification and does not express or imply that the indicated devices or elements necessarily have a specific orientation or are configured and operated in a specific orientation, and should therefore not be considered a limitation of this disclosure. The positional relationships of components are appropriately modified depending on the direction in which each component is described. Therefore, the terminology used in this specification is not limited and can be appropriately substituted as appropriate in the context.

[0028] In this specification, unless otherwise explicitly stated or limited, the terms “attachment” and “connection” should be understood in a broad sense. For example, this could mean being permanently connected, or detachably connected, or integrally connected; it could be a mechanical connection or an electrical connection; it could be a direct connection, an indirect connection via an intermediate component, or internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of the above terms in this disclosure from the specific context.

[0029] In this specification, a transistor refers to an element having at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. However, in this specification, the channel region refers to the region through which the current primarily flows.

[0030] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When transistors with opposite polarity are used, or when the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be swapped. Therefore, in this specification, the "source electrode" and the "drain electrode" can be swapped with each other, and the "source terminal" and the "drain terminal" can be swapped with each other.

[0031] In this specification, “electrical connection” includes cases where components are connected via an element having some electrical function. “An element having some electrical function” is not particularly limited, as long as it can transmit and receive electrical signals between the connected components. Examples of “elements having some electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements having different functions.

[0032] In this specification, "parallel" refers to a state in which the angle between two straight lines is -10° or more and 10° or less, and therefore also includes a state in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" refers to a state in which the angle between two straight lines is 80° or more and 100° or less, and therefore also includes a state in which the angle is 85° or more and 95° or less.

[0033] In this specification, "film" and "layer" can be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0034] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0035] In this disclosure, "approximately" means that the limits are not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0036] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data signal driver, a scanning signal driver, and a pixel array. The timing controller is connected to the data signal driver and the scanning signal driver, respectively. The data signal driver is connected to a plurality of data signal lines (D1 to Dn), and the scanning signal driver is connected to a plurality of scanning signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, where i and j are natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting element connected to the circuit unit. The circuit unit may include at least one scanning signal line, at least one data signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may provide the data signal driver with gradation values ​​and control signals suitable for the specifications of the data signal driver, and may also provide the scanning signal driver with a clock signal, a scan start signal, etc., suitable for the specifications of the scanning signal driver. The data signal driver may use the gradation values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, a data signal driver may use a clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn, with each pixel row being a natural number. A scanning signal driver may receive a clock signal, a scanning start signal, etc., from a timing controller and generate scanning signals to be provided to scanning signal lines S1, S2, S3, ..., and Sm. For example, a scanning signal driver can sequentially provide scanning signals having turn-on level pulses to scanning signal lines S1 to Sm. For example, a scanning signal driver may be configured in the form of a shift register and generate scanning signals so as to sequentially transmit the scanning start signal provided in the form of a turn-on level pulse to the next stage circuit under the control of a clock signal, with m being a natural number.

[0037] Figure 2 is a schematic diagram of the planar structure of a display board. As shown in Figure 2, the display board may include a plurality of pixel units P arranged in a matrix manner, and at least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color ray, a second subpixel P2 that emits a second color ray, a third subpixel P3 that emits a third color ray, and a fourth subpixel P4 that emits a fourth color ray, and each of the four subpixels may include a circuit unit and a light-emitting element, and the circuit unit may include a scan signal line, a data signal line, and a pixel driving circuit, and the pixel driving circuit is electrically connected to the scan signal line and the data signal line, respectively, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scan signal line and to output a corresponding current to the light-emitting element. The light-emitting element in each subpixel is connected to the pixel driving circuit of the subpixel in which it is located, and the light-emitting element is configured to emit light of a corresponding brightness according to the current output from the pixel driving circuit of the subpixel in which it is located.

[0038] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light rays, the second subpixel P2 may be a green subpixel (G) that emits green light rays, the third subpixel P3 may be a white subpixel (W) that emits white light rays, and the fourth subpixel P4 may be a blue subpixel (B) that emits blue light rays.

[0039] In exemplary embodiments, the shape of the subpixels may be rectangular, rhombus, pentagonal, or hexagonal. In one exemplary embodiment, four subpixels may be arranged in a horizontal parallel arrangement to form an RWBG pixel array. In other exemplary embodiments, the four subpixels may be arranged in a square, diamond, or vertical parallel arrangement, and the disclosure is not limited thereto.

[0040] In an exemplary embodiment, a plurality of subpixels arranged sequentially in the horizontal direction are referred to as pixel rows, and a plurality of subpixels arranged sequentially in the vertical direction are referred to as pixel columns. is a pixel array It constitutes.

[0041] Figure 3 is a schematic cross-sectional diagram of the display substrate, illustrating the structure of the four subpixels of the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, each subpixel on the display substrate may include a drive circuit layer 102 provided on the base substrate 10, a light-emitting structure layer 103 provided on the side of the drive circuit layer 102 away from the base substrate, and a package layer 104 provided on the side of the light-emitting structure layer 103 away from the base substrate.

[0042] In exemplary embodiments, the base substrate 10 may be a flexible base substrate or a rigid base substrate. The drive circuit layer 102 of each subpixel may include a pixel drive circuit consisting of a plurality of transistors and memory capacitors. The light-emitting structure layer 103 of each subpixel may include a light-emitting element consisting of a plurality of film layers, the plurality of film layers may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, the anode being connected to the pixel drive circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light rays of the corresponding color when driven by the anode and cathode. The package layer 104 may include a first package layer, a second package layer, and a third package layer that are stacked, the first and third package layers may be made of inorganic materials, and the second package layer may be made of organic materials, the second package layer being provided between the first package layer and the third package layer to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0043] In exemplary embodiments, the organic light-emitting layer may comprise a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron barrier layer (EBL), a light-emitting layer (EML), a hole barrier layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In exemplary embodiments, the hole injection layer, hole transport layer, electron barrier layer, hole barrier layer, electron transport layer, and electron injection layer of all subpixels may be a common layer connected to one another, the light-emitting layers of all subpixels may be a common layer connected to one another, or they may be isolated from one another, and the light-emitting layers of adjacent subpixels may have a small overlap. In some possible implementations, the display substrate may comprise other film layers, and this disclosure is not limited thereto.

[0044] In exemplary embodiments, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 is a schematic equivalent circuit diagram of the pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 3T1C structure and may include three transistors (first transistor T1, second transistor T2, and third transistor T3), one memory capacitor C, and six signal lines (data signal line D, first scan signal line G1, second scan signal line G2, compensation signal line S, first power line VDD, and second power line VSS).

[0045] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensating transistor. The first pole of the memory capacitor C is coupled to the control pole of the second transistor T2, and the second pole of the memory capacitor C is coupled to the second pole of the second transistor T2, and the memory capacitor C is used to store the potential of the control pole of the second transistor T2. The control pole of the first transistor T1 is coupled to the first scan signal line G1, the first pole of the first transistor T1 is coupled to the data signal line D, and the second pole of the first transistor T1 is coupled to the control pole of the second transistor T2, and the first transistor T1 is used to control the first scan signal line G1, receive the data signal transmitted by the data signal line D, and cause the control pole of the second transistor T2 to receive the data signal. The control pole of the second transistor T2 is coupled to the second pole of the first transistor T1, the first pole of the second transistor T2 is coupled to the first power line VDD, and the second pole of the second transistor T2 is coupled to the first pole of the light-emitting element. The second transistor T2 is used to generate a corresponding current at its second pole in control of the data signal received by its control pole. The control pole of the third transistor T3 is coupled to the second scan signal line G2, the first pole of the third transistor T3 is coupled to the compensation signal line S, and the second pole of the third transistor T3 is coupled to the second pole of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, thereby compensating for the threshold voltage Vth.

[0046] In an exemplary embodiment, the light-emitting element may be an OLED, comprising a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), wherein the first electrode of the OLED is coupled to the second electrode of a second transistor T2, and the second electrode of the OLED is coupled to a second power line VSS, and the OLED is used to emit light of a corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0047] In an exemplary embodiment, the signal on the first power line VDD is a continuously supplied high-level signal, and the signal on the second power line VSS is a low-level signal. The first transistor T1 to the third transistor T3 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the difficulty of the display panel process can be reduced, and the product yield can be increased.

[0048] In an exemplary embodiment, the first to third transistors T1 to T3 may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. In an exemplary embodiment, low-temperature polysilicon thin-film transistors and oxide thin-film transistors may be integrated onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, utilizing the advantages of both, enabling high resolution (Pixels Per Inch, PPI), low-frequency driving, reduced power consumption, and improved display quality. In exemplary embodiments, the light-emitting element may be an organic electroluminescent diode (OLED), comprising a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0049] In an exemplary embodiment, assuming that all three transistors are N-type transistors, the operation process of the exemplary pixel driving circuit in Figure 4 may include the following first stage A1 and second stage A2.

[0050] In the first stage A1, the signals on the first scan signal line G1 and the second scan signal line G2 are high-level signals, the data signal line D outputs a data voltage, the compensation signal line S outputs a compensation voltage, the signal on the first power line VDD is high-level, and the signal on the second power line VSS is low-level. The signal on the first scan signal line G1 is a high-level signal, turning on the first transistor T1, and the data voltage output from the data signal line D is written to the first node N1, raising the potential of the first node N1 and charging the memory capacitor C. At this time, the potential of the first node N1 is V1 = V data Therefore, the signal on the second scan signal line G2 is a high-level signal, which turns on the third transistor T3, and the compensation voltage output from the compensation signal line S is written to the second node N2, at which point the potential of the second node N2 is V2 = V s The difference in potential between the first node N1 and the second node N2 is the threshold voltage V of the second transistor T2. th Because it is greater than the first transistor T2, the second transistor T2 is turned on, and the power supply voltage output from the first power line VDD provides a drive voltage to the first pole of the OLED via the turned-on second transistor T2, driving the OLED to emit light.

[0051] In the second stage A2, the signals on the first scan signal line G1 and the second scan signal line G2 are low-level signals, turning off the first transistor T1 and the third transistor T3. The voltage across the memory capacitor C remains such that the second transistor T2 is still ON, and the power supply voltage output from the first power supply line VDD continues to raise the potential of the second node N2, causing the OLED to continue to emit light. data -V th When this value is equal, the second transistor T2 turns off, and the OLED stops emitting light.

[0052] In an exemplary embodiment, both the OLED and the second transistor T2 are forward-biased to drive normal light emission of the OLED. In the first stage, the power supply voltage output from the first power supply line VDD is greater than the data voltage output from the data signal line D, the data voltage output from the data signal line D is greater than the compensation voltage output from the compensation signal line S, and the compensation voltage output from the compensation signal line S is greater than the power supply voltage output from the second power supply line VSS.

[0053] As display technology advances, OLED technology is increasingly being applied to transparent displays. Transparent displays are a distinctive and important field of display technology, referring to the display of images in a transparent state. Viewers can not only see the image inside the display device but also the scenery behind it, enabling virtual reality (VR), augmented reality (AR), and 3D display functions. In transparent displays employing AMOLED technology, each pixel is typically divided into a display area and a transparent area. Pixel driving circuits and light-emitting elements are provided in the display area to realize image display, while light transmission is achieved in the transparent area.

[0054] However, in large transparent display products, the overlap area between power lines and other signal lines is large, which can easily affect the yield rate of the product, and as a result, the reliability of the product may not meet the process requirements.

[0055] An exemplary embodiment of the present disclosure provides a display substrate comprising a base substrate and a plurality of display units provided on the base substrate, wherein at least one display unit comprises a display area and a transparent area, and at least one display area comprises a plurality of subpixels.

[0056] At least one display area is provided with a first power line and a second power line in the first direction, the first and second power lines extending in the second direction, and at least one display area is provided with a first scan signal line, a second scan signal line, a second scan connection line, and a first scan connection line in the second direction, the second scan connection line and the second scan signal line are connected to each other to form a first ring structure, and at least one display area is provided with a third scan connection line between the first scan signal line and the first scan connection line, the third scan connection line, the first scan connection line and the first scan signal line are connected to each other to form a second ring structure, and the first and second directions intersect.

[0057] There is no overlapping region between the orthographic projection of the base substrate of the first ring structure and the orthographic projection of the base substrate of the first and second power lines, and there is no overlapping region between the orthographic projection of the base substrate of the second ring structure and the orthographic projection of the base substrate of the first and second power lines.

[0058] The display board provided by the embodiments of this disclosure features a ring-winding design for the first and second scanning signal lines in the display area, with the ring-winding positions of the first and second scanning signal lines avoiding the first and second power lines. This avoids the problem of large overlap area between power lines and other signal lines, which can easily affect the product yield rate. This allows for optimization to minimize intersections between signal lines while maintaining repair functionality, further improving the product yield rate and providing technical support for transparent display products.

[0059] Figure 5 is a schematic diagram of the structure of a display panel according to an exemplary embodiment of the present disclosure, schematically showing the structure of four subpixels (one pixel unit), and Figure 6 is a schematic equivalent circuit diagram of the pixel driving circuit in the four subpixels shown in Figure 5. As shown in Figures 5 and 6, in a direction parallel to the display substrate, at least one pixel unit may comprise a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged sequentially, and each subpixel comprises a pixel driving circuit and a memory capacitor. In the following description, the term "subpixel" refers to the region in which a pixel driving circuit is provided. In exemplary embodiments, at least one pixel unit may further include one first scan signal line G1, one second scan signal line G2, one first power line VDD, one second power line VSS, four data signal lines D (in Figure 6, the four data signal lines D are the first to fourth data signal lines D1 to D4, respectively, with the first subpixel P1 connected to the first data signal line D1, the second subpixel P2 connected to the second data signal line D2, the third subpixel P3 connected to the third data signal line D3, and the fourth subpixel P4 connected to the fourth data signal line D4), one compensation signal line S, and four pixel drive circuits.

[0060] In an exemplary embodiment, the first scan signal line G1 and the second scan signal line G2 may extend in the first direction D1 and be sequentially provided in the second direction D2, and the first direction D1 and the second direction D2 intersect. The first power line VDD, data signal line D, and compensation signal line S may extend in the second direction D2 and be provided correspondingly along the first direction D1.

[0061] In an exemplary embodiment, four data signal lines D and one compensation signal line S are provided between a first power line VDD and a second power line VSS. Two of the four data signal lines D are located between the compensation signal line S and the first power line VDD, and the other two data signal lines D are located between the compensation signal line S and the second power line VSS. Thus, four subpixels are formed between the first power line VDD and the second power line VSS by providing four data signal lines D and one compensation signal line S. Correspondingly, four subpixels are also formed between the two compensation signal lines S by providing one first power line VDD, one second power line VSS, and four data signal lines D.

[0062] In an exemplary embodiment, one first power line VDD, two data signal lines D, a compensation signal line S, two other data signal lines D, and one second power line VSS may be sequentially provided in the first direction D1. In the first direction D1, the first subpixel P1 and the second subpixel P2 are arranged alternately to form the first row, and the third subpixel P3 and the fourth subpixel P4 are arranged alternately to form the second row. In the second direction D2, the first subpixel P1 and the third subpixel P3 are arranged alternately to form the first column, and the second subpixel P2 and the fourth subpixel P4 are arranged alternately to form the second column.

[0063] In an exemplary embodiment, the pixel driving circuit for each subpixel among the four subpixels of at least one pixel unit may include a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor. The first transistor T1 may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode; the second transistor T2 may include a second active layer, a second gate electrode, a second source electrode, and a second drain electrode; the third transistor T3 may include a third active layer, a third gate electrode, a third source electrode, and a third drain electrode; and the memory capacitor may include a first plate and a second plate.

[0064] In an exemplary embodiment, the first and second plates are transparent conductive layers, forming a transparent memory capacitor.

[0065] In an exemplary embodiment, the first scan signal line G1 is connected to the gate electrode of the first transistor T1 in each subpixel, the second scan signal line G2 is connected to the gate electrode of the third transistor T3 in each subpixel, the data signal line D is connected to the first pole of the first transistor T1 in each subpixel, the compensation signal line S is connected to the first pole of the third transistor T3 in each subpixel, the first power line VDD is connected to the first pole of the second transistor T2 in each subpixel, the second pole of the first transistor T1 in each subpixel is connected to the gate electrode of the second transistor T2, the second pole of the second transistor T2 in each subpixel is connected to the first pole of the third transistor T3 and the anode of the light-emitting element, the first electrode plate in each subpixel is connected to the second pole of the second transistor T2 and the second pole of the third transistor T3, respectively, and the second electrode plate in each subpixel is connected to the second pole of the first transistor T1 and the gate electrode of the second transistor T2, respectively.

[0066] In exemplary embodiments, at least one pixel unit may have a plurality of connection lines, the plurality of connection lines including at least two lateral power connection lines extending in a first direction D1 and two compensation connection lines extending in the first direction D1 and the opposite direction to the first direction D1, forming a one-for-four structure for the first power line and a one-for-four structure for the compensation signal line S.

[0067] In an exemplary embodiment, one lateral power supply line is provided for the first subpixel P1 and the second subpixel P2, with one end of the lateral power supply line connected to the first power line VDD via a through-hole, and the other end connected to the second transistor T2 in the first subpixel P1 and the second subpixel P2 via a through-hole. Another lateral power supply line is provided for the third subpixel P3 and the fourth subpixel P4, with one end of the lateral power supply line connected to the first power line VDD via a through-hole, and the other end connected to the second transistor T2 in the third subpixel P3 and the fourth subpixel P4 via a through-hole. Thus, one first power line VDD can provide power signals to four subpixels.

[0068] In an exemplary embodiment, the compensation connection line is located in the center of one pixel unit, and the compensation connection line and the compensation signal line are connected to each other in an integrated structure. The compensation connection line is connected to the third transistor T3 in each subpixel via a through-hole. In this way, one compensation signal line S can provide a compensation signal to four subpixels.

[0069] In the embodiments of this disclosure, the 1-drag-4 structure of the first power line and the 1-drag-4 structure of the compensation signal line save the number of signal lines, reduce the occupied space, have a simple structure, a rational arrangement, make full use of the layout space, increase space utilization, and are advantageous for improving resolution.

[0070] In an exemplary embodiment, in a direction perpendicular to the display substrate, the sub-pixel drive circuit layer may comprise a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, and a flat layer, all stacked on a base substrate. The first conductive layer comprises at least a first electrode plate of a memory capacitor, compensation signal lines, and compensation connection lines; the semiconductor layer comprises at least three active layers of transistors; the second conductive layer comprises at least a first scanning signal line, a second scanning signal line, a lateral power supply connection line, a second electrode plate of a memory capacitor, and gate electrodes of three transistors; and the third conductive layer comprises at least a first power line VDD, a second power line VSS, a data signal line D, and the first and second electrodes of three transistors. The orthographic projection of the first electrode plate on the base substrate and the orthographic projection of the second electrode plate on the base substrate have at least an overlapping region, forming a memory capacitor.

[0071] In an exemplary embodiment, the second conductive layer may include a first scanning connection line and a second scanning connection line, the first and second scanning connection lines located at the first subpixel P1 and the second subpixel P2, the first scanning signal line and the second scanning signal line located at the third subpixel P3 and the fourth subpixel P4, and the second scanning connection line and the second scanning signal line are connected to each other to form an integrated structure. The third conductive layer may include a third scanning connection line, which is connected to the first scanning connection line and the first scanning signal line via through-holes.

[0072] In exemplary embodiments, the second conductive layer may include a longitudinal power connection line and an auxiliary power line, where the first power line VDD is electrically connected to the longitudinal power connection line via a through-hole to form a two-layer first power wiring, and the second power line VSS is electrically connected to the auxiliary power line via a through-hole to form a two-layer second power wiring.

[0073] In an exemplary embodiment, the third conductive layer may include an auxiliary cathode, and the auxiliary cathode and the second power line VSS are connected to each other in an integrated structure.

[0074] In an exemplary embodiment, in a direction perpendicular to the display substrate, the subpixel further comprises a light-emitting structural layer provided on the side away from the base substrate of the drive circuit layer, the light-emitting structural layer comprises an anode, and the auxiliary connecting electrode is provided on the same layer as the anode.

[0075] Next, the manufacturing process of the display substrate will be illustrated. The “patterning process” as referred to in this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, treatments such as photoresist coating, mask exposure, development, etching, and photoresist stripping, and for organic materials, treatments such as coating, mask exposure, and development of the organic material. Deposition may be one or more of sputtering, vapor deposition, or chemical vapor deposition; coating may be one or more of spray coating, spin coating, or inkjet printing; and etching may be one or more of dry etching or wet etching, but this disclosure is not limited thereto. A “thin film” refers to a thin film of a single layer produced on a base substrate by deposition, coating, or other process of a certain material. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may further be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after undergoing a patterning process contains at least one “pattern.” “A and B are provided in the same layer” as used in this disclosure means that A and B are formed simultaneously by the same patterning process, and the “thickness” of the film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A and the boundary of the orthographic projection of B overlap.

[0076] Figures 7 to 26 are schematic diagrams of the display substrate manufacturing process of the present disclosure, schematically showing the layout structure of one display unit of a top-emission OLED display substrate, each display unit comprising a display area 100 and a transparent area 200, the display area 100 comprising a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4, and the pixel driving circuit for each subpixel comprising a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor. In exemplary embodiments, the display substrate manufacturing process may include the following operations (1) to (11).

[0077] (1) Forming a first conductive layer pattern, which includes depositing a first metal thin film on a base substrate and patterning the first metal thin film by a patterning process to form a first conductive layer pattern on the base substrate 10, wherein the first conductive layer pattern comprises a first electrode plate 41 and compensation signal lines S, each subpixel forming one first electrode plate 41, and the compensation signal lines S are a stripe structure provided between four subpixels, as shown in Figures 7 and 8. Figure 8 is a cross-sectional view in the AA direction in Figure 7.

[0078] In an exemplary embodiment, the first plate 41 is configured as one plate of the first capacitor to form the first capacitor with a subsequently formed second plate, and the first plate 41 is also configured as a shielding layer to provide light shielding to the transistor, thereby reducing the light intensity irradiated to the transistor, reducing the drain current, and thereby reducing the effect of light irradiation on the transistor characteristics.

[0079] In an exemplary embodiment, the compensation signal line S extends in a second direction D2, and the compensation signal line S is provided with a compensation connection line S-1 protruding in a first direction D1 and in the opposite direction to the first direction D1. The compensation connection line S-1 is connected to the first pole of a subsequently formed third transistor and is used to provide a compensation signal to the third transistor in each subpixel.

[0080] In an exemplary embodiment, the first electrode plate 41 is a long rectangle, and the first electrode plate 41 in the first subpixel P1 and the first electrode plate 41 in the second subpixel P2 are each provided with a first aperture 45 located near the center of the pixel unit and away from the compensation signal line S, while the first electrode plate 41 in the third subpixel P3 and the first electrode plate 41 in the fourth subpixel P4 are each provided with a second aperture 46 located near the center of the pixel unit and close to the compensation signal line S.

[0081] In an exemplary embodiment, the first conductive layer pattern in the first subpixel P1 and the first conductive layer pattern in the second subpixel P2 are mirror images symmetric with respect to the vertical axis (the vertical axis may be a compensation signal line S), and the first conductive layer pattern in the third subpixel P3 and the first conductive layer pattern in the fourth subpixel P4 are mirror images symmetric with respect to the vertical axis.

[0082] After this patterning process, the first conductive layer pattern is formed in the display area 100, and there is no corresponding film layer in the transparent area 200.

[0083] (2) Forming a semiconductor layer pattern, which includes sequentially depositing a first insulating thin film and a semiconductor layer thin film on a base substrate on which the aforementioned pattern is formed, patterning the semiconductor layer thin film by a patterning process to form a first insulating layer 61 covering the first conductive layer pattern, and forming a semiconductor layer pattern on the first insulating layer 61, wherein the semiconductor layer comprises a pattern of a first active layer 11, a second active layer 21, and a third active layer 31 provided on each subpixel, and Figure 10 is a cross-sectional view in the AA direction in Figure 9. The first active layer 11 is the active layer of the first transistor, the second active layer 21 is the active layer of the second transistor, and the third active layer 31 is the active layer of the third transistor.

[0084] In an exemplary embodiment, in four subpixels, there is an overlapping region between the orthographic projection of the second active layer 21 on the base substrate 10 and the orthographic projection of the first electrode plate 41 on the base substrate 10. As a result, the first electrode plate 41, acting as a shielding layer, can shield the channel region of the second transistor, preventing light rays from affecting the channel and preventing the display effect from being affected by light leakage current generated by the channel.

[0085] In the exemplary embodiment, the first active layer 11 in the first subpixel P1 and the second subpixel P2 is located near the first aperture 45, and the first active layer 11 in the third subpixel P3 and the fourth subpixel P4 is located near the second aperture 46.

[0086] In an exemplary embodiment, in the four subpixels P1 to P4, the third active layer 31 is provided in a position close to the compensation connection line S-1, and there is an overlapping region between the orthographic projection of the third active layer 31 on the base substrate 10 and the orthographic projection of the compensation connection line S-1 on the base substrate 10. In an exemplary embodiment, the third active layer 31 in the first subpixel P1 and the third active layer 31 in the third subpixel P3 are connected to each other as an integrated structure, and the third active layer 31 in the second subpixel P2 and the third active layer 31 in the fourth subpixel P4 are connected to each other as an integrated structure.

[0087] In an exemplary embodiment, the semiconductor layer pattern in the first subpixel P1 and the semiconductor layer pattern in the second subpixel P2 are mirror images symmetric with respect to the vertical axis, and the semiconductor layer pattern in the third subpixel P3 and the semiconductor layer pattern in the fourth subpixel P4 are mirror images symmetric with respect to the vertical axis.

[0088] In an exemplary embodiment, the semiconductor layer may be made of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0089] After this patterning process, the semiconductor layer pattern is formed in the display area 100, and the transparent area 200 comprises the base substrate 10 and the first insulating layer 61 provided on the base substrate 10.

[0090] (3) Forming a second conductive layer pattern, which involves sequentially depositing a second insulating thin film and a second metal thin film on a base substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film and the second metal thin film by a patterning process to form a second insulating layer 62 pattern and a second conductive layer pattern provided on the second insulating layer 62, the second conductive layer pattern as shown in Figures 11 and 12, comprising a first scanning signal line G1, a second scanning signal line G2, a first scanning connection line G1-1, a second scanning connection line G2-1, a vertical power supply connection line 51, a horizontal power supply connection line 52, an auxiliary power line 53, a second electrode plate 42 formed on each subpixel, a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32, the second conductive layer pattern being a cross-sectional view in the AA direction in Figure 11.

[0091] In an exemplary embodiment, there is an overlapping region between the orthographic projection of the second electrode plate 42 on the base substrate 10 and the orthographic projection of the first electrode plate 41 on the base substrate 10, and the first electrode plate 41 and the second electrode plate 42 form a first capacitor.

[0092] In an exemplary embodiment, the second electrode plate 42 is a long rectangle, and the second electrode plate 42 in the first subpixel P1 and the second subpixel P2 is provided with a third aperture 47 located near the center of the pixel unit, while the second electrode plate 42 in the third subpixel P3 and the fourth subpixel P4 is provided with a fourth aperture 48 located near the center of the pixel unit.

[0093] In the exemplary embodiment, both the first scan signal line G1 and the second scan signal line G2 extend in the first direction D1, the second scan connection line G2-1 has an inverted "U" shape, the second scan connection line G2-1 and the second scan signal line G2 are connected to each other to form an integrated structure, the first scan connection line G1-1 has a "single" shape, the first scan connection line G1-1 and the second scan connection line G2-1 are located at the first subpixel P1 and the second subpixel P2, and the first scan signal line G1 and the second scan signal line G2 are located at the third subpixel P3 and the fourth subpixel P4.

[0094] In the exemplary embodiment, there is an overlapping region between the orthographic projection of the second scanning signal line G2 on the base substrate and the orthographic projection of the third active layer 31 on the base substrate in the third subpixel P3 and the fourth subpixel P4. The overlapping region between the second scanning signal line G2 and the third active layer 31 on the base substrate in the third subpixel P3 and the fourth subpixel P4 is the gate electrode 32 of the third transistor T3 in the third subpixel P3 and the fourth subpixel P4. There is an overlapping region between the orthographic projection of the second scanning connection line G2-1 on the base substrate and the orthographic projection of the third active layer 31 on the base substrate in the first subpixel P1 and the second subpixel P2. The overlapping region between the second scanning connection line G2-1 and the third active layer 31 on the base substrate in the first subpixel P1 and the second subpixel P2 is the gate electrode 32 of the third transistor T3 in the first subpixel P1 and the second subpixel P2.

[0095] In an exemplary embodiment, the first scanning signal line G1 has a single "U" shaped bend, and there is an overlapping region between the orthographic projection of the first scanning signal line G1 on the base substrate and the orthographic projection of the first active layer 11 on the base substrate in the third subpixel P3 and the fourth subpixel P4. The overlapping region between the first scanning signal line G1 and the first active layer 11 on the base substrate in the third subpixel P3 and the fourth subpixel P4 is the gate electrode 12 of the first transistor T1 in the third subpixel P3 and the fourth subpixel P4. There is an overlapping region between the orthographic projection of the first scanning connection line G1-1 on the base substrate and the orthographic projection of the first active layer 11 on the base substrate in the first subpixel P1 and the second subpixel P2. The overlapping region between the first scanning connection line G1-1 and the first active layer 11 on the base substrate in the first subpixel P1 and the second subpixel P2 is the gate electrode 12 of the first transistor T1 in the first subpixel P1 and the second subpixel P2.

[0096] In an exemplary embodiment, the second gate electrode 22 is provided across the second active layer 21 and is connected to the second electrode plate 42 to form an integrated structure.

[0097] In an exemplary embodiment, each display unit is provided with two vertical power connection lines 51, which are formed within a first sub-pixel P1 and a third sub-pixel P3 and have a stripe structure extending in a second direction D2. Within the first sub-pixel P1, the vertical power connection line 51 is located on the side of the second electrode plate 42 opposite to the first direction D1. Within the third sub-pixel P3, the vertical power connection line 51 is located on the side of the second electrode plate 42 opposite to the first direction D1. The vertical power connection lines 51 are configured to be connected to a later-formed first power line VDD to form a double wiring, ensuring the reliability of power signal transmission and reducing the resistance of the first power line.

[0098] In an exemplary embodiment, each display unit is provided with two lateral power connection lines 52, one of which is located above the pixel unit (i.e., on the side of the first subpixel P1 and second subpixel P2 away from the third subpixel P3 and fourth subpixel P4), and the other lateral power connection line 52 is located below the pixel unit (i.e., on the side of the third subpixel P3 and fourth subpixel P4 away from the first subpixel P1 and second subpixel P2). Each lateral power connection line 52 may be provided with a through hole, and there is an overlapping region between the orthographic projection of the through hole on the base substrate and the orthographic projection of the compensation signal line and the later-formed data signal line on the base substrate, and the through hole is configured to reduce parasitic capacitance between the lateral power connection line 52 and the data signal line and compensation signal line.

[0099] In an exemplary embodiment, the lateral power connection line 52 located above the pixel unit and the vertical power connection line 51 located within the first sub-pixel P1 may be connected to each other to form an integrated structure, and the lateral power connection line 52 located below the pixel unit and the vertical power connection line 51 located within the third sub-pixel P3 may be connected to each other to form an integrated structure.

[0100] In an exemplary embodiment, each display unit is provided with two auxiliary power lines 53, which are formed within a second sub-pixel P2 and a fourth sub-pixel P4 and have a stripe structure extending in a second direction D2. Within the second sub-pixel P2, the auxiliary power line 53 is located on the first direction D1 side of the second electrode plate 42. Within the fourth sub-pixel P4, the auxiliary power line 53 is located on the first direction D1 side of the second electrode plate 42. The auxiliary power lines 53 are configured to be electrically connected to a second power line that is formed later to form a double wiring, thereby ensuring the reliability of power signal transmission and reducing the resistance of the second power line.

[0101] In exemplary embodiments, the pattern of the second insulating layer 62 may be the same as the pattern of the second conductive layer, that is, the second insulating layer 62 is located below the second conductive layer (i.e., on the side of the second conductive layer closer to the base substrate), and the second insulating layer 62 is not present in areas other than the second conductive layer.

[0102] In the exemplary embodiment, the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the first subpixel P1 and the second subpixel P2 are mirror images symmetric with respect to the vertical axis, and the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 in the third subpixel P3 and the fourth subpixel P4 are mirror images symmetric with respect to the vertical axis.

[0103] In the exemplary embodiment, the process further includes a conduction treatment. The conduction treatment involves, after the second conductive layer pattern is formed, plasma treatment is performed using the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 as shielding, and the semiconductor layer in the region shielded by the first gate electrode 12, the second gate electrode 22, and the third gate electrode 32 (i.e., the region where the semiconductor layer overlaps with the first gate electrode 12, the second gate electrode 22, and the third gate electrode) is treated to become the channel region of the transistor, and the semiconductor layer in the region not shielded by the second conductive layer is treated to become a conduction layer, thereby forming a conductionized source-drain region.

[0104] Following this patterning process, the second conductive layer pattern is formed in the display area 100, and the transparent area 200 comprises the base substrate 10, a first insulating layer 61 and a second insulating layer 62 laminated on the base substrate 10, and a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62.

[0105] (4) Forming a third insulating layer pattern. Forming a third insulating layer pattern involves depositing a third insulating thin film on a base substrate on which the above-mentioned pattern is formed, patterning the third insulating thin film by a patterning process, and forming a third insulating layer 63 pattern that covers the above-mentioned structure. The third insulating layer 63 is provided with a plurality of through-hole patterns, and the plurality of through-hole patterns are, as shown in Figures 13 and 14, a first through-hole V1 and a second through-hole V2 located on both sides of the first gate electrode 12, a third through-hole V3 and a fourth through-hole V4 located on both sides of the second gate electrode 22, a fifth through-hole V5 and a sixth through-hole V6 located on both sides of the third gate electrode 32, and a third through-hole V2 located at the location of the auxiliary power line 53. The device comprises a plurality of seventh through-holes V7, an eighth through-hole V8 located at the location of the compensation connection line S-1, a ninth through-hole V9 located in the overlapping region of the first drain electrode 14 and the second electrode plate 42 which are formed later, a tenth through-hole V10 located on the first electrode plate 41 and overlapping with the opening region of the second electrode plate 42, a plurality of eleventh through-holes V11 located at the location of the vertical power supply connection line 51, a thirteenth through-hole V13 located at the location of the horizontal power supply connection line 52, a fourteenth through-hole V14 located at the location of the first scanning connection line G1-1, and a fifteenth through-hole V15 located at the location of the first scanning signal line G1. Figure 14 is a cross-sectional view in the AA direction in Figure 13.

[0106] The third insulating layer 63 in the first through-hole V1 and the second through-hole V2 is etched, exposing the surfaces of both ends of the first active layer 11. The third insulating layer 63 in the third through-hole V3 and the fourth through-hole V4 is etched, exposing the surfaces of both ends of the second active layer 21. The third insulating layer 63 in the fifth through-hole V5 and the sixth through-hole V6 is etched, exposing the surfaces of both ends of the third active layer 31. The seventh through-hole V7 is located where the auxiliary power line 53 is located, and multiple seventh through-holes V7 are provided at intervals, and the third insulating layer 63 in the seventh through-hole V7 is etched, exposing the surface of the auxiliary power line 53. The eighth through-hole V8 is located where the later-formed third source electrode 33 and the compensation connection line S-1 overlap, and the first insulating layer 61 and the third insulating layer 63 in the eighth through-hole V8 are etched, exposing the surface of the compensation connection line S-1. The ninth through-hole V9 is formed in the second electrode plate 42, and the third insulating layer 63 within the ninth through-hole V9 is etched, exposing the surface of the second electrode plate 42. The tenth through-hole V10 in the first sub-pixel P1 and the second sub-pixel P2 is located at the position of the third opening 47 of the second electrode plate 42, and the tenth through-hole V10 in the third sub-pixel P3 and the fourth sub-pixel P4 is located at the position of the fourth opening 48 of the second electrode plate 42, and the first insulating layer 61 and the third insulating layer 63 within the tenth through-hole V10 are etched, exposing the surface of the first electrode plate 41. The eleventh through-hole V11 is located at the position of the vertical power supply connection line 51, and multiple eleventh through-holes V11 are provided at intervals, and the third insulating layer 63 within the eleventh through-hole V11 is etched, exposing the surface of the vertical power supply connection line 51. The 13th through-hole V13 is located in the overlapping region between the lateral power supply connection line 52 and the second source electrode 23 that will be formed later. The third insulating layer 63 within the 13th through-hole V13 is etched, exposing the surface of the lateral power supply connection line 52. The 14th through-hole V14 is located in the overlapping region between the first scanning connection line G1-1 and the third scanning connection line 54 that will be formed later. The third insulating layer 63 within the 14th through-hole V14 is etched, exposing the surface of the first scanning connection line G1-1.The 15th through-hole V15 is located in the overlapping region between the first scan signal line G1 and the later formed third scan connection line 54. The third insulating layer 63 within the 15th through-hole V15 is etched, exposing the surface of the first scan signal line G1.

[0107] Following this patterning process, multiple through-hole patterns are formed in the display area 100, and the transparent area 200 comprises a first insulating layer 61 and a second insulating layer 62 stacked on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

[0108] (5) A third conductive layer pattern is formed, which includes depositing a third metal thin film on a base substrate on which the aforementioned pattern is formed, patterning the third metal thin film by a patterning process, and forming a third conductive layer pattern on the third insulating layer 63. As shown in Figures 15 and 16, the third conductive layer comprises one first power line VDD, one second power line VSS, four data signal lines D, two third scanning connection lines 54 formed on each display unit, as well as a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a pattern of a third electrode plate 43 formed on each subpixel, with Figure 16 being a cross-sectional view in the AA direction in Figure 15.

[0109] In an exemplary embodiment, the first power line VDD, the second power line VSS, the compensation signal line S, and the data signal line D are provided in parallel and all extend in the second direction D2, the second power line VSS is provided within the second sub-pixel P2 and the fourth sub-pixel P4, the first power line VDD is provided within the first sub-pixel P1 and the third sub-pixel P3, the compensation signal line S is provided midway between the first power line VDD and the second power line VSS, two data signal lines D are provided between the second power line VSS and the compensation signal line S, and the other two data signal lines D are provided between the first power line VDD and the compensation signal line S.

[0110] In an exemplary embodiment, the first power line VDD is connected to a longitudinal power connection line 51 and a transverse power connection line 52 via a plurality of 11th through-holes V11, the transverse power connection line 52 is connected to the second source electrode 23 of each subpixel via a 13th through-hole V13, the second source electrode 23 is connected to one end of the second active layer 21 via a third through-hole V3, and the connection between the second source electrode 23 and the first power line VDD is realized, forming a double wiring between the first power line VDD and the longitudinal power connection line 51, ensuring the reliability of power signal transmission and reducing the resistance of the first power line VDD.

[0111] In an exemplary embodiment, the second power line VSS is connected to the auxiliary power line 53 via a plurality of seventh through-holes V7, and the second power line VSS forms a double wiring with the auxiliary power line 53 to ensure the reliability of power signal transmission and reduce the resistance of the second power line VSS. In some possible implementations, the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the compensation signal line S in the first direction D1, and the widths of the first power line VDD and the second power line VSS in the first direction D1 are both greater than the width of the data signal line D in the first direction D1, which can further reduce the resistance of the first power line VDD and the second power line VSS.

[0112] In an exemplary embodiment, the compensation connection line S-1 is connected to the third source electrode 33 of each subpixel via an eighth through-hole V8. The compensation connection line S-1 is located in the center of the subpixels on both the upper and lower sides of the display area 100, and the compensation signal line S is located in the center of the subpixels on both the left and right sides of the display area 100. The compensation connection line S-1 and the compensation signal line S are connected to each other in an integrated structure, and the third transistors of the subpixels on both the left and right sides are located symmetrically with respect to the compensation signal line S. This symmetrical design allows each display unit to employ only one compensation signal line, ensuring that the RC delay before the compensation signal is written to the transistor is approximately the same, thereby ensuring uniformity of the display.

[0113] In an exemplary embodiment, the third scanning connection line 54 is a straight or broken line structure extending in the second direction D2, the third scanning connection line 54 is connected to the first scanning connection line G1-1 via the 14th through-hole V14, and the third scanning connection line 54 is connected to the first scanning signal line G1 via the 15th through-hole V15.

[0114] In the exemplary embodiment, the data signal line D of the first subpixel P1 is provided on the side of the first subpixel P1 closer to the first power line VDD, the data signal line D of the second subpixel P2 is provided on the side of the second subpixel P2 closer to the second power line VSS, the data signal line D of the third subpixel P3 is provided on the side of the third subpixel P3 closer to the compensation signal line S, and the data signal line D of the fourth subpixel P4 is provided on the side of the fourth subpixel P4 closer to the compensation signal line S.

[0115] In an exemplary embodiment, the first source electrode 13 is an integrated structure connected to the data signal line D, so that each data signal line D is connected to the first source electrode 13 of the subpixel in which it is located, the first source electrode 13 is connected to one end of the first active layer 11 via a first through-hole V1, the first drain electrode 14 is connected to the other end of the first active layer 11 via a second through-hole V2, the first drain electrode 14 is further connected to the second gate electrode 22 and the second electrode plate 42 via a ninth through-hole V9, so that the first drain electrode 14, the second gate electrode 22 and the second electrode plate 42 have the same potential. The second source electrode 23 is connected to one end of the second active layer 21 via the third through-hole V3 and to the lateral power supply connection line 52 via the thirteenth through-hole V13. The lateral power supply connection line 52 is connected to the first power supply line VDD via the eleventh through-hole V11, thereby realizing the connection between the second source electrode 23 and the first power supply line VDD. The second drain electrode 24 is connected to the other end of the second active layer 21 via the fourth through-hole V4. The third source electrode 33 is connected to one end of the third active layer 31 via the fifth through-hole V5 and to the compensation connection line S-1 via the eighth through-hole V8. The compensation connection line S-1 and the compensation signal line S are an integrated structure connected to each other, realizing the connection between the third source electrode 33 and the compensation signal line S. The third drain electrode 34 is connected to the other end of the third active layer 31 via the sixth through-hole V6. The second drain electrode 24, the third drain electrode 34, and the third electrode plate 43 are an integrated structure connected to each other. The third electrode plate 43 is connected to the first electrode plate 41 via the tenth through-hole V10. Therefore, the second drain electrode 24 is connected to the first electrode plate 41 and the third electrode plate 43, respectively, and the third drain electrode 34 is connected to the first electrode plate 41 and the third electrode plate 43, respectively. This ensures that the second drain electrode 24, the third drain electrode 34, the first electrode plate 41, and the third electrode plate 43 have the same potential. There is an overlap region between the orthographic projection of the third electrode plate 43 on the base substrate 10 and the orthographic projection of the second electrode plate 42 on the base substrate 10, and the third electrode plate 43 and the second electrode plate 42 form a second capacitor.

[0116] In an exemplary embodiment, the first source electrode 13, first drain electrode 14, second source electrode 23, second drain electrode 24, third source electrode 33, third drain electrode 34, and third electrode plate 43 in the first subpixel P1 and second subpixel P2 are mirror images symmetric with respect to the vertical axis, and the first source electrode 13, first drain electrode 14, second source electrode 23, second drain electrode 24, third source electrode 33, third drain electrode 34, and third electrode plate 43 in the third subpixel P3 and fourth subpixel P4 are mirror images symmetric with respect to the vertical axis.

[0117] Following this patterning process, a third conductive layer pattern is formed in the display area 100, and the transparent area 200 comprises a first insulating layer 61 and a second insulating layer 62 laminated on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, and a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2.

[0118] (6) Forming a fourth insulating layer and a flat layer pattern, which, as shown in Figures 17 and 18, first deposits a fourth insulating thin film on a base substrate on which the aforementioned pattern is formed, then coats a flat thin film, and etches the fourth insulating thin film by masking, exposure and development of the flat thin film to form a fourth insulating layer 64 pattern that covers the aforementioned structure and a flat (PLN) layer 65 pattern provided on the fourth insulating layer 64, wherein the fourth insulating layer 64 and the flat layer 65 are provided with a plurality of through-hole patterns, the plurality of through-hole patterns include at least a 16th through-hole V16 located at the position of the third electrode plate 43 in each subpixel of the display area 100 and a 17th through-hole V17 in the second power line VSS, Figure 18 is a cross-sectional view in the AA direction in Figure 17.

[0119] In an exemplary embodiment, the 16th through-hole V16 is located in the center of the third electrode plate 43, the 4th insulating layer 64 and the flat layer 65 in the 16th through-hole V16 are etched to expose the surface of the third electrode plate 43, and the 4th insulating layer 64 and the flat layer 65 in the 17th through-hole V17 are etched to expose the surface of the second power line VSS.

[0120] After this patterning process, the transparent region 200 comprises a first insulating layer 61 and a second insulating layer 62 laminated on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, and a fourth insulating layer 64 and a flat layer 65 provided on the third insulating layer 63.

[0121] (7) Forming a first transparent conductive layer pattern, which includes depositing a first transparent conductive thin film on a base substrate on which the aforementioned pattern is formed, as shown in Figures 19 and 20, patterning the first transparent conductive thin film by a patterning process to form a first transparent conductive layer pattern on a flat layer 65, the first transparent conductive layer comprising a first anode 70 and a first connecting electrode 81, the first anode 70 being formed in each subpixel of the display area 100, the first anode 70 in each subpixel being connected to the drain electrode of the second transistor T2 via a 16th through-hole V16 in the corresponding subpixel, the first connecting electrode 81 being formed at the location of a 17th through-hole V17 on the second power line VSS in the display area 100, the first connecting electrode 81 being connected to the second power line VSS via the 17th through-hole V17, Figure 20 being a cross-sectional view in the AA direction in Figure 19. Since the drain electrode of the second transistor T2, the drain electrode of the third transistor T3, and the third electrode plate 43 in each subpixel are connected to each other in an integrated structure, a connection is achieved between the first anode 70 and the drain electrode of the second transistor T2 in each subpixel. In an exemplary embodiment, four first anodes 70 can form a red light-emitting unit, a green light-emitting unit, a blue light-emitting unit, and a white light-emitting unit.

[0122] In an exemplary embodiment, the first anode 70 may comprise two individually provided sub-anode blocks and a connection structure connected to each of the two sub-anode blocks, with the two sub-anode blocks being interconnected by the connection structure. As shown in Figure 19, the connection structure may comprise a first connection electrode 701 and a second connection electrode 702, where the first connection electrode 701 has a "U" shape and both ends are connected to one of the two sub-anode blocks, and the second connection electrode 702 has one end connected to a drive transistor and the other end connected to the first connection electrode 701, thereby connecting the two sub-anode blocks to each other via the connection structure.

[0123] If a dark spot or bright spot appears in any one of the subpixels of the display panel, a portion of the first connecting electrode 701 in the connection structure can be laser-cut, thereby allowing one of the two sub-anode blocks from a single subpixel to be electrically connected to the drive transistor, while the other sub-anode block remains detached, thereby enabling the subpixel to be driven normally.

[0124] In an exemplary embodiment, four first anodes 70 are arranged in a square, with the upper left first anode 70 connected to the third electrode plate 43 of the first subpixel P1 via the 16th through-hole V16 of the first subpixel P1, the upper right first anode 70 connected to the third electrode plate 43 of the second subpixel P2 via the 16th through-hole V16 of the second subpixel P2, the lower left first anode 70 connected to the third electrode plate 43 of the third subpixel P3 via the 16th through-hole V16 of the third subpixel P3, and the lower right first anode 70 connected to the third electrode plate 43 of the fourth subpixel P4 via the 16th through-hole V16 of the fourth subpixel P4. In several possible implementations, the arrangement of the first anodes 70 within the display area 100 can be adjusted as needed, and this disclosure is not limited thereto.

[0125] After this patterning process, the transparent region 200 comprises a first insulating layer 61 and a second insulating layer 62 laminated on the base substrate 10, a first scanning signal line G1 and a second scanning signal line G2 provided on the second insulating layer 62, a third insulating layer 63 covering the first scanning signal line G1 and the second scanning signal line G2, and a fourth insulating layer 64 and a flat layer 65 provided on the third insulating layer 63.

[0126] (8) Forming an anode pattern. In exemplary embodiments, forming an anode pattern may include sequentially depositing a fourth metal thin film and a second transparent conductive thin film on a base substrate on which the aforementioned pattern is formed, patterning the fourth metal thin film and the second transparent conductive thin film by a patterning process to form patterns for a second anode 71, a third anode 72, a second connecting electrode 82, and a third connecting electrode 83, wherein the second anode 71 is provided on the side of the first anode 70 away from the base substrate and connected to the first anode 70, the third anode 72 is provided on the side of the second anode 71 away from the base substrate and connected to the second anode 71, the second connecting electrode 82 is provided on the side of the first connecting electrode 81 away from the base substrate and connected to the first connecting electrode 81, and the third connecting electrode 83 is provided on the side of the second connecting electrode 82 away from the base substrate and connected to the second connecting electrode 82. As shown in Figures 21 and 22, the stacked first anode 70, second anode 71, and third anode 72 constitute an anode 74, and the stacked first connecting electrode 81, second connecting electrode 82, and third connecting electrode 83 constitute auxiliary connecting electrodes. Figure 22 is a cross-sectional view in the AA direction in Figure 21.

[0127] In an exemplary embodiment, in a plane parallel to the display substrate, the shapes of the second anode 71 and the third anode 72 are similar to the shape of the first anode 70, and the orthographic projection of the second anode 71 on the base substrate may be located within the range of the orthographic projection of the first anode 70 on the base substrate, and the orthographic projection of the second anode 71 on the base substrate may be located within the range of the orthographic projection of the third anode 72 on the base substrate. In a plane parallel to the display substrate, the shapes of the second connecting electrode 82 and the third connecting electrode 83 are similar to the shape of the first connecting electrode 81, and the orthographic projection of the second connecting electrode 82 on the base substrate may be located within the range of the orthographic projection of the first connecting electrode 81 on the base substrate, and the orthographic projection of the second connecting electrode 82 on the base substrate may be located within the range of the orthographic projection of the third connecting electrode 83 on the base substrate.

[0128] In an exemplary embodiment, the first connecting electrode 81, located on the side adjacent to the base substrate (lower side) of the second connecting electrode 82 in a plane perpendicular to the display substrate, has an edge that protrudes from the contour of the second connecting electrode 82, forming a "pedestal" structure, and the third connecting electrode 83, located on the side away from the base substrate (upper side) of the second connecting electrode 82, has an edge that protrudes from the contour of the second connecting electrode 82, so that the first connecting electrode 81 and the third connecting electrode 83 form a "eaves" structure, thereby forming an "I" shape when stacked and installed.

[0129] In an exemplary embodiment, the first anode 70, located on the side adjacent to the base substrate (lower side) of the second anode 71, has an edge that protrudes from the contour of the second anode 71, forming a "pedestal" structure, and the third anode 72, located on the side away from the base substrate (upper side) of the second anode 71, has an edge that protrudes from the contour of the second anode 71, forming a "eaves" structure, thereby forming an "I" shape when the first anode 70, second anode 71, and third anode 72 are stacked together.

[0130] In exemplary embodiments, in the process of patterning the fourth metal thin film and the second transparent conductive thin film, etching may be performed using a first etching solution and a second etching solution, respectively, and a "I" shaped structure of the auxiliary electrode and anode may be formed using drill etching. In exemplary embodiments, the first etching solution may be an etching solution for etching transparent conductive materials (ITO etching solution), and the second etching solution may be an etching solution for etching metallic materials (Metal etching solution). In exemplary embodiments, after forming a photoresist pattern through photoresist masking, exposure, and development, the etching process may include first etching the second transparent conductive thin film not covered by the photoresist using an ITO etching solution to expose the fourth metal thin film in the area not covered by the photoresist and form a pattern for the third anode 72 and the third connecting electrode 83, and then etching the exposed fourth metal thin film using a Metal etching solution to form a pattern for the second anode 71 and the second connecting electrode 82. Since the etching rate of the fourth metal thin film by the metal etching solution is greater than the etching rates of the first transparent conductive thin film and the second transparent conductive thin film, the sides of the second anode 71 and the second connecting electrode 82 are etched to form concave pits. The first anode 70 below the second anode 71 and the third anode 72 above the second anode 71 both protrude one step from the second anode 71, and the first connecting electrode 81 below the second connecting electrode 82 and the third connecting electrode 83 above the second connecting electrode 82 also protrude one step from the second connecting electrode 82, forming an "I" shaped structure.

[0131] In exemplary embodiments, the material of the fourth metal thin film may include one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, and the second transparent conductive material may be indium tin oxide (ITO) or indium zinc oxide (IZO), etc.

[0132] (9) Forming a pixel definition layer pattern. In exemplary embodiments, forming a pixel definition layer pattern may include, as shown in Figures 23 and 24, applying a pixel definition thin film on a base substrate on which the aforementioned pattern is formed, patterning the pixel definition thin film by a patterning process, and forming a pixel definition (PDL) layer 91 pattern, wherein the pixel definition layer 91 is provided with a first pixel aperture K1 and a second auxiliary electrode aperture K2, the pixel definition layer 91 in the first pixel aperture K1 is removed, a portion of the surface of the third anode 72 of the anode is exposed, the pixel definition layer 91 in the second auxiliary electrode aperture K2 is removed, and all surfaces of the second connection electrode 82 and the third connection electrode 83 of the auxiliary connection electrode are exposed, and Figure 24 is a cross-sectional view in the AA direction in Figure 23.

[0133] In an exemplary embodiment, the orthographic projection of the first pixel aperture K1 on the base substrate lies within the range of the orthographic projection of the third anode 72 on the base substrate, the orthographic projection of the second auxiliary electrode aperture K2 on the base substrate lies within the range of the orthographic projection of the first connecting electrode 81 on the base substrate, and the orthographic projections of the second connecting electrode 82 and the third connecting electrode 83 on the base substrate lies within the range of the orthographic projection of the second auxiliary electrode aperture K2 on the base substrate. Exposure of all surfaces of the second connecting electrode 82 and the third connecting electrode 83 in the second auxiliary electrode aperture K2 means that the second auxiliary electrode aperture has a second lower opening adjacent to the base substrate and a second upper opening away from the base substrate, and the orthographic projections of the second connecting electrode 82 and the third connecting electrode 83 on the base substrate lies within the range of the orthographic projection of the second lower opening on the base substrate.

[0134] In exemplary embodiments, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. In a plane parallel to the display substrate, the shape of the first pixel aperture K1 may be similar to the shape of a plurality of anode blocks, and the shape of the second auxiliary electrode aperture K2 may be rectangular. In a plane perpendicular to the display substrate, the cross-sectional shapes of the first pixel aperture K1 and the second auxiliary electrode aperture K2 may be rectangular or trapezoidal, etc.

[0135] (10) Forming an organic light-emitting layer pattern. In an exemplary embodiment, forming an organic light-emitting layer pattern includes depositing an organic light-emitting material on a base substrate on which the aforementioned pattern is formed, as shown in Figure 25, to form an organic light-emitting layer 92 and an organic light-emitting block pattern, wherein the organic light-emitting layer 92 is provided in a region other than the third connecting electrode 83, the organic light-emitting layer 92 is connected to the third anode 72 in the anode 74 via the first pixel aperture K1, the organic light-emitting block is provided on the surface of the third connecting electrode 83 away from the base substrate, and the organic light-emitting block and the organic light-emitting layer 92 are provided in isolation.

[0136] In some other exemplary embodiments, the organic light-emitting layer pattern may be formed by an inkjet printing method, and the embodiments of this disclosure are not limited thereto.

[0137] In an exemplary embodiment, the "I" shaped structure of the auxiliary electrode causes the third connecting electrode 83 to protrude one step from the second connecting electrode 82. As a result, the organic light-emitting material is cut off at the side edge of the third connecting electrode 83, forming an organic light-emitting block on the second upper surface of the third connecting electrode 83, and forming an organic light-emitting layer 92 in the area other than the third connecting electrode 83, thereby achieving mutual isolation between the organic light-emitting layer 92 and the organic light-emitting block. In an exemplary embodiment, the orthographic projection of the organic light-emitting block on the base substrate may be approximately equal to the orthographic projection of the third connecting electrode 83 on the base substrate. The "I" shaped auxiliary electrode blocks the organic light-emitting layer, forming an isolated organic light-emitting block, effectively avoiding interference of the organic light-emitting block with the emitted light, improving the quality of the emitted light, and is advantageous for improving display quality.

[0138] In exemplary embodiments, the organic light-emitting layer may comprise an Emitting Layer (EML) and one or more of the following layers: a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Block Layer (EBL), a Hole Block Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In exemplary embodiments, the organic light-emitting layer may be formed by employing a Fine Metal Mask (FMM) or Open Mask deposition, or by employing an inkjet process.

[0139] In exemplary embodiments, the organic light-emitting layer may be manufactured by employing the following manufacturing method. First, an open mask is used to sequentially deposit a hole injection layer and a hole transport layer to form a common layer of the hole injection layer and hole transport layer on the display substrate. Then, a fine metal mask is used to deposit an electron barrier layer and a red light-emitting layer in the red subpixel, an electron barrier layer and a green light-emitting layer in the green subpixel, and an electron barrier layer and a blue light-emitting layer in the blue subpixel, with the electron barrier layers and light-emitting layers of adjacent subpixels having a small overlap (for example, the area of ​​the overlap portion in each light-emitting layer pattern is less than 10%), or they may be separated. Then, an open mask is used to sequentially deposit a hole barrier layer, an electron transport layer, and an electron injection layer to form a common layer of the hole barrier layer, an electron transport layer, and an electron injection layer on the display substrate.

[0140] In exemplary embodiments, the electron barrier layer may also serve as a microcavity adjustment layer for the light-emitting element, and by designing the thickness of the electron barrier layer, the thickness of the organic light-emitting layer between the cathode and anode can be made to satisfy the design of the microcavity length. In some exemplary embodiments, a hole transport layer, a hole barrier layer, or an electron transport layer in the organic light-emitting layer may be used as a microcavity adjustment layer for the light-emitting element, and this disclosure is not limited thereto.

[0141] In exemplary embodiments, the light-emitting layer may include a host material and a doped guest material, with a doping ratio of 1% to 20% of the guest material. Within this doping ratio range, the host material can effectively transfer exciton energy to the guest material to excite its emission, and the host material can "dilute" the guest material, effectively improving fluorescence quenching due to intermolecular and energy collisions, thereby improving luminescence efficiency and device lifetime. In exemplary embodiments, the doping ratio refers to the ratio of the mass of the guest material to the mass of the light-emitting layer, i.e., a mass percentage. In exemplary embodiments, the host material and guest material may be deposited together by a multi-source deposition process, and the host material and guest material may be uniformly dispersed in the light-emitting layer. The doping ratio may be adjusted by controlling the deposition rate of the guest material in the deposition process, or by controlling the deposition rate ratio between the host material and the guest material. In exemplary embodiments, the thickness of the light-emitting layer may be approximately 10 nm to 50 nm.

[0142] In exemplary embodiments, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, and may also be made of a strongly electron-absorbing p-type dopant and a hole transport material dopant. In exemplary embodiments, the thickness of the hole injection layer may be about 5 nm to 20 nm.

[0143] In exemplary embodiments, the hole transport layer may be made of a material with relatively high hole mobility, such as an aromatic amine compound, and its substituents may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan. In exemplary embodiments, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0144] In exemplary embodiments, the hole barrier layer and electron transport layer may be aromatic heterocyclic compounds, such as imidazole derivatives including benzimidazole derivatives, imidazopyridine derivatives, benzimidazolepyridine derivatives, pyrimidine derivatives, triazine derivatives, and other azine derivatives, quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives, and other compounds containing a nitrogen-containing six-membered ring structure (including compounds having phosphine oxide substituents on the heterocyclic ring). In exemplary embodiments, the thickness of the hole barrier layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.

[0145] In exemplary embodiments, the electron injection layer may be made of an alkali metal or metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals. In exemplary embodiments, the thickness of the electron injection layer may be approximately 0.5 nm to 2 nm.

[0146] (11) Forming a cathode pattern. In an exemplary embodiment, forming a cathode pattern may include depositing a cathode material onto a base substrate on which the aforementioned pattern is formed, as shown in Figure 26, to form a cathode 94 pattern, and the cathode 94 is connected to the organic light-emitting layer 92.

[0147] In exemplary embodiments, the cathodes 94 may be integral structures that communicate with each other. In areas other than the auxiliary connection electrodes, the cathodes 94 are provided in the organic light-emitting layer 92. In the areas where the auxiliary connection electrodes are located, the cathodes 94 are provided on one surface where the organic light-emitting block is exposed and on the other surface where the auxiliary connection electrodes are exposed, forming a structure that encloses the auxiliary connection electrodes and the organic light-emitting block.

[0148] Up to this point, the manufacturing of the light-emitting structure layer pattern in the drive circuit layer is complete. The light-emitting structure layer comprises an anode, an auxiliary connection electrode, a pixel definition layer, an organic light-emitting layer, and a cathode. The organic light-emitting layer is connected to the anode and cathode, respectively, the cathode is connected to the auxiliary connection electrode, and the auxiliary connection electrode is electrically connected to the second power line via the auxiliary cathode.

[0149] In exemplary embodiments, the manufacturing process for the display substrate may further include forming a package layer pattern, which may include first depositing a first inorganic thin film using plasma-enhanced chemical vapor deposition (PECVD) with an open mask to form a first package layer; then inkjet printing an organic material onto the first package layer using an inkjet printing process, curing it to form a film, and then forming a second package layer; and finally depositing a second inorganic thin film using an open mask to form a third package layer, so that the package layers are composed of the first package layer, the second package layer, and the third package layer. In exemplary embodiments, the first and third package layers may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), carbon silicon nitride (SiCN), and silicon nitrate (SiON), and may be single-layer, multi-layer, or composite layers. The second package layer may be made of a resin material to form an inorganic / organic / inorganic laminated structure, and the organic material layer is provided between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0150] In an exemplary embodiment, after the packaging layer is manufactured, a color filter layer and a black matrix may be manufactured on another substrate by a patterning process to form a color filter cover plate, a frame sealant may be applied to the surface of the color filter cover plate, and the color filter cover plate and the display substrate may be pressed together to form an OLED display panel as shown in Figure 5. In Figure 5, only the black matrix (BM) is shown, and the color filter layer is not shown. The black matrix has multiple aperture regions exhibiting a matrix arrangement, and the color filter layer is filled within the aperture regions.

[0151] In some other exemplary embodiments, the color filter layer and the black matrix may be manufactured on the display substrate, in which case they may be manufactured after the cathode is formed and before the package layer is formed. By providing a black matrix, optical crosstalk between adjacent subpixels can be effectively prevented, color mixing can be avoided and the display effect can be enhanced.

[0152] Referring to Figures 5 to 26, in each subpixel, a first transistor T1 is formed from a first active layer 11, a first gate electrode 12, a first source electrode 13, and a first drain electrode 14; a second transistor T2 is formed from a second active layer 21, a second gate electrode 22, a second source electrode 23, and a second drain electrode 24; a third transistor T3 is formed from a third active layer 31, a third gate electrode 32, a third source electrode 33, and a third drain electrode 34; a first capacitor is formed from a first plate 41 and a second plate 42; and a second capacitor is formed from a second plate 42 and a third plate 43. The first and second capacitors are in a parallel structure, and the potential of the second gate electrode 22 of the subpixel in which they are located is stored. The first transistor T1, second transistor T2, third transistor T3, first capacitor, and second capacitor in the first subpixel P1 and second subpixel P2 are mirror-image symmetric with respect to the compensation signal line S, and the first transistor T1, second transistor T2, third transistor T3, first capacitor, and second capacitor in the third subpixel P3 and fourth subpixel P4 are mirror-image symmetric with respect to the compensation signal line S.

[0153] In each subpixel, the first gate electrode 12 is connected to the first scan signal line G1, the first source electrode 13 is connected to the data signal line D, and the first drain electrode 14 is connected to the second gate electrode 22 of the subpixel in which it is located. The second gate electrode 22 is connected to the first drain electrode 14 of the subpixel in which it is located, the second source electrode 23 is connected to the first power line VDD via the lateral power supply connection line 52, and the second drain electrode 24 is connected to the anode of the subpixel in which it is located. The third gate electrode 32 is connected to the second scan signal line G2, the third source electrode 33 is connected to the compensation signal line S, and the third drain electrode 34 is connected to the second drain electrode 24 of the subpixel in which it is located. The first electrode plate 41 is connected to the second drain electrode 24 and the third drain electrode 34 of the subpixel in which it is located, the second electrode plate 42 is connected to the second gate electrode 22 and the first drain electrode 14 of the subpixel in which it is located, and the third electrode plate 43 is connected to the second drain electrode 24 and the third drain electrode 34 of the subpixel in which it is located. The anode 74 is connected to the second drain electrode 24 of the subpixel in which it is located, and the cathode 94 covering all subpixels is connected to the second power line VSS via an auxiliary connecting electrode, so that the organic light-emitting layer 92 between the anode 74 and the cathode 94 emits light of a corresponding brightness in response to the current in the second drain electrode 24 of the subpixel in which it is located.

[0154] In exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of one or more metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of one or more silicon oxide (SiOx), silicon nitride (SiNx), and silicon nitride (SiON), and may be a single-layer, multilayer, or composite layer. The first insulating layer is called the buffer layer and is used to enhance the hydrogen oxide resistance of the base substrate. The second insulating layer is called the gate insulating (GI) layer, the third insulating layer is called the interlayer insulating (ILD) layer, and the fourth insulating layer is called the passivation (PVX) layer. The thickness of the second insulating layer is smaller than the thickness of the third insulating layer, and the thickness of the first insulating layer is smaller than the combined thickness of the second and third insulating layers, thereby increasing the capacitance of the memory capacitor while ensuring insulation. The flat layer may be made of an organic material, the transparent conductive thin film may be made of indium tin oxide (ITO), indium tin ITO, or indium zinc oxide (IZO), and the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate. The cathode may be made of one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of one or more of the above metals.

[0155] In several possible implementations, the thickness of the first insulating layer is 3000 to 5000 angstroms, the thickness of the second insulating layer is 1000 to 2000 angstroms, the thickness of the third insulating layer is 4500 to 7000 angstroms, and the thickness of the fourth insulating layer is 3000 to 5000 angstroms. The thickness of the first conductive layer is 80 to 1200 angstroms, the thickness of the second conductive layer is 3000 to 5000 angstroms, and the thickness of the third conductive layer is 3000 to 9000 angstroms.

[0156] In exemplary embodiments, the semiconductor layer may be made of an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, an oxide containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0157] As shown in Figures 5 to 26, the display substrate provided in this disclosure is The device comprises a base substrate 10, a first conductive layer, a first insulating layer 61, a semiconductor layer, a second insulating layer 62, a second conductive layer, a third insulating layer 63, a third conductive layer, a fourth insulating layer 64, a flat layer 65, an anode 74, an auxiliary connecting electrode, a pixel definition layer 91, an organic light-emitting layer 92, an organic light-emitting block, a cathode 94, and a package layer. The first conductive layer is provided on the base substrate 10. The first conductive layer comprises a first electrode plate 41 and a compensation signal line S. The first insulating layer 61 covers the first conductive layer. The semiconductor layer is provided on the first insulating layer 61. The semiconductor layer comprises a first active layer 11, a second active layer 21, and a third active layer 31. The second conductive layer is provided on the second insulating layer 62. The second conductive layer comprises a first scanning signal line G1, a second scanning signal line G2, a second electrode plate 42, a vertical power supply connection line 51, a horizontal power supply connection line 52, an auxiliary power supply line 53, a first gate electrode 12, a second gate electrode 22, and a third gate electrode 32. The second insulating layer 62 has the same pattern as the second conductive layer, and there is an overlap region between the orthographic projection of the second electrode plate 42 on the base substrate 10 and the orthographic projection of the first electrode plate 41 on the base substrate 10, and the second electrode plate 42 and the first electrode plate 41 form a first capacitor. Furthermore, it comprises a third insulating layer 63 covering the second conductive layer, and multiple through-holes are provided on each of these layers. The third conductive layer is provided on the third insulating layer 63. The third conductive layer comprises a first power line VDD, a second power line VSS, a data signal line D, a third scanning connection line 54, a first source electrode 13, a first drain electrode 14, a second source electrode 23, a second drain electrode 24, a third source electrode 33, a third drain electrode 34, and a third electrode plate 43. The first power line VDD is connected to the vertical power connection line 51 and the horizontal power connection line 52 via the 11th through-hole V11, the second power line VSS is connected to the auxiliary power line 53 via the 7th through-hole V7, the first source electrode 13 is integrated with the data signal line D, the second source electrode 23 is connected to one end of the second active layer 21 via the third through-hole V3, the third source electrode 33 is connected to the compensation signal line S via the 8th through-hole V8, and the first drain electrode 14 is The second gate electrode 22 and the second electrode plate 42 are connected via a ninth through-hole V9. The second drain electrode 24, the third drain electrode 34, and the third electrode plate 43 are connected to each other in an integrated structure. The third electrode plate 43 is connected to the first electrode plate 41 via a tenth through-hole V10. There is an overlap region between the orthographic projection of the third electrode plate 43 on the base substrate 10 and the orthographic projection of the second electrode plate 42 on the base substrate 10. The second electrode plate 42 and the third electrode plate 43 form a second capacitor. The fourth insulating layer 64 and the flat layer 65 cover the third conductive layer. Multiple through-holes are provided on top of them. The anode 74 and auxiliary connecting electrodes are provided in the flat layer 65. The anode 74 comprises a stacked first anode 70, a second anode 71, and a third anode 72, and the auxiliary connecting electrodes comprises a stacked first connecting electrode 81, a second connecting electrode 82, and a third connecting electrode 83, with the first anode 70 connected to the drain electrode of the second transistor via the 16th through-hole V16, and the first connecting electrode 81 connected to the second power line VSS via the 17th through-hole V17. The pixel definition layer 91 is provided in the flat layer 65. The pixel definition layer 91 defines a first pixel aperture that exposes the anode in each subpixel, and the pixel definition layer 91 defines a second auxiliary electrode aperture that exposes the auxiliary connection electrode in the second power line VSS. The organic light-emitting layer 92 is provided within the first pixel aperture region. The organic light-emitting block is provided within the second auxiliary electrode aperture region. The organic light-emitting layer 92 is connected to the anode, and the organic light-emitting block and the organic light-emitting layer 92 are provided in isolation. The cathode 94 of the display area 100 is connected to the organic light-emitting layer 92, and the cathode of the transparent area is connected to the second power line VSS via an auxiliary connecting electrode. The package layer covers the structure described above.

[0158] In the embodiment of this disclosure, if a short-circuit fault occurs between a first scanning connection line and / or a second scanning connection line and other signal lines in the drive circuit layer, the short-circuit fault can be repaired by laser cutting the first scanning connection line and / or the second scanning connection line on both sides of the short-circuit fault. Exemplarily, as shown in Figure 27, if a short-circuit fault occurs at the overlap position between a data signal line and a first scanning connection line, the short-circuit fault can be repaired by laser cutting the first scanning connection line on both sides of the short-circuit fault.

[0159] As shown in Figure 28, in the embodiment of the present disclosure, if a short-circuit fault occurs between a sub-anode block and another signal line in the drive circuit layer, the first connecting electrode in the connection structure can be cut by a laser at the position on the sub-anode block side, thereby allowing another sub-anode block in the sub-pixel corresponding to the sub-anode block to be electrically connected to the drive transistor, causing the sub-anode block to float and thereby repairing the short-circuit fault.

[0160] The structures and manufacturing processes described herein are illustrative only, and in exemplary embodiments, the corresponding structures can be modified as needed in practice, and the patterning process can be increased or decreased. For example, the display area may comprise three subpixels. Also, for example, the pixel driving circuit may be 5T1C or 7T1C. Furthermore, for example, other electrodes or lead wires may be provided in the film layer structure, but this disclosure is not limited thereto.

[0161] As can be seen from the structure and manufacturing flow of the display board described above, the display board according to this disclosure has a ring winding design for the first scan signal line and the second scan signal line in the display area, respectively, with the ring winding positions of the first scan signal line and the second scan signal line avoiding the first power line and the second power line. This avoids the problem that can easily affect the yield rate of products due to a large overlap area between power lines and other signal lines, and optimizes the number of intersection points between signal lines to be minimized while realizing repair functionality, further improving the yield rate of products and providing technical support for transparent display products.

[0162] The display substrate according to this disclosure employs a second electrode plate made of a metal oxide material as the electrode plate of a memory capacitor. The second electrode plate forms a memory capacitor with the first electrode plate in the first conductive layer and the third electrode plate in the third conductive layer. The first electrode plate and the third electrode plate have the same potential, while the second electrode plate has a different potential from the first electrode plate and the third electrode plate. As a result, two parallel memory capacitors are formed between the first electrode plate, the second electrode plate, and the third electrode plate, which effectively increases the capacitance of the memory capacitor and is advantageous for realizing high-resolution displays.

[0163] The manufacturing process disclosed herein can be implemented using existing mature manufacturing equipment, requires minimal improvement over existing processes, is highly compatible with existing manufacturing processes, is easy to implement, boasts high production efficiency, low production costs, and a high yield rate. The design disclosed herein enables repair within subpixels, more than doubling the yield rate of the product.

[0164] In exemplary embodiments, the display substrate of the present disclosure can be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), etc., and the present disclosure is not limited thereto.

[0165] Exemplary embodiments of this disclosure further provide a method for manufacturing a display substrate, the display substrate may include a plurality of subpixels, and the manufacturing method is: Multiple display units are formed on the base substrate, at least one of the display units comprises a display area and a transparent area, at least one of the display areas is provided with a first power line and a second power line in a first direction, the first power line and the second power line extend in a second direction, at least one of the display areas is provided with a first scan signal line, a second scan signal line, a second scan connection line and a first scan connection line in the second direction, the second scan connection line and the second scan signal line are connected to each other to form a first ring structure, and at least one of the display areas is the first A third scanning connection line is provided between the scanning signal line and the first scanning connection line, and the third scanning connection line, the first scanning connection line, and the first scanning signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, the orthographic projection of the first ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate, and the orthographic projection of the second ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate.

[0166] The embodiments disclosed herein are as described above, but these are merely embodiments used to understand the disclosure and are not intended to limit the invention. Those skilled in the art may modify and change the form and details of the implementation without deviating from the spirit and scope disclosed herein, but the scope of patent protection of the invention should be limited to the scope set forth in the claims. [Explanation of Symbols]

[0167] 10 base boards 102 Drive circuit layer 103 Light-emitting structural layer 104 Packaging Layers

Claims

1. A display board comprising a base board and a plurality of display units provided on the base board, wherein each display unit comprises a display area and a transparent area, and the display area comprises a plurality of subpixels, The display area is provided with a first power line and a second power line in the first direction, the first power line and the second power line extend in the second direction, the display area is provided with a first scan signal line, a second scan signal line, a second scan connection line and a first scan connection line in the second direction, the second scan connection line and the second scan signal line are connected to each other to form a first ring structure, the display area is provided with a third scan connection line between the first scan signal line and the first scan connection line, the third scan connection line, the first scan connection line and the first scan signal line are connected to each other to form a second ring structure, the first direction and the second direction intersect, A display board in which the orthographic projection of the base substrate of the first ring structure does not overlap with the orthographic projection of the base substrate of the first power line and the second power line, and the orthographic projection of the base substrate of the second ring structure does not overlap with the orthographic projection of the base substrate of the first power line and the second power line.

2. The display substrate according to claim 1, wherein the orthographic projection on the base substrate of the first ring structure does not overlap with the orthographic projection on the base substrate of the second ring structure, and the orthographic projection on the base substrate of the second ring structure encloses the orthographic projection on the base substrate of the first ring structure.

3. In a direction perpendicular to the display substrate, the subpixel comprises a drive circuit layer provided on the base substrate and a light-emitting structure layer provided on the side of the drive circuit layer away from the base substrate, the drive circuit layer comprises a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer. The first conductive layer comprises a compensation signal line and a first electrode plate, the semiconductor layer comprises active layers of a plurality of transistors, the second conductive layer comprises a first scanning signal line, a second scanning signal line, a first scanning connection line, a second scanning connection line, a second electrode plate, and gate electrodes of a plurality of transistors, the third conductive layer comprises a first power line, a second power line, a third scanning connection line, a data signal line, and source electrodes and drain electrodes of a plurality of transistors, and there exists an overlap region between the orthographic projection of the second electrode plate on the base substrate and the orthographic projection of the first electrode plate on the base substrate, thereby forming a first capacitor. The second scanning connection line and the second scanning signal line are connected to each other to form an integrated structure. The display board according to claim 1, wherein the third scanning connection line is electrically connected to the first scanning connection line and the first scanning signal line, respectively, via through-holes.

4. At least one of the subpixels comprises a first transistor, a second transistor, a third transistor, and a first capacitor, wherein the first capacitor comprises a first plate and a second plate. The display substrate according to claim 1, wherein the gate electrode of the first transistor is electrically connected to the first scanning signal line, the first pole of the first transistor is electrically connected to the data signal line, the second pole of the first transistor is electrically connected to the gate electrode of the second transistor, the first pole of the second transistor is electrically connected to the first power line, the second pole of the second transistor is electrically connected to the first pole of the organic electroluminescent diode, the gate electrode of the third transistor is electrically connected to the second scanning signal line, the first pole of the third transistor is electrically connected to the compensation signal line, the second pole of the third transistor is electrically connected to the second pole of the second transistor, the second pole of the organic electroluminescent diode is electrically connected to the second power line, the first electrode plate is electrically connected to the second pole of the second transistor, and the second electrode plate is electrically connected to the gate electrode of the second transistor.

5. The plurality of subpixels include a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel, and in the first direction, the first subpixel and the second subpixel are arranged alternately to form a first row, the third subpixel and the fourth subpixel are arranged alternately to form a second row, in the second direction, the first subpixel and the third subpixel are arranged alternately to form a first column, and the second subpixel and the fourth subpixel are arranged alternately to form a second column. The display board according to claim 1, wherein the first scanning connection line and the second scanning connection line are located at the first subpixel and the second subpixel, and the first scanning signal line and the second scanning signal line are located at the third subpixel and the fourth subpixel.

6. At least one of the subpixels comprises a first transistor, a second transistor, and a third transistor, the first transistor comprising a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, the second transistor comprising a second active layer, a second gate electrode, a second source electrode, and a second drain electrode, and the third transistor comprising a third active layer, a third gate electrode, a third source electrode, and a third drain electrode, The region where the second scanning signal line and the third active layer in the third and fourth subpixels overlap is defined as the third gate electrode in the third and fourth subpixels, and the region where the second scanning connection line and the third active layer in the first and second subpixels overlap is defined as the third gate electrode in the first and second subpixels. The display substrate according to claim 5, wherein the region where the first scanning signal line and the first active layer in the third and fourth subpixels overlap is defined as the first gate electrode in the third and fourth subpixels, and the region where the first scanning connection line and the first active layer in the first and second subpixels overlap is defined as the first gate electrode in the first and second subpixels.

7. At least one of the display regions further comprises one compensation signal line, the compensation signal line extending in a second direction, The display substrate according to claim 6, wherein the first gate electrode, second gate electrode, and third gate electrode in the first subpixel and the second subpixel are mirror images symmetric with respect to the vertical axis, and the first gate electrode, second gate electrode, and third gate electrode in the third subpixel and the fourth subpixel are mirror images symmetric with respect to the vertical axis, and the vertical axis is the compensation signal line.

8. The compensation signal line is provided with compensation connection lines that protrude in a first direction and in the opposite direction to the first direction. The compensation connection lines are located at positions where the first subpixel and the third subpixel are adjacent, and at positions where the second subpixel and the fourth subpixel are adjacent. The display board according to claim 7, wherein the compensation connection line is electrically connected to the third source electrode of the third transistor via a through-hole.

9. The display substrate according to claim 8, wherein the third active layer in the first to fourth subpixels is provided in a position close to the compensation connection line, and there is an overlapping region between the orthographic projection of the third active layer on the base substrate and the orthographic projection of the compensation connection line on the base substrate.

10. The display substrate according to claim 8, wherein the third active layer in the first subpixel and the third active layer in the third subpixel are connected to each other in an integrated structure, and the third active layer in the second subpixel and the third active layer in the fourth subpixel are connected to each other in an integrated structure.

11. The display substrate according to claim 6, wherein at least one of the subpixels further comprises a first capacitor, the first capacitor comprising a first electrode plate and a second electrode plate installed opposite to each other, and the second gate electrode is provided across the second active layer and connected to the second electrode plate to form an integrated structure.

12. The first electrode plate in the first subpixel has a first aperture on the side that is close to the third subpixel and away from the second subpixel, and the first electrode plate in the second subpixel also has a first aperture on the side that is close to the fourth subpixel and away from the first subpixel. The first electrode plate in the third subpixel has a second aperture on the side that is close to the first subpixel and close to the fourth subpixel, and the first electrode plate in the fourth subpixel also has a second aperture on the side that is close to the second subpixel and close to the third subpixel. The display substrate according to claim 11, wherein the first active layer in the first subpixel and the second subpixel is provided in a position close to the first aperture, and the first active layer in the third subpixel and the fourth subpixel is provided in a position close to the second aperture.

13. The display board according to claim 11, wherein at least one of the subpixels further comprises a second capacitor, the second capacitor comprising a second electrode plate and a third electrode plate installed opposite to each other, the orthographic projection of the third electrode plate on the base substrate and the orthographic projection of the second electrode plate on the base substrate overlap, and the third electrode plate is electrically connected to the first electrode plate via through holes.

14. A display device comprising a display board according to any one of claims 1 to 13.

15. A method for manufacturing a display board, A method for manufacturing a display substrate, comprising: forming a plurality of display units on a base substrate; each display unit comprising a display area and a transparent area; the display area being provided with a first power line and a second power line in a first direction; the first power line and the second power line extending in a second direction; the display area being provided with a first scan signal line, a second scan signal line, a second scan connection line, and a first scan connection line in the second direction; the second scan connection line and the second scan signal line being connected to each other to form a first ring structure; the display area being provided with a third scan connection line between the first scan signal line and the first scan connection line; the third scan connection line, the first scan connection line, and the first scan signal line being connected to each other to form a second ring structure; the first direction and the second direction intersect; the orthographic projection of the first ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate; and the orthographic projection of the second ring structure on the base substrate does not overlap with the orthographic projection of the first power line and the second power line on the base substrate.

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