Semiconductor equipment

Abstract

To provide a semiconductor device formed by laminating a plurality of substrates, and prevent mixing of noise and a reduction in operation accuracy due to cross talk between the substrates.SOLUTION: A semiconductor device has a first substrate provided with a first circuit unit, and a second substrate provided with a second circuit unit connected with the first circuit unit and a third circuit unit connected with the second circuit unit. The second circuit unit supplies a drive potential to the first circuit unit, and at least part of the drive potential of the second circuit unit is supplied to the second circuit unit from the side of the first substrate.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] As semiconductor devices, logic devices such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), and memory devices such as a DRAM (Dynamic Random Access Memory) and a NVM (Non-Volatile Memory) are known. Further, as semiconductor devices, photoelectric conversion devices such as a CCD (Charge Coupled Device) sensor and a CMOS (Complementary Metal-Oxide-Semiconductor) sensor used in a digital still camera, a camcorder, or the like are known.

[0003] For these semiconductor devices, further miniaturization and high functionality are required to achieve higher performance and higher added value. For example, in a photoelectric conversion device, miniaturization of pixels is required to obtain a high-definition image. However, as the pixels are made finer, the light receiving area of the photoelectric conversion elements included in the pixels becomes smaller, and the sensitivity decreases. Further, when the control of the pixels and the processing of the pixel signals are complicated for high functionality, the circuits and signal lines for realizing them increase, and the light receiving area of the photoelectric conversion elements is further compressed.

[0004] Patent Document 1 describes a CMOS image sensor formed by laminating two substrates. In this image sensor, pixels and a readout circuit are arranged on a first substrate, and a control circuit for controlling pixels, a readout circuit, and the like is arranged on a second substrate. By configuring the image sensor in this way, the number of circuits on the first substrate can be reduced, and the compression of the area of the photoelectric conversion elements can be reduced. Further, by configuring so that pixels can be controlled for each predetermined block, high functionality of the photoelectric conversion device can be achieved.

Prior Art Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2012-151847 [Overview of the project] [Problems that the invention aims to solve]

[0006] In semiconductor devices with multiple stacked substrates, functional blocks such as pixels, readout circuits, and control circuits are distributed to each substrate, and power supply and input / output of various signals are performed between the substrates. However, in such a configuration, crosstalk can occur between one substrate and another. For example, power fluctuations on one substrate can affect the circuits on the other substrate, superimposing noise on the pixel signal and causing degradation of image quality and reduced operating accuracy of the circuits.

[0007] The object of the present invention is to provide a technology for suppressing noise interference and a decrease in operating accuracy caused by crosstalk between substrates in a semiconductor device comprising multiple stacked substrates. [Means for solving the problem]

[0008] According to one disclosure of this specification, the present invention comprises a first substrate on which a first circuit section is provided, a second substrate on which a second circuit section connected to the first circuit section is provided, a third circuit section connected to the second circuit section is provided, and a pad electrode to which the power supply voltage of the second circuit section is supplied, wherein the second circuit section is a circuit that supplies control signals to the first circuit section, and the power supply voltage of the second circuit section is, After propagating from the pad electrode through the first connection between the first substrate and the second substrate from the side of the second substrate to the side of the first substrate, the signal is transmitted through the second connection between the first substrate and the second substrate. A semiconductor device is provided that is supplied from the first substrate to the second circuit section.

[0009] Furthermore, according to another disclosure of this specification, the invention comprises a first substrate on which pixels that output pixel signals based on charge generated by a photoelectric conversion element and an amplifier that amplifies the pixel signals are disposed, a second substrate on which a first calculation unit that generates a control signal for controlling the gain of the amplifier and a first drive unit that drives the amplifier by shifting the level of the control signal to a level corresponding to the drive voltage of the amplifier, wherein the control signal is between the first substrate and the second substrate 1 The power supply voltage for driving the first drive unit is input from the first drive unit to the amplifier via the connection part and supplied to the pad electrodes provided on the second substrate. After being propagated from the second substrate side to the first substrate side via the second connection between the first substrate and the second substrate, between the first substrate and the second substrate Third A semiconductor device is provided that is supplied to the first drive unit from the side of the first substrate via a connection part. [Effects of the Invention]

[0010] According to the present invention, in a semiconductor device comprising multiple stacked substrates, it is possible to suppress the intrusion of noise and a decrease in operating accuracy caused by crosstalk between substrates. [Brief explanation of the drawing]

[0011] [Figure 1] This is a perspective view showing the overall configuration of an imaging device according to the first embodiment of the present invention. [Figure 2] This is a schematic plan view (part 1) showing the general configuration of an imaging device based on a reference example. [Figure 3] This is a schematic plan view (part 2) showing the general configuration of an imaging device based on a reference example. [Figure 4] This is an equivalent circuit diagram showing an example of pixel configuration in an imaging device. [Figure 5] This is an equivalent circuit diagram showing an example of an amplifier configuration in an imaging device. [Figure 6] This is a schematic diagram showing an example of the configuration of the connection section in an imaging device, based on a reference example. [Figure 7] This is a schematic plan view (part 1) showing the general configuration of an imaging device according to the first embodiment of the present invention. [Figure 8]It is a schematic plan view (part 2) showing the schematic configuration of an imaging device according to a first embodiment of the present invention. [Figure 9] It is a schematic diagram showing a configuration example of a connection part in an imaging device according to a first embodiment of the present invention. [Figure 10] It is a schematic plan view (part 1) showing the schematic configuration of an imaging device according to a second embodiment of the present invention. [Figure 11] It is a schematic plan view (part 2) showing the schematic configuration of an imaging device according to a second embodiment of the present invention. [Figure 12] It is a schematic diagram showing a configuration example of a connection part in an imaging device according to a second embodiment of the present invention. [Figure 13] It is a schematic plan view (part 1) showing the schematic configuration of an imaging device according to a third embodiment of the present invention. [Figure 14] It is a schematic plan view (part 2) showing the schematic configuration of an imaging device according to a third embodiment of the present invention. [Figure 15] It is a schematic diagram showing a configuration example of a connection part in an imaging device according to a third embodiment of the present invention. [Figure 16] It is a schematic plan view (part 1) showing the schematic configuration of an imaging device according to a fourth embodiment of the present invention. [Figure 17] It is a schematic plan view (part 2) showing the schematic configuration of an imaging device according to a fourth embodiment of the present invention. [Figure 18] It is a schematic diagram showing a configuration example of a connection part in an imaging device according to a fourth embodiment of the present invention. [Figure 19] It is a block diagram showing the schematic configuration of an imaging system according to a fifth embodiment of the present invention. [Figure 20] It is a diagram showing a configuration example of an imaging system and a moving body according to a sixth embodiment of the present invention. [Figure 21] It is a block diagram showing the schematic configuration of a device according to a seventh embodiment of the present invention.

Embodiments for Carrying Out the Invention

[0012] Embodiments of the present invention will be described below with reference to the drawings. In the embodiments described below, an imaging device will be described as an example of a semiconductor device. However, the semiconductor device to which the configuration of each embodiment can be applied is not limited to an imaging device, but can also be applied to other examples of semiconductor devices. Examples of semiconductor devices to which the present invention can be applied include logic devices such as CPUs and GPUs, memory devices such as DRAMs and NVMs, and photoelectric converters. Examples of photoelectric converters include the imaging device described below, distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight), etc.), and photometric devices (devices for measuring the amount of incident light, etc.).

[0013] [First Embodiment] The overall configuration of the imaging device according to the first embodiment of the present invention will be described with reference to Figure 1. Figure 1 is a perspective view showing the schematic configuration of the imaging device according to this embodiment.

[0014] The imaging device 1000 according to this embodiment has a first substrate 10 and a second substrate 20, as shown in Figure 1. In Figure 1, the first substrate 10 and the second substrate 20 are shown separately for clarity, but in reality, the first substrate 10 and the second substrate 20 are laminated and bonded together to form a single integrated imaging device 1000.

[0015] The method for bonding the first substrate 10 and the second substrate 20 is not particularly limited, but here, the first substrate 10 and the second substrate 20 are joined by a metal joint between a metal member disposed in the insulating layer of the first substrate 10 and a metal member disposed in the insulating layer of the second substrate 20. In Figure 1, this metal joint is shown as a connection part 400. The first substrate 10 and the second substrate 20 can also be joined electrically and physically using bump electrodes.

[0016] Multiple pad electrodes 300 are arranged on the surface of the second substrate 20. Multiple openings 200 are provided in the first substrate 10 corresponding to the positions of the multiple pad electrodes 300. The openings 200 are provided so as to penetrate the first substrate 10, and when the first substrate 10 and the second substrate 20 are joined, the pad electrodes 300 are exposed within the openings 200. An electrical connection is made between the imaging device and an external device by connecting a bonding wire (not shown) to the pad electrodes 300 exposed within the openings 200.

[0017] Next, before describing the imaging device according to this embodiment, the schematic configuration of the imaging device according to a reference example of this embodiment will be described with reference to Figures 2 to 6. Figures 2 and 3 are schematic plan views showing the schematic configuration of the imaging device according to the reference example. Figure 4 is an equivalent circuit diagram showing an example of pixel configuration. Figure 5 is an equivalent circuit diagram showing an example of amplifier configuration. Figure 6 is a circuit diagram showing the connection relationship between the amplifier and the signal processing control unit in the imaging device according to the reference example.

[0018] Figure 2 shows the planar layout of the first substrate 10. Figure 3 shows the planar layout of the second substrate 20. In this reference example, it is assumed that the pixel section and analog circuits that mainly process pixel signals are arranged on the first substrate 10, and circuits that mainly generate timing to drive the circuits arranged on the first substrate 10 and circuits that process digital signals are arranged on the second substrate 20. Furthermore, each circuit arranged on the first substrate 10 and the second substrate 20 is configured to be connected to an appropriate power supply according to its classification, such as whether it is an analog circuit or a digital circuit, and the operating voltage of each circuit.

[0019] It should be noted that the arrangement of these functional blocks is not limited to the example described in this reference example. For example, the first substrate 10 may consist only of the pixel section 100, or it may consist of circuits related to timing generation and some circuits that process digital signals.

[0020] As described above, the second substrate 20 has multiple pad electrodes 300 arranged on it, and an electrical connection is made between it and an external device via bonding wires. Therefore, the first substrate 10 is provided with openings 200 for connecting wiring to the pad electrodes 300 by wire bonding, in accordance with the positions of the pad electrodes 300 on the second substrate 20. Figure 2 shows multiple openings 200 provided on the first substrate 10 to illustrate the relationship with the positions of the pad electrodes 300 arranged on the second substrate 20. The openings 200-1 to 200-12 shown in Figure 2 correspond to the pad electrodes 300-1 to 300-12 provided on the second substrate 20. The same applies to the openings 200-13 to 200-17 and the pad electrodes 300-13 to 300-17, which will be described in a later embodiment.

[0021] Furthermore, the first substrate 10 and the second substrate 20 are electrically connected via a plurality of connection points 400. Each of these connection points 400 is located at the same coordinate on the planar layout of both the first substrate 10 and the second substrate 20. In the following description, the same reference numeral will be used to denote each of the plurality of connection points 400, whether it is located on the first substrate 10 or on the second substrate 20. In addition, each of the plurality of connection points 400 will be distinguished by a sub-number attached to the reference numeral 400. For example, connection point 400-1 is a connection point 400 located at the same coordinate on the planar layout of both the first substrate 10 and the second substrate 20, and is located at a different coordinate than connection point 400-2. Furthermore, when describing multiple connection points 400 in common, the reference numeral will be used without the sub-number. For example, when "connection point 400" is written, it refers to a plurality of connection points 400-n (where n is a natural number).

[0022] In the drawings of this application, wiring and connection points 400 are represented as single elements, but in reality, a single wiring or connection point 400 in the drawings may be composed of multiple wirings or multiple connection points 400, such as multiple power lines, multiple grounding lines, or multiple control lines. Furthermore, even when the same power or signal is supplied, multiple connection points 400 may be provided to reduce resistance or provide redundancy. In the following description, even if multiple wirings or connection points are provided, they may be omitted in order to simplify the drawings and descriptions.

[0023] In Figures 2 and 3, the components, wiring, and connection parts 400 are shown in a configuration where they do not physically overlap in a plan view; however, some of these may overlap in a plan view. For example, the connection part 400 may be positioned to overlap with other components in a plan view.

[0024] Between the first substrate 10 and the second substrate 20, drive signals for controlling the pixels 101 and the circuits that process the pixel signals, and the processed pixel signals are transmitted via a plurality of connection parts 400. First, the components arranged on the first substrate 10 will be described, and then, in the configuration with the substrates bonded together, the components arranged on the second substrate 20 and the signal transmission, control, and driving between the substrates will be described.

[0025] First, the configuration of the first substrate 10 will be explained using Figures 2, 4, and 5. The first substrate 10 may be provided with, for example, a plurality of openings 200 and a plurality of connection parts 400, as well as a pixel part 100, a pixel control part 120, a signal processing part 500, a reference voltage generation part 600, and an output part 700, as shown in Figure 2.

[0026] The pixel unit 100 is provided with multiple pixels 101 arranged in a matrix across multiple rows and columns. Each pixel 101 includes a photoelectric conversion element such as a photodiode, which converts an optical signal into an electrical signal and outputs it. In this reference example, the pixel unit 100 is provided with multiple pixel blocks, each containing multiple pixels 101, and the drive control of the pixels 101 can be performed at the unit level of these pixel blocks. Here, as shown by the dotted lines in Figure 2, the pixel unit 100 is divided into a total of 64 pixel blocks in an 8x8 grid. The number of pixel blocks included in the pixel unit 100, the way the pixel blocks are divided, and the number of pixels 101 included in each pixel block can be changed as appropriate. By configuring the multiple pixels 101 arranged in two dimensions to be controllable at the unit level of pixel blocks, it becomes possible to perform optimal control for each pixel block according to the brightness of the subject.

[0027] Each pixel 101 may be configured to include, for example, a photoelectric conversion element 102, a transfer transistor 103, a reset transistor 104, an amplification transistor 105, and a selection transistor 106, as shown in Figure 4.

[0028] The photoelectric conversion element 102 is, for example, a photodiode, with its anode connected to a reference voltage line (reference voltage GND) and its cathode connected to the source of the transfer transistor 103. The drain of the transfer transistor 103 is connected to the source of the reset transistor 104 and the gate of the amplification transistor 105. The node to which the drain of the transfer transistor 103, the source of the reset transistor 104, and the gate of the amplification transistor 105 are connected is a so-called floating diffusion section (FD). The floating diffusion section FD includes a capacitive component (floating diffusion capacitance) and functions as a charge holding section. The floating diffusion capacitance may include pn junction capacitance and wiring capacitance. The drain of the reset transistor 104 and the drain of the amplification transistor 105 are connected to a power supply voltage line (power supply voltage VDD). The source of the amplification transistor 105 is connected to the drain of the selection transistor 106. The source of the selection transistor 106 is connected to the output line 107.

[0029] Each pixel 101 is controlled by a control signal supplied from the pixel control unit 120 via a pixel control line 121 provided in each row. In the pixel configuration shown in Figure 4, the pixel control line 121 includes a signal line connected to the gate of the transfer transistor 103, a signal line connected to the gate of the reset transistor 104, and a signal line connected to the gate of the selection transistor 106. The gate of the transfer transistor 103 is supplied with a control signal PTX from the pixel control unit 120 via this signal line. The gate of the reset transistor 104 is supplied with a control signal PRES from the pixel control unit 120 via this signal line. The gate of the selection transistor 106 is supplied with a control signal PSEL from the pixel control unit 120 via this signal line. When each transistor is composed of an N-type MOS transistor, a high-level control signal supplied from the pixel control unit 120 turns the corresponding transistor ON. Conversely, a low-level control signal supplied from the pixel control unit 120 turns the corresponding transistor OFF.

[0030] Output lines 107 are signal lines provided in each row of the pixel section 100. Each output line 107 is connected to multiple pixels 101 located in the corresponding row. The power supply voltage line that supplies the power supply voltage VDD and the reference voltage line that supplies the reference voltage GND are included in the power supply line 108. In Figure 2, for the sake of simplicity, the power supply line 108 is shown as a single signal line. The same notation will be used for other power supply lines below. When distinguishing between power supply voltage lines and reference voltage lines, a sub-number will be added, such as power supply line 108-1 for power supply voltage lines and power supply line 108-2 for ground voltage lines.

[0031] The pixel control unit 120 is a control circuit that supplies control signals for controlling the pixels 101 to the pixel unit 100 via the pixel control line 121. In Figure 2, for the sake of simplicity, the pixel control line 121 is shown as a single signal line, but the pixel control line 121 includes multiple signal lines, including signal lines for supplying control signals PTX, PRES, and PSEL. Also, although the reference numerals are omitted in Figure 2, the pixel control line 121 is arranged for each of the 8x8 pixel blocks. The control signals supplied via the pixel control line 121 may be intended for control of each pixel, control of each row of pixels, or control of each pixel block.

[0032] The pixel signal output from the pixel unit 100 is input to the signal processing unit 500 via wiring 503. The signal processing unit 500 has processing circuits for performing predetermined signal processing on the pixel signal output from the pixel unit 100. The signal processing unit 500 includes multiple processing circuits corresponding to each row of the pixel block of the pixel unit 100 and is configured to be controllable on a block-by-block basis.

[0033] The signal processing unit 500 may include a constant current circuit. The amplification transistor 105 of the pixel 101 is supplied with bias current from this constant current circuit via wiring 503, output line 107, and selection transistor 106, thus forming a source follower circuit. With this source follower circuit configured, a pixel signal corresponding to the amount of charge generated by the photoelectric conversion element 102 is output from the pixel unit 100. The output signal from the source follower circuit may be amplified by an amplifier 501 provided in each of the multiple processing circuits of the signal processing unit 500.

[0034] The amplifier 501 may consist of an amplification circuit 502, an input capacitor C0, feedback capacitors C1 and C2, and switches M0 and M1, as shown in Figure 5, for example. The input node of the amplification circuit 502 is connected to wiring 503 via the input capacitor C0. The output node of the amplification circuit 502 is connected to the amplification signal output line 504. Between the input node and the output node of the amplification circuit 502, a switch M0, a capacitor C1, and a series connection of capacitor C2 and switch M1 are connected in parallel. Switch M0 is controlled by a control signal supplied via the reset control line 505. Switch M1 is controlled by a control signal supplied via the gain control line 506. If the amplification circuit 502 is an inverting amplifier circuit, the voltage amplification factor of the amplifier 501 is expressed as -(input capacitor (C0) / feedback capacitors (C1, C2)). In a system where negative feedback is applied to the amplification circuit 502, the voltage amplification factor, which is determined by the voltage division ratio between the feedback capacitances C1 and C2 and the input capacitance C0, can be switched by selecting either feedback capacitance C1 or C1+C2 using switch M1.

[0035] Switch M0 is a switch that short-circuits the input node and output node of the amplification circuit 502, and when turned on, it resets the amplifier 501. The amplifier 501 is reset before it performs the pixel signal readout and amplification operations. After the reset of the amplifier 501 is released, the pixel signal output from the source follower circuit is amplified at a predetermined voltage amplification factor set in the amplifier 501 and output from the amplified signal output line 504. That is, when switch M1 is off, the pixel signal is amplified at a voltage amplification factor of -C0 / C1 and output from the amplified signal output line 504. When switch M1 is on, the pixel signal is amplified at a voltage amplification factor of -C0 / (C1+C2) and output from the amplified signal output line 504. In this reference example, there is one type of input capacitance (C0) and two types of feedback capacitances (C1, C2), but the number of input capacitances and / or feedback capacitances may be increased to allow setting more types of voltage amplification factors.

[0036] The signal processing unit 500 may include multiple signal processing functions, including an amplifier 501. For example, the signal processing unit 500 may further include a function to perform analog-to-digital (A / D) conversion of the pixel signal amplified by the amplifier 501. The signal processing unit 500 may also further include a digital memory for holding the A / D conversion results and a scanning circuit for sequentially reading the digital data held in the digital memory. Other functions that the signal processing unit 500 may have include, for example, a function to perform correction processing using CDS (Correlated Double Sampling) and a function to sample and hold (S / H) the pixel signal. The signal processing unit 500 is supplied with a power supply voltage and a reference voltage GND via a power supply line 507. Note that in Figure 2, for the sake of simplifying the drawing, components other than the amplifier 501 are omitted from the description.

[0037] The signal processing unit 500 is controlled by control signals input via control lines 510, 515, and 516, and by control signals generated in the signal processing control unit 511 and input via the reset control line 505. Here, the signal processing control unit 511 has a function to generate a reset control signal for controlling the reset operation of the amplifier 501. The signal processing control unit 511 generates the reset control signal based on a control signal input via control line 512 from the drive timing control unit 900 located on the second board 20, which will be described later.

[0038] Here, the operating voltage of some circuits included in the signal processing unit 500 may differ from the operating voltage of the drive timing control unit 900. For example, the drive timing control unit 900 is classified as a digital circuit, handles small signal amplitudes, and operates at a low voltage (let's call it voltage V1) to reduce power consumption. On the other hand, some circuits included in the signal processing unit 500 handle large signal amplitudes and require a wide input / output range, so they operate at a higher voltage (let's call it voltage V2) than voltage V1. In this reference example, the amplifier 501 that amplifies the pixel signal requires a wide output range, so the operating voltage of the amplifier 501 is set to voltage V2. The signal processing control unit 511 is supplied with the same power supply voltage V1 and reference voltage as the drive timing control unit 900 via power line 513, and the same power supply voltage V2 and reference voltage as the signal processing unit 500 are supplied via power line 507. The signal processing control unit 511 converts a control signal with a signal amplitude corresponding to the voltage V1 input from the drive timing control unit 900 into a control signal with a signal amplitude corresponding to the voltage V2, which is the drive voltage of the amplifier 501, and generates a reset control signal for driving the amplifier 501.

[0039] The reference voltage generation unit 600 generates a reference voltage for driving the pixel unit 100. The reference voltage generation unit 600 is supplied with a power supply voltage and a reference voltage GND via a power supply line 601. The reference voltage generation unit 600 is also supplied with control signals via a control line 602 to control the settings of the voltage to be generated, etc. The reference voltage generation unit 600 also outputs the generated voltage via an output line 603.

[0040] The output unit 700 has the function of processing a digital signal based on the pixel signal processed by the signal processing unit 500 and outputting it to the outside of the imaging device. Digital data processed by the signal processing unit 500 is input to the output unit 700 via the signal input line 701. Power supply voltage and reference voltage GND are also supplied to the output unit 700 via the power supply line 702. The data processed by the output unit 700 is output to the outside of the imaging device via the output line 703, connection unit 400-10, wiring 810 and pad electrode 300-10. The data output method may be, for example, a method that outputs voltage from a single terminal, such as a buffer circuit, or an LVDS (Low Voltage Differential Signaling) method with two differential terminals. If the digital signal input to the output unit 700 is parallel data, the output unit 700 may have a parallel-to-serial converter (P / S converter).

[0041] Next, the configuration of the second substrate 20 and the signal transmission and control relationships between it and the first substrate 10 via the connection portion 400 will be explained using Figure 3. As shown in Figure 3, the second substrate 20 may be provided with a plurality of pad electrodes 300 and a plurality of connection portions 400, as well as a drive timing control unit 900, a pixel control unit 904, and a signal processing control unit 917. Furthermore, the second substrate 20 may be provided with a signal processing control unit 930, a signal processing drive control unit 931, and a digital signal processing unit 940.

[0042] The pad electrode 300-1 is supplied with the power supply voltage and reference voltage GND from outside the imaging device to the pixel unit 100. In Figure 3, for the sake of simplicity, the power supply pad to which the power supply voltage and reference voltage GND are supplied is represented by a single pad electrode 300-1, similar to the case of the power supply line. The pad electrode 300-1 is electrically connected to the pixel unit 100 via the power supply line 801, the connection part 400-1, and the power supply line 108.

[0043] The drive timing control unit 900 is a control circuit that controls the entire imaging device. The drive timing control unit 900 is supplied with the power supply voltage V1 and the reference voltage GND from the pad electrodes 300-4 via the power supply line 804. Control lines 901, 902, 903, 914, 915, and 916 are connected to the drive timing control unit 900.

[0044] Control lines 901, 902, and 903 are wirings that transmit control signals related to the control of the pixel unit 100. Control line 901 is connected to the pixel control unit 120 via connection part 400-20 and wiring 123. Control line 902 is connected to the pixel unit 100 via connection part 400-21 and pixel control line 122.

[0045] In this reference example, the multiple pixels 101 arranged in the pixel section 100 are controlled in units of pixel blocks. An example of operation controlled in units of pixel blocks is the control of the storage time of pixels 101. In this reference example, connection sections 400-50 are provided in the pixel section 100, and the storage time of each pixel block can be controlled via these connection sections 400-50. A pixel control unit 904 and a connection section 400-50 are arranged at the positions corresponding to each pixel block. The pixel control unit 904 is connected to the pixels 101 via wiring 905, connection section 400-50, and wiring 130. The pixel control unit 904 is supplied with a control signal from the drive timing control unit 900 via control line 903. The pixel control unit 904 generates a storage time control signal to control the storage time of the pixels 101 belonging to that pixel block in response to the control signal from the drive timing control unit 900. The accumulation time control signal generated by the pixel control unit 904 is supplied to the pixel 101 via wiring 905, connection parts 400-50, and wiring 130.

[0046] Note that in Figures 2 and 3, for the sake of simplifying the drawings, the pixel control unit 904 and connection unit 400-50 are shown in only one pixel block, but the pixel control unit 904 and connection unit 400-50 are provided in all pixel blocks. Furthermore, the storage time in the pixel unit 100 may be controlled not only by the pixel control unit 904, but also by the drive timing control unit 900 and the pixel control unit 120. Similarly, other operations related to the pixel 101 may be controlled by any of the drive timing control unit 900, the pixel control unit 120, and the pixel control unit 904.

[0047] Control lines 914, 915, and 916 are wirings that transmit control signals related to the control of the signal processing unit 500. Control line 914 is connected to the signal processing unit 500 via connection part 400-30 and control line 510. Control line 915 is connected to the signal processing control unit 511 via connection part 400-31 and control line 512. Control line 916 is connected to the signal processing control unit 917. The signal processing control unit 917 has the same functions as the signal processing control unit 511 located on the first board 10. The signal processing control unit 917 is supplied with a power supply voltage V1 and a reference voltage GND from pad electrode 300-4 via power line 804, and with a power supply voltage V2 and a reference voltage GND from pad electrode 300-6 via power line 806. The signal processing control unit 917 is connected to the signal processing unit 500 via control line 918, connection part 400-32, and control line 515. The control signal generated by the signal processing control unit 917 is input to the signal processing unit 500 via control line 918, connection unit 400-32, and control line 515.

[0048] In this reference example, as mentioned above, the pixels 101 are controlled in units of pixel blocks containing multiple pixels 101. In this reference example, the signal processing unit 500 is also configured to control the drive of each block according to the pixel block unit. In Figure 3, the units of blocks constituting the signal processing unit 500 are shown with dotted lines, just like the pixel unit 100. A signal processing control unit 930 and connection units 400-33 are located at the positions corresponding to each block of the signal processing unit 500. An example of an operation controlled at the block level is the control of the voltage amplification factor in the amplifier 501. Other controls include the control of the drive current of the amplification circuit 502, and power-on and power-down controls.

[0049] The signal processing drive control unit 931 has a function to control the voltage amplification factor of the amplifier 501. The signal processing drive control unit 931 is supplied with a power supply voltage V1 and a reference voltage GND from the pad electrodes 300-4 via the power supply line 804. The signal processing drive control unit 931 is connected to the signal processing control unit 930 via the control line 932. The signal processing control unit 930 is connected to the amplifier 501 via wiring 933, connection part 400-33 and gain control line 506. The signal processing control unit 930 receives a control signal via the control line 932 to control the voltage amplification factor for each block generated by the signal processing drive control unit 931. The voltage amplification factor for each block can be controlled according to, for example, the storage time controlled for each pixel block, the voltage conversion rate of the readout charge, the light intensity of the subject, etc.

[0050] The signal processing control unit 930 has the same functions as the signal processing control units 511 and 917. The signal processing control unit 930 is supplied with the power supply voltage V1 and the reference voltage GND from the pad electrode 300-4 via the power supply line 804, and the power supply voltage V2 and the reference voltage GND from the pad electrode 300-6 via the power supply line 806. The control signal for the voltage amplification factor generated by the signal processing control unit 930 is supplied to the amplifier 501 via the wiring 933, the connection part 400-33, and the gain control line 506.

[0051] The digital signal processing unit 940 has the function of performing various digital signal processing on the digital signal held by the signal processing unit 500, such as noise reduction processing, digital gain processing, offset addition / subtraction, compression processing, and data scrambling processing. The digital signal processing unit 940 is supplied with a power supply voltage V1 and a reference voltage GND from the pad electrode 300-8 via the power line 808. The digital signal processing unit 940 may also require a clock signal of a certain frequency for signal processing operation. In this reference example, the clock signal is supplied from an external source, and this clock signal is supplied to the digital signal processing unit 940 from the pad electrode 300-11 via wiring 811. Although not shown in Figure 3, other control signals may be supplied to the digital signal processing unit 940, such as control signals from outside the imaging device, for example, serial communication from an external controller (not shown). The same applies to the drive timing control unit 900 and the signal processing drive control unit 931 described earlier.

[0052] The pixel signals converted by A / D in the signal processing unit 500 are stored in the digital memory of the signal processing unit 500. The digital signal processing unit 940 inputs a selection signal to the signal processing unit 500 via control line 941, connection unit 400-34, and control line 516 to select the digital memory from which to read the digital signal. The signal processing unit 500 reads the digital signal held in the selected digital memory to the digital signal processing unit 940 via output line 517, connection unit 400-35, and wiring 942. The voltage amplitude of the digital signal is an amplitude based on voltage V1. The pixel signals processed digitally in the digital signal processing unit 940 are output to the outside of the imaging device via wiring 943, connection unit 400-36, signal input line 701, and output unit 700.

[0053] The reference voltage generation unit 600, located on the first substrate 10, is supplied with power supply voltage and reference voltage GND from the pad electrode 300-2 via power line 802, connection part 400-2, and power line 601. The reference voltage generation unit 600 also receives control signals from the drive timing control unit 900 via wiring 911, connection part 400-40, and control line 602. The voltage generated by the reference voltage generation unit 600 is supplied to the pixel control unit 120 via output line 603 and also output to the outside of the imaging device via output line 603, connection part 400-3, wiring 803, and pad electrode 300-3. The pad electrode 300-3 serves as a test terminal for testing that the reference voltage generation unit 600 is generating the desired voltage, and as an electrode for reference voltage input when the reference voltage is input from an external source. Furthermore, by connecting a capacitor to the outside of the imaging device, fluctuations in the reference voltage due to the operation of the imaging device can be suppressed.

[0054] Figure 6 is a diagram that more specifically shows the connection between the amplifier 501 and the signal processing control unit 930, and the connection of the power line, among the connections via the connection part 400 shown in Figures 2 and 3. Although Figure 6 shows a configuration in which each connection part 400 is connected via a single connection part 400, a configuration in which multiple connection parts 400 are connected in parallel may be used to reduce the resistance of the connection parts 400 or to provide redundancy.

[0055] The signal processing control unit 930 may include a calculation unit 934 that generates control signals and a drive unit 935 that drives the amplifier 501. The calculation unit 934 receives a signal from the signal processing drive control unit 931 via a control line 932 that controls the voltage amplification ratio for each block. The calculation unit 934 generates a signal to control the amplifier 501 in accordance with the control signal from the signal processing drive control unit 931. The calculation unit 934 handles the same voltage V1 signal as the signal processing drive control unit 931. Therefore, the calculation unit 934 is supplied with a power supply voltage (voltage V1) and a reference voltage GND from the pad electrode 300-4 via a power supply line 804. Specifically, the calculation unit 934 is supplied with a power supply voltage (voltage V1) from the pad electrode 300-4-1 via a power supply line 804-1, and the reference voltage GND is supplied from the pad electrode 300-4-2 via a power supply line 804-2. The control signal generated by the calculation unit 934 is input to the drive unit 935 of the signal processing control unit 930.

[0056] The drive unit 935 drives the amplifier 501, which operates at voltage V2. Therefore, the drive unit 935 is supplied with the power supply voltage (voltage V2) and the reference voltage GND from the pad electrode 300-6 via the power supply line 806. Specifically, the drive unit 935 is supplied with the power supply voltage (voltage V2) from the pad electrode 300-6-1 via the power supply line 804-1, and the reference voltage GND is supplied from the pad electrode 300-6-2 via the power supply line 804-2. The drive unit 935 has the function of boosting the control signal generated by the calculation unit 934 to a voltage corresponding to voltage V2. The control signal boosted by the drive unit 935 is input to the amplifier 501 via the wiring 933, the connection part 400-33, and the gain control line 506.

[0057] Amplifier 501 is supplied with a power supply voltage V2 and a reference voltage GND from pad electrode 300-7 via power line 807. Specifically, amplifier 501 is supplied with a power supply voltage (voltage V2) from pad electrode 300-7-1 via power line 804-1, and a reference voltage GND is supplied from pad electrode 300-7-2 via power line 804-2.

[0058] The power supply voltage supplied from pad electrodes 300-6 and 300-7 is both voltage V2, but here, separate pad electrodes and power supply wiring are provided for the drive unit 935 and the amplifier 501, thus isolating the power supply. This configuration prevents crosstalk between circuits that operate differently via the power supply. As for the power supply isolation configuration, the pad electrodes and power supply wiring may be separated as in this reference example, or the pad electrodes may be common, and the power supply wiring may be separated in such a way that the common impedance is low.

[0059] In this reference example, the pad electrodes and power supply wiring are separated, and the power supply line connected to the amplifier 501 is connected to the circuit of the first board 10 via a connection part 400 near the pad electrodes. This reduces the effect of crosstalk through coupling capacitance between power supply wirings arranged on the second board 20.

[0060] However, in the imaging device according to this reference example, the control signal boosted by the drive unit 935, i.e., the control signal output to the gain control line 506, may be affected by power supply fluctuations of the power supply line 806 connected to the drive unit 935. Factors causing power supply fluctuations of the power supply line 806 include crosstalk via parasitic capacitance between it and other wiring provided on the second substrate 20, and fluctuations due to the operation of other circuits connected to the power supply line 806. Fluctuations in the control signal on the gain control line 506 may act on the negative feedback path of the amplification circuit 502 via parasitic capacitance between the gate electrode and the source and drain electrodes of the transistor constituting the switch M1 of the amplifier 501, and may affect the operation of the amplifier 501. For example, fluctuations in the control signal on the gain control line 506 may appear as an error in the voltage amplification ratio of the pixel signal processed by the amplifier 501 and an output offset, which can result in image quality degradation. In particular, the second substrate 20 generally contains circuits that control the drive timing, which are classified as digital circuits, and circuits that process and control digital signals at predetermined frequencies. Typically, power supply fluctuations in digital circuits are significant, and it is necessary to consider configurations that reduce the impact on image quality.

[0061] Next, the configuration of the imaging device according to this embodiment will be described with reference to Figures 7 to 9. Figures 7 and 8 are schematic plan views showing the general configuration of the imaging device according to this embodiment. Figure 9 is a circuit diagram showing the connection relationship between the amplifier and the signal processing control unit in the imaging device according to this embodiment. Components similar to those in the imaging device according to the reference examples shown in Figures 2 to 6 are denoted by the same reference numerals, and their descriptions are omitted or simplified. The imaging device according to this embodiment is an example configured to reduce the influence of power fluctuations in the power line 806 via the drive unit 935 on the operation of the amplifier 501.

[0062] As shown in Figures 7 and 8, in the imaging device according to this embodiment, the power supply voltage and reference voltage GND of voltage V1 to the signal processing control unit 930 are supplied from the pad electrode 300-4 via the power line 804, similar to the imaging device according to the reference example. On the other hand, the power supply voltage and reference voltage of voltage V2 to the signal processing control unit 930 are supplied from the pad electrode 300-7 via the power line 807, connection part 400-7, power line 507, connection part 400-37, and wiring 919, unlike the imaging device according to the reference example. In other words, the power supply voltage and reference voltage GND of voltage V2 to the signal processing control unit 930 are supplied via a part of the power wiring used to supply power to the amplifier 501.

[0063] Figure 9 is a diagram that more specifically shows the connection between the amplifier 501 and the signal processing control unit 930, and the connection of the power line, among the connections via the connection part 400 shown in Figures 7 and 8. Although Figure 9 shows a configuration in which each connection part 400 is connected via a single connection part 400, a configuration in which multiple connection parts 400 are connected in parallel may be used to reduce the resistance of the connection parts 400 or to provide redundancy.

[0064] The drive unit 935 of the signal processing control unit 930 is supplied with a power supply voltage via pad electrode 300-7-1, power line 807-1, connector 400-7-1, power line 507-1, connector 400-37-1, and wiring 919-1. In addition, the drive unit 935 is supplied with a reference voltage GND via pad electrode 300-7-2, power line 807-2, connector 400-7-2, power line 507-2, connector 400-37-2, and wiring 919-2.

[0065] In Figure 9, the power line 807 extends along the second substrate 20. However, as shown in Figures 2 and 6, in a planar layout, the power line 807 is connected to the connection part 400-7 near the pad electrode 300-7 and then connected to the power line 507 provided on the first substrate 10. Furthermore, to reduce the resistance of the wiring and connection parts, the connection part 400-37 may be configured to be placed in multiple locations for the power line 507-2 located on the first substrate 10 and the wiring 919 located on the second substrate 20. The connection part 400-37 may also be configured to be placed in accordance with the arrangement of the signal processing unit 500 blocks and the signal processing control unit 930, or it may be placed in multiple locations regardless of the arrangement of the signal processing unit 500 blocks and the signal processing control unit 930. In this embodiment, the signal processing control unit 930 is configured to be placed in multiple locations corresponding to the blocks of the signal processing unit 500. The wiring 919 arranged on the second board 20 may be a common wiring connecting multiple signal processing control units 930 and connection units 400-37, or it may be multiple wirings connecting each of the multiple signal processing control units 930 to the connection unit 400-37.

[0066] As described above, in the imaging device of this embodiment, a portion of the power supply for the signal processing control unit 930 that controls and drives the amplifier 501 is supplied via the power supply wiring of the amplifier 501 located on the first board 10. This configuration suppresses fluctuations in the drive signal output from the signal processing control unit 930 caused by power supply fluctuations of the wiring and circuits located on the second board 20, thereby reducing the impact on the operation of the amplifier 501.

[0067] Alternatively, a capacitor (not shown) may be placed on at least one of the first substrate 10 and the second substrate 20 and connected to the power line 507 and wiring 919. By configuring it in this way, in a configuration where the power supply is shared between substrates as in this embodiment, the influence of power supply fluctuations due to the operation of circuits placed on each substrate can be reduced. The location of the capacitor placed on each substrate is not particularly limited, but for example, the vicinity of the pad electrode 300, the vicinity of the connection part 400, and the vicinity of the circuit to which the power supply is connected are effective locations.

[0068] In other words, the imaging device according to this embodiment includes a first substrate 10 on which a first circuit section is provided, and a second substrate 20 on which a second circuit section connected to the first circuit section and a third circuit section connected to the second circuit section are provided. The second circuit section is configured to supply a drive potential to the first circuit section, and at least a portion of the drive potential of the second circuit section is supplied to the second circuit section from the first substrate 10. In this embodiment, the first circuit section, the second circuit section, and the third circuit section correspond to the amplifier 501, the drive unit 935, and the calculation unit 934, respectively. The drive unit 935 is a level shift circuit that shifts the level of the signal input from the third circuit section to a level corresponding to the first circuit section. The drive potential is a voltage signal used to drive the circuit, such as a power supply (power supply voltage, reference voltage), a control signal, or a clock signal.

[0069] In this embodiment, a signal processing control unit 930 that controls the pixel section 100 of the signal processing unit 500 in units of pixel blocks has been described. In a configuration where the voltage amplification factor of the signal processing unit 500 is changed in units of pixel blocks, as in this embodiment, the voltage amplification factor may be switched during the vertical readout scan of the pixel 101. In this case, the responsiveness of the amplifier 501 to the control of the voltage amplification factor may affect the readout time, i.e., the frame rate. Therefore, when the signal processing unit 500 is controlled block by block, the control unit can be placed near each block to shorten the time it takes for the control to be reflected and the response time, thereby reducing the impact on the readout time. On the other hand, when a control unit is placed for each block, the power supply wiring of the control unit becomes longer in proportion to the area of ​​the signal processing unit 500, the coupling capacitance with other wiring increases, and consequently the effect of crosstalk via the coupling capacitance becomes larger.

[0070] However, in this embodiment, the power supply for the control unit is supplied via the first board 10, rather than from the second board 20, which has a relatively larger number of digital circuits than the first board 10. This reduces the impact on the circuits caused by power fluctuations and suppresses image quality degradation.

[0071] In this embodiment, a configuration in which pixels and signal processing circuits are controlled block by block has been described, but it is not necessary for pixels and signal processing circuits to be controlled block by block. Also, the signal processing control unit 917 located on the second substrate 20 may be configured in the same way as the signal processing control unit 930, with the power supply voltage and reference voltage supplied from the pad electrode 300-6 via the power supply line 806 being supplied from the pad electrode 300-7 via the first substrate 10. In this case as well, the same effects as in the case of the signal processing control unit 930 can be obtained. Furthermore, in this embodiment, the power supply for the control unit that controls the voltage amplification factor of the amplifier has been described, but other control units can also be configured in the same way.

[0072] Thus, according to this embodiment, in a semiconductor device formed by stacking multiple substrates, it is possible to suppress the intrusion of noise and a decrease in operating accuracy caused by crosstalk between substrates.

[0073] [Second Embodiment] An imaging device according to a second embodiment of the present invention will be described with reference to Figures 10 to 12. Components similar to those in the imaging device according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified. Figures 10 and 11 are schematic plan views showing the general configuration of the imaging device according to this embodiment. Figure 12 is a circuit diagram showing the connection relationship between pixels and the drive timing control unit in the imaging device according to this embodiment.

[0074] The imaging device according to this embodiment further includes a reference voltage generation unit 610 located on the first substrate 10, in addition to the components described in the first embodiment. Except for the part related to the reference voltage generation unit 610, the imaging device according to this embodiment has the same configuration as the imaging device according to the first embodiment, so here we will mainly describe the differences from the imaging device of the first embodiment.

[0075] As shown in Figure 10, the reference voltage generation unit 610 is located on the first substrate 10. Similar to the reference voltage generation unit 600, the reference voltage generation unit 610 has the function of generating a reference voltage related to the driving of the pixel unit 100.

[0076] As shown in Figures 10 and 11, the reference voltage generation unit 610 is supplied with power supply voltage and reference voltage GND from the pad electrode 300-13 via power line 813, connection part 400-13, and power line 611. The reference voltage generation unit 610 is also supplied with control signals from the drive timing control unit 900 via wiring 912, connection part 400-41, and control line 612 to control the settings of the voltage generated by the reference voltage generation unit 610. The voltage generated by the reference voltage generation unit 610 is supplied to the drive timing control unit 900 via output line 613, connection part 400-42, and wiring 814, and is also output to the outside of the imaging device via wiring 814 and pad electrode 300-14. Pad electrode 300-14 serves as a test terminal for testing that the reference voltage generation unit 610 is generating the desired voltage, and also as a pad electrode for reference voltage input in modes where an external reference voltage is input. Furthermore, by connecting a capacitor to the outside of the imaging device, power fluctuations associated with the operation of the imaging device can be suppressed.

[0077] Figure 12 is a diagram that more specifically shows the connections between the pixel 101 and the reference voltage generation unit 610 and the drive timing control unit 900, as well as the power line connections, among the connections via the connection part 400 in Figures 10 and 11. In this embodiment, the accumulation time of each pixel 101 is controlled by a control signal input from the drive timing control unit 900 to the pixel unit 100 via the control line 902, connection part 400-21, and pixel control line 122. In this embodiment, one of the power supply voltage and the reference voltage GND supplied from the pad electrode 300-1 to the pixel unit 100 is supplied to the drive timing control unit 900 via a part of the connection part 400-21. In Figures 10 to 12, this part of the connection part 400-21 is shown as connection part 400-22. Also, for the sake of simplification of the drawings, the power line 611 that supplies power to the reference voltage generation unit 610 is omitted in Figure 12.

[0078] The accumulation operation of pixel 101 is performed by driving the transfer transistor 103 and the reset transistor 104. For example, first, the photoelectric conversion element 102 is reset by simultaneously turning on the transfer transistor 103 and the reset transistor 104. After the reset of the photoelectric conversion element 102, the timing at which the transfer transistor 103 is turned off marks the start time of the accumulation period. After a predetermined accumulation period has elapsed, the charge accumulated in the photoelectric conversion element 102 during the accumulation period is transferred to the floating diffusion unit FD by turning on the transfer transistor 103. The timing at which the transfer transistor 103 is turned on to transfer the charge marks the end time of the accumulation period. The transfer transistor 103 is controlled by a control signal PTX supplied from the drive timing control unit 900 via the control line 902, the connection unit 400-21, and the pixel control line 122. Note that the control of the transfer transistor 103 may be controlled by a reference voltage other than the power supply voltage or the reference voltage GND in order to control the potential during the charge accumulation operation and charge transfer of the photoelectric conversion element 102.

[0079] The drive timing control unit 900 may be configured to include a calculation unit 936 and a drive unit 937. The drive timing control unit 900 has the function of controlling the storage time of the pixel 101 by driving the transfer transistor 103 with a control signal PTX supplied via the control line 902, connection unit 400-21, and pixel control line 122. The calculation unit 936 operates with a power supply voltage of voltage V1. The drive unit 937 is supplied with one of the following as its operating voltage to drive the transfer transistor 103: the power supply voltage (voltage V1), the reference voltage GND, or a reference voltage different from the reference voltage GND (low voltage, high voltage). In this embodiment, the high voltage of the drive unit 937 is assumed to be the voltage generated by the reference voltage generation unit 610. The voltage generated by the reference voltage generation unit 610 is supplied to the drive unit 937 via the output line 613, connection unit 400-42, and wiring 814. The low voltage of the drive unit 937 is assumed to be the reference voltage GND. Similar to the first embodiment, the drive unit 937 is supplied with a reference voltage GND from the pad electrode 300-1-2 via the power line 801-2, connection part 400-1-2, connection part 400-22-2, and wiring 913. In addition to the above configuration, the drive unit 937 may be configured to use the low voltage as the reference voltage, or the drive unit 937 may be configured to use the high voltage as the power supply voltage. Alternatively, two reference voltage generation units corresponding to the low voltage and high voltage, respectively, may be arranged on the first substrate 10.

[0080] The operational accuracy of charge transfer by the transfer transistor 103 is one of the important performance characteristics of the imaging device. Therefore, the voltage generated by the reference voltage generation unit 610 is required to have high voltage value accuracy and low noise. Each circuit arranged on the same substrate may be affected by parasitic capacitance formed between the substrate and semiconductor regions where elements are arranged, parasitic capacitance between wiring, and adjacent circuits that generate heat during operation. In this embodiment, the second substrate 20 is arranged with circuits classified as digital circuits, such as circuits that control the drive timing and circuits that control digital signals at a predetermined frequency. Power supply fluctuations in digital circuits are large, and when the drive frequency is high, the amount of heat generated also increases, and the impact on adjacent circuits becomes greater.

[0081] From this perspective, in this embodiment, the configuration is such that fluctuations in the reference voltage GND of the drive unit 937 do not affect the operation of the pixel 101 via the gate electrode of the transfer transistor 103. Specifically, the reference voltage generation unit 610 is placed on the first substrate 10, and the reference voltage generated by the reference voltage generation unit 610 is supplied to the drive timing control unit 900 on the second substrate 20. As a result, the pixel 101 can be driven with a reference voltage that has higher voltage accuracy and lower noise than when the reference voltage generation unit 610 is placed on the second substrate 20, and the degradation of the performance related to charge transfer of the pixel 101 can be suppressed.

[0082] In other words, the imaging device according to this embodiment includes a first substrate 10 on which a first circuit section is provided, and a second substrate 20 on which a second circuit section connected to the first circuit section and a third circuit section connected to the second circuit section are provided. The second circuit section is configured to supply a drive potential to the first circuit section, and at least a portion of the drive potential of the second circuit section is configured to be supplied to the second circuit section from the first substrate 10. In this embodiment, the first circuit section, the second circuit section, and the third circuit section correspond to the pixel 101, the drive section 937, and the calculation section 936, respectively. The drive section 937 is a level shift circuit that shifts the level of the signal input from the third circuit section to a level corresponding to the first circuit section.

[0083] Furthermore, as described in the first embodiment, even when the pixel control unit 904 controls the storage time of each block of pixels 101, the connection relationship with the reference voltage generation unit 610 can be configured similarly. In addition, although the storage operation of pixels 101 has been described in this embodiment, a similar configuration can be applied to the drive control of the reset transistor 104 and the selection transistor 106.

[0084] Thus, according to this embodiment, in a semiconductor device formed by stacking multiple substrates, it is possible to suppress the intrusion of noise and a decrease in operating accuracy caused by crosstalk between substrates.

[0085] [Third Embodiment] An imaging device according to a third embodiment of the present invention will be described with reference to Figures 13 to 15. Components similar to those in the imaging device according to the first or second embodiment will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figures 13 and 14 are schematic plan views showing the general configuration of the imaging device according to this embodiment. Figure 15 is a circuit diagram showing the connection relationship between the clock generation unit and the digital signal processing unit in the imaging device according to this embodiment.

[0086] The imaging device according to this embodiment further includes a clock generation unit 710 located on the first substrate 10, in addition to the components described in the second embodiment. Except for the part related to the clock generation unit 710, the other components of the imaging device according to this embodiment are the same as those of the imaging device according to the second embodiment; therefore, this description will focus on the differences from the imaging device of the second embodiment.

[0087] As shown in Figure 13, the clock generation unit 710 is located on the first substrate 10. The clock generation unit 710 generates a clock signal to drive the digital signal processing unit 940 located on the second substrate 20. In this embodiment, an example of supplying a clock signal from the clock generation unit 710 to the digital signal processing unit 940 is described, but the same clock signal may be supplied to the drive timing control unit 900 and the signal processing drive control unit 931. Alternatively, a clock generation unit corresponding to the drive timing control unit 900 and the signal processing drive control unit 931 may be provided separately from the clock generation unit 710.

[0088] In the first embodiment, a configuration was described in which a clock signal for driving the digital signal processing unit 940 is input from outside the imaging device via a pad electrode 300-11. On the other hand, in this embodiment, since the clock signal for driving the digital signal processing unit 940 is generated in the clock generation unit 710, the pad electrode 300-11 described in the first and second embodiments is unnecessary. In this embodiment, this pad electrode is used as a pad electrode 300-15 for supplying the power supply voltage and reference voltage for driving the clock generation unit 710.

[0089] As shown in Figures 13 and 14, the clock generation unit 710 is supplied with power supply voltage and reference voltage from pad electrodes 300-15 via power line 815, connection part 400-15, and power line 711. The clock generation unit 710 also receives control signals from the digital signal processing unit 940 via wiring 952, connection part 400-61, and control line 712 to control the frequency setting of the clock signal generated by the clock generation unit 710. The clock signal generated by the clock generation unit 710 is supplied to the digital signal processing unit 940 via output line 713, connection part 400-62, and wiring 953. In this embodiment, the digital signal processing unit 940 is supplied with power supply voltage from pad electrode 300-8 via power line 808, and with reference voltage GND supplied from pad electrode 300-16 via power line 816.

[0090] Figure 15 is a diagram that more specifically shows the connection between the clock generation unit 710 and the digital signal processing unit 940, and the power line connection, among the connections via the connection part 400 shown in Figures 13 and 14.

[0091] The digital signal processing unit 940 may include a calculation unit 938 and a drive unit 939. The calculation unit 938 is supplied with a power supply voltage from pad electrode 300-8-1 via power line 808-1, and a reference voltage GND is supplied from pad electrode 300-8-2 via power line 808-2. The drive unit 939 is supplied with a power supply voltage from pad electrode 300-16-1 via power line 816-1, and a reference voltage GND is supplied from pad electrode 300-16-2 via power line 816-2.

[0092] The clock generation unit 710 is supplied with a power supply voltage from pad electrode 300-15-1 via power line 815-1, connection part 400-15-1, and power line 711-1. The clock generation unit 710 is also supplied with a reference voltage GND from pad electrode 300-15-2 via power line 815-2, connection part 400-15-2, and power line 711-2. Furthermore, the clock generation unit 710 receives control signals from the drive unit 939 of the digital signal processing unit 940 via wiring 952, connection part 400-61, and control line 712 to control the frequency and other parameters of the clock signal generated by the clock generation unit 710. The clock signal generated by the clock generation unit 710 is supplied to the calculation unit 938 of the digital signal processing unit 940 via output line 713, connection part 400-62, and wiring 953. The arithmetic unit 938 performs various digital signal processing on the pixel signals input from the signal processing unit 500 based on the clock signal supplied from the clock generation unit 710.

[0093] In this embodiment, the power supply voltage and reference voltage GND of the calculation unit 938 are separated from the power supply voltage and reference voltage GND of the drive unit 939. However, this configuration can be appropriately changed depending on the operating voltage of the clock generation unit 710. For example, if the operating voltage of the clock generation unit 710 and the amplitude of the clock signal it generates are the same as the operating voltage of the calculation unit 938 to which the clock signal is supplied, then the power supply voltage and reference voltage GND of the calculation unit 938 and the power supply voltage and reference voltage GND of the drive unit 939 may be the same.

[0094] The clock signal generated by the clock generation unit 710 serves as the reference clock for the operation of the digital signal processing unit 940. Frequency errors and noise such as jitter in the reference clock can cause malfunctions in the digital signal processing operation. Therefore, it is desirable that the clock signal generated by the clock generation unit 710 has high frequency accuracy and low jitter. In this embodiment, the clock generation unit 710 is located on the first board 10, and the generated clock signal is supplied to the digital signal processing unit 940 on the second board 20. Similar to the reference voltage generation unit 610 described in the second embodiment, the configuration in which the clock generation unit 710 is located on the first board 10 is less susceptible to influence from other circuits, such as digital circuits, compared to the configuration in which the clock generation unit 710 is located on the second board 20. Therefore, according to the configuration of this embodiment in which the clock generation unit 710 is located on the first board 10, it is possible to generate a clock signal with higher frequency accuracy and lower jitter, and malfunctions in the digital signal processing of the digital signal processing unit 940 can be reduced.

[0095] In other words, the imaging device according to this embodiment includes a first substrate 10 on which a first circuit section is provided, and a second substrate 20 on which a second circuit section connected to the first circuit section and a third circuit section connected to the second circuit section are provided. The second circuit section is configured to supply a drive potential to the first circuit section, and at least a portion of the drive potential of the second circuit section is configured to be supplied to the second circuit section from the first substrate 10. In this embodiment, the first circuit section, the second circuit section, and the third circuit section correspond to the clock generation section 710, the drive section 939, and the calculation section 938, respectively.

[0096] In this embodiment, the power supplied to the clock generation unit 710 is supplied from the pad electrodes 300-15. This configuration reduces the impact of power supply fluctuations caused by the operation of other circuits. However, since the clock signal generated by the clock generation unit 710 becomes the reference clock for the digital signal processing unit 940, at least a portion of the power supplied to the clock generation unit 710 may be shared with the digital signal processing unit 940. When the power supply is shared between boards, as described in the first embodiment, it is also possible to reduce the impact of power supply fluctuations by placing a capacitor on at least one of the first board 10 and the second board 20 and connecting it to the power lines 711 and 815.

[0097] Furthermore, by configuring the clock generation unit that supplies clock signals to the drive timing control unit 900 and the signal processing drive control unit 931 in the same way as the clock generation unit 710, the same effects as described in this embodiment can be obtained. The drive timing control unit 900 generates control signals related to the control of the accumulation time of the pixels 101. For example, if the jitter of the clock signal input to the drive timing control unit 900 is large, it can cause errors in the control of the accumulation time, leading to image quality degradation such as sensitivity variations between pixels and linearity errors with respect to the light intensity of the subject. By configuring the clock generation unit that supplies clock signals to the drive timing control unit 900 in the same way as the clock generation unit 710 described in this embodiment, the accuracy of the control signals can be maintained, and image quality degradation can be reduced.

[0098] Thus, according to this embodiment, in a semiconductor device formed by stacking multiple substrates, it is possible to suppress the intrusion of noise and a decrease in operating accuracy caused by crosstalk between substrates.

[0099] [Fourth Embodiment] An imaging device according to a fourth embodiment of the present invention will be described with reference to Figures 16 to 18. Components similar to those in the imaging devices of the first to third embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figures 16 and 17 are schematic plan views showing the general configuration of the imaging device according to this embodiment. Figure 18 is a circuit diagram showing the connection relationship between the output unit and the digital signal processing unit in the imaging device according to this embodiment.

[0100] In the imaging device according to this embodiment, some of the circuits of the output unit 700 described in the first to third embodiments are arranged on the second substrate 20. That is, the imaging device according to this embodiment includes an output unit 700 provided on the first substrate 10 and an output unit 705 provided on the second substrate 20. Except for the parts related to the output units 700 and 705, the other configurations of the imaging device according to this embodiment are the same as those of the imaging device according to the third embodiment, so here we will mainly explain the differences from the imaging device of the third embodiment.

[0101] The functions of the output unit 700 described in the first to third embodiments include, for example, a P / S conversion function and a function to output a signal to the outside of the imaging device. In this embodiment, the output unit 700 located on the first substrate 10 is a circuit having a P / S conversion function, and the output unit 705 located on the second substrate 20 is a circuit having a function to output a pixel signal to the outside of the imaging device.

[0102] The pixel signals converted by A / D in the signal processing unit 500 are stored in a digital memory composed of multiple bits. The digital data stored in the digital memory of the signal processing unit 500 is input as parallel data to the digital signal processing unit 940 via the output line 517, connection section 400-35, and wiring 942. The digital signal processing unit 940 performs various digital signal processing on the input parallel data. The parallel data processed by the digital signal processing unit 940 is input to the output unit 700 via wiring 943, connection section 400-36, and signal input line 701. Although each wiring and connection section is shown as a single element in the diagram, they are actually composed of multiple wirings and connection sections in order to transmit multiple data in parallel. In addition, a portion of the signal input line 701 includes signals that control the operating mode of the P / S conversion of the output unit 700, such as the number of bits of data to be converted.

[0103] The output unit 700 converts the parallel input digital data into serial data. The pixel signals converted into serial data by the output unit 700 are input to the digital signal processing unit 940 via wiring 704, connection units 400-70, and wiring 960. The digital signal processing unit 940 performs digital signal processing such as holding the input serial data, converting the number of bits, and adding data. The serial data processed by the digital signal processing unit 940 is input to the output unit 705 via wiring 961 and output to the outside of the imaging device via wiring 810 and pad electrodes 300-10.

[0104] Figure 18 is a diagram that more specifically shows the connections between the output unit 700, the digital signal processing unit 940, and the output unit 705, as well as the power line connections, among the connections via the connection unit 400 shown in Figures 16 and 17.

[0105] The calculation unit 938 of the digital signal processing unit 940 is supplied with power voltage from pad electrode 300-8-1 via power line 808-1, and the reference voltage GND is supplied from pad electrode 300-8-2 via power line 808-2. The drive unit 939 of the digital signal processing unit 940 is supplied with power voltage from pad electrode 300-16-1 via power line 816-1, and the reference voltage GND is supplied from pad electrode 300-16-2 via power line 816-2. The output unit 700 is supplied with power voltage from pad electrode 300-9-1 via power line 809-1, connection part 400-9-1, and power line 702-1. In addition, the output unit 700 is supplied with reference voltage GND from pad electrode 300-9-2 via power line 809-2, connection part 400-9-2, and power line 702-2. The output section 705 is supplied with a power supply voltage from pad electrode 300-17-1 via power line 817-1, and a reference voltage GND is supplied from pad electrode 300-17-2 via power line 817-2.

[0106] The pixel signals digitally processed by the arithmetic unit 938 are input as parallel data from the drive unit 939 to the output unit 700 via wiring 943, connection unit 400-36, and signal input line 701. As previously described, the signal input line 701 includes control signal lines as part of it. The output unit 700 generates serial data based on the input parallel data and outputs it to the arithmetic unit 938 via wiring 704, connection unit 400-70, and wiring 960. The digital signal processing unit 940 outputs the digitally processed serial data to the output unit 705 via wiring 961. The output unit 705 generates, for example, a differential signal based on the input serial data and outputs the LVDS output signal to the outside of the imaging device via wiring 810 and pad electrodes 300-10.

[0107] One example of P / S conversion operation in the output unit 700 is the operation of converting parallel data to serial data at a frequency that is a multiple of the number of bits of the pixel data, corresponding to the period during which parallel data is input from the digital signal processing unit 940. For example, if 14 bits of parallel data are input from the digital signal processing unit 940 with a period of 1 / 50 MHz, the output unit 700 performs P / S conversion at a frequency of 50 MHz × 14 bits, i.e., 700 MHz. In P / S conversion operation, even a conversion error of 1 bit can have a significant impact on the pixel data. For example, the conversion error may be observed as random noise, or the light intensity of the subject may not be accurately represented due to the conversion error. P / S conversion operation, which operates at high frequencies, is susceptible to power supply fluctuations and crosstalk from the operation of surrounding circuits. Therefore, in this embodiment, the output unit 700 equipped with the P / S conversion function is arranged on the first board 10. In addition, P / S conversion operation requires a high-frequency clock signal with high frequency accuracy and low jitter. Therefore, as described in the third embodiment, a clock generation unit (not shown) that generates a clock signal to be supplied to the output unit 700 may be arranged near the output unit 700 of the first substrate 10.

[0108] On the other hand, since the output unit 705 generates a differential signal based on series data input at high speed from the output unit 700, the power supply fluctuations associated with its operation are large and may affect other circuits located nearby. Furthermore, if the signal output to the outside of the imaging device is an LVDS output signal, the design of the signal transmission path becomes important. For this reason, it is desirable to place the output unit 705, which has an output function, near the pad electrodes 300 of the second substrate 20.

[0109] As described above, in this embodiment, an output unit 700, which converts parallel data digitally processed by the digital signal processing unit 940 into serial data, is located on the first board 10. This enables high-speed and highly accurate P / S conversion operation. In addition, in this embodiment, an output unit 705, which generates a differential signal from the serial data and outputs the signal to the outside of the imaging device via the pad electrodes 300, is located on the second board 20. This reduces the impact on the circuits located on the first board 10. Furthermore, by locating the output unit 705 near the pad electrodes, the design of the signal transmission path can be simplified.

[0110] In other words, the imaging device according to this embodiment includes a first substrate 10 on which a first circuit section is provided, and a second substrate 20 on which a second circuit section connected to the first circuit section and a third circuit section connected to the second circuit section are provided. The second circuit section is configured to supply a drive potential to the first circuit section, and at least a portion of the drive potential of the second circuit section is supplied to the second circuit section from the first substrate 10. In this embodiment, the first circuit section, the second circuit section, and the third circuit section correspond to the output section 700, the drive section 939, and the calculation section 938, respectively.

[0111] Thus, according to this embodiment, in a semiconductor device formed by stacking multiple substrates, it is possible to suppress the intrusion of noise and a decrease in operating accuracy caused by crosstalk between substrates.

[0112] [Fifth Embodiment] A fifth embodiment of the present invention, specifically an imaging system, will be described with reference to Figure 19. Figure 19 is a block diagram showing the schematic configuration of the imaging system according to this embodiment.

[0113] The imaging devices described in the first to fourth embodiments above are applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include an optical system such as a lens and an imaging device, are also included in imaging systems. Figure 19 shows a block diagram of a digital still camera as an example of these.

[0114] The imaging system 1200 illustrated in Figure 19 includes an imaging device 1201, a lens 1202 for forming an optical image of a subject onto the imaging device 1201, an aperture 1204 for varying the amount of light passing through the lens 1202, and a barrier 1206 for protecting the lens 1202. The lens 1202 and aperture 1204 form an optical system that focuses light onto the imaging device 1201. The imaging device 1201 converts the optical image formed by the imaging device and lens 1202 described in any of the first to fourth embodiments into image data.

[0115] The imaging system 1200 also includes a signal processing unit 1208 that processes the output signal from the imaging device 1201. The signal processing unit 1208 generates image data from the digital signal output by the imaging device 1201. The signal processing unit 1208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 1201 may include an A / D conversion unit that generates the digital signal processed by the signal processing unit 1208. The A / D conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 1201 is formed, or on a semiconductor substrate separate from the semiconductor layer on which the photoelectric conversion unit of the imaging device 1201 is formed. The signal processing unit 1208 may also be formed on the same semiconductor substrate as the imaging device 1201.

[0116] The imaging system 1200 further includes a memory unit 1210 for temporarily storing image data, and an external interface unit (external I / F unit) 1212 for communicating with an external computer or the like. Furthermore, the imaging system 1200 includes a recording medium 1214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1216 for recording or reading data from the recording medium 1214. The recording medium 1214 may be built into the imaging system 1200 or it may be detachable.

[0117] Furthermore, the imaging system 1200 includes an overall control and calculation unit 1218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1220 that outputs various timing signals to the imaging device 1201 and the signal processing unit 1208. Here, the timing signals and the like may be input from an external source, and the imaging system 1200 only needs to have at least an imaging device 1201 and a signal processing unit 1208 that processes the output signals output from the imaging device 1201.

[0118] The imaging device 1201 outputs an imaging signal to the signal processing unit 1208. The signal processing unit 1208 performs predetermined signal processing on the imaging signal output from the imaging device 1201 and outputs image data. The signal processing unit 1208 generates an image using the imaging signal.

[0119] Thus, according to this embodiment, an imaging system can be realized that applies the imaging device according to the first to fourth embodiments.

[0120] [Sixth Embodiment] A sixth embodiment of the present invention, consisting of an imaging system and a mobile body, will be described with reference to Figure 20. Figure 20 is a diagram showing the configuration of the imaging system and mobile body according to this embodiment.

[0121] Figure 20(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 1300 includes an imaging device 1310. The imaging device 1310 is the imaging device described in any of the first to fourth embodiments above. The imaging system 1300 includes an image processing unit 1312 that performs image processing on a plurality of image data acquired by the imaging device 1310, and a parallax acquisition unit 1314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging device 1310. The imaging system 1300 also includes a distance acquisition unit 1316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 1314 and the distance acquisition unit 1316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 1318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0122] The imaging system 1300 is connected to a vehicle information acquisition device 1320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 1300 is also connected to a control ECU 1330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 1318. The imaging system 1300 is also connected to a warning device 1340 that issues a warning to the driver based on the judgment result of the collision judgment unit 1318. For example, if the collision judgment result of the collision judgment unit 1318 indicates a high probability of collision, the control ECU 1330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0123] In this embodiment, the imaging system 1300 captures images of the area around the vehicle, for example, the front or rear. Figure 20(b) shows the imaging system when capturing images of the area in front of the vehicle (imaging range 1350). The vehicle information acquisition device 1320 sends instructions to the imaging system 1300 or the imaging device 1310. This configuration can further improve the accuracy of distance measurement.

[0124] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically prevent vehicles from straying from their lanes. Furthermore, the imaging system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0125] [Seventh Embodiment] A device according to the seventh embodiment of the present invention will be described with reference to Figure 21. Figure 21 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0126] Figure 21 is a schematic diagram showing an EQP device including a photoelectric converter APR. The photoelectric converter APR has the functions of an imaging device according to any of the first to fourth embodiments. All or part of the photoelectric converter APR is a semiconductor device IC. In this example, the photoelectric converter APR can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0127] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. Each peripheral circuit on the second semiconductor chip can be a column circuit corresponding to a pixel row on the first semiconductor chip. Alternatively, each peripheral circuit on the second semiconductor chip can be a matrix circuit corresponding to a pixel or pixel block on the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0128] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0129] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0130] The EQP (Equipment Equipped Device) shown in Figure 21 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Also, the EQP can be medical devices such as endoscopes and CT scanners.

[0131] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0132] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0133] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways. For example, examples in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, are also included as embodiments of the present invention.

[0134] Furthermore, although additional configurations for the imaging device of the first embodiment were described in the second to fourth embodiments above, the additional configurations described in each of the second to fourth embodiments may also be applied to the imaging device according to the reference example described with reference to Figures 2 to 6.

[0135] Furthermore, the circuit configuration of the pixel 101 shown in Figure 4 is just an example and can be modified as appropriate. For example, each pixel 101 may have two or more photoelectric conversion elements 102. Alternatively, multiple photoelectric conversion elements 102 of a single pixel 101 may constitute a pupil-splitting pixel sharing a single microlens. Also, the pixel 101 does not necessarily need to have a selection transistor 106. In addition, the capacitance value of the floating diffusion section FD may be configured to be switchable.

[0136] Furthermore, the circuit configuration of amplifier 501 shown in Figure 5 is just one example and can be modified as appropriate. For example, in the configuration example in Figure 5, two feedback capacitors C1 and C2 can be connected in parallel to the amplification circuit 502, but the number of feedback capacitors is not limited to this. Also, in the configuration example in Figure 5, an input capacitor C0 is provided, but the capacitance value of the input capacitor may be configured to be switchable. The circuit configuration of amplifier 501 can be modified as appropriate depending on the required voltage amplification factor, etc.

[0137] Furthermore, the imaging systems shown in the fifth and sixth embodiments above are examples of imaging systems to which the semiconductor device of the present invention can be applied, and the imaging systems to which the semiconductor device of the present invention can be applied are not limited to the configurations shown in Figures 19 and 20.

[0138] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0139] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features. [Explanation of symbols]

[0140] 10…First circuit board 20…Second board 100... Pixel area 101... pixels 120...Pixel control unit 300... Pad electrodes 400...Connection part 501... Amplifier 700...Output section 710...Clock generation unit 900... Drive Timing Control Unit 930... Signal Processing Control Unit 934,936,938...Arithmetic section 935, 937, 939… Drive unit 940... Digital signal processing unit

Claims

1. A first circuit board on which the first circuit section is provided, The device comprises a second circuit section connected to the first circuit section, a third circuit section connected to the second circuit section, and a second substrate on which pad electrodes supplied with the power supply voltage of the second circuit section are provided. The second circuit is a circuit that supplies control signals to the first circuit, The power supply voltage of the second circuit section is propagated from the pad electrodes through the first connection between the first and second substrates, from the side of the second substrate to the side of the first substrate, and then supplied from the side of the first substrate to the second circuit section through the second connection between the first and second substrates. A semiconductor device characterized by the following features.

2. The first circuit section and the second circuit section are connected in parallel via a plurality of connection points between the first substrate and the second substrate. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

3. The second circuit is a level shift circuit that shifts the level of the signal input from the third circuit to a level corresponding to the first circuit. The semiconductor device according to claim 1 or 2, characterized in that it is as described above.

4. The first circuit section is an amplifier, The third circuit generates a control signal for controlling the gain of the amplifier. The semiconductor device according to claim 3, characterized in that it is as described above.

5. The first circuit section has a pixel that includes a photoelectric conversion element, The third circuit unit generates control signals for controlling the pixels. The semiconductor device according to claim 3, characterized in that it is as described above.

6. The first substrate further comprises a voltage generation unit, The voltage generation unit generates a reference voltage supplied to the second circuit unit. The semiconductor device according to any one of claims 1 to 5.

7. The first circuit section is a clock generation section that generates a clock signal, The second circuit section is a drive unit that controls the frequency of the clock signal, The third circuit section is a signal processing unit that performs signal processing based on the clock signal. The semiconductor device according to claim 1 or 2, characterized in that it is as described above.

8. The first circuit unit is a parallel-to-serial conversion unit that converts parallel data supplied from the second circuit unit into serial data. The third circuit unit is an output unit for outputting the series data received from the first circuit unit via the second circuit unit to the outside. The semiconductor device according to claim 1 or 2, characterized in that it is as described above.

9. The system further comprises a first power supply wiring that supplies a power supply voltage to the first circuit section, and a second power supply wiring that supplies the power supply voltage to the second circuit section. The first power supply wiring and the second power supply wiring are partially common. The semiconductor device according to any one of claims 1 to 8.

10. The pad electrode to which the power supply voltage of the first circuit is supplied and the pad electrode to which the power supply voltage of the second circuit is supplied are common. The functional device according to claim 9.

11. The system further comprises a second power supply wiring that supplies the power supply voltage to the second circuit section, and a third power supply wiring that supplies the power supply voltage to the third circuit section. The second power supply wiring and the third power supply wiring are provided separately. The semiconductor device according to any one of claims 1 to 8.

12. The pad electrode to which the power supply voltage of the second circuit is supplied and the pad electrode to which the power supply voltage of the third circuit is supplied are provided separately. The semiconductor device according to claim 11, characterized in that it is a semiconductor device.

13. The second power supply wiring comprises a first wiring to which the power supply voltage is supplied and a second wiring to which a reference voltage is supplied. A capacitor is provided on the first substrate and connected between the first wiring and the second wiring. The semiconductor device according to any one of claims 9 to 12.

14. A first substrate on which pixels that output pixel signals based on charge generated by a photoelectric conversion element and amplifiers that amplify the pixel signals are arranged, The device includes a second substrate on which a first calculation unit for generating a control signal for controlling the gain of the amplifier and a first drive unit for driving the amplifier by shifting the level of the control signal to a level corresponding to the drive voltage of the amplifier are arranged. The control signal is input from the first drive unit to the amplifier via the first connection between the first board and the second board. The power supply voltage for driving the first drive unit is supplied to the pad electrodes provided on the second substrate, propagated from the second substrate side to the first substrate side via the second connection between the first substrate and the second substrate, and then supplied from the first substrate side to the first drive unit via the third connection between the first substrate and the second substrate. A semiconductor device characterized by the following features.

15. The system further comprises a second calculation unit that generates a control signal for controlling the aforementioned pixel, and a second drive unit that shifts the level of the control signal to a level corresponding to the drive voltage of the aforementioned pixel and drives the aforementioned pixel. The second calculation unit and the second drive unit are arranged on the second substrate. The control signal is input from the second drive unit to the pixel via the fourth connection between the first substrate and the second substrate. The power supply voltage for driving the second drive unit is propagated from the second board side to the first board side via the fifth connection between the first and second boards, and then supplied from the first board side to the second drive unit via the sixth connection between the first and second boards. The semiconductor device according to claim 14, characterized by the features described above.

16. It further comprises a clock generation unit that generates a clock signal, a third drive unit that controls the frequency of the clock signal, and a third arithmetic unit that performs signal processing on the pixel signal based on the clock signal. The clock generation unit is located on the first substrate, The third drive unit and the third calculation unit are arranged on the second substrate, The third drive unit drives the clock generation unit via the seventh connection between the first substrate and the second substrate. The clock signal is supplied to the third arithmetic unit via the eighth connection between the first and second substrates. The semiconductor device according to claim 14 or 15, characterized by the above.

17. The system further comprises: a signal processing unit that converts the pixel signal from analog to digital and holds it as multiple bits of parallel data; a digital signal processing unit that performs digital signal processing on the parallel data; a parallel-to-serial conversion unit that converts the parallel data processed by the digital signal processing unit into serial data; a fourth drive unit for controlling the parallel-to-serial conversion unit; and an output unit that outputs the serial data to the outside. The signal processing unit and the parallel-to-serial conversion unit are arranged on the first board. The digital signal processing unit, the fourth drive unit, and the output unit are arranged on the second board. The parallel data is input from the signal processing unit to the digital signal processing unit via the ninth connection between the first board and the second board. The parallel data processed by the digital signal processing unit is input from the digital signal processing unit to the parallel-to-serial conversion unit via the tenth connection unit between the first board and the second board. The serial data is input from the parallel-to-serial conversion unit to the output unit via the 11th connection between the first board and the second board. The semiconductor device according to any one of claims 14 to 16.

18. A semiconductor device according to any one of claims 14 to 17, A signal processing device that processes the signal output from the semiconductor device and An imaging system characterized by having the following features.

19. It is a mobile object, A semiconductor device according to any one of claims 14 to 17, Distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the semiconductor device, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

20. A semiconductor device according to any one of claims 1 to 17, Optical device corresponding to the aforementioned semiconductor device, Control device for controlling the aforementioned semiconductor device, A processing unit that processes the signal output from the aforementioned semiconductor device, A mechanical device controlled based on information obtained from the aforementioned semiconductor device, A display device for displaying information obtained by the aforementioned semiconductor device, and At least one of the following: a memory device for storing information obtained by the semiconductor device, and A device characterized by being equipped with the following features.

Images