memory circuit

Abstract

A memory circuit that has: a plurality of memory groups that execute a write operation or a read operation in response to a request signal; a plurality of memory group control units that are provided corresponding to each of the plurality of memory groups; and a first memory control unit that outputs a request signal to an adjacent memory group control unit. Each memory group control unit outputs to a memory group corresponding to the request signal or to a later-stage memory group control unit, according to an address signal included in the received request signal. As a result, each of the memory group control units can control access for each memory group and increase in power consumption can be suppressed while still suppressing increase in access time.

Description

Technical Field

[0004] ,

[0006] , , , , , ,

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[0001] The present invention relates to a memory circuit.

Background Art

[0002] In an image processing apparatus having SRAM (Static Random Access Memory), there is known a method of dividing the SRAM into a plurality of groups that can be switched between a low power mode and a normal mode, and storing encoded image data in one of the groups. The image processing apparatus reduces power consumption by switching only the group storing the encoded image data from the low power mode to the normal mode (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, semiconductor devices such as a system LSI (Large-Scale Integration) that processes video data may have a memory circuit such as a frame memory that stores video data in units of frames. As the size of one frame of video data increases, the memory capacity to be used increases, and the scale of the memory circuit mounted on the system LSI increases. As a result, the power consumption of the memory circuit increases, and the access time of the memory circuit increases due to the lengthening of bus wiring and the like within the memory circuit.

[0005] The present invention has been made in view of the above points, and an object thereof is to suppress an increase in power consumption while suppressing an increase in access time.

Means for Solving the Problems

[0006] In one aspect of the present invention, the memory circuit includes a plurality of memory groups, each containing a plurality of memory cells, which perform write or read operations in response to a request signal; a plurality of memory group control units provided corresponding to each of the plurality of memory groups; and a first memory control unit that outputs a request signal received from the outside to an adjacent memory group control unit. Each of the plurality of memory group control units outputs the request signal to the corresponding memory group if the address signal included in the received request signal indicates the corresponding memory group, and outputs the request signal to a subsequent memory group control unit if the address signal indicates a memory group other than the corresponding memory group. The memory group has at least one sub-memory group that can be set to either a low-power mode that suppresses power consumption while retaining data, or an active mode that allows write or read operations to be performed. The memory group control unit corresponding to the memory group sets the sub-memory group on which write or read operations are to be performed to the active mode, and sets the sub-memory group on which write or read operations are not performed for a predetermined period to the low-power mode. . [Effects of the Invention]

[0007] According to the disclosed technology, it is possible to suppress increases in power consumption while suppressing increases in access time. [Brief explanation of the drawing]

[0008] [Figure 1] This is a block diagram showing an example of a memory circuit according to the first embodiment. [Figure 2] Figure 1 is a block diagram showing an example of a memory control unit. [Figure 3] Figure 1 is a block diagram showing an example of the memory block configuration. [Figure 4] This block diagram shows an example of the configuration of a memory group in Figure 3. [Figure 5] Figure 4 is a block diagram showing an example of the configuration of a memory unit. [Figure 6] Figure 5 is a timing diagram showing an example of memory read and write operations. [Figure 7] Figure 1 is a block diagram showing an example of the configuration of the memory group control unit. [Figure 8] Figure 4 is a state transition diagram showing an example of the transitions in the operating states of the memory unit array. [Figure 9]It is a flowchart showing an example of the operation of the memory group control unit in FIG. 7. [Figure 10] It is a flowchart showing an example of step S100 in FIG. 9. [Figure 11] It is a flowchart showing an example of step S200 in FIG. 9. [Figure 12] It is a flowchart showing an example of step S220 in FIG. 11. [Figure 13] It is a flowchart showing an example of step S300 in FIG. 9. [Figure 14] In the memory circuit of FIG. 1, it is an explanatory diagram showing an example of an operation to transition a memory unit row to the active mode ACT. [Figure 15] It is a timing diagram showing an example of the timing of signals when transitioning to the active mode in FIG. 14. [Figure 16] It is a timing diagram showing the continuation of FIG. 15. [Figure 17] It is an explanatory diagram showing an example of the write operation of the memory circuit in FIG. 1. [Figure 18] It is a timing diagram showing an example of the timing of signals during the write operation in FIG. 17. [Figure 19] It is a timing diagram showing the continuation of FIG. 18. [Figure 20] It is an explanatory diagram showing an example of the read operation of the memory circuit in FIG. 1. [Figure 21] It is a timing diagram showing an example of the timing of signals during the read operation in FIG. 20. [Figure 22] It is a timing diagram showing the continuation of FIG. 21. [Figure 23] It is a timing diagram showing the continuation of FIG. 22. [Figure 24] It is a timing diagram showing the continuation of FIG. 23. [Figure 25] It is a timing diagram showing another example of the timing of signals during the read operation of the memory circuit in FIG. 1. [Figure 26] It is a timing diagram showing the continuation of FIG. 25. [Figure 27] It is a timing diagram showing the continuation of FIG. 26. [Figure 28] This is a timing diagram showing a continuation of Figure 27. [Figure 29] Figure 1 is a block diagram showing an example of redundant circuitry incorporated into the memory circuit. [Figure 30] This block diagram shows an example of a system in which the memory circuit shown in Figure 1 is installed. [Figure 31] Block diagram showing an example of another memory circuit. [Figure 32] Figure 31 is a block diagram showing an example of the configuration of a memory group. [Figure 33] This is an explanatory diagram showing an example of the read operation of the memory circuit in Figure 31. [Figure 34] This is an explanatory diagram showing another example of the read operation of the memory circuit in Figure 31. [Modes for carrying out the invention]

[0009] The embodiments will be described below with reference to the drawings. In the following, the same symbols as the signal names will be used for signal lines through which information such as signals is transmitted. Also, signal lines shown with thick lines consist of multiple bits, but signal lines shown with single lines may also consist of multiple bits.

[0010] Figure 1 shows an example of a memory circuit according to the first embodiment. The memory circuit 100 shown in Figure 1 is mounted on a semiconductor device such as a system LSI that processes image data. For example, a semiconductor device including the memory circuit 100 is mounted on an imaging device such as a surveillance camera, a head-mounted device such as AR / VR (Augmented Reality / Virtual Reality) glasses, or a digital camera, and generates moving image data, etc., to be displayed on a display device.

[0011] The memory circuit 100 includes a memory block MBLK, a memory control unit 200 (input side) connected to the input side of the memory block MBLK, and a memory control unit 200 (output side) connected to the output side of the memory block MBLK. The memory control unit 200 (input side) is an example of a first memory control unit, and the memory control unit 200 (output side) is an example of a second memory control unit. Hereafter, when describing the memory control unit 200 (input side) and 200 (output side) without distinction, they will be referred to as the memory control unit 200.

[0012] The memory block MBLK comprises multiple memory groups MG arranged in one direction and containing multiple memory cells, and multiple memory group control units MCNTs positioned on the signal input side of each of the memory groups MG. The memory block MBLK also has a memory group control unit MCNT positioned on the signal output side of the final stage memory group MG. For example, each memory group MG is positioned between a pair of memory group control units MCNT. In other words, the memory group control units MCNT and memory groups MG are arranged alternately. The memory group control units MCNT function as interface circuits for signals input and output between the memory control unit 200 and the memory groups MG, or as interface circuits for signals input and output between the memory group control units MCNT.

[0013] Each memory group control unit (MCNT) has a flip-flop (FF) that receives access request signals (control signal CMD, address signal A, etc.), memory write data signals D, and read data signals Q, respectively. When each memory group control unit (MCNT) receives an access request signal for an adjacent memory group MG (hereinafter also referred to as its own memory group MG or managed memory group MG) on its output side, it outputs an access request signal to its own memory group MG. In the following, the memory group control unit (MCNT) that outputs an access request signal to the memory group control unit (MCNT) of interest is referred to as the preceding memory group control unit (MCNT). The memory group control unit (MCNT) that receives an access request signal from the memory group control unit (MCNT) of interest is referred to as the subsequent memory group control unit (MCNT).

[0014] In this case, each memory group control unit (MCNT) suppresses the output of access request signals to subsequent memory group control units (MCNTs), except for the signals used by the final-stage memory group control unit (MCNT). The subsequent memory group control unit (MCNT) is the memory group control unit (MCNT) located on the output side of the memory control unit 200, separated from the memory group control unit (MCNT) of interest by one memory group MG.

[0015] Furthermore, when each memory group control unit (MCNT) receives an access request signal for a memory group MG other than its own, it forwards the access request signal to the next memory group control unit (MCNT). In this case, each memory group control unit (MCNT) suppresses the output of the access request signal for its own memory group MG.

[0016] Each memory group control unit (MCNT) transfers the memory read data signal Q read from its own memory group MG during a read operation, or the memory read data signal Q transferred from the preceding memory group control unit (MCNT), to the subsequent memory group control unit (MCNT).

[0017] In this way, each memory group control unit MCNT can control access for each memory group MG. Since the command line CMD, address line A, write data line D, and read data line Q are not wired over long distances across multiple memory groups MG, the increase in wiring load can be suppressed. As a result, the increase in power consumption can be suppressed while suppressing the increase in access time of the memory circuit 100.

[0018] Furthermore, the number of clock cycles required for the transfer of access request signals, memory write data signals D, and memory read data signals Q between a pair of memory group control units (MCNTs) located on either side of a memory group MG is set to be the same for both. For example, the number of clock cycles required for the transfer of signals between a pair of memory group control units (MCNTs) located on either side of a memory group MG is "1". Since the signals transferred between memory group control units (MCNTs) are not affected by the load on the signal wiring within the memory group MG (e.g., signal skew), the number of clock cycles required for the transfer can always be the same regardless of the number of memory group units in the array.

[0019] Therefore, for example, when adding a memory group MG between the memory control unit 200 (input side) and the memory control unit 200 (output side), the number of clock cycles should be increased according to the number of added memory groups. This makes it easy to design timing even when increasing or decreasing the number of memory groups MG to design other memory circuits with different storage capacities. In Figure 1, the final-stage memory group control unit MCNT adjacent to the memory control unit 200 (output side) does not have a managed memory group MG, but it has the function of readjusting the timing for the memory control unit 200 (output side). A final-stage memory group control unit MCNT that does not have a managed memory group MG is functionally a subset of other memory group control units MCNTs.

[0020] The memory control unit 200 is connected to the system bus SBUS of the semiconductor device and to a peripheral bus that inputs and outputs various control signals CNTL. While not particularly limited, the system bus SBUS may, for example, input and output signals based on ARM's AXI4 (Advanced eXtensible Interface 4) (another company's trademark). The memory control unit 200 functions as an interface circuit between signals input and output to the system bus SBUS and signals input and output to the memory group control unit MCNT.

[0021] Figure 1 shows an example where two rows of memory group control units MCNT and memory group MG are arranged between the memory control unit 200 (input side) and the memory control unit 200 (output side). However, only one or more rows of memory group control units MCNT and memory group MG are required. Furthermore, the rows of memory group control units MCNT and memory group MG may be arranged in a U-shape. In this case, the memory control unit 200 (input side) and the memory control unit 200 (output side) are arranged together at one end of the area where the memory group control units MCNT and memory group MG are located.

[0022] The memory control unit 200 (input side) receives request signals such as REQ for read and write operations to the memory circuit 100, address signals ADR, and write data signals WD from a higher-level controller such as the CPU (Central Processing Unit) via the system bus SBUS. The request signal REQ is an example of a request signal (access request signal) that causes the memory group MG to perform a write or read operation, or a request signal that changes the operating mode of the memory group MG. The access request signal is either a write request signal or a read request signal. Note that in Figure 1, only the flow of major information signals is shown for the sake of simplification. Although not shown in the figure, there are also additional information signals, signals indicating the validity or invalidity of each signal, and control signals indicating data output instructions or data acquisition instructions.

[0023] The memory control unit 200 (input side) generates a control signal CMD containing additional information for accessing the memory within the memory group MG, based on the address signal ADR and the request signal REQ which includes information such as the request ID or access size. The memory control unit 200 (input side) outputs the generated control signal CMD to the first-stage memory group control unit MCNT.

[0024] For example, the memory control unit 200 (input side) outputs a 512-bit memory write data signal D to the two first-stage memory group control units MCNT in 256-bit increments every eight times it receives a 64-bit write data signal WD. In other words, the memory control unit 200 (input side) converts the N-bit (64-bit in this example) write data signal WD received from the system bus SBUS into an (N × M)-bit (in this example, M is "8") memory write data signal D, and causes the memory group MG to execute the write operation of the memory write data signal D. Depending on the address ADR or data size from the system bus SBUS, it may not be possible to receive all 512 bits of the memory write data signal D before receiving the write data signal WD eight times, but only the valid data is written to the memory circuit 100 due to the mask information included in the control signal CMD, etc.

[0025] Furthermore, the memory control unit 200 (input side) receives a control signal CNTL via the peripheral bus that sets the operating specifications of at least one of the memory group MG and the memory group control unit MCNT. In addition, the memory control unit 200 (input side) outputs the operating specifications of at least one of the memory group MG and the memory group control unit MCNT as a control signal CNTL to the peripheral bus. For example, the peripheral bus is a slower interface than the system bus SBUS.

[0026] The memory control unit 200 (output side) receives access control signals such as the command signal CMD and address signal A from one of the two memory group control units MCNT in the final stage. The memory control unit 200 (output side) receives the memory read data signal Q from the two memory group control units MCNT in the final stage and outputs the read data signal RDT to the system bus SBUS. For example, each time the memory control unit 200 (output side) receives two 256-bit memory read data signals Q, it outputs a 64-bit read data signal RDT eight times. In other words, the memory control unit 200 converts the parallel memory read data signal Q read from the memory group MG into a serial read data signal RDT and outputs it to the system bus SBUS.

[0027] The 512-bit data input / output to the memory block BLK is eight times the 64-bit data input / output to the system bus SBUS. Therefore, ideally, the operating frequency of the memory block MBLK can be reduced to one-eighth of the operating frequency of the system bus SBUS. Consequently, the power consumption of the memory block MBLK can be reduced compared to when 64-bit data is input / output to the memory block MBLK. Because the operating frequency of the memory block MBLK can be lowered, there can be more operating margin for the memory group control unit MCNT and the memory group MG, making it easier to implement circuit timing design and other related processes.

[0028] The number of bits of data input to and output to the memory block BLK should be 2 to the power of n times the number of bits of data input to and output to the system bus SBUS (where n is an integer greater than or equal to 1; in this example, n=3).

[0029] Figure 2 is a block diagram showing an example of the memory control unit 200 in Figure 1. The memory control unit 200 (input side) includes a system bus input control unit 202, buffers 204 and 206, peripheral bus control unit 208, overall management unit 210, memory state management unit 212, and input interface control unit 214. The memory control unit 200 (output side) includes an output interface control unit 220, buffers 222 and 224, and system bus output control unit 226.

[0030] The system bus input control unit 202 stores the address signal ADR, the request signal REQ which includes information such as the request ID or access size, the command signal CMD which includes additional information for memory control, and the address signal A in buffer 204. It receives the write data signal WD from the system bus SBUS up to eight times and stores 512 bits of data and 1 bit of additional information (Last information), for a total of 513 bits (hereinafter, unless otherwise specified, the explanation of the Last signal will be omitted and the total will be 512 bits) in buffer 206.

[0031] Buffers 204 and 206 are, for example, FIFO (First-In First-Out) buffers. Buffer 204 outputs the control signal CMD and address signal A to the input interface control unit 214 in the order in which they are held. Buffer 206 outputs the write data WD to the input interface control unit 214 in the order in which it is held. Buffer 204 outputs the 512-bit memory write data WD to the input interface control unit 214.

[0032] The input interface control unit 214 waits for valid information to be prepared in buffer 204. Once the information in buffer 204 becomes valid, it checks information A and, if the memory area to be accessed within the target memory block MBLK is not in an active state, it performs a process to make it active. Once it becomes active, it checks the CMD information in buffer 204, and if it is a read operation for memory block MBLK, it retrieves the information from buffer 204 and outputs the control signal CMD and address A, etc., to memory block MBLK to execute the read operation.

[0033] The CMD information in buffer 204 is checked, and if a write operation is performed on memory block MBLK, the system waits for the information in buffer 206 to become valid. Once the information in buffer 206 becomes valid, information D and Last information are retrieved, and the control signal CMD and address A etc. are output to execute a write or read operation on memory block MBLK, while the write data signal WD is output to memory block MBLK as two 256-bit memory write data signals D.

[0034] The peripheral bus control unit 208 outputs various control signals CNTL received from the peripheral bus to the overall management unit 210. The peripheral bus control unit 208 also outputs various control signals CNTL received from the overall management unit 210 to the peripheral bus.

[0035] The overall management unit 210 has several registers (not shown) for setting the operating specifications, such as the operating mode, of the memory group MG (Figure 1). The overall management unit 210 sets the registers according to various control signals CNTL from the peripheral bus. For example, the operating modes include shutdown mode, sleep mode, and active mode. For example, the shutdown mode, sleep mode, and active mode can be switched on a unit basis of the memory unit row MUC, which will be described later. However, the unit for switching between the shutdown mode, sleep mode, and active mode is not limited to the memory unit row MUC.

[0036] For example, in shutdown mode, the power supply to the memory cell area of ​​the memory unit row MUC to be shut down is cut off, and the power supply to peripheral circuits other than the memory cell area that are not related to shutdown and sleep control is cut off. In sleep mode, the power supply to the memory cell area of ​​the memory unit row MUC to be slept is reduced to a low voltage that can maintain the data held in the memory cells, and the power supply to peripheral circuits other than the memory cell area that are not related to shutdown and sleep control is cut off. In this embodiment, an example is shown in which the memory block MBLK itself has a built-in power supply circuit for the shutdown and sleep functions, but even if the memory block MBLK itself does not have a power supply circuit, this technology can be applied if the power supply voltage of the memory cell area and the power supply voltage of peripheral circuits other than the memory cell area can be adjusted or the power supply cut off on a per-memory unit row MUC or per-memory group MG basis by a power supply circuit provided outside the memory block MBLK.

[0037] In active mode, write or read operations can be performed. Additionally, the registers of the memory state management unit 212 may contain a time limit for transitioning to sleep mode if there is no access during active mode.

[0038] The memory state management unit 212 manages the operating mode of the memory unit row MUC based on the settings of several built-in registers. The memory state management unit 212 also maintains fault information indicating the location of faulty memory cells within the memory group MG and performs management to access normal memory cells instead of faulty ones.

[0039] The output interface control unit 220 stores two 256-bit memory read data signals Q received from the memory block MBLK in the buffer 224 during the read operation of the memory block MBLK. The output interface control unit 220 also stores the control signal CMD and address signal A, which include additional information for memory control, received from the memory block MBLK in the buffer 222.

[0040] Buffers 222 and 224 are, for example, FIFO buffers. Buffer 222 outputs the control signal CMD and address signal A, which contain additional information for memory control, to the system bus output control unit 226 in the order in which they are held. Buffer 224 outputs two 256-bit memory read data signals Q as 512-bit read data to the system bus output control unit 226.

[0041] The memory control unit 200 has a function to convert between the frequency of data input / output to the system bus SBUS and the frequency of data input / output to the memory block MBLK. For example, in the memory control unit 200, the input side of buffers 204 and 206 operates with the system clock signal SCLK used by the system bus SBUS. In the memory control unit 200, the output side of buffers 204 and 206 operates with the memory clock signal MCLK used by the memory block MBLK.

[0042] Similarly, in the memory control unit 200, the input side of buffers 222 and 224 operates with the memory clock signal MCLK used in the memory block MBLK. In the memory control unit 200, the output side of buffers 222 and 224 operates with the system clock signal SCLK used in the system bus SBUS. Thus, buffers 204, 206, 222, and 224 also function as clock swapping circuits.

[0043] The system bus output control unit 226 receives the control signal CMD and address signal A, which include additional information for memory control, output from buffer 222, and the 512-bit memory read data signal Q, which is output from buffer 224. In response to the control signal CMD and address signal A, which include additional information for memory control, the system bus output control unit 226 sequentially outputs the 512-bit memory read data signal Q to the system bus SBUS as up to eight 64-bit read data RDTs. Depending on the size information included in the address signal A and the additional information, the 512-bit memory read data signal Q may include data that is not to be accessed. Only the data to be accessed is output to the system bus SBUS.

[0044] Figure 3 shows an example of the configuration of the memory block MBLK in Figure 1. In the following description, the memory block MBLK is assumed to have eight memory groups MG (MG10, MG11, MG20, MG21, MG30, MG31, MG40, MG41) arranged in a 2x4 grid. Note that the number and arrangement of memory groups MG mounted on the memory block MBLK are not limited to the example shown in Figure 3.

[0045] Each memory block MBLK has memory group control units MCNT (MCNT10, MCNT11, MCNT20, MCNT21, MCNT30, MCNT31, MCNT40, MCNT41) located on the input side of each memory group MG. Furthermore, each memory block MBLK has memory group control units MCNT50 and MCNT51 located on the output side of the final-stage memory groups MG40 and MG41, respectively.

[0046] Each memory group MG has 16 memory units MU arranged in a 4x4 grid. The number and arrangement of memory units MU mounted in each memory group MG are not limited to the example shown in Figure 3.

[0047] While not particularly limited, the size of each memory unit MU is 32k words × 64 bits (= 2M bits), and four memory units MU arranged vertically input and output 256 bits of data. The size of a memory group MG containing 16 memory units MU is 128k words × 256 bits (= 32M bits). The size of a memory block MBLK containing eight memory groups MG is 512k words × 512 bits (= 256M bits).

[0048] A memory group column MGC is formed by two vertically aligned memory groups MG. A memory unit column MUC is formed by four vertically aligned memory units MU. The memory unit column MUC is an example of a sub-memory group. For example, each memory group column MGC is identified by bits AD[24:23] of the 25-bit address signal A. Each memory unit column MUC is identified by bits AD[22:21] of the 25-bit address signal A.

[0049] In this embodiment, the unit for switching between shutdown mode, sleep mode, and active mode is the memory unit row MUC. Sleep mode is an example of a low-power mode. The memory unit row MUC is an example of a sub-memory group that is the unit for switching between sleep mode and active mode.

[0050] Furthermore, the shutdown mode, sleep mode, and active mode may be switched on a unit basis of two vertical memory unit columns (MUC), or on a unit basis of columns obtained by further subdividing the memory unit column (MUC) into multiple columns. For example, they may be switched on a unit basis of the memory column (MEMC) as shown in Figure 5 below. In addition, the shutdown mode, sleep mode, and active mode may be switched on a unit basis of the memory group (MG).

[0051] For example, in each memory unit row MUC, the power consumption in shutdown mode is about one-tenth of the standby power consumption in active mode, and the power consumption in sleep mode is about one-third of the standby power consumption in active mode.

[0052] The input-side memory group control unit MCNT of each memory group MG outputs a control signal CMD, an address signal A, and a memory write data signal D to the memory group MG and the output-side memory group control unit MCNT of the memory group MG. Each memory group MG outputs a memory read data signal Q to the output-side memory group control unit MCNT. As shown in Figure 3, the command line CMD and address line A are not wired across multiple memory groups MG. Therefore, the increase in wiring load can be suppressed. As a result, the increase in power consumption can be suppressed while suppressing the increase in access time of the memory circuit 100.

[0053] Figure 4 shows an example of the configuration of the memory group MG in Figure 3. The code (i) appended to the end of the signal indicates an input signal, and the code (o) appended to the end of the signal indicates an output signal. The memory group MG receives the memory clock signal MCLK, 16 chip enable signals CEB, write enable signal WEB, and bit write enable signal BWEB from the memory group control unit MCNT as the control signal CMD in Figure 3. The 16 chip enable signals CEB are supplied in groups of four to the memory unit row MUC and used for selecting the memory unit row MUC and the memory row MEMC within the memory unit row MUC (Figure 5, described later).

[0054] For example, signals with the sign B at the end are negative logic signals, and signals without the sign B at the end are positive logic signals. The bit write enable signal BWEB is a signal that controls the writing of data signals bit by bit, and the bit write enable signal BWEB corresponding to the bit to be masked during writing is set to a high level.

[0055] Furthermore, the memory group MG receives the address signal A and the 256-bit memory write data signal D, and outputs the memory read data signal Q. The 256-bit memory write data signal D is supplied in 64-bit increments to the four memory units MU of the memory unit row MUC. The memory group MG has multiple selectors SEL that select one of the 64-bit memory read data signals Q output from the four horizontally arranged memory units MU and output it to the memory group control unit MCNT.

[0056] Furthermore, the memory group MG receives the shutdown signal SD and the sleep signal SLP from the memory group control unit MCNT as the control signal CMD in Figure 3. As explained in Figure 3, in this embodiment, the switching between shutdown mode, sleep mode, and active mode is performed on a per-memory unit row MUC basis. Therefore, the shutdown signal SD and the sleep signal SLP are supplied for each memory unit row MUC.

[0057] The code SDO of each memory unit MU indicates a terminal that outputs a shutdown signal SD to adjacent memory units MU in the memory unit row MUC. The code SLPO of each memory unit MU indicates a terminal that outputs a sleep signal SLP to adjacent memory units MU in the memory unit row MUC. This allows the shutdown signal SD and sleep signal SLP, which are shared by the last memory unit MU in the memory unit row MUC, to be sequentially transmitted to other memory units MU in the memory unit row MUC. When the operating mode of a memory unit MU is switched, a phenomenon called inrush current occurs, in which a temporarily larger current flows than usual. By sequentially transmitting the shutdown signal SD and sleep signal SLP to the memory units MU, the timing of the operating mode switching of the four memory units MU in the memory unit row MUC can be sequentially staggered, and the timing of the occurrence of inrush current is also staggered, thus suppressing the peak current.

[0058] Figure 5 shows an example of the configuration of the memory unit MU in Figure 4. The memory unit MU has eight memory MEMs arranged in a 2x4 grid. The size of each memory MEM is 8k words × 32 bits (= 256k bits). For example, a memory MEM may have multiple SRAM memory cells, but it may also have memory cells of other volatile memory. Alternatively, a memory MEM may have memory cells of non-volatile memory such as MRAM (Magnetoresistive Random Access Memory) or ReRAM (Resistive Random Access Memory). Note that the number and arrangement of memory MEMs mounted on the memory unit MU are not limited to the example shown in Figure 5.

[0059] The memory MEM within the memory unit MU transmits the shutdown signal SD and the sleep signal SLP sequentially, similar to the memory unit MU within the memory group MG shown in Figure 4. This further suppresses the peak current. The shutdown signal SD and the sleep signal SLP may be further subdivided. For example, the peak current can be further suppressed by controlling the shutdown signal SD and the sleep signal SLP in units of a memory column MEMC containing two memory MEMs arranged vertically.

[0060] Figure 6 shows an example of read and write operations for the memory MEM in Figure 5. During read and write operations, the shutdown signal SD and sleep signal SLP must be fixed at a low level (L), and the memory unit row MUC being operated on must be in an active state.

[0061] The read operation begins on the rising edge of the clock signal CLK, when the chip enable signal CEB is low and the write enable signal WEB is high. The memory MEM reads data from the memory region indicated by the address signal A, which is received synchronously with the rising edge of the clock signal CLK, and outputs the memory read data signal Q at time tcd from the rising edge of the clock signal CLK.

[0062] The write operation begins on the rising edge of the clock signal CLK, when the chip enable signal CEB is low and the write enable signal WEB is low. The memory MEM receives the address signal A and the memory write data signal D in synchronization with the rising edge of the clock signal CLK. The memory MEM then writes the memory write data signal D to the memory area indicated by the received address signal A. However, the memory MEM masks write operations for bits where the bit value of the bit write enable signal BWEB, which is received in synchronization with the rising edge of the clock signal MCLK, is high.

[0063] When the bit value of the bit write enable signal BWEB is low, the bit value of the corresponding memory write data signal D is written to the memory cell. Figure 6 shows that in WriteCycle i, since the BWEB(i) bit is low, the value of the corresponding D(i) bit is written to the memory cell, and since the BWEB(j) bit is high, the writing of the corresponding D(j) bit to the memory cell is masked. Similarly, in WriteCycle j, since the BWEB(j) bit is low, the corresponding D(j) bit is written to the memory cell, and since the BWEB(i) bit is high, the writing of the corresponding D(i) bit to the memory cell is masked. Although not shown in the figure, if all BWEB bits are low, the values ​​of all D bits are written to the memory cell, and if all BWEB bits are high, the writing of all D bit values ​​to the memory cell is masked.

[0064] Figure 7 shows an example of the configuration of the memory group control unit MCNT in Figure 1. The memory group control unit MCNT has multiple flip-flops FF (FF1, FF2, FF3, FF4, FF5, FF6, FF7), a relay control unit RCNT, and multiple mask circuits MSK (MSKC, MSKW1, MSKW2, MSKR). Multiple flip-flops FF, to which thick signal lines are connected, are composed of each other. Signals with (i) appended to the end indicate input signals, and signals with (o) appended to the end indicate output signals.

[0065] In Figure 7, the code PARAM(i) is a multi-bit signal used to identify the memory group control unit MCNT, and is fixed at a high or low level on a bit-by-bit basis. The logic of the PARAM(i) signal is determined during the design of the memory circuit 100. The code CAWD(i) indicates the control signal CMD and address A received from the preceding memory group control unit MCNT. The code D[255:0](i) indicates the memory write data signal D received from the preceding memory group control unit MCNT. The upper code Q[255:0](i) indicates the memory read data signal Q from the preceding memory group MG. The lower code Q[255:0](i) indicates the memory read data signal Q received from the preceding memory group control unit MCNT.

[0066] The code CAWD(o) indicates the control signal CMD and address signal A output to the subsequent memory group control unit MCNT. The codes CEB[3:0], WEB[3:0], A, BWEB, SLP[3:0], and SD[3:0] indicate various control signals and address signal A output to the own memory group MG. The upper code D[255:0](o) indicates the memory write data signal D output to the subsequent memory group control unit MCNT. The lower code D[255:0](o) indicates the write data signal D output to the own memory group MG. The code Q[255:0](o) indicates the memory read data signal Q output to the subsequent memory group control unit MCNT.

[0067] The memory clock signal MCLK is transmitted to each synchronization circuit within the memory group control unit MCNT via buffer BUF1. The memory clock signal MCLK output from buffer BUF1 is output to the subsequent memory group control unit MCNT via buffer BUF2. Furthermore, the memory clock signal MCLK output from buffer BUF1 is output to its own memory group MG as the memory clock signal IMCLK via buffer BUF3.

[0068] When the command address enable signal CAEN is at a valid level, flip-flop FF1 holds and outputs the received control signal CMD, address signal A, and additional information (command address signal CAWD). The command address enable signal CAEN is output from the memory control unit 200 along with the control signal CMD and address signal A. Flip-flop FF2 forwards the command address enable signal CAEN received from the memory control unit 200 or the preceding memory group control unit MCNT to the subsequent memory group control unit MCNT. For example, the valid level of the command address enable signal CAEN is high.

[0069] When the write data enable signal WDEN is at a valid level, the flip-flop FF3 holds and outputs the received 256-bit write data signal D. The write data enable signal WDEN is output from the memory control unit 200 along with the write data signal D. The flip-flop FF4 forwards the write data enable signal WDEN, which it receives from the memory control unit 200 or the preceding memory group control unit MCNT, to the subsequent memory group control unit MCNT. For example, the valid level of the write data enable signal WDEN is high.

[0070] The flip-flop FF5 holds and outputs a 256-bit memory read data signal Q received via the selector SELQ when the read data enable signal RDEN, received from the preceding memory group control unit MCNT, is at an effective level. For example, the effective level of the read data enable signal RDEN is high.

[0071] The memory read data signal Q is output from the preceding memory group MG and the preceding memory group control unit MCNT, respectively. The preceding memory group MG is a memory group MG located adjacent to the memory control unit 200 (input side) with respect to the memory group control unit MCNT of interest. The operation of the preceding memory group MG is controlled by the memory group control unit MCNT preceding the memory group control unit MCNT of interest.

[0072] The selector SELQ selects the memory read data signal Q read from the preceding memory group MG or the memory read data signal Q transferred from the preceding memory group control unit MCNT, according to the level of the control signal from the relay control unit RCNT. The selector SELQ allows the memory read data signal Q to be transferred to the memory control unit 200 regardless of the position of the memory group MG that outputs the memory read data signal Q.

[0073] The read data enable signal RDEN is output from either the preceding memory group control unit MCNT or the memory group control unit MCNT preceding it. The flip-flop FF6 forwards the read data enable signal RDEN received from the preceding memory group control unit MCNT to the subsequent memory group control unit MCNT via an OR circuit. Note that the first-stage memory group control unit MCNT does not receive the memory read data signal Q from the preceding memory group MG or the memory read data signal Q from the preceding memory group control unit MCNT. The second-stage memory group control unit MCNT does not receive the memory read data signal Q from the preceding memory group control unit MCNT.

[0074] The flip-flop FF7 in the preceding memory group control unit MCNT receives the read data enable signal IRDEN output from the relay control unit RCNT and outputs it as an RDEN signal via an OR circuit to the memory group control unit MCNT of interest, after a 1-clock delay. As shown in Figure 6, in this embodiment, the memory circuit 100 outputs data with a tcd time delay from the read request timing (CEB=L, WEB=H, CLK rising edge). Therefore, the memory read data signal Q, which is the data read from the preceding memory group MG by the IRDEN signal, is captured by the flip-flop FF5 in the subsequent memory group control unit MCNT. For example, the effective level of the read data enable signal IRDEN is high. Note that if a memory circuit different from the timing at which the read data of the memory circuit 100 in this embodiment shown in Figure 6 becomes effective is used, the circuit configuration of the part in the memory group control unit MCNT that generates the RDEN signal from the IRDEN signal will change.

[0075] The relay control unit RCNT controls its own operation as well as the operation of the subsequent memory group MG. The subsequent memory group MG is a memory group MG that is positioned adjacent to the memory control unit 200 (output side) with respect to the memory group control unit MCNT of interest, and whose operation is controlled by the memory group control unit MCNT of interest.

[0076] The relay control unit RCNT operates according to a parameter signal PARAM, which indicates which stage of memory group control unit MCNT it is relative to the memory control unit 200. Each bit of the parameter signal PARAM is fixed to a high or low level outside each memory group control unit MCNT based on the overall design of the memory circuit 100, specifying which stage of memory group control unit MCNT each unit is. For example, in the configuration shown in Figure 3, there are five memory group control units laterally. In this case, the PARAM signal is 3 bits and represents one of the values ​​from 0 to 7.

[0077] In Figure 3, the leftmost memory group control units MCNT10 and MCNT11 are set to PARAM=1. The second memory group control units from the left, MCNT20 and MCNT21, are set to PARAM=2. The rightmost memory group control units MCNT50 and MCNT51, which do not have their own memory generator (MG), are set to PARAM=0. Since the memory group control units MCNT10 and MCNT11 with PARAM=1 are located on the far left and do not receive the memory read data signal Q from the preceding stage, they do not need to have circuits such as flip-flops FF5 and FF6 and selector SELC for receiving the memory read data signal from the preceding stage. The memory group control units MCNT50 and MCNT51 with PARAM=0 are located on the far right and do not need to transmit the memory write data signal D to the subsequent stage, so they do not need to have circuits such as flip-flops FF3 and FF4 and mask circuits MSKW1 and MSKW2.

[0078] The relay control unit RCNT can detect the memory group MG that is performing a write or read operation by processing the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, from the flip-flop FF1. If the relay control unit RCNT determines that a write operation is being performed on the subsequent memory group MG, it outputs a low-level chip enable signal CEB, a low-level write enable signal WEB, address A, and bit write enable signal BWEB to the subsequent memory group MG. The chip enable signal CEB and the write enable signal WEB are generated corresponding to each of the four memory unit rows MUC within the subsequent memory group MG.

[0079] When the relay control unit RCNT determines that a read operation is being performed on its own memory group MG, it outputs a low-level chip enable signal CEB, a high-level write enable signal WEB, and address A to the memory unit column MUC being read. When the relay control unit RCNT determines that its own memory group MG is transitioning to sleep mode or shutdown mode, it outputs a predetermined logical level sleep signal SLP and shutdown signal SD to the memory unit column MUC being controlled. The sleep signal SLP and shutdown signal SD are generated corresponding to each of the four memory unit column MUCs within its own memory group MG.

[0080] When the relay control unit RCNT determines that its own memory group MG should be released from sleep mode or shutdown mode, it outputs a low-level sleep signal SLP and a low-level shutdown signal SD to its own memory group MG. The state of each memory unit row MUC is managed collectively by the memory state management unit 212 within the memory control unit 200. If it is necessary to release the memory from sleep mode or shutdown mode before a write or read operation is performed, the memory control unit 200 outputs a change command to change the state of the memory unit MUC before outputting the write or read operation command.

[0081] For example, during shutdown mode, the sleep signal SLP and shutdown signal SD are set to low and high levels, respectively. During sleep mode, the sleep signal SLP and shutdown signal SD are set to high and low levels, respectively. During active mode, both the sleep signal SLP and shutdown signal SD are set to low levels.

[0082] When the memory circuit 100 is started, the sleep signal SLP and the shutdown signal SD are set to low and high levels, respectively, and all memory unit rows MUC within the memory group MG are set to shutdown mode. After this, only the memory unit row MUC to be operated transitions from shutdown mode to active mode ACT, and write or read operations are performed. Furthermore, if there is no access for a predetermined period while in active mode, the memory control unit 200 outputs a memory state change command, and the memory unit row MUC within the memory group MG managed by the corresponding memory group control unit MCNT transitions from active mode to sleep mode. The predetermined period for determining the transition from active mode to sleep mode can be changed by the setting value of the register in the memory state management unit 212 shown in Figure 2.

[0083] Furthermore, memory unit arrays (MUCs) in sleep mode or active mode can transition to shutdown mode based on instructions from the memory control unit 200. In this way, memory unit arrays (MUCs) on which write or read operations are performed are set to active mode and remain in active mode as long as continuous access is occurring. If there is no access for a certain period of time, they are returned to sleep mode. By minimizing the number of memory unit arrays (MUCs) set to active mode, the power consumption of the memory circuit (MEM) can be reduced.

[0084] The relay control unit RCNT detects, based on the control signal CMD and address signal A received from the preceding memory group control unit MCNT, that a memory read data signal Q is output from the preceding or preceding memory group MG. If the memory read data signal Q is output from the preceding memory group MG, the relay control unit RCNT selects the memory read data signal Q from the preceding memory group MG using the selector SELECTQ. If the memory read data signal Q is output from a memory group MG that precedes the preceding stage, the relay control unit RCNT selects the memory read data signal Q to be transferred from the preceding memory group control unit MCNT using the selector SELECTQ.

[0085] The relay control unit RCNT releases the mask state of the mask circuit MSKR when the read data enable signal RDEN is at an active level (e.g., high level), and sets the mask circuit MSKR to a mask state when the read data enable signal RDEN is at an inactive level (e.g., low level). As a result, when the memory group control unit MCNT receives a 256-bit memory read data signal Q from the preceding memory group MG, it can relay the memory read data signal Q to the subsequent memory group control unit MCNT. Furthermore, if the relay control unit RCNT does not receive a memory read data signal Q from the preceding stage, it suppresses the transfer of the invalid memory read data signal Q to the subsequent memory group control unit MCNT. This reduces power consumption.

[0086] The relay control unit RCNT detects that a memory read data signal Q is output from its own memory group MG based on the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, received from the preceding memory group control unit MCNT. When the memory read data signal Q is output from its own memory group MG, the relay control unit RCNT outputs a read data enable signal IRDEN at an effective level to the flip-flop FF7. The flip-flop FF7 outputs the read data enable signal IRDEN to the subsequent memory group control unit MCNT via an OR circuit.

[0087] The relay control unit RCNT outputs the read data enable signal IRDEN in the same cycle as the chip enable signal CEB, which causes the subsequent memory group MG to perform a read operation. Therefore, the read data enable signal RDEN output from the flip-flop FF7 is supplied to the subsequent memory group control unit MCNT one cycle after the subsequent memory group MG starts its read operation. Consequently, the subsequent memory group control unit MCNT can hold the memory read data signal Q received from the corresponding memory group MG in the flip-flop FF5.

[0088] When a read operation is performed in the preceding memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKR in order to transfer the memory read data signal Q to the subsequent memory group control unit MCNT. Also, when a write operation is performed in the subsequent memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKW1 in order to transfer the write data signal D to the subsequent MCNT. Furthermore, to suppress the transfer of the write data signal D to its own memory group MG, the relay control unit RCNT sets the mask circuit MSKW2 to the mask state.

[0089] The relay control unit RCNT sets the mask state of the mask circuit MSKC to unmasked in order to transfer the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, to the subsequent memory group control unit MCNT. When a write operation is performed in a subsequent memory group MG or a memory group behind the subsequent stage, the relay control unit RCNT unmasks the mask state of the mask circuit MSKC in order to transfer the control signal CMD, address signal A, and command address signal CAWD, which includes additional information, to the subsequent memory group control unit MCNT. When a write operation is performed in any of its own memory groups MG, the relay control unit RCNT sets the mask state of the mask circuit MSKC in order to transfer the command address signal CAWD to the subsequent memory group control unit MCNT. In a read operation, the final stage memory group control unit MCNT can execute control to output the control signal CMD, address signal A, command address signal CAWD, which includes additional information, and memory read data signal Q to the memory control unit 200.

[0090] When a write operation is performed in its own memory group MG, the relay control unit RCNT sets the mask circuit MSKW1 to the masked state in order to suppress the transfer of the write data signal D to the memory group control unit MCNT. Furthermore, it releases the mask state of the mask circuit MSKW2 in order to transfer the memory write data signal D to its own memory group MG.

[0091] When a write operation is performed in a subsequent memory group MG, the relay control unit RCNT releases the mask state of the mask circuit MSKW1 in order to transfer the write data signal D to the subsequent memory group control unit MCNT. When a write operation is performed in a subsequent memory group MG, the relay control unit RCNT sets the mask circuit MSKW2 to the mask state in order to suppress the transfer of the memory write data signal D to its own memory group MG.

[0092] Figure 8 shows an example of the transition of the operating states of the memory unit array MUC in Figure 4. The state transitions in Figure 8 are managed by the memory group control unit MCNT, which controls the operation of the memory unit array MUC. However, the transition to shutdown mode SD is performed by register settings in the memory state management unit 212 of the memory control unit 200.

[0093] Figure 8 shows the state transitions at the level of switching between shutdown mode SD, sleep mode SLP, and active mode ACT. Therefore, when the unit for switching between shutdown mode SD, sleep mode SLP, and active mode ACT is the memory group MG, Figure 8 shows the state transitions of the memory group MG. When the switching of the operating mode is performed at the level of the memory column MEMC within the memory unit column MUC, Figure 8 shows the state transitions at the level of the memory column MEMC. An example of control at the level of the memory unit column MUC is described below.

[0094] When the memory circuit MEM in Figure 1 is started, the state of all memory unit rows MUCs is set to shutdown mode SD. When a write or read request occurs in a memory unit row MUC, it transitions from shutdown mode SD to active transition mode ATRNS, and, for example, power is turned on to peripheral circuits other than the memory cell area. Then, after a period of time for the power supply to stabilize, the memory unit row MUC transitions to active mode ACT, and the write or read operation is executed. In active mode ACT, the write or read operation is executed each time a write or read request occurs for that memory unit row MUC.

[0095] In active mode (ACT), if a predetermined period of time passes without any write or read requests, the memory unit column (MUC) transitions to sleep mode (SLP). Sleep mode (SLP) is an example of a low-power mode that suppresses power consumption while retaining the data held by the memory unit column (MUC). By switching a memory unit column (MUC) that has not performed write or read operations for a predetermined period from active mode (ACT) to sleep mode (SLP), the power consumption of the memory circuit (100) can be reduced. In sleep mode (SLP), a memory unit column (MUC) that has received a write or read request transitions to active transition mode (ATRNS).

[0096] The memory unit column MUC transitions to shutdown mode SD when a shutdown instruction for the memory unit column MUC is issued in active mode ACT or sleep mode SLP. The shutdown instruction is performed, for example, by register setting in the memory state management unit 212 based on the reception of the control signal CTNL shown in Figure 2. Depending on the application, it is also possible to implement an embodiment in which the memory unit column MUC transitions to shutdown mode SD if sleep mode SLP continues for a predetermined time. In this case, the duration of sleep mode SLP may be set in advance in the register of the overall management unit 210 shown in Figure 2. Automatic transition to shutdown mode SD is possible, for example, in the processing of moving images, when frame image data held in the memory circuit 100 is guaranteed to be accessed within a certain period of time, and when it can be guaranteed that the data held there will not be used if there is no access for a certain period of time or longer. For example, when memory access processing is performed at a certain screen size, and then the screen size is switched to a smaller screen size and the memory access processing continues, unused memory areas will be created from the memory area used when processing at the initial screen size when the screen size is switched to a smaller screen size. In such cases, automatically transitioning to the shutdown signal SD based on the duration of the sleep mode SLP makes access control of the memory circuit 100 easier compared to issuing a shutdown command from an external source.

[0097] Furthermore, the duration of sleep mode SLP until transitioning to shutdown mode SD may be set based on statistical information such as access frequency. In this case, the memory control unit 200 is further equipped with an acquisition circuit for acquiring statistical information such as the time from transitioning to the sleep state to the active state, the frequency of transitions from the active state to the sleep state, and the frequency of access in the active state, as well as a circuit for calculating the duration.

[0098] Figures 9 to 13 show an example of the operation of the memory group control unit MCNT in Figure 7. The processes shown in Figures 9 to 13 are executed for each memory unit row MUC by the relay control unit RCNT of the multiple memory group control units MCNT within the memory circuit 100. In the processes shown in Figures 9 to 13, an example is shown where the unit for switching between shutdown mode SD, sleep mode SLP, and active mode ACT is the memory unit row MUC.

[0099] First, in step S10, the relay control unit RCNT waits until it detects a positive edge of the system clock signal SCLK. If it detects a positive edge, it executes step S12. In step S12, if a state transition request is issued, the relay control unit RCNT executes step S100 (state transition processing). If no state transition request is issued, it executes step S14. An example of step S100 is shown in Figure 10.

[0100] State transition requests are active commands to transition to active mode (ACT), sleep commands to transition to sleep mode (SLP), or shutdown commands to transition to shutdown mode (SD). For example, an active command is issued by the corresponding relay control unit (RCNT) based on a write or read request when the memory unit column (MUC) to be accessed is in shutdown mode (SD) or sleep mode (SLP). A shutdown command is issued by the memory control unit (RCNT) based on a request issued to the memory circuit (100) via the system bus (SBUS). A sleep command is issued by the corresponding relay control unit (RCNT) to transition the memory unit column (MUC) from active mode (ACT) to sleep mode (SLP). Note that the sleep command may also be issued by the memory control unit (200) based on a request issued to the memory circuit (100) via the system bus (SBUS).

[0101] In step S14, the relay control unit RCNT executes step S200 (read operation) if a read request is issued, and executes step S16 if no read request is issued. An example of step S200 is shown in Figures 11 and 12. In step S16, the relay control unit RCNT executes step S300 (write operation) if a write request is issued, and returns to step S10 if no write request is issued. An example of step S300 is shown in Figure 13.

[0102] In step S100, the relay control unit RCNT executes the state transition process shown in Figure 10 and returns to step S10. In step S200, the relay control unit RCNT executes the read process shown in Figure 11 and returns to step S10. In step S300, the relay control unit RCNT executes the write process and returns to step S10.

[0103] Figure 10 shows an example of step S100 (state transition processing) in Figure 9. First, in step S102, the relay control unit RCNT determines whether the address signal A received along with the state transition command points to its own memory group MG. In the example in Figure 1, the own memory group MG is the own memory group MG of the memory group control unit MCNT, and is the memory group MG that is accessed and on which a write or read operation is performed. If the address signal A points to its own memory group MG, the relay control unit RCNT executes step S104; if the address signal A does not point to its own memory group MG, it executes step S116.

[0104] In step S104, if the state transition command is an active command or a sleep wake command, the relay control unit RCNT executes step S106. If the state transition command is not an active command or a sleep wake command, the relay control unit RCNT executes step S108.

[0105] In step S106, the relay control unit RCNT outputs a low-level sleep signal SLP and a low-level shutdown signal SD to the memory unit row MUC, which is the target of activation indicated by address signal A. As a result, the memory unit row MUC transitions to active mode ACT. After step S106, step S114 is executed.

[0106] In step S108, the relay control unit RCNT executes step S110 if the state transition command is a sleep command, and executes step S112 if the state transition command is not a sleep command.

[0107] In step S110, the relay control unit RCNT outputs a high-level (H) sleep signal SLP and a low-level shutdown signal SD to the memory unit row MUC, which is the active target (the target to be transitioned to active mode ACT) indicated by address signal A. As a result, the active target memory unit row MUC transitions to sleep mode SLP. After step S110, step S114 is executed.

[0108] In step S112, the relay control unit RCNT outputs a low-level sleep signal SLP and a high-level shutdown signal SD to the memory unit row MUC that is the target of the active operation, indicated by address signal A. As a result, the memory unit row MUC transitions to shutdown mode SD. After step S112, step S114 is executed.

[0109] In step S114, the relay control unit RCNT suppresses the transfer of the control signal CMD and the address signal A to the memory group control unit MCNT by setting the mask circuit MSKC to the masked state, and terminates the process shown in Figure 10. On the other hand, in step S116, the relay control unit RCNT allows the transfer of the control signal CMD and the address signal A to the memory group control unit MCNT by setting the mask circuit MSKC to the unmasked state, and terminates the process shown in Figure 10.

[0110] Figure 11 shows an example of step S200 (read operation) in Figure 9. First, in step S202, the relay control unit RCNT determines whether the address signal A received along with the read request signal indicates its own memory group MG. If the address signal A indicates its own memory group MG, the relay control unit RCNT executes step S204; if the address signal A does not indicate its own memory group MG, it executes step S210.

[0111] In step S204, the relay control unit RCNT outputs a low-level chip enable signal CEB to the memory unit row MUC to be read, indicated by address signal A. The relay control unit RCNT outputs a high-level chip enable signal CEB to the memory unit row MUC that is not to be read.

[0112] Next, in step S206, the relay control unit RCNT outputs a high-level write enable signal WEB and a high-level bit write enable signal BWEB to its own memory group MG. The relay control unit RCNT outputs the received address signal A along with the control signal CMD to its own memory group MG.

[0113] Next, in step S208, the target relay control unit RCNT corresponding to the memory group MG to be read outputs a high-level read-enable signal RDEN. The target relay control unit RCNT causes the selector SELCQ to select an invalid memory read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELCQ to select an invalid memory read data signal Q from the preceding memory group MG. After step S208, step S220 is executed.

[0114] In step S210, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory unit row MUC. The relay control unit RCNT also outputs a low-level address signal A to each memory unit row MUC. By not changing the logic level of the address signal A, power consumption can be reduced.

[0115] In step S212, the relay control unit RCNT determines whether the address signal A received along with the read request signal indicates the memory group MG on the preceding stage (the preceding stage or before the preceding stage). If the address signal A indicates the memory group MG on the preceding stage, the relay control unit RCNT executes step S214; if the address signal A does not indicate the memory group MG on the preceding stage, it executes step S216.

[0116] In step S214, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT also causes the selector SELC to select either the memory read data signal Q from the preceding memory group MG or the memory read data signal Q from the preceding memory group control unit MCNT. This allows the memory read data signal Q, read from either the memory unit column MUC of the preceding memory group MG, to be transferred to the subsequent stage. The relay control unit RCNT also receives the high-level read-enable signal RDEN output from the preceding memory group control unit MCNT via an OR circuit and transfers it to the subsequent memory group control circuit MCNT. After step S214, step S220 is executed.

[0117] In step S216, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT also causes the selector SELC to select an invalid memory read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select an invalid memory read data signal Q from the preceding memory group MG. After step S216, step S220 is executed.

[0118] In step S220, the relay control unit RCNT sets the mask state of the mask circuits MSKC and MSKR, and terminates the operation shown in Figure 11.

[0119] Figure 12 shows an example of step S220 in Figure 11. In step S222, the relay control unit RCNT sets the mask circuit MSKC to the unmasked state and permits the transfer of the control signal CMD and the subsequent memory group control unit MCNT to address signal A.

[0120] Next, in step S224, the relay control unit RCNT determines whether or not the preceding memory group MG will perform a read operation based on the address signal A received along with the read request signal. If the preceding memory group MG will perform a read operation, step S226 is executed. If the preceding memory group MG will not perform a read operation, step S228 is executed.

[0121] In step S226, the relay control unit RCNT sets the mask circuit MSKR to an unmasked state, enabling the transfer of the memory read data signal Q from the preceding memory group MG or the memory read data signal Q from the preceding memory group control unit MCNT to the subsequent stage. After step S226, step S230 is executed.

[0122] In step S228, the relay control unit RCNT sets the mask circuit MSKR to the mask state because the memory read data signal Q from the preceding memory group MG or the memory read data signal Q from the preceding memory group control unit MCNT is not transferred. Power consumption can be reduced by suppressing the transfer of the invalid memory read data signal Q. After step S228, step S230 is executed.

[0123] In step S230, the relay control unit RCNT sets the mask circuits MSKW1 and MSKW2 to the masked state and terminates the operation shown in Figure 12. Power consumption can be reduced by suppressing the transfer of invalid write data signals D and invalid memory write data signals D.

[0124] Figure 13 shows an example of step S300 (write operation) in Figure 9. First, in step S302, the relay control unit RCNT determines whether the address signal A received along with the write request signal indicates its own memory group MG. If the address signal A indicates its own memory group MG, the relay control unit RCNT executes step S304; if the address signal A does not indicate its own memory group MG, it executes step S312.

[0125] In step S304, the relay control unit RCNT outputs a low-level chip enable signal CEB and a low-level write enable signal WEB to the memory unit row MUC to be written, indicated by address signal A. The relay control unit RCNT outputs a high-level chip enable signal CEB and a high-level write enable signal WEB to the memory unit row MUC that is not to be written to.

[0126] Next, in step S306, the relay control unit RCNT outputs to its own memory group MG the bit write enable signal BWEB included in the control signal CMD and the address signal A received together with the control signal CMD.

[0127] Next, in step S308, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT causes the selector SELC to select an invalid memory read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELC to select an invalid memory read data signal Q from the preceding memory group MG.

[0128] Next, in step S310, the relay control unit RCNT sets mask circuits MSKC and MSKW1 to the masked state, sets mask circuit MSKW2 to the unmasked state, and terminates the operation shown in Figure 13. By setting mask circuit MSKC to the masked state, the transfer of control signal CMD and address signal A to the subsequent stage, which are unrelated to the write operation, is suppressed, thereby reducing power consumption. By setting mask circuit MSKW1 to the masked state, the transfer of memory write data signal D to the subsequent stage is suppressed, thereby reducing power consumption. By setting mask circuit MSK2 to the unmasked state, the memory write data signal D can be transferred to the memory unit row MUC that is to be written to.

[0129] In step S312, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory unit row MUC. The relay control unit RCNT also outputs a low-level address signal A to each memory unit row MUC. This reduces power consumption, similar to step S210 in Figure 11.

[0130] Next, in step S314, the relay control unit RCNT outputs a low-level read-enable signal RDEN. The relay control unit RCNT causes the selector SELCQ to select an invalid memory read data signal Q from the preceding memory group control unit MCNT. Alternatively, the relay control unit RCNT may cause the selector SELCQ to select an invalid memory read data signal Q from the preceding memory group MG.

[0131] Next, in step S316, the relay control unit RCNT sets the mask state or unmasked state of the mask circuits MSKC, MSKR, MSKW1, and MSKW2. First, the relay control unit RCNT sets the mask circuit MSCR to the mask state. Next, based on the address signal A received along with the write request signal, the relay control unit RCNT determines whether or not the preceding memory group MG will perform a write operation.

[0132] The relay control unit RCNT sets the mask circuits MSKC, MSKW1, and MSKW2 to the unmasked state when the preceding memory group MG performs a write operation. If the preceding memory group MG does not perform a write operation, the relay control unit RCNT sets the mask circuits MSKC and MSKW1 to the unmasked state and the mask circuit MSKW2 to the masked state. Then, the relay control unit RCNT terminates the operation shown in Figure 13. Power consumption can be reduced by setting the mask circuits MSKC and MSKW1 to the masked state when the access request signal and write data signal D are not transferred to the subsequent stage.

[0133] Figure 14 shows an example of the operation of transitioning the memory unit array MUC to active mode ACT in the memory circuit 100 of Figure 1. In Figure 14, only the signals used for the transition to active mode ACT are shown.

[0134] When the memory control unit 200 receives an access request signal (write request or read request) while in shutdown mode SD, it outputs a state transition request to transition the memory unit row MUC to active mode ACT from shutdown mode SD. Also, when the memory control unit 200 receives an access request signal while in sleep mode SLP, it outputs a state transition request to transition the memory unit row MUC to active mode ACT from sleep mode SLP.

[0135] Each memory group control unit (MCNT), following instructions from the memory control unit (200), outputs a low-level shutdown signal (SD) and a low-level sleep signal (SLP) to the corresponding memory unit column (MUC) within its own memory group if the request is for a memory state transition. In the example shown in Figure 14, the second memory unit column (MUC) of memory group MG20 is referred to as the target memory unit column (labeled as the active target MUC in the figure). The process until it becomes active will be explained in order below.

[0136] The memory control unit 200 outputs a state transition request to the first-stage memory group control units MCNT10 and MCNT11 to set the target memory unit sequence MUC to the active state. Based on the address signal A included in the state transition request, the memory group control units MCNT10 and MCNT11 determine that the memory unit sequence MUC included in their own memory groups MG10 and MG11 is not the target memory unit sequence MUC. Therefore, the memory group control units MCNT10 and MCNT11 forward the state transition request to the subsequent memory group control units MCNT20 and MCNT21.

[0137] The memory group control units MCNT20 and MCNT21 determine, based on the address signal A included in the state transition request, that the memory unit sequence MUC included in their own memory groups MG20 and MG21 is the target memory unit sequence MUC. Then, for each memory group MG20 and MG21, the memory group control units MCNT20 and MCNT21 output a low-level sleep signal SLP and a low-level shutdown signal SD to one of the target memory unit sequences MUCs. Since the memory group control units MCNT20 and MCNT21 have determined that the memory unit sequence MUC within their own memory groups MG20 and MG21 is the target memory unit sequence MUC, the subsequent memory group control units MCNT30, MCNT31, MCNT40, and MCNT41 do not forward the state transition request.

[0138] Figures 15 and 16 show an example of signal timing during the transition to active mode ACT in Figure 14. Figures 15 and 16 show the timing waveforms of various signals corresponding to the operation described in Figure 14. In Figures 15, 16, and the timing diagrams described later, the code (i) at the end of a signal indicates an input signal to the target circuit, and the code (o) at the end of a signal indicates an output signal from the target circuit. Hereafter, each signal may be described by its code rather than its signal name. The signal names shown in the waveforms of the timing diagrams from Figure 15 onward may differ from the signal names described above. For example, the code ID indicates a command signal, the code ADR indicates an address signal A, and the code ETC indicates other control signals. The codes AWID(i), AWetc(i), and AWVLD(i) indicate the request signal REQ from the system bus SBUS. The code AWA(i) indicates the address signal ADR from the system bus SBUS. The code AWRDY(o) indicates an acknowledgment signal to the system bus SBUS.

[0139] The system bus input control unit 202 in Figure 2 detects from the system bus SBUS that valid AWID, AWA, and AWetc signals, which are examples of the request signal REQ and address signal ADR, are supplied from the system bus SBUS, based on a high-level AWVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS. The AWID signal contains information that identifies a state transition request, the AWA signal indicates the address to be used in the state transition request, and the AWetc signal indicates additional information to be used in the state transition request.

[0140] The system bus input control unit 202 stores (pushes) the CAWD signal (data), which includes the control signal CMD containing additional information and the 512-bit address A, which is the memory access unit, into the buffer 204. This CAWD signal is converted from the AWID, AWA, and AWetc signals received during the high-level period of the AWVLD signal. After confirming that there is space in the buffer 204 based on the low-level CAFULL signal, the system bus input control unit 202 outputs a high-level AWRDY signal (acknowledgment signal) to the system bus SBUS to indicate that the state transition request has been accepted. The CAFULL signal is set to high when there is no space in the buffer 204. The CAPUSH signal indicates the timing of storage into the buffer 204.

[0141] The input interface control unit 214 checks the information held in the buffer 204 and detects the memory unit sequence MUC that is the target of the state transition based on the address information. The input interface control unit 214 receives the state of the memory unit sequence MUC that is the target of the state transition as an MST signal from the memory state management unit 212.

[0142] For example, suppose the MST signal is in the shutdown state (SD) or sleep state (SLP). In this case, the input interface control unit 214 outputs an instruction to change to the active state and information indicating the memory unit row MUC to be activated to the first-stage memory group control units MCNT10 and CNT11. The instruction to change to the active state and the information indicating the memory unit row MUC to be activated are output to the memory group control units MCNT10 and CNT11 as CAWD signals in synchronization with the high level of the CAEN signal.

[0143] The instruction to change to the active state is also output to the memory state management unit 212. In the clock cycle following the receipt of the instruction to change to the active state, the memory state management unit 212 changes the MST signal from the shutdown state SD to the transition state TOACT for the active mode ACT. Furthermore, after the elapsed time T1, the memory state management unit 212 sets the MST signal to the active state ACT.

[0144] In Figure 16, the symbol (A) indicates the timing of the symbol (A) in Figure 15. There is a physical distance between the output of the input interface control unit 214 and the inputs of the memory group control units MCNT10 and MCNT11. Therefore, the signal output from the input interface control unit 214 reaches the memory group control units MCNT10 and MCNT11 after time Td. In this example, the memory unit sequence MUC, which is the target of the state transition, is included in the memory group MG downstream of the memory group control units MCNT20 and MCNT21, and is controlled by the memory group control units MCNT20 and MCNT21. Therefore, the memory group control units MCNT10 and MCNT11 forward the CAWD signal, which indicates a change instruction to the active state, to the memory group control units MCNT20 and MCNT21 one clock cycle after receiving the CAWD signal.

[0145] The memory group control units MCNT20 and MCNT21 detect whether a memory unit row MUC within their own memory group MG is the target of activation, based on the address contained in the received CAWD signal. Then, the memory group control units MCNT20 and MCNT21 set the SD terminal of the target memory unit row MUC from high level to low level, transitioning it to the active state. Since the memory group control units MCNT20 and MCNT21 have detected the target memory unit row MUC, they mask the output of the CAWD(o) and CAEN(o) signals to the subsequent memory group control units MCNT30 and MCNT31, and do not transfer them.

[0146] Figure 17 shows an example of the write operation of the memory circuit 100 in Figure 1. Detailed explanations of operations similar to those in Figure 14 are omitted. Figure 17 describes the operation when data is written to the memory unit row MUC targeted for writing within memory groups MG20 and MG21.

[0147] When the memory control unit 200 receives a write request signal, it sequentially stores 512 bits (up to eight 64-bit write data signals WD) and a 1-bit LAST signal (described later; the explanation of the LAST signal will be omitted unless otherwise specified) in the buffer 206 shown in Figure 2, as explained in Figure 2. If the memory unit row MUC containing the memory cell to be written is in a shut-down state, the memory control unit 200 transitions the target memory unit row MUC to an active state, as shown in Figure 14, and then performs the operation shown in Figure 17.

[0148] The memory control unit 200 outputs, for example, a 512-bit memory write data signal D along with a control signal CMD and an address signal A to the first-stage memory group control units MCNT10 and MCNT11. Based on the received address signal A, the memory group control units MCNT10 and MCNT11 determine that their own memory groups MG10 and MG11 are not the target of the write operation. Therefore, the memory group control units MCNT10 and MCNT11 forward the control signal CMD, address signal A, and memory write data signal D to the subsequent memory group control units MCNT20 and MCNT21.

[0149] The memory group control units MCNT20 and MCNT21 determine, based on the received address signal A, that their respective memory groups MG20 and MG21 are the target of the write operation. Then, MCNT20 and MCNT21 output a 64-bit memory write data signal D to each of the target memory units MU. Additionally, MCNT20 and MCNT21 output a control signal CMD and address signal A to each of the target memory units MU. Finally, the write data is written to the target memory cell.

[0150] As shown in Figure 17, each memory group control unit MCNT20 and MCNT21 masks the transfer of the control signal CMD, address signal A, and memory write data signal D to the subsequent memory group control units MCNT30 and MCNT31 because the address signal received along with the write request signal indicates its own memory group MG. Each memory group control unit MCNT transfers the write request signal and address signal to the subsequent memory group control unit MCNT if the address signal received along with the write request signal indicates a memory group other than its own memory group MG. This makes it possible to suppress the charging and discharging currents of the command line CMD, address line A, and write data line D compared to, for example, supplying the control signal CMD, address signal A, and memory write data signal D in common to each memory group MG. As a result, it is possible to suppress the increase in power consumption while further suppressing the increase in access time of the memory circuit 100.

[0151] Figures 18 and 19 show an example of signal timing during the write operation in Figure 17. Detailed explanations of operations similar to those in Figures 15 and 16 are omitted. Figures 18 and 19 show the timing waveforms of various signals corresponding to the write operation described in Figure 17.

[0152] The system bus input control unit 202 in Figure 2 detects that a valid WDATA signal (data), etc., is being supplied based on a high-level WVLD signal. The WDATA signal includes the data to be written to the memory cell by the write operation and the write address, etc.

[0153] The system bus input control unit 202 temporarily stores the DWATA signal received during the high-level period of the WVLD signal internally, and stores (pushes) up to eight sets of data, each containing 512 bits, into buffers 204 and 206. After confirming that buffers 204 and 206 are free based on the low-level WFULL signal, the system bus input control unit 202 outputs a high-level WRDY signal (acknowledgment signal) to the system bus SBUS to indicate that a write request has been accepted.

[0154] The WPUSH signal indicates the timing for storing data, such as write data, into buffers 204 and 206. In this embodiment, every eight 64-bit data packets received from the system bus SBUS, 512-bit data packets are stored together in buffer 206. At this time, the WLAST signal, indicating that the data from the system bus SBUS is the last, is stored in buffer 204. In the write data signal D, "not-last" indicates that it is not the last data, while "last" indicates that it is the last data.

[0155] When the input interface control unit 214 detects a write request from the information held in buffer 204, it reads the control signal CMD, address signal A, and memory write data signal D from buffers 204 and 206. The input interface control unit 214 determines whether it is the last memory write data signal D using last and not-last in WDRD. In this example, it is shown that the 512-bit memory write data signal D is obtained twice from buffer 206.

[0156] The input interface control unit 214 generates CAWD, CAEN, D, and WDEN signals based on the control signal CMD, address signal A, and memory write data signal D read from buffers 204 and 206, and outputs them to the first-stage memory group control units MCNT10 and MCNT11.

[0157] In Figure 19, the symbol (B) indicates the timing of the symbol (B) in Figure 18. The memory group control units MCNT10 and MCNT11 receive the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory group control units MCNT10 and MCNT11 determine that their own memory group MG is not a target for write access. Therefore, the memory group control units MCNT10 and MCNT11 forward the signal received from the input interface control unit 214 to the subsequent memory group control units MCNT20 and MCNT21.

[0158] The memory group control units MCNT20 and MCNT21 detect that the memory unit column MUC within their own memory group MG is the target of a write operation based on the received control signal CMD and address signal A. Then, the memory group control units MCNT20 and MCNT21 set the CEB and WEB terminals of the memory unit column MUC to be written to a low level. In addition, the memory group control units MCNT20 and MCNT21 output address A and the bit write enable signal BWEB to the A and BWEB terminals of the memory unit column MUC to be written. As a result, data is written to the memory cell of the memory unit column MUC. Since the address signal A received along with the write request signal indicates their own memory group MG, the memory group control units MCNT20 and MCNT21 mask the transfer of signals CAWD(o), CAEN(o), D(o), and WDEN(o) to the subsequent memory group control units MCNT30 and MCNT31.

[0159] Figure 20 shows an example of the read operation of the memory circuit 100 in Figure 1. Detailed explanations of operations similar to those in Figures 14 and 17 are omitted. Figure 20 describes the operation when data is read from the memory unit row MUC within memory groups MG20 and MG21.

[0160] When the memory control unit 200 receives a read request, it operates in the same manner as when it receives a write request, except that it does not receive the memory write data signal D. Furthermore, if the memory unit row MUC containing the memory cell to be read is in a shut-down state, the memory control unit 200 transitions the target memory unit row MUC (labeled as the active target MUC in the figure) to an active state, as shown in Figure 14, and then performs the operation shown in Figure 20.

[0161] The memory control unit 200 (output side) outputs the control signal CMD and address signal A to the first-stage memory group control units MCNT10 and MCNT11. Based on the received address signal A, the memory group control units MCNT10 and MCNT11 determine that their own memory groups MG10 and MG11 are not the target of reading. Therefore, the memory group control units MCNT10 and MCNT11 forward the control signal CMD and address signal A to the subsequent memory group control units MCNT20 and MCNT21.

[0162] The memory group control units MCNT20 and MCNT21 determine, based on the received address signal A, that their respective memory groups MG20 and MG21 are the target of reading. Then, the memory group control units MCNT20 and MCNT21 output a control signal CMD and address signal A to each of the memory units MU that are to be read. A memory read data signal Q is then read from the memory cell to be read and output to the subsequent memory group control units MCNT30 and MCNT31.

[0163] The memory group control units MCNT30 and MCNT31 forward the received control signal CMD, address signal A, and memory read data signal Q to the subsequent memory group control units MCNT40 and MCNT41. The memory group control units MCNT40 and MCNT41 forward the received control signal CMD, address signal A, and memory read data signal Q to the subsequent memory group control units MCNT50 and MCNT51. Based on the received control signal CMD and address signal A, the memory group control units MCNT50 and MCNT51 output the received memory read data signal Q to the memory control unit 200 (output side). The memory control unit 200 outputs the received 512-bit memory read data signal Q in multiple parts as a series read data signal DT (for example, 64 bits).

[0164] During a read operation, the memory block MBLK can receive an access request signal from the memory control unit 200 (input side) and output a memory read data signal Q to the memory control unit 200 (output side). This makes it possible to keep the sum of the length of the signal line that transfers the access request signal from the memory control unit 200 to the memory group MG to be read, and the length of the signal line that transfers the memory read data signal Q to the memory control unit 200, approximately constant regardless of the access position. As a result, it is possible to suppress fluctuations in the read access time depending on the position of the memory group MG in which the read operation is performed.

[0165] Each memory group control unit (MCNT) outputs a read request signal to its own memory group MG if the address signal A included in the read request signal indicates its own memory group MG. If the address signal included in the read request signal indicates a memory group other than its own memory group MG, each memory group control unit (MCNT) forwards the read request signal to the next memory group control unit (MCNT).

[0166] Figures 21 to 24 show an example of signal timing during the read operation in Figure 20. Detailed explanations of operations similar to those in Figures 15, 16, 18, and 19 are omitted. Figures 21 and 24 show the timing waveforms of various signals corresponding to the read operation described in Figure 20. The codes ARID(i), ARetc(i), and ARVLD(i) indicate the request signal REQ from the system bus SBUS. The code ARAD(i) indicates the address signal ADR from the system bus SBUS. The code ARRDY(o) indicates the acknowledgment signal to the system bus SBUS.

[0167] In Figure 21, the system bus input control unit 202 in Figure 2 stores (pushes) the CAWD signal (data), which includes the control signal CMD containing additional information and address A, which represents the 512-bit access unit of the memory area, into buffer 204. This CAWD signal is converted from the ARID signal (command), ARAD signal (address), and ARetc signal (other signals), which are examples of the request signal REQ and address signal ADR received from the system bus SBUS, during the high-level period of the ARVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS. After confirming that buffer 204 is free based on the low-level CAFULL signal input from the system bus SBUS, the system bus input control unit 202 outputs a high-level ARRDY signal (acknowledgment signal) to the system bus SBUS to indicate that a read request has been received. The CAPUSH signal indicates the timing of storing the read request signal and other data included in the read request into buffer 204.

[0168] When the input interface control unit 214 detects a read request from the information held in the buffer 204, it reads the control signal CMD and address signal A, etc., from the buffer 204. Based on the control signal CMD and address signal A, etc., read from the buffer 204, the input interface control unit 214 outputs the information to be used for read access to the first-stage memory group control units MCNT10 and MCNT11. For example, the signals output for use in read access are the CAWD signal, CAEN signal, and WDEN signal. Note that the write data line D is not used in read operations.

[0169] If the burst length (the number of outputs of the read data signal RDT for a single read request) is large, a read request may not be completed in a single access to the memory unit column MUC. In this case, the input interface control unit 214 generates a second or subsequent read request. "not-last" in CAWD indicates that the read request is not the last, while "last" indicates that it is the last.

[0170] In Figure 22, the symbol (A) indicates the timing of the symbol (A) in Figure 218. The memory group control units MCNT10 and MCNT11 receive the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory group control units MCNT10 and MCNT11 determine that their own memory group MG is not a target for read access. Therefore, the memory group control units MCNT10 and MCNT11 forward the signal received from the input interface control unit 214 to the subsequent memory group control units MCNT20 and MCNT21.

[0171] The memory group control units MCNT20 and MCNT21 detect that a memory unit column MUC within their own memory group MG is the target of reading, based on the received control signal CMD and address signal A. Then, the memory group control units MCNT20 and MCNT21 set the CEB terminal of the target memory unit column MUC to a low level and the WEB terminal to a high level. In addition, the memory group control units MCNT20 and MCNT21 output address A to the A terminal of the target memory unit column MUC. As a result, data is read from the memory cells of the target memory unit column MUC.

[0172] The memory group control units MCNT20 and MCNT21 generate a read data enable signal IRDEN (Figure 7) to transfer the memory read data signal Q to the subsequent memory group control unit MCNT. The read data enable signal IRDEN is output to the memory group control units MCNT30 and MCNT31 as a read data enable signal RDEN.

[0173] Furthermore, during the read operation, the memory read data signal Q read from the memory unit row MUC is converted from series to parallel by the system bus output control unit 226 and output to the system bus SBUS as the read data signal RDT. For this reason, the memory group control units MCNT20 and MCNT21 output the received control signal CMD and address signal A, along with the memory read data signal Q, to the memory group control units MCNT30 and MCNT31.

[0174] In Figure 23, the symbols (B), (C), and (D) indicate the timing of the symbols (B), (C), and (D) in Figure 18. The memory group control units MCNT30 and MCNT31 receive the signals output from the memory group control units MCNT20 and MCNT21 after time Td. The memory group control units MCNT30 and MCNT31 forward the received control signal CMD, address signal A, and memory read data signal Q to the memory group control units MCNT40 and MCNT41. The memory group control units MCNT40 and MCNT41 forward the received control signal CMD, address signal A, and memory read data signal Q to the memory group control units MCNT50 and MCNT51. The memory group control units MCNT50 and MCNT51 output the received control signal CMD, address signal A, and memory read data signal Q to the memory control unit 200.

[0175] In Figure 24, the symbols (E) and (F) indicate the timing of the symbols (E) and (F) in Figure 18. The output interface control unit 220 of the memory control unit 200 stores (pushes) the received control signal CMD and address signal A into buffer 222, and stores (pushes) the received memory read data signal Q into buffer 224. The system bus output control unit 226 of the memory control unit 200 refers to the CRAVLD signal output from buffer 222 and the RDVLD signal output from buffer 224, and waits for buffers 222 and 224 to become readable (valid). When buffers 222 and 224 become readable and the system bus SBUS is in a ready state (RRDY=H), the system bus output control unit 226 generates the RID signal and RDATA signal to output to the system bus SBUS. The RID and RDATA signals use the control signal CMD and address signal A held in buffer 222, and the memory read data signal Q held in buffer 224, to generate read data RDATE (an example of the read data signal RDT) and additional information RID and RLAST for the system bus side. The system bus output control unit 226 also sets the RVLD signal, which indicates that the output signal to the system bus SBUS is valid, to the valid level (RVLD=H). While the read data from the memory block MBLK is in 512-bit units, the read data from the system bus SBUS side is in 64-bit units. Therefore, the read data is output to the system bus SBUS in up to 8 parts. When the CRAPOP and RDPOP signals are set to the valid level (H), the following commands, addresses, and data are output to buffers 222 and 224.

[0176] In the example shown in Figure 24, the system bus output control unit 226 sequentially selects the 512-bit memory read data signals Q read from the memory block MBLK to match the 64-bit data bus width on the system bus SBUS side. The first 64 bits of data Q1.1 to Q1.8 are output to the system bus SBUS in 8 clock cycles. Furthermore, the next 512 bits of memory read data signals Q from the memory block MBLK, from data Q2.1 to Q2.8, are also output to the system bus SBUS in 8 clock cycles. Finally, when the last memory read data signal Q, data Q2.8, is output, the system bus output control unit 226 outputs RLAST at an active level (e.g., high level) to complete the read operation.

[0177] Figures 25 to 28 show another example of signal timing during a read operation of the memory circuit 100 in Figure 1. Figures 25 to 28 show an example in which a read request is issued for one of the memory unit columns MUCs of memory groups MG40 and MG50, followed by a read request being issued for one of the memory unit columns MUCs of memory groups MG10 and MG20.

[0178] The operation of each circuit element in Figures 25 to 28 is the same as that of each circuit element shown in Figures 21 to 24, except that two read requests are issued sequentially. In other words, the operation for each read request in Figures 25 to 28 is the same as that shown in Figures 21 to 24.

[0179] In this embodiment, the access request signal, memory write data signal D, and memory read data signal Q can be pipelined between the memory group control unit MCNT. Therefore, for example, other read requests can be sequentially supplied to the memory block BLK before the memory read data signal Q responding to one read request is output from the memory block MBLK. As a result, as shown in Figures 25 to 28, read access to memory groups MG10 and MG20 can be performed in the clock cycle following read access to memory groups MG40 and MG50.

[0180] Figure 29 shows an example of a redundant circuit mounted on the memory circuit 100 in Figure 1. In Figure 29, for the sake of clarity, the memory groups MG11, MG21, MG31, MG41 and the memory group control units MCNT11, MCNT21, MCNT31, MCNT41, MCNT51 are omitted. The redundant circuits corresponding to memory groups MG11-MG41 are the same as the redundant circuits corresponding to memory groups MG10-MG40.

[0181] Semiconductor memories such as SRAM typically have redundant memory cells that operate in place of defective memory cells, in addition to the memory cells required for the necessary capacity, in order to improve the yield rate (the percentage of good products). If a defective memory cell is detected during operational testing in the semiconductor memory manufacturing process, the defective memory cell is replaced with a redundant memory cell, for example, by using a redundant memory cell instead. The replacement unit of word lines may be one line or four lines.

[0182] In this embodiment, as shown in Figure 29, in the memory group MG40, a predetermined number of normal word lines in the memory unit row MUC adjacent to the memory control unit 200 are used as redundant word lines. Although four redundant word lines are shown in Figure 29, the number of redundant word lines is not limited to four. For example, when the memory circuit 100 is used as a frame memory for image processing, the amount of memory used is determined by the image size, so the entire storage capacity of the memory block MBLK is not used.

[0183] For example, a redundant word line is assigned to a memory unit row MUC adjacent to the memory control unit 200 (input or output side) in at least one of memory groups MG40 and MG10, and is common to all memory groups MG10-MG40. If we consider each memory unit MU in Figure 29 as one memory, then the circuit size of the redundant circuit can be reduced compared to the case where a redundant memory cell is provided for each of the 64 memory units MU.

[0184] Failure information, such as the address indicating a faulty memory cell (or faulty word) detected during the operation test of the memory circuit 100, and the redundant address indicating the redundant word line to be replaced, is stored in a non-volatile memory such as an e-Fuse provided in the memory circuit 100. Furthermore, the memory circuit 100 may perform a self-test at startup to detect faulty memory cells and store the failure information, such as the faulty address indicating the detected faulty memory cell, in volatile memory or non-volatile memory. In the case of volatile memory, a self-test at startup is required each time the power is turned on, but if the information is stored in non-volatile memory, a self-test at startup is not required from the second power-on onwards.

[0185] The memory control unit 200 reads fault information from the non-volatile memory when the memory circuit 100 is started and stores it in the registers of the memory state management unit 212. The input interface control unit 214 refers to the memory state management unit 212 when a memory block MBLK is accessed and determines whether the access address is a faulty address. If the access address is a faulty address, the input interface control unit 214 outputs a redundant address to the memory group control unit MCNT10 (MCNT11) in place of the faulty address.

[0186] The memory circuit 100 may also have redundant memory cells for each memory group MG, memory unit MU, or memory MEM.

[0187] Figure 30 shows an example of a system 300 in which the memory circuit 100 of Figure 1 is installed. For example, system 300 may be a head-mounted device such as AR / VR glasses capable of processing moving images, a digital camera, or a game console. System 300 may also be an image processing system installed in a vehicle. Furthermore, the system in which the memory circuit 100 is installed is not limited to the configuration of system 300.

[0188] The system 300 includes a controller 310, an imaging device 320, a display device 330, and an external memory 340. The controller 310 includes a CPU 311, an image processing unit 312, a display processing unit 313, an encoder / decoder 314, an external memory control unit 315, and the memory circuit 100 shown in Figure 1, all interconnected via a system bus SBUS. For example, the controller 310 may be designed as a system LSI.

[0189] The CPU 311 controls the entire system 300. The image processing unit 312 processes the image data acquired by the imaging device 320, converts the processed image data into frame image data that can be displayed on the display device 330, and stores the frame image data in the memory circuit 100. The display processing unit 313 reads the frame image data from the memory circuit 100 and displays the image on the display device 330. The encoder / decoder 314 encodes the image data before it is stored in the memory circuit 100 and decodes the compressed image data read from the memory circuit 100. The external memory control unit 315 controls access to external memory 340 such as DRAM (Dynamic Random Access Memory).

[0190] For example, the resolution of the video images handled by system 300 may be VGA (Video Graphics Array), Full HD, or 4K. The memory circuit 100 of system 300 is equipped with a number of memory groups MG (not shown) corresponding to the resolution of the video images. As described above, even if the number of memory groups MG increases or decreases, the clock cycle required for signal transfer between memory group control units MCNT remains unchanged, making timing design easier and suppressing increases in access time.

[0191] Figure 31 shows an example of another memory circuit 400. Detailed explanations of elements similar to those in Figures 1 to 3 are omitted. The memory circuit 400 has a memory block MBLKa containing multiple memory groups MGa and a memory control unit 200a. Unlike the memory block MBLK in Figure 3, the memory block MBLKa does not have a memory group control unit MCNT. Furthermore, when accessing memory, each memory group MGa selects one of the four memory units MU arranged in an orthogonal direction to the arrangement direction of memory groups MGa10, MGa20, MGa30, and MGa40, and inputs / outputs 64 bits of data.

[0192] The memory control unit 200a accesses memory group MGa in 64-bit units in response to access request signals (write request signals or read request signals) received via the system bus SBUS. Furthermore, the memory control unit 200a is positioned adjacent to memory groups MGa10 and MGa11. Therefore, for example, read data from memory group MGa40 is transmitted to the memory control unit 200 via memory groups MGa30, MGa20, and MGa10.

[0193] Furthermore, the memory circuit 400 does not have memory group control units MCNT between memory groups MGa. Therefore, the memory control unit 200a outputs the memory write data signal D to a write data line that is common to memory groups MGa10, MGa20, MGa30, and MGa40. The memory control unit 200a receives the memory read data signal Q from, for example, a read data line that is common to memory groups MGa10, MGa20, MGa30, and MGa40. The memory block MBLKa has a selector SEL to avoid collisions of the memory read data signals Q output from each memory group MGa.

[0194] Figure 32 shows an example of the configuration of memory group MGa in Figure 31. Like memory group MG shown in Figure 4, memory group MGa has 16 memory units MU. Memory group MGa transmits the 64-bit memory read data signal Q output from each memory unit MU to the read data terminal Q of memory group MGa via four selectors SEL. Memory group MGa also supplies a common memory write data signal D, received at the 64-bit write data terminal D, to each memory unit MU. The 64 chip enable signals CEB received by memory group MG are supplied to the memory units MU in groups of four and are used for selecting the memory units MU and the memory array MEMC within each memory unit MU.

[0195] Figure 33 shows an example of the read operation of the memory circuit 400 in Figure 31. In the example in Figure 33, the memory control unit 200a receives a read request for the memory unit MU of the memory group MGa10 that is close to the memory control unit 200a.

[0196] The memory control unit 200a outputs the control signal CMD and the address signal A to all memory group MGs. Since the command line CMD and address line A are wired in common to all memory group MGs, the load capacitance and propagation delay time are larger compared to when a memory group control unit MCNT is provided.

[0197] The memory control unit 200a receives a 64-bit memory read data signal Q read from the memory unit MU that is the target of the read access via the selector SEL and outputs it to the system bus SBUS. In this way, the memory circuit 400 performs a 64-bit read operation on the memory block MBLKa for each read request supplied via the system bus SBUS.

[0198] Therefore, the memory circuit 400 has a lower read rate for the memory read data signal Q compared to the memory circuit 100 in Figure 1, which performs a 512-bit read operation for each read request. Furthermore, the memory circuit 400 accesses the memory block MBLKa at the same frequency as the read request signals supplied via the system bus SBUS. Consequently, the timing design for the read control of the memory circuit 400 is more difficult than that of the memory circuit 100.

[0199] Furthermore, in the case of write requests, similar to read requests, the write rate of the memory write data signal D decreases compared to the memory circuit 100 in Figure 1, and the timing design of the write control for the memory circuit 400 becomes more difficult than the timing design for the memory circuit 100.

[0200] Figure 34 shows another example of the read operation of the memory circuit 400 in Figure 31. A detailed explanation of the operation similar to that in Figure 33 is omitted. In the example in Figure 34, the memory control unit 200a receives a read request for the memory unit MU of the memory group MGa40, which is far from the memory control unit 200a.

[0201] The memory control unit 200a receives the 64-bit memory read data signal Q read from the memory unit MU of the memory group MGa40 that is the target of read access, sequentially via multiple selectors SEL, and outputs it to the system bus SBUS. Since the read data line Q is wired in common to all memory groups MG, it has a heavy load and a large propagation delay time.

[0202] Furthermore, during read access to memory group MGa40, which is far from the memory control unit 200a, the control signal CMD, address signal A, and memory read data signal Q are transmitted across the four memory groups MG. The timing design of the memory circuit 400 is based on the worst-case scenario. Therefore, the timing specifications for read access of the memory circuit 400 are determined by the access timing of memory group MGa40.

[0203] In this embodiment, a memory group control unit MCNT is provided for each of the multiple memory groups MG. Each memory group control unit MCNT outputs an access request signal to its own memory group MG if the access request signal indicates its own memory group MG. Each memory group control unit MCNT forwards an access request signal to a subsequent memory group control unit MCNT if the access request signal indicates a memory group other than its own memory group MG. As a result, each memory group control unit MCNT can control access for each memory group MG. Since the command line CMD and address line A are not wired across multiple memory groups MG, the increase in wiring load can be suppressed. As a result, the increase in power consumption can be suppressed while suppressing the increase in access time of the memory circuit 100.

[0204] In a write operation, the control signal CMD, address signal A, and memory write data signal D are not forwarded beyond the memory group control unit MCNT corresponding to the memory group MG being written to. In a read operation, the control signal CMD and address signal A are supplied to the memory group MG being read from, but not to the memory group MG that is not being read from. This allows for the suppression of the charge and discharge currents of the command line CMD, address line A, and write data line D compared to, for example, the case where the control signal CMD, address signal A, and memory write data signal D are supplied commonly to each memory group MG. As a result, the increase in power consumption can be further suppressed while further suppressing the increase in access time of the memory circuit 100.

[0205] The memory group control unit MCNT has a selector SELQ that selects a memory read data signal Q from the preceding memory group MG or a memory read data signal Q from the preceding memory group control unit MCNT and transfers it to the subsequent memory group control unit MCNT. This allows the memory read data signal Q to be transferred to the memory control unit 200 regardless of the position of the memory group MG that outputs the memory read data signal Q.

[0206] The memory circuit 100 has memory group control units MCNT and memory group MG alternately arranged between the memory control unit 200 (input side) and the memory control unit 200 (output side). In a read operation, the memory block MBLK can receive an access request signal from the memory control unit 200 (input side) and output a memory read data signal Q to the memory control unit 200 (output side). This makes it possible to keep the sum of the length of the signal line that transfers the access request signal from the memory control unit 200 to the memory group MG to be read, and the length of the signal line that transfers the memory read data signal Q to the memory control unit 200, approximately constant regardless of the access position. As a result, it is possible to suppress fluctuations in the read access time depending on the position of the memory group MG performing the read operation.

[0207] The memory control unit 200 combines multiple write data signals WD received from the system bus SBUS into a single memory write data signal D, and instructs the memory group MG to execute the write operation of the memory write data signal D. The memory control unit 200 also converts the memory read data signal Q read from the memory group MG into multiple read data signals RDT and outputs them to the system bus SBUS. This allows the operating frequency of the memory block MBLK to be lower than the operating frequency of the system bus SBUS, thereby reducing the power consumption of the memory block MBLK. Because the operating frequency of the memory block MBLK can be lowered, there is more operating margin for the memory group control unit MCNT and the memory group MG, facilitating circuit timing design and other configurations.

[0208] Each memory group control unit (MCNT) sets the memory unit row MUC that will perform write or read operations to active mode (ACT), and sets the other memory unit row MUCs to shutdown mode (SD) or sleep mode (SLP). This reduces the power consumption of the memory circuit 100. Furthermore, each memory group control unit (MCNT) can further reduce the power consumption of the memory circuit 100 by switching the memory unit row MUC that will not perform write or read operations for a predetermined period from active mode (ACT) to sleep mode (SLP).

[0209] The number of clock cycles required for the transfer of the access request signal, memory write data signal D, and memory read data signal Q between the pair of memory group control units MCNT located on either side of the memory group MG is set to be the same for both. This makes timing design easier even when increasing or decreasing the number of memory groups MG and designing other memory circuits with different storage capacities.

[0210] The redundant word lines for recovering faulty memory cells are provided in common to multiple memory groups MG within a memory group MG that is close to at least one of the memory group control units MCNT10 and CNT50. This reduces the circuit size of the redundant circuit compared to providing a redundant word line for each memory group MG.

[0211] Although the present invention has been described above based on various embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be modified as long as they do not impair the spirit of the present invention, and can be appropriately determined according to their application. [Explanation of Symbols]

[0212] 100 memory circuits 200, 200a Memory Control Unit 202 System Bus Input Control Unit 204, 206 buffers 208 Peripheral Bus Control Unit 210 General Management Department 212 Memory State Management Unit 214 Input Interface Control Unit 220 Output Interface Control Unit 222, 224 buffers 226 System Bus Output Control Unit 300 Systems 310 Controller 311 CPU 312 Image Processing Unit 313 Display Processing Unit 314 Encoder / Decoder 315 External Memory Control Unit 320 Imaging device 330 Display device 340 external memory 400 memory circuits A, ADR address signal ACT Active Mode ATRNS Active Transition Mode BUF1, BUF2, BUF3 buffers CMD Control Signal CNTL control signal D: Memory write data signal MBLK, MBLKa memory block MCLK memory clock signal MCNT Memory Group Control Unit MEM memory MEMC memory column MG, MGa memory group MGC Memory Group Column MSKC, MSKR, MSKW1, MSKW2 Mask Circuits MU Memory Unit MUC memory unit row Q: Memory read data signal RCNT Relay Control Unit RDT readout data signal SBUS System Bus SCLK System Clock Signal SD Shutdown Mode SEL, SELQ selector SLP Sleep Mode WD write data signal

Claims

1. Multiple memory groups, each containing multiple memory cells, perform write or read operations in response to request signals, A plurality of memory group control units are provided corresponding to each of the plurality of memory groups, It includes a first memory control unit that outputs a request signal received from an external source to an adjacent memory group control unit, Each of the plurality of memory group control units outputs the request signal to the corresponding memory group if the address signal included in the received request signal indicates the corresponding memory group, and outputs the request signal to a subsequent memory group control unit if the address signal indicates a memory group other than the corresponding memory group. The memory group has at least one sub-memory group that can be set to either a low-power mode that suppresses power consumption while retaining data, or an active mode that enables write or read operations. The memory group control unit corresponding to the memory group sets the sub-memory group to which write or read operations are to be performed in active mode. Set a sub-memory group in which write or read operations are not performed for a predetermined period of time to the low-power mode. Memory circuit.

2. The first memory control unit outputs a write request signal along with a write data signal as the request signal. Each of the plurality of memory group control units outputs the write request signal and the write data signal to the corresponding memory group when the address signal indicates the corresponding memory group, and suppresses the output of the write request signal and the write data signal to subsequent memory group control units. The memory circuit according to claim 1.

3. The first memory control unit converts M N-bit write data signals received from an external source into N × M-bit write data signals and outputs them to the memory group control unit (where M is an integer greater than or equal to 2, and N is an integer greater than or equal to 1). The memory circuit according to claim 2.

4. The first memory control unit outputs a read request signal as the request signal, Each of the plurality of memory group control units outputs the read request signal to the corresponding memory group if the address signal indicates the corresponding memory group, and suppresses the output of the read request signal to the corresponding memory group if the address signal indicates a memory group other than the corresponding memory group. A memory circuit according to any one of claims 1 to 3.

5. The second and subsequent memory group control units of the plurality of memory group control units have a selector that selects a read data signal output from a memory group corresponding to the preceding memory group control unit or a read data signal transferred from the preceding memory group control unit, according to the address signal included in the read request signal. The memory circuit according to claim 4.

6. The memory group further includes a memory group control unit and a second memory control unit on the downstream side of the final stage memory group of the plurality of memory groups. The memory group control unit and the memory group are arranged alternately. The read data signal from any of the above-mentioned multiple memory groups is transferred from the final-stage memory group control unit to the second memory control unit, and then output to the outside from the second memory control unit. The memory circuit according to claim 4 or claim 5.

7. The second memory control unit converts the N × M bit read data signal received from the final stage memory group control unit into M N bit read data signals and outputs them to the outside (where M is an integer of 2 or more, and N is an integer of 1 or more). The memory circuit according to claim 6.

8. The number of clock cycles required for transferring request signals, write data signals, and read data signals between the pair of memory group control units located on either side of each of the plurality of memory groups is the same for all of them. A memory circuit according to any one of claims 1 to 7.

9. Each of the plurality of memory groups has a plurality of word lines connected to a predetermined number of memory cells, A redundant word line for recovering a faulty memory cell is assigned to at least one of the word lines in the memory group furthest from the first memory control unit and the memory group closest to the first memory control unit. A memory circuit according to any one of claims 1 to 8.

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