Low-capacity memory in a sensing amplifier

Abstract

A memory is provided that includes a number of memory banks, each associated with a read multiplexer. The first read multiplexer couples a first number of bit lines to a first sense node pair, and the second read multiplexer couples a second number of bit lines to a second sense node pair. The first sense amplifier is coupled to the first sense node pair. The second sense node pair can be coupled to the same sense amplifier or a different sense amplifier.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the priority and benefit of U.S. Patent Application No. 17 / 446,195, filed on August 27, 2021, the disclosure of which is hereby incorporated by reference in its entirety for all applicable purposes as if fully set forth herein below.

[0002] This application relates to memories, and more particularly, to low - capacitance multi - bank memories in sense amplifiers.

Background Art

[0003] In a conventional static random - access memory (SRAM), a bit cell is connected to a pair of bit lines during a read operation. Before the read operation, the bit lines are pre - charged to the power supply voltage used by the bit cell. Depending on the binary content of the bit cell, the bit cell slightly discharges either the true bit line or the complementary bit line in the bit line pair from its pre - charged state. For example, assume that the bit cell stores a binary 1. During the read operation, the word line is asserted so that the bit cell is coupled to its bit line pair. Due to the value of binary 1, the complementary bit line is discharged from its pre - charged state. However, the bit cell maintains the true bit line in its pre - charged state.

[0004] Thus, the read operation develops a voltage difference between the two ends of the bit line pair. This bit line voltage difference is not a full rail and is equal to a fraction of the power supply voltage. In response to this relatively small voltage difference, a sense amplifier can use a relatively large amount of gain to make a bit decision regarding what is stored in the bit cell.

[0005] A charge transfer sense amplifier (CTSA) can provide a relatively large amount of gain to enable bit determination with a relatively small voltage difference. A CTSA can partially provide gain by transferring charge between a bit line (or complementary bit line) and a sense node (or complementary sense node). However, several bit lines may share a sense node, and the more bit lines there are per sense node, the higher the parasitic capacitance can become, which can hinder fast and reliable bit determination.

[0006] Therefore, in this field, memory with reduced parasitic capacity is required. [Overview of the Initiative]

[0007] In one implementation, the circuit includes a first read multiplexer that connects a first plurality of bit lines to a first sensing node and a first complementary sensing node; a second read multiplexer that connects a second plurality of bit lines to a second sensing node and a second complementary sensing node; and a first sensing amplifier connected to the first sensing node and the first complementary sensing node, wherein the first read multiplexer is associated with a first bank of memory bit cells and the second read multiplexer is associated with a second bank of memory bit cells.

[0008] In another implementation, the method includes, in a first read operation, multiplexing a first plurality of bit line pairs with a first sensing node pair, which includes coupling a first bit line pair from the first plurality of bit line pairs with a first sensing node pair; sharing charge between the first bit line pairs and the first sensing node pair; inputting a value from the first sensing node pair to a logic circuit; causing the logic circuit to perform a bit determination based on the value from the first sensing node pair; and in a subsequent read operation, multiplexing a second plurality of bit line pairs with a second sensing node pair, which includes coupling a second bit line pair from the second plurality of bit line pairs with a second sensing node pair, wherein the first plurality of bit line pairs are associated with a first bank of memory bit cells and the second plurality of bit line pairs are associated with a second bank of memory bit cells.

[0009] In another implementation, the memory device includes multiple memory banks, each containing multiple bit line pairs; multiple sensing node pairs, each associated with one of the memory banks; means for multiplexing bit line pairs with sensing node pairs; and means for performing bit determination based on voltages associated with sensing node pairs during multiple read operations targeting multiple memory banks.

[0010] In yet another implementation, the memory includes a first memory bank containing a first plurality of bit cells arranged in a first plurality of columns, a second memory bank containing a second plurality of bit cells arranged in a second plurality of columns, a first pair of sensing nodes coupled to the first plurality of columns by a first read multiplexer, a second pair of sensing nodes coupled to the second plurality of columns by a second read multiplexer, and a first sensing amplifier coupled to the first pair of sensing nodes.

[0011] These and additional advantages can be better understood through the following embodiments for carrying out the invention. [Brief explanation of the drawing]

[0012] [Figure 1] One aspect of this disclosure shows a multibank memory having a plurality of sensing node pairs. [Figure 2] Figure 1 shows an exemplary sensing amplifier in the memory. [Figure 3] Figure 1 shows the timing diagram of an exemplary sensing amplifier. [Figure 4] Figure 1 shows an exemplary sensing amplifier in the memory. [Figure 5] One aspect of this disclosure shows a multibank memory having a plurality of sensing node pairs. [Figure 6] Figure 5 shows an exemplary sensing amplifier in the memory. [Figure 7] An exemplary interface between a bit line pair and a sensing node pair, according to one aspect of this disclosure, is shown. [Figure 8] Figures 1 and 5 show flowcharts illustrating exemplary methods that can be performed using multibank memory. [Figure 9] An exemplary system-on-a-chip (SOC) capable of incorporating memory is shown according to one aspect of this disclosure.

[0013] The implementations of this disclosure and their advantages are best understood by referring to the detailed description below. Please note that the same reference numbers are used to identify similar elements shown in one or more of the figures. [Modes for carrying out the invention]

[0014] A memory such as SRAM is provided, containing multiple memory banks, each associated with a read multiplexer. For example, a first read multiplexer may connect a first set of bit lines to a first sensing node and a first complementary sensing node. A second read multiplexer may connect a second set of bit lines to a second sensing node and a second complementary sensing node. The set of bit lines may include multiple bit line pairs (bit lines and bit line complements). Each bit line pair may correspond to a sequence of bit cells. Thus, each memory bank may contain multiple sequences of bit cells traversed by multiple word lines.

[0015] In contrast to other examples where multiple read multiplexers may be coupled to the same sensing node pair (sensing node and sensing node complement), the implementations discussed herein may include an architecture in which a first read multiplexer is coupled to a first sensing node and a first complementary sensing node, and a second read multiplexer is coupled to a second sensing node and a second complementary sensing node. As described above, as the number of bit lines sharing a sensing node and a complementary sensing node increases, so does the parasitic capacitance. However, the implementations discussed herein increase the number of sensing node pairs by providing at least one pair to each memory bank. Thus, the ratio of bit lines to sensing nodes is reduced, thereby reducing the parasitic capacitance observed by each sensing amplifier. Lower parasitic capacitance can increase the voltage achieved by charge sharing, thereby providing faster and more reliable bit decisions.

[0016] In one example, there is a first sensing amplifier coupled to a first sensing node and a first complementary sensing node, and a second sensing amplifier coupled to a second sensing node and a second complementary sensing node. In other words, each memory bank is associated with its own sensing amplifier. Sensing amplifiers can be implemented in any suitable way, including the fact that each sensing amplifier is constructed as a cross-coupled pair of NAND gates, and each cross-coupled pair is coupled to a push-pull circuit.

[0017] In another implementation, multiple memory banks are coupled to a single sensing amplifier. In other words, the sensing amplifier is coupled to both sensing node pairs and therefore to each of the multiplexers. The sensing amplifier may also include a cross-coupled pair of AND-OR-inverting (AOI) gates, where the first AOI gate is coupled to the output from the first complementary sensing node, the second complementary sensing node, and the second AOI gate, and the second AOI gate is coupled to the output from the first sensing node, the second sensing node, and the first AOI gate. The cross-coupled pair of AOI gates may share a push-pull circuit.

[0018] An advantage of implementations using cross-coupled AOI gates is that the number of transistors can be reduced compared to implementations using two cross-coupled pairs of NAND gates. Reducing the number of transistors can reduce the amount of silicon area used on the chip, which may reduce manufacturing costs and potentially save dynamic power and leakage power.

[0019] The sense amplifier can be implemented as a charge-sharing sense amplifier (CTSA). In one example, each bit line of a group of multiplexed columns is coupled to the sense node via its own charge transfer transistor. The source of each charge transfer transistor is coupled to its bit line, and the drain of each charge transfer transistor is coupled to its sense node. Thus, the gate-source voltage of each charge transfer transistor is determined by its gate voltage and its bit line voltage. In the following discussion, we assume that each charge transfer transistor is a p-type metal-oxide-semiconductor (PMOS) transistor, but it will be understood that charge transfer can also be achieved with n-type metal-oxide-semiconductor (NMOS) transistors.

[0020] Before the word line assertion for the read operation, the bit lines are pre-charged to the power supply voltage and the sense nodes are discharged. The word line is then asserted over a word line assertion period, during which a bit line voltage difference that depends on the bit stored in each bit cell at the intersection of the word line and the bit line pair of the multiplexed column group is developed for each bit line pair. Depending on this bit, either the true bit line or the complementary bit line in each bit line pair is slightly discharged from the pre-charged state (power supply voltage, VDD). Charge transfer occurs during a charge transfer period that begins near the end of the word line assertion period. Before the charge transfer period, the gate voltage of each charge transfer transistor is maintained at the power supply voltage so that each charge transfer transistor is off. The charge transfer period is delayed with respect to the assertion of the word line so that a bit line voltage difference can be developed for each bit line pair. During the charge transfer period, the gate voltage of the charge transfer transistor drops from the power supply voltage towards ground at some slew rate. For example, a relatively small inverter or a dummy bit line voltage can be used to control the gate voltage of the charge transfer transistor. Depending on the bit value, either the true bit line or the complementary bit line in each bit line pair drops slightly from its pre-charged state (power supply voltage). This bit line is referred to as the partially charged bit line in the following discussion. However, the remaining bit line of each bit line pair remains charged to the power supply voltage. This bit line is referred to as the fully charged bit line in the following discussion.

[0021] During the charge transfer period, the gate voltage of each charge transfer transistor within a group of multiplexed columns decreases such that the voltage between the gate and source of the charge transfer transistor of a fully charged bit line (the voltage between the gate and the bit line) meets its threshold voltage. However, the decrease in the voltage of a partially charged bit line is such that this same gate voltage does not meet the threshold voltage of the charge transfer transistor of the partially charged bit line. Thus, only the charge transfer transistor of the fully charged bit line in a bit line pair first conducts charge to its sense node. Since the capacitance of the sense node is relatively small compared to the capacitance of the bit line, the resulting charge transfer charges the sense node to approximately the supply voltage. In contrast, since the sense node for a partially discharged bit line remains in its discharged default state, the voltage difference between the sense nodes for the accessed bit line pair is approximately full rail (the voltage difference is approximately equal to the supply voltage). Thus, charge transfer amplifies a relatively small bit line voltage difference into an approximately full rail voltage difference on the sense node. Sensing by the sense amplifier occurs during the sense period.

[0022] FIG. 1 is a diagram of a memory system 100 according to one implementation. Memory system 100 is a multi-bank memory system and, in this case, uses two memory banks, namely bank b0 195 and bank b1 196. Each of memory banks 195, 196 includes a plurality of columns of bit cells, each column having a bit line and a complementary bit line, and each of the memory banks is traversed by a plurality of word lines. Bit lines and complementary bit lines 190, 191 are shown as each having two pairs, and it is understood that a given memory bank can include any suitable number of bit line pairs corresponding to any suitable number of columns.

[0023] Looking at multiplexer 110, it corresponds to bank b0 195 and multiplexes bit line pair 190 to sensing nodes q_b0 and qb_b0. Similarly, multiplexer 120 corresponds to bank b1 196 and multiplexes bit line pair 191 to sensing nodes q_b1 and qb_b1. In this example, each of multiplexers 110 and 120 receives three signals, including pre_n (bit line pre-charge), rm[0:3] (read multiplexing signal), and wm[0:3] (write multiplexing signal). Here, signals rm and wm are shown as being selected from four columns, and as mentioned above, note that the range of implementation forms supports any number of columns that can be multiplexed.

[0024] The sensing nodes (q_b0, q_b1) and complementary sensing nodes (qb_b0, qb_b1) are inputs to the sensing amplifier 130. Furthermore, in this example, the memory system 100 performs either a read operation or a write operation on one of the memory banks 195 and 196 at a given time, and does not perform operations on both memory banks 195 and 196 simultaneously. The sensing amplifier 130 bases the bit determination on the voltage difference between a given pair of sensing nodes corresponding to one of the memory banks 195 and 196 in response to a read operation on that individual bank.

[0025] The interface between the bit line pair and the sensing node pair will be described in more detail with reference to Figure 7. Furthermore, an exemplary architecture of the sensing amplifier 130 will be described in more detail with reference to Figures 2 and 4.

[0026] Figure 7 illustrates an exemplary interface of a single bit line and bit line pair (bl and blb) to a sensing node and complementary sensing nodes (q and qb). Figure 7 is generalized for ease of explanation, and it should be understood that the concepts described in Figure 7 are applicable to both the sensing amplifier architectures in Figures 1-4 and Figures 5-6. Figure 7 shows only a single bit line pair, and it should be understood that other bit line pairs may be coupled to sensing nodes q and qb and selected using an appropriate multiplexer signal rm[0:3].

[0027] The bit line pair, bit line bl and complementary bit line blb, forms a column. Bit cell 705 is located at the intersection of the column and the word line wl. In this example, bit cell 705 is formed by a pair of cross-coupled inverters. The output node of the first inverter is the true (Q) output of bit cell 705. This output node is coupled to bit line bl via NMOS access transistor M4. Similarly, the output node of the remaining second inverter is the complementary (QB) output of bit cell 705, coupled to complementary bit line blb via NMOS access transistor M3. The word line wl is coupled to the gate of the access transistor so that the Q node and QB node drive their respective bit lines during the word line assertion period.

[0028] In an exemplary read operation, a clock cycle triggers a voltage assertion on the word line wl. Prior to this word line assertion, the bit lines bl and blb are pre-charged to the supply voltage by the bit line pre-charge circuit 750. Bit line bl is coupled to the corresponding sensing node q via PMOS charge transfer transistor M1. Similarly, the complementary bit line blb is coupled to the corresponding sensing node qb via PMOS charge transfer transistor M2. Prior to the word line assertion, the gate voltages rm of charge transfer transistors M1 and M2 are asserted to the supply voltage to prevent charge transfer to the sensing nodes. Controller 745 asserts a sensing node pre-charge signal (pch) before the word line assertion. The asserted sensing node pre-charge signal drives the gates of NMOS transistors (e.g., N1 and N2 in Figure 4). The sources of these NMOS transistors are connected to ground, and their drains are connected to q and qb, respectively. Therefore, the assertion of the sensing node pre-charge signal discharges both q and qb. The same applies to transistors N3 and N4, for example, which discharge q and qb in other memory banks.

[0029] Next, the voltage of word line wl may be asserted, which switches on access transistors M3 and M4 so that the true output node and complementary output node of bit cell 705 are connected to bit lines bl and blb, respectively. Word line assertion creates a bit line voltage difference between the bit lines in each bit line pair. One bit line in each bit line pair is slightly reduced from the supply voltage (the bit line is partially discharged), while the remaining bit lines in each bit line pair remain in their pre-charged state (the bit lines are fully charged).

[0030] With the word line still asserted and a bit line voltage difference present, the charge transfer period is triggered by the discharge of the gate voltage rm. For example, the gate voltage rm may be controlled by a dummy bit line. Due to the discharge of the gate voltage rm less than this moment, the gate voltage rm discharges to the threshold voltage of the charge transfer transistor (e.g., M2) whose source is connected to the fully charged bit line, but still exceeds the threshold voltage of the charge transfer transistor (e.g., M1) whose source is connected to the partially discharged bit line. Thus, the charge transfer transistor of the fully charged bit line conducts charge to its sensing node before the charge transfer transistor conducts charge from the partially discharged bit line. Consequently, the sensing node voltage qb increases prior to the increase in the complementary sensing node voltage q.

[0031] The architectures shown in both Figures 1-4 and Figures 5-6 use this voltage difference to perform bit decisions. For example, Figure 2 is a diagram of a sense amplifier 130 that exemplifies the implementation of Figure 1. In this example, the sense amplifier 130 is implemented using a cross-coupled pair of AOI gates 131 and 132. The truth table for AOI gate 131 is shown below.

[0032] [Table 1]

[0033] The truth table for AOI gate 132 is shown below.

[0034] [Table 2]

[0035] Figure 3 provides an exemplary timing diagram of the signal applied to the sensing amplifier 130 in Figure 2, in one implementation configuration. This example follows the discussion in Figure 7 (above), where bl and blb correspond to bit line pairs in bank 195, starting with VDD and bl is finally discharged to read the stored 0.

[0036] The top signal (b0_bl_pre) is the pre-charge signal, as discussed above with respect to Figure 7. Pre-charging is turned off at time t1, and then the word line wl signal is asserted at time t2. The bit line (bl) is discharged, but the bit line complement (blb) remains VDD.

[0037] When bl and blb have a sufficient voltage difference, pch_b0 is deasserted at time t3, which means that discharge NMOS transistors N3 and N4 are turned off, while transistors N1 and N2 remain on. Transistor P14 is turned on, but signals SROP and SRON are both high, which turns off transistors P1-P4, as well as N11 and P12. Transistors P1 and P3 couple VDD to q_b0 and q_b1, and transistors P2 and P4 couple VDD to qb_b0 and qb_b1.

[0038] Next, the read mux signal (b0_rm) turns on at time t4, which couples the sensing node pair to the bit line pair. Bit line bl is coupled to sensing node q, and blb is coupled to the complementary sensing node qb. The bit line complement blb has a higher potential, which causes qb to rise faster than q at time t5. (Note that q_b1 and qb_b1 remain low, with transistors P5 and P6 on and transistors N7 and N8 off.) As a result, the SRON signal becomes low at time t6. When SRON is low, transistors P9, P2, P4, and N11 turn on, and transistor N9 turns off. On the other hand, the high value of SROP causes transistors P1, P3, and P11 to turn off, and N10 turns on. Transistor N11 pulls its output (sa_out) to 0 (i.e., ground) while transistor P12 is off, and therefore the output complement (sa_out_n) is 1. At time t7, the word line wl is deasserted, followed by pch and rm. As a result, the sensing amplifier 130 senses an output value of 0 and can send it to an output circuit such as an output latch (not shown).

[0039] In contrast, a digital 1 read operation keeps bl high, discharges blb, and as a result, q_b0 becomes high, qb_b0 becomes low, and sa_out is output as a digital 1. Of course, this example is for a read operation performed on memory bank 195. It is understood that a read operation performed on memory bank 196 would be performed similarly.

[0040] Figure 4 shows an exemplary sensing amplifier 430 in one implementation configuration. The example in Figure 4 is provided to demonstrate that the range of implementation configurations is not limited to any particular number of memory banks. Rather, the sensing amplifier 430 can be scaled to accommodate a further number of memory banks up to N memory banks, where N is an integer greater than 2, and each memory bank will have sensing nodes and complementary sensing nodes (i.e., q_b0 to q_bn-1 and qb_b0 to qb_bn-1). The sensing amplifier 430 can be scaled by increasing the number of series PMOS transistors PX and PX-b and the number of parallel NMOS transistors NX and NX_b.

[0041] Figure 5 shows an exemplary memory system 500 in one implementation configuration. The implementation configuration in Figure 5 uses two sensing amplifiers 510 and 520 to accommodate multiple memory banks 195 and 196. Sensing amplifiers 510 and 520 can be implemented similarly to each other. In this implementation configuration, memory bank 195 corresponds to sensing node pair q_b0, qb_b0, and memory bank 196 corresponds to sensing node pair q_b1, qb_b1. Sensing amplifier 510 is coupled to multiplexer 110 by sensing node pair q_b0, qb_b0, and sensing amplifier 520 is coupled to multiplexer 120 by sensing node pair q_b1, qb_b1.

[0042] In this example, only one of memory banks 195 and 196 is written to or read from at a particular time. In other words, only one of the sensing amplifiers 510 and 520 is expected to perform a bit determination during any particular read operation. Furthermore, sensing amplifiers 510 and 520 are not used during write operations. Once a bit determination is performed, the bit may be applied to downstream circuits such as a latch (not shown).

[0043] Figure 6 shows the sensing amplifiers 510 and 520 in one implementation configuration. Specifically, sensing amplifier 510 may include a cross-coupled pair of NAND gates 631 and 632, and sensing amplifier 520 may include a cross-coupled pair of NAND gates 633 and 634. Each cross-coupled pair of NAND gates performs bit determination based on the voltage difference between sensing nodes in the sensing node pair, similar to the examples in Figures 1 to 4.

[0044] This example continues from the discussion in Figure 7 (above), where bl and blb correspond to bit line pairs in bank 195, starting at the power supply voltage VDD, and bl is eventually discharged to read the stored 0. The following table is the truth table for the cross-coupled NAND gates 631 and 632, and it is understood that the same logic is provided by the cross-coupled NAND gates 633 and 634.

[0045] [Table 3]

[0046] The sensing node q_b is connected to the input of NAND gate 631, and the sensing node qb_b0 is connected to the input of NAND gate 632. NAND gates 631 and 632 are cross-coupled to form an RS latch. In this example, the sensing node pair is pre-charged to 0 volts, causing both outputs of NAND gates 631 and 632 to assert high with respect to the supply voltage VDD, and bit cell 705 stores digital 1. Pre-charging the sensing node pair to 0 volts turns on transistors P24 and P26. Both SRON_b0 and SROP_b0 are high, which turns off transistors P21, P22, P23, P25, P27, and N27, and turns on transistors N23 and N25. The parasitic capacitance of the sensing node, conceptually represented by capacitor C (Figure 7), is relatively small compared to the bit line capacitance, conceptually represented by capacitor Cbl (Figure 7). The short time period during which charge transfer transistor M1 (Figure 7) begins to conduct before charge transfer transistor M2 (Figure 7) therefore causes a significant increase in the voltage of sensing node q_b0 compared to sensing node qb_b0. This voltage increase exceeds the threshold voltage of NAND gate 631, so its output is discharged to 0. In other words, the increase in the voltage of sensing node q_b0 turns on transistors N24 and N26, which pulls SROP_b0 to a value of 0. The 0 output of NAND gate 631 enhances the high binary output of NAND gate 632 by turning on transistor P26 and turning off transistor N25. Transistor P27 is turned on, and transistor N27 remains off so that the binary value 1 stored in bit cell 705 is detected.

[0047] In the example where 0 is stored in bit cell 705, the value output by NAND gate 632 becomes 0 by turning on transistors N25 and N26, and the value output by NAND gate 631 becomes 1. In different reading operations, the same process may be performed within the sensing amplifier 520. In other words, the array of transistors in sensing amplifier 520, through the cross-coupled NAND gates 633 and 634, brings about the same logic provided by the array of transistors in sensing amplifier 510.

[0048] Another difference between the embodiments in Figures 1-4 and the implementations in Figures 5-6 is that the implementations in Figures 5-6 include two push-pull circuits containing transistors P27, N27, P37, and N37, whereas the implementations in Figures 1-4 include a single push-pull circuit containing transistors P12 and N11. This is one example of how the implementations in Figures 1-4 reduce the number of transistors compared to the implementations in Figures 5-6. Also, as mentioned above, a single set of cross-coupled AOI gates has fewer transistors than two sets of cross-coupled NAND gates, which is another example of how the implementations in Figures 1-4 reduce the number of transistors. Nevertheless, both implementations described herein provide reliable operation and can be implemented in given applications as needed. As mentioned above, the implementations herein can reduce the number of bit line pairs per sensing node pair, thereby reducing the parasitic capacitance seen in the sensing amplifier and thus enabling faster detection of smaller voltage differences.

[0049] An exemplary method for a read operation will be discussed with reference to the flowchart shown in Figure 8. Method 800 may be performed by a memory such as those shown in Figures 1 and 5. In other words, Method 800 may be performed by a multibank memory system having multiple read multiplexers and one or more sense amplifiers to perform bit determination for a given read operation.

[0050] Action 810 includes multiplexing a first set of bit line pairs with a first set of sensing nodes. Action 810 may also include coupling a first set of bit line pairs with a first set of sensing nodes. An example in which the bit line pairs and sensing node pairs are coupled by a set of transistors and, when those transistors are turned on, the bit line pairs and sensing node pairs share a charge is described above with reference to Figure 7.

[0051] In action 820, the method includes charge sharing between a first bit line pair and a first sensing node pair. In the example in Figure 7, when the transistor is turned on, the bit line pair is electrically coupled to the sensing node pair. In the example where the transistor is a PMOS transistor, the gate-source voltage determines when a particular transistor turns on. For example, when the magnitude of the gate-source voltage reaches a higher voltage faster, the transistor turns on faster, and when the magnitude of the gate-source voltage reaches a higher voltage more slowly, the transistor turns on more slowly. Thus, the bit lines or complementary bit lines may charge or discharge the sensing nodes or complementary sensing nodes faster or slower, depending on the charge-sharing architecture. However, the time lag in charge sharing is a fraction of the rail voltage, but it may result in a voltage that can be detected for bit determination.

[0052] In action 830, the method includes inputting values ​​from a pair of sensing nodes into a logic circuit. In one example, the logic circuit may include a cross-coupled AOI gate, as shown in the implementation in Figure 2. In another example, the logic circuit may include a cross-coupled NAND gate, as shown in the implementation in Figure 6.

[0053] In action 840, the method includes causing a logic circuit to perform a bit determination based on values ​​from a first pair of sensing nodes. For example, the logic circuit may provide a logic function that provides a digital 1 or digital 0 output in response to a voltage difference detected between a sensing node and a complementary sensing node.

[0054] As described above, this method may be performed in a memory system having multiple memory banks, each of which is coupled to a read multiplexer, and each read multiplexer is coupled to a sensing node pair. In some examples, only one memory bank may be accessed during a read or write operation. Therefore, subsequent read operations may be performed on the same memory bank or a different memory bank. Actions 850-870 show subsequent read operations performed on a second memory bank using a second bit line pair and a second sensing node pair. However, in other examples, it is understood that actions 850-870 may be performed on the same memory bank using a first bit line pair and a second sensing node pair.

[0055] The scope of implementations is not limited to the series of actions described with respect to Figure 8. Rather, other implementations may add, omit, rearrange, or modify one or more actions. For example, during the operation of the memory system, a read operation may be performed on a first memory bank or a second memory bank, and then a subsequent read operation may be performed on either the first memory bank or the second memory bank, and so on. Read operations may or may not be interspersed with write operations, and operations may be repeated as needed.

[0056] Figure 9 shows an exemplary SOC900 in one implementation configuration. In this example, the SOC900 is implemented on a semiconductor die and includes several system components 910-990. Specifically, in this example, the SOC900 includes a CPU 910, which is a multi-core general-purpose processor having four processor cores, cores 0-3. Of course, other implementation configurations may include two cores, eight cores, or any other appropriate number of cores in the CPU 910, so the scope of implementation configurations is not limited to any specific number of cores. The SOC900 further includes other system components such as a first digital signal processor (DSP) 940, a second DSP 950, a modem 930, a GPU 920, a video subsystem 960, a wireless local area network (WLAN) transceiver 970, and a video-front-end (VFE) subsystem 980. The SOC900 also includes a RAM memory unit 990 which can act as system RAM for any of the components 910 to 980. For example, the RAM memory unit 990 can receive data and instructions from any of the components 910 to 980.

[0057] The RAM memory unit 990 may include a sensing amplifier architecture that serves a multibank array as described above with respect to Figures 1 to 7. Furthermore, the RAM memory unit 990 may perform the actions shown in Figure 8 to perform a read action.

[0058] As those skilled in the art will understand at present, in accordance with the specific applications present, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration and method of use of the devices of this disclosure, and to them, without departing from their scope. In light of this, the specific embodiments shown and described herein are only a few examples, and therefore the scope of this disclosure should not be limited to the scope of such specific implementations, but rather should be exactly the same as the scope of the claims and their functional equivalents appended below.

[0059] The following numbered clauses describe the implementation forms. 1. A first read multiplexer that connects a first set of bit lines to a first sensing node and a first complementary sensing node, A second read multiplexer that connects a second set of bit lines to a second sensing node and a second complementary sensing node, A first sensing amplifier coupled to a first sensing node and a first complementary sensing node, wherein the first reading multiplexer is associated with a first bank of memory bit cells and the second reading multiplexer is associated with a second bank of memory bit cells, and A circuit that includes this.

[0060] 2. A second sensing amplifier coupled to a second sensing node and a second complementary sensing node, wherein the output of the second sensing amplifier is coupled to the output of the first sensing amplifier. The circuit of clause 1, further including the following.

[0061] 3. The first sense amplifier includes a first cross-coupled pair of NAND gates, and the second sense amplifier includes a second cross-coupled pair of NAND gates, and the circuit is A first push-pull circuit coupled to a first cross-coupled pair of NAND gates, and a second push-pull circuit coupled to a second cross-coupled pair of NAND gates It further includes, The output of the first sensing amplifier and the output of the second sensing amplifier are coupled via the first push-pull circuit and the second push-pull circuit. Circuit for clause 2.

[0062] 4. The circuit of clause 3, wherein a first cross-coupled pair of NAND gates is coupled to a first sensing node, and a second cross-coupled pair of NAND gates is coupled to a first complementary sensing node.

[0063] 5. The circuit of clause 1, wherein the first sensing amplifier is further coupled to the second sensing node and the second complementary sensing node.

[0064] 6. The first sensing amplifier, Cross-coupled pairs of AND-OR-inversion (AOI) gates Includes, The first AOI gate of the cross-coupled pair of AOI gates is coupled to the output from the first complementary sensing node, the second complementary sensing node, and the second AOI gate of the cross-coupled pair of AOI gates. The second AOI gate of the cross-coupled pair of AOI gates is coupled to the output from the first sensing node, the second sensing node, and the first AOI gate of the cross-coupled pair of AOI gates. Circuitry for clause 5.

[0065] 7. The first sensing amplifier, A cross-connected pair of AND-OR-inversion (AOI) gates, A push-pull circuit coupled to the output of the first AOI gate of a cross-coupled pair of AOI gates and the output of the second AOI gate of the cross-coupled pair of AOI gates. The circuit of clause 5, including the circuit of clause 5.

[0066] 8. The first sensing amplifier is coupled to N further sensing nodes and N further complementary sensing nodes, and the first sensing amplifier, Includes a cross-connected pair of AND-OR-invert (AOI) gates, The first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sensing node, the second complementary sensing node, and N further complementary sensing nodes. A second AOI gate of a cross-connected pair of AOI gates is connected to the first sensing node, the second sensing node, and N further sensing nodes, where N is an integer greater than 1. Circuitry for clause 5.

[0067] 9. In a first read operation, multiplexing a first plurality of bit line pairs with a first sensing node pair, which includes combining a first bit line pair among the first plurality of bit line pairs with the first sensing node pair. The first bit line pair and the first sensing node pair share charge, Inputting values ​​from the first pair of sensing nodes into a logic circuit, The logic circuit is made to perform a bit determination based on the value from the first pair of sensing nodes, In a subsequent read operation, the second set of bit line pairs is multiplexed with the second set of sensing nodes, including coupling the second set of bit line pairs with the second set of sensing nodes, wherein the first set of bit line pairs is associated with the first bank of memory bit cells, and the second set of bit line pairs is associated with the second bank of memory bit cells. Methods that include...

[0068] 10. Charge sharing between the second bit line pair and the second sensing node pair, The logic circuit is made to perform subsequent bit determinations based on inputs from the second pair of sensing nodes. The method of Article 9, further including the method of Article 9.

[0069] 11. The method of clause 10, wherein the logic circuit includes a first sensing amplifier associated with a first sensing node pair and a second sensing amplifier associated with a second sensing node pair.

[0070] 12. The method of clause 10, wherein the logic circuit includes a sensing amplifier coupled to a first pair of sensing nodes and a second pair of sensing nodes.

[0071] 13. The method of clauses 9-10, wherein the logic circuit includes multiple cross-coupled pairs of NAND gates.

[0072] 14. The method of Clause 9 or 10, wherein causing a logic circuit to perform a bit determination involves pushing up or pulling down the output of a first cross-coupled NAND pair of gates using a first push-pull circuit coupled to a second push-pull circuit associated with an additional cross-coupled pair of NAND gates.

[0073] 15. The method of Clause 9 or 10, wherein the logic circuit includes a cross-coupled pair of AND-OR-inverting (AOI) gates.

[0074] 16. Multiple memory banks, each containing multiple bit line pairs, Multiple pairs of sensing nodes, each associated with one of the memory banks, A means for multiplexing bit line pairs with sensing node pairs, Means for performing bit determination based on voltages associated with sensing node pairs during multiple read operations targeting multiple memory banks A memory device that includes this.

[0075] 17. A memory device according to clause 16, wherein the means for performing a bit determination includes a cross-coupled pair of AND-OR-inverting (AOI) gates, and the cross-coupled pair of AOI gates is coupled to a plurality of sensing node pairs.

[0076] 18. The memory device of clause 17, further comprising a push-pull circuit coupled to the output of a first AOI gate of a cross-coupled pair of AOI gates and the output of a second AOI gate of a cross-coupled pair of AOI gates.

[0077] 19. The memory device of clause 16, wherein the means for performing bit determination includes a plurality of cross-coupled NAND gate pairs, wherein a first NAND gate pair of the NAND gate pairs is coupled to a first sensing node pair, and a second NAND gate pair of the NAND gate pairs is coupled to a second sensing node pair.

[0078] 20. A first memory bank containing a first set of bit cells arranged in a first set of columns, A second memory bank containing a second set of bit cells arranged in a second set of columns, A first pair of sensing nodes joined to a first number of columns by a first read multiplexer, A second pair of sensing nodes joined to a second set of columns by a second read multiplexer, A first sensing amplifier coupled to the first sensing node pair and Memory, including

[0079] 21. Memory of clause 20, wherein the first sensing amplifier includes a cross-coupled pair of AND-OR-inverting (AOI) gates further coupled to the second sensing node pair.

[0080] 22. The first sensing amplifier is coupled to N further pairs of sensing nodes, The first AOI gate of the cross-coupled pair of AOI gates is coupled to the first complementary sensing node, the second complementary sensing node, and N further complementary sensing nodes. A second AOI gate of a cross-connected pair of AOI gates is connected to the first sensing node, the second sensing node, and N further sensing nodes, where N is an integer. Memory for clause 21.

[0081] 23. The memory of clause 20, further comprising a second sense amplifier, the first sense amplifier comprising a first cross-coupled pair of NAND gates, and the memory comprising a second cross-coupled pair of NAND gates and coupled to a second sense node pair.

[0082] 24. A memory according to any of the clauses 20 to 23, wherein a first sensing node pair is coupled to a first plurality of columns by a plurality of bit line pairs, and a first read multiplexer is configured to turn on a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor to couple a first bit line pair of the bit line pairs to the first sensing node pair.

Claims

1. A first read multiplexer that connects a first set of bit lines to a first sensing node and a first complementary sensing node, A first transistor having a source connected to ground and a drain connected to the first sensing node, A second transistor having a source connected to ground and a drain connected to the first complementary sensing node, A second read multiplexer that connects a second set of bit lines to a second sensing node and a second complementary sensing node, A third transistor having a source connected to ground and a drain connected to the second sensing node, A fourth transistor having a source connected to ground and a drain connected to a second complementary sensing node, A first sensing amplifier coupled to the first sensing node and the first complementary sensing node, wherein the first read multiplexer is associated with a first bank of memory bit cells and the second read multiplexer is associated with a second bank of memory bit cells. Includes, The first sensing amplifier is further coupled to the second sensing node and the second complementary sensing node. circuit.

2. The first sensing amplifier, Includes a cross-coupled pair of AND-OR-inversion (AOI) gates, The first AOI gate of the cross-coupled pair of AOI gates is coupled to the output from the first complementary sensing node, the second complementary sensing node, and the output from the second AOI gate of the cross-coupled pair of AOI gates. The second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sensing node, the second sensing node, and the output from the first AOI gate of the cross-coupled pair of AOI gates. The circuit according to claim 1.

3. The first sensing amplifier is coupled with N further sensing nodes and N further complementary sensing nodes, and the first sensing amplifier Further including cross-coupled pairs of AND-OR-inversion (AOI) gates, The cross-coupled pair of first AOI gates of the AOI gate are coupled to the first complementary sensing node, the second complementary sensing node, and the N further complementary sensing nodes, The second AOI gate of the cross-coupled pair of AOI gates is coupled to the first sensing node, the second sensing node, and the N further sensing nodes, where N is an integer greater than 1. The circuit according to claim 1.

4. In the first reading operation, the multiplexing includes multiplexing a first plurality of bit line pairs with a first sensing node pair, which includes combining a first bit line pair among the first plurality of bit line pairs with the first sensing node pair. The first bit line pair and the first sensing node pair share charge, Inputting the values ​​from the first pair of sensing nodes into the logic circuit, The logic circuit is made to perform bit determination based on the value from the first pair of sensing nodes, In a subsequent read operation, the second plurality of bit line pairs are multiplexed with the second pair of sensing nodes, and the second bit line pair among the second plurality of bit line pairs is coupled to the second pair of sensing nodes, wherein the first plurality of bit line pairs are associated with a first bank of memory bit cells, and the second plurality of bit line pairs are associated with a second bank of memory bit cells, and the multiplexing is performed. A method including, The logic circuit includes a first sensing amplifier (130, 430) coupled to the first sensing node pair and the second sensing node pair, The method further includes discharging the first pair of sensing nodes using a first transistor having a source connected to ground and a drain connected to a first sensing node, and a second transistor having a source connected to ground and a drain connected to a first complementary sensing node. The method further includes discharging the second pair of sensing nodes using a third transistor having a source connected to ground and a drain connected to a second sensing node, and a fourth transistor having a source connected to ground and a drain connected to a second complementary sensing node. method.

5. The second bit line pair and the second sensing node pair share charge, The logic circuit is made to perform subsequent bit determination based on the input from the second pair of sensing nodes. The method according to claim 4, further comprising:

6. The method according to claim 5, wherein the logic circuit includes a sensing amplifier coupled to the first sensing node pair and the second sensing node pair.

7. The method according to claim 4, wherein the logic circuit includes a cross-coupled pair of AND-OR-inverting (AOI) gates.

8. A memory comprising the circuit described in Claim 1, wherein the memory is A first memory bank containing a first plurality of bit cells arranged in a first plurality of columns, A second memory bank containing a second set of bit cells arranged in a second set of columns, A first pair of sensing nodes joined to the first plurality of columns by the first read multiplexer, A second pair of sensing nodes joined to the second plurality of columns by the second read multiplexer, Memory, including

9. The memory according to claim 8, wherein the first sensing node pair is coupled to the first plurality of columns by a plurality of bit line pairs, and the first read multiplexer is configured to turn on a first p-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor to couple a first bit line pair among the bit line pairs to the first sensing node pair.

Images