Processor and compiler

Abstract

To solve a processing delay problem which occurs when a counter circuit for repeatedly counting loop variables or accumulator variables consists of programmable devices.SOLUTION: A processor 161 comprises an array 162 consisting of multiple programmable logics 1, and at least one dedicated counter circuit 163 for counting variables that are repeatedly changed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] ,

[0001] The present disclosure relates to a processor and a compiler.

Background Art

[0002] In a system combining a dynamic reconfiguration processor and an operation synthesis tool, arithmetic units and wiring resources are reused by folding a multi-state circuit in time series (see Patent Document 1). Therefore, such a system can execute a program with high area efficiency with respect to a fine-grained reconfigurable device represented by an FPGA (Field Programmable Gate Array) that continues to use a circuit once written.

[0003] In operation synthesis for synthesizing a program written in an operation description language such as the C language as a circuit for a programmable device capable of rewriting such as a dynamic reconfiguration processor, a state transition machine (FSM) and a data path are generated, and a circuit for switching the data path in time series according to each state is generated. As one of the parallelization methods in this operation synthesis, a method of synthesizing a loop description as a pipeline circuit is known (Patent Document 2).

[0004] In operation synthesis for synthesizing a pipeline circuit, a method of controlling execution for each stage of the pipeline is known (Patent Document 3).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0006] When a counter circuit that repeatedly counts loop variables or accumulator variables is configured using programmable logic, a problem arises in that processing delays occur.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] One embodiment of the processor comprises an array of multiple programmable logics and at least one dedicated counter circuit for counting variables that are repeatedly modified. [Effects of the Invention]

[0009] According to one embodiment of the processor, the counter circuit is a dedicated circuit, so processing delays can be avoided. [Brief explanation of the drawing]

[0010] [Figure 1] This diagram shows the configuration of the processor 161 according to the first embodiment. [Figure 2] This is a diagram to explain image filters. [Figure 3] This diagram shows an image filtering process described in C language. [Figure 4] This diagram shows the configuration of the dynamic reconfiguration processor according to the second embodiment. [Figure 5] This diagram shows the configuration of the processing element PE. [Figure 6] This figure shows an example of a loop description in the second embodiment. [Figure 7] This is a block diagram showing the components of a dedicated counter circuit 2 for counting the loop variables of the loop in Figure 6. [Figure 8] This diagram shows the detailed configuration of the counter circuit according to the second embodiment. [Figure 9] It is a diagram showing an example of a method for implementing the counter of the reference example. [Figure 10] It is a diagram showing the configuration of processing elements PE(X), PE(Y), and PE(Z). [Figure 11] It is a diagram showing an example of a loop description of a modification of the second embodiment. [Figure 12] It is a block diagram showing the components of a dedicated counter circuit 2A for counting the loop variable of the loop in FIG. 11. [Figure 13] It is a block diagram showing the components of the counter circuit 202 of the third embodiment. [Figure 14] It is a block diagram showing the components of the counter circuit 302 of a modification of the third embodiment. [Figure 15] It is a block diagram showing the components of the counter circuit 402 of the fourth embodiment. [Figure 16] It is a diagram showing the configuration of the counter circuit 502 of a modification of the fourth embodiment. [Figure 17] It is a diagram showing the counter circuit, state transition controller, and processing element array of the fifth embodiment. [Figure 18] It is a diagram showing the counter circuit, state transition controller, and processing element array of modification 1 of the fifth embodiment. [Figure 19] It is a diagram showing the counter circuit, state transition controller, and processing element array of modification 2 of the fifth embodiment. [Figure 20] It is a diagram showing the configuration of the dynamic reconfiguration processor of the sixth embodiment. [Figure 21] It is a block diagram showing the configuration of the counter circuit 2X of a modification of the sixth embodiment. [Figure 22] It is a diagram showing an example of a program in which an escape condition establishment signal PS and an inverted escape condition signal / PS are used. [Figure 23] It is a block diagram showing the components of the counter circuit 72 of the seventh embodiment. [Figure 24]This diagram illustrates an example of a program that utilizes an accumulator. [Figure 25] This is a diagram illustrating the compiler's structure. [Figure 26] This diagram shows an example of a state transition machine and a data path context generated by the behavior synthesis unit 900. [Figure 27] This diagram shows an example of a pipeline generated during behavioral synthesis. [Figure 28] This diagram shows an example of a pipeline circuit execution when the loop repeats four times. [Figure 29] This diagram illustrates the overhead of pipeline implementation. [Figure 30] This diagram illustrates an example of reducing the overhead of pipeline development. [Modes for carrying out the invention]

[0011] The embodiments will be described below with reference to the drawings. [First Embodiment] Figure 1 is a diagram showing the configuration of the processor according to the first embodiment.

[0012] The processor 161 comprises an array 162 and at least one counter circuit 163.

[0013] Array 162 includes multiple programmable logic units 1. Programmable logic 1 provides computational resources such as adders, selectors, and LUTs.

[0014] The counter circuit 163 is a dedicated circuit for counting variables that are repeatedly modified. Variables that are repeatedly modified include, for example, loop variables in a loop description, or accumulator variables whose increment value is repeatedly added inside a loop.

[0015] In this embodiment, since the counter circuit is a dedicated circuit, the problem of processing delay can be solved.

[0016] [Second Embodiment] Figure 2 is a diagram illustrating image filters. It shows an example of convolution processing of image data using an FIR (Finite Impulse Response) filter, etc. Figure 2 shows an example of applying a 3x3 pixel kernel filter to an image.

[0017] Figure 3 shows an image filtering process description in C language. The image is described with a horizontal size (x direction) of 200 pixels, a vertical size (y direction) of 100 pixels, and a kernel of 3x3 pixels. Since there are invalid areas of 1 pixel each on the left and right, totaling 2 pixels, the maximum value in the x direction is (200-2) pixels, and similarly in the y direction, the maximum value is (100-2) pixels by subtracting the 2 invalid areas in the vertical direction.

[0018] Processors such as CPUs (Central Processing Units) generally process information sequentially as it is written. On the other hand, processors such as FPGAs or dynamically reconfigurable processors, or dedicated hardware, can increase processing speed by performing multiple calculations simultaneously.

[0019] Figure 4 shows the configuration of a dynamic reconfiguration processor according to a second embodiment. The dynamic reconfiguration processor includes an array 51 containing multiple processing elements PE capable of basic operations such as addition and subtraction, larger arithmetic elements such as a multiplier MUL, memory HMEM, VMEM, wiring for connecting these, and wiring switches. The dynamic reconfiguration processor includes a state transition controller 50. The state transition controller 50 controls the state transitions of the dynamic reconfiguration processor by switching the wiring switches and instructions for the processing elements PE.

[0020] Figure 5 shows the configuration of the processing element PE. The processing element PE comprises an instruction memory 91, an arithmetic unit 92, and a register 93.

[0021] The instruction pointer PT from the state transition controller 50 specifies the instruction to be executed in the instruction memory 91. The arithmetic unit 92 executes the instruction. The register 93 stores the data. SWI switches whether or not to input data on the data wiring. SWO switches whether or not to output the data in register 93 to the data wiring. SW switches the data transmission route.

[0022] The image filter described above can be implemented by switching the instruction pointer from the state transition controller 50 and the switches SW, SWI, and SWO. In this case, the image filtering portion of the (3x3) kernel within the inner loop can be pipelined. However, the part that controls the loop is self-referential, with the same loop variable on both the left and right sides, such as x=x+1. Therefore, the counter circuit that counts the loop variable cannot increase its operating frequency through pipelineization.

[0023] The dynamic reconfiguration processor of this embodiment includes a dedicated counter circuit 2 for counting loop variables. The state transition controller 50 controls the state of the dynamic reconfiguration processor by controlling the counter circuit 2.

[0024] Loop control can be described using either a for statement or a do-while statement. In a for statement, the loop variable is incremented after being compared with the maximum value. In a do-while statement, the loop variable is incremented, and then compared with the maximum value. In this embodiment, a counter circuit for counting the loop variable in a for statement is shown.

[0025] Figure 6 is a diagram showing an example of a loop description of the second embodiment. Figure 7 is a block diagram showing the components of a dedicated counter circuit 2 for counting the loop variable x of the loop in Figure 6. The counter circuit 2 comprises a storage unit 11, a selection unit 13, an addition unit 12, and a comparison unit 14.

[0026] The memory unit 11 stores the output of the selection unit 13 as a counter value (sCnt). When the writeable signal WE is asserted, the memory unit 11 updates the counter value (sCnt) based on the output signal of the selection unit 13.

[0027] The selection unit 13 stores an initial value (sInit). When the initialization signal (INIT) is asserted, the selection unit 13 outputs the initial value (sInit) to the storage unit 11. When the initialization signal (INIT) is not asserted, the selection unit 13 outputs the output signal of the adder 12 to the storage unit 11. The initial value (sInit) is, for example, "0".

[0028] The adder 12 stores the increment value (sInc). When the add instruction signal (EN) is asserted, the adder 12 adds the output (sCnt) of the storage unit 11 and the increment value (sInc). The increment value (sInc) is, for example, "1".

[0029] The comparison unit 14 stores the maximum value (sMax). The comparison unit 14 compares the counter value (sCnt) with the maximum value (sMax) and outputs a signal indicating the comparison result. When the counter value (sCnt) reaches the maximum value (sMax), the comparison unit 14 asserts the loop exit condition fulfillment signal (PS).

[0030] Figure 8 shows a detailed configuration of the counter circuit according to the second embodiment. The selection unit 13 comprises a selector 381 and a register 386. The selector 381 receives an initialization signal (INIT). The register 386 stores an initial value (sInit). The initial value (sInit) is, for example, "0".

[0031] The memory unit 11 includes a register 382. The register 382 stores a counter value (sCnt).

[0032] The addition unit 12 comprises an adder 383 and a register 384. The adder 383 receives an add instruction signal (EN). The register 384 stores an increment value (sInc). The increment value (sInc) is, for example, "1".

[0033] In this embodiment, by making the counter circuit a dedicated circuit, the delay can be reduced and the operating speed can be improved.

[0034] (Reference example) Figure 9 is a diagram illustrating an example of how to implement the counter in the reference example. Figure 10 is a diagram illustrating the configuration of the processing elements PE(X), PE(Y), and PE(Z).

[0035] A counter circuit is realized using three PE(X), PE(Y), and PE(Z) elements. In this way, PEs in programmable logic, or LUTs in FPGAs, offer a high degree of flexibility and allow for the creation of general-purpose circuits, but they have a greater delay compared to dedicated hardware circuits.

[0036] [Modified version of the second embodiment] Figure 11 is a diagram showing an example of a loop description of a modified version of the second embodiment. Figure 11 shows an example of a loop description using a do-while statement. Figure 12 is a block diagram showing the components of a dedicated counter circuit 152 for counting the loop variable x of the loop in Figure 11. The counter circuit 152 comprises a storage unit 11, a selection unit 13, an addition unit 12, and a comparison unit 64.

[0037] The configuration and operation of the memory unit 11, selection unit 13, and addition unit 12 of the counter circuit 152 are the same as those of the memory unit 11, selection unit 13, and addition unit 12 of the counter circuit 2, so the explanation will not be repeated.

[0038] The comparison unit 64 stores the maximum value (sMax). The comparison unit 14A compares the output of the adder 12 with the maximum value (sMax). When the output of the adder 12 reaches the maximum value (sMax), the comparison unit 64 asserts the loop exit condition fulfillment signal (PS).

[0039] [Third Embodiment] Figure 13 is a block diagram showing the components of the counter circuit 202 of the third embodiment. The counter circuit 202 counts the loop variables of loop A (for example, x in Figure 3) and the loop variables of loop B, which is one loop outside of loop A (for example, y in Figure 3). The counter circuit 202 comprises a first loop counter 22A that counts the loop variables of loop A and a second loop counter 22B that counts the loop variables of loop B.

[0040] The first loop counter 22A outputs a loop exit condition fulfillment signal (PS1) (first signal) to the second loop counter 22B when the termination condition of loop A is met. When the second loop counter 22B receives the loop exit condition fulfillment signal (PS1) (first signal), it increments the loop variable of loop B. When the termination condition of loop B is met, the second loop counter 22B outputs a loop exit condition fulfillment signal (PS1) (second signal) to the state transition controller 50.

[0041] The first loop counter 22A comprises a storage unit 11A, a selection unit 13A, an addition unit 12A, and a comparison unit 14A. The second loop counter 22B comprises a storage unit 11B, a selection unit 13B, an addition unit 12B, and a comparison unit 14B.

[0042] The memory unit 11A stores the counter value (sCnt1) of the loop variable of loop A. When the writeable signal WE is asserted, the memory unit 11A updates the counter value (sCnt1) based on the output signal of the selection unit 13A.

[0043] The selection unit 13A stores an initial value (sInit1). When the initialization signal (INIT) is asserted or the loop exit condition signal (PS1) is asserted, the selection unit 13A outputs the initial value (sInit1) to the storage unit 11A. When the initialization signal (INIT) is not asserted and the loop exit condition signal (PS1) is not asserted, the selection unit 13A outputs the output signal of the adder 12A to the storage unit 11A. The initial value (sInit1) is, for example, "0".

[0044] The adder 12A stores the increment value (sInc1). When the add instruction signal (EN) is asserted, the adder 12A adds the output (sCnt1) of the storage unit 11A and the increment value (sInc1). The increment value (sInc1) is, for example, "1".

[0045] The comparison unit 14A stores the maximum value (sMax1). The comparison unit 14A compares the counter value (sCnt1) with the maximum value (sMax1). When the counter value (sCnt1) reaches the maximum value (sMax1), the comparison unit 14A asserts the loop exit condition fulfillment signal (PS1). The loop exit condition fulfillment signal (PS1) is sent to the selection unit 13A and the addition unit 12B of the second loop counter 22B.

[0046] The memory unit 11B stores the counter value (sCnt2) of the loop variable of loop B. When the writeable signal WE is asserted, the memory unit 11B updates the counter value (sCnt2) based on the output signal of the selection unit 13B.

[0047] The selection unit 13B stores the initial value (sInit2). When the initialization signal (INIT) is asserted, the selection unit 13B outputs the initial value (sInit2) to the storage unit 11B. When the initialization signal (INIT) is not asserted, the selection unit 13B outputs the output signal of the adder 12B to the storage unit 11B. The initial value (sInit2) is, for example, "0".

[0048] The adder 12B stores the increment value (sInc2). When the loop exit condition signal (PS1) is asserted, the adder 12B adds the output (sCnt2) of the storage unit 11B and the increment value (sInc2). The increment value (sInc2) is, for example, "1".

[0049] The comparison unit 14B stores the maximum value (sMax2). The comparison unit 14B compares the counter value (sCnt2) with the maximum value (sMax2). When the counter value (sCnt2) reaches the maximum value (sMax2), the comparison unit 14B asserts the loop exit condition fulfillment signal (PS2). The loop exit condition fulfillment signal (PS2) is sent to the state transition controller 50.

[0050] In the counter circuit 202 of this embodiment, when the number of repetitions in loop A reaches a predetermined number, the comparison condition for the first loop counter 22A is met, a signal is sent to the second loop counter 22B instructing it to add, and the first loop counter 22A itself returns to the initial state of the loop, allowing it to move on to the next repetition. Also, when the number of repetitions in loop B reaches a predetermined number, the comparison condition for the second loop counter 22B is met, allowing it to exit the loop and move on to the next operation.

[0051] [Modified example of the third embodiment] Figure 14 is a block diagram showing the components of a counter circuit 302 of a modified example of the third embodiment. This counter circuit 302 counts the loop variables of loop A, the loop variables of loop B which is one loop outside of loop A, and the loop variables of loop C which is one loop outside of loop B. The counter circuit 302 comprises a first loop counter 22A that counts the loop variables of loop A, a second loop counter 22B that counts the loop variables of loop B, and a third loop counter 22C that counts the loop variables of loop C.

[0052] The counter 22A for the first loop is the same as in the third embodiment, so we will not repeat the explanation. The second loop counter 22B differs from the third embodiment in the following respects: The loop exit condition signal (PS2) is sent to the selection unit 13B and the addition unit 12C of the third loop counter 22C.

[0053] The selection unit 13B outputs an initial value (sInit2) to the storage unit 11B when the initialization signal (INIT) is asserted, or when both the loop A exit condition fulfillment signal (PS1) and the loop B exit condition fulfillment signal (PS2) are asserted.

[0054] The counter 22C for the third loop comprises a storage unit 11C, a selection unit 13C, an addition unit 12C, and a comparison unit 14C.

[0055] The memory unit 11C stores the counter value (sCnt3) of the loop variable of loop C. When the writeable signal WE is asserted, the memory unit 11C updates the counter value (sCnt3) based on the output signal of the selection unit 13C.

[0056] The selection unit 13C stores the initial value (sInit3). When the initialization signal (INIT) is asserted, the selection unit 13C outputs the initial value (sInit3) to the storage unit 11C. When the initialization signal (INIT) is not asserted, the selection unit 13C outputs the output signal of the adder 12C to the storage unit 11C. The initial value (sInit3) is, for example, "0".

[0057] The adder 12C stores the increment value (sInc3). When both the loop A exit condition fulfillment signal (PS1) and the loop B exit condition fulfillment signal (PS2) are asserted, the adder 12C adds the output of the storage unit 11C (sCnt3) to the increment value (sInc3). The increment value (sInc3) is, for example, "1".

[0058] The comparison unit 14C stores the maximum value (sMax3). The comparison unit 14C compares the counter value (sCnt3) with the maximum value (sMax3). When the counter value (sCnt3) reaches the maximum value (sMax3), the comparison unit 14C asserts the loop escape condition fulfillment signal (PS3). The loop escape condition fulfillment signal (PS3) is sent to the state transition controller 50.

[0059] [Fourth Embodiment] Figure 15 is a block diagram showing the components of the counter circuit 402 of the fourth embodiment. The counter circuit 402 counts a loop variable with twice the bit width of the loop. Twice the bit width is, for example, 32 bits.

[0060] The counter circuit 402 includes a lower-bit counter 32A that counts the lower bits of the loop variable, an upper-bit counter 32B that counts the upper bits of the loop variable, and a double-width determination unit 33. The double-width determination unit 33 determines whether the loop termination condition has been met based on the value of the lower-bit counter 32A and the value of the upper-bit counter 32B. The lower bits are the lower 16 bits of the 32-bit loop variable. The upper bits are the upper 16 bits of the 32-bit loop variable.

[0061] The lower bit counter 32A outputs a carry signal CR to the upper bit counter 32B when the lower bit of the loop variable exceeds its maximum value. When the upper bit counter 32B receives the carry signal CR, it increments the upper bit of the loop variable.

[0062] The lower bit counter 32A comprises a storage unit 11A, a selection unit 13A, an addition unit 12A, and a comparison unit 14A. These components are designed for 16 bits.

[0063] The upper-order bit counter 32B comprises a storage unit 11B, a selection unit 13B, an addition unit 12B, and a comparison unit 14B. These components are designed for 16 bits.

[0064] The memory unit 11A stores the counter value (sCnt1) of the lower bits of the loop variable. When the writeable signal WE is asserted, the memory unit 11A updates the counter value (sCnt1) based on the output signal of the selection unit 13A.

[0065] The selection unit 13A stores an initial value (sInit1). When the initialization signal (INIT) is asserted, the selection unit 13A outputs the initial value (sInit1) to the storage unit 11A. When the initialization signal (INIT) is not asserted, the selection unit 13A outputs the output signal of the adder 12A to the storage unit 11A. The initial value (sInit1) is, for example, "0".

[0066] The adder 12A stores the increment value (sInc1). When the add instruction signal (EN) is asserted, the adder 12A adds the output (sCnt1) of the storage unit 11A and the increment value (sInc1). The increment value (sInc1) is, for example, "1". If a carry occurs (i.e., if the added value exceeds "0xFFFF"), the adder 12A asserts the carry signal CR.

[0067] The memory unit 11B stores the counter value (sCnt2) of the upper bits of the loop variable. When the writeable signal WE is asserted, the memory unit 11B updates the counter value (sCnt2) based on the output signal of the selection unit 13B.

[0068] The selection unit 13B stores the initial value (sInit2). When the initialization signal (INIT) is asserted, the selection unit 13B outputs the initial value (sInit2) to the storage unit 11B. When the initialization signal (INIT) is not asserted, the selection unit 13B outputs the output signal of the adder 12B to the storage unit 11B. The initial value (sInit2) is, for example, "0".

[0069] The adder 12B stores the increment value (sInc2). When the carry signal CR is asserted, the adder 12B adds the output of the storage unit 11B (sCnt2) to the increment value (sInc2). The increment value (sInc2) is, for example, "1".

[0070] The double width determination unit 33 includes a comparison unit 34. The comparison unit 34 stores the maximum value (sMax). The comparison unit 14 compares a value (for example, 32 bits) obtained by using the counter value (sCnt1) from the storage unit 11A as the lower bits and the counter value (sCnt2) from the storage unit 11B as the upper bits with the maximum value (sMax). When the counter value (sCnt2) reaches the maximum value (sMax), the comparison unit 34 asserts a loop escape condition fulfillment signal (PSX). The loop escape condition fulfillment signal (PSX) is sent to the state transition controller 50. sMax2 is, for example, "0xFFFFFFFF".

[0071] [Modified version of the fourth embodiment] Figure 16 shows the configuration of a counter circuit 502 in a modified example of the fourth embodiment.

[0072] In the first mode, the counter circuit 502 counts the loop variables of the multiple loops: loop A, loop B which is one loop outside of loop A, and loop C which is one loop outside of loop B. In the second mode, it counts the loop variables of loop D which is twice the bit width.

[0073] The counter circuit 502 comprises a first counter 532A, a second counter 532B, a third counter 532C, a double width determination unit 533, and a selector 190. In Figure 16, block 800 represents the components that are executed in the second mode.

[0074] The first counter 532A counts the loop variables of loop A in the first mode, and counts the lower bits of the loop variables of loop D in the second mode.

[0075] The second counter 532B counts the loop variables of loop B in the first mode, and counts the higher bits of the loop variables of loop D in the second mode.

[0076] The third counter 532C counts the loop variables of loop C in the first mode.

[0077] In the second mode, the double-width determination unit 533 determines whether the termination condition of loop D has been met based on the value of the first counter 532A and the value of the second counter 532B. In the second mode, when the termination condition of loop D is met, the double-width determination unit 533 asserts a condition fulfillment signal EventL to the state transition controller 50.

[0078] In the first mode, the first counter 532A asserts a condition-fulfilling signal EventL to the second counter 532B when the termination condition of loop A is met.

[0079] The second counter 532B increments the loop variable of loop B when the condition satisfying signal EventL is asserted in the first mode.

[0080] In the first mode, the second counter 532B asserts a condition-fulfilling signal EventM to the third counter 532C when the termination condition of loop B is met.

[0081] The third counter 532C increments the loop variable of loop C when the condition-fulfilling signal EventL is asserted and the condition-fulfilling signal EventM is asserted in the first mode.

[0082] The third counter 532C asserts a condition-fulfilling signal EventU to the state transition controller 50 when the termination condition of loop C is met in the first mode.

[0083] The first counter 532A includes register 89A, selector 81A, register 82A, register 84A, adder 83A, selector 88, register 86A, and comparator 85A.

[0084] Register 89A stores the initial value sInit[0]. Selector 81A outputs the initial value sInit[0] when the initialization signal Init is asserted. Selector 81A outputs the initial value sInit[0] when EventL is asserted. In the first mode, when the initialization signal Init is not asserted and the mode signal mode is asserted, selector 81A outputs the counter value sCnt[0] of register 82A. In the first mode, when the initialization signal Init is not asserted and the mode signal mode is not asserted, selector 81A outputs the output of adder 83A. In the second mode, selector 81A outputs the lower 16 bits of the 32-bit output of adder 183 of the double-width determination unit 533.

[0085] Register 82A stores the output of selector 81A as the counter value sCnt[0].

[0086] Register 84A stores the increment value sInc[0]. When the add instruction signal CntEn is asserted, adder 83A adds the output of register 82A and the output of register 84A.

[0087] Selector 88 outputs the output of adder 83A when mode CmpMode is asserted. Selector 88 outputs the output of register 82A when mode CmpMode is not asserted.

[0088] Register 86A stores the maximum value sMax[0]. Comparator 85A compares the MSB of the output of selector 88 with the extended signal and the maximum value sMax[0] based on the code mode. Comparator 85A asserts the condition satisfied signal EventL when the MSB of the output of selector 88 is greater than or equal to the maximum value sMax[0].

[0089] The second counter 532B includes register 89B, selector 81B, register 82B, register 84B, adder 83B, register 86B, and comparator 85B.

[0090] Register 89B stores the initial value sInit[1]. Selector 81B outputs the initial value sInit[1] when the initialization signal Init is asserted. Selector 81B outputs the initial value sInit[1] when EventL and EventM are asserted. In the first mode, when the initialization signal Init is not asserted and the mode signal mode is asserted, selector 81B outputs the counter value sCnt[1] of register 82B. In the first mode, when the initialization signal Init is not asserted and the mode signal mode is not asserted, selector 81B outputs the output of adder 83B. In the second mode, selector 81B outputs the upper 16 bits of the 32-bit output of adder 183 of the double-width determination unit 533.

[0091] Register 82B stores the output of selector 81B as the counter value sCnt[1].

[0092] Register 84B stores the increment value sInc[1]. The adder 83B adds the output of register 82B and the output of register 84B when the add instruction signal CntEn is asserted and the condition fulfillment signal EventL is asserted.

[0093] Register 86B stores the maximum value sMax[1]. Comparator 85B compares the MSB-extended signal of the output of register 82B with the maximum value sMax[1] based on the sign mode. Comparator 85B asserts the condition satisfied signal EventM when the MSB-extended signal of the output of register 82B is greater than or equal to the maximum value sMax[1].

[0094] The third counter 532C comprises a register 89C, a selector 81C, a register 82C, a register 84C, an adder 83C, a register 86C, and a comparator 85C.

[0095] Register 89C stores the initial value sInit[2]. Selector 81C outputs the initial value sInit[2] when the initialization signal Init is asserted. Selector 81B outputs the counter value sCnt[2] of register 82C when the initialization signal Init is not asserted and the mode signal mode is asserted in the first mode. Selector 81C outputs the output of adder 83C when the initialization signal Init is not asserted and the mode signal mode is not asserted in the first mode.

[0096] Register 82C stores the output of selector 81C as the counter value sCnt[2].

[0097] Register 84C stores the increment value sInc[2]. The adder 83A adds the output of register 82C and the output of register 84C when the add instruction signal CntEn is asserted, the condition fulfillment signal EventL is asserted, and the condition fulfillment signal EventM is asserted.

[0098] Register 86C stores the maximum value sMax[2]. Comparator 85C compares the MSB-extended signal of the output of register 82C with the maximum value sMax[2] based on the sign mode. Comparator 85C asserts the condition satisfied signal EventU when the MSB-extended signal of the output of register 82C is greater than or equal to the maximum value sMax[2].

[0099] The double-width determination unit 533 comprises a register 184, an adder 183, a selector 188, a register 86, and a comparator 185.

[0100] Register 184 stores the increment value sInc[0]. In the second mode, when the add instruction signal CntEn is asserted, the adder 183 adds the output of register 184 to a value obtained by taking the lower 16 bits of the counter value sCnt[0] output from register 82A and the upper 16 bits of the counter value sCnt[1] output from register 82B.

[0101] Selector 188 outputs the output of adder 183 when mode CmpMode is asserted. When mode CmpMode is not asserted, selector 188 outputs a value where the lower 16 bits are the counter value sCnt[0] output from register 82A and the upper 16 bits are the counter value sCnt[1] output from register 82B.

[0102] Register 86 stores the maximum value sMax[0]. Comparator 185 compares the output of selector 188 with the maximum value sMax[0] based on the code mode. Comparator 185 asserts the condition satisfied signal EventL when the output of selector 188 is greater than or equal to the maximum value sMax[0].

[0103] While dedicated counter circuits offer high speed, they have the drawback of becoming large in scale when attempting to accommodate all multiple nested loop descriptions. In this embodiment, by linking multiple dedicated counter circuits, it is possible to implement nested counter circuits even when, for example, a 32-bit counter circuit is required in all of the triple loop descriptions.

[0104] Compared to a scenario where all three dedicated counter circuits are 32-bit, a 16-bit counter circuit is sufficient for many loop descriptions. Therefore, this embodiment prevents increased delay and enables high-speed operation. Furthermore, this embodiment avoids the increased area caused by providing numerous dedicated counter circuits and wiring switches for connecting the counter circuits to the programmable logic.

[0105] Furthermore, if a dedicated counter circuit only matches a portion of a multi-loop description (for example, only the inner loop description), the dedicated counter circuit may be used for the relevant portion, while the counter circuit for the unmatched portion may be implemented by combining existing computational resources such as PE or LUT.

[0106] [Fifth Embodiment] Figure 17 shows the counter circuit, state transition controller, and processing element array of the fifth embodiment.

[0107] The counter circuit 502 is positioned adjacent to the state transition controller 50. The counter circuit 502 outputs loop escape condition signals PS1, PS2, PS3, and PX to the state transition controller 50.

[0108] The state transition controller 50 includes a selector 53 and a state specification unit 52. Selector 53 selects the signal to be used for determination from multiple loop escape condition fulfillment signals PS1, PS2, PS3, and PX.

[0109] The state specification unit 52 determines the next state and the data path context corresponding to each state, according to the selected signal.

[0110] By positioning the counter circuit 502 adjacent to the state transition controller 50, the loop escape condition signals PS1, PS2, PS3, and PX can be sent directly to the state transition controller 50 without passing through the processing element array 51. This reduces the delay time and enables high-speed operation.

[0111] On the other hand, the process of referencing the value of the loop variable by the counter circuit 502 within the loop includes processes that are performed only when the loop exit condition is met, and processes that are performed while the loop exit condition is not met. Depending on how the program is written, the value referenced at this time may be the value before addition or the value after addition.

[0112] In this embodiment, the output S1 of the storage unit 11A and the output A1 of the adder 12 of the first counter 532A are output to the processing element array 51. The processing element array 51 can utilize both the output S1 of the storage unit 11A and the output A1 of the adder 12.

[0113] The second counter 532B and the third counter 532C may also output the output of the storage unit and the output of the adder unit to the processing element array 51.

[0114] [Modification 1 of the 5th embodiment] Figure 18 shows a counter circuit, state transition controller, and processing element array of a modified example 1 of the fifth embodiment.

[0115] The first counter circuit 602 and the second counter circuit 702 work together to handle nested loops.

[0116] The first counter circuit 602 and the second counter circuit 702 can handle multiple loops with 16-bit variables, but only single loops with 32-bit variables. By linking the first counter circuit 602 and the second counter circuit 702, it is possible to support multiple loops.

[0117] The first counter circuit 602 counts the loop variables of a multi-loop consisting of loop A, loop B which is one loop outside of loop A, and loop C which is one loop outside of loop B, in the first mode. The second counter circuit 702 counts the loop variables of a multi-loop consisting of loop D, loop E which is one loop outside of loop D, and loop F which is one loop outside of loop E, in the first mode.

[0118] The first counter circuit 602 counts loop variables with twice the bit width of the inner loop G in the second mode. The second counter circuit 702 counts loop variables with twice the bit width of the outer loop H of loop G in the second mode.

[0119] The first counter circuit 602 includes a first counter 132A, a second counter 132B, a third counter 132C, and a double width determination unit 133.

[0120] The first counter 132A counts the loop variables of loop A in the first mode, and counts the lower bits of the loop variables of loop G which are twice the bit width in the second mode.

[0121] The second counter 132B counts the loop variables of loop B in the first mode, and counts the higher bits of the loop variables of loop G which are twice the bit width in the second mode.

[0122] The third counter 132C counts the loop variables of loop C in the first mode.

[0123] In the first mode, the first counter 132A outputs a condition-fulfilled signal PS1A to the second counter 132B when the termination condition of loop A is met.

[0124] In the first mode, the second counter 132B increments the loop variable of loop B when it receives the condition fulfillment signal PS1A. In the first mode, the second counter 132B outputs the condition fulfillment signal PS2A to the third counter 132C when the termination condition of loop B is met.

[0125] In the first mode, the third counter 132C increments the loop variable of loop C when it receives the condition fulfillment signal PS2A. In the first mode, the third counter 132C outputs the condition fulfillment signal PS3A to the state transition controller 50 when the termination condition of loop C is met.

[0126] In the second mode, the first counter 132A outputs a condition-fulfilled signal PS1A to the second counter 132B when the lower bit of the loop variable of loop G exceeds its maximum value.

[0127] In the second mode, when the condition-fulfilling signal PS1A is received, the second counter 132B increments the higher-order bit of the loop variable of loop G.

[0128] In the second mode, the double-width determination unit 133 determines whether the termination condition of loop G has been met based on the value of the first counter 132A and the value of the second counter 132B, and outputs a condition-fulfilled signal PSX when the termination condition of loop G has been met.

[0129] The second counter circuit 702 includes a first counter 232A, a second counter 232B, a third counter 232C, and a double width determination unit 233.

[0130] The first counter 232A counts the loop variables of loop D in the first mode, and in the second mode, it counts the lower bits of the loop variables of loop H that are twice the bit width.

[0131] The second counter 232B counts the loop variables of loop E in the first mode, and counts the higher bits of the loop variables of loop H that are twice the bit width in the second mode.

[0132] The third counter 232C counts the loop variables of loop F in the first mode.

[0133] In the first mode, the first counter 232A outputs a condition-fulfilled signal PS1B to the second counter 232B when the termination condition of loop D is met.

[0134] In the first mode, the second counter 232B increments the loop variable of loop E when it receives the condition fulfillment signal PS1B. In the first mode, the second counter 232B outputs the condition fulfillment signal PS2B to the third counter 232C when the termination condition of loop E is met.

[0135] In the first mode, the third counter 232C increments the loop variable of loop F when it receives the condition fulfillment signal PS2B. In the first mode, the third counter 232C outputs the condition fulfillment signal PS3B to the state transition controller 50 when the termination condition of loop F is met.

[0136] In the second mode, when the first counter 232A receives the condition-fulfilled signal PSX, it increments the lower bit of the loop variable of loop H.

[0137] In the second mode, the first counter 232A outputs a condition-fulfilled signal PS1B to the second counter 232B when the lower bit of the loop variable of loop H exceeds its maximum value.

[0138] In the second mode, when the condition-fulfilled signal PS1B is received, the second counter 232B increments the higher-order bit of the loop variable of loop H.

[0139] In the second mode, the double-width determination unit 233 determines whether the loop H termination condition has been met based on the value of the first counter 232A and the value of the second counter 232B, and outputs a condition-fulfilled signal PSY when the loop H termination condition has been met.

[0140] [Modification 2 of the 5th embodiment] Figure 19 shows a counter circuit, state transition controller, and processing element array of a modified example 2 of the fifth embodiment.

[0141] In the second mode, the first counter circuit 602 counts a loop variable with twice the bit width of loop A.

[0142] The second counter circuit 702, in the second mode, counts a loop variable that is twice the bit width of loop B, which is one loop outside of loop A.

[0143] The first counter circuit 602 outputs a loop exit condition signal PSX to the processing element array 51 when the termination condition of loop A is met.

[0144] At least one processing element PE of the processing element array 51 performs a logic operation based on the loop escape condition signal PSX, and outputs an increment instruction signal to the second counter circuit 702 when the result of the logic operation satisfies a predetermined condition.

[0145] The second counter circuit 702 increments the loop variable of loop B when it receives an increment instruction signal. The second counter circuit 702 outputs a loop exit condition fulfillment signal PSY to the state transition controller 50 when the termination condition of loop B is met.

[0146] [Sixth Embodiment] Figure 20 is a diagram showing the configuration of the dynamic reconfiguration processor according to the sixth embodiment.

[0147] The dynamic reconfiguration processor comprises first counter circuits 2A, 2B, and 2C, and second counter circuits 20A, 20B, and 20C.

[0148] The second counter circuits 20A, 20B, and 20C are copy counters of the first counter circuits 2A, 2B, and 2C.

[0149] The first counter circuit 2A counts variable A. The first counter circuit 2B counts variable B. The first counter circuit 2C counts variable C. The second counter circuit 20A counts variable A. The second counter circuit 20B counts variable B. The second counter circuit 20C counts variable C.

[0150] The first counter circuit 2A and the second counter circuit 20A can both count variable A simultaneously, or one of them can count variable B simultaneously, or one of them can count variable B simultaneously, or one of them can count variable C simultaneously, or one of them can count variable C simultaneously, or one of them can count variable C simultaneously, or one of them can count variable B simultaneously, or the first counter circuit 2C and the second counter circuit 20C can both count variable C simultaneously, or one of them can count variable C simultaneously, or one of them can count variable B simultaneously, or one of them can count variable B simultaneously, or the first counter circuit 2C and the second counter circuit 20C can count variable C simultaneously, or one of them can count variable C simultaneously, or one of them can count variable B.

[0151] The first counter circuits 2A, 2B, and 2C are located near the state transition controller 50. The outputs of the first counter circuits 2A, 2B, and 2C are sent to the state transition controller 50 and used to control the dynamic reconfiguration processor.

[0152] The second counter circuits 20A, 20B, and 20C are located near the memories VMEM and HMEM. Since the memories VMEM and HMEM are located far from the first counter circuits 2A, 2B, 2C and the state transition controller 50, supplying loop escape condition signals or variable counter values ​​from the first counter circuits 2A, 2B, and 2C to VMEM and HMEM requires wiring through the PE array 51, resulting in a large delay.

[0153] The second counter circuits 20A, 20B, and 20C can reduce delay by supplying loop escape condition signals or variable counter values ​​to nearby memories VMEM and HMEM.

[0154] In the example shown in Figure 20, no counter circuit is placed in the upper left corner, but a second counter circuit may be placed there.

[0155] [Modified version of the sixth embodiment] The exit condition fulfillment signal PS can be used to enable processing that should only be performed when the loop exit condition is met. On the other hand, for processing that should be performed while the loop exit condition is not met, the exit condition fulfillment signal PS needs to be inverted. For example, a signal to enable the write function of a register may be asserted while the loop exit condition is not met.

[0156] While it is conceivable to invert the escape condition fulfillment signal PS within the processing element array 51, this would require the use of an arithmetic unit and increase the delay. These problems can be avoided by having the counter circuit output a signal that is an inverted version of the escape condition fulfillment signal PS.

[0157] Figure 21 is a block diagram showing the configuration of a modified counter circuit 2X of the sixth embodiment. The difference between this counter circuit 2X and the counter circuit 2 of the first embodiment is that the counter circuit 2X includes an inversion unit 114.

[0158] The inverting unit 114 generates and outputs an inverted loop escape condition signal / PS by inverting the loop escape condition signal PS. The inverting unit 114 is configured, for example, by an inverter.

[0159] Figure 22 shows an example of a program that utilizes the escape condition signal PS and the inverted escape condition signal / PS.

[0160] For writing to the array within the inner loop, to enable writing when the inner loop has not been exited, the inverted exit condition signal PS can be used as the signal to enable writing to the array register. This eliminates the need for a separate general-purpose arithmetic unit for signal inversion between the counter circuit and memory.

[0161] For writing to array2 after exiting the inner loop, the exit condition fulfillment signal PS can be used as a signal to enable writing to the register for array2.

[0162] [Seventh Embodiment] Counter circuits have the following applications: Counter circuits can also be used in operations inside loops. An accumulator, which adds a value supplied from another source to a certain register each time, can also be constructed using a processing element PE. However, this requires programmable wiring connections between the register and the adder, forming a loop with the register as both the starting and ending point, which results in a problem of large delays.

[0163] Figure 23 is a block diagram showing the components of the counter circuit 72 of the seventh embodiment. The counter circuit 72 counts an accumulator variable whose increment value is repeatedly added within the loop.

[0164] The counter circuit 72, like the counter circuit 2 described in the first embodiment, includes a storage unit 11, a selection unit 134, an addition unit 12, and a comparison unit 14.

[0165] Figure 24 shows an example of a program that utilizes an accumulator. In the program shown in Figure 24, the accumulator variable `acum` performs self-referential calculations (accumulation) within the `for` loop. For example, such an accumulator is necessary when calculating the average of pixel values ​​within an image region.

[0166] The increment value α input to the adder 12 can also be supplied from the processing element PE. As a result, the processing circuit inside the loop described above can be made into a fixed circuit. By inserting a pipelined register in the part where the increment value α is input, the overall delay can be reduced.

[0167] By making the adder in the addition unit 12 compatible with floating-point numbers, it can also be used as a floating-point accumulator. Since floating-point arithmetic generally has a greater delay than integer arithmetic, the delay can be reduced by using the counter circuit 72.

[0168] [Eighth Embodiment] In image processing, the processing area is moved by shifting the position of a point on a two-dimensional plane using double nested loop descriptions in the x and y directions. In AI convolution processing, processing in the z direction (channel direction) may also be added. When processing such image processing and AI convolution using dedicated logic or programmable logic, pipelined circuits can be considered as a way to achieve high throughput.

[0169] However, as the delay in the pipeline circuit is reduced and speed is increased, a problem arises: the counter circuit becomes the critical path (the path with the maximum delay, i.e., the bottleneck in increasing the operating frequency). This is especially true when loops are nested and multiplexed, which increases the likelihood of the counter circuit becoming the critical path.

[0170] These problems can be solved by making the counter circuit a dedicated circuit as described in the above embodiment.

[0171] This embodiment describes a dynamically reconfigurable processor, its compilation method, and the synthesis of pipeline circuits, and then presents a method for mapping counter circuits and an example thereof.

[0172] The compiler of this embodiment generates code that is executed by a dynamically reconfigured processor equipped with the counter circuit described in the above embodiment.

[0173] Figure 25 is a diagram showing the compiler's configuration. The compiler comprises a behavioral synthesis unit 900, a technology mapping unit 904, a placement and routing unit 905, and a code generation unit 906.

[0174] The operation synthesis unit 900 generates a state transition machine (FSM) to be assigned to the state transition controller 50, and a data path context, which is a circuit corresponding to each state.

[0175] The behavior synthesis unit 900 generates a state transition machine (FSM) and data path contexts corresponding to each state of the state transition machine from a program written in a behavior description language such as C, a circuit library including delay information, and synthesis constraints such as operating frequency and circuit size.

[0176] The motion synthesis unit 900 extracts the dedicated counter circuit described in the above embodiment during data flow analysis. Since the dedicated counter circuit can be considered in the scheduling of motion synthesis, the management of the number of resources and delays of the counter circuit becomes easier.

[0177] The technology mapping unit 904 performs optimization such as logic synthesis and mapping processing according to the operation bit width of the PE.

[0178] The placement and routing unit 905 determines the locations of the arithmetic units, registers, and memory, and connects the programmable wiring.

[0179] The code generation unit 906 generates configuration code for the state transition controller (STC) and configuration code for the PE array.

[0180] Figure 26 shows an example of a state transition machine and a data path context generated by the operation synthesis unit 900.

[0181] A dynamic reconstruction processor, by leveraging circuit switching, can run only the necessary parts as contexts without mixing circuits and initialization circuits for multiple conditions. For example, in an image processing example, the dynamic reconstruction processor switches between the pipeline circuit for image processing in the inner loop, the register initialization circuit for setting the dedicated counter circuit, other pre-processing, and post-processing. These are assigned to each data path context of the dynamic reconstruction processor, and the state transition machine switches the data path context according to the image region.

[0182] Figure 27 shows an example of a pipeline generated during motion synthesis. The operation synthesis unit 900 pipelines the processing inside the innermost loop to improve processing throughput. After generating a data flow graph, the operation synthesis unit 900 constrains and schedules resources such as arithmetic units for pipelineization. At this time, to avoid data hazards, the operation synthesis unit 900 performs register forwarding and other operations, and then folds multiple states into a pipeline circuit for pipelineization and synthesis.

[0183] Figure 27 shows an example where a 4-state circuit is folded into a 1-state, 4-stage circuit and combined into a single context, thereby increasing throughput by four times.

[0184] As mentioned earlier, the throughput of processing within a loop can be improved by pipelining. Pipelining reduces latency by inserting registers or flip-flops during the calculation process.

[0185] However, the loop descriptions of the inner and outer loops cannot be pipelined, which often becomes a performance bottleneck. In particular, in the case of nested loops, it becomes difficult to increase the operating frequency because multiple counter circuits need to be coordinated. Therefore, the operation synthesis unit 900 maps the description of the multiple loops to a dedicated counter circuit corresponding to the multiple loops described in the above embodiment.

[0186] Figure 28 shows an example of a pipeline circuit in which the loop repeats four times.

[0187] A pipeline circuit requires cycles for the prologue, which introduces data, and cycles for the epilogue, which exits the data. In the case of a 1-state, 4-stage pipeline circuit, as shown in Figure 28, three cycles are required for the prologue and three cycles for the epilogue.

[0188] Figure 29 illustrates the overhead of pipeline implementation. In a double-nested loop, if only the inner loop A is pipelined, as shown in Figure 29, another loop exists outside the 1-state, 4-stage pipeline circuit. Each time the outer loop B is executed, the time of the prologue and epilogue of the inner loop A creates a gap, resulting in overhead in the execution cycle.

[0189] Figure 30 illustrates an example of reducing pipeline overhead. The operation synthesis unit 900 generates a data path context in which the loop variable of loop A is incremented in the first loop counter 22A after the completion of the first stage in each iteration of loop A. The operation synthesis unit 900 generates a data path context in which the loop variable of loop B is incremented in the second loop counter 22B after the completion of the first stage in the last iteration of loop A.

[0190] As a result, in each iteration of loop B, after the completion of the first stage of loop A at its kth iteration, the first stage of loop A at its (k+1)th iteration begins. After the completion of the first stage of loop A at its sth iteration, the first stage of loop A at its 1st iteration begins at its (s+1)th iteration.

[0191] As shown in Figure 30, the outer loop can be enclosed within the inner loop to create a single loop. As a result, the overhead associated with the prologue and epilogue of the inner loop, which occurs each time the outer loop completes a cycle, can be reduced. This allows for a reduction in the overall number of cycles.

[0192] Furthermore, in the synthesis flow, circuits corresponding to counter circuits may be extracted during technology mapping and mapped to dedicated counter circuits. This may involve determining whether a circuit matches a dedicated counter circuit, dividing a multiple nested loop description into multiple dedicated counter circuits, and connecting programmable wiring between them.

[0193] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0194] 1 Programmable logic, 2,2A,2B,2C,2X,20A,20B,20C,72,152,163,202,203,302,402,502,602,702 Counter circuits, 11,11A,11B,11C Memory units, 12,12A,12B,12C Adding units, 13,13A,13B,13C,134 Selection units, 14,14A,14B,14C,34,64 Comparison units, 22A First loop counter, 22B Second loop counter, 22C Third loop counter, 32A Lower bit counter, 32B Upper bit counter, 33,133,233,533 Double width determination unit, 50 State transition controller, 51,182 Array, 52 State specification unit, 53, 81A, 81B, 81C, 88, 188, 190, 381 Selector, 82A, 82B, 82C, 84A, 84B, 84C, 86, 86A, 86B, 86C, 89A, 89B, 89C, 93, 184, 382, ​​384, 386 Register, 83A, 83B, 83C, 183, 383 Adder, 85A, 85B, 85C, 185 Comparator, 91 Instruction memory, 92 Arithmetic unit, 114 Inverter unit, 132A, 232A, 532A First counter, 132B, 232B, 532B Second counter, 132C, 232C, 532C Third counter, 161 Processor, 900 Operation synthesis unit, 904 Technology mapping unit, 905 placement and routing unit, 906 code generation unit, HMEM, VMEM memory, MUL multiplier, PE processing element, SW, SWI, SWO switch.

Claims

1. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The aforementioned counter circuit is It comprises a selection unit, a storage unit, an addition unit, and a comparison unit. The selection unit selects and outputs either the initial value or the output of the addition unit. The storage unit stores the output of the selection unit, The addition unit adds the output of the storage unit and the increment value, The comparison unit is a processor that compares the output of the addition unit with the maximum value and outputs a signal representing the comparison result.

2. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The counter circuit counts the loop variables in the loop description, The aforementioned counter circuit is A first counter that counts the loop variables of the first loop, A second counter that counts the loop variables of a second loop that is one loop outside the first loop, The first counter outputs a first signal to the second counter when the termination condition of the first loop is met. The second counter is a processor that, upon receiving the first signal, increments the loop variable of the second loop.

3. The aforementioned processor, The system further comprises a state transition controller that controls the state transitions of the processor by controlling the programmable logic and the counter circuit, The processor according to claim 2, wherein the second counter outputs a second signal to the state transition controller when the termination condition of the second loop is met.

4. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The counter circuit counts the loop variables in the loop description, The aforementioned counter circuit is A first counter that counts the lower bits of the loop variable, A second counter that counts the higher bits of the aforementioned loop variable, The system includes a double-width determination unit that determines whether the loop termination condition has been met based on the value of the first counter and the value of the second counter, The first counter outputs a carry signal to the second counter when the lower bit of the loop variable exceeds its maximum value. The second counter is a processor that, upon receiving the carry signal, increments the higher bit of the loop variable.

5. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The counter circuit counts the loop variables in the loop description, The counter circuit counts the loop variables of a multi-loop including the first loop and the second loop one loop outside the first loop in the first mode, and in the second mode counts the loop variables of the third loop with twice the bit width. A first counter that counts the loop variables of the first loop in the first mode, and counts the lower bits of the loop variables of the third loop in the second mode, A second counter that counts the loop variables of the second loop in the first mode, and counts the upper bits of the loop variables of the third loop in the second mode, The second mode includes a double-width determination unit that determines whether the termination condition of the third loop has been met based on the value of the first counter and the value of the second counter, The first counter outputs a first signal to the second counter when the termination condition of the first loop is met in the first mode. In the first mode, when the second counter receives the first signal, it increments the loop variable of the second loop. In the second mode, the first counter outputs the first signal to the second counter when the lower bit of the loop variable of the third loop exceeds the maximum value. The second counter is a processor that, in the second mode, increments the upper bits of the loop variable of the third loop when it receives the first signal.

6. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The counter circuit counts the loop variables in the loop description, The at least one counter circuit comprises a first counter circuit and a second counter circuit, The first counter circuit counts the loop variables of a multi-loop including the first loop and the second loop one loop outside the first loop in the first mode, and the second counter circuit counts the loop variables of a multi-loop including the third loop and the fourth loop one loop outside the third loop in the first mode. The first counter circuit counts a loop variable with twice the bit width of the fifth loop inside the double loop in the second mode, and the second counter circuit counts a loop variable with twice the bit width of the sixth loop one loop outside the fifth loop in the second mode. The first counter circuit is, A first counter that counts the loop variables of the first loop in the first mode, and counts the lower bits of the loop variables of the fifth loop in the second mode, A second counter that counts the loop variables of the second loop in the first mode, and counts the upper bits of the loop variables of the fifth loop in the second mode, In the second mode, the system includes a double-width determination unit that determines whether the termination condition for the fifth loop has been met based on the value of the first counter and the value of the second counter, and outputs a fifth loop condition fulfillment signal when the termination condition for the fifth loop has been met. In the first mode, the first counter outputs a first condition satisfied signal to the second counter when the termination condition of the first loop is met. In the first mode, when the second counter receives the signal indicating that the first condition has been met, it increments the loop variable of the second loop. In the second mode, the first counter outputs a first condition satisfied signal to the second counter when the lower bit of the loop variable of the fifth loop exceeds the maximum value. In the second mode, when the second counter receives the signal that the first condition is met, it increments the upper bit of the loop variable of the fifth loop. The second counter circuit described above is: A first counter that counts the loop variables of the third loop in the first mode, and counts the lower bits of the loop variables of the sixth loop in the second mode, A second counter that counts the variables of the fourth loop in the first mode, and counts the upper bits of the loop variables of the sixth loop in the second mode, In the second mode, the system includes a double-width determination unit that determines whether the termination condition of the sixth loop has been met based on the value of the first counter and the value of the second counter, In the first mode, the first counter outputs a first condition satisfied signal to the second counter when the termination condition of the third loop is met. In the first mode, when the second counter receives the signal that the first condition is met, it increments the variable in the fourth loop. In the second mode, when the first counter receives the signal indicating that the fifth loop condition is met, it increments the lower bit of the loop variable of the sixth loop. In the second mode, the first counter outputs a first condition satisfied signal to the second counter when the lower bit of the loop variable of the sixth loop exceeds the maximum value. The second counter is a processor that, in the second mode, increments the upper bits of the loop variable of the sixth loop when it receives the signal that the first condition is met.

7. An array comprising a plurality of programmable logics, It comprises at least one dedicated counter circuit for counting variables that are repeatedly modified, The counter circuit counts the loop variables in the loop description, The at least one counter circuit is, A first counter circuit that counts the loop variables of the first loop, The system includes a second counter circuit that counts the loop variables of a second loop located one loop outside the first loop, The first counter circuit outputs a first signal to the programmable logic when the termination condition of the first loop is met. The programmable logic performs a logical operation based on the first signal, and outputs an increment instruction signal to the second counter circuit when the result of the logical operation satisfies a predetermined condition. The second counter circuit is a processor that, upon receiving the increment instruction signal, increments the loop variable of the second loop.

8. The aforementioned processor, The system further comprises a state transition controller that controls the state transitions of the processor by controlling the programmable logic and the counter circuit, The processor according to claim 7, wherein the second counter circuit outputs a second signal to the state transition controller when the termination condition of the second loop is met.

9. A processor, An array consisting of multiple programmable logics, A dedicated counter circuit for counting variables that are repeatedly modified, Memory and The system includes a state transition controller that controls the state transitions of the processor by controlling the programmable logic and the counter circuit, The at least one counter circuit is, A first counter circuit is located near the state transition controller and counts a first variable, A processor comprising: a second counter circuit located near the memory and counting the first variable.

10. The aforementioned counter circuit is The processor according to claim 1, further comprising an inversion unit that generates an inverted signal of the signal representing the comparison result.

11. A compiler that generates code to be executed by a dynamically reconfigured processor, The aforementioned dynamic reconfiguration processor is An array consisting of multiple programmable processors, A first counter that counts the loop variables of the first loop, A second counter that counts the loop variables of the second loop, which is one loop outside the first loop, The system comprises a programmable processor, a state transition controller that controls the state transitions of the dynamic reconfiguration processor by controlling the first counter and the second counter, The aforementioned compiler, A compiler comprising: an operation synthesis unit that pipelines the processing inside the first loop into multiple stages, generates a data path context that, in each iteration of the first loop, increments the loop variable of the first loop in the first counter after the completion of the first stage, and increments the loop variable of the second loop in the second counter after the completion of the first stage in the last iteration of the first loop.

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