Quantum error correction decoding method, apparatus, device, and chip based on neural networks

Abstract

A neural network-based quantum error correction decoding method, device, equipment, and chip, relating to the fields of artificial intelligence and quantum technology, includes the steps of: acquiring error syndrome information by performing syndrome measurements on a quantum circuit (1010); extracting feature information from the error syndrome information using a neural network decoder (1020); performing a decoding process on the feature information using the neural network decoder to obtain a decoding result (1030); and determining error result information based on the decoding result (1040). The method significantly improves decoding performance, shortens decoding time, and is relatively easy to implement in hardware engineering.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with an application number of 202211468927.9, titled "Quantum Error Correction Decoding Method, Apparatus, Equipment, and Chip Based on Neural Network", which was filed with the Chinese Patent Office on November 22, 2022, and all the contents of the Chinese patent application are incorporated herein by reference.

[0002] Embodiments of this application relate to the fields of artificial intelligence and quantum technology, and in particular, to a quantum error correction decoding method, apparatus, equipment, and chip based on neural network.

Background Art

[0003] All operation processes in actual quantum computing, including quantum gates and quantum measurements, are accompanied by noise. That is, the circuit itself used for quantum error correction also contains noise.

[0004] In fault - tolerant quantum error correction, syndrome measurement is performed on the quantum circuit to obtain the corresponding error syndrome information, and then, by decoding the error syndrome information, the quantum bit where an error occurs in the quantum circuit and its corresponding error type are determined. In related technologies, several schemes for decoding error syndrome information are provided. For example, decoding schemes based on MWPM (Minimum Weight Perfect Matching), RG (Renormalization Group) algorithm, CA (Cellular Automaton), and neural network are included. Currently, the decoding scheme based on neural network still has some drawbacks in decoding ability.

Summary of the Invention

[0005] Embodiments of the present application provide a quantum error correction decoding method, apparatus, device, and chip based on a neural network. The technical solution is as follows:

[0006] According to one embodiment of the present invention, a quantum error correction decoding method based on a neural network is provided, the method being executed by a control device, the method comprising: acquiring error syndrome information obtained by performing a syndrome measurement on a quantum circuit; extracting feature information from the error syndrome information using a neural network decoder; performing a decoding process on the feature information using the neural network decoder to obtain a decoding result; and determining error result information of the quantum circuit based on the decoding result.

[0007] According to one embodiment of the present invention, a quantum error correction decoding device based on a neural network is provided, the device is A syndrome acquisition module configured to acquire error syndrome information obtained by performing syndrome measurements on a quantum circuit, A feature extraction module configured to extract feature information from the error syndrome information using a neural network decoder, A feature decoding module configured to perform decoding processing on the feature information using the neural network decoder and obtain a decoding result, The system includes a result determination module configured to determine error result information of the quantum circuit based on the decoding result.

[0008] According to one embodiment of the present invention, a computer device comprising a processor and memory is provided, wherein a computer program is stored in the memory, and the above method is realized by loading and executing the computer program by the processor.

[0009] According to one embodiment of the present invention, a computer-readable storage medium is provided in which a computer program is stored, and the above method is realized by loading and executing the computer program by a processor.

[0010] According to one embodiment of the present invention, a computer program product including a computer program is provided, wherein the computer program is loaded and executed by a processor to realize the above method.

[0011] According to one embodiment of the present invention, a chip is provided on which a neural network decoder is located, the neural network decoder is used to implement the above method. [Effects of the Invention]

[0012] The embodiment of the present invention provides an error correction decoding scheme based on a multi-task learning neural network model. It extracts corresponding feature information from input error syndrome information using a neural network decoder, decodes this feature information using another neural network decoder, outputs a decoded result of a noise-decomposed local information distribution, and then determines error result information based on the decoding result. Compared to schemes employing multiple neural network decoders, the scheme of the present invention can accurately determine error result information using a single neural network decoder. This significantly improves decoding performance and reduces decoding time without increasing algorithmic complexity, while maintaining scalability. Furthermore, hardware implementation in engineering is relatively easy. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic diagram of the rotating surface reference numerals shown in one embodiment of the present application. [Figure 2] This is a schematic diagram illustrating the occurrence of an error in the surface reference numerals shown in one embodiment of the present application. [Figure 3]Schematic diagram of comparison of decoding performance and decoding time of several decoding schemes shown in one embodiment of the present application. [Figure 4] Schematic diagram of an application scenario of a scheme according to one embodiment of the present application. [Figure 5] Schematic diagram of an error correction decoding process according to an application scenario of the scheme shown in FIG. 4. [Figure 6] Schematic diagram of a simplified expression corresponding to a syndrome point in a rotation surface code according to one embodiment of the present application. [Figure 7] Schematic diagram of a syndrome measurement circuit according to one embodiment of the present application. [Figure 8] Schematic diagram of a three-dimensional syndrome distribution according to one embodiment of the present application. [Figure 9] Architectural diagram of decoding using multiple neural network models according to one embodiment of the present application. [Figure 10] Flowchart of a neural network-based quantum error correction decoding method according to one embodiment of the present application. [Figure 11] Architectural diagram of a neural network decoder based on multi-task learning according to one embodiment of the present application. [Figure 12] Schematic diagram of a decoding process of a first type of decoder according to one embodiment of the present application. [Figure 13] Schematic diagram of a decoding process of a second type of decoder according to one embodiment of the present application. [Figure 14] Schematic diagram of a decoding process of a second type of decoder according to another embodiment of the present application. [Figure 15] Schematic diagram of local feature extraction mapping by a feature extraction sub-network according to one embodiment of the present application. [Figure 16] Schematic diagram of correlated noise generated by a syndrome measurement circuit according to one embodiment of the present application. [Figure 17] Schematic diagram of the division of a physical quantum bit according to one embodiment of the present application. [Figure 18]Schematic diagram of the splitting of a physical qubit according to another embodiment of the present application. [Figure 19] Schematic diagram of a multi-core architecture according to one embodiment of the present application. [Figure 20] Schematic diagram of experimental result data corresponding to a first error decomposition method according to one embodiment of the present application. [Figure 21] Schematic diagram of chip placement according to one embodiment of the present application. [Figure 22] Schematic diagram of experimental result data corresponding to a first error decomposition method according to another embodiment of the present application. [Figure 23] Schematic diagram of experimental result data corresponding to a second error decomposition method according to one embodiment of the present application. [Figure 24] Block diagram of a quantum error correction decoder based on a neural network according to one embodiment of the present application. [Figure 25] Schematic diagram of the configuration of a computer device according to one embodiment of the present application.

Mode for Carrying Out the Invention

[0014] Before describing the embodiments of the present application, first, some terms used in the present application will be described.

[0015] 1. Quantum Computation (QC): A method of rapidly performing specific computational tasks by utilizing the superposition and entanglement properties of quantum states.

[0016] 2. Quantum Error Correction (QEC) code: A method of encoding by mapping a quantum state into a subspace within the Hilbert space of a multi-body quantum system. Quantum noise transitions the encoded quantum state to another subspace. By continuously observing the location space of the quantum state (syndrome extraction), the quantum noise can be evaluated and corrected without interfering with the encoded quantum state, thereby preventing the encoded quantum state from being interfered with by quantum noise. Specifically, one TIFF0007848400000001.tif6170 A quantum error correction code represents encoding k logical qubits in n physical qubits, and any single qubit that results in any TIFF0007848400000002.tif5 is used to correct 170 errors.

[0017] 3. Data quantum state: This is the quantum state of a data qubit used to store quantum information during quantum computation.

[0018] 4. Stabilizer generator: Also called parity check operator. The occurrence of quantum noise (error) causes a change in the eigenvalue of some stabilizer generator, and therefore, quantum error correction can be performed based on this information.

[0019] 5. Stabilizer group: The stabilizer group is a group generated by stabilizer generators. For example, the abelian group generated by stabilizer generators is called the stabilizer generator group. If there are k stabilizer generators, the stabilizer group will have 2 k It contains n elements, and this is an Abelian group.

[0020] 6. Error Syndrome: In the absence of errors, the eigenvalues ​​of the stabilizer generators are 0. When quantum noise occurs, the eigenvalues ​​of the stabilizer generators (parity check operators) of several error correction codes that anticommutate with the error become 1. The bit sequence consisting of these 0 and 1 syndrome bits is called the error syndrome.

[0021] 7. Topological quantum code: A special type of quantum error correction code. The qubits of this type of error correction code are distributed in a lattice-like array of more than two dimensions. The lattice constitutes a discrete structure of a higher-dimensional manifold. In this case, the stabilizer generators of the error correction code are defined on a limited number of geometrically adjacent qubits, making them geometrically local and physically easily measurable. The qubits on which the logical operators of this type of error correction code act constitute a kind of topologically nontrivial geometric object on the lattice-like manifold.

[0022] 8. Surface Code: A surface code is a type of topological quantum error correction code defined on a two-dimensional manifold. Its stabilizer generator is typically supported by four qubits (two qubits at the boundary), and its logical operators are non-trivial chains that traverse the array in a band-like manner. The specific two-dimensional structure of a surface code (7x7, containing a total of 97 physical qubits, including 49 data qubits and 48 auxiliary qubits, and capable of correcting any error occurring in two qubits) is shown in Figure 1, where the black circles 11 represent data qubits used in quantum computation, and the crosses 12 represent auxiliary qubits. The auxiliary qubits are initially... The TIFF0007848400000003.tif7170 file is prepared. The diagonally filled blocks and the white filled blocks represent two types of stabilizer generators for detecting Z errors and X errors, respectively.

[0023] 9. Surface code scale TIFF0007848400000004.tif4170: This is one-quarter of the perimeter of the surface code array. Surface code array in Figure 1 The qubit code is TIFF0007848400000005.tif4170, and it contains a total of 97 physical qubits, including 49 data qubits and 48 auxiliary qubits.

[0024] 10. X and Z errors: These are errors caused by the Pauli X and Pauli Z operators that randomly occur in the quantum state of a physical qubit. According to quantum error correction theory, if an error correction code can correct X and Z errors, it can correct errors occurring in any single qubit.

[0025] 11. Fault-tolerant Quantum Error Correction (FTQEC): All operational processes in actual quantum computing, including quantum gates and quantum measurements, are accompanied by noise. In other words, the circuits used for quantum error correction themselves also contain noise. Fault-tolerant quantum error correction refers to a method that, through clever design, can correct errors even when using correction circuits that contain noise, achieving the goal of correcting errors and preventing the spread of errors over time.

[0026] 12. Fault-Tolerant Quantum Computation (FTQC): In the process of quantum computing, any physical operation, including the quantum error correction circuit itself and qubit measurements, is accompanied by noise. Assuming that classical operations (e.g., instruction input, decoding of error correction codes) are noise-free, fault-tolerant quantum computing is a technical solution for effectively controlling and correcting errors in the process of performing quantum computing using noisy qubits by rationally designing quantum error correction schemes and performing quantum gate operations on encoded logical quantum states in a specific manner.

[0027] 13. Physical qubits: These are qubits that are realized using actual physical devices.

[0028] 14. Logical qubit: A mathematical degree of freedom in a Hilbert subspace defined by an error-correcting code. Its quantum state is usually described as a many-body entanglement state, and is generally a two-dimensional subspace composed of multiple physical qubits and a Hilbert space. Fault-tolerant quantum computation must be performed on logical qubits protected by an error-correcting code.

[0029] 15. Quantum gates / circuits: These are quantum gates / circuits that act on physical qubits.

[0030] 16. Threshold Theorem: For a quantum computing scheme that satisfies the requirements of fault-tolerant quantum computing, if the error rate of all operations is below a certain threshold, the accuracy of the computation can be arbitrarily brought closer to 1 by using better error correction codes, more qubits, and more quantum operations, while these additional resource consumptions are negligible compared to the exponential acceleration of quantum computing.

[0031] 17. Neural Networks: Artificial neural networks are adaptive, nonlinear, and dynamic systems composed of a large number of interconnected neurons, which are simple basic elements. While the structure and function of each neuron are relatively simple, the system behavior generated by the combination of a large number of neurons is extremely complex and, in principle, can represent any function.

[0032] 18. Convolutional Neural Network (CNN): A convolutional neural network is a type of feedforward neural network that includes convolutional operations and has a deep structure. The convolutional layer is the core foundation of a convolutional neural network, and it performs convolutional operations between discrete two-dimensional or three-dimensional filters (also called convolutional kernels, which are two-dimensional or three-dimensional matrices, respectively) and two-dimensional or three-dimensional data point clouds.

[0033] 19, Linear rectification layer (Rectified Linear Units layer, ReLU layer): Linear rectification (Rectified Linear Units, ReLU) Use TIFF0007848400000006.tif5170 as the excitation function for the neural network.

[0034] 20. The Leaky Rectified Linear Unit Layer (LeakyReLU Unit) is a type of activation function based on ReLU, but it does not have a flat slope for negative values, but rather a very small slope.

[0035] 21. Backpropagation (BP): A type of supervised learning algorithm in artificial neural networks. The BP neural network algorithm can theoretically approximate any function, and its basic structure consists of nonlinear change units, giving it very powerful nonlinear mapping capabilities.

[0036] 22. Field Programmable Gate Array (FPGA): This is a further development of programmable devices such as PAL (Programmable Array Logic) and GAL (Generic Array Logic). It emerged as a kind of semi-custom circuit in the Application Specific Integrated Circuit (ASIC) field, solving the shortage of custom circuits while simultaneously overcoming the drawback of conventional programmable devices having a finite number of gate circuits.

[0037] 23. Application Specific Integrated Circuit (ASIC): This refers to an integrated circuit designed and manufactured to meet the specific requirements of a particular user and the needs of a particular electronic system. Designing ASICs using CPLDs (Complex Programmable Logic Devices) and FPGAs is one of the most popular methods. They share the characteristics of being programmable in the field by the user and supporting boundary scan technology, but each has its own characteristics in terms of integration density, speed, and programming method.

[0038] 24. Single Flux Quantum (SFQ) Circuit: Also known as RSFQ (Rapid Single Flux Quantum) circuit, this circuit is composed of Josephson junctions (JJ) and represents "1" or "0" depending on the presence or absence of a flux quantum. Within the circuit, "X" represents the Josephson junction. The top and bottom two layers are composed of superconductors, and the middle layer is composed of a very thin insulator. It can be used for digital logic calculations.

[0039] 25. Multi-task learning: In this application, this is defined as performing multiple classification tasks simultaneously using the same neural network model. The objective is to reduce the overall computational and spatial complexity by configuring multiple neural networks into one large neural network and sharing some of the neural networks as much as possible.

[0040] 26. Canonical Pauli Operator: For a given stabilizer code, one of the Pauli operators of its equivalent class can be represented as the representative Pauli operator. This representative Pauli operator is called the canonical Pauli operator of that class.

[0041] 27. Adam (Adaptive moment estimation): This is a type of algorithm that performs first-order gradient optimization on a random target function and is based on adaptive low-order moment estimation. The Adam algorithm is easy to implement, highly computationally efficient, and requires little memory.

[0042] The solutions provided in the embodiments of this application relate to the application of artificial intelligence machine learning techniques to the quantum technology field, and more specifically, to the application of quantum error correction code decoding algorithms in machine learning techniques, and will be described with reference to the embodiments shown below.

[0043] Because qubits are highly susceptible to noise, directly implementing quantum computation on physical qubits is not yet feasible with current technology. The development of quantum error correction and fault-tolerant quantum computing techniques offers the possibility of achieving quantum computation with arbitrary precision on noisy qubits. Generally, measuring the stabilizer generator of quantum error correction codes (also known as qubit parity checking) requires the introduction of long-range quantum gates, and simultaneously requires the preparation of complex quantum auxiliary states using additional qubits to perform fault-tolerant error correction. Due to limitations in current experimental means, people do not yet have the ability to realize high-precision long-range quantum gates or prepare complex quantum auxiliary states. On the other hand, fault-tolerant quantum error correction and fault-tolerant quantum computing schemes using surface codes do not require the use of long-range quantum gates or the preparation of complex quantum auxiliary states, and are therefore considered to have a very high potential for realizing general-purpose fault-tolerant quantum computers using current technology.

[0044] As an error-correcting code, after an error occurs, an error syndrome can be obtained through parity checking. Based on these syndromes, it is then necessary to determine the location and type of the error (X error, Z error, or Y error, which includes both) based on a more specific error-correcting code decoding algorithm. In the case of surface codes, errors and error syndromes have specific spatial locations. If an error causes a syndrome, the eigenvalue of the auxiliary qubit at the corresponding location is 1 (it can be considered that a single point particle appeared at that location), and if there is no error, the eigenvalue of the auxiliary qubit at the corresponding location is 0. In this case, decoding can be reduced to the following problem: given a spatial digital array (two or three dimensions, where the values ​​are 0 or 1), based on a specific error model, i.e., the error probability distribution occurring in the qubits, it is necessary to infer which qubit is most likely to have an error and its specific error type, and then perform error correction based on this inference.

[0045] Figure 2 is a schematic diagram of error occurrence in surface coding. The qubits are located on the edges of the two-dimensional array, and the auxiliary qubits that measure the error syndrome are located at the nodes of the two-dimensional array (these syndromes are perfect measurements). In Figure 2, the black edges 21 represent the error chain formed by the qubits that have experienced errors, and the shaded circular portions 22 represent points where the syndrome value caused by the error is 1. If a chain of errors can be identified based on the point-like syndromes, decoding can be performed.

[0046] As mentioned above, by employing an error correction code decoding algorithm (also called a decoder) to decode the error syndrome information, corresponding error result information, including the location and type of the error, can be obtained. The decoding capability of a single decoder can be evaluated using several key indicators, including decoding algorithm complexity, decoding time, decoding performance, suitability for real-time error correction, and the difficulty of implementation in engineering.

[0047] Decryption algorithm complexity: This refers to the total number of basic computational steps required for the decoding algorithm's operation, and corresponds to computational complexity. The higher the complexity, the greater the amount of computation required.

[0048] Decryption Time: Time here is an abstract concept and differs from actual decoding time, but it is strongly related. Here, it refers to the depth of the algorithm after the decoding algorithm has been sufficiently parallelized. This depth determines the lower bound of the execution time of the actual decoding algorithm, i.e., the execution time of the algorithm required after maximum parallelization.

[0049] Decoding performance: This is evaluated using the error rate that occurs in the logical qubits after decoding and correcting errors based on a specific noise model. For the same physical qubit error rate, a lower logical error rate indicates higher decoding performance.

[0050] Suitability for real-time error correction: Due to the relatively short lifetime of qubits (for example, the lifetime of a superconducting qubit is about 150 microseconds under good process conditions, and after multiple syndrome measurements, real-time decoding and error correction are performed based on these syndromes, and during the decoding process, the system enters an idle state, errors accumulate over time, and theoretically, the total time consumed by the error correction process is required to be less than 1 / 1000 to 1 / 100 of the superconducting qubit lifetime, meaning the allowable margin for the total correction time is about 150 ns to 1500 ns, and exceeding this may cause the error rate to exceed the correction capability of the surface code), CPUs (Central Processing Units) and GPUs (Graphics Processing Units) have problems such as uncertainty in memory read and write times, uncertainty in cache hits, and branch jumps, which result in relatively long delays and cannot meet the requirements, and the computational microarchitecture of CPUs / GPUs is not optimized for decoding algorithms and cannot achieve performance metrics for generality. This application considers porting the decoding algorithm to a specific computing device such as an FPGA or ASIC. However, these devices are suitable for parallelizing and executing simple steps (e.g., vector dot product, matrix multiplication) but are not suitable for executing instructions involving complex conditional checks or jumps.

[0051] Engineering implementation difficulty: This refers to the ease of hardware implementation of the decoder from an engineering perspective. Even if the theoretical time complexity of the decoding algorithm is low, in practice the control may be relatively complex, or the actual computational load may still be large, requiring multiple computing devices to work together in parallel. In this case, the delay caused by inter-chip communication can be larger than the delay of the computation itself, which is unacceptable in actual real-time decoding. Therefore, algorithms that are easy to implement from an engineering perspective must reliably reduce the computational load and the number of computing devices used and the communication between computing devices (chips). Also, since the majority of the chip area of ​​FPGA / ASIC is used for real-time computation, the remaining on-chip high-speed cache is limited, and therefore, it is required that a large amount of data should not be preloaded on the chip. Specifically applied to neural network decoders, this means that the number of usable network parameters should not be large, should not increase excessively as the scale of the error correction code increases, and the on-chip memory pre-placed on the chip must be easily readable.

[0052] Currently known quantum error correction decoding schemes include those based on MWPM, RG algorithm, CA, MCMC (Monte Carlo Markov Chain), MLD (Maximum Likelihood Decoding), and NN (Neural Network). Figure 3 shows a schematic comparison of the decoding performance and decoding time of each decoding scheme. In Figure 3, the black dots corresponding to MWPM are used to show the decoding performance and decoding time of the MWPM-based decoding scheme, the black dots corresponding to RG are used to show the decoding performance and decoding time of the RG algorithm-based decoding scheme, the black dots corresponding to CA are used to show the decoding performance and decoding time of the CA algorithm-based decoding scheme, the black dots corresponding to MCMC are used to show the decoding performance and decoding time of the MCMC algorithm-based decoding scheme, the black dots corresponding to MLD are used to show the decoding performance and decoding time of the MLD algorithm-based decoding scheme, and the black dots corresponding to NNbD are used to show the decoding performance and decoding time of the neural network-based decoding scheme. In short, as can be seen from Figure 3, the neural network-based decoding strategy can achieve good decoding performance for small-scale surface codes, and the required decoding time is also relatively short.

[0053] This invention proposes an end-to-end machine learning decoding method based on multitask learning. This method reduces the complexity of the algorithm (computational complexity). TIFF0007848400000007.tif6170, Decryption time Assuming that TIFF0007848400000008.tif5170 is not increased and scalability is maintained, decoding performance is significantly improved, and simultaneous optimization of decoding time and decoding performance is achieved, as shown in the area 30 enclosed by the dotted line in the lower right corner of Figure 3. At the same time, its structure is also simpler, that is, TIFF0007848400000009.tif6170 models The number of TIFF0007848400000010.tif files is reduced to 5170, communication between models is no longer required, and hardware implementation in engineering becomes easier.

[0054] Figure 4 is a schematic diagram of an application scenario of a solution according to one embodiment of the present invention. As shown in Figure 4, this application scenario may be a superconducting quantum computing platform, and this application scenario may include a quantum circuit 41, a dilution refrigerator 42, a control device 43, and a computer 44.

[0055] The quantum circuit 41 is a circuit that acts on a physical qubit, and the quantum circuit 41 can be realized as a quantum chip such as a superconducting quantum chip near absolute zero. The dilution refrigerator 42 is used to provide an absolute zero environment for the superconducting quantum chip.

[0056] The control device 43 is used to control the quantum circuit 41, and the computer 44 is used to control the control device 43. For example, the created quantum program is compiled into instructions by software in the computer 44 and sent to the control device 43 (e.g., an electron / microwave control system), which converts the above instructions into electron / microwave control signals and inputs them to the dilution refrigerator 42 to control the 10mK superconducting qubit. The readout process is the reverse of this.

[0057] As shown in Figure 5, the neural network-based quantum error correction decoding method according to the embodiment of the present invention operates in cooperation with the control device 43 (for example, by integrating this decoding algorithm into an electron / microwave control system). After the control device 43's overall control system 43a (for example, a central board FPGA) reads error syndrome information from the quantum circuit 41, the overall control system 43a sends an error correction command to the control device 43's error correction module 43b, which includes the error syndrome information of the quantum circuit 41. The error correction module 43b may be an FPGA or an ASIC chip. The error correction module 43b executes the neural network-based quantum error correction decoding algorithm, decodes the error syndrome information, converts the error result information obtained by decoding into an error correction control signal in real time, and transmits it to the quantum circuit 41 to perform error correction.

[0058] To facilitate the explanations that will follow, let me first introduce some of the basic concepts proposed in this application.

[0059] 1. Canonical representation of Pauli operators Any Pauli operator TIFF0007848400000011.tif4170, and error correction code The generator of the stabilizer group for TIFF0007848400000012.tif4170 (although this application uses a rotating surface code as an example, any topological error correction code can be defined in a similar manner). Given TIFF0007848400000013.tif4170, the Pauli operator acts on the physical qubits that support the error correction code. TIFF0007848400000014.tif4170 can be broken down as follows: TIFF0007848400000015.tif5170

[0060] Here, TIFF0007848400000016.tif5170 is In TIFF0007848400000017.tif4170 The generator of the part that anticommutates TIFF0007848400000018.tif4170 (Pauli operator) This is also known as the TIFF0007848400000019.tif4170 syndrome, TIFF0007848400000020.tif5170 can be considered a bit array consisting of 0s and 1s. TIFF0007848400000021.tif5170 is a Pauli operator generated by mapping based on a portion of this generator. In quantum mechanics, operators F and G are said to commute if FG=GF, and anticommutate if FG=-GF. TIFF0007848400000022.tif5170 and TIFF0007848400000023.tif5170 has a one-to-one correspondence. This is called the simple representation of TIFF0007848400000024.tif4170. In the case of a rotating surface code, a definition with geometric meaning can be given to the simple representation, that is, the shortest path connecting the syndrome to the boundary. It can be defined as a Pauli operator that is anticommutative with TIFF0007848400000025.tif4170. Figure 6 is a schematic diagram of a simple representation corresponding to a syndrome point in a rotating surface code, where the circle a represents a syndrome point with a single value of 1, and the line 61 represents an X-type Pauli operator, which is the shortest path connecting the syndrome point a to the boundary. This is a Pauli operator that anticommutates TIFF0007848400000026.tif4170. Similarly, the circled point b represents a syndrome point with a single value of 1, and the line 62 represents a Z-type Pauli operator, which is the shortest path connecting syndrome point b to the boundary. This is a Pauli operator that anticommutates TIFF0007848400000027.tif4170. In general, all topological error correction codes can have similar simple representation mappings.

[0061] TIFF0007848400000028.tif5170 is TIFF0007848400000029.tif4170 is a specific operator in the logic type of error correction code to which it belongs (once selected, it is fixed). Another Pauli operator When considering TIFF0007848400000030.tif5170, a similar decomposition is applied. TIFF0007848400000031.tif5170

[0062] It is TIFF0007848400000032.tif5170, TIFF0007848400000033.tif5170 and If TIFF0007848400000034.tif5170 belongs to the same logical type, TIFF0007848400000035.tif5170 and TIFF0007848400000036.tif4170 differs by only one element of its stabilizer group, meaning they are equivalent in terms of error correction. Then any Pauli operator For TIFF0007848400000037.tif4170, the following definition can be used: TIFF0007848400000038.tif5170

[0063] Here, TIFF0007848400000039.tif5170 is TIFF0007848400000040.tif5170 is one of the fixed representative elements of the logical type to which it belongs. TIFF0007848400000041.tif5170 is This is called the canonical representation of TIFF0007848400000042.tif4170. TIFF0007848400000043.tif5170 is This is called the canonical decomposition of TIFF0007848400000044.tif4170. It converts all Pauli operators to their equivalent canonical representations. This greatly limits the unnecessary diversity of Pauli operators, significantly reducing the difficulty of model training and improving the convergence speed of the training process, especially when Pauli operators are selected as the model's output.

[0064] 2. Fault tolerance and error correction in multi-model learning According to theory, fault tolerance and error correction of surface codes are After performing 170 syndrome measurements, all collected syndrome information can be decoded together, thereby ensuring that the error correction capability of the error correction code is not affected even in fault-tolerant scenarios.

[0065] Exemplary, a syndrome measurement circuit may be as shown in Figure 7. Here, Figure 7(a) shows an eigenvalue measurement circuit for a stabilizer generator that detects a Z error, and Figure 7(b) shows an eigenvalue measurement circuit for a stabilizer generator that detects an X error. In this circuit, the order of operation of the controlled NOT gates (CNOTs) is crucial; they must not be reversed, otherwise collisions will occur due to different quantum gates using the same qubit. In this process, all steps, including the controlled NOT gates, the preparation of the auxiliary states, and the measurement of the final auxiliary states, introduce noise because the controlled NOT gates propagate errors, and the two types of syndrome measurements, X and Z, are nested with each other. The arrangement shown in Figure 7 minimizes error propagation and reduces its impact on correction capability to a negligible degree. Other arrangements significantly reduce correction capability.

[0066] Thus, after multiple syndrome measurements, the error syndrome information obtained by the syndrome measurement circuit becomes a three-dimensional 0-1 array as shown in Figure 8. Figure 8 shows a schematic diagram of the three-dimensional syndrome distribution, with the vertical direction representing time. This can be considered as a three-dimensional data array composed of 0s and 1s. Figure 8 contains a total of four slices 81, each slice 81 representing the error syndrome information obtained in a single measurement. Line 82 represents the syndrome caused by the Z error, line 83 represents the syndrome caused by the X error, and line 84 represents the measurement error.

[0067] After 170 such syndrome measurements, the mathematical definition of the fault-tolerant optimal decoder (Maximum a posterior, MAP) is as follows: TIFF0007848400000047.tif6170 (This formula will be referred to as Formula 1)

[0068] Here, TIFF0007848400000048.tif4170 is a three-dimensional data array composed of 0s and 1s, representing error syndrome information. TIFF0007848400000049.tif5170 is the most likely error in a two-dimensional data qubit, which can be inferred based on the measured error syndrome information. Perform the operation corresponding to TIFF0007848400000050.tif5170 and correct any physical errors that occur. Note the following: TIFF0007848400000051.tif5170 and the errors that actually persist in the physical qubit TIFF0007848400000052.tif6170 does not need to match, and the weight of the difference between the two is... TIFF0007848400000053.tif6170 is small enough. It is sufficient to guarantee that TIFF0007848400000054.tif6170 can be corrected in the next correction process. Note that the classification result corresponding to each data qubit includes four cases: I, X, Y, and Z, where I represents no error, X represents an X error, Z represents a Z error, and Y represents the presence of both X and Z errors. Furthermore, a quantum circuit with an error correction code scale of L has a number of data qubits included in it that is L. 2 Therefore, The possible options for TIFF0007848400000055.tif4170 are TIFF0007848400000056.tif5170 contains different types of Pauli operators. Traverse all Since it is impossible to calculate the probability of TIFF0007848400000057.tif4170, the decoding problem is a #P-Complete problem in terms of computational complexity. To decode effectively, it needs to be simplified. The canonical representation of TIFF0007848400000058.tif4170, i.e., By using TIFF0007848400000059.tif5170, all equivalent TIFF0007848400000060.tif4170 can be represented. This means the number of Pauli operators that need to be traversed is It decreases to TIFF0007848400000061.tif10170. The reason is that for error correction codes, all errors multiplied by one element of the stabilizer group are equivalent, so when classifying errors, these equivalent errors can be grouped together, and the stabilizer group is TIFF0007848400000062.tif5 contains 170 elements, therefore here TIFF0007848400000063.tif5170 errors of any type need to be traversed. From here on, Pauli errors... Regarding TIFF0007848400000064.tif4170, without distinguishing between them, a canonical representation representing an equivalent Pauli operator. Use TIFF0007848400000065.tif5170.

[0069] Furthermore, it is necessary to represent error information and to divide and conquer the represented information, dividing it into different information blocks, thereby reducing the complexity of traversal. This application provides two error decomposition methods.

[0070] The first method is a method of canonically decomposing canonical representations. Due to the one-to-one correspondence between simple errors and syndromes, two TIFF0007848400000066.tif5170 syndromes TIFF0007848400000067.tif6170, It can be written using the elements of TIFF0007848400000068.tif6170, TIFF0007848400000069.tif5170 is TIFF0007848400000070.tif6170 and This can be determined based on TIFF0007848400000071.tif6170. TIFF0007848400000072.tif5170 and TIFF0007848400000073.tif5170 is referred to as a canonical syndrome in the decoded output. Taking TIFF0007848400000074.tif5170 as an example, it can be broken down as follows. TIFF0007848400000075.tif6170

[0071] each TIFF0007848400000076.tif6170 contains some X-type syndrome bits. A similar decomposition exists for Z-type syndrome bits. Therefore, the MAP decoding process for Z-type errors is approximately as follows: TIFF0007848400000077.tif7170

[0072] The same process can be applied to X-type errors, and the MAP decoding process for X-type errors is approximately as follows. TIFF0007848400000078.tif7170

[0073] The second method involves directly decomposing the Pauli error according to its distribution in physical qubits. The physical qubits can be divided into disjoint sets of different blocks. TIFF0007848400000079.tif5170

[0074] This division If we write TIFF0007848400000080.tif5170, the following equation holds true. TIFF0007848400000081.tif5170

[0075] Here, TIFF0007848400000082.tif5170 is, Acts on TIFF0007848400000083.tif5170 This is the Pauli operator for TIFF0007848400000084.tif4170, TIFF0007848400000085.tif5170 represents the Cartesian product. Thus, the decoding process can be approximately simplified as follows. TIFF0007848400000086.tif6170

[0076] Here The expression TIFF0007848400000087.tif14170 is This is the marginal probability distribution for TIFF0007848400000088.tif5170. TIFF0007848400000089.tif7170 is, Block of TIFF0007848400000090.tif4170 This represents the operators that operate on parts other than TIFF0007848400000091.tif4170, where the value of i is an integer in the range [1, m]. Similar to the canonical representation decomposition case, further errors can be detected. TIFF0007848400000092.tif6170 and It can also be decomposed into TIFF0007848400000093.tif6170 and decoded using approximate MAP for each part. TIFF0007848400000094.tif7170

[0077] In any method, the selected splitting method is: TIFF0007848400000095.tif7170 or It is necessary to ensure that the value is TIFF0007848400000096.tif5170, meaning that there is an upper limit to its size, and that this upper limit does not depend on the scale of the error correction code. Under this limitation, decoding performance must be improved as much as possible. The reason for this choice is based on the intuition that the correlation between the syndrome and errors occurring in the physical bits is limited, and that the scale of this correlation does not increase with L.

[0078] Furthermore, MWPM is Only use syndromes of type TIFF0007848400000097.tif5170 This code attempts to decode an error of type TIFF0007848400000098.tif5170. However, it can be argued that all syndrome bit information must be used simultaneously to decode the X and Z errors, because the Z and X errors are interrelated, and their corresponding syndrome bits are not entirely independent. By considering all syndromes together, the positions of the X and Z errors can be determined more accurately. In contrast, MWPM and other algorithms have not yet utilized this point.

[0079] The purpose of using machine learning-based methods is, TIFF0007848400000099.tif7170, TIFF0007848400000100.tif7170, TIFF0007848400000101.tif5170 This is nothing more than approximating these distribution functions with neural networks. Since all of these functions have a common input S (three-dimensional syndrome bits), the direct method is to approximate each distribution function using a neural network model, normalization is performed using the Softmax function at the end of the network to generate the corresponding probability distribution, error information is compiled based on the distribution results, and corrections are made to the data qubits. The overall decoding process is as shown in Figure 9, where m (m is greater than 1) neural network models each perform decoding on the error syndrome information S to obtain m sets of probability distributions, and then error result information is determined based on these m sets of probability distributions, and this error result information indicates the data qubit where the error occurred and the corresponding error type.

[0080] It is important to note that there is a maximum upper limit to the output size of each network. Therefore, the number of neural networks and the number of physical qubits are important. TIFF0007848400000102.tif5170 is directly proportional.

[0081] If there is no noise in each syndrome measurement, a single-level syndrome measurement is sufficient, eliminating the need to infer the simple error portion in the canonical representation of the error operator, and thus Equation 1 above can be simplified as follows. TIFF0007848400000103.tif6170

[0082] For surface codes encoding single bits, this decoding scheme simplifies to a four-classification problem, allowing a single network to perform the decoding. From a topological perspective, in fault-tolerant scenarios with measurement noise, the decoding problem cannot be reduced to a similarly simple classification problem. Therefore, fault-tolerant decoding using neural networks is far more complex than in the perfect syndrome case.

[0083] Figure 10 is a flowchart of a neural network-based quantum error correction decoding method according to one embodiment of the present invention, which is applicable to a control device in the application scenario shown in Figure 4, and which may include at least one of the following steps 1010 to 1040.

[0084] In step 1010, error syndrome information is obtained by performing a syndrome measurement on the quantum circuit.

[0085] Here, the error syndrome information is a data array composed of eigenvalues ​​from the stabilizer generators of the quantum error correction code.

[0086] By performing error syndrome measurements on a quantum circuit using a quantum error correction code, corresponding error syndrome information can be obtained. This error syndrome information is a data array composed of eigenvalues ​​from the stabilizer generator of the quantum error correction code. For example, the error syndrome information is a two-dimensional or three-dimensional data array composed of 0s and 1s. For instance, if there is no error, the eigenvalue of the stabilizer generator is 0, and if an error occurs, the eigenvalue of the stabilizer generator is 1.

[0087] Taking the case of a quantum error-correction code being a surface code as an example, in the case of a surface code, errors and error syndromes have specific spatial locations. When an error triggers a syndrome, the eigenvalue of the auxiliary qubit at the corresponding location is 1 (it can be considered that a single point particle has appeared at that location), and when there is no error, the eigenvalue of the auxiliary qubit at the corresponding location is 0. Therefore, for a surface code, if we do not consider errors in the correction process itself (i.e., the measurement process is perfect, in which case it is called a perfect syndrome), the error syndrome information can be considered as a two-dimensional data array consisting of 0s and 1s.

[0088] For example, when multiple syndrome measurements are performed on a quantum circuit, error syndrome information in the form of a two-dimensional data array can be obtained with each measurement, and error syndrome information in the form of a three-dimensional data array can be obtained by performing multiple syndrome measurements, as shown in Figure 8.

[0089] In step 1020, a neural network decoder is used to extract feature information from the error syndrome information.

[0090] In one possible embodiment, when extracting feature information from error syndrome information using a neural network decoder, the control device can extract features from the error syndrome information using the feature extraction network of the neural network decoder and obtain feature information. Here, the neural network decoder includes a feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0091] A neural network decoder is a machine learning model built on a neural network for decoding error syndrome information. The input data to the neural network decoder is error syndrome information, and the output data is error result information corresponding to that error syndrome information.

[0092] In the embodiment of the present invention, the neural network decoder includes one feature extraction network and multiple feature decoding networks. Here, the feature extraction network is used to extract features from error syndrome information and obtain feature information. The feature information output from the feature extraction network is input to each of the multiple feature decoding networks, which then perform decoding on the feature information, and a corresponding decoding result can be obtained for each feature decoding network.

[0093] In some embodiments, the feature extraction network can be constructed based on a Convolutional Neural Network (CNN). In some embodiments, the feature decoding network can be constructed based on a Fully Connected Neural Network (FCN). Of course, this application is not limited to the feature extraction network and the feature decoding network, and the feature extraction network and the feature decoding network may be other network structures.

[0094] In Figure 9, the number of models is equal to the number of bits. As TIFF0007848400000104.tif5170 increases, it increases linearly, resulting in a large computational complexity. Too many models also significantly increase the difficulty of implementing the algorithms on specific hardware. While these models are executable in parallel, the hardware resources consumed increase rapidly with increasing complexity, leading to a very large demand for FPGA or ASIC chips and causing difficulties in system integration. Therefore, these We attempt to extract as many reusable parts as possible from TIFF0007848400000105.tif6170 models and construct a single frontend, i.e., a feature extraction network. The output of the frontend is TIFF0007848400000106.tif6170 simplified feature decoding networks, such as a feed-forward fully connected network (FFN), are output to generate n probability distributions and perform decoding, and these n different feature decoding networks constitute the backend of the model.

[0095] Exemplary, the overall model is shown in Figure 11. The front-end is a feature extraction network, which may include multiple cascaded feature extraction subnetworks and one feature fusion subnetwork. The role of the feature extraction subnetworks is to extract local feature information using a divide-and-conquer approach, while the feature fusion subnetwork ultimately aggregates and compresses all the local feature information to obtain the final feature information. Here, the feature extraction subnetworks can be built on a CNN, for example, each feature extraction subnetwork may include one or more convolutional layers. The feature fusion subnetworks can be built on a fully connected network, for example, including one or two fully connected layers.

[0096] This is a typical multitask learning neural network model, and its effectiveness is based on the assumption that a sufficient number of features are extracted in the front-end and provided to an arbitrary back-end feature decoding network for accurate local information distribution of noise decomposition (e.g., TIFF0007848400000107.tif7170, TIFF0007848400000108.tif7170, It is possible to comprehensively generate TIFF0007848400000109.tif5170). This is reasonable in principle because the backend is TIFF0007848400000110.tif6170 can be considered a localized simplified version of the global classifier, and the premise for this to hold is that the information provided by the front-end is, in principle, used by this global classifier. TIFF0007848400000111.tif6170 can be provided for the calculation of the Pauli operator distribution. Furthermore, assuming that decoding performance is unaffected, it is required that the computational complexity of the front-end is engineeringly acceptable.

[0097] The size of the front-end and back-end networks is determined on a case-by-case basis. Current experimental results suggest that the size of the back-end feature decoding network (e.g., when employing fully connected layers) is proportional to the error correction code scale. The number of backend model parameters does not depend on TIFF0007848400000112.tif4170. The computational depth is directly proportional to TIFF0007848400000113.tif6170. The filename is TIFF0007848400000114.tif5170. The computational complexity of the entire backend is The filename is TIFF0007848400000115.tif6170. The computational complexity of the front-end and the complexity of the overall algorithm will be explained later.

[0098] Furthermore, both of the error decomposition methods described above can utilize the model architecture based on the multi-task learning described above. The advantage of the first error decomposition method is that the actual network size is relatively small, but the performance of the resulting decoder may be limited due to constraints on the training data generation method. The second error decomposition method provides end-to-end training and can significantly improve decoding performance by performing decoding using X-type and Z-type syndromes. In the embodiments of this application, a neural network decoder that performs training and reasoning using the first error decomposition method is called a first-type decoder, and a neural network decoder that performs training and reasoning using the second error decomposition method is called a second-type decoder.

[0099] For example, the feature extraction network of a neural network decoder employs a block-partitioning feature extraction method based on the idea of ​​dividing and processing the error syndrome information when performing feature extraction. In other words, each or some of the feature extraction subnetworks is used to perform block-partitioning feature extraction on the input data. Block-partitioning feature extraction refers to the process by which the feature extraction subnetwork divides the input data into blocks, further dividing it into multiple smaller blocks, and then performing feature extraction on each smaller block. In other words, block-partitioning feature extraction means that after dividing the input data into blocks and obtaining at least two blocks, at least two feature extraction units are used to perform feature extraction on these at least two blocks in parallel. Here, there is a one-to-one correspondence between at least two blocks and at least two feature extraction units, and each feature extraction unit is used to perform feature extraction on one block, with the number of blocks and feature extraction units being equal. Furthermore, since the feature extraction on the above at least two blocks is performed in parallel, i.e., simultaneously, it helps to reduce the time required for feature extraction. For example, as shown in Figure 11, the error syndrome information is a three-dimensional syndrome bit. After dividing the three-dimensional syndrome bit into C1 blocks, the first feature extraction subnetwork performs feature extraction in parallel on the C1 block, obtaining C2 blocks. Similarly, the second feature extraction subnetwork performs feature extraction in parallel on the C2 block, obtaining C3 blocks. And so on, the kth feature extraction subnetwork is C k Feature extraction is performed in parallel for each block, C k+1 We obtain blocks such that k is a positive integer. Finally, we use a feature fusion subnetwork to obtain the above C k+1 Each block is subjected to fusion and compression processing to obtain feature information, which is then used as input for the backend.

[0100] In step 1030, the neural network decoder performs a decoding process on the feature information to obtain the decoding result.

[0101] In one possible embodiment, if the neural network decoder includes a feature extraction network and n feature decoding networks, the control device can perform decoding on the feature information using the n feature decoding networks and obtain the corresponding decoding results for each of the n feature decoding networks, where the n feature decoding networks are trained using a multi-task learning method and are capable of generating different decoding results.

[0102] For the first type of decoder, step 1030 is: The process involves decrypting the feature information using n1 feature decoding networks, obtaining corresponding decoding results for each of the n1 feature decoding networks, wherein for the i-th feature decoding network among the n1 feature decoding networks, the corresponding decoding result includes the i-th canonical syndrome related to the target error type, where i is a positive integer less than or equal to n1, and the canonical syndrome refers to the canonical decomposition result of the error syndrome information. The process involves performing a decoding operation on feature information using n2 feature decoding networks, and obtaining corresponding decoding results for each of the n2 feature decoding networks, wherein for the j-th feature decoding network among the n2 feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element related to the target error type, where j is a positive integer less than or equal to n2, and where the sum of n1 and n2 is equal to n, and n1 and n2 are positive integers.

[0103] In some embodiments, the target error types include Pauli X errors and Pauli Z errors, where n1 is equal to the sum of m1 and m2, m1 and m2 are positive integers, and n2 is 2. Of the n1 feature decoding networks mentioned above, m1 feature decoding networks are used to perform decoding on the feature information and obtain the canonical syndrome of the m1 term related to the Pauli X error. Of the n1 feature decoding networks mentioned above, m2 feature decoding networks are used to perform decoding on the feature information and obtain the canonical syndrome of the m2 term related to the Pauli Z error. One of the n2 feature decoding networks described above is used to perform a decoding process on the feature information and obtain a fixed representative element associated with the Pauli X error. One of the n2 feature decoding networks mentioned above is used to perform a decoding process on the feature information and obtain fixed representative elements associated with the Pauli Z error.

[0104] For example, the values ​​of m1 and m2 may be the same or different. For example, the error syndrome information includes Z-type syndrome information and X-type syndrome information, decoding is performed based on the Z-type syndrome information to obtain X-type error result information, which indicates a qubit in which a Pauli X error occurred in the quantum circuit, decoding is performed based on the X-type syndrome information to obtain Z-type error result information, which indicates a qubit in which a Pauli Z error occurred in the quantum circuit.

[0105] For example, the canonical syndrome of the m1 term related to the Pauli X error above is: It can be represented as TIFF0007848400000116.tif6170, and each TIFF0007848400000117.tif6170 contains some Z-type syndrome bits and is used for decoding to determine X-type errors. The canonical syndrome of the m2 term related to the above Pauli Z error is: It can be represented as TIFF0007848400000118.tif6170, and each TIFF0007848400000119.tif6170 contains some X-type syndrome bits and is used for decoding to determine Z-type errors. The fixed representative elements related to the above Pauli X errors are: It can be represented as TIFF0007848400000120.tif6170. The fixed representative element related to the above Pauli Z error is, It can be represented as TIFF0007848400000121.tif6170.

[0106] For the second type of decoder, the qubits contained in the quantum circuit are divided into n blocks, each block containing at least one qubit. For the k-th feature decoding network among the n feature decoding networks, the decoding result corresponding to the k-th feature decoding network includes a Pauli operator acting on the qubits contained in the k-th block among the n blocks, where k is a positive integer less than or equal to n.

[0107] For example, the k-th block is It can be written as TIFF0007848400000122.tif5170, and the k-th block The Pauli operators acting on the qubits contained in TIFF0007848400000123.tif5170 are This can be written as TIFF0007848400000124.tif5170. In this way, the n feature decoding network is a Pauli operator that acts on each of the n blocks. You can obtain TIFF0007848400000125.tif5170.

[0108] In step 1040, the error result information of the quantum circuit is determined based on the decoding result.

[0109] In some embodiments, the above error result information indicates the qubit in which an error occurred in the quantum circuit.

[0110] For example, the error result information described above can also indicate the error type corresponding to the qubit in the quantum circuit where the error occurred.

[0111] In one possible embodiment, if the neural network decoder includes a feature extraction network and n feature decoding networks, the control device can determine error result information based on the decoding results corresponding to each of the n feature decoding networks.

[0112] Based on the error result information output from the neural network decoder, it is possible to determine the qubit in the quantum circuit that has experienced an error and the corresponding error type. For example, it is possible to determine the location of the data qubit in the quantum circuit where the error occurred, and the error type of the data qubit at that location (e.g., whether it is a Pauli X error, a Pauli Z error, or a Pauli Y error which includes both Pauli X and Pauli Z errors).

[0113] For the first type of decoder, step 1040 may include the following:

[0114] Based on the fixed representative element associated with the Pauli X error and the canonical syndrome of the m1 term associated with the Pauli X error, X-type error result information is determined, and X-type error result information indicates the qubit in the quantum circuit where the Pauli X error occurred. In other words, TIFF0007848400000126.tif6170 and Based on TIFF0007848400000127.tif6170, X-type error result information Determine TIFF0007848400000128.tif5170; Based on the fixed representative element associated with the Pauli Z error and the canonical syndrome of the m² term associated with the Pauli Z error, Z-type error result information is determined, and Z-type error result information indicates the qubit in the quantum circuit where the Pauli Z error occurred. In other words, TIFF0007848400000129.tif6170 and Based on TIFF0007848400000130.tif6170, Z-type error result information Determine TIFF0007848400000131.tif5170; the above TIFF0007848400000132.tif5170 and For specific principles regarding the determination of TIFF0007848400000133.tif5170, please refer to the introductory explanation in the above embodiment.

[0115] In some embodiments, two neural network decoders can be trained for the first type decoder, denoted as the first neural network decoder and the second neural network decoder, respectively. As shown in Figure 12, the feature extraction network of the first neural network decoder extracts features from the Z-type error syndrome information to obtain the first feature information. Then, the m1+1 feature decoding networks of the first neural network decoder each perform a decoding process on the first feature information, obtaining decoding results corresponding to each of the m1+1 feature decoding networks. Here, the decoding result corresponding to the m1 feature decoding network includes a canonical syndrome of m1 terms related to the Pauli X error, and the decoding result corresponding to another feature decoding network includes a fixed representative element related to the Pauli X error. Based on the canonical syndrome of m1 terms related to the Pauli X error and the fixed representative element related to the Pauli X error, X-type error result information is determined, and this X-type error result information indicates the qubit in which the Pauli X error occurred in the quantum circuit. Furthermore, the feature extraction network of the second neural network decoder extracts features from the X-type error syndrome information to obtain second-type feature information. Subsequently, the m2+1 feature decoding networks of the second neural network decoder perform decoding on the second-type feature information, obtaining decoding results corresponding to each of the m2+1 feature decoding networks. Here, the decoding results corresponding to the m2 feature decoding networks include the m2-term canonical syndrome related to the Pauli Z error, and the decoding result corresponding to another feature decoding network includes a fixed representative element related to the Pauli Z error. Based on the m2-term canonical syndrome related to the Pauli Z error and the fixed representative element related to the Pauli Z error, Z-type error result information is determined, and this Z-type error result information indicates the qubit in which the Pauli Z error occurred in the quantum circuit.Both the first neural network decoder and the second neural network decoder described above can be trained using the multi-task learning method introduced above, and the number of feature decoding networks included in the first neural network decoder and the second neural network decoder may be the same or different, and the present invention is not limited thereto.

[0116] Furthermore, the example shown in Figure 12 only illustrates the case where the error syndrome information is decomposed into two parts: Z-type error syndrome information and X-type error syndrome information, and input to the first neural network decoder and the second neural network decoder, respectively. This helps reduce the computational complexity of the neural network decoder. In some other embodiments, the error syndrome information is not decomposed, and is directly input to the first neural network decoder and the second neural network decoder, respectively. The first neural network decoder then obtains X-type error result information based on the error syndrome information, and the second neural network decoder obtains Z-type error result information based on the error syndrome information.

[0117] For the second type of decoder, step 1040 may include determining error result information based on Pauli operators acting on each of the n blocks. That is, Error result information based on TIFF0007848400000134.tif5170 Determine TIFF0007848400000135.tif5170 and the above For specific principles regarding the determination of TIFF0007848400000136.tif5170, please refer to the introductory explanation in the above embodiment.

[0118] In some embodiments, as shown in Figure 13, for the second type of decoder, the error result information indicates the qubits in the quantum circuit that have experienced Pauli X errors and those that have experienced Pauli Z errors. In other words, the error syndrome information does not distinguish between X-type and Z-type error syndrome information, but uses all syndrome bits simultaneously to decode X and Z errors. Correspondingly, the decoded result also does not distinguish between X-type and Z-type error result information, but directly decodes to obtain error result information that includes both X and Z errors. Because there is an interrelationship between X and Z errors, by considering all syndrome bits together using the above method, the location of X and Z errors can be determined more accurately. Experimental data, which will be discussed later, also confirms a significant improvement in decoding performance by doing so. In this case, the decoding of error syndrome information can be performed and error result information can be obtained using only one neural network decoder.

[0119] In some embodiments, two neural network decoders may be used for the second type decoder, which will be denoted as the first neural network decoder and the second neural network decoder, respectively. As shown in Figure 14, the inputs to both the first and second neural network decoders are error syndrome information, and without distinguishing between X-type and Z-type error syndrome information, all syndrome bits are used simultaneously to decode X and Z errors. The feature extraction network of the first neural network decoder extracts features from the error syndrome information to obtain first feature information, and then the n feature decoding networks of the first neural network decoder each perform decoding on the first feature information, obtaining first decoding results corresponding to each of the n feature decoding networks. Here, the first decoding result corresponding to the k-th feature decoding network includes a Pauli operator related to the X-type error acting on the k-th block, and based on the first decoding results corresponding to each of the n feature decoding networks, the X-type error result information is determined, and this X-type error result information indicates the qubit in which a Pauli X error occurred in the quantum circuit. Furthermore, the feature extraction network of the second neural network decoder extracts features from the error syndrome information to obtain second feature information. Subsequently, the n feature decoding networks of the second neural network decoder each perform a decoding process on the second feature information, obtaining second decoding results corresponding to each of the n feature decoding networks. Here, the second decoding result corresponding to the k-th feature decoding network includes a Pauli operator related to a Z-type error acting on the k-th block. Based on the second decoding results corresponding to each of the n feature decoding networks, Z-type error result information is determined, and this Z-type error result information indicates the qubit in which a Pauli Z error occurred in the quantum circuit.Both the first neural network decoder and the second neural network decoder described above can be trained using the multi-task learning method introduced above, and the number of feature decoding networks included in the first neural network decoder and the second neural network decoder may be the same or different, and the present invention is not limited thereto.

[0120] The embodiments of this application do not limit the output type of the neural network decoder. In one possible embodiment, a physical-level output is employed, and the physical-level output model directly generates information about the specific qubit where the error occurred, i.e., which qubit specifically experienced what type of error. In another possible embodiment, a logical-level output is employed, and the logical-level output model outputs a logical error type to which the specific error has been transformed through a specific mapping, and then, based on this logical error type, the equivalent error that occurred specifically on the qubit can be calculated (this calculated error is not necessarily identical to the original error that occurred, but the effect is the same; this is an error degeneracy phenomenon unique to quantum error correction codes). Exemplaryly, to reduce the complexity of the neural network decoder and further shorten the decoding time, the neural network decoder may use a logical-level output.

[0121] In some embodiments, the neural network decoder performs a process of decoding already acquired error syndrome information while simultaneously executing a process of measuring and collecting new error syndrome information in parallel. By parallelizing syndrome measurement and decoding, TIFF0007848400000137.tif5170 eliminates the need to start decoding only after all syndrome measurements have been completed. The corresponding calculation can begin when enough syndrome bits have performed the smallest unit of computation (e.g., a single convolution operation). In this way, decoding can begin during subsequent syndrome measurement periods, and the two processes are parallelized. This reduces the overall delay time caused by performing error correction only after the final syndrome measurement is complete. A shorter delay time is desirable to prevent the accumulation of errors during the error correction process.

[0122] In some embodiments, the feature extraction network and n feature decoding networks included in the neural network decoder are located on the same chip. Exemplarily, this chip may be an FPGA or an ASIC. Exemplarily, if two neural network decoders are required in some embodiments, these two neural network decoders may be located on the same chip or on two separate chips, and the application is not limited thereto.

[0123] As described above, the technical solution provided in the embodiment of the present invention provides an error correction decoding scheme based on a multi-task learning neural network model. The neural network decoder extracts corresponding feature information from the input error syndrome information, then the neural network decoder decodes this feature information and outputs the decoded result of the noise-decomposed local information distribution. Subsequently, the error result information is determined based on the decoding result. Compared to schemes employing multiple neural network decoders, the scheme of the present invention can accurately determine the error result information with only a single neural network decoder. This significantly improves decoding performance and reduces decoding time without increasing algorithmic complexity and while maintaining scalability. Furthermore, hardware implementation in engineering is relatively easy. For example, in the above embodiment, the neural network decoder is designed as a structure including a feature extraction network and multiple feature decoding networks. The feature extraction network extracts corresponding feature information from the input error syndrome information, and this feature information is simultaneously used as input to multiple feature decoding networks. These multiple feature decoding networks output a noise-decomposed local information distribution, and then the error result information is determined based on the decoding results of these multiple feature decoding networks. Compared to the approach of employing multiple neural network decoders, this approach significantly improves decoding performance and reduces decoding time without increasing the complexity of the algorithm, while maintaining scalability. Furthermore, hardware implementation in engineering is relatively easy.

[0124] Furthermore, for the second type of decoder described above, a method that directly decomposes based on the distribution of Pauli errors in physical qubits can provide end-to-end reasoning and training. Moreover, since X and Z errors are interrelated, decoding using both X-type and Z-type syndromes simultaneously allows for a more accurate determination of the X and Z error locations by considering all syndrome bits together, significantly improving decoding performance.

[0125] In some embodiments, for the feature extraction network of the neural network decoder, we propose using LFEM (Local Feature Extraction Mapping) to compress the computational complexity.

[0126] In addition to the complexity of the output terminal due to measurement noise (which can be solved by multitasking learning), another complexity of neural network decoders is the complexity of their own training and reasoning. In the embodiments of this invention, the following solution is proposed: a large-scale error correction code is treated as multiple small-scale error correction codes (which can be called "minor error correction codes"), and after locally "decoding" the "minor error correction codes," the obtained information is aggregated at a higher level and "decoded" again. This process can be carried out recursively until the final decoded information contains errors that need to be corrected. Decoding of a specific region of "minor error correction codes" in each layer can be called LFEM.

[0127] In some embodiments, the feature extraction network includes multiple cascaded feature extraction subnetworks, where the input data of the first feature extraction subnetwork includes error syndrome information, the input data of the s-th feature extraction subnetwork includes the output data of the s-1th feature extraction subnetwork, and the output data of the last feature extraction subnetwork includes feature information, where s is an integer greater than 1.

[0128] For a target feature extraction subnetwork among multiple cascaded feature extraction subnetworks, the input data for the target feature extraction subnetwork is divided into multiple input data blocks of the same scale. The target feature extraction subnetwork may be any one of the above multiple cascaded feature extraction subnetworks. The target feature extraction subnetwork is used to perform multiple local feature extraction mappings on multiple input data blocks to obtain multiple sets of mapping output data. Here, each local feature extraction mapping is performed on a region at the same location in multiple input data blocks to obtain one set of mapping output data, while different numbers of local feature extraction mappings are used to perform mappings on regions at different locations in multiple input data blocks to obtain multiple sets of mapping output data. The target feature extraction subnetwork is further used to obtain output data for the target feature extraction subnetwork based on the above multiple sets of mapping output data.

[0129] Figure 15 illustrates a schematic diagram of local feature extraction mapping performed by a feature extraction subnetwork. Figure 15 shows the process of performing LFEM on two different regions (distinguished by the symbols (1) and (2) in the figure), with one LFEM input. TIFF0007848400000138.tif5 operates on the same location region in 170 input data blocks. Different numbers of LFEMs are input TIFF0007848400000139.tif5 acts on regions at different locations within 170 input data blocks, with two different regions, (1) and (2), shown in the figure.

[0130] In some embodiments, superposition exists between regions at different locations. The so-called superposition between regions at different locations means that there is superimposed data between regions at different locations. Furthermore, superposition may exist in some three-dimensional directions or in all directions. To compress computational complexity, the superposition between the "minor error correction codes" in each layer is small in the three-dimensional direction. Thus, the increase in the number of layers of local "error correction" is The result is TIFF0007848400000140.tif5170. The decoding effect can be improved by setting up superposition between regions at different locations. This is because the information in the same portion can be cross-validated after being processed by two LFEMs, thereby improving decoding performance. However, we do not want to introduce additional computational complexity due to excessive superposition. Note that the parameters of the networks themselves related to the different LFEMs are the same; only the input regions they act on are different.

[0131] In some embodiments, the target feature extraction subnetwork includes at least one convolutional layer and at least one fully connected layer. The at least one convolutional layer is used to perform multiple local feature extraction mappings on multiple input data blocks to obtain multiple sets of mapping output data. The at least one fully connected layer is used to obtain the output data of the target feature extraction subnetwork based on the multiple sets of mapping output data.

[0132] The simplest method for constructing a feature extraction subnetwork is to use a single-layer 3D CNN, but the expressive power of this neural network is limited, and when the scale of the error correction code is large, it significantly affects the decoding performance. Therefore, 3D CNN kernels should be able to process all input three-dimensional information blocks (total After acting on the same region (170 TIFFs) (the dashed box with the same symbol in Figure 15), we consider connecting to an FFN to perform further information integration and compression. This FFN may contain fully connected layers with different numbers of layers, and in practice, the maximum number of layers can be limited to 2.

[0133] Regarding overall parameter complexity analysis, when performing real-time decoding in hardware, the parameters must be pre-configured in the computing device (FPGA, ASIC, etc.). The number of parameters ultimately determines how much on-chip memory is used. The number of parameters in each feature extraction subnetwork is determined by its LFEM structure. Here, The number of parameters in TIFF0007848400000142.tif4170-layer 3D CNN is: It is TIFF0007848400000143.tif6170, and here, TIFF0007848400000144.tif5170 is the edge size of the maximum scale convolution kernel. The FFN parameters are The filename is TIFF0007848400000145.tif5170. If the filename is TIFF0007848400000146.tif5170, the total number of parameters in the frontend is as follows: TIFF0007848400000147.tif16170

[0134] The number of backend parameters The filename is TIFF0007848400000148.tif6170, and therefore the total number of parameters is The filename becomes TIFF0007848400000149.tif6170. The constant hidden under TIFF0007848400000150.tif4170 is usually large, If TIFF0007848400000151.tif4170 is small, the parameters actually occupied by the frontend may be greater than those occupied by the backend. Whether this is an asymptotic increase or the actual parameters of the actual model obtained from testing, it is acceptable in practical engineering.

[0135] Regarding the overall algorithm depth (or computation time), this part is determined by the method of performing multiplication and addition quickly. All multiplication operations in the 3D CNN and FFN parts of the feature extraction subnetwork (FFN layer count <= 2) are performed as quickly as possible. TIFF0007848400000152.tif5 can be completed in 170 hours, and the cumulative processing after multiplication is as follows: TIFF0007848400000153.tif5 requires 170 steps, therefore the total computation time for a single feature extraction subnetwork is The filename is TIFF0007848400000154.tif5170. Total TIFF0007848400000155.tif5 has 170 feature extraction subnetworks, so the total computation time (depth) of the frontend is The filename is TIFF0007848400000156.tif5170. The total computation time of the backend is fully parallelizable, and the backend The scale of the TIFF0007848400000157.tif6170-feature decoding network is The number of layers does not depend on TIFF0007848400000158.tif4170. The filename is TIFF0007848400000159.tif5170, and the multiplication calculation time is The filename is TIFF0007848400000160.tif5170, and the cumulative calculation time is The filename is TIFF0007848400000161.tif5170. Therefore, the depth of the entire algorithm is The filename is TIFF0007848400000162.tif5170. This algorithm time is the shortest theoretically achievable time, given sufficient computing resources.

[0136] For the overall computational complexity analysis, the input three-dimensional feature blocks of each layer are the output feature blocks of the previous layer. The number of input feature blocks of the i-th layer The filename is TIFF0007848400000163.tif5170, and the number of output feature blocks is... Let's assume it's TIFF0007848400000164.tif5170. The filename is TIFF0007848400000165.tif5170, and the input scale for each LFEM is If the filename is TIFF0007848400000166.tif5170, the number of LFEMs that need to operate in this layer is... TIFF0007848400000167.tif9170, and here, TIFF0007848400000168.tif5170 is the minimum convolution kernel for the entire network. The front-end multiplication complexity is as follows: TIFF0007848400000169.tif16170

[0137] It is mainly multiplication calculations, and the computational complexity of the backend multiplication is Since the filename is TIFF0007848400000170.tif6170, the computational complexity of the entire decryption process is It can fit into TIFF0007848400000171.tif6170. Without using multitasking learning, the computational complexity of the entire decoding process is: The file size increases to TIFF0007848400000172.tif6170, which is unacceptable from a practical engineering standpoint.

[0138] Furthermore, there are various different types of activation layers in neural networks. For the convenience of hardware implementation, this application uses two of them, namely ReLU and LeakyReLU. Here, LeakyReLU is defined as follows. TIFF0007848400000173.tif9170

[0139] At TIFF0007848400000174.tif4170 Select TIFF0007848400000175.tif4170, and Let's call it TIFF0007848400000176.tif8170. TIFF0007848400000177.tif5170 represents a set of positive integers. This approach significantly simplifies the implementation of the activation layer calculation, requiring only the determination of the sign bit and a right shift operation on a limited number of bits. Simulation results have confirmed that LeakyReLU achieves sufficiently good results.

[0140] In some embodiments, the training process for the neural network decoder is as follows:

[0141] 1. Obtain sample error syndrome information and sample error result information corresponding to the sample error syndrome information sample.

[0142] 2. The trained neural network decoder obtains predictive decoding results corresponding to each of the n feature decoding networks, based on sample error syndrome information.

[0143] 3. Based on the predicted decoding results corresponding to each of the n feature decoding networks, and the labeled decoding results corresponding to each of the n feature decoding networks determined based on the sample error result information, the loss function value corresponding to each of the n feature decoding networks is determined.

[0144] 4. Determine the total loss function value based on the loss function value corresponding to each of the n feature decoding networks.

[0145] 5. Based on the total loss function value, the parameters of the neural network decoder to be trained are adjusted to obtain the trained neural network decoder.

[0146] After the model network structure is set up, the model needs to be trained. Since it is necessary to learn multiple distribution functions at the output end, training is performed using a cross-entropy loss function on the outputs of n feature decoding networks. When generating input-output training data, the input end is set to a randomly generated syndrome (which may be a single X or Z syndrome, or a combination of both), and the output end is set to the output corresponding to that syndrome, and one-hot encoding is performed. It should be noted that the same syndrome input may correspond to different outputs. This diversity of output ends allows the model to ultimately learn an output probability distribution based on a specific input syndrome during the training process.

[0147] For the i-th feature decoding network among the n feature decoding networks described above, the loss function value corresponding to the i-th feature decoding network is determined based on the predicted decoding result corresponding to the i-th feature decoding network and the labeled decoding result corresponding to the i-th feature decoding network, which is determined based on the sample error result information. Here, the loss function value corresponding to the i-th feature decoding network is used to measure the similarity between the predicted decoding result corresponding to the i-th feature decoding network and the labeled decoding result corresponding to the i-th feature decoding network. The labeled decoding result corresponding to the i-th feature decoding network is a pre-set output label for the i-th feature decoding network, and can also be understood as the expected output result. The goal of training the i-th feature decoding network is to make its corresponding predicted decoding result match or approximate the labeled decoding result as closely as possible. For each of the n feature decoding networks, the loss function value corresponding to that feature decoding network can be determined using the above method.

[0148] After obtaining the loss function values ​​corresponding to each of the n feature decoding networks, the total loss function value can be obtained by weighting and summing these loss function values. This total loss function value is used to represent the overall performance of the neural network decoder. Furthermore, the weight values ​​corresponding to each feature decoding network may be the same or different, and this invention is not limited to this.

[0149] Subsequently, using gradient descent, the parameter tuning gradient of the neural network decoder is calculated with the goal of minimizing the total loss function value. Based on this parameter tuning gradient, the parameters of the neural network decoder to be trained are adjusted to obtain the trained neural network decoder. Here, the parameters of the neural network decoder include the weight parameters of each neural network included in the neural network decoder.

[0150] Furthermore, when using error canonical decomposition as the output (first decomposition method), it is necessary to ensure a one-to-one correspondence between inputs and outputs in the training data. This is because one input syndrome can lead to multiple output estimation syndromes. When dealing with TIFF0007848400000178.tif5170, the connections between reasoning syndromes are severed, therefore, in the case of a single input and multiple outputs, TIFF0007848400000179.tif5170 This is because it has a probability of causing a localized discrepancy in canonical syndrome reasoning. Unlike the inference of noise that occurs on physical bits, once a discrepancy in canonical syndrome reasoning occurs, TIFF0007848400000180.tif5170 has a probability of immediately causing a decoding failure. When generating training data directly from simulation data, it is not possible to guarantee a one-to-one correspondence between this input and output. Therefore, when using canonical representation decomposition, it is necessary to use a third-party decoder to generate a one-to-one corresponding input and output. A natural choice is to use an MWPM decoder to generate a single output based on the simulation-generated syndrome. If computational complexity is not a concern, one should also consider using a better, more complex known decoder. In this case, the two types of syndromes can be separated and used to decode two types of errors respectively (because this is the input / output pattern generated by MWPM), compressing the overall computational complexity while minimizing the increase in computational complexity.

[0151] In the second decomposition method, the canonical representation of the original error data generated in the simulation is directly used as the output label for multitask learning, while simultaneously using X and Z type syndromes as model inputs. This allows the same input syndrome to correspond to multiple output errors in the training set. This is because different results inferred based on the physical bit distribution only cause local residual physical bit errors at best, and do not result in logical errors. Furthermore, by learning the physical error distribution in addition to maximum likelihood learning, better decoding performance can be obtained.

[0152] In the actual training process, the classic Adam algorithm can be used for the two decomposition methods, and the batch size can be 1000 or more. The loss function corresponding to the feature decoding network is If we use TIFF0007848400000181.tif5170 (where i represents the i-th feature decoding network and takes a positive integer), we can sum up all the loss functions to generate the total loss function. TIFF0007848400000182.tif12170

[0153] Here, TIFF0007848400000183.tif4170 represents the total loss function of a neural network decoder. TIFF0007848400000184.tif5170 represents the loss function corresponding to the i-th feature decoding network, TIFF0007848400000185.tif5170 represents the weight values ​​of the loss function corresponding to the i-th feature decoding network. Then, the Adam algorithm is used to calculate the loss function Perform gradient descent multitask federated learning on TIFF0007848400000186.tif4170. In practice, all TIFF0007848400000187.tif5170 can be set to 1, and of course, it can also be set to other values. In each training epoch, the learning rate may be gradually decreased, or it may be increased initially and then decreased; you should handle it flexibly according to the actual situation.

[0154] In some embodiments, the block division is related to the correlation between errors, and qubits contained within the same block are more likely to generate related errors.

[0155] Here, the statement that qubits in the same block are more likely to generate related errors means that the probability of related errors occurring between qubits in the same block is greater than the probability of related errors occurring between qubits in different blocks.

[0156] For example, the probability of a Pauli X or Pauli Z error occurring between related qubits in the same block is greater than the probability of a Pauli X or Pauli Z error occurring between related qubits in different blocks.

[0157] As mentioned above, when employing the second decomposition method, the original errors generated during the simulation process can be used instead of training the model using indirect error data generated by other decoders. As mentioned above, in order to reduce the complexity of error correction algorithms on a large scale, physical qubits can be divided as follows. TIFF0007848400000188.tif5170

[0158] During multitasking learning, Error affecting TIFF0007848400000189.tif5170 TIFF0007848400000190.tif6170 and Only TIFF0007848400000191.tif6170 should be considered. Selecting TIFF0007848400000192.tif5170 significantly impacts decoding performance because, While keeping the number of qubits contained in TIFF0007848400000193.tif5170 within a certain constant, This is because it is desirable for TIFF0007848400000194.tif5170 to cover as many local error associations as possible. The most typical error association among these is that produced by the syndrome measurement circuit. As shown in Figure 16, the typical associated errors generated by the syndrome measurement circuit are the two-body X and Z errors along the shaded lines, where dotted box 161 represents the two-body X error and dotted box 162 represents the two-body Z error. Therefore, the bit region When splitting TIFF0007848400000195.tif4170, it is necessary to include as many of these diagonal distributions as possible for the two types of errors.

[0159] Figure 17 shows Qubit partitioning scheme for Z error in the case of TIFF0007848400000196.tif4170 This shows TIFF0007848400000197.tif5170. In Figure 17, each small white circle represents a physical qubit, and each physical qubit connected by a dark black line belongs to the same block. Looking at this scheme from bottom to top, The quantities for TIFF0007848400000198.tif5170 are as follows: TIFF0007848400000199.tif5170 Pauli errors contained in 170 physical qubits The filename is TIFF0007848400000200.tif5170. In the case of an X-type error, each subset of the divided qubits needs to be rotated by 90 degrees.

[0160] When dividing the physical qubits of a quantum circuit into blocks, considering the relationships between errors makes it easier to generate related errors among the qubits in the same block, which helps to further improve decoding performance.

[0161] In some embodiments, during the training process of the neural network decoder, the qubits contained in the sample quantum circuit are divided using multiple different block partitioning schemes, and associative training is performed on the neural network decoder based on these multiple different block partitioning schemes. During the use process of the neural network decoder, the qubits contained in the quantum circuit are divided using one of the multiple different block partitioning schemes.

[0162] Considering a second type of decoder, after end-to-end training using the original errors generated during the simulation process, a so-called error floor phenomenon appears in the decoding effect within a low physical error rate range. That is, at a low physical error rate, the logical error decreases very slowly as the physical error decreases, losing the original decoding effect of the error correction code.

[0163] This is because, when the physical error rate is sufficiently low, higher-order related errors play the dominant role. And these errors are Same area as TIFF0007848400000201.tif5170 It is difficult to completely cover all of these simultaneously within TIFF0007848400000202.tif5170. Therefore, when decoding, the marginal probabilities obtained cannot cover all of these relationships. At the same time, the region The size of TIFF0007848400000203.tif5170 needs to be kept within a certain range, and the complexity of the output terminals needs to be reduced. In practice, unless all physical bits are covered, In TIFF0007848400000204.tif5170, a larger number of qubits is not necessarily better; more important is whether it effectively contains possible higher-order related noise. Under this constraint, to reduce the impact of higher-order related noise, a method is used that employs multiple types of partitioning and performs cross-validation during training. The specific method is as follows:

[0164] The following TIFF0007848400000205.tif4170 types of partitioning are considered. TIFF0007848400000206.tif37170

[0165] These divisions should be designed to produce the maximum possible differentiation, while acknowledging the differences in associated noise. Figure 18 shows that This shows an alternative partitioning of the qubits in TIFF0007848400000207.tif4170, which differs from the partitioning method shown in Figure 17.

[0166] During the training phase, the backend of the decoding neural network is: TIFF0007848400000208.tif7170 multitask networks are deployed simultaneously to support 170 partitions. During the training phase, federated training is performed on the distribution of corresponding regions of these different partitions. Specifically, the total loss function needs to be redefined as follows. TIFF0007848400000209.tif12170

[0167] Furthermore, learning is performed using stochastic gradient descent. This fulfills the purpose of cross-validation during the training phase and eliminates the influence of higher-order related errors as much as possible during the training phase. Once training is complete, during actual decoding, only one of these splits is used, for example, Use TIFF0007848400000210.tif7170. While this increases the training complexity, it does not change the complexity or computation time of the error correction algorithm itself, and therefore does not affect the actual decoding delay or implementation in engineering. Simulation experiments showed that, It has been shown that TIFF0007848400000211.tif4170 alone can largely eliminate the effects of higher-order related errors and significantly improve the logical error rate of error correction algorithms in the low physical error rate range.

[0168] In some embodiments, the chip implementing the neural network decoder described above may employ a single-core architecture or a multi-core architecture. Here, single-core architecture and multi-core architecture refer to the number of processors (or processing cores, also called cores) included.

[0169] When a single-core architecture is adopted, the chip includes a single processor, which performs all the steps of the neural network decoder described in the above embodiment. As described above, the computational complexity of the decoding method provided in this application is The file TIFF0007848400000212.tif6170 shows that while a single-core architecture can tolerate this computational complexity when L is small, it has limitations when L is large. Therefore, this application proposes a multi-architecture solution.

[0170] When a multicore architecture is adopted, the chip includes multiple processors in a tree structure. In the embodiment of the present invention, the number of processors included in the chip in the multicore architecture is not limited, and specifically, it can be designed considering the size of L and the computational complexity, and the overall decoding algorithm can be executed assuming that the computing power of each processor is fully utilized.

[0171] When a multicore architecture is adopted, any two processors that do not have a connection relationship can be parallelized, thereby maximizing the computing power of each processor and shortening the decoding time. Also, any two processors that do have a connection relationship can be executed sequentially. For example, Figure 19 shows a schematic diagram of a multicore architecture. Processors 1 to p do not have a connection relationship with each other, and these p processors can be executed in parallel. For example, different blocks of error syndrome information can be processed in parallel using a partitioning method, and / or local feature extraction mapping can be performed on different input data blocks using LFEM (Local Feature Extraction Mapping). Feature data extracted by processors 1 to p is sent to processor p+1, which processes the feature data provided by processors 1 to p and obtains feature information. Subsequently, this feature information is input to processors p+2 to N, respectively. Processors p+2 to N do not have a connection relationship with each other, and these multiple processors can be executed in parallel. One feature decoding network is implemented in each processor, and decoding processing is performed on the feature information to obtain the corresponding decoding result. Finally, a processor can determine error result information based on the decoding results corresponding to each feature decoding network.

[0172] For multiple processors that execute in parallel, the information to be processed is sent to each processor simultaneously, enabling parallel execution. For example, in the above example, different blocks of error syndrome information can be sent simultaneously to processors 1 to p, thereby enabling parallel execution among those p processors. In another example, feature information can be sent simultaneously to processors p+2 to N, thereby enabling parallel execution among those multiple processors. In some other embodiments, a single controller or processor can be installed to control the execution sequence of each processor. For example, by controlling multiple parallel processors to start execution simultaneously, or by controlling serial processors to process sequentially, the operation of each processor can be coordinated more appropriately, ensuring the accuracy and stability of the processing flow.

[0173] The neural network decoder based on multitask learning provided in this application has intrinsic parallelism in both its feature extraction and feature decoding portions, allowing it to be easily distributed and executed across multiple different processors. Furthermore, the inputs to different processors are almost independent, requiring minimal communication between processors, with data transmission only occurring between a small number of processors. This method is, in principle, infinitely parallelizable, and the computational scale can always be expanded by adding processors to fully utilize each processor. The decoding delay for TIFF0007848400000213.tif5170 can be maintained.

[0174] Simulation experiments have shown that the technical solution provided in this application can bring about several improvements, including the following:

[0175] 1. Reduce the number of models and simplify the implementation of hardware systems. Regardless of the scale of the error correction code, two models are used: one that outputs X-type errors and another that outputs Z-type errors. Given the current computing power of FPGAs, we first focus on the first type of decoder (output-end error canonical decomposition). As shown in the simulation results in Figure 20, decoding performance for different output canonical syndrome sizes is demonstrated after training with indirect training data generated by MWPM. In this case, it can be seen that the decoding performance is almost independent of the output canonical syndrome size. Furthermore, even when using only two models, the decoding performance is almost comparable to that trained with an MWPM decoder, and is particularly remarkable for low physical error rates. This demonstrates that the shared front-end of the multi-task learning decoder provided in this application can reliably capture all the feature information necessary for high-performance decoding.

[0176] Regarding the performance of the actual hardware implementation, This study will examine the case of TIFF0007848400000214.tif4170 (a total of 49 data bits and auxiliary bits) and 10 syndrome measurements. We will consider splitting the output terminal into three outputs, each TIFF0007848400000215.tif7170 and two canonical syndromes, each containing 12 bits of information. TIFF0007848400000216.tif7170, This corresponds to TIFF0007848400000217.tif7170. The corresponding model uses 330,000 parameters. After 8-bit unsigned quantization (UINT8) of this model, the two networks are implemented on two Intel Stratix 10 SX FPGAs, one for each network. As shown in Figure 21, 201 and 202 in the figure represent the two Intel Stratix 10 SX FPGAs, used for decoding X-type errors and Z-type errors, respectively.

[0177] To simulate the entire decoding process, the computer simulates the generation of quantum noise and the execution of a noise-inclusive syndrome measurement circuit. After 10 syndrome measurements, the resulting syndromes (120 classical bits of information) are divided into X-type and Z-type syndromes (60 each) and transmitted to two FPGAs via different network ports. After the FPGAs complete decoding, the error information obtained from the decoding is sent back to the computer to determine whether the decoding was successful. After a large-scale Monte Carlo simulation, the FPGA decoding performance is shown in Figure 22, with an overall decoding delay of 700 ns. Using the higher-performance Intel Stratix 10 SX and starting decoding when some of the syndromes are received, the total time from syndrome reception to completion of the entire decoding process was 280 ns, achieving the fastest record for 49-bit hardware decoding.

[0178] 2. Significant improvement in decoding performance By using a second type of decoder and employing the following method, decoding performance can be significantly improved.

[0179] (1) Error decomposition of the second type (2) Use two types of syndromes simultaneously as the output of decoding. (3) Output area partitioning considering the patterns of related errors (4) Associative learning and cross-validation in the training phase using multiple different partitioning schemes The decoder provided in this application can significantly improve actual decoding capabilities with low computational complexity, network complexity, and computational depth.

[0180] Figure 23 shows, TIFF0007848400000218.tif4170 and The case of TIFF0007848400000219.tif4170 (corresponding to 49 and 97 physical bits respectively, including data bits and auxiliary bits) is shown. As can be seen from the figure, in all physical error regions, the second type of decoder exhibits superior decoding performance compared to MWPM, and its logical error rate is less than half that of MWPM. This is one of the best fault-tolerant decoders known to date.

[0181] The following are embodiments of the apparatus of the present application, which are used to carry out embodiments of the method of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the method of the present application.

[0182] Figure 24 is a block diagram of a neural network-based quantum error correction and decoding device according to one embodiment of the present invention. The device has functions to implement the above-described method example, and these functions can be implemented in hardware or by running corresponding software in hardware. The device may be a computer device or may be installed on a computer device. The device 2400 may include a syndrome acquisition module 2410, a feature extraction module 2420, a feature decoding module 2430, and a result determination module 2440.

[0183] The syndrome acquisition module 2410 is configured to acquire error syndrome information obtained by performing syndrome measurements on a quantum circuit.

[0184] The feature extraction module 2420 is configured to extract feature information from the error syndrome information using a neural network decoder, where the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0185] The feature decoding module 2430 is configured to perform decoding processing on the feature information using the neural network decoder and obtain the decoding result.

[0186] The result determination module 2440 is configured to determine error result information of the quantum circuit based on the decoding result.

[0187] In some embodiments, the feature extraction module 2420 is configured to extract features from the error syndrome information via a feature extraction network of a neural network decoder to obtain feature information, where the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1.

[0188] The feature decoding module 2430 is configured to perform decoding on the feature information through the n feature decoding networks, and to obtain a decoding result corresponding to each of the n feature decoding networks, where the n feature decoding networks are networks trained in a multi-task learning manner to have the ability to generate different decoding results.

[0189] The result determination module 2440 is configured to determine error result information based on the decoding results corresponding to each of the n feature decoding networks.

[0190] In some embodiments, the qubits included in the quantum circuit are divided into n blocks, each block containing at least one qubit. For the k-th feature decoding network among the n feature decoding networks, the decoding result corresponding to the k-th feature decoding network includes a Pauli operator acting on the qubits included in the k-th block among the n blocks, where k is a positive integer less than or equal to n.

[0191] The result determination module 2440 is configured to determine the error result information based on the Pauli operators that act on each of the n blocks.

[0192] In some embodiments, the error result information indicates the qubits in the quantum circuit that have experienced a Pauli X error and the qubits that have experienced a Pauli Z error.

[0193] In some embodiments, the division of the blocks relates to the correlation between errors, and qubits contained within the same block are more likely to generate related errors.

[0194] In some embodiments, during the training process of the neural network decoder, the qubits contained in the sample quantum circuit are divided using a plurality of different block partitioning schemes, and federated training is performed on the neural network decoder based on the plurality of different block partitioning schemes. During the use process of the neural network decoder, the qubits contained in the quantum circuit are divided using one of the plurality of different block partitioning schemes.

[0195] In some embodiments, the feature decoding module 2430 is Each of the n1 feature decoding networks performs a decoding process on the feature information, and a decoding result corresponding to each of the n1 feature decoding networks is obtained. For the i-th feature decoding network among the n1 feature decoding networks, the decoding result corresponding to the i-th feature decoding network includes the i-th canonical syndrome related to the target error type, where i is a positive integer less than or equal to n1, and the canonical syndrome refers to the canonical decomposition result of the error syndrome information. n2 feature decoding networks are respectively configured to perform decoding processing on the feature information to obtain decoding results respectively corresponding to the n2 feature decoding networks. Here, for the j-th feature decoding network among the n2 feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element related to the target error type, and j is a positive integer not exceeding n2. Here, the sum of n1 and n2 is equal to n, and n1 and n2 are positive integers.

[0196] In some embodiments, the target error type includes Pauli X error and Pauli Z error, n1 is equal to the sum of m1 and m2, m1 and m2 are positive integers, and n2 is 2. m1 of the n1 feature decoding networks are respectively configured to perform decoding processing on the feature information and are used to obtain m1-term canonical syndromes related to the Pauli X error. m2 of the n1 feature decoding networks are respectively configured to perform decoding processing on the feature information and are used to obtain m2-term canonical syndromes related to the Pauli Z error. One of the n2 feature decoding networks is configured to perform decoding processing on the feature information and is used to obtain a fixed representative element related to the Pauli X error. Another one of the n2 feature decoding networks is configured to perform decoding processing on the feature information and is used to obtain a fixed representative element related to the Pauli Z error. [[ID=十六]]The result determination module 2440 [[ID=十七]] determines X-type error result information based on the fixed representative element related to the Pauli X error and the m1-term canonical syndrome related to the Pauli X error. The X-type error result information indicates the qubit where the Pauli X error occurs in the quantum circuit. configured to determine Z-type error result information based on a fixed representative element associated with the Pauli Z error and a canonical syndrome of m2 terms associated with the Pauli Z error, wherein the Z-type error result information indicates a qubit in which the Pauli Z error has occurred in the quantum circuit.

[0197] In some embodiments, the feature extraction network includes a plurality of cascaded feature extraction sub-networks. Here, the input data of the first feature extraction sub-network includes the error syndrome information, the input data of the s-th feature extraction sub-network includes the output data of the (s - 1)-th feature extraction sub-network, and the output data of the last feature extraction sub-network includes the feature information, where s is an integer greater than 1. For a target feature extraction sub-network among the plurality of cascaded feature extraction sub-networks, the input data of the target feature extraction sub-network is divided into a plurality of input data blocks with the same scale. The target feature extraction sub-network is used to perform a plurality of local feature extraction mappings on the plurality of input data blocks to obtain a plurality of sets of mapping output data. Here, each local feature extraction mapping is used to perform mapping processing on regions at the same position in the plurality of input data blocks to obtain a set of mapping output data, and different numbers of local feature extraction mappings are used to perform mapping processing on regions at different positions in the plurality of input data blocks to obtain the plurality of sets of mapping output data. The target feature extraction sub-network is further used to obtain the output data of the target feature extraction sub-network based on the plurality of sets of mapping output data.

[0198] In some embodiments, there is an overlap between the regions at different positions.

[0199] In some embodiments, the target feature extraction subnetwork includes at least one convolutional layer and at least one fully connected layer. The at least one convolutional layer is used to perform the multiple local feature extraction mappings on the multiple input data blocks and to obtain the multiple sets of mapping output data. The at least one fully connected layer is used to obtain the output data of the target feature extraction subnetwork based on the multiple sets of mapping output data.

[0200] In some embodiments, the neural network decoder performs a process of measuring and collecting new error syndrome information in parallel with the process of decoding the error syndrome information that has already been acquired.

[0201] In some embodiments, the training process of the neural network decoder is as follows: To obtain sample error syndrome information and sample error result information corresponding to the sample error syndrome information sample, The neural network decoder being trained obtains predictive decoding results corresponding to each of the n feature decoding networks based on the sample error syndrome information, Based on the predicted decoding results corresponding to each of the n feature decoding networks, and the labeled decoding results corresponding to each of the n feature decoding networks determined based on the sample error result information, the loss function value corresponding to each of the n feature decoding networks is determined. The total loss function value is determined based on the loss function value corresponding to each of the n feature decoding networks. This includes adjusting the parameters of the neural network decoder to be trained based on the total loss function value, thereby obtaining the trained neural network decoder.

[0202] In some embodiments, the feature extraction network and the n feature decoding networks included in the neural network decoder are located on the same chip.

[0203] In some embodiments, the chip on which the neural network decoder is located includes a tree structure of multiple processors, where any two processors that do not have a connection relationship are parallel.

[0204] Furthermore, the above-described division of the functional modules in the apparatus provided in the above embodiment is merely illustrative in terms of how it realizes its functions. In actual applications, the above functions can be assigned to different functional modules as needed. In other words, all or part of the functions described above can be performed by dividing the internal structure of the device into different functional modules. Also, the apparatus provided in the above embodiment belongs to the same concept as the method embodiment, and its specific implementation process can be found in the method embodiment, which will not be described again here.

[0205] Referring to Figure 25, which is a schematic diagram showing the structure of a computer device according to an embodiment of the present application, this computer device may be the control device 43 in the application scenario of the configuration shown in Figure 4. This computer device can be used to implement the neural network-based quantum error correction decoding method according to the above embodiment. Specifically, this is as follows.

[0206] The computer device 2500 includes a processing unit 2501 (including, for example, a CPU and / or GPU), a system memory 2504 including random access memory (RAM) 2502 and read-only memory (ROM) 2503, and a system bus 2505 connecting the system memory 2504 and the processing unit 2501. The computer device 2500 further includes a basic input / output system (I / O system) 2506 that assists in the transmission of information between devices within the computer device, and a mass storage device 2507 that stores an operating system 2513, applications 2514, and other program modules 2515.

[0207] The basic input / output system 2506 includes a display 2508 for displaying information and input devices 2509 such as a mouse or keyboard for the user to input information. Here, both the display 2508 and the input devices 2509 are connected to the processing unit 2501 via an input / output controller 2510 connected to a system bus 2505. The basic input / output system 2506 may further include an input / output controller 2510 for receiving and processing input from a keyboard, mouse, or any other device such as an electronic stylus.

[0208] The mass storage device 2507 is connected to the processing unit 2501 via a mass storage controller (not shown) connected to the system bus 2505. The mass storage device 2507 and its associated computer-readable media provide non-volatile storage to the computer equipment 2500. In other words, the mass storage device 2507 may include a computer-readable media (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0209] Without loss of generality, the computer-readable medium may include computer storage media and communication media. Computer storage media include volatile and non-volatile, removable and non-removable media implemented in any method or technique for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include RAM, ROM, EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other solid-state storage device technologies, CD-ROM, DVD (Digital Video Disc) or other optical storage devices, magnetic tape cartridges, magnetic tapes, disk storage, or other magnetic storage devices. Of course, those skilled in the art will see that the computer equipment is not limited to those described above. The system memory 2504 and mass storage device 2507 described above may be collectively referred to as memory.

[0210] According to various embodiments of the present application, the computer device 2500 can also be connected to and run on a remote computer device connected to a network, such as the Internet. That is, the computer device 2500 may be connected to a network 2512 via a network interface unit 2511 connected to the system bus 2505, or it may be connected to another type of network or remote computer system (not shown) using the network interface unit 2511.

[0211] The memory stores a computer program, which causes one or more processors to execute the quantum error correction decoding method based on the neural network according to the above embodiment.

[0212] In an exemplary embodiment, a computer-readable storage medium is provided on which a computer program is stored, and the computer program causes the processor of a computer device to execute a quantum error correction decoding method based on a neural network according to the above embodiment. In the exemplary embodiment, the computer-readable storage medium may be a ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

[0213] In an exemplary embodiment, a computer program product is further provided, which, when the chip is executed, is used to implement a quantum error correction decoding method based on a neural network according to the above embodiment.

[0214] In an exemplary embodiment, a chip is further provided which includes a programmable logic circuit and / or program instructions, which causes a computer device to execute a quantum error correction decoding method based on a neural network according to the above embodiment.

[0215] Selectively, the chip is either an FPGA chip or an ASIC chip.

Claims

1. A quantum error correction decoding method based on a neural network, which is performed by a control device, The steps include obtaining error syndrome information obtained by performing syndrome measurements on a quantum circuit, and A step of extracting feature information from the error syndrome information using a neural network decoder, The neural network decoder performs a decoding process on the feature information and obtains a decoding result. The steps include determining error result information of the quantum circuit based on the decoding result, The step of extracting feature information from the error syndrome information using the neural network decoder is as follows: The process includes the step of extracting features from the error syndrome information using the feature extraction network of the neural network decoder to obtain feature information, wherein the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1. The step of performing a decoding process on the feature information using the neural network decoder and obtaining the decoding result is as follows: The step includes performing a decoding process on the feature information using the n feature decoding networks, and obtaining a decoding result corresponding to each of the n feature decoding networks, wherein the n feature decoding networks are networks trained in a multi-task learning manner to have the ability to generate different decoding results. The step of determining the error result information of the quantum circuit based on the decoding result is: A quantum error correction decoding method comprising the step of determining the error result information based on the decoding results corresponding to each of the n feature decoding networks.

2. The qubits included in the quantum circuit are divided into n blocks, and each block contains at least one qubit. For the k-th feature decoding network among the n feature decoding networks, the decoding result corresponding to the k-th feature decoding network includes a Pauli operator acting on the qubits contained in the k-th block among the n blocks, where k is a positive integer less than or equal to n. The step of determining the error result information based on the decoding results corresponding to each of the n feature decoding networks is as follows: The step includes determining the error result information based on the Pauli operators acting on each of the n blocks, The quantum error correction decoding method according to claim 1.

3. The aforementioned error result information indicates the qubits in the quantum circuit that have experienced a Pauli X error and the qubits that have experienced a Pauli Z error. The quantum error correction decoding method according to claim 2.

4. The division of the aforementioned blocks is related to the relationships between errors, and the probability of a related error occurring between qubits in the same block is greater than the probability of a related error occurring between qubits in different blocks. The quantum error correction decoding method according to claim 2.

5. In the training process of the neural network decoder, the qubits included in the sample quantum circuit are divided using multiple different block partitioning schemes, and federated training is performed on the neural network decoder based on the multiple different block partitioning schemes. In the process of using the neural network decoder, the qubits included in the quantum circuit are divided using one of the multiple different block partitioning methods. The quantum error correction decoding method according to claim 2.

6. The step of performing a decoding process on the feature information using the n feature decoding networks and obtaining a decoding result corresponding to each of the n feature decoding networks is: n １ Each of the feature decoding networks performs a decoding process on the feature information, and the n １ A step of obtaining a decoding result corresponding to each of the n feature decoding networks, wherein the n １ For the i-th feature decoding network among the i-th feature decoding network, the decoding result corresponding to the i-th feature decoding network includes the i-th canonical syndrome related to the target error type, where i is n １ Step and a positive integer, wherein the canonical syndrome refers to the canonical decomposition result of the error syndrome information. n ２ Each of the feature decoding networks performs a decoding process on the feature information, and the n ２ A step of obtaining a decoding result corresponding to each of the n feature decoding networks, wherein the n ２ For the j-th feature decoding network among the feature decoding networks, the decoding result corresponding to the j-th feature decoding network includes a fixed representative element related to the target error type, where j is n ２ The following are positive integers, including step and , n １ and n ２ The sum of which is equal to n, n １ and n ２ are positive integers, The quantum error correction decoding method according to claim 1.

7. The aforementioned target error types include Pauli X errors and Pauli Z errors, n １ ham １ Tom ２ The sum is equal to m １ Tom ２ n is a positive integer, and ２ It is 2, The aforementioned n １ m of the feature decoding networks １ Each feature decoding network performs a decoding process on the feature information, and the m related to the Pauli X error １ Used to obtain the canonical syndrome of the item, The aforementioned n １ m of the feature decoding networks ２ Each feature decoding network performs a decoding process on the feature information, and the m associated with the Pauli Z error ２ Used to obtain the canonical syndrome of the item, The aforementioned n ２ One of the feature decoding networks is used to perform a decoding process on the feature information and obtain a fixed representative element related to the Pauli X error. The aforementioned n ２ One of the feature decoding networks is used to perform a decoding process on the feature information and obtain a fixed representative element related to the Pauli Z error. The step of determining the error result information based on the decoding results corresponding to each of the n feature decoding networks is as follows: The fixed representative element related to the Pauli X error, and the m related to the Pauli X error. １ A step of determining X-type error result information based on the canonical syndrome of the term, wherein the X-type error result information indicates the qubit in the quantum circuit where the Pauli X error occurred. The fixed representative element related to the Pauli Z error, and the m related to the Pauli Z error. ２ A step of determining Z-type error result information based on the canonical syndrome of the term, wherein the Z-type error result information indicates a qubit in the quantum circuit where the Pauli Z error occurred, The quantum error correction decoding method according to claim 6.

8. The feature extraction network includes a plurality of cascaded feature extraction subnetworks, where the input data of the first feature extraction subnetwork includes the error syndrome information, the input data of the s-th feature extraction subnetwork includes the output data of the s-1-th feature extraction subnetwork, and the output data of the last feature extraction subnetwork includes the feature information, where s is an integer greater than 1. Regarding the target feature extraction subnetwork among the multiple cascaded feature extraction subnetworks, the input data of the target feature extraction subnetwork is divided into multiple input data blocks of the same scale. The target feature extraction subnetwork is used to perform multiple local feature extraction mappings on the multiple input data blocks to obtain multiple sets of mapping output data, each local feature extraction mapping is performed on the same location region in the multiple input data blocks to obtain one set of mapping output data, and different numbers of local feature extraction mappings are used to perform mapping on different locations region in the multiple input data blocks to obtain multiple sets of mapping output data. The aforementioned target feature extraction subnetwork is further used to obtain output data of the target feature extraction subnetwork based on the multiple sets of mapping output data. The quantum error correction decoding method according to claim 1.

9. There is an overlap between the regions at the different locations mentioned above. The quantum error correction decoding method according to claim 8.

10. The aforementioned target feature extraction subnetwork includes at least one convolutional layer and at least one fully connected layer. The at least one convolutional layer is used to perform the multiple local feature extraction mappings on the multiple input data blocks and to obtain the multiple sets of mapping output data. The at least one fully connected layer is used to obtain the output data of the target feature extraction subnetwork based on the multiple sets of mapping output data. The quantum error correction decoding method according to claim 8.

11. In the process by which the neural network decoder decodes the error syndrome information already acquired, it executes the process of measuring and collecting new error syndrome information in parallel. The quantum error correction decoding method according to claim 1.

12. The training process of the aforementioned neural network decoder is as follows: To obtain sample error syndrome information and sample error result information corresponding to the sample error syndrome information sample, The neural network decoder being trained obtains predictive decoding results corresponding to each of the n feature decoding networks based on the sample error syndrome information, Based on the predicted decoding results corresponding to each of the n feature decoding networks, and the labeled decoding results corresponding to each of the n feature decoding networks determined based on the sample error result information, the loss function value corresponding to each of the n feature decoding networks is determined. The total loss function value is determined based on the loss function values ​​corresponding to each of the n feature decoding networks. This includes adjusting the parameters of the neural network decoder being trained based on the total loss function value, thereby obtaining the trained neural network decoder. The quantum error correction decoding method according to claim 1.

13. The feature extraction network and the n feature decoding networks included in the neural network decoder are arranged on the same chip. The quantum error correction decoding method according to claim 1.

14. The chip on which the neural network decoder is located includes a tree structure of multiple processors, and any two processors that do not have a connection relationship are parallel. The quantum error correction decoding method according to claim 1.

15. A quantum error correction and decoding device based on a neural network, A syndrome acquisition module configured to acquire error syndrome information obtained by performing syndrome measurements on a quantum circuit, A feature extraction module configured to extract feature information from the error syndrome information using a neural network decoder, wherein the neural network decoder includes a feature extraction network and n feature decoding networks, where n is an integer greater than 1, and A feature decoding module configured to perform decoding processing on the feature information using the neural network decoder and obtain a decoding result, The system includes a result determination module configured to determine error result information of the quantum circuit based on the decoding result, The feature extraction module is configured to extract features from the error syndrome information using the feature extraction network of the neural network decoder and obtain feature information, and the neural network decoder includes the feature extraction network and n feature decoding networks, where n is an integer greater than 1. The feature decoding module is configured to perform decoding on the feature information using the n feature decoding networks, and to obtain a decoding result corresponding to each of the n feature decoding networks. The n feature decoding networks are networks trained using a multi-task learning method to have the ability to generate different decoding results. The result determination module is configured to determine the error result information based on the decoding results corresponding to each of the n feature decoding networks, in a quantum error correction decoding device.

16. A computer device comprising a processor and memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to realize the quantum error correction decoding method described in any one of claims 1 to 14.

17. A computer program that causes a processor to execute the quantum error correction decoding method described in any one of claims 1 to 14.

18. A chip on which a neural network decoder is arranged, wherein the neural network decoder is used to realize the quantum error correction decoding method described in any one of claims 1 to 14.

Images