Display panels and display devices

Abstract

A display panel and a display device are provided. The display panel includes a base substrate and a conductive member. The conductive member is located on the base substrate and includes a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer stacked in sequence. The first conductive sublayer is closer to the base substrate than the third conductive sublayer. The conductivity of the first conductive sublayer is lower than that of the second conductive sublayer. The melting point of the third conductive sublayer is higher than that of the second conductive sublayer. The second conductive sublayer has a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer. The first surface and the second surface are disposed opposite each other. The third conductive sublayer protrudes from the second surface along a width direction of the conductive member, the width direction intersecting the extension direction of the conductive member. A display device including the display panel can reduce the risk of electrostatic discharge damage.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims the priority of a Chinese patent application with application number 202010435328.1 filed on May 21, 2020, and the entire content disclosed in the above - mentioned Chinese patent application is incorporated herein by reference as part of this application.

[0002] At least one embodiment of the present disclosure relates to a display panel and a display device.

Background Art

[0003] The daily development of display devices, such as Liquid Crystal Display (LCD) devices, Active Matrix Organic Light - Emitting Diode (AMOLED) devices, Micro - Light - Emitting Diode (Micro - LED) devices, etc., has greatly enriched people's lives, and consumers' pursuit of the quality of display panels has also increased. For example, display panels with higher resolution (8K), higher refresh rates (90HZ, 120HZ) and more product forms (foldable, curlable) have been developed. With the improvement of the quality of display panels, new challenges have also been brought to the manufacturing process of display panels.

Summary of the Invention

Means for Solving the Problems

[0004] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0005] At least one embodiment of the present disclosure provides a display panel. The display panel includes a display area having a plurality of pixel units, a peripheral area located on at least one side of the display area, a barrier layer located on a base substrate, and a conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially stacked and provided on one side of the barrier layer away from the base substrate, with the length in its extension direction being greater than the width in a direction intersecting the extension direction, wherein the first conductive sublayer comprises a conductive member closer to the base substrate than the third conductive sublayer, and a first conductive portion located in the display area and provided in the same layer as the conductive member and made of The conductive member comprises a first conductive portion having the same material, wherein the conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, the melting point of the third conductive sublayer is higher than that of the second conductive sublayer, the second conductive sublayer comprises a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, the first surface and the second surface are provided opposite to each other, the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, and the width direction intersects with the elongation direction of the conductive member.

[0006] Based on a display panel according to one or more embodiments of the present disclosure, the third conductive sublayer does not come into contact with the first conductive sublayer.

[0007] Based on a display panel according to one or more embodiments of the present disclosure, the second conductive sublayer further includes a side surface connecting the sides of the first surface and the second surface located on the same side of the second conductive sublayer, wherein in a cross section cut in an elongation direction perpendicular to the conductive member, the intersection of the side surface and the first conductive sublayer is a first intersection, the intersection of the side surface and the third conductive sublayer is a second intersection, and at least a portion of the side surface is located on one side closer to the second conductive sublayer than the connection line between the first intersection and the second intersection.

[0008] Based on a display panel according to one or more embodiments of the present disclosure, the side surface includes at least two sub-side surfaces, the at least two sub-side surfaces including a first sub-side surface adjacent to the first conductive sub-layer and a second sub-side surface adjacent to the third conductive sub-layer, wherein the angle between the first sub-side surface and the first conductive sub-layer is smaller than the angle between the second sub-side surface and the first conductive sub-layer.

[0009] Based on a display panel according to one or more embodiments of the present disclosure, in the cross section cut in an elongation direction perpendicular to the conductive member, the distance between the intersection of the extension line of the second sub-side and the first conductive sub-layer and the intersection of the first sub-side and the first conductive sub-layer is d1, the distance by which the first conductive sub-layer extends beyond the first surface is Δw1, and d1 < Δw1.

[0010] Based on a display panel according to one or more embodiments of the present disclosure, the distance by which the third conductive sublayer extends beyond the second surface is Δw2, and d1 < Δw2.

[0011] Based on one or more embodiments of the present disclosure, the angle between the second sub-side and the first conductive sub-layer is greater than 90 degrees.

[0012] Based on a display panel according to one or more embodiments of the present disclosure, the side surface includes three sequentially provided sub-side surfaces, the three sub-side surfaces including a first sub-side surface, a second sub-side surface, and a third sub-side surface, wherein the first sub-side surface is closer to the first conductive sub-layer than the third sub-side surface, the angle between the first sub-side surface and the first conductive sub-layer is a first angle, the angle between the second sub-side surface and the first conductive sub-layer is a second angle, and the angle between the third sub-side surface and the first conductive sub-layer is a third angle, the third angle being greater than the second angle, and the second angle being greater than the first angle.

[0013] Based on a display panel according to one or more embodiments of the present disclosure, the second conductive sublayer includes two sides, the two sides are arranged opposite to each other, and the two sides are arranged symmetrically along the thickness direction of the conductive member.

[0014] Based on one or more embodiments of the present disclosure, the display panel wherein at least one of the first surface, the second surface and the side surface of the second conductive sublayer contains at least one of N, S, P and Cl elements.

[0015] Based on one or more embodiments of the present disclosure, the barrier layer comprises at least one of the elements F and Cl.

[0016] Based on a display panel according to one or more embodiments of the present disclosure, the content of at least one of the F element and the Cl element in the barrier layer is 1 × 10 per cubic centimeter. 18 ~5×10 20 It is an individual atom.

[0017] Based on one or more embodiments of the present disclosure, the display panel is configured such that the first surface is in contact with the first conductive sublayer, and the second surface is in contact with the third conductive sublayer.

[0018] Based on a display panel according to one or more embodiments of the present disclosure, the third conductive sublayer covers the second conductive sublayer and is in contact with the first conductive sublayer.

[0019] Based on a display panel according to one or more embodiments of the present disclosure, the width of the first surface is smaller than the width of the first conductive sublayer, the width of the second surface is smaller than the width of the third conductive sublayer, and the difference in width between the third conductive sublayer and the second surface is greater than the thickness of the third conductive sublayer.

[0020] Based on a display panel according to one or more embodiments of the present disclosure, two adjacent conductive members are provided, the two adjacent conductive members being insulated from each other and located in the same layer, comprising a first conductive member and a second conductive member, wherein the distance between the third conductive sublayer of the first conductive member and the third conductive sublayer of the second conductive member is smaller than the distance between the second surface of the second conductive sublayer of the first conductive member and the second surface of the second conductive sublayer of the second conductive member.

[0021] Based on a display panel according to one or more embodiments of the present disclosure, the distance between the second surface of the first conductive member and the second surface of the second conductive member is different at different positions.

[0022] Based on a display panel according to one or more embodiments of the present disclosure, w1 is the maximum width in the widthwise cross-section of the first conductive member, w2 is the maximum width in the widthwise cross-section of the second conductive member, Δw11 is the distance at which the third conductive sublayer in the first conductive member extends beyond the second surface, Δw12 is the distance at which the third conductive sublayer in the second conductive member extends beyond the second surface, and dmin is the minimum distance between the first conductive member and the second conductive member, satisfying the following relationship.

number

[0023] Based on a display panel according to one or more embodiments of the present disclosure, two conductive members are provided, the two conductive members are insulated from each other, the distances from the two conductive members to the base substrate are different, the two conductive members include a first conductive member and a second conductive member, the thickness of the first conductive member is T3, the thickness of the second conductive member is T4, T4 is greater than T3, the distance by which the third conductive sublayer in the first conductive member extends beyond the second surface is Δw3, and the distance by which the third conductive sublayer in the second conductive member extends beyond the second surface is Δw4, satisfying the following relation.

number

[0024] Based on the display panel according to one or more embodiments of the present disclosure, two conductive members are provided. The two conductive members are insulated from each other and include a first conductive member and a second conductive member. The first conductive member is closer to the display area than the second conductive member. The dimension by which the third conductive sub-layer in the first conductive member protrudes from the second surface is larger than the dimension by which the third conductive sub-layer in the second conductive member protrudes from the second surface.

[0025] Based on the display panel according to one or more embodiments of the present disclosure, the display panel further includes a second conductive portion. The second conductive portion and the conductive member are provided in different layers. The conductive member has a first end portion, the second conductive portion has a second end portion, and an insulating layer is provided between the first end portion and the second end portion. The insulating layer has a first via hole exposing the first end portion or the second end portion. The conductive member is connected to the second conductive portion through the first via hole.

[0026] Based on the display panel according to one or more embodiments of the present disclosure, the display panel further includes a second conductive portion. The second conductive portion and the conductive member are located in the same layer.

[0027] Based on the display panel according to one or more embodiments of the present disclosure, the display panel further includes a third conductive portion. The first conductive portion is electrically connected to the third conductive portion. The third conductive portion has a third end portion, the first conductive portion has a fourth end portion, and an insulating layer is provided between the third end portion and the fourth end portion. The insulating layer has a second via hole exposing the third end portion or the fourth end portion. The first conductive portion is electrically connected to the third conductive portion through the second via hole.

[0028] Based on a display panel according to one or more embodiments of the present disclosure, the conductive member comprises a first portion and a second portion, wherein the width of the first portion is greater than the width of the second portion, the third conductive sublayer of the first portion protrudes from the second surface along the width direction of the conductive member, and the third conductive sublayer of the second portion is coplanar with the second surface along the width direction of the conductive member, or the third conductive sublayers of both the first and second portions protrude from the second surface along the width direction of the conductive member, and the protruding width of the first portion is greater than the protruding width of the second portion.

[0029] A display panel according to one or more embodiments of the present disclosure, wherein the conductive members are electrically connected to the first conductive portion, a plurality of first conductive portions are provided, having a first interval between adjacent conductive members and a second interval between adjacent first conductive portions, wherein the first interval is different from the second interval.

[0030] Based on a display panel according to one or more embodiments of the present disclosure, the first interval is smaller than the second interval.

[0031] Based on a display panel according to one or more embodiments of the present disclosure, the length of the conductive member is less than the length of the first conductive portion, the first conductive portion includes data lines, and the data lines provide data voltages to the pixel units connected thereto.

[0032] Based on a display panel according to one or more embodiments of the present disclosure, each pixel unit includes a pixel circuit layer provided on the barrier layer, an organic electroluminescent element electrically connected to the pixel circuit layer, and a touch electrode provided on the light-emitting side of the organic electroluminescent element, wherein the first conductive portion is any one of the pixel circuit layer, the organic electroluminescent element, or the touch electrode.

[0033] At least one embodiment of the present disclosure further provides a display panel. The display panel has a plurality of pixel units and includes a foldable region, a display region including a first display region and a second display region located on opposite sides of the foldable region, a peripheral region located on at least one side of the display region, a barrier layer located on a base substrate, and a conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially stacked and provided on one side of the barrier layer away from the base substrate, with the length in its extension direction being greater than the width in a direction intersecting the extension direction, wherein the first conductive sublayer is a conductive member closer to the base substrate than the third conductive sublayer, and a first conductive portion, the display The conductive sublayer includes a first conductive portion located in the region, provided in the same layer as the conductive member and made of the same material, wherein the conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, the melting point of the third conductive sublayer is higher than that of the second conductive sublayer, the second conductive sublayer includes a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, the first surface and the second surface are provided opposite to each other, the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, and the width direction intersects with the extension direction of the conductive member.

[0034] Based on one or more embodiments of the present disclosure, a display panel is provided which includes two conductive members, which are insulated from each other, and which include a first conductive member and a second conductive member, wherein the first conductive member is closer to the foldable region than the second conductive member, and the dimension by which the third conductive sublayer in the first conductive member protrudes from the second surface is greater than the dimension by which the third conductive sublayer in the second conductive member protrudes from the second surface.

[0035] At least one embodiment of the present disclosure further provides a display panel. The display panel includes a display area having a plurality of pixel units, a peripheral area located on at least one side of the display area, a light-transmitting area located on one side of the peripheral area away from the display area or surrounded by the display area, a barrier layer located on a base substrate, and a conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially stacked and provided on one side of the barrier layer away from the base substrate, with the length in its extension direction being greater than the width in a direction intersecting the extension direction, wherein the first conductive sublayer comprises a conductive member closer to the base substrate than the third conductive sublayer, and a first conductive portion, the display area The conductive sublayer includes a first conductive portion located in the same layer as the conductive member and made of the same material, wherein the conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, the melting point of the third conductive sublayer is higher than that of the second conductive sublayer, the second conductive sublayer includes a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, the first surface and the second surface are provided opposite to each other, the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, and the width direction intersects with the elongation direction of the conductive member.

[0036] Based on a display panel according to one or more embodiments of the present disclosure, two conductive members are provided, the two conductive members being insulated from each other, and comprising a first conductive member and a second conductive member, wherein the first conductive member is closer to the light-transmitting region than the second conductive member, and the dimension by which the third conductive sublayer in the first conductive member protrudes from the second surface is greater than the dimension by which the third conductive sublayer in the second conductive member protrudes from the second surface.

[0037] At least one embodiment of the present disclosure further provides a display device including any one of the above-described display panels. [Brief explanation of the drawing]

[0038] To more clearly illustrate the technical concepts of the embodiments of this disclosure, the accompanying drawings of these embodiments are briefly introduced below. Obviously, the accompanying drawings in the following description relate only to some embodiments of this disclosure and do not limit the disclosure. [Figure 1] This is a schematic diagram of multiple conductive components in a display panel. [Figure 2] This is a cross-sectional view along line AB in Figure 1. [Figure 3] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 4] This is a cross-sectional view along the line A1-A2 in Figure 3. [Figure 5A] This is another cross-sectional view along the line A1-A2 in Figure 3. [Figure 5B] This is another cross-sectional view along the line A1-A2 in Figure 3. [Figure 6A] This is another cross-sectional view along the line A1-A2 in Figure 3. [Figure 6B] This is a partial cross-sectional view of a conductive member on a display panel according to one embodiment of the present disclosure. [Figure 7] This is a partial cross-sectional view of a conductive member on a display panel according to one embodiment of the present disclosure. [Figure 8] This is another cross-sectional view along the line A1-A2 in Figure 3. [Figure 9] This is a cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 10] Figure 9 is a plan view of the first conductive member and the third conductive member in the display panel shown. [Figure 11] Figure 9 shows cross-sectional views of the first conductive member and the third conductive member in the display panel. [Figure 12] This is a cross-sectional view of adjacent conductive members in a display panel according to one embodiment of the present disclosure. [Figure 13] This is a cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 14] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 15A] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 15B] This is a plan view of a display panel according to another embodiment of the present disclosure. [Figure 16A] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 16B] This is a plan view of a display panel according to another embodiment of the present disclosure. [Figure 17A] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 17B] This is a plan view of a display panel according to one embodiment of the present disclosure. [Figure 17C] This is a partial plan view of a display panel according to one embodiment of the present disclosure. [Figure 18] This is a three-dimensional view of a display device including a display panel according to one embodiment of the present disclosure. [Figure 19] Figure 18 is a plan view of the display device shown. [Figure 20] This is a plan view of a foldable display device, including a display panel according to one embodiment of the present disclosure. [Figure 21] Figure 20 is a schematic diagram of a partial GOA circuit in a foldable display device. [Figure 22A] This is a plan view of the horizontally positioned connecting lines in Figure 21. [Figure 22B] This is a plan view of two adjacent connecting lines that are horizontally positioned in Figure 21. [Figure 23] This is a plan view of a foldable display device, including a display panel according to another embodiment of the present disclosure. [Figure 24] This is a schematic plan view of a display panel according to one embodiment of the present disclosure. [Figure 25] This is a circuit diagram of a pixel driving circuit in a pixel of a display panel according to one embodiment of the present disclosure. [Figure 26] Figure 25 is an operation sequence diagram of the pixel driving circuit shown. [Figure 27] This is a schematic diagram of the second source drain metal layer in a display panel according to one embodiment of the present disclosure. [Figure 28] This is a layout diagram of a display panel according to one embodiment of the present disclosure. [Figure 29] This is a layout diagram of a display panel according to one embodiment of the present disclosure. [Figure 30] This is a cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 31] This is a cross-sectional view of a display panel according to another embodiment of the present disclosure. [Figure 32] This is a partial plan view of a display panel according to an embodiment of the present disclosure. [Figure 33] Figure 32 is a magnified schematic diagram of the data selector. [Figure 34A] This is a partial cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 34B] This is a partial cross-sectional view of a display panel according to one embodiment of the present disclosure. [Figure 35] This is a partial plan view of a display panel according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0039] To further clarify the purpose, technical proposals, and advantages of the embodiments of this disclosure, the technical proposals of the embodiments of this disclosure will be clearly and completely described below with reference to the drawings of the embodiments of this disclosure. It will be apparent that the embodiments described are only some, and not all, embodiments of this disclosure. Any other embodiments that a person skilled in the art could obtain without creative work based on the embodiments of this disclosure described are all within the scope of protection of this disclosure.

[0040] Unless otherwise defined, technical or scientific terms used in this disclosure have their ordinary meanings as understood by those skilled in the art. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but merely distinguish different components. Similarly, similar terms such as “includes” and “contains” mean that the element or object appearing before the term includes the element or object listed after the term, and their equivalents, but do not exclude other elements or objects. Similar terms such as “connected” and “connected to one another” are not limited to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. “Up,” “down,” “left,” and “right,” etc., are merely used to indicate relative positions, and such relative positions may change if the absolute position of the subject changes.

[0041] As the display resolution of display devices increases, the load on the device increases, worsening signal delay. Introducing low-resistance conductive structures is one way to resolve this signal delay. However, the spacing between low-resistance conductive structures decreases as the resolution increases, making them more susceptible to defects caused by the process or subsequent usage processes, such as electrostatic discharge and electrostatic discharge breakdown.

[0042] Figure 1 is a schematic diagram of multiple conductive members in a display panel. As shown in Figure 1, the distance between adjacent conductive members 11 is relatively small, making electrostatic discharge (ESD) breakdown likely to occur. Figure 1 schematically shows only four conductive members, and the number of conductive members and the arrangement of conductive members are not limited to those shown in the figure. The conductive members 11 are located on a base substrate, and the base substrate is not shown in Figure 1; please refer to Figure 2.

[0043] Figure 2 is a cross-sectional view along line A and B in Figure 1. As shown in Figure 2, the conductive members 11 are located on the base substrate 10, and each conductive member 11 includes a first conductive sublayer 11a, a second conductive sublayer 11b, and a third conductive sublayer 11c. The cross-section of each conductive member 11 may be a trapezoid, but is not limited to that. When forming the conductive members 11, a first conductive film, a second conductive film, and a third conductive film may be formed sequentially on the base substrate 10, and then the conductive members 11 shown in Figure 2 may be formed by etching the first conductive film, the second conductive film, and the third conductive film. The conductive members 11 may also be formed by dry etching or wet etching. As shown in Figure 2, the spacing between adjacent third conductive sublayers 11c is greater than the spacing between adjacent second conductive sublayers 11b.

[0044] As shown in Figure 2, the gap between the two adjacent conductive members 11 is relatively small, making it easy for defects, such as electrostatic discharge, to occur in the two adjacent conductive members 11 shown in Figure 2.

[0045] Figure 3 is a plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 3, the display panel includes a base substrate 100 (not shown in Figure 3, see Figure 4) and a conductive member CL.

[0046] Figure 4 is a cross-sectional view along the line A1-A2 in Figure 3. Referring to Figures 3 and 4, the length of the conductive member CL in its extension direction is greater than the width of the conductive member CL in the direction intersecting the extension direction. The direction intersecting the extension direction may refer to the width direction of the conductive member CL. Referring to Figures 3 and 4, the conductive member CL includes a first conductive sublayer 101, a second conductive sublayer 102, and a third conductive sublayer 103 that are sequentially laminated, with the first conductive sublayer 101 being closer to the base substrate 100 than the third conductive sublayer 103. For example, the conductivity of the first conductive sublayer 101 is lower than that of the second conductive sublayer 102, and the melting point of the third conductive sublayer 103 is higher than that of the second conductive sublayer 102. For example, the conductivity of the third conductive sublayer 103 is lower than that of the second conductive sublayer 102, and the melting point of the first conductive sublayer 101 is higher than that of the second conductive sublayer 102. Figure 3 shows two adjacent conductive members CL. The base substrate 100 may be a rigid base substrate or a flexible base substrate. The rigid base substrate includes a glass substrate, and the material of the flexible base substrate includes, but is not limited to, polyimide.

[0047] For example, the base substrate may be a flexible base or a glass base, and the flexible base may be a laminate of one or more of the following: polyimide (PI), polysilane, polysiloxane, polysilazane, polycarbosilane, and polyacrylic acid ester.

[0048] For example, the first conductive sublayer 101, the second conductive sublayer 102, and the third conductive sublayer 103 may all be made from metallic materials or alloys. For example, the material of the first conductive sublayer 101 may be at least one of molybdenum (Mo), titanium (Ti), neodymium (Nd), chromium (Cr), and nickel (Ni); the material of the second conductive sublayer 102 may be at least one of aluminum (Al), copper (Cu), and silver (Ag); and the material of the third conductive sublayer 103 may be at least one of molybdenum, titanium, neodymium, chromium, nickel, and tungsten (W), but is not limited to these. For example, the first conductive sublayer 101 and the third conductive sublayer 10 may be made from the same material, but is not limited to this. For example, the conductive member CL may be configured in which three conductive sublayers such as Mo / Al / Mo, Ti / Al / Ti, Mo / Cu / Mo, and Ti / Cu / Ti are laminated together.

[0049] For example, as shown in Figure 4, the display panel further includes a barrier layer BRL located on the base substrate. The barrier layer BRL is provided between the conductive member CL and the base substrate 100. The barrier layer BRL may be an inorganic insulating film, for example, a single layer of silicon nitride (SiNx), a single layer of silicon oxide (SiOx), or a multilayer containing silicon nitride (SiNx) and silicon oxide (SiOx) stacked on top of each other. The barrier layer BRL can effectively cover impurities or fine particles on the base substrate and has a protective effect on the conductive member. For example, the barrier layer BRL may be made of silicon oxide, but is not limited to that.

[0050] For example, referring to Figures 14 and 32, a display panel according to an embodiment of the present disclosure includes a display area R1 and a peripheral area R2, wherein the display area R1 has a plurality of pixel units SP, and the peripheral area R2 is located on at least one side of the display area R1. The display panel further includes a first conductive portion 61 located on a base substrate, the first conductive portion located in the display area R1, and the first conductive portion 61 and the conductive member CL are provided in the same layer and are made of the same material.

[0051] As shown in Figure 4, the conductive member CL is located on the base substrate 100, and the second conductive sublayer 102 includes a first surface S1 adjacent to the first conductive sublayer 101 and a second surface S2 adjacent to the third conductive sublayer 103, with the first surface S1 and the second surface S2 facing each other. Referring to Figures 3 and 4, the third conductive sublayer 103 protrudes from the second surface S2 along the width direction (first direction) DR1 of the conductive member CL, and the width direction DR1 intersects with the extension direction (second direction) DR2 of the conductive member CL. Figure 3 shows the boundary of the second conductive sublayer 102 at the second surface S2. As shown in Figure 4, the third conductive sublayer 103 covers the periphery of the second conductive sublayer 102.

[0052] For example, as shown in Figure 4, the thickness of the second conductive sublayer 102 is greater than the thickness of the first conductive sublayer 101. Because the thickness of the second conductive sublayer 102 is relatively large and its conductivity is relatively large, there is a relatively large risk of process defects, such as etching residue, occurring in the second conductive sublayer 102. If etching residue occurs, the risk of lateral conduction or electrostatic discharge increases. The second conductive sublayer 102 and the third conductive sublayer 103 may be adjusted so that the third conductive sublayer protrudes from the second surface along the width direction of the conductive member in order to reduce the risk of lateral conduction and electrostatic discharge. Sources of electrostatic discharge generally include electrostatic discharge generated during the manufacturing process of the display panel and electrostatic discharge generated during the use process of the apparatus containing the display panel.

[0053] For example, the thickness range of the second conductive sublayer 102 is 3000 to 12000 Å, the thickness range of the first conductive sublayer 101 is 50 to 2000 Å, and the thickness range of the third conductive sublayer 103 is 50 to 2000 Å, but is not limited to these ranges. For example, the thickness of the second conductive sublayer 102 is greater than the thickness of the first conductive sublayer 101, and the thickness of the second conductive sublayer 102 is greater than the thickness of the third conductive sublayer 103.

[0054] For example, as shown in Figure 4, the orthographic projection area of ​​the third conductive sublayer 103 onto the base substrate 100 is larger than the orthographic projection area of ​​the first surface S1 of the second conductive sublayer 102 onto the base substrate 100, but is not limited to this. In other embodiments, the orthographic projection area of ​​the third conductive sublayer 103 onto the base substrate 100 may be less than or equal to the orthographic projection area of ​​the first surface S1 of the second conductive sublayer 102 onto the base substrate 100.

[0055] For example, as shown in Figure 4, the second conductive sublayer 102 further includes a side surface S3 that connects the sides of the first surface S1 and the second surface S2 that are located on the same side of the second conductive sublayer 102. As shown in Figure 4, in the second conductive member CL2, the side surface S3 located on the left connects the left side of the first surface S1 and the left side of the second surface S2, and the side surface S3 located on the right connects the right side of the first surface S1 and the right side of the second surface S2. As shown in Figure 4, the side surface S3 is a slope. The second conductive sublayer 102 may, but is not limited to, a trapezoidal structure. The side surface S3 is provided at an angle to the first conductive sublayer 101.

[0056] Referring to Figures 3 and 4, the width direction DR1 of the conductive member CL is horizontal, and as shown in Figure 3, the extension direction DR2 of the conductive member CL is vertical, and referring to Figures 3 and 4, the thickness direction (third direction) DR3 of the conductive member CL is perpendicular to the width direction DR1 and perpendicular to the extension direction DR2 of the conductive member CL. Figure 3 illustrates the example where the conductive member CL is a straight line, but in other embodiments, the conductive member CL does not have to be a straight line; for example, the conductive member CL may be a polyline or a curve, or other form.

[0057] For example, the extension direction DR2 of the conductive member CL may be the extension direction of the connecting line between the two endpoints of the conductive member CL, and the width direction DR1 of the conductive member CL may be perpendicular to the extension direction DR2 of the conductive member CL.

[0058] For example, in embodiments of the present disclosure, the distance between conductive sublayers and the width of the conductive sublayers may be determined based on the geometric dimensions between substantially the same positions of different conductive sublayers, and with respect to the second conductive sublayer, they may be determined based on the uppermost position of the second conductive sublayer (e.g., the second surface S2), the bottom position of the second conductive sublayer (e.g., the first surface S1), or the middle position of the second conductive sublayer.

[0059] For example, referring to Figures 3 and 4, two adjacent conductive members CL are insulated from each other, are located in the same layer, and include a first conductive member CL1 and a second conductive member CL2, where the spacing spc1 between the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than the spacing spc2 between the second surface S2 of the second conductive sublayer 102 of the first conductive member CL1 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2, thereby advantageous in reducing the risk of electrostatic discharge between adjacent conductive members. The first conductive member CL1 and the second conductive member CL2 may, but are not limited to, have the same structure. For example, in embodiments of this disclosure, the location of two elements in the same layer means that the two elements are formed by employing the same patterning process with the same film layer. Alternatively, the location of two elements in the same layer means that the substrate material in direct contact with the two elements is the same. For example, the element material formed in the same film layer is the same. For example, as shown in Figure 4, the third conductive sublayer 103 does not come into contact with the first conductive sublayer 101. The width of the third conductive sublayer 103 is greater than the width of the second surface S2. For example, referring to Figures 3 and 4, the orthographic projection area of ​​the third conductive sublayer 103 onto the base substrate 100 is greater than the orthographic projection area of ​​the second surface S2 onto the base substrate 100. Referring to Figures 3 and 4, since the width of the third conductive sublayer 103 is greater than the width of the second surface S2, increasing the distance between adjacent second conductive sublayers 102 reduces the risk of electrostatic discharge between adjacent second conductive sublayers, improving the stability of the device including the display panel and improving the yield rate.

[0060] The inventors of this invention have discovered the following: If the width of the third conductive sublayer beyond the second conductive sublayer is too large, the width of the second conductive sublayer becomes smaller, increasing the resistance of the conductive member, which is unfavorable for high-resolution display. If the width of the third conductive sublayer beyond the second conductive sublayer is too small, the risk of electrostatic discharge between adjacent second conductive sublayers increases. However, when the width of the third conductive sublayer beyond the second conductive sublayer satisfies certain conditions, a conductive member structure that balances resistance and stability can be obtained.

[0061] For example, as shown in Figure 4, a display panel that satisfies the following relationship achieves both resistance and stability.

number

[0062] For example, a method for manufacturing the display panel shown in Figure 4 may include the steps of forming a first conductive film and patterning the first conductive film to form a first conductive sublayer 101, forming a second conductive film and patterning the second conductive film to form a second conductive sublayer 102, forming an insulating layer between adjacent second conductive sublayers 102, and forming a third conductive film on the insulating layer and the second conductive sublayers 102, with the third conductive film in contact with the second conductive sublayers 102, and patterning the third conductive film to form a third conductive sublayer 103. It should be noted that the method for manufacturing the display panel shown in Figure 4 is not limited to the method illustrated above, and those skilled in the art may select an appropriate method based on the description of the structure of the display panel in the embodiments of this disclosure.

[0063] Figure 5A is a schematic diagram of a plurality of conductive members according to one embodiment of the present disclosure. As shown in Figure 5A, the display panel includes a plurality of conductive members CL, the plurality of conductive members CL are located in the same layer, and the plurality of conductive members CL include a first conductive member CL1, a second conductive member CL2, a third conductive member CL3, and a fourth conductive member CL4, the distance SPC01 between the first conductive member CL1 and the second conductive member CL2 is different from the distance SPC02 between the third conductive member CL3 and the fourth conductive member CL4, the dimension by which the third conductive sublayer 103 in the two left conductive members CL protrudes from the second surface S2 of the second conductive sublayer 102 is different from the dimension by which the third conductive sublayer 103 in the two right conductive members CL protrudes from the second surface S2 of the second conductive sublayer 102.

[0064] As shown in Figure 5A, the distance SPC01 between the first conductive member CL1 and the second conductive member CL2 is smaller than the distance SPC02 between the third conductive member CL3 and the fourth conductive member CL4.

[0065] As shown in Figure 5A, the dimension by which the third conductive sublayer 103 in the first conductive member CL1 protrudes from the second surface S2 of the second conductive sublayer 102 along the width direction of the first conductive member CL1 is D01, the dimension by which the third conductive sublayer 103 in the second conductive member CL2 protrudes from the second surface S2 of the second conductive sublayer 102 along the width direction of the second conductive member CL2 is D02, the dimension by which the third conductive sublayer 103 in the third conductive member CL3 protrudes from the second surface S2 of the second conductive sublayer 102 along the width direction of the third conductive member CL3 is D03, and the dimension by which the third conductive sublayer 103 in the fourth conductive member CL4 protrudes from the second surface S2 of the second conductive sublayer 102 along the width direction of the fourth conductive member CL4 is D04. D01 is greater than D03 and greater than D04, and D02 is greater than D03 and greater than D04. For example, in some embodiments, D01 is equal to D02, and D03 is equal to D04, but this is not limited to them.

[0066] As shown in Figure 5A, the first conductive member CL1, the second conductive member CL2, the third conductive member CL3, and the fourth conductive member CL4 are parallel to each other, and in other embodiments, adjacent conductive members do not have to be parallel.

[0067] Figure 5B is a schematic diagram of multiple conductive members according to one embodiment of the present disclosure. The first conductive member CL1 is not parallel to the second conductive member CL2, and the distance SPC01 between the first conductive member CL1 and the second conductive member CL2 gradually increases from the first end to the second end, so that the dimensions by which the third conductive sublayer 103 protrudes from the second surface S2 of the second conductive sublayer 102 are different at different positions relative to the same conductive member CL.

[0068] For example, as shown in Figure 5B, with respect to the same conductive member, the dimension by which the third conductive sublayer 103 protrudes from the second surface S2 of the second conductive sublayer 102 at a position where the spacing SPC01 is small is smaller than the dimension by which the third conductive sublayer 103 protrudes from the second surface S2 of the second conductive sublayer 102 at a position where the spacing SPC01 is large, but is not limited to this.

[0069] Figure 6A is another cross-sectional view along the line A1-A2 in Figure 3. For example, as shown in Figure 6A, side surface S3 includes at least two sub-side surfaces S3, the at least two sub-side surfaces S3 including a first sub-side surface S31 adjacent to the first conductive sub-layer 101 and a second sub-side surface S32 adjacent to the third conductive sub-layer 103, wherein the angle θ1 between the first sub-side surface S31 and the first conductive sub-layer 101 is smaller than the angle θ2 between the second sub-side surface S32 and the first conductive sub-layer 101.

[0070] The second conductive sublayer 102 generally forms sides with a constant inclination angle, with the bottom being larger and the top smaller. As a result, the spacing between adjacent second conductive sublayers naturally increases from bottom to top. In the embodiments of this disclosure, while reducing the risk of electrostatic discharge mainly by reducing the width of the second conductive sublayer, the spacing between adjacent second conductive sublayers does not have to be increased unilaterally. The tendency for this to increase is mitigated by the angle θ2, allowing for the formation of a gentler slope, thereby structurally increasing the width of the second conductive sublayer at the bottom and reducing the resistance of the conductive member.

[0071] Figure 6B is a partial cross-sectional view of a conductive member on a display panel according to one embodiment of the present disclosure. As shown in Figure 6B, in a cross section cut in the elongation direction DR2 perpendicular to the conductive member CL, the intersection of the side surface S3 and the first conductive sub-layer 101 is the first intersection P1, the intersection of the side surface S3 and the third conductive sub-layer 103 is the second intersection P2, and at least a portion of the side surface S3 is located on one side that is closer to the second conductive sub-layer 102 than the connection line LN0 between the first intersection P1 and the second intersection P2. The cross section cut perpendicular to the elongation direction DR2 of the conductive member CL is a plane formed by the thickness direction DR3 and the width direction DR1 of the conductive member CL.

[0072] For example, as shown in Figure 6B, in a cross section cut perpendicular to the extension direction DR2 of the conductive member CL, the distance between the intersection point P3 of the extension line LN1 of the second sub-side surface S32 and the first conductive sub-layer 101 and the intersection point P1 of the first sub-side surface S31 and the first conductive sub-layer 101 is d1, and the distance by which the first conductive sub-layer 101 extends beyond the first surface S1 is Δw1.

[0073] For example, as shown in Figure 6B, in a cross section cut perpendicular to the extension direction DR2 of the conductive member CL, the distance between the intersection point P4 of the extension line LN2 of the first sub-side surface S31 and the third conductive sub-layer 103 and the intersection point P2 of the second sub-side surface S32 and the third conductive sub-layer 103 is d2, and the distance by which the third conductive sub-layer 103 extends beyond the second surface S2 is Δw2. For example, in the embodiments of this disclosure, the distance by which the third conductive sub-layer 103 extends beyond the second surface S2 is the dimension in the width direction of the conductive member where the third conductive sub-layer 103 extends beyond the second surface S2. The width direction of the conductive member intersects with the length direction of the conductive member. For example, the width direction of the conductive member is perpendicular to the length direction of the conductive member.

[0074] For example, as shown in Figure 6B, in order to achieve both a reduction in the risk of electrostatic discharge and a decrease in the resistance of the conductive material, d1 < Δw1, and furthermore, for example, d1 < Δw2.

[0075] For example, as shown in Figure 6B, in order to achieve both a reduction in the risk of electrostatic discharge and a decrease in the resistance of the conductive material, d2 < Δw1, and furthermore, for example, d2 < Δw2.

[0076] For example, as shown in Figure 6B, in order to achieve both a reduction in the risk of electrostatic discharge and a decrease in the resistance of the conductive material, Δw2 < Δw1.

[0077] For example, as shown in Figure 6B, both the first sub-side surface S31 and the second sub-side surface S32 are slopes. Referring to Figures 6A and 6B, the first sub-side surface S31 and the second sub-side surface S32 may each be slopes relative to the base substrate 100.

[0078] Figure 7 is a partial cross-sectional view of a conductive member on a display panel according to one embodiment of the present disclosure. For example, as shown in Figure 7, in order to achieve both a reduction in the risk of electrostatic discharge and a reduction in the resistance of the conductive member, the angle θ2 between the second sub-side surface S32 and the first conductive sub-layer 101 is greater than 90 degrees.

[0079] Figure 8 is another cross-sectional view along the line A1-A2 in Figure 3. For example, as shown in Figure 8, side surface S3 includes three successively provided sub-side surfaces S3, the three sub-side surfaces S3 include a first sub-side surface S31, a second sub-side surface S32, and a third sub-side surface S33, the first sub-side surface S31 being closer to the first conductive sub-layer 101 than the third sub-side surface S33, the angle between the first sub-side surface S31 and the first conductive sub-layer 101 being a first angle θ1, the angle between the second sub-side surface S32 and the first conductive sub-layer 101 being a second angle θ2, and the angle between the third sub-side surface S33 and the first conductive sub-layer 101 being a third angle θ3, and in order to achieve both a reduction in the risk of electrostatic discharge and a reduction in the resistance of the conductive member, the third angle θ3 is greater than the second angle θ2, and the second angle θ2 is greater than the first angle θ1.

[0080] For example, referring to Figures 4, 6A, and 8, the second conductive sublayer 102 includes two sides S3, the two sides S3 being opposite each other, and the two sides S3 being arranged symmetrically along the thickness direction of the conductive member CL. Figures 6B and 7 show only one side S3 of the conductive member CL, and the other side S3 of the conductive member CL may be arranged symmetrically with respect to the side S3 shown with respect to the thickness direction of the conductive member CL. It should be noted that the two opposing sides of the same conductive member do not have to be arranged symmetrically, and the embodiments of this disclosure are not limited thereto.

[0081] Referring to Figures 6A and 8, the two adjacent conductive members CL are insulated from each other, are located in the same layer and have the same structure, and the two adjacent conductive members CL include a first conductive member CL1 and a second conductive member CL2, the distance spc1 between the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than the distance spc2 between the second surface S2 of the second conductive sublayer 102 of the first conductive member CL1 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2.

[0082] Referring to Figures 3 to 6A and Figure 8, the distance between the first conductive member CL1 and the second conductive member CL2 is relatively small. For example, the distance between the first conductive member CL1 and the second conductive member CL2 may be 5 to 19 μm, but is not limited thereto, and the embodiments of this disclosure do not specifically limit the value of the distance between the first conductive member CL1 and the second conductive member CL2.

[0083] Referring to Figures 4, 6A, and 8, the distance from the first conductive member CL1 to the base substrate 100 may be equal to, but is not limited to, the distance from the second conductive member CL2 to the base substrate 100.

[0084] Figure 9 is a cross-sectional view of a display panel according to one embodiment of the present disclosure. As shown in Figure 9, the display panel includes a base substrate 100, a first conductive member layer 21 located on the base substrate 100, an insulating layer 22, and a second conductive member layer 23. The first conductive member layer 21 includes a first conductive member CL1 and a second conductive member CL2, and the second conductive member layer 23 includes a third conductive member CL3 and a fourth conductive member CL4. The first conductive member CL1 and the second conductive member CL2 may be the first conductive member CL1 and the second conductive member CL2 described above, respectively, and the third conductive member CL3 and the fourth conductive member CL4 may be the first conductive member CL1 and the second conductive member CL2 described above, respectively.

[0085] For example, the first conductive member layer 21 and the second conductive member layer 23 are located in different layers, the distance from the first conductive member layer 21 to the base substrate 100 is different from the distance from the second conductive member layer 23 to the base substrate 100, and the distances from the first conductive member CL1 and the third conductive member CL3 to the base substrate 100 are different.

[0086] Figure 10 is a plan view of the first conductive member and the third conductive member in the display panel shown in Figure 9. Both the first conductive member CL1 and the third conductive member CL3 employ a structure in which the third conductive sublayer protrudes from the second surface along the width direction of the conductive member.

[0087] Figure 11 is a cross-sectional view of the first conductive member and the third conductive member in the display panel shown in Figure 9. The thickness of the second conductive sublayer 102 of the first conductive member CL1 is T3, and the thickness of the second conductive sublayer 102 of the third conductive member CL3 is T4, where T4 is greater than T3. The distance over which the third conductive sublayer 103 of the first conductive member CL1 extends beyond the second surface S2 is Δw3, and the distance over which the third conductive sublayer 103 of the third conductive member CL3 extends beyond the second surface S2 is Δw4, satisfying the following relationship.

number

[0088] Therefore, if the display panel has multiple conductive members, each of which requires a third conductive sublayer to protrude from the second surface along the width direction of the conductive member, the distance at which the third conductive sublayer 103 extends beyond the second surface S2 in a conductive member having a different distance from the base substrate may be determined based on the thickness of the second conductive sublayer.

[0089] It should be explained that the embodiments of this disclosure are described as having a small thickness for the conductive member close to the base substrate and a large thickness for the conductive member farther away from the base substrate. In other embodiments, the conductive member close to the base substrate may be thick, while the conductive member farther away from the base substrate may be thin.

[0090] Figure 12 is a cross-sectional view of adjacent conductive members in a display panel according to one embodiment of the present disclosure. As shown in Figure 12, the gap spc1 between the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than the gap spc2 between the second surface S2 of the second conductive sublayer 102 of the first conductive member CL1 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2, thereby being advantageous in reducing the risk of electrostatic discharge.

[0091] For example, as shown in Figure 12, the third conductive sublayer 103 covers the second conductive sublayer 102 and is in contact with the first conductive sublayer 101. The side surface S33 of the third conductive sublayer 103 covers the second conductive sublayer 102, reducing the risk of electrostatic discharge damage to the second conductive sublayer 102.

[0092] For example, in order to significantly reduce the frequency of risk occurrence by further reducing the effects of electrostatic discharge, at least one of N, S, P, and Cl elements may be doped onto at least one of the first surface S1, second surface S2, and side surface S3 of the second conductive sublayer 102. For example, the above doping may be performed on the second conductive sublayer 102 of the conductive member CL in the display panel shown in Figures 3 to 12 according to the embodiment of this disclosure.

[0093] Figure 13 is a cross-sectional view of a display panel according to one embodiment of the present disclosure. As shown in Figure 13, the display panel includes a base substrate 100, a barrier layer 42, and a conductive member layer 43, the conductive member layer 43 including a conductive member CL, the conductive member CL being located on an inorganic insulating film 42. For example, the conductive member CL is in contact with the barrier layer 42, but is not limited to that. For example, the conductive member layer 43 includes the first conductive member CL1 and the second conductive member CL2 described above.

[0094] For example, the barrier layer 42 includes an inorganic insulating film and has at least one of F and Cl elements. The barrier layer 42, having at least one of F and Cl elements, can effectively adsorb metal ions in the conductive member and reduce the risk of electrostatic discharge.

[0095] For example, in order to significantly reduce the frequency of electrostatic discharge, the content of at least one of element F and element Cl in the barrier layer 42 is 1 × 10¹⁶ per cubic centimeter. 18 ~5×10 20 It is an individual atom.

[0096] For example, referring to Figures 4, 6A to 8, 11 and 12, the first surface S1 is in contact with the first conductive sublayer 101, and the second surface S2 is in contact with the third conductive sublayer 103.

[0097] For example, referring to Figures 4, 6A to 8, 11 and 12, the width of the first surface S1 is smaller than the width of the first conductive sublayer 101, and the width of the second surface S2 is smaller than the width of the third conductive sublayer 103. In order to obtain a conductive member that balances resistance and stability, the difference in width between the third conductive sublayer 103 and the second surface S2 is greater than the thickness of the third conductive sublayer 103.

[0098] In the embodiments of this disclosure, it is not limited whether the third conductive sublayer 103 extends beyond the first surface S1. For example, the third conductive sublayer 103 may extend beyond the first surface S1, i.e., the area of ​​the orthographic projection of the third conductive sublayer 103 onto the base substrate is larger than the area of ​​the orthographic projection of the first surface S1 onto the base substrate. Of course, in other embodiments, the third conductive sublayer 103 may not extend beyond the first surface S1, i.e., the orthographic projection of the third conductive sublayer 103 onto the base substrate falls within the orthographic projection of the first surface S1 onto the base substrate. In some embodiments, the orthographic projection of the third conductive sublayer 103 onto the base substrate may overlap with the orthographic projection of the first surface S1 onto the base substrate.

[0099] The following describes the application of conductive materials in the display panels shown in Figures 3 to 13 according to the embodiments of this disclosure. However, it should be noted that the application of conductive materials in the display panels according to the embodiments of this disclosure is not limited to the description below.

[0100] Figure 14 is a plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 14, the display panel includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1. A plurality of sub-pixels SP are located in the display area R1. A plurality of gate lines GL and a plurality of data lines DL are located in the display area R1. The plurality of gate lines GL and a plurality of data lines DL intersect and are insulated from each other. As shown in Figure 14, each data line DL is connected to a pad PD located in the peripheral area R2. As shown in Figure 14, a plurality of pads PD are located in the peripheral area R2, and the plurality of pads PD may be configured to be connected to other elements or external circuits, such as a flexible circuit board. Two adjacent pads PD in Figure 14 may be the first conductive member CL1 and the second conductive member CL2 described above. Figure 14 further shows a plurality of pixel units SP. The plurality of pixel units SP may be arranged in an array, but are not limited to that. Figure 14 illustrates, but are not limited to, a matrix arrangement of the plurality of pixel units SP. Figure 14 illustrates an example where each data line DL is connected to a single pad PD. However, in other embodiments, multiple data lines DL may be connected to a single pad PD, for example, two or more data lines DL may be connected to a single pad PD. For example, two or more data lines DL can be connected to a single pad PD by providing a data selection unit, such as a mux unit.

[0101] Figure 15A is a plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 15A, the first conductive member CL1 and the second conductive member CL2 are connected to pin PN of the external circuit CC, respectively, by an anisotropic conductive adhesive ADH. The anisotropic conductive adhesive ADH conducts in the third direction DR3 (vertical direction), thereby electrically connecting the first pin PN1 of the external circuit CC to the first conductive member CL1, and the second pin PN2 of the external circuit CC to the second conductive member CL2. The fact that the third conductive sublayer 103 of the conductive member CL protrudes from the second surface S2 is advantageous for binding it to the external circuit. Figure 15A schematically illustrates, but is not limited to, a second conductive sublayer 102 having two slopes. The conductive member CL in Figure 15A may be any one of the conductive members CL described in the embodiments of the present disclosure.

[0102] Figure 15A shows the conductive portion ADH1 of the anisotropic conductive adhesive ADH. The portion of the anisotropic conductive adhesive ADH other than the conductive portion ADH1 is an insulating portion. That is, the portion of the anisotropic conductive adhesive ADH located between two adjacent conductive portions ADH1 is an insulating portion, thereby achieving both longitudinal connection and transverse insulation of the conductive element.

[0103] Figure 15B is a plan view of a display panel according to another embodiment of the present disclosure. Compared to the display panel shown in Figure 15A, the conductive member CL of the display panel shown in Figure 15A is provided in a stack with a first stack element ST1 and a second stack element ST2, and the first stack element ST1 and the second stack element ST2 are provided on both sides of the conductive member CL, with the first stack element ST1 being closer to the base substrate than the second stack element ST2. The second stack element ST2 is connected to pin PN by the conductive portion of the anisotropic conductive adhesive ADH. Figure 15B illustrates an example in which the conductive member CL is in contact with both the first stack element ST1 and the second stack element ST2, but is not limited to this, and in other embodiments, the conductive member CL may be connected to the first stack element ST1 via a via hole penetrating the insulating layer, and the conductive member CL and the second stack element ST2 may be connected via a via hole penetrating the insulating layer. In Figures 15A and 15B, the barrier layer between the base substrate 100 and the conductive member CL is omitted.

[0104] Figure 16A is a plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 16A, the display panel has a light-transmitting region HL. Because the base substrate is cut out in the light-transmitting region HL, the distance d21 between two adjacent gate lines GT adjacent to the light-transmitting region HL is smaller than the distance d22 between two adjacent gate lines GT further away from the light-transmitting region HL. The gate lines GT in Figure 16A that are adjacent to the light-transmitting region HL and have a portion that bends / refracts in the forward direction may be conductive members CL having a structure in which the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, according to embodiments of the present disclosure. As shown in Figure 16A, the first conductive member CL1 is closer to the light-transmitting region HL than the second conductive member CL2. To reduce the risk of electrostatic discharge, the distance that the third conductive sublayer 103 in the first conductive member CL1 extends beyond the second surface S2 is greater than the distance that the third conductive sublayer 103 in the second conductive member CL2 extends beyond the second surface S2. Of course, the conductive element CL may be any other signal line in the display panel.

[0105] Figure 16B is a plan view of a display panel according to another embodiment of the present disclosure. Compared to the display panel shown in Figure 16A, the display panel shown in Figure 16B has a notch at the periphery where the light-transmitting region HL is located on the base substrate. The light-transmitting region HL can be used to position components such as a camera, which is advantageous for realizing multiple functions of the display device. The shape of the light-transmitting region HL is not limited to those shown in Figures 16A and 16B, and may be determined as needed.

[0106] Figure 17A is a plan view of a display panel according to one embodiment of the present disclosure. Figure 17A shows a plurality of data lines DL and a plurality of first power lines PL1, wherein the data lines DL are adjacent to the first power lines PL1, and the portions of the data lines DL and first power lines PL1 located near the light-transmitting region HL may be the first conductive member CL1 and the second conductive member CL2 described above, respectively. In a location close to the light-transmitting region HL, the distance d21 between an adjacent data line DL and a first power line PL1 that is close to the light-transmitting region HL is smaller than the distance d22 between an adjacent data line DL and a first power line PL1 that is further away from the light-transmitting region HL. As shown in Figure 17A, in a location close to the light-transmitting region HL, the distance d21 between an adjacent data line DL1 and a first power line PL11 that is close to the light-transmitting region HL is smaller than the distance d22 between an adjacent data line DL2 and a first power line PL12 that is further away from the light-transmitting region HL.

[0107] Figure 17B is a plan view of a display panel according to one embodiment of the present disclosure. Compared to the display panel shown in Figure 17A, the display panel shown in Figure 17B includes a separation column SEP. The installation of the separation column SEP is advantageous in preventing the intrusion of water oxygen into the light-emitting layer of the light-emitting diode. The separation column SEP may employ the structure of the conductive member CL described above. The separation column SEP is provided around the light-transmitting region HL, and the separation column SEP and the first power line PL1 adjacent to it may be the first conductive member CL1 and the second conductive member CL2 described above, respectively. Of course, in other embodiments, the data line DL may be adjacent to the separation column SEP, that is, the separation column SEP and the data line DL adjacent to it may be the first conductive member CL1 and the second conductive member CL2 described above, respectively. For example, the data line DL and the first power line PL1 are provided in the same layer. What needs to be explained is that there is no data line between the isolation column SEP and the adjacent first power line PL1, and there is no first power line PL1 between the isolation column SEP and the adjacent data line DL.

[0108] Figure 17C is a partial plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 17, the isolation column SEP includes a plurality of sub-isolation columns SEP0, where the distance d32 between a sub-isolation column SEP0 adjacent to a signal line SL and an adjacent sub-isolation column SEP0 is greater than the spacing d31 between adjacent sub-isolation columns SEP0. The signal line SL may be a data line DL or a first power line PL1 as shown in Figure 17B. There is spacing between adjacent sub-isolation columns SEP0. Adjacent sub-isolation columns SEP0 may be the first conductive member CL1 and the second conductive member CL2 described above.

[0109] Figure 18 is a stereoscopic view of a display device including a display panel according to one embodiment of the present disclosure. As shown in Figure 18, the display device is a foldable display device. The display device may be an OLED display device. The display device includes a foldable region R13 and a first display region R11 and a second display region R12 provided on both sides of the foldable region R13, respectively. Figure 18 shows the foldable line FL. The foldable region R13, the first display region R11 and the second display region R12 constitute a display region R1.

[0110] Figure 19 is a plan view of the display device shown in Figure 18. As shown in Figure 19, a first peripheral region R21 is provided on one side of the first display region R11, and a first pad region PDR1 is provided within the first peripheral region R21. A plurality of first pads PD1 are located in the first pad region PDR1, and the plurality of first pads PD1 include two adjacent first pads PD1: a first pad PD11 that is close to the foldable line FL and a first pad PD12 that is away from the foldable line FL. The first pads PD11 and PD12 may be the first conductive member CL1 and the second conductive member CL2 described above, respectively. To reduce the risk of electrostatic discharge, the distance that the third conductive sublayer 103 in the first conductive member CL1 extends beyond the second surface S2 is greater than the distance that the third conductive sublayer 103 in the second conductive member CL2 extends beyond the second surface S2. In other words, the first conductive member CL1 is closer to the foldable wire FL than the second conductive member CL2, and the distance at which the third conductive sublayer 103 in the first conductive member CL1 extends beyond the second surface S2 is greater than the distance at which the third conductive sublayer 103 in the second conductive member CL2 extends beyond the second surface S2. Figure 19 illustrates this using the example that the first pad PD11 is the first pad closest to the foldable wire FL, but it is not limited to this, and the first pad PD11 does not have to be the first pad closest to the foldable wire FL.

[0111] For example, the distance between adjacent second conductive sublayers of two adjacent conductive members close to the foldable wire FL is greater than the distance between adjacent second conductive sublayers of two adjacent conductive members further away from the foldable wire FL.

[0112] As shown in Figure 19, a second peripheral region R22 is provided on one side of the second display region R12, and a second pad region PDR2 is provided within the second peripheral region R22. Multiple second pads PD2 are located in the second pad region PDR2, and the multiple second pads PD2 include two adjacent second pads PD2: a second pad PD21 that is close to the foldable line FL and a second pad PD22 that is further away from the foldable line FL. The second pads PD21 and PD22 may be the first conductive member CL1 and the second conductive member CL2 described above, respectively. To reduce the risk of electrostatic discharge, the distance that the third conductive sublayer 103 in the first conductive member CL1 extends beyond the second surface S2 is greater than the distance that the third conductive sublayer 103 in the second conductive member CL2 extends beyond the second surface S2. That is, the closer it is to the foldable line FL, the greater the dimension that the third conductive sublayer in the conductive member protrudes from the second surface along the width direction of the conductive member.

[0113] Figure 19 shows only four first pads PD1 and four second pads PD. The number of first pads PD1 and the number of second pads PD may be determined as needed, but are not limited to those shown in the figure.

[0114] Figure 19 illustrates an example where the spacing between adjacent conductive members CL is equal, but the embodiments of this disclosure are not limited to this. In other embodiments, the spacing between adjacent conductive members CL may change gradually. For example, the spacing between adjacent conductive members CL may gradually increase from the direction approaching the display area R1 to the direction away from the display area R1. Figure 19 illustrates an example where adjacent conductive members CL are parallel to each other, but in other embodiments, adjacent conductive members CL may not be parallel to each other.

[0115] Figure 20 is a plan view of a foldable display device, including a display panel according to one embodiment of the present disclosure. As shown in Figure 20, the foldable display device is an OLED display device. For example, the foldable display device includes a foldable region R13 and a first display region R11 and a second display region R12 located on either side thereof, and the foldable region R13, the first display region R11 and the second display region R12 constitute a display region R1, and outside the display region R1 is a peripheral region R2, which includes a first peripheral region R21 located on at least one side of the first display region R11 and a second peripheral region R21 located on at least one side of the second display region R21. The display region includes multiple rows of pixel units. The first display region R11 and the second display region R12 are non-foldable regions.

[0116] Figure 21 is a schematic diagram of a partial GOA circuit in the foldable display device shown in Figure 20.

[0117] Referring to Figures 20 and 21, the first peripheral region R21 includes a plurality of signal lines 46 and a plurality of GOA unit circuits 45, each of which is electrically connected to the corresponding row of pixel units by the signal lines 46, and each of which is used to drive the corresponding row of pixel units.

[0118] As shown in Figures 20 and 21, each stage of the GOA unit circuit 45 is connected to signal lines 46 by scan data lines (not shown), and the signal lines 46 include GOA signal lines, pixel unit signal lines, and power signal lines. The GOA signal lines include a first clock signal line CK1, a second clock signal line CK2, a low-level signal line VGL, and a high-level signal line VGH, which are necessary for the GOA unit circuit 45 to operate normally.

[0119] For example, as shown in Figure 21, the input signal IN in the Nth stage GOA unit circuit 45 is provided by the output signal OUT of the N-1th stage GOA unit circuit, and the output signal OUT of the Nth stage GOA unit circuit provides the switch signal for the Nth row pixel unit and the input signal for the N+1th stage GOA unit circuit.

[0120] For example, the first clock signal line CK1 is configured to provide the first clock signal, the second clock signal line CK2 is configured to provide the second clock signal, the low-level signal line VGL is configured to provide the low-level signal, and the high-level signal line VGH is configured to provide the high-level signal.

[0121] For example, the conductive member CL in the display panel according to the embodiment of this disclosure may be any two adjacent members from the first clock signal line CK1, the second clock signal line CK2, the low-level signal line VGL, and the high-level signal line VGH shown in Figure 21. That is, the first conductive member CL1 and the second conductive member CL2 may be any two adjacent members from the first clock signal line CK1, the second clock signal line CK2, the low-level signal line VGL, and the high-level signal line VGH shown in Figure 21. When the first conductive member CL1 is closer to the more foldable line FL than the second conductive member CL2, the distance at which the third conductive sublayer 103 of the first conductive member CL1 extends beyond the second surface S2 is greater than the distance at which the third conductive sublayer 103 of the second conductive member CL2 extends beyond the second surface S2 in order to reduce the risk of electrostatic discharge. Figure 21 illustrates an example where the first conductive member CL1 is the high-level signal line VGH and the second conductive member CL2 is the low-level signal line VGL.

[0122] Figure 21 further shows the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line CNL4. The high-level signal line VGH, the low-level signal line VGL, the first clock signal line CK1, and the second clock signal line CK2 are connected to the Nth stage GOA unit circuit 45 by the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line CNL4, respectively. The display panel shown in Figure 21 will be explained as an example in which the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line CNL4 are arranged horizontally, and the high-level signal line VGH, the low-level signal line VGL, the first clock signal line CK1, and the second clock signal line CK2 are arranged vertically.

[0123] For example, the first conductive member CL1 and the second conductive member CL2 may be any two adjacent connections from the first connecting line CNL1, the second connecting line CNL2, the third connecting line CNL3, and the fourth connecting line CNL4 shown in Figure 21.

[0124] Figure 22A is a plan view of the horizontally arranged connecting lines in Figure 21. The conductive member shown in Figure 22A may be any one of the first connecting line CNL1, second connecting line CNL2, third connecting line CNL3, and fourth connecting line CNL4 shown in Figure 21. For example, to reduce the risk of electrostatic discharge, the distance d1 at which the third conductive sublayer 103 of the conductive member CL adjacent to the foldable line FL exceeds the second surface S2 is greater than the distance d2 at which the third conductive sublayer 103 of the conductive member CL away from the foldable line FL exceeds the second surface S2. That is, the distance at which the third conductive sublayer 103 exceeds the second surface S2 at different locations on the same conductive member is different.

[0125] Figure 22B is a plan view of two adjacent horizontally arranged connecting lines in Figure 21. As shown in Figure 22B, the distance d0 between the second surface S2 between the first conductive member CL1 and the second conductive member CL2 gradually decreases from the direction approaching the foldable line FL to the direction away from the foldable line FL.

[0126] Figure 23 is a plan view of a foldable display device, including a display panel according to another embodiment of the present disclosure. In the foldable display device shown in Figure 20, the signal lines 46 and the GOA unit circuit 45 are located on the left and right sides of the display device, while in the foldable display device shown in Figure 23, the signal lines 46 and the GOA unit circuit 45 are located on the top and bottom sides of the display device, compared to the foldable display device shown in Figure 20.

[0127] Figure 24 is a schematic plan view of a display panel according to one embodiment of the present disclosure. As shown in Figure 24, the display panel includes a base substrate 100, which is divided into two regions. For example, the base substrate 100 includes a display region R1 and a peripheral region R2 located on at least one side of the display region R1. For example, the peripheral region R2 may be located on at least one of the above, below, left, and right sides of the display region R1. Figure 24 shows that the peripheral region R2 is located on the above, below, left, and right sides of the display region R1, that is, the peripheral region R2 surrounds the display region R1. For example, the peripheral region R2 may be located on only one side of the display region R1, for example, only on the above, below, left, or right side of the display region R1. The gray-filled area in Figure 24 is the display region R1, and the remaining part of the base substrate 100 is the peripheral region R2. For example, in an embodiment of the present disclosure, the display region R1 is the screen display region and the light output region. For example, peripheral region R2 is an area where the screen is not displayed and is a non-light-emitting area.

[0128] As shown in Figure 24, a crack stopper line 51 is provided in the peripheral region R2 to prevent peripheral cracks from spreading into the display region R1. The crack stopper line 51 includes a first crack stopper line 511 and a second crack stopper line 512. Further in the peripheral region R2, a crack detection line 52 is provided, configured to detect cracks. The crack detection line 52 includes a first crack detection line 521 and a second crack detection line 522. The crack detection line 52 is closer to the display region R1 than the crack stopper line 51. If the occurrence of a crack is detected by the crack detection line 52, it is possible to avoid providing the client with a product that has peripheral cracks. For example, cracks can occur at the periphery of a layer, such as an inorganic layer, on the base substrate 100 during the process of cutting a display panel motherboard into multiple single display panels, during the transportation process, or when the display panel is subjected to mechanical or thermal shock.

[0129] In the display panel according to the embodiment of this disclosure, the first conductive member CL1 and the second conductive member CL2 may be a first crack stopper line 511 and a second crack stopper line 512, respectively, or the first conductive member CL1 and the second conductive member CL2 in the display panel according to the embodiment of this disclosure may be a first crack detection line 521 and a second crack detection line 522, respectively.

[0130] As shown in Figure 24, in order to reduce the risk of electrostatic discharge, the distance at which the third conductive sublayer 103 in the first conductive member CL1 adjacent to the display area R1 extends beyond the second surface S2 is smaller than the distance at which the third conductive sublayer 103 in the second conductive member CL2 further away from the display area R1 extends beyond the second surface S2.

[0131] For example, the display panel has a feature region and is provided with two conductive members CL, the two conductive members CL are insulated from each other, and the two conductive members CL include a first conductive member CL1 and a second conductive member CL2, the first conductive member CL1 is closer to the feature region than the second conductive member CL2, and the dimension by which the third conductive sublayer 103 in the first conductive member CL1 protrudes from the second surface S2 is greater than the dimension by which the third conductive sublayer 103 in the second conductive member CL2 protrudes from the second surface S2. For example, the feature region includes at least one of a light-transmitting region, a foldable region and a display region.

[0132] In the following explanation, Figures 25 to 28 are linked together to illustrate that the first conductive member CL1 and the second conductive member CL2 are the first power line (power voltage line) ELVDD and the data line, respectively.

[0133] The transistors used in Figures 25 and 28 may both be triodes, thin-film transistors, field-effect transistors, or other devices with the same characteristics. In the embodiments of this disclosure, in order to distinguish between the two electrodes other than the control electrode of the transistor, one electrode is referred to as the first electrode and the other as the second electrode.

[0134] For example, if the transistor is a triode, the control electrode may be the base electrode, the first electrode may be the collector electrode, and the second electrode may be the emitter electrode; or the control electrode may be the base electrode, the first electrode may be the emitter electrode, and the second electrode may be the collector electrode.

[0135] For example, if the transistor is a thin-film transistor or a field-effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0136] The display panel shown in Figure 28 includes an array layer located on a base substrate and a light-shielding layer located on one side of the array layer away from the base substrate. Multiple imaging holes are formed on the light-shielding layer, and the imaging holes ensure that the first positive projection on the base substrate does not overlap with the second positive projection on the base substrate of the active layer pattern of the switch transistors in the array layer. The switch transistors are transistors connected to the gate electrodes of the drive transistors in the array layer.

[0137] In the embodiment of this disclosure, the display panel is provided with imaging holes formed on the light-shielding layer in the active layer pattern that does not correspond to the switch transistors in the array layer, so that light rays penetrating the imaging holes do not affect the active layer pattern of the switch transistors. As a result, light irradiation does not generate photo-generated leakage current in the switch transistors when they are in the off state, and furthermore, does not affect the potential of the gate electrodes of the drive transistors, thus avoiding the problem of inaccurate display gradation.

[0138] For example, the statement that the first orthographic projection and the second orthographic projection do not overlap means, but is not limited to, that there is no overlapping portion between the first orthographic projection and the second orthographic projection.

[0139] For example, the array layer may be a thin-film transistor array layer, but is not limited to that.

[0140] For example, the thin-film transistor array layer may include an array layer and a second source-drain metal layer, and the second source-drain metal layer is multiplexed as a light-shielding layer, but is not limited to that.

[0141] For example, the orthographic projection of the channel region in the active layer pattern of a control transistor in an array layer onto the base substrate is a third orthographic projection, while the orthographic projection of the channel region in the active layer pattern of a drive transistor onto the base substrate is a fourth orthographic projection.

[0142] The orthogonal projection of the channel region in the active layer pattern of a switch transistor onto the base substrate is the fifth orthogonal projection.

[0143] For example, the shortest distance between the periphery of the first orthographic projection and the fifth orthographic projection is greater than the distance between the periphery of the first orthographic projection and the third orthographic projection.

[0144] For example, the shortest distance between the periphery of the first orthographic projection and the fifth orthographic projection is greater than the distance between the periphery of the first orthographic projection and the fourth orthographic projection.

[0145] For example, control transistors are transistors in the array layer other than switch transistors and drive transistors.

[0146] For example, the shortest distance between the periphery of the first orthographic projection and the fifth orthographic projection is greater than the distance between the periphery of the first orthographic projection and the third orthographic projection, and the shortest distance between the periphery of the first orthographic projection and the fifth orthographic projection is greater than the distance between the periphery of the first orthographic projection and the fourth orthographic projection, the distance from the imaging aperture to the channel region of the active layer pattern of the switch transistor is relatively far, and the channel region of the active layer pattern of the switch transistor is prevented from being illuminated by light rays penetrating the imaging aperture.

[0147] For example, the display panel may include a first pixel region with an imaging aperture and a second pixel region without an imaging aperture. For example, the area of ​​the first pixel region is larger than the area of ​​the second pixel region.

[0148] For example, the aspect ratio of a switch transistor in the first pixel region may be smaller than the aspect ratio of a switch transistor in the second pixel region. This reduces the current value of the light-generating leakage current and further improves the accuracy of the display grayscale, but is not limited to this.

[0149] For example, in the first orthographic projection, the metal pattern contained in the array layer does not overlap with the orthographic projection onto the base substrate.

[0150] Furthermore, the imaging hole must not be obstructed by the metal pattern, thereby improving the accuracy of the hole-capture fingerprint recognition.

[0151] For example, the diameter of the imaging aperture may be between 2 μm and 20 μm, but is not limited to that.

[0152] For example, the diameter of the imaging aperture may be between 4 μm and 7 μm, but is not limited to that.

[0153] For example, the density of imaging apertures may be flexibly adjusted according to the actual situation, and one imaging aperture may be provided within N pixel regions, where N is a positive integer.

[0154] For example, N can be 3 or greater and 10 or less, but is not limited to that.

[0155] For example, the array layer may include an active layer sequentially provided between the base substrate and the light-shielding layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, and a second insulating layer, and the display panel further includes a flat layer and an anode electrode layer sequentially provided on one side of the light-shielding layer away from the second insulating layer.

[0156] For example, the light-shielding layer includes a light-shielding pattern and a connecting pattern, and the light-shielding pattern has imaging holes.

[0157] For example, the first source-drain metal layer is electrically connected to the anode electrode layer via a first via hole penetrating the second insulating layer, a connection pattern, and a second via hole penetrating the flat layer, with a light leakage gap existing between the connection pattern and the light-shielding pattern.

[0158] The orthographic projection of the light leakage gap onto the base substrate occurs because the metal electrodes contained in the thin-film transistor array layer are covered by the orthographic projection onto the base substrate.

[0159] For example, the light-shielding pattern and the connection pattern are separated from each other, and the light-shielding pattern and the connection pattern are insulated from each other.

[0160] For example, the display panel may include a base substrate arranged sequentially from bottom to top, an array layer, a light-shielding layer, a flat layer, and an anode electrode layer.

[0161] For example, the array layer may include an active layer extending from bottom to top, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, and a second insulating layer.

[0162] For example, the anode electrode layer needs to be electrically connected to the first source-drain metal layer. Therefore, by providing a connection pattern separated from the light-shielding pattern in the light-shielding layer, the first source-drain metal layer is electrically connected to the anode electrode layer via a first via hole penetrating the second insulating layer, the connection pattern, and a second via hole penetrating the flat layer.

[0163] Since the light-shielding pattern and the connection pattern are insulated from each other, a light leakage gap exists between them. Because light can leak through this light leakage gap, the light leakage gap is positioned such that the metal electrodes included in the array layer are covered by the orthographic projection onto the base substrate, thereby preventing the light exposed through the light leakage gap from affecting the small-hole fingerprint recognition.

[0164] The metal electrode may be, for example, the upper electrode plate of a storage capacitor, but is not limited to that.

[0165] Figure 25 is a circuit diagram of a pixel driving circuit in a display panel according to one embodiment of the present disclosure.

[0166] As shown in Figure 25, the pixel driving circuit may include a driving transistor T1, a first switching transistor T3, a second switching transistor T6, a first control transistor T2, a second control transistor T4, a third control transistor T5, a fourth control transistor T7, and a storage capacitor Cst.

[0167] The source electrode T3s of the first switch transistor T3 is electrically connected to the gate electrode T1g of the drive transistor T1, and the drain electrode T3d of the first switch transistor T3 is electrically connected to the drain electrode T1d of the drive transistor T1.

[0168] The gate electrode T3g of the first switch transistor T3 is electrically connected to the gate line G(n) of the nth row.

[0169] The gate electrode T6g of the second switch transistor T6 is electrically connected to the reset line Reset(n) of the nth row, the drain electrode T6d of the second switch transistor T6 is electrically connected to the gate electrode T1g of the drive transistor T1, and the source electrode T6s of the second switch transistor T6 is electrically connected to the initial voltage line Vint.

[0170] The gate electrode T2g of the first control transistor T2 is electrically connected to the gate line G(n) in the nth row, the source electrode T2s of the first control transistor T2 is electrically connected to the data line D(m) in the mth column, and the drain electrode T2d of the first control transistor T2 is electrically connected to the source electrode T1s of the drive transistor T1.

[0171] The gate electrode T4g of the second control transistor T4 is electrically connected to the nth row light emission control line EM(n), the source electrode T4s of the second control transistor T4 is electrically connected to the first power supply line ELVDD, and the drain electrode T4d of the second control transistor T4 is electrically connected to the source electrode T1s of the drive transistor T1.

[0172] The gate electrode T5g of the third control transistor T5 is electrically connected to the nth row light emission control line EM(n), the source electrode T5s of the third control transistor T5 is electrically connected to the drain electrode T1d of the drive transistor T1, the drain electrode T5d of the third control transistor T5 is electrically connected to the anode electrode of the organic light-emitting diode OLED, and the cathode electrode of the organic light-emitting diode OLED is electrically connected to the second power line ELVSS.

[0173] The gate electrode T7g of the fourth control transistor T7 is electrically connected to the reset line Reset(n+1) of the (n+1)th row, the drain electrode T7d of the fourth control transistor T7 is electrically connected to the anode electrode of the organic light-emitting diode OLED, and the source electrode T7s of the fourth control transistor T7 is electrically connected to the initial voltage line Vint.

[0174] The first electrode plate Csa of the storage capacitor Cst is electrically connected to the first power line ELVDD, and the gate electrode T1g of the drive transistor T1 may be multiplexed as the second electrode plate Csb of the storage capacitor Cst.

[0175] For example, n is a positive integer, and m is a positive integer.

[0176] The pixel driving circuit shown in Figure 25 may, but is not limited to, a pixel driving circuit for the pixel region in the nth row and mth column.

[0177] In the pixel driving circuit shown in Figure 25, all transistors are p-type thin-film transistors, but are not limited to them.

[0178] In Figure 25, the first node N1 is a node electrically connected to the gate electrode of the drive transistor T1.

[0179] The pixel driving circuit shown in Figure 25 is merely one embodiment of a pixel driving circuit in a pixel, and does not limit the structure of the pixel driving circuit.

[0180] For example, the second switching transistor T6 may be a double-gate transistor, which reduces its leakage current and allows for good maintenance of the gate electrode potential of the driving transistor T1, but it is not limited to this.

[0181] Figure 26 is an operating sequence diagram of the pixel driving circuit shown in Figure 25. t1 is the first stage, t2 is the second stage, t3 is the third stage, and the code Vdata is the data voltage provided by the data line D(n).

[0182] As shown in Figure 26, the description of the operation of the pixel driving circuit shown in Figure 26 is as follows:

[0183] In the first stage t1 (i.e., the reset stage), Reset(n) receives a low level input, G(n) receives a high level input, and EM(n) receives a high level input, opening the second switch transistor T6 and resetting the potential of the gate electrode of the drive transistor T1 to the initial voltage.

[0184] In the second stage t2 (i.e., the data writing and threshold voltage compensation stage), Reset(n) is input to a high level, G(n) to a low level, Data(m) to the data voltage Vdata, and EM(n) to a high level, the second switch transistor T6 turns off, the second control transistor T4 and the third control transistor T5 turn off, the first control transistor T2, the first switch transistor T3, the drive transistor T1 and the fourth control transistor T7 turn on, Vdata charges Cst by the first control transistor T2, the drive transistor T1 and the first switch transistor T3, raising the potential of the gate electrode of the drive transistor T1 until the potential of the gate electrode of the drive transistor T1 changes to Vdata + Vth (where Vth is the threshold voltage of the drive transistor T1), the first switch transistor T3 turns off, the potential of N1 is stored by Cst, and the potential of the anode electrode of the OLED is reset to the initial voltage by opening the fourth control transistor T7.

[0185] In the third stage t3 (i.e., the light emission stage), Reset(n) is a high level input, G(n) is a high level input, and EM(n) is a low level input, causing the drive transistor T1, the first control transistor T2, the first switch transistor T3, the second switch transistor T6, and the fourth control transistor T7 to turn off, the second control transistor T4 and the third control transistor T5 to turn on, the OLED to emit light, and the drive current I that the drive transistor T1 drives the light emission of the OLED is equal to (1 / 2)K(Vdata-Vdd)², where K is the current coefficient and Vdd is the power supply value of the power supply voltage input by ELVDD.

[0186] In the pixel driving circuit shown in Figure 25, the source electrode T3s of the first switch transistor T3 is electrically connected to the gate electrode T1g of the driving transistor T1, and the drain electrode T6d of the second switch transistor T6 is electrically connected to the gate electrode T1g of the driving transistor T1. When light rays are shone on the first switch transistor T3 and the second switch transistor T6, a light-generating leakage current exists even when the first switch transistor T3 and the second switch transistor T6 are in the off state, which can further affect the potential of the gate electrode T1g of the driving transistor T1 and potentially cause inaccurate display gradation. The display panel integrating the hole-capturing function according to the embodiment of this disclosure adjusts the installation position and method of the capture hole to ensure the accuracy of hole-capturing fingerprint recognition and reduce the influence of the capture hole on display quality and display accuracy.

[0187] For example, specific fingerprint recognition areas may be individually set on the display panel, or the entire screen may be designated as a fingerprint recognition area.

[0188] In embodiments of the present disclosure, the display panel may include a base substrate extending from bottom to top, a buffer layer, an array layer, a second source-drain metal layer, a flat layer, an anode electrode layer, a pixel definition layer, an emitting layer, and a cathode electrode layer. The array layer includes an active layer sequentially extending from bottom to top, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source-drain metal layer, and a second insulating layer.

[0189] The first gate metal layer is used to form structures such as gate lines, light emission control lines, and gate electrodes of each transistor in the pixel driving circuit.

[0190] The second gate metal layer is used to form the electrode plates and initial voltage lines of the storage capacitor.

[0191] The first source-drain metal layer is used to form structures such as data lines, the first power line, the source electrodes of each transistor in the pixel driving circuit, and the drain electrodes of each transistor in the pixel driving circuit.

[0192] The second source-drain metal layer is multilayered as a light-shielding layer, and imaging holes are formed on the light-shielding layer.

[0193] For example, since the anode electrode layer needs to be electrically connected to the first source-drain metal layer to complete the circuit structure, a second source-drain metal layer (i.e., a light-shielding layer) needs to be provided, further including a connection pattern, and the first source-drain metal layer is electrically connected to the anode electrode layer via a first via hole penetrating the second insulating layer, a connection pattern, and a second via hole penetrating the flat layer.

[0194] For example, the active layer pattern may include a channel region, a source electrode region, and a drain electrode region. The channel region does not need to be doped with impurities, and therefore has semiconductor properties. The source electrode region is provided on the first side of the channel region, and the drain electrode region is provided on the second side of the channel region, and the first and second sides are opposite each other, and are doped with impurities and therefore have conductivity. The impurities may vary depending on whether the transistor is an n-type transistor or a p-type transistor.

[0195] For example, the doping source electrode region may correspond to the source electrode of the transistor, and the doping drain electrode region may correspond to the drain electrode of the transistor.

[0196] Figure 27 is a schematic diagram of a second source-drain metal layer in a display panel according to one embodiment of the present disclosure. In Figure 27, the symbol L0 is a connection pattern included in the second source-drain metal layer, the symbol SE is a light-shielding pattern included in the second source-drain metal layer, the symbol H0 is a camera hole, and the symbol F1 is a light leakage gap. The connection pattern L1 included in the first source-drain metal layer is used for electrical connection between the drain electrode of the third control transistor T5 and the connection pattern L0 included in the second source-drain metal layer. The connection pattern L0 included in the second source-drain metal layer is used for electrical connection between the connection pattern L1 included in the second source-drain metal layer and the anode electrode layer.

[0197] Figure 28 is a layout diagram of a display panel according to one embodiment of the present disclosure. In Figure 28, the code Data(m) is the data line in the mth column, the code Data(m+1) is the data line in the m+1th column, the code ELVDD is the first power line, the code Vint is the initial voltage line, the code Reset(n) is the reset line in the nth row, the code Reset(n+1) is the reset line in the n+1th row, the code EM(n) is the light emission control line in the nth row, the code EM(n+1) is the light emission control line in the n+1th row, the code G(n) is the gate line in the nth row, and the code G(n+1) is the gate line in the n+1st row.

[0198] In Figure 28, reference numeral 16g denotes the channel region of the active layer pattern of the second switch transistor T6, reference numeral 16s denotes the source electrode region of the active layer pattern of the second switch transistor T6, reference numeral 16d denotes the drain electrode region of the active layer pattern of the second switch transistor T6, reference numeral 13g denotes the channel region of the active layer pattern of the first switch transistor T3, reference numeral 11g denotes the channel region of the active layer pattern of the drive transistor T1, reference numeral 11d denotes the drain electrode region of the active layer pattern of the drive transistor T1, reference numeral 11s denotes the source electrode region of the active layer pattern of the drive transistor T1, reference numeral 12g denotes the channel region of the active layer pattern of the first control transistor T2, reference numeral 12s denotes the source electrode region of the active layer pattern of the first control transistor T2, and reference numeral 14g denotes the second The channel region of the active layer pattern of the control transistor T4 is denoted by 14s, the source electrode region of the active layer pattern of the second control transistor T4 is denoted by 15g, the channel region of the active layer pattern of the third control transistor T5 is denoted by 15d, the drain electrode region of the active layer pattern of the third control transistor T5 is denoted by 17g, the channel region of the active layer pattern of the fourth control transistor T7 is denoted by 17s, the source electrode region of the active layer pattern of the fourth control transistor T7 is denoted by Csa, the first electrode plate of the storage capacitor Cst is denoted by 16g', the channel region of the active layer pattern of the second switch transistor in the pixel region of the (n+1)th row and mth column is denoted by 16d', and the drain electrode region of the active layer pattern of the second switch transistor in the pixel region of the (n+1)th row and mth column is denoted by 16d'.

[0199] In Figure 28, the symbol H0 represents the imaging hole. When H0 is orthogonally projected onto the base substrate, the active layer pattern of the first switch transistor T3 does not overlap with the orthogonal projection onto the base substrate. When H0 is orthogonally projected onto the base substrate, the active layer pattern of the second switch transistor T6 does not overlap with the orthogonal projection onto the base substrate. When H0 is orthogonally projected onto the base substrate, it does not overlap with the active layer pattern of the second switch transistor in the pixel region of the (n+1)th row and mth column. As a result, the active layer patterns of the first switch transistor T3, the active layer patterns of the second switch transistor T6, and the active layer pattern of the second switch transistor in the pixel region of the (n+1)th row and mth column are not illuminated by light rays passing through the imaging hole H0. This avoids the existence of photo-generated leakage current in each switch transistor in the off state due to light irradiation, and further avoids affecting the potential of the gate electrode of the drive transistor T1, thus avoiding the problem of inaccurate display gradation.

[0200] In Figure 28, the distance d1 between the periphery of the orthographic projection of H0 onto the base substrate and 16g' is greater than the distance d2 between the periphery of the orthographic projection of H0 onto the base substrate and 15g.

[0201] In Figure 28, the shortest distance from the periphery of the orthographic projection of H0 onto the base substrate to the active layer of the first switch transistor T3 is greater than the distance from the periphery of the orthographic projection of H0 onto the base substrate to the active layer of any one transistor other than the first switch transistor T3 and the second switch transistor T6, and the shortest distance from the periphery of the orthographic projection of H0 onto the base substrate to the active layer of the second switch transistor T6 is greater than the distance from the periphery of the orthographic projection of H0 onto the base substrate to the active layer of any one transistor other than the first switch transistor T3 and the second switch transistor T6.

[0202] Furthermore, in the display panel shown in Figure 28, 11d communicates with the source electrode region of the active layer pattern of the third control transistor T5, 15d communicates with the drain electrode region of the active layer pattern of the fourth control transistor T7, 16d communicates with the source electrode region of the active layer pattern of the first switch transistor T3, 11s communicates with the drain electrode region of the active layer pattern of the second control transistor T4, 11d communicates with the drain electrode region of the active layer pattern of the third control transistor T5, and 11s communicates with the drain electrode region of the active layer pattern of the first control transistor T2.

[0203] For example, the symbol T6g' is the gate electrode of the second switch transistor in the pixel region at the (n+1)th row and mth column.

[0204] In Figures 25 and 28, the symbol T1g is the gate electrode of the drive transistor T1, the symbol T2g is the gate electrode of the first control transistor T2, the symbol T3g is the gate electrode of the first switch transistor T3, the symbol T4g is the gate electrode of the second control transistor T4, the symbol T5g is the gate electrode of the third control transistor T5, the symbol T6g is the gate electrode of the second switch transistor T6, and the symbol T7g is the gate electrode of the fourth control transistor T7.

[0205] In Figures 25 and 28, the crosses enclosed in square frames represent beer halls.

[0206] In Figure 28, the vertical lines other than the data lines and the first power line are connection lines.

[0207] The display panel according to the embodiment of the present disclosure shown in Figure 28 designs the position of the imaging hole to maintain the accuracy of hole imaging and recognition, and reduces the influence of the hole imaging system on display quality, particularly display accuracy, thereby improving display quality.

[0208] As shown in Figure 28, the symbol An1 is the first anode electrode included in the anode electrode layer, the symbol An2 is the second anode electrode included in the anode electrode layer, the symbol An3 is the third anode electrode included in the anode electrode layer, and the symbol An4 is the fourth anode electrode included in the anode electrode layer.

[0209] The first anode electrode An1 contained in the anode electrode layer is electrically connected to the drain electrode of the third control transistor T5 by connection patterns L0 and L1 contained in the second source-drain metal layer.

[0210] Figure 28 shows the data line Data(m+2) in column m+2, the data line Data(m+3) in column m+3, and the first power lines in two columns, and further shows the fifth anode electrode An5, the sixth anode electrode An6, and the seventh anode electrode An7 included in the anode electrode layer.

[0211] In Figure 28, An1 may be the anode electrode of a blue organic light-emitting diode, An5 may be the anode electrode of a red organic light-emitting diode, and An7 may be the anode electrode of a green organic light-emitting diode, but is not limited to these.

[0212] In Figure 28, the imaging aperture H0 is provided within the pixel region enclosed by Reset(n), Reset(n+1), D(m), and D(m+1), but is not limited to this.

[0213] For example, a certain distance is required between the imaging hole H0 and the connection pattern L0, and the orthographic projection of the light leakage gap F1 between the connection pattern L0 and the light-shielding pattern SE onto the base substrate requires that the metal electrodes included in the array layer (e.g., electrode plates of a storage capacitor) are covered by the orthographic projection onto the base substrate. However, due to limitations in manufacturing precision, the width of the light leakage gap F1 cannot be made infinitely narrow, and the radius of the imaging hole H0, the dimensions of the connection pattern L0, and the distance between the imaging hole H0 and the connection pattern L0 cannot be made infinitely small due to limitations in manufacturing precision. Therefore, the area of ​​each pattern in the pixel region where the imaging hole is provided may be appropriately enlarged compared to the area of ​​each pattern in the pixel region where the imaging hole is not provided, thereby ensuring that the orthographic projection of the light leakage gap F1 between the connection pattern L0 and the light-shielding pattern SE onto the base substrate requires that the metal electrodes included in the array layer (e.g., electrode plates of a storage capacitor) are covered by the orthographic projection onto the base substrate.

[0214] A method for manufacturing a display panel according to an embodiment of the present disclosure shown in Figure 28 may include the steps of: forming an array layer on a base substrate; forming a light-shielding layer on one side of the array layer away from the base substrate; forming a plurality of imaging holes on the light-shielding layer; ensuring that the imaging holes do not overlap the active layer pattern of the switch transistors in the array layer with the second imaging hole on the base substrate; and the switch transistors being transistors connected to the gate electrodes of the drive transistors in the array layer.

[0215] In a display panel according to another embodiment of the present disclosure, a light-shielding layer and imaging holes in the light-shielding layer may not be provided. The structure of the display panel according to an embodiment of the present disclosure is not limited to that shown in Figure 28.

[0216] Figure 29 is a layout diagram of a display panel according to another embodiment of the present disclosure. Compared to the display panel shown in Figure 28, the display panel shown in Figure 29 does not have an imaging hole. The first anode electrode An1 is electrically connected to the drain electrode of the third control transistor T5 by connection patterns L01 and L11 included in the second source-drain metal layer. Alternatively, the second source-drain metal layer may not be provided, and the first anode electrode An1 is electrically connected to the drain electrode of the third control transistor T5 by connection patterns L11 included in the first source-drain metal layer. Of course, other suitable installation methods may be employed.

[0217] Figure 30 is a cross-sectional view of a display panel according to one embodiment of the present disclosure. As shown in Figure 30, the display panel includes a first base substrate BS1, a first stopper layer BR1, and a second base substrate BS2. A first transistor 01 and a second transistor 02 are provided on the second base substrate BS2. The first transistor 01 is connected to an anode electrode AN.

[0218] As shown in Figure 30, the first transistor 01 includes an active layer ACT1, a first gate electrode insulating layer GI1, a first gate electrode GT1, a first source electrode SE1, and a first drain electrode DE1. The first source electrode SE1 includes two layers: source electrode SE11 and source electrode SE12. The first drain electrode DE1 includes two layers: drain electrode DE11 and drain electrode DE12.

[0219] As shown in Figure 30, the second transistor 02 includes an active layer ACT2, a second gate electrode insulating layer GI2, a second gate electrode GT2, a second source electrode SE2, and a second drain electrode DE2. The second source electrode SE2 includes two layers: source electrode SE21 and source electrode SE22. The second drain electrode DE2 includes two layers: drain electrode DE21 and drain electrode DE22.

[0220] As shown in Figure 30, the display panel further includes a first interlayer dielectric layer ILD1, a second buffer layer BF2, a second interlayer dielectric layer ILD2, an inert layer PVX, a first flat layer PLN1, a second flat layer PLN2, a pixel definition layer PDL, and a support layer PS. The pixel definition layer PDL and the support layer PS may, but are not limited to, be formed using the same film layer and employing the same patterning process.

[0221] For example, referring to Figures 30 and 29, drain electrodes DE11 and DE12 in Figure 30 may be connection patterns L11 and L01 in Figure 29, respectively.

[0222] For example, the first active layer ACT1 is a polycrystalline silicon semiconductor layer, and the second active layer ACT2 is an oxide semiconductor layer, with the polycrystalline silicon semiconductor layer being even closer to the base substrate. For example, the base substrate is a flexible base, and both the first base substrate BS1 and the second base substrate BS2 are flexible base substrates, and may, but are not limited to, polyimide. For example, the material of the first stopper layer BR1 may be SiOx or SiNx or a laminate thereof, and its thickness is between 400 nm and 800 nm. For example, the base substrate may further employ other flexible plastic bases. For example, the base substrate may further employ a glass or quartz material base substrate.

[0223] For example, a second stopper layer BR2 and a first buffer layer BF1 are further provided between the second base substrate BS2 and the first transistor 01. The second stopper layer BR2 may, but is not limited to, silicon oxide. The first buffer layer BF1 may include buffer layer BF11 and buffer layer BF12. Buffer layer BF11 may be made of SiNx, and buffer layer BF12 may be made of SiOx. The thickness of the first buffer layer BF1 is 600 to 1000 nm. The thickness of buffer layer BF11 is between 400 and 600 nm. The first buffer layer BF1 may be a single layer instead of a multilayer. The function of buffer layer BF11 (SiNx) is to prevent impurity particles in the base substrate from entering the semiconductor region and affecting the characteristics of the transistor. At least one of buffer layer BF11, buffer layer BF12, first stopper layer BR1, and second stopper layer BR2 may be a barrier layer as described above.

[0224] For example, the thickness of the first active layer ACT1 is 30 to 70 nm, and a polycrystalline silicon semiconductor layer may be used. The polycrystalline silicon semiconductor layer can be used as the channel of the drive transistor. For example, a light-blocking layer may be formed before forming the polycrystalline silicon, and then the polycrystalline silicon may be formed after forming SiOx on the light-blocking layer.

[0225] For example, the first gate electrode insulating layer GI may be made of SiOx, and its thickness may be 80 to 180 nm.

[0226] For example, the first gate electrode GT1 may be made of Mo, Ti, Cu, or an alloy thereof, and its thickness is 15 to 350 nm.

[0227] For example, a first gate electrode may be formed, and a conductive pattern may be formed in the same layer as the oxide semiconductor region. This conductive pattern may also serve as a barrier layer for subsequent oxide layers, preventing degradation of the oxide semiconductor layer's properties due to light irradiation.

[0228] For example, the first interlayer insulating layer ILD1 may employ a three-layer laminated structure of SiOx, SiNx, and SiOx. For instance, the thickness of the first interlayer insulating layer ILD1 is 100 to 350 nm, and the SiOx layer is adjacent to the oxide semiconductor layer. By having a greater thickness than the SiNx layer, the properties of the oxide are ensured.

[0229] For example, the second buffer layer BF2 may be made of SiOx.

[0230] For example, the thickness of the second active layer ACT2 is 30-60 nm, and IGZO may be used, but is not limited to it.

[0231] For example, the second gate electrode insulating layer GI2 may be made of SiOx, and its thickness may be 100 to 300 nm.

[0232] For example, the second gate electrode GT2 may be made of Mo, Ti, Cu, or an alloy thereof, and its thickness may be 15 to 350 nm.

[0233] For example, the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may be made of at least one of SiOx and SiNx. For example, the first interlayer dielectric layer ILD1 may be made of a two-layer stacked structure of SiNx / SiOx, and the second interlayer dielectric layer ILD2 may be made of SiOx.

[0234] For example, the first gate electrode insulating layer GI1 and the second gate electrode insulating layer GI2 may be made of at least one of SiOx and SiNx.

[0235] For example, the inert layer PVX may be made of SiOx, and its thickness may be 200 to 500 nm.

[0236] For example, the first flat layer PLN1, the second flat layer PLN2, the pixel definition layer PDL, and the support layer PS may all be made of polyimide, but are not limited to that.

[0237] As shown in Figure 30, the placement of source electrodes SE21 and SE22 can improve the stability of the second transistor 02 by protecting the second active layer ACT2.

[0238] An OLED display device can be formed by forming an organic functional layer and a cathode electrode on the structure shown in Figure 30, and then packaging it. A touch structure may be formed on the packaging layer, and the touch structure may, but is not limited to, a metal mesh.

[0239] Figure 30 further shows conductive member 03 and conductive member 04. Conductive member 03 and conductive member 04 may each be conductive member CL according to embodiments of the present disclosure. As shown in Figure 30, conductive member 03, source electrode SE21, drain electrode DE22, source electrode SE11 and drain electrode DE12 are formed using the same film layer and employing the same patterning process. As shown in Figure 30, conductive member 04, source electrode SE12 and drain electrode DE12 are formed using the same film layer and employing the same patterning process. For example, both the source electrode and the drain electrode are formed using a metal or alloy material.

[0240] Figure 31 is a cross-sectional view of a display panel according to another embodiment of the present disclosure. The display panel shown in Figure 31 does not have source electrodes SE21 and SE22 compared to the display panel shown in Figure 30.

[0241] In the display panel according to the embodiments of this disclosure, the first conductive member CL1 and the second conductive member CL2 may be located in areas with high electrostatic generation, such as pad areas, or in areas with low electrostatic generation, such as pixel areas. To ensure a reduction in resistance, the third conductive sublayer is not installed to protrude from the second surface; that is, a normal conductive member is provided. For example, a conductive member having a third conductive sublayer protruding from the second surface and a normal conductive member have a boundary, and this boundary is located outside the display area to avoid electrostatic influence on the pixel area. The pad area includes, but is not limited to, at least one of a pad area attached to an external circuit, a pad area for array testing, and a pad area to which a touch circuit is bound.

[0242] It should be explained that the first conductive sublayer 101, the second conductive sublayer 102, and the third conductive sublayer 103 in the figure form a planar structure that is perfectly parallel to the base substrate 100, but are not limited to this. Depending on the characteristics of the film layer shape beneath the conductive member, it may be naturally formed on an uneven surface, and it may also have a plane that is not perfectly flat, and in such examples, the above angle may be understood as a corresponding angle formed according to the surface of the conductive sublayer, but are not limited to this.

[0243] Figure 32 is a partial plan view of a display panel according to an embodiment of the present disclosure. Figure 33 is an enlarged schematic view of the data selector in Figure 32. The display panel will be described below with reference to Figures 32 and 33.

[0244] For example, as shown in Figure 32, the conductive member CL is electrically connected to the first conductive part 61, and the display panel shown in Figure 32 is illustrated as an example in which the first conductive part 61 is a data line DL and the conductive member CL is a pad PD. The data line DL provides a data voltage to each pixel unit SP. The pad PD is used to connect to an external circuit. The external circuit includes, but is not limited to, an integrated circuit (IC). The conductive member CL and the first conductive part 61 are formed using the same film layer and employing the same patterning process. For example, the conductive member CL and the first conductive part 61 are located in the first source-drain metal layer LY3.

[0245] For example, the insulating layer between adjacent conductive members includes a first organic material (e.g., epoxy resin), and the insulating layer between adjacent first conductive parts is a second organic material different from the first organic material (e.g., polyimide) or an inorganic material (e.g., SiOx or silicon oxide or a laminate thereof). For example, the dielectric constant of the first organic material is smaller than that of the second organic material or the inorganic material.

[0246] For example, as shown in Figures 32 and 33, the display panel further includes a second conductive portion 62, and the second conductive portion 62 and the conductive member CL are provided in different layers. For example, the second conductive portion 62 and the conductive member CL are located in the same layer, but are not limited to that.

[0247] For example, as shown in Figures 32 and 33, a plurality of first conductive parts 61 and a plurality of second conductive parts 62 are provided, with a first spacing IN1 between adjacent conductive members CL and a second spacing IN2 between adjacent first conductive parts 61, wherein the first spacing IN1 is different from the second spacing IN2. For example, the first spacing IN1 is smaller than the second spacing IN2.

[0248] For example, as shown in Figure 33, the length of the conductive member CL is smaller than the length of the first conductive portion 61. In the embodiments of this disclosure, the length of one element is the dimension along the elongation direction of the element.

[0249] As shown in Figure 32, the conductive member CL is connected to the unfolded line FL, and the unfolded line FL is connected to the data line DL. The unfolded line FL is connected to the data line via a via hole that penetrates the DL insulating layer. The unfolded line FL includes unfolded line FL1 and unfolded line FL2, for example, one of unfolded line FL1 and unfolded line FL2 is located in the first gate metal layer LY1, and the other of unfolded line FL1 and unfolded line FL2 is located in the second gate metal layer LY2.

[0250] Figure 32 further shows the first power line PL1 and the second power line PL2, where multiple second power lines PL2 are connected to bus 311, and both the first power line PL1 and the second power line PL2 are located in the first source drain metal layer LY2.

[0251] Figure 32 further illustrates multiple gate lines GL and multiple pixel units SP. The gate lines GL extend along a first direction DR1, and the data lines DL extend along a second direction DR2. The multiple gate lines GL and multiple data lines DL are isolated from each other and define the multiple pixel units SP by intersecting each other. A first power line PL1 is configured to provide a first power supply voltage to the pixel units SP, and a second power line PL2 is configured to provide a second power supply voltage to the pixel units SP. For example, the first power line PL1 is a VDD line, and the second power line PL2 is a VSS line. For example, the second power line PL2 is connected to the cathode electrode of a light-emitting diode.

[0252] As shown in Figure 32, each pad PD is connected to two deployment lines FL1 by a data selector MUX, and further electrically connected to two data lines DL. For example, after the data signal reaches the data selector MUX, the data signal is transmitted to the two data lines DL connected to the data selector MUX by controlling the first signal line L1 and the second signal line L2 to be turned on for different periods. The installation method of the data selector MUX may refer to a typical design. The data selector MUX is not limited to connecting two data lines DL, and the number of data lines DL connected to the data selector MUX may be determined as needed.

[0253] Referring to Figures 32 and 33, each data selector MUX includes an active layer ACTL, the portion of the active layer ACTL covered by the first signal line L1 and the second signal line L2 is a channel region, and the portion of the active layer ACTL not covered by the first signal line L1 and the second signal line L2 is a conductor. The first end of the active layer ACTL is connected to one data line DL, the second end of the active layer ACTL is connected to another data line DL, and the third end of the active layer ACTL is connected to the pad PD by the second conductive portion 62. The first, second, and third ends of the active layer ACTL are all located in the conductive portion of the active layer ACTL and may be connected to the active layer ACTL by an adapter (which may be located in the first source-drain metal layer).

[0254] The first conductive portion 61 is not limited to data lines. For example, each pixel unit includes a pixel circuit layer provided on a barrier layer, an organic electroluminescent element electrically connected to the pixel circuit layer, and a touch electrode provided on the light-emitting side of the organic electroluminescent element, and the first conductive portion 61 is any one of the pixel circuit layer, the organic electroluminescent element, or the touch electrode.

[0255] Figure 34A is a partial cross-sectional view of a display panel according to one embodiment of the present disclosure. Figure 34A is a partial cross-sectional view of the area indicated by the dashed circle B1 in Figure 32. As shown in Figure 34A, a barrier layer BR and an insulating layer ISL1 are provided on a base substrate 100, and the second conductive portion 62 is located on the insulating layer ISL1. The conductive member CL has a first end E1, and the second conductive portion 62 has a second end E2. An insulating layer ISL2 is provided between the first end E1 and the second end E2, and the insulating layer ISL2 has a first via hole V1 that exposes the second end E2, and the conductive member CL is connected to the second conductive portion 62 via the first via hole V1. When the conductive member CL is located below the second conductive portion 62, the insulating layer ISL2 has a first via hole that exposes the first end E1. In some other embodiments, the second conductive portion 62 may be located between the barrier layer BR and the insulating layer ISL1, thereby allowing the first via hole V1 to penetrate the insulating layer ISL1 and the insulating layer ISL2.

[0256] Figure 34B is a partial cross-sectional view of a display panel according to one embodiment of the present disclosure. Figure 34B is a partial cross-sectional view of the area indicated by the dashed circle B2 in Figure 32. As shown in Figures 32 and 34B, the display panel further includes a third conductive portion 63 to which a conductive member CL is electrically connected, the third conductive portion 63 having a third end E3, the first conductive portion 61 having a fourth end E4, an insulating layer ISL2 provided between the third end E3 and the fourth end E4, the insulating layer ISL2 having a second via hole V2 exposing the third end E3, and the first conductive portion 61 being electrically connected to the third conductive portion 63 via the second via hole V2. When the conductive member CL is located below the third conductive portion 63, the insulating layer ISL2 has a second via hole V2 exposing the fourth end. In some other embodiments, the third conductive portion 63 may be located between the barrier layer BR and the insulating layer ISL1, thereby allowing the first via hole V1 to penetrate the insulating layer ISL1 and the insulating layer ISL2.

[0257] Figure 35 is a partial plan view of a display panel according to one embodiment of the present disclosure. For example, as shown in Figure 35, the conductive member CL includes a first portion PT1 and a second portion PT2, the width of the first portion PT1 is greater than the width of the second portion PT2, the third conductive sublayer 103 of the first portion PT1 protrudes from the second surface S2 along the width direction of the conductive member CL, and the third conductive sublayer 103 of the second portion PT2 is coplanar with the second surface S2 along the width direction of the conductive member CL. Of course, in other embodiments, the third conductive sublayers 103 of both the first portion PT1 and the second portion PT2 may protrude from the second surface S2 along the width direction of the conductive member CL, and the width of the third conductive sublayer 103 of the first portion PT1 protruding from the second surface S2 along the width direction of the conductive member CL is greater than the width of the third conductive sublayer 103 of the second portion PT2 protruding from the second surface S2 along the width direction of the conductive member CL.

[0258] For example, in an embodiment of the present disclosure, a conductive member having a structure in which a third conductive sublayer protrudes from a second surface of a second conductive sublayer along the width direction of the conductive member is not covered by a flat layer. For example, the first conductive portion 61 provided in the same layer as the conductive member CL shown in FIG. 32 is covered by a flat layer, and the conductive member CL is not covered by a flat layer.

[0259] At least one embodiment of the present disclosure provides a display device including any one of the above display panels.

[0260] For example, the display device may be a display device such as a liquid crystal display, an electronic paper, an organic light-emitting diode (OLED) display, or any product or member having a display function including these, such as a television, a digital camera, a mobile phone, a wristwatch, a tablet computer, a notebook computer, a navigator, etc.

[0261] For example, in an embodiment of the present disclosure, the conductive member may be part or all of a conductive structure, and the conductive member may be a pattern formed of a continuous metal structure or a stacked structure of a plurality of metal conductive patterns.

[0262] It should be noted that, for clarity, in the accompanying drawings for explaining the embodiments of the present disclosure, the thickness of a layer or region is enlarged. When an element such as a layer, a film, a region, or a substrate is referred to as being located "above" or "below" another element, the element may be located "directly" "above" or "below" the other element, or there may be an intermediate element.

[0263] In the embodiments of the present disclosure, the shape of each element is only a schematic description and is not limited to that shown in the drawings, and may be determined as needed.

[0264] When there is no conflict, the features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0265] The above description represents only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modification or substitution that a person skilled in the art could easily conceive of within the technical scope presented in the Disclosure should be included within the scope of protection of the Disclosure. Therefore, the scope of protection of the Disclosure should be based on the scope of protection of the claims.

Claims

1. A display area having multiple pixel units, A peripheral region located on at least one side of the display area, A barrier layer located on the base substrate, A conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially laminated, provided on one side of the barrier layer away from the base substrate, and whose length in the extension direction is greater than its width in the direction intersecting the extension direction, wherein the first conductive sublayer is a conductive member that is closer to the base substrate than the third conductive sublayer, A first conductive portion, which is located in the display area and is formed using the same film layer and the same patterning process as the conductive member, The conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, and the melting point of the third conductive sublayer is higher than that of the second conductive sublayer. The second conductive sublayer includes a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, wherein the first surface and the second surface are provided opposite to each other, and the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, the width direction intersects with the extension direction of the conductive member. The second conductive sublayer further includes a surface that connects the sides of the first surface and the second surface located on the same side of the second conductive sublayer, the surface includes at least two sub-surfaces arranged sequentially along a direction away from the first conductive sublayer, and the angle between the at least two sub-surfaces and the first conductive sublayer or a plane parallel to the first conductive sublayer increases sequentially along a direction away from the first conductive sublayer. Display panel, wherein the at least two sub-sides include a first sub-side, a second sub-side, and a third sub-side, the first sub-side being closer to the first conductive sub-layer than the third sub-side, the angle between the first sub-side and the first conductive sub-layer being a first angle, the angle between the second sub-side and a plane parallel to the first conductive sub-layer being a second angle, and the angle between the third sub-side and another plane parallel to the first conductive sub-layer being a third angle, the third angle being greater than the second angle, and the second angle being greater than the first angle.

2. The display panel according to claim 1, wherein the third conductive sublayer does not come into contact with the first conductive sublayer.

3. The display panel according to claim 1, wherein in a cross-section formed by the thickness direction of the conductive member and the width direction of the conductive member, the intersection point between the side surface and the first conductive sub-layer is a first intersection point, the intersection point between the side surface and the third conductive sub-layer is a second intersection point, and at least a portion of the side surface is bent in a direction away from the connection line between the first intersection point and the second intersection point.

4. The display panel according to claim 3, wherein the second conductive sublayer includes two sides, the two sides are arranged opposite to each other, and the two sides are arranged symmetrically along the thickness direction of the conductive member.

5. The display panel according to claim 1, wherein the width of the first surface is smaller than the width of the first conductive sublayer, the width of the second surface is smaller than the width of the third conductive sublayer, and the difference in width between the third conductive sublayer and the second surface is greater than the thickness of the third conductive sublayer.

6. The display panel according to claim 1, wherein two adjacent conductive members are provided, the two adjacent conductive members are insulated from each other, located in the same layer, and include a first conductive member and a second conductive member, the distance between the third conductive sublayer of the first conductive member and the third conductive sublayer of the second conductive member is smaller than the distance between the second surface of the second conductive sublayer of the first conductive member and the second surface of the second conductive sublayer of the second conductive member.

7. The display panel according to claim 6, wherein the width direction and extension direction of the conductive member are a first direction and a second direction, respectively, and the distance along the first direction between the second surface of the first conductive member and the second surface of the second conductive member differs at different positions along the second direction on the second surface of the first conductive member or on the second surface of the second conductive member.

8. The display panel according to claim 6, wherein w1 is the maximum width in the widthwise cross-section of the first conductive member, w2 is the maximum width in the widthwise cross-section of the second conductive member, Δw11 is the distance at which the third conductive sublayer in the first conductive member extends beyond the second surface, Δw12 is the distance at which the third conductive sublayer in the second conductive member extends beyond the second surface, and dmin is the minimum distance between the first conductive member and the second conductive member, and the following relation is satisfied. [Math 1]

9. A display panel according to claim 1, wherein two conductive members are provided, the two conductive members are insulated from each other, the distances from the two conductive members to the base substrate are different, the two conductive members include a first conductive member and a third conductive member, the thickness of the second conductive sublayer of the first conductive member is T3, the thickness of the second conductive sublayer of the third conductive member is T4, T4 is greater than T3, the distance at which the third conductive sublayer of the first conductive member extends beyond the second surface is Δw3, the distance at which the third conductive sublayer of the third conductive member extends beyond the second surface is Δw4, and the following relation is satisfied. [Math 2]

10. The display panel according to claim 1, wherein two conductive members are provided, the two conductive members being insulated from each other, and comprising a first conductive member and a second conductive member, the first conductive member being closer to the display area than the second conductive member, and the dimension by which the third conductive sublayer in the first conductive member protrudes from the second surface is greater than the dimension by which the third conductive sublayer in the second conductive member protrudes from the second surface.

11. The display panel according to claim 1, further comprising a second conductive portion, wherein the second conductive portion and the conductive member are provided in different layers, the conductive member has a first end, the second conductive portion has a second end, an insulating layer is provided between the first end and the second end, the insulating layer has a first via hole that exposes the first end or the second end, and the conductive member is connected to the second conductive portion via the first via hole.

12. The display panel according to claim 1, further comprising a second conductive portion, wherein the second conductive portion and the conductive member are located in the same layer.

13. The display panel according to claim 1, further comprising a third conductive portion, wherein the first conductive portion is electrically connected to the third conductive portion, the third conductive portion has a third end, the first conductive portion has a fourth end, an insulating layer is provided between the third end and the fourth end, the insulating layer has a second via hole that exposes the third end or the fourth end, and the first conductive portion is electrically connected to the third conductive portion via the second via hole.

14. The display panel according to claim 1, wherein the conductive member includes a first portion and a second portion, the width of the first portion is greater than the width of the second portion, the third conductive sublayer of the first portion protrudes from the second surface along the width direction of the conductive member, the third conductive sublayer of the second portion is coplanar with the second surface along the width direction of the conductive member, or both the third conductive sublayers of the first portion and the second portion protrude from the second surface along the width direction of the conductive member, and the protruding width of the first portion is greater than the protruding width of the second portion.

15. The display panel according to claim 1, wherein the conductive member is electrically connected to the first conductive portion, a plurality of first conductive portions are provided, having a first interval between adjacent conductive members and a second interval between adjacent first conductive portions, the first interval being different from the second interval.

16. A display area comprising a foldable area having a plurality of pixel units, and a display area including a first display area and a second display area located on opposite sides of the foldable area, A peripheral region located on at least one side of the display area, A barrier layer located on the base substrate, A conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially laminated, provided on one side of the barrier layer away from the base substrate, and whose length in the extension direction is greater than its width in the direction intersecting the extension direction, wherein the first conductive sublayer is a conductive member that is closer to the base substrate than the third conductive sublayer, A first conductive portion, which is located in the display area and is formed using the same film layer and the same patterning process as the conductive member, The conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, and the melting point of the third conductive sublayer is higher than that of the second conductive sublayer. The second conductive sublayer includes a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, wherein the first surface and the second surface are provided opposite to each other, and the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, the width direction intersects with the extension direction of the conductive member. The second conductive sublayer further includes a surface that connects the sides of the first surface and the second surface located on the same side of the second conductive sublayer, the surface includes at least two sub-surfaces arranged sequentially along a direction away from the first conductive sublayer, and the angle between the at least two sub-surfaces and the first conductive sublayer or a plane parallel to the first conductive sublayer increases sequentially along a direction away from the first conductive sublayer. Display panel, wherein the at least two sub-sides include a first sub-side, a second sub-side, and a third sub-side, the first sub-side being closer to the first conductive sub-layer than the third sub-side, the angle between the first sub-side and the first conductive sub-layer being a first angle, the angle between the second sub-side and a plane parallel to the first conductive sub-layer being a second angle, and the angle between the third sub-side and another plane parallel to the first conductive sub-layer being a third angle, the third angle being greater than the second angle, and the second angle being greater than the first angle.

17. A display area having multiple pixel units, A peripheral region located on at least one side of the display area, A light-transmitting region located on one side of the peripheral region away from the display region or surrounded by the display region, A barrier layer located on the base substrate, A conductive member comprising a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer, which are sequentially laminated, provided on one side of the barrier layer away from the base substrate, and whose length in the extension direction is greater than its width in the direction intersecting the extension direction, wherein the first conductive sublayer is a conductive member that is closer to the base substrate than the third conductive sublayer, A first conductive portion, which is located in the display area and is formed using the same film layer and the same patterning process as the conductive member, The conductivity of the first conductive sublayer is less than that of the second conductive sublayer, the thickness of the first conductive sublayer is less than that of the second conductive sublayer, and the melting point of the third conductive sublayer is higher than that of the second conductive sublayer. The second conductive sublayer includes a first surface adjacent to the first conductive sublayer and a second surface adjacent to the third conductive sublayer, wherein the first surface and the second surface are provided opposite to each other, and the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, the width direction intersects with the extension direction of the conductive member. The second conductive sublayer further includes a surface that connects the sides of the first surface and the second surface located on the same side of the second conductive sublayer, the surface includes at least two sub-surfaces arranged sequentially along a direction away from the first conductive sublayer, and the angle between the at least two sub-surfaces and the first conductive sublayer or a plane parallel to the first conductive sublayer increases sequentially along a direction away from the first conductive sublayer. Display panel, wherein the at least two sub-sides include a first sub-side, a second sub-side, and a third sub-side, the first sub-side being closer to the first conductive sub-layer than the third sub-side, the angle between the first sub-side and the first conductive sub-layer being a first angle, the angle between the second sub-side and a plane parallel to the first conductive sub-layer being a second angle, and the angle between the third sub-side and another plane parallel to the first conductive sub-layer being a third angle, the third angle being greater than the second angle, and the second angle being greater than the first angle.

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