Transparent display device

Abstract

To provide a transparent display device having a high light transmittance and capable of improving reflection characteristics.SOLUTION: A transparent display device according to one or more embodiments of this specification may include a substrate including a non-transmissive area having a light-emitting area in which a light-emitting element is arranged and a transmissive area, at least one gate line crossing the non-transmissive area and the transmissive area on the substrate, and a gate bridge pattern arranged in the transmissive area on the substrate and at least partially overlapping at least one gate line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This specification relates to a transparent display device. [Background technology]

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. As a result, in recent years, display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), micro light-emitting diodes (Micro LEDs), and quantum dot displays (QDs) have been utilized.

[0003] Recently, there has been a surge in research on transparent display devices that not only display images to the user but also allow light to pass through, enabling the user to see objects or images located behind the display device. A transparent display device includes a display area where an image is displayed and a non-display area, and the display area may include a transparent area that can transmit external light and an opaque area. A transparent display device can have high light transmittance in the display area through the transparent area.

[0004] Such transparent display devices have high potential for use in various fields because they allow images and backgrounds to be viewed together. However, because of the diverse range of fields and applications, they need to be manufactured in a variety of types (or sizes). However, when manufacturing transparent display devices in a variety of types (or sizes), the number of processes increases, leading to higher manufacturing costs and increased production energy. [Overview of the project] [Problems that the invention aims to solve]

[0005] The problem to be solved by one or more examples of this specification is to provide a transparent display device that has high light transmittance and can improve reflectivity characteristics.

[0006] The problem to be solved by one or more embodiments of this specification is to provide a transparent display device that can be manufactured in a wide variety (or in a wide range of sizes).

[0007] The problems addressed by one or more embodiments of this specification are not limited to those described above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A transparent display device according to one or more embodiments of this specification may include a substrate including an opaque region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged; at least one gate line crossing the opaque region and the transparent region on the substrate; and a gate bridge pattern arranged in the transparent region on the substrate and at least partially overlapping the at least one gate line.

[0009] Specific details, other than the solutions to the problems mentioned above, are included in the following descriptions and figures.

[0010] According to the embodiments of this specification, a transparent display device can be provided that has high light transmittance and improved reflectivity characteristics.

[0011] According to the embodiments of this specification, a transparent display device can be provided that can be manufactured in a wide variety (or in various sizes).

[0012] The effects described herein are not limited to those mentioned above, and any other effects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0013] Since the content of the invention described in the problems to be solved, the means for solving the problems, and the effects does not specify the essential features of the claims, the scope of rights of the claims is not restricted by the matters described in the content of the invention.

Brief Description of the Drawings

[0014] [Figure 1] It is a diagram showing a transparent display device according to an embodiment of this specification. [Figure 2] It is a circuit diagram of a sub-pixel of a transparent display device according to an embodiment of this specification. [Figure 3] It is a diagram showing the A region shown in FIG. 1 according to an embodiment of this specification. [Figure 4] It is a diagram showing the B region shown in FIG. 3 according to an embodiment of this specification. [Figure 5] It is a diagram showing the C region shown in FIG. 4 according to an embodiment of this specification. [Figure 6] It is a cross-sectional view of line I-I' shown in FIG. 5 according to an embodiment of this specification. [Figure 7] It is a diagram showing the B region shown in FIG. 3 according to another embodiment of this specification. [Figure 8] It is a diagram showing the D region shown in FIG. 7 according to another embodiment of this specification. [Figure 9] It is a cross-sectional view of line II-II' shown in FIG. 8 according to another embodiment of this specification. [Figure 10] It is a diagram showing the B region shown in FIG. 3 according to another embodiment of this specification. [Figure 11] It is a diagram showing the E region shown in FIG. 10 according to another embodiment of this specification. [Figure 12] It is a cross-sectional view of line III-III' shown in FIG. 11 according to another embodiment of this specification. [Figure 13] It is a diagram showing the B region shown in FIG. 3 according to another embodiment of this specification. [Figure 14] It is a diagram showing the F region shown in FIG. 13 according to another embodiment of this specification. [Figure 15]It is a cross-sectional view of line IV-IV' shown in FIG. 14 according to another embodiment of the present specification.

Embodiments for Carrying Out the Invention

[0015] The advantages and features of the present specification, and the methods for achieving them, will become apparent by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, but is embodied in various different forms, and merely these embodiments are provided to make the disclosure of the present specification complete and to fully inform those with ordinary knowledge in the technical field to which the present specification belongs of the scope of the invention, and the present specification is only defined by the scope of the claims.

[0016] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, and the present specification is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to the same components. Also, in the description of the present specification, when it is determined that a specific description of related known technologies may unnecessarily obscure the gist of the present specification, the detailed description thereof is omitted.

[0017] When terms such as "including", "having", "consisting of", etc. mentioned in the present specification are used, other parts can be added unless "only" is used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0018] In interpreting a component, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0019] In the case of an explanation of the positional relationship, for example, when the positional relationship between two parts is explained by "on", "above", "below", "beside", etc., unless an expression such as "immediately" or "directly" is used, one or more other parts can also be located between the two parts.

[0020] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0021] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0022] In describing the components of this specification, terms such as 1st, 2nd, A, B, (a), or (b) may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component.

[0023] Where it is stated that one component “connects,” “joins,” “connects,” or “adheres” to another component, it should be understood that the component may directly connect, join, connect, or adhere to the other component, but that other components may “intersect” between each component that can indirectly connect, join, connect, or adhere, unless otherwise explicitly stated.

[0024] Where it is stated that a component or layer "contacts" or "overlaps" with another component or layer, it should be understood that the component or layer may directly contact or overlap with another component or layer, but other components may be interposed between each component that may indirectly contact or overlap, unless otherwise explicitly stated.

[0025] The term "at least one" should be understood to include all combinations of one or more of the relevant components. For example, "at least one of the first, second, and third components" may mean not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

[0026] Each feature of some of the embodiments described herein can be combined or combined with one another, either partially or as a whole, and various technical interdependencies and drives are possible. Each embodiment can be implemented independently of one another or together in a related manner.

[0027] The embodiments of this specification will be described in detail below through the attached figures and examples. The scales of the components shown in the figures are different from those of actual components for the sake of explanation and are not limited to those shown in the figures.

[0028] Figure 1 shows a transparent display device according to an embodiment of this specification. Figure 2 is a circuit diagram of a subpixel of the transparent display device according to an embodiment of this specification.

[0029] In the following, the X-axis represents the direction parallel to the scan lines, the Y-axis represents the direction parallel to the data lines, and the Z-axis represents the height direction of the transparent display device.

[0030] Although the transparent display device according to one embodiment of this specification has been primarily described as being implemented using an Organic Light Emitting Display (OLED), it can also be implemented using Liquid Crystal Displays (LCDs), Micro Light Emitting Diodes (Micro LED Displays), Quantum Dot Displays (QDs), and the like.

[0031] Referring to Figures 1 and 2, a transparent display device according to one embodiment of this specification may include a transparent display panel 110 that includes a display area (DA) where pixels are formed to display an image and a non-display area (NDA) where no image is displayed.

[0032] The display area (DA) of the transparent display panel 110 may include a first signal line (SL1), a second signal line (SL2), and pixels, and the non-display area (NDA) may include a pad area (PA) where pads are located and at least one gate drive unit 205.

[0033] The first signal line (SL1) can be extended in the first direction (or Y-axis direction) and can intersect with the second signal line (SL2) in the display area (DA). The second signal line (SL2) can be extended in the second direction (or X-axis direction). Pixels are arranged in the region where the first signal line (SL1) and the second signal line (SL2) intersect, and can emit predetermined light to display an image.

[0034] The gate driver unit 205 can be connected to the scan line to supply a scan signal. Such a gate driver unit 205 can be implemented in the non-display area (NDA) on one or both sides of the display area (DA) of the transparent display panel 110 using a GIP (gate driver in panel) method or a TAB (tape automated bonding) method.

[0035] The pad area (PA) of the transparent display panel 110 can be electrically connected to a source drive integrated circuit, a circuit board, or a timing control unit, etc., via a flexible circuit film.

[0036] Referring to Figure 2, each pixel includes multiple subpixels that constitute a unit pixel, and each of the multiple subpixels may, but is not limited to, a circuit element having a 3T(Transistor)1C(Capacitor) structure including a first switching transistor (TR1), a second switching transistor (TR2), a drive transistor (DTR), and a capacitor (Cst), and a light-emitting element (ED). Each subpixel may further include a compensation circuit, in which case it can have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0037] Each of the transistors (DTR, TR1, TR2) in each subpixel can include a gate electrode, a source electrode, and a drain electrode. The source electrode and drain electrode are not fixed and can be changed by the direction of the voltage and current applied to the gate electrode, so one of the source electrode and drain electrode can be represented as the first electrode and the other as the second electrode. Each of the transistors (DTR, TR1, TR2) in each subpixel can be at least one of polysilicon semiconductors, amorphous silicon semiconductors, or oxide semiconductors. The transistors (DTR, TR1, TR2) can be P-type or N-type, or a mixture of P-type and N-type.

[0038] The first switching transistor (TR1) can supply the data voltage (Vdata) from the data line (DL) to the drive transistor (DTR). For example, the first switching transistor (TR1) can charge a capacitor (Cst) with the data voltage (Vdata) supplied from the data line (DL). To this end, the first switching transistor (TR1) can have its gate electrode connected to the scan line (SCANL) (or gate line) and its first electrode connected to the data line (DL). In addition, the first switching transistor (TR1) can have its second electrode connected to one end of the capacitor (Cst) and the gate electrode of the drive transistor (DTR).

[0039] The first switching transistor (TR1) can be turned on in response to a scan signal (Scan) applied via the scan line (SCANL) (or gate line). When the first switching transistor (TR1) is turned on, the data voltage (Vdata) applied via the data line (DL) can be transmitted to one end of the capacitor (Cst).

[0040] The second switching transistor (TR2) can supply a reference voltage (Vref) from the reference line (REFL) to the drive transistor (DTR). For example, the second switching transistor (TR2) can have its gate electrode connected to the scan line (SCANL) (or gate line) and its first electrode connected to the reference line (REFL). Alternatively, the second switching transistor (TR2) can have its second electrode connected to the first electrode of the drive transistor (DTR) and the other end of the capacitor (Cst).

[0041] The second switching transistor (TR2) can be turned on in response to a scan signal (Scan) applied via the scan line (SCANL) (or gate line). When the second switching transistor (TR2) is turned on, it can transmit the reference voltage (Vref) applied via the reference line (REFL) to the other end of the capacitor (Cst). The reference voltage (Vref) can also be applied to the source electrode of the drive transistor (DTR).

[0042] A capacitor (Cst) can play a role in maintaining the data voltage (Vdata) supplied to the drive transistor (DTR) for one frame. For example, the capacitor (Cst) may have its first electrode connected to the gate electrode of the drive transistor (DTR) and its second electrode connected to the source electrode of the drive transistor (DTR). The capacitor (Cst) stores a voltage corresponding to the data voltage (Vdata) transmitted through the first switching transistor (TR1), and can turn on the drive transistor (DTR) with the stored voltage.

[0043] A drive transistor (DTR) can generate data current from a first power supply (EVDD) supplied from the pixel power line (VDDL) and supply it to the anode electrode of the light-emitting element (ED). For example, a drive transistor (DTR) can have a gate electrode connected to one end of a capacitor (Cst) and a first electrode connected to the pixel power line (VDDL). Furthermore, a second electrode can be connected to the anode electrode of the light-emitting element (OLED).

[0044] The drive transistor (DTR) can be turned on by the data voltage charged in the capacitor (Cst). When the drive transistor (DTR) is turned on, it can transmit the first power supply (EVDD) applied via the pixel power line (VDDL) to the anode electrode of the light-emitting element (ED).

[0045] A light-emitting element (ED) may comprise an anode electrode connected to a drive transistor (DTR), a cathode electrode receiving a second power supply (EVSS) from a common power line (VSSL), and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode is an independent electrode for each light-emitting element, but the cathode electrode may be a common electrode shared by the entire light-emitting element. When a drive current is supplied from the drive transistor (DTR), electrons from the cathode electrode are injected into the light-emitting layer, and holes from the anode electrode are injected into the light-emitting layer. The recombination of electrons and holes in the light-emitting layer causes fluorescence or phosphorescence to be emitted, thereby generating light with a brightness proportional to the value of the drive current.

[0046] A light-emitting element (ED) can have its anode electrode connected to the second electrode of a drive transistor (DTR) and its cathode electrode connected to a common power line (VSSL). The light-emitting element (ED) can emit light in response to the drive current generated by the drive transistor (DTR).

[0047] Figure 3 shows area A shown in Figure 1 according to an embodiment of this specification. Figure 4 shows area B shown in Figure 3 according to one embodiment of this specification.

[0048] Referring to Figures 3 and 4 in conjunction with Figures 1 and 2, the transparent display panel 110 according to the embodiments of this specification may include a display area (DA) and a non-display area (NDA). The display area (DA) may include a transparent area (TA) and an opaque area (NTA). The transparent area (TA) may be an area that allows most of the light incident from the outside to pass through, and the opaque area (NTA) may be an area that does not allow most of the light incident from the outside to pass through. For example, the transparent area (TA) may be an area with a light transmittance greater than α%, and the opaque area (NTA) may be an area with a light transmittance less than β%, where α may be a value greater than β. The transparent display panel 110 allows viewing of objects or backgrounds located on the back (or rear) side of the transparent display panel 110 through the transparent area (TA).

[0049] The nontransparent region (NTA) may include a first nontransparent region (NTA1), a second nontransparent region (NTA2), and pixels (P).

[0050] The first opaque region (NTA1) can be extended in the first direction (or Y-axis direction) within the display region (DA) and positioned so as to overlap at least a portion of the light-emitting regions (EA1, EA2, EA3, EA4). Multiple first opaque regions (NTA1) can be composed of several. Multiple first opaque regions (NTA1) can be extended in the first direction (or Y-axis direction) and positioned spaced apart from each other in the second direction (or X-axis direction). Two adjacent first opaque regions (NTA1) can be positioned spaced apart from each other with a transparent region (TA) in between. For example, a transparent region (TA) can be positioned between two adjacent first opaque regions (NTA1). A first signal line (SL1) extended in the first direction (or Y-axis direction) can be placed within the first opaque region (NTA1). For example, the first signal line (SL1) can be positioned so as to overlap the first opaque region (NTA1).

[0051] The first signal line (SL1) may include at least one of the following: a pixel power line (VDDL), a common power line (VSSL), a reference line (REFL), and data lines (DL1, DL2, DL3, DL4). For example, the first signal line (SL1) may further include a touch sensor line (TL), but the embodiments herein are not limited thereto.

[0052] The pixel power line (VDDL) can supply a first power supply (EVDD) to the drive transistor (DTR) of each sub-pixel (SP1, SP2, SP3, SP4) provided in the display area (DA).

[0053] The common power line (VSSL) can supply a second power supply (EVSS) to the cathode electrodes of the sub-pixels (SP1, SP2, SP3, SP4) provided in the display area (DA). Here, the second power supply (EVSS) may be a common power supply supplied to all sub-pixels (SP1, SP2, SP3, SP4).

[0054] A reference line (REFL) can supply an initialization voltage (or reference voltage) to each of the drive transistors (DTR) of the subpixels (SP1, SP2, SP3, SP4) provided in the display area (DA). For example, a reference line (REFL) can be placed between multiple data lines (DL1, DL2, DL3, DL4). For example, a reference line (REFL) can be placed in the center of multiple data lines (DL1, DL2, DL3, DL4).

[0055] Each of the data lines (DL1, DL2, DL3, DL4) can supply a data voltage (Vdata) to a subpixel (SP1, SP2, SP3, SP4). For example, the first data line (DL1) can supply the first data voltage to the first drive transistor of the first subpixel (SP1), the second data line (DL2) can supply the second data voltage to the second drive transistor of the second subpixel (SP2), the third data line (DL3) can supply the third data voltage to the third drive transistor of the third subpixel (SP3), and the fourth data line (DL4) can supply the fourth data voltage to the fourth drive transistor of the fourth subpixel (SP4).

[0056] At least two touch sensor lines (TLs) can be placed in the first opaque region (NTA1). In the transparent display panel 110, if multiple touch sensor lines (TLs) are placed in the transparent region (TA), the light transmittance may decrease due to the multiple touch sensor lines (TLs). For this reason, touch sensor lines (TLs) can be placed in the first opaque region (NTA1) rather than in the transparent region (TA). For example, touch sensor lines (TLs) can be placed in the first opaque region (NTA1) so as to overlap with at least one of the pixel power lines (VDDL) and common power lines (VSSL). For example, touch sensor lines (TLs) can be placed in a different layer from the pixel power lines (VDDL) and common power lines (VSSL). Touch sensor lines (TLs) do not need to overlap with circuit regions (CA1, CA2, CA3, CA4) where circuit elements are placed, and can be placed so as to overlap with at least one of the pixel power lines (VDDL) and common power lines (VSSL), or adjacent to them. For example, multiple touch sensor lines can be arranged in the first opaque region (NTA1). For instance, if four touch sensor lines are arranged, two of the touch sensor lines can overlap with or be adjacent to the pixel power line (VDDL), and the other two touch sensor lines can overlap with or be adjacent to the common power line (VSSL). However, the embodiments herein are not limited to these examples.

[0057] The second opaque region (NTA2) can be extended in the second direction (or X-axis direction) within the display region (DA) and positioned so as to overlap at least a portion of the light-emitting regions (EA1, EA2, EA3, EA4). For example, the second opaque region (NTA2) can be extended in the second direction (or X-axis direction) between two adjacent first opaque regions (NTA1). Multiple second opaque regions (NTA2) can be composed of. Multiple second opaque regions (NTA2) can be extended in the second direction (or X-axis direction) and positioned spaced apart from each other in the first direction (or Y-axis direction). Two adjacent second opaque regions (NTA2) can be positioned spaced apart from each other with a transparent region (TA) in between. For example, a transparent region (TA) can be positioned between two adjacent second opaque regions (NTA2). A second signal line (SL2) extended in the second direction (or X-axis direction) can be placed in the second opaque region (NTA2). For example, the second signal line (SL2) can be placed so as to overlap the second opaque region (NTA2).

[0058] The second signal line (SL2) may extend in a second direction (or X-axis direction) and may include a scan line (SCANL) (or gate line). The scan line (SCANL) can supply scan signals to subpixels (SP1, SP2, SP3, SP4) of a pixel (P).

[0059] Pixels (P) are arranged in each intersection region where a first opaque region (NTA1) and a second opaque region (NTA2) intersect, and can emit light to display an image. Each pixel (P) is arranged between adjacent transparent regions (TA), and each pixel (P) may include light-emitting regions (EA1, EA2, EA3, EA4) where light-emitting elements are located and emit light. The light-emitting regions (EA1, EA2, EA3, EA4) can correspond to the regions where light is emitted by the pixels (P). Because the area of ​​the opaque regions (NTA) of the transparent display panel 110 is small, circuit elements can be arranged so as to overlap with the light-emitting regions (EA1, EA2, EA3, EA4). For example, the light-emitting regions (EA1, EA2, EA3, EA4) can overlap at least partially with the circuit regions (CA1, CA2, CA3, CA4) where the circuit elements are located. For example, the circuit regions (CA1, CA2, CA3, CA4) may include a first circuit region (CA1) where a circuit element connected to the first subpixel (SP1) is located, a second circuit region (CA2) where a circuit element connected to the second subpixel (SP2) is located, a third circuit region (CA3) where a circuit element connected to the third subpixel (SP3) is located, and a fourth circuit region (CA4) where a circuit element connected to the fourth subpixel (SP4) is located.

[0060] The first to fourth light-emitting regions (EA1, EA2, EA3, EA4) can all emit light of different colors. For example, the first light-emitting region (EA1) can emit green light, the second light-emitting region (EA2) can emit red light, and the third light-emitting region (EA3) can emit blue light. The fourth light-emitting region (EA4) can emit white light, but is not necessarily limited to this. Furthermore, the arrangement order and configuration of each subpixel (SP1, SP2, SP3, SP4) can be changed in various ways.

[0061] The transparent display panel 110 according to the embodiments of this specification may include multiple light-emitting regions (EA1, EA2, EA3, EA4) within each of the multiple subpixels (SP1, SP2, SP3, SP4) that are divided into multiple light-emitting regions. For example, each of the first to fourth light-emitting regions (EA1, EA2, EA3, EA4) may include a first divided light-emitting region and a second divided light-emitting region, but the embodiments of this specification are not limited thereto.

[0062] Each pixel circuit (CA1, CA2, CA3, CA4) of multiple subpixels (SP1, SP2, SP3, SP4) can include a capacitor (Cst), at least one thin-film transistor (DTR, TR1, TR2), and a light-emitting element (ED), as shown in Figure 2. For example, at least one thin-film transistor (DTR, TR1, TR2) can include a drive transistor (DTR), a first switching transistor (TR1), and a second switching transistor (TR2). The light-emitting element (ED) can also include a first electrode (or anode electrode, pixel electrode), a light-emitting layer (or organic light-emitting layer), and a second electrode (or cathode electrode, common electrode).

[0063] The transparent display panel 110 according to the embodiments herein may further include at least one undercut line (UCL) extending in a first direction (or Y-axis direction) in the transparent region (TA).

[0064] At least one undercut line (UCL) can serve to interrupt the light-emitting layer (or organic light-emitting layer) formed in the transmission region (TA). At least one undercut line (UCL) can consist of a portion of at least one protective layer (e.g., a planarization layer and a passivation layer). For example, at least one undercut line (UCL) can be formed by removing at least a portion of at least one protective layer (e.g., a planarization layer and a passivation layer). Below at least one undercut line (UCL), a scan line (SCANL) (or gate line) can be placed across the transmission region (TA). A block pattern (BP) may further be included where at least one undercut line (UCL) and the scan line (SCANL) intersect. For example, the block pattern (BP) can prevent damage to the scan line (SCANL) intersecting below at least one undercut line (UCL) during the process of forming at least one undercut line (UCL).

[0065] At least one undercut line (UCL) can be located in at least two locations within a transparent region (TA). At least one undercut line (UCL) can be located adjacent to at least one of the pixel power lines (VDDL) and common power lines (VSSL) within the transparent region (TA). For example, at least one undercut line (UCL) can be located adjacent to both the pixel power line (VDDL) and the common power line (VSSL) within the transparent region (TA). For example, at least one undercut line (UCL) can consist of multiple undercut lines (UCL1, UCL2) within a single transparent region (TA). Multiple undercut lines (UCL1, UCL2) can include a first undercut line (UCL1) and a second undercut line (UCL2). For example, the first undercut line (UCL1) can be positioned adjacent to a pixel (P1) on one side of the transparent region (TA), and the second undercut line (UCL2) can be positioned adjacent to a pixel (P2) on the other side of the transparent region (TA).

[0066] A first undercut line (UCL1) can disconnect the light-emitting layer (or organic light-emitting layer) extending from a pixel (P1) on one side of the transmission region (TA), and a second undercut line (UCL2) can disconnect the light-emitting layer (or organic light-emitting layer) extending from a pixel (P2) on the other side of the transmission region (TA). The area between the first undercut line (UCL1) and the second undercut line (UCL2) may be a region disconnected from the light-emitting layers (or organic light-emitting layers) of the respective pixels (P1, P2) on one and the other side of the transmission region (TA). For example, the first undercut line (UCL1) and the second undercut line (UCL2) can be formed by removing at least a portion of at least one protective layer (e.g., a planarization layer and a passivation layer). For example, at least one protective layer may include an organic insulating layer, and the first undercut line (UCL1) and the second undercut line (UCL2) can be formed by removing at least a portion of the organic insulating layer, thereby disrupting the organic insulating layer. This prevents moisture permeation between the pixel (P1) on one side of the transparent region (TA) and the transparent region (TA) by the first undercut line (UCL1), and prevents moisture permeation between the pixel (P2) on the other side of the transparent region (TA) and the transparent region (TA) by the second undercut line (UCL2). Therefore, even if the region between the first undercut line (UCL1) and the second undercut line (UCL2) is cut by a cutting device such as a laser or wheel, moisture permeation to each pixel (P1, P2) on one side and the other side of the transparent region (TA) can be prevented.

[0067] The transparent display panel 110 according to the embodiment of this specification is configured such that a first undercut line (UCL1) and a second undercut line (UCL2) extend in a first direction (or Y-axis direction) within the transparent region (TA). The first undercut line (UCL1) prevents moisture from penetrating toward adjacent pixels (P1), and the second undercut line (UCL2) prevents moisture from penetrating toward adjacent pixels (P2). As a result, the space between the first undercut line (UCL1) and the second undercut line (UCL2) can become a cuttable region that prevents moisture from penetrating toward pixels (P1, P2) even when cut (or separated). Therefore, the transparent display panel 110 according to the embodiment of this specification can embody or realize a cuttable transparent display panel that can be divided and manufactured in various sizes depending on the field and application to which the transparent display panel 110 is applied, by providing a cuttable region by the undercut line (UCL) in the transparent region (TA).

[0068] Figure 5 shows region C shown in Figure 4 according to one embodiment of this specification. Figure 6 is a cross-sectional view of the line I-I' shown in Figure 5 according to one embodiment of this specification.

[0069] Referring to Figures 5 and 6, the transparent display panel 110 according to the embodiments herein may include at least one first signal line (e.g., a data line (DL), a touch sensor line (TL), a common power line (VSSL)) located in an opaque region (NTA) and extending in a first direction (or Y-axis direction), at least one second signal line (e.g., a scan line (SCANL)) extending across a transparent region (TA) in a second direction (or X-axis direction), and at least one undercut line (UCL) located in the transparent region (TA) and extending in a first direction (or Y-axis direction).

[0070] Specifically, a touch sensor line (TL) of the first signal lines can be placed on the substrate 111. The touch sensor line (TL) can be placed so as to extend in the first direction (or Y-axis direction) in the non-transparent region (NTA). For example, the touch sensor line (TL) can be placed so as to overlap with at least one of the pixel power line (VDDL) and the common power line (VSSL). For example, the touch sensor line (TL) can be placed on a different layer from the pixel power line (VDDL) and the common power line (VSSL). For example, the touch sensor line (TL) can be placed so as to overlap with the common power line (VSSL).

[0071] A touch sensor line (TL) can be located at the bottom edge of the substrate 111. The touch sensor line (TL) can be formed on the same layer as the light-shielding layer located on the substrate 111, and of the same material. For example, the light-shielding layer can serve to block external light incident on the active layer of a thin-film transistor. The light-shielding layer can consist of a single or multiple layer made of one of the following materials or alloys: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, a first signal line formed on the same layer as the light-shielding layer on the substrate 111, and of the same material, can form at least one of the following: a touch sensor line (TL), a pixel power line (VDDL), a common power line (VSSL), a reference line (REFL), and a data line (DL), but the embodiments herein are not limited thereto.

[0072] A buffer layer (BF) can be placed on the substrate 111 on which the touch sensor line (TL) and light-shielding layer are arranged. The buffer layer (BF) is intended to protect the thin-film transistor from moisture that may penetrate through the substrate 111, which may be susceptible to moisture permeability, and is made of silicon oxide (SiO X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0073] A second signal line, the scan line (SCANL), can be placed on the buffer layer (BF). The scan line (SCANL) can be placed in the non-transparent region (NTA) and the transparent region (TA). For example, at least a portion of the scan line (SCANL) can be placed so as to extend in the second direction (or the X-axis direction) across the transparent region (TA). At least a portion of the scan line (SCANL) can be placed so as to intersect with at least one of the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). For example, the scan line (SCANL) can be placed on a different layer from the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). The scan line (SCANL) may include a portion that is bent at least once and extends in the first direction (or the Y-axis direction).

[0074] Scanlines (SCANL) can be formed on the same layer and of the same material as the gate electrode of a thin-film transistor placed on a buffer layer (BF). For example, a thin-film transistor can be placed on a buffer layer (BF). The thin-film transistor may include an active layer, a gate insulating layer, a gate electrode, and source / drain electrodes, all placed on the buffer layer (BF). The gate insulating layer can be placed between the active layer and the gate electrode. For example, the gate insulating layer can be formed only in the region where the gate electrode is located. An interlayer insulating layer (ILD) can be placed between the gate electrode and the source / drain electrodes of the thin-film transistor.

[0075] A repair line (RL) for repairing dark spots of a light-emitting element can be placed on the same layer as the scan line (SCANL). For example, the first electrode (or anode electrode) of the light-emitting element can be divided into a first divided electrode and a second divided electrode, and the repair line (RL) can electrically connect the divided first and second divided electrodes to the pixel circuit. For example, the repair line (RL) can be positioned to intersect with a touch sensor line (TL) placed on the substrate 111. The repair line (RL) can be made of a different material and on a different layer from the touch sensor line (TL). For example, the touch sensor line (TL) can be made of the same material as the light-shielding layer, and the repair line (RL) and the touch sensor line (TL) can be separated from each other by a buffer layer (BF).

[0076] An interlayer insulating layer (ILD) can be placed on the substrate 111 on which scan lines (SCANL) and repair lines (RL) are arranged. The interlayer insulating layer (ILD) is made of silicon oxide (SiO X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0077] Source / drain electrodes of a thin-film transistor can be placed on the interlayer insulating layer (ILD). At least some of the following can be formed on the same layer as the source / drain electrodes: touch sensor lines (TL), pixel power lines (VDDL), common power lines (VSSL), reference lines (REFL), and data lines (DL). For example, the source / drain electrodes can be formed on the same layer as the data lines (DL) and from the same material, but the embodiments herein are not limited thereto.

[0078] A first passivation layer (PAS1) can be placed on the interlayer insulating layer (ILD) where the source / drain electrodes and data line (DL) are located. A second passivation layer (PAS2) can be placed on the first passivation layer (PAS1). The first passivation layer (PAS1) and the second passivation layer (PAS2) are made of silicon oxide (SiO2). X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0079] Pixel power lines (VDDL) and common power lines (VSSL) can be placed on the first passivation layer (PAS1). For example, the pixel power lines (VDDL) and common power lines (VSSL) can be placed between the first passivation layer (PAS1) and the second passivation layer (PAS2). The pixel power lines (VDDL) and common power lines (VSSL) can be placed so as to overlap with the touch sensor lines (TL) on the substrate 111.

[0080] A planarization layer (PLN) can be placed on the second passivation layer (PAS2) to flatten the steps caused by thin-film transistors and multiple signal lines. The planarization layer (PLN) can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0081] The transparent display panel 110 according to the embodiments of this specification can have an undercut line (UCL) formed using a planarization layer (PLN) and a second passivation layer (PAS2). For example, the undercut line (UCL) can be formed to extend in a first direction (or Y-axis direction) in the transparent region (TA). The undercut line (UCL) can be formed by removing at least a portion of the planarization layer (PLN) and the second passivation layer (PAS2). For example, the undercut line (UCL) can be formed as a line-shaped structure extending along the first direction (or Y-axis direction) by removing a portion of the planarization layer (PLN), or as a column structure supporting the planarization layer (PLN) with a line-shaped eaves structure by removing a portion of the second passivation layer (PAS2) inward from the planarization layer (PLN). For example, an undercut line (UCL) can be formed by a column structure consisting of a second passivation layer (PAS2) and an eaves structure consisting of a flattening layer (PLN) on the upper surface of the second passivation layer (PAS2) of the column structure.

[0082] A scan line (SCANL) (or gate line) can be placed below the undercut line (UCL) and across the transmissive area (TA). A block pattern (BP) can be placed where the undercut line (UCL) and scan line (SCANL) intersect. For example, a block pattern (BP) can be formed where the undercut line (UCL) and scan line (SCANL) intersect.

[0083] Block patterns (BPs) are designed to prevent damage to scan lines (SCANLs) from the etching solution used when forming undercut lines (UCLs). For example, block patterns (BPs) can be formed between undercut lines (UCLs) and scan lines (SCANLs). Block patterns (BPs) can be formed on the first passivation layer (PAS1). For example, block patterns (BPs) can be formed from the same material as other signal lines formed on the first passivation layer (PAS1). For example, block patterns (BPs) can be formed from the same material on the same layer as pixel power lines (VDDLs) and common power lines (VSSLs).

[0084] The transparent display panel 110 according to the embodiments of this specification embodies or realizes a cuttable transparent display panel that can be divided and manufactured into various sizes according to the field and application to which the transparent display panel 110 is applied, by providing a cuttable area by an undercut line (UCL) in the transparent area (TA). However, the transparent display panel 110 according to the embodiments of this specification may have reduced light transmittance or reduced reflectivity due to at least one scan line (SCANL) crossing the transparent area (TA) and a block pattern (BP) arranged in the transparent area (TA). Therefore, the inventors of this specification have invented a new transparent display device with a structure that can improve the light transmittance and reflectivity of the transparent display panel 110 through various studies and experiments.

[0085] In the following sections, with reference to Figures 7 to 15, we will describe in more detail other transparent display devices according to this specification that can improve the light transmittance of the transparent display panel 110 and enhance its reflectivity characteristics.

[0086] Figure 7 shows area B shown in Figure 3 according to another embodiment of this specification. Figure 8 shows area D shown in Figure 7 according to another embodiment of this specification. Figure 9 is a cross-sectional view of line II-II' shown in Figure 8 according to another embodiment of this specification. Figures 7 to 9 show modified scanline configurations in the transparent display panel 110 described with reference to Figures 1 to 6. Therefore, in the following description, the same reference numerals are used for the remaining identical components, excluding those related to the scanlines, and redundant descriptions thereof are omitted or simplified.

[0087] Referring to Figures 7 to 9, the transparent display panel 110 according to other embodiments of this specification may include at least one scanline (SCANL) and a gate bridge pattern (GBP).

[0088] At least one scanline (SCANL) may include a first scanline (SCANL1) and a second scanline (SCANL2). For example, the first scanline (SCANL1) and the second scanline (SCANL2) may be connected to pixels (P) corresponding to adjacent horizontal lines. For example, a horizontal line may mean that multiple pixels (P) are arranged parallel to each other along a second direction (or the X-axis direction). For example, the first scanline (SCANL1) may be connected to a pixel (P) corresponding to the lower of two adjacent horizontal lines. For example, the lower horizontal line may be a horizontal line corresponding to a pixel (P) located below the pixel (P) shown in Figure 7. The second scanline (SCANL2) may be connected to a pixel (P) corresponding to the upper of two adjacent horizontal lines. For example, the upper horizontal line may be a horizontal line corresponding to the pixel (P) shown in Figure 7, but the embodiments herein are not limited thereto. For example, the first scan line (SCANL1) and the second scan line (SCANL2) can provide different scan signals to pixels (P) corresponding to a single horizontal line. For instance, different scan signals can be provided to pixels (P) corresponding to horizontal lines corresponding to pixels (P) as shown in Figure 7.

[0089] The first scan line (SCANL1) can be located in the non-transparent area (NTA). For example, at least a portion of the first scan line (SCANL1) can be extended in a second direction (or the X-axis direction) within the non-transparent area (NTA). The first scan line (SCANL1) can be bent at least once within the non-transparent area (NTA) and extended in a first direction (or the Y-axis direction). For example, the first scan line (SCANL1) can be located in the non-transparent area (NTA) so as to overlap with at least one of the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL). The first scan line (SCANL1) can be located in a different layer from the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL). The first scan line (SCANL1) can include partitions (DP) that are separated from each other within the non-transparent area (NTA). For example, a discontinuation (DP) of the first scan line (SCANL1) can be formed at the point where it intersects with a repair line (RL) for repairing dark spots on the light-emitting element. The discontinuation (DP) of the first scan line (SCANL1) can be electrically connected by a coupling pattern (CP).

[0090] The second scan line (SCANL2) can be positioned in the non-transparent area (NTA) and the transparent area (TA). For example, at least a portion of the second scan line (SCANL2) can be positioned to extend in a second direction (or the X-axis direction) across the transparent area (TA). At least a portion of the second scan line (SCANL2) can be positioned to intersect with at least one of the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). For example, the second scan line (SCANL2) can be positioned on a different layer from the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). The second scan line (SCANL2) may include a portion that is bent at least once and extends in a first direction (or the Y-axis direction). The second scan line (SCANL2) can be formed on the same layer as the first scan line (SCANL1) and from the same material. The second scan line (SCANL2) can be electrically isolated from the first scan line (SCANL1) by being on the same layer and separated from each other.

[0091] A gate bridge pattern (GBP) can be placed in a transparent region (TA). The gate bridge pattern (GBP) can superimpose at least part of one scan line (SCANL). Furthermore, the gate bridge pattern (GBP) can be electrically connected to at least one scan line (SCANL). For example, the gate bridge pattern (GBP) can superimpose at least part of a first scan line (SCANL1) and a second scan line (SCANL2). The gate bridge pattern (GBP) can be electrically connected to the first scan line (SCANL1) and electrically isolated from the second scan line (SCANL2). For example, the gate bridge pattern (GBP) can be placed in a different layer from the first scan line (SCANL1) and the second scan line (SCANL2). The gate bridge pattern (GBP) can overlap the leading edge of the first scanline (SCANL1) and be electrically connected to the leading edge of the first scanline (SCANL1) through contact holes penetrating the insulating layer between the first scanline (SCANL1) and the gate bridge pattern (GBP). The gate bridge pattern (GBP) can be extended parallel to the second scanline (SCANL2). The gate bridge pattern (GBP) is not in direct contact with the second scanline (SCANL2) and can be separated from the second scanline (SCANL2) by at least one insulating layer. The gate bridge pattern (GBP) can be extended in the transmission region (TA) to overlap the second scanline (SCANL2) in a second direction (or X-axis direction).

[0092] Specifically, touch sensor lines (TL) and gate bridge patterns (GBP) can be arranged on the substrate 111. The touch sensor lines (TL) can be arranged to extend in a first direction (or Y-axis direction) in the non-transparent region (NTA). For example, the touch sensor lines (TL) can be arranged to overlap with at least one of the pixel power lines (VDDL) and common power lines (VSSL). The gate bridge patterns (GBP) can extend in a first direction (or Y-axis direction) in the non-transparent region (NTA), be bent in a second direction (or X-axis direction), and extended across the transparent region (TA). For example, the touch sensor lines (TL) and gate bridge patterns (GBP) can be formed in the same layer from the same material. The touch sensor lines (TL) and gate bridge patterns (GBP) can be arranged in layers different from the first scan line (SCANL1), second scan line (SCANL2), pixel power line (VDDL), and common power line (VSSL). For example, the touch sensor line (TL) can be positioned to overlap with the common power line (VSSL). The gate bridge pattern (GBP) can be positioned to overlap, at least partially, with the first scan line (SCANL1) and the second scan line (SCANL2).

[0093] The touch sensor line (TL) and gate bridge pattern (GBP) can be positioned at the bottom edge of the substrate 111. The touch sensor line (TL) and gate bridge pattern (GBP) can be formed on the substrate 111 in the same layer and from the same material as the light-shielding layer. For example, the light-shielding layer can block external light incident on the active layer of the thin-film transistor. The light-shielding layer can be formed as a single or multi-layer structure made of one of the following materials or alloys: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0094] A buffer layer (BF) can be placed on the substrate 111 on which the touch sensor line (TL), gate bridge pattern (GBP), and light-shielding layer are arranged. The buffer layer (BF) is for protecting the thin-film transistor from moisture that may penetrate through the substrate 111, which may be susceptible to moisture permeability, and is made of silicon oxide (SiO X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0095] A first scanline (SCANL1) and a second scanline (SCANL2) can be placed on the buffer layer (BF). The first scanline (SCANL1) can be placed in the non-transparent area (NTA), and the second scanline (SCANL2) can be placed in both the non-transparent area (NTA) and the transparent area (TA).

[0096] The first scan line (SCANL1) can be positioned to extend in a second direction (or X-axis direction) in the non-transparent area (NTA) and then bend and extend in the first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower of two adjacent horizontal lines. For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower of two adjacent horizontal lines, extend in a second direction (or X-axis direction), bend in the first direction (or Y-axis direction), and extend so as to overlap at least partially with the touch sensor line (TL). For example, a portion of the first scan line (SCANL1) can be extended so as to overlap with the touch sensor line (TL) in the first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be positioned to overlap with at least a portion of the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL) that extend in the first direction (or Y-axis direction).

[0097] A repair line (RL) for repairing dark spots of a light-emitting element can be placed on the same layer as the first scan line (SCANL1). For example, the first electrode (or anode electrode) of a light-emitting element can be divided into a first divided electrode and a second divided electrode, and the repair line (RL) can electrically connect the divided first and second divided electrodes to the pixel circuit. The first scan line (SCANL1) may include a segmentation section (DP) spaced at a certain interval in the portion extending in the first direction (or Y-axis direction). The segmentation section (DP) of the first scan line (SCANL1) can be formed in the portion that intersects with a repair line (RL) located on the same layer. The first scan line (SCANL1) can be separated from the repair line (RL) by the segmentation section (DP) and electrically isolated.

[0098] The leading edge of the first scan line (SCANL1) can be superimposed on the gate bridge pattern (GBP) on the substrate 111. The leading edge of the first scan line (SCANL1) can be electrically connected to the gate bridge pattern (GBP) through a contact hole that penetrates the buffer layer (BF) and exposes the gate bridge pattern (GBP). The gate bridge pattern (GBP) electrically connected to the first scan line (SCANL1) can perform the same signal transmission function as the first scan line (SCANL1).

[0099] The second scan line (SCANL2) can be positioned in the non-transparent area (NTA) and the transparent area (TA). At least a portion of the second scan line (SCANL2) can be positioned to extend in a second direction (or the X-axis direction) across the transparent area (TA). At least a portion of the second scan line (SCANL2) can be positioned to intersect with at least one of the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). For example, the second scan line (SCANL2) can be positioned in a different layer from the pixel power lines (VDDL), common power lines (VSSL), and touch sensor lines (TL). The scan line (SCANL) may include a portion that is bent at least once and extends in a first direction (or the Y-axis direction).

[0100] The portion of the second scan line (SCANL2) that extends across the transparent region (TA) in the second direction (or X-axis direction) can overlap with the gate bridge pattern (GBP). At least a portion of the second scan line (SCANL2) can extend parallel to and overlap with the gate bridge pattern (GBP). The second scan line (SCANL2) can be separated from the gate bridge pattern (GBP), which acts as the first scan line (SCANL1), by a buffer layer (BF) and electrically isolated. By sharing the region that crosses the transparent region (TA) with each other, the margin of the transparent region (TA) can be further secured, thereby improving the light transmittance of the transparent display panel 110.

[0101] The first scan line (SCANL1), the second scan line (SCANL2), and the repair line (RL) can be formed of the same material in the same layer as the gate electrode of the thin film transistor disposed on the buffer layer (BF). For example, a thin film transistor can be disposed on the buffer layer (BF). The thin film transistor can include an active layer, a gate insulating layer, a gate electrode, and source / drain electrodes disposed on the buffer layer (BF). The gate insulating layer can be disposed between the active layer and the gate electrode. For example, the gate insulating layer can be formed only in the region where the gate electrode is disposed. An interlayer insulating layer (ILD) can be disposed between the gate electrode and the source / drain electrodes of the thin film transistor.

[0102] An interlayer insulating layer (ILD) can be disposed on the substrate 111 on which the first scan line (SCANL1), the second scan line (SCANL2), and the repair line (RL) are disposed. The interlayer insulating layer (ILD) can be formed of a single layer or multiple layers including an inorganic insulating material such as silicon oxide (SiO X ), silicon nitride (SiN X ), aluminum oxide (Al2O3).

[0103] A connection pattern (CP) for electrically connecting the divided portion (DP) of the first scan line (SCANL1) can be disposed on the interlayer insulating layer (ILD). The connection pattern (CP) can be formed of the same material in the same layer as the source / drain electrodes of the thin film transistor disposed on the interlayer insulating layer (ILD). For example, the connection pattern (CP) and the source / drain electrodes can be formed of the same material in the same layer as the data line (DL), but the embodiments of the present specification are not limited thereto.

[0104] The coupling pattern (CP) can be superimposed on at least a portion of the first scanline (SCANL1) and on a repair line (RL) that passes through the divider (DP) of the first scanline (SCANL1). One end and the other end of the coupling pattern (CP) can be connected to the other end of the first scanline (SCANL1), which is separated from each other by the divider (DP), through contact holes that penetrate the interlayer insulation layer (ILD) and expose a portion of the first scanline (SCANL1). The one end and the other end of the first scanline (SCANL1), which are separated by the divider (DP), can be electrically connected to each other by the coupling pattern (CP).

[0105] A first passivation layer (PAS1) can be placed on the interlayer insulating layer (ILD) on which the coupling pattern (CP), source / drain electrodes, and data line (DL) are arranged. A second passivation layer (PAS2) can be placed on the first passivation layer (PAS1). The first passivation layer (PAS1) and the second passivation layer (PAS2) are made of silicon oxide (SiO2). X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0106] Pixel power lines (VDDL) and common power lines (VSSL) can be placed on the first passivation layer (PAS1). For example, the pixel power lines (VDDL) and common power lines (VSSL) can be placed between the first passivation layer (PAS1) and the second passivation layer (PAS2). The pixel power lines (VDDL) and common power lines (VSSL) can be placed so as to overlap with the touch sensor lines (TL) on the substrate 111. In addition, the pixel power lines (VDDL) and common power lines (VSSL) can be placed so as to overlap with the first scan line (SCANL1) placed between the buffer layer (BF) and the interlayer insulating layer (ILD). For example, the pixel power lines (VDDL) and common power lines (VSSL) can be placed so as to overlap with a portion of the first scan line (SCANL1) extending in the first direction (or Y-axis direction).

[0107] A planarization layer (PLN) can be placed on the second passivation layer (PAS2) to flatten the steps caused by thin-film transistors and multiple signal lines. The planarization layer (PLN) can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0108] An undercut line (UCL) can be formed in the transmissive region (TA) using a planarization layer (PLN) and a second passivation layer (PAS2) so as to extend in the first direction (or Y-axis direction). The undercut line (UCL) can be formed by removing at least a portion of the planarization layer (PLN) and the second passivation layer (PAS2).

[0109] Below the undercut line (UCL), a second scan line (SCANL2) and a gate bridge pattern (GBP) can be placed across the transmission area (TA). A block pattern (BP) can be placed where the undercut line (UCL), the second scan line (SCANL2), and the gate bridge pattern (GBP) intersect. For example, a block pattern (BP) can be formed where the undercut line (UCL), the second scan line (SCANL2), and the gate bridge pattern (GBP) intersect.

[0110] In other embodiments of this specification, the transparent display panel 110 can be made into a cuttable transparent display panel that can be manufactured in various sizes depending on the field and application to which the transparent display panel 110 is applied, by providing a cuttable area by an undercut line (UCL) in the transparent area (TA). In addition, in other embodiments of this specification, the transparent display panel 110 can have a gate bridge pattern (GBP) electrically connected to the first scan line (SCANL1) to replace the role of the first scan line (SCANL1). By sharing the area that crosses the transparent area (TA) with the second scan line (SCANL2), the placement of the first scan line (SCANL1) crossing the transparent area (TA) can be omitted, thereby further securing the margin of the transparent area (TA), and thereby improving the light transmittance of the transparent display panel 110. Furthermore, in other embodiments of this specification, the transparent display panel 110 can block external light incident through the substrate 111 by a gate bridge pattern (GBP) arranged to overlap with the second scan line (SCANL2) in the transparent region (TA), thereby improving the reflectivity characteristics of the transparent display panel 110.

[0111] Figure 10 shows area B shown in Figure 3 according to another embodiment of this specification. Figure 11 shows area E shown in Figure 10 according to another embodiment of this specification. Figure 12 is a cross-sectional view of line III-III' shown in Figure 11 according to another embodiment of this specification. Figures 10 to 12 show modified scanline configurations in the transparent display panel 110 described with reference to Figures 1 to 6. Therefore, in the following description, the same reference numerals are used for the remaining identical components except for those related to the scanlines, and redundant descriptions thereof are omitted or simplified.

[0112] Referring to Figures 10 to 12, the transparent display panel 110 according to other embodiments of this specification may include at least one scanline (SCANL) and a gate bridge pattern (GBP).

[0113] At least one scanline (SCANL) may include a first scanline (SCANL1) and a second scanline (SCANL2).

[0114] The first scan line (SCANL1) can be located in the non-transparent area (NTA). For example, at least a portion of the first scan line (SCANL1) can be extended in a second direction (or the X-axis direction) in the non-transparent area (NTA). The first scan line (SCANL1) can be bent at least once in the non-transparent area (NTA) and extended in a first direction (or the Y-axis direction). For example, the first scan line (SCANL1) can be located in the non-transparent area (NTA) so as to intersect with at least one of the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL). The first scan line (SCANL1) can be located on a different layer from the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL).

[0115] The first scan line (SCANL1) can be positioned to extend in a second direction (or X-axis direction) in the non-transparent area (NTA), crossing and passing through the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL), and then bend and extend in a first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower of two adjacent horizontal lines. For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower of two adjacent horizontal lines, extend in a second direction (or X-axis direction), crossing and passing through the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL), and then bend in a first direction (or Y-axis direction) to extend parallel to and adjacent to at least one of the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL). For example, a portion of the first scan line (SCANL1) can be arranged adjacent to and parallel to at least a portion of the touch sensor line (TL), pixel power line (VDDL), and common power line (VSSL) extending in the first direction (or Y-axis direction).

[0116] In other embodiments of this specification, the transparent display panel 110 can be made into a cuttable transparent display panel that can be manufactured in various sizes depending on the field and application to which the transparent display panel 110 is applied, by providing a cuttable area by an undercut line (UCL) in the transparent area (TA). In addition, in the transparent display panel 110 of the other embodiments of this specification, the margin of the transparent area (TA) can be further secured by having the second scan line (SCANL2) and the gate bridge pattern (GBP) share an area that crosses the transparent area (TA), thereby improving the light transmittance of the transparent display panel 110. Furthermore, in the transparent display panel 110 of the other embodiments of this specification, external light incident through the substrate 111 can be blocked by the gate bridge pattern (GBP) which is arranged to overlap with the second scan line (SCANL2) in the transparent area (TA), thereby improving the reflectivity characteristics of the transparent display panel 110. Furthermore, the transparent display panel 110 according to other embodiments of this specification can prevent the occurrence of parasitic capacitance by minimizing the area in which the first scan line (SCANL1) overlaps with the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL). This improves the driving reliability of the transparent display panel 110.

[0117] Figure 13 shows area B shown in Figure 3 according to another embodiment of this specification. Figure 14 shows area F shown in Figure 13 according to another embodiment of this specification. Figure 15 is a cross-sectional view of line IV-IV' shown in Figure 14 according to another embodiment of this specification. Figures 13 to 15 show modified scanline configurations in the transparent display panel 110 described with reference to Figures 1 to 6. Therefore, in the following description, the same reference numerals are used for the remaining identical components, excluding those related to the scanlines, and redundant descriptions thereof are omitted or abbreviated.

[0118] Referring to Figures 13 to 16, the transparent display panel 110 according to other embodiments of this specification may include at least one scanline (SCANL) and a linked bridge pattern (CBP).

[0119] At least one scanline (SCANL) can be positioned in the nontransparent area (NTA) and the transparent area (TA). At least a portion of the at least one scanline (SCANL) can be positioned to extend in a second direction (or the X-axis direction) across the transparent area (TA).

[0120] An undercut line (UCL) can be formed in the transmissive region (TA) using a planarization layer (PLN) and a second passivation layer (PAS2) so as to extend in the first direction (or Y-axis direction). An undercut line (UCL) can be formed by removing at least a portion of the planarization layer (PLN) and the second passivation layer (PAS2).

[0121] Below the undercut line (UCL), at least one scan line (SCANL) can be positioned across the transmissive area (TA). The at least one scan line (SCANL) may include a discontinuity (DP) that is isolated for a certain distance at the point where it intersects the undercut line (UCL). The discontinuity (DP) of the at least one scan line (SCANL) can be electrically connected by a connecting bridge pattern (CBP).

[0122] Specifically, a connecting bridge pattern (CBP) formed from the same material as the light-shielding layer can be placed on the substrate 111. The connecting bridge pattern (CBP) can be placed in the area where a scan line (SCANL) and an undercut line (UCL) intersect in the transmission region (TA). For example, the connecting bridge pattern (CBP) can be formed from a single layer or multiple layers of any one of the following materials, or an alloy thereof: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0123] A buffer layer (BF) can be placed on the substrate 111 on which the linked bridge pattern (CBP) and light-shielding layer are arranged. The buffer layer (BF) is intended to protect the thin-film transistor from moisture that may penetrate through the substrate 111, which may be susceptible to moisture permeability, and is made of silicon oxide (SiO X ), silicon nitride (SiN X ), or it can be formed as a single or multi-layer structure containing an inorganic insulating material such as aluminum oxide (Al2O3).

[0124] At least one scan line (SCANL) can be placed on the buffer layer (BF). At least one scan line (SCANL) can be placed in an opaque region (NTA) and a transparent region (TA). For example, at least a portion of at least one scan line (SCANL) can be placed so as to extend in a second direction (or the X-axis direction) across the transparent region (TA). At least one scan line (SCANL) can include a divided portion (DP) spaced at a certain distance apart at the point where it intersects an undercut line (UCL) in the transparent region (TA). The divided portions (DP) of at least one scan line (SCANL) can be formed to be spaced apart from each other with the undercut line (UCL) in between. One end and the other end of at least one scan line (SCANL) spaced apart with the divided portion (DP) in between can be connected to a connecting bridge pattern (CBP) through a contact hole that penetrates the buffer layer (BF) and exposes a portion of the connecting bridge pattern (CBP). At least one scanline (SCANL) separated by a divergence (DP) can be electrically connected to each other by a coupling bridge pattern (CBP).

[0125] On a substrate 111 on which at least one scanline (SCANL) is placed, an interlayer insulating layer (ILD), a first passivation layer (PAS1), a second passivation layer (PAS2), and a planarization layer (PLN) can be placed.

[0126] An undercut line (UCL) can be formed in the transmissive region (TA) using a planarization layer (PLN) and a second passivation layer (PAS2) so as to extend in the first direction (or Y-axis direction). The undercut line (UCL) can be formed by removing at least a portion of the planarization layer (PLN) and the second passivation layer (PAS2).

[0127] At least one scan line (SCANL) intersecting an undercut line (UCL) can be separated from the undercut line (UCL) by an interlayer insulating layer (ILD) and a first passivation layer (PAS1). This prevents at least one scan line (SCANL) from being damaged by the etching solution used when the undercut line (UCL) is formed, without the need to form a separate block pattern in the transparent display panel 110 according to other embodiments of this specification.

[0128] The transparent display panel 110 according to other embodiments of this specification embodies or realizes a cuttable transparent display panel that can be manufactured in various sizes depending on the field and application to which the transparent display panel 110 is applied, by providing a cuttable area by an undercut line (UCL) in the transparent area (TA). Furthermore, the transparent display panel 110 according to other embodiments of this specification can further secure the margin of the transparent area (TA) by eliminating the formation of a separate block pattern at the intersection of the undercut line (UCL) and at least one scan line (SCANL), thereby improving the light transmittance of the transparent display panel 110.

[0129] A transparent display device according to one or more embodiments of this specification can be described as follows:

[0130] A transparent display device according to one or more embodiments of this specification may include a substrate having a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged; at least one gate line on the substrate that crosses the non-transparent region and the transparent region; and a gate bridge pattern on the substrate that is arranged in the transparent region and at least partially overlaps the at least one gate line.

[0131] According to one or more embodiments of this specification, a gate bridge pattern can be electrically connected to at least one gate line.

[0132] According to one or more embodiments of this specification, at least one gate line includes a first gate line and a second gate line, and the gate bridge pattern can be electrically connected to the first gate line and electrically isolated from the second gate line.

[0133] According to one or more embodiments of this specification, the first gate line may be located in a non-transparent region, and the second gate line may be located in both a non-transparent and a transparent region.

[0134] According to one or more embodiments of this specification, a first gate line can be connected to a pixel corresponding to the lower of two adjacent horizontal lines, and a second gate line can be connected to a pixel corresponding to the upper of two adjacent horizontal lines.

[0135] According to one or more embodiments of this specification, the gate bridge pattern can extend parallel to and overlap with the second gate line in the transmission region.

[0136] According to one or more embodiments of this specification, the gate bridge pattern can be separated from the second gate line by at least one insulating layer.

[0137] According to one or more embodiments of this specification, a gate bridge pattern can be connected to a first gate line through a contact hole penetrating at least one insulating layer.

[0138] According to one or more embodiments of this specification, the substrate further includes at least one power line extending in a first direction, the at least one gate line including a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction.

[0139] According to one or more embodiments of this specification, at least one power line and a first gate line may be located in an opaque region, and a second gate line may be located in both an opaque region and a transparent region.

[0140] According to one or more embodiments of this specification, the first gate line can be superimposed on at least one power line in a non-transparent region.

[0141] According to one or more embodiments of this specification, the first gate line can be extended parallel to and adjacent to at least one power line in a non-transparent region.

[0142] According to one or more embodiments of this specification, the first gate line may include a separation of portions separated from each other in a non-transparent region, and a connecting pattern that electrically connects the separation portions.

[0143] According to one or more embodiments of this specification, other metallic patterns within the opaque region can be placed in the division of the first gate line.

[0144] According to one or more embodiments of this specification, a gate bridge pattern can be electrically connected to a first gate line and electrically separated from a second gate line, extending in parallel.

[0145] According to one or more embodiments of this specification, the gate bridge pattern is arranged on a substrate, and at least one gate line can be arranged on a first insulating layer covering the gate bridge pattern.

[0146] According to one or more embodiments of this specification, at least one gate line includes a separation portion that is spaced apart from each other and a connecting pattern that electrically connects the separation portions, the connecting pattern being located on a second insulating layer covering at least one gate line, and the separation portions being electrically connected through contact holes penetrating the second insulating layer.

[0147] According to one or more embodiments of this specification, the substrate further includes at least one power line extending in a first direction, the at least one power line being located on a third insulating layer covering at least one gate line and a coupling pattern.

[0148] According to one or more embodiments of this specification, the transparent region on the substrate may further include at least one undercut line that is located in a transparent region and extends in a first direction.

[0149] According to one or more embodiments of this specification, at least one undercut line may include a first undercut line and a second undercut line, wherein the first undercut line is positioned adjacent to a pixel on one side of the transparent region and the second undercut line is positioned adjacent to a pixel on the other side of the transparent region.

[0150] According to one or more embodiments of this specification, at least one undercut line can be configured to interrupt the organic light-emitting layer constituting the light-emitting element.

[0151] According to one or more embodiments of this specification, at least one undercut line may consist of a portion of at least one protective layer located on at least one gate line.

[0152] According to one or more embodiments of this specification, at least one undercut line can be formed by removing a portion of at least one protective layer.

[0153] According to one or more embodiments of this specification, a block pattern may further be provided, which is located at the intersection of at least one gate line and at least one undercut line.

[0154] According to one or more embodiments of this specification, the block pattern may be between at least one undercut line and at least one gate line.

[0155] A transparent display device according to one or more embodiments of this specification may include a substrate including an opaque region and a transparent region including a light-emitting region on which light-emitting elements are arranged; at least one undercut line arranged in the transparent region on the substrate and extending in a first direction; at least one gate line traversing the opaque region and the transparent region on the substrate and including a divided portion separated by a certain distance at the point where it intersects with at least one undercut line in the transparent region; and a connecting bridge pattern arranged in the portion where at least one gate line and at least one undercut line are located, electrically connecting the divided portion of at least one gate line.

[0156] According to one or more embodiments of this specification, the linking bridge pattern is arranged on a substrate, and at least one gate line can be arranged on an insulating layer covering the linking bridge pattern.

[0157] According to one or more embodiments of this specification, one end and the other end of at least one gate line separated by a divider can be electrically connected to a connecting bridge pattern through a contact hole penetrating the insulating layer.

[0158] According to one or more embodiments of this specification, at least one undercut line can be configured to interrupt the organic light-emitting layer constituting the light-emitting element.

[0159] According to one or more embodiments of this specification, at least one undercut line may consist of a portion of at least one protective layer located on at least one gate line.

[0160] According to one or more embodiments of this specification, at least one undercut line can be formed by removing a portion of at least one protective layer.

[0161] Although embodiments of this specification have been described in more detail above with reference to the attached figures, this specification is not necessarily limited to such embodiments and can be implemented in various ways without departing from the technical concept of this specification. Therefore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Accordingly, the embodiments described above should be understood in all respects to be illustrative and not limiting. The scope of protection of this specification should be interpreted by the claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of rights of this specification. [Explanation of symbols]

[0162] 110: Display Panel 205: Gate drive unit DA:Display area NDA: Hidden area SL1: First signal line SL2: Second signal line

Claims

1. A substrate including a non-transparent region and a transparent region, which include a light-emitting region in which light-emitting elements are arranged. On the substrate, at least one gate line crossing the non-transparent region and the transparent region, and The substrate includes a gate bridge pattern arranged in the transparent region and overlapping at least one gate line with at least a portion thereof, The at least one gate line includes a first gate line and a second gate line, The gate bridge pattern is electrically connected to the first gate line and electrically isolated from the second gate line. The first gate line is located in the non-transparent region, The second gate line is arranged in the non-transparent region and the transparent region, The gate bridge pattern extends parallel to the second gate line in the transparent region and overlaps with the second gate line. Transparent display device.

2. The transparent display device according to claim 1, wherein the gate bridge pattern is electrically connected to at least one gate line.

3. The transparent display device according to claim 1, wherein the gate bridge pattern is separated from the second gate line by at least one insulating layer.

4. The transparent display device according to claim 1, wherein the gate bridge pattern is connected to the first gate line through a contact hole penetrating at least one insulating layer.

5. The substrate further includes at least one power line extending in a first direction, The transparent display device according to claim 1, wherein the at least one gate line includes a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction.

6. The at least one power line and the first gate line are arranged in the non-transparent region. The transparent display device according to claim 5, wherein the second gate line is arranged in the non-transparent region and the transparent region.

7. A substrate including a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged. On the substrate, at least one gate line crosses the non-transparent region and the transparent region. A gate bridge pattern arranged in the transparent region on the substrate and overlapping at least one gate line in part, and The substrate includes at least one power line extending in a first direction, The at least one gate line includes a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction. The at least one power line and the first gate line are arranged in the non-transparent region. The second gate line is arranged in the non-transparent region and the transparent region, A transparent display device in which the first gate line is superimposed on the at least one power line in the non-transparent region.

8. The transparent display device according to claim 6, wherein the first gate line extends parallel to and adjacent to the at least one power line in the non-transparent region.

9. A substrate including a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged. On the substrate, at least one gate line crossing the non-transparent region and the transparent region, and The substrate includes a gate bridge pattern arranged in the transparent region and overlapping at least one gate line with at least a portion thereof, The at least one gate line includes a first gate line and a second gate line, The gate bridge pattern is electrically connected to the first gate line and electrically isolated from the second gate line. The first gate line is located in the non-transparent region, The second gate line is arranged in the non-transparent region and the transparent region, The first gate line is The separated portions in the aforementioned non-transparent region, A transparent display device including a connecting pattern that electrically connects the aforementioned divided portions.

10. A substrate including a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged. On the substrate, at least one gate line crosses the non-transparent region and the transparent region. A gate bridge pattern arranged in the transparent region on the substrate and overlapping at least one gate line in part, and The substrate includes at least one power line extending in a first direction, The at least one gate line includes a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction. The at least one power line and the first gate line are arranged in the non-transparent region. The second gate line is arranged in the non-transparent region and the transparent region, The first gate line is The separated portions in the aforementioned non-transparent region, A transparent display device including a connecting pattern that electrically connects the aforementioned divided portions.

11. The transparent display device according to claim 9 or 10, wherein a metal pattern different from that of the first gate line in the non-transparent region is arranged in the divided portion of the first gate line.

12. The transparent display device according to claim 6, wherein the gate bridge pattern is electrically connected to the first gate line and extends parallel to the second gate line, electrically separated from it.

13. A substrate including a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged. On the substrate, at least one gate line crossing the non-transparent region and the transparent region, and The substrate includes a gate bridge pattern arranged in the transparent region and overlapping at least one gate line with at least a portion thereof, The gate bridge pattern is arranged on the substrate, A transparent display device wherein the at least one gate line is located on a first insulating layer covering the gate bridge pattern.

14. The at least one gate line includes a separation portion that is separated from each other and a connecting pattern that electrically connects the separation portion, The transparent display device according to claim 13, wherein the connecting pattern is arranged on a second insulating layer covering at least one gate line, and electrically connects the divided portion through contact holes penetrating the second insulating layer.

15. The substrate further includes at least one power line extending in a first direction, The transparent display device according to claim 14, wherein the at least one power line is arranged on a third insulating layer covering the at least one gate line and the connecting pattern.

16. A substrate including a non-transparent region and a transparent region, which include a light-emitting region on which light-emitting elements are arranged. On the substrate, at least one gate line crosses the non-transparent region and the transparent region. A gate bridge pattern arranged in the transparent region on the substrate and overlapping at least one gate line in part, and Displaced in the transparent region on the substrate and including at least one undercut line extending in a first direction, A transparent display device in which the at least one undercut line is configured to interrupt the organic light-emitting layer constituting the light-emitting element.

17. The at least one undercut line includes a first undercut line and a second undercut line, The transparent display device according to claim 16, wherein the first undercut line is arranged adjacent to a pixel on one side of the transparent region, and the second undercut line is arranged adjacent to a pixel on the other side of the transparent region.

18. The transparent display device according to claim 16, wherein the at least one undercut line is composed of a portion of at least one protective layer located on the at least one gate line.

19. The transparent display device according to claim 18, wherein the at least one undercut line is located within an opening that penetrates the at least one protective layer.

20. The transparent display device according to claim 16, further comprising a block pattern positioned at the intersection of the at least one gate line and the at least one undercut line, which prevents damage to the at least one gate line.

21. The transparent display device according to claim 20, wherein the block pattern is located between the at least one undercut line and the at least one gate line when viewed in the height direction of the transparent display device.

22. A substrate including a non-transparent region and a transparent region, which include a light-emitting region in which light-emitting elements are arranged. On the substrate, at least one undercut line is arranged in the transparent region and extends in the first direction, On the substrate, at least one gate line that crosses the opaque region and the transparent region, and intersects with the at least one undercut line in the transparent region, including a segment that is isolated for a certain period of time, and It includes a connecting bridge pattern that is arranged in the portion where the at least one gate line and the at least one undercut line are located, and electrically connects the divided portion of the at least one gate line, A transparent display device in which the at least one undercut line is configured to interrupt the organic light-emitting layer constituting the light-emitting element.

23. The connecting bridge pattern is arranged on the substrate, The transparent display device according to claim 22, wherein the at least one gate line is arranged on an insulating layer covering the connecting bridge pattern.

24. The transparent display device according to claim 23, wherein one end and the other end of the at least one gate line separated by the dividing portion are electrically connected to the connecting bridge pattern through a contact hole penetrating the insulating layer.

25. The transparent display device according to claim 22, wherein the at least one undercut line is composed of a portion of at least one protective layer located on the at least one gate line.

26. The transparent display device according to claim 25, wherein the at least one undercut line is located within an opening that penetrates the at least one protective layer.

Images