Power supply equipment

Abstract

To suppress a harmonic component in output current of an inverter.SOLUTION: A power supply device according to an embodiment, comprises: a converter configured to convert AC power output from an AC power supply into DC power; a counter configured to receive an interrupt signal for each half cycle of a carrier wave and output a first trigger every time a predetermined odd number of interrupt signals greater than one are received; and a control circuit configured to acquire system voltage and phase current of the AC power supply and a value of DC unit voltage which is a voltage value of the DC power based on a first trigger, generate a voltage command to the converter based on the values of the system voltage, the phase current, and the DC unit voltage, and output the voltage command to the converter.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Embodiments of the present invention relate to a power supply device.

Background Art

[0002] When driving a motor with a converter for the purpose of rectifying an AC power supply to DC and an inverter for inverting the converted DC, if the converter uses diode rectification, harmonics occur on the connected AC power supply side. There was a possibility of noise-related malfunctions in electrical equipment and facilities connected to the same AC power supply.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In order to suppress harmonic components in the input current to the converter, for example, it has been proposed to use a harmonic suppression unit. It is possible to adopt a pulse width modulation (PWM) converter as the harmonic control unit.

[0005] To suppress harmonic components in the input current to the converter, it is desirable to perform interrupt control to suppress harmonic components at half-periods of the carrier wave used for converter control. However, due to limitations imposed by the processing power of the processor installed in the power converter, it was sometimes not possible to control the suppression of harmonic components at half-periods of the carrier wave. For example, in the case of a PWM converter that outputs a sine wave using PWM switching, the control of the carrier frequency is limited according to the processing power of the processor, and harmonic currents increase in addition to the fundamental frequency. As a result, distortion occurs in the output current of the converter, and when connecting an LC filter to suppress harmonic currents, it is generally necessary to design the cutoff frequency considering the carrier frequency component without reducing the gain at the fundamental frequency. When the carrier frequency decreases, the cutoff frequency needs to be lowered, and in that case, the inductance needs to be increased to limit the leakage current of the capacitor, which can increase power loss in the filter and potentially reduce the overall power conversion efficiency of the system.

[0006] This embodiment of the present invention has been made in view of the above circumstances, and its purpose is to provide a power conversion device that suppresses harmonic components while taking into consideration the processing capability of the processor. [Means for solving the problem]

[0007] The power supply device according to the embodiment includes a converter that converts AC power output from an AC power source into DC power; a counter that receives an interrupt signal every half-period of the carrier wave and outputs a first trigger every time the interrupt signal is received a predetermined odd number of times greater than 1; and a control circuit that, based on the first trigger, acquires the system voltage and phase current of the AC power source and the DC voltage which is the voltage value of the DC power, generates a voltage command to the converter based on the values ​​of the system voltage, the phase current, and the DC voltage, and outputs it to the converter. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a conceptual diagram showing an example of the configuration of a power system panel mounted on a power conversion device according to one embodiment. [Figure 2] Figure 2 is a schematic diagram illustrating an example of the relationship between the carrier wave, interrupt instruction signal, and voltage command used in PWM control in a power converter according to one embodiment. [Figure 3] Figure 3 is a schematic block diagram showing one example of the configuration of the control circuit of a power converter according to one embodiment. [Figure 4] Figure 4 is a schematic diagram showing one example configuration of a power conversion device according to one embodiment. [Figure 5] Figure 5 is a flowchart illustrating an example of the operation of a power converter according to one embodiment. [Modes for carrying out the invention]

[0009] The power supply device will be described in detail below with reference to the drawings. In the following embodiments, parts with the same number will be assumed to perform the same operation, and therefore repeated explanations will be omitted. For example, when there are multiple identical or similar elements, a common reference numeral may be used to describe each element without distinction, or a sub-number may be used in addition to the common reference numeral to describe each element separately.

[0010] Figure 1 is a conceptual diagram showing an example of the configuration of a power system panel equipped with a power conversion device according to one embodiment. The power system panel 100 includes a switch 2, an LCL filter 3, a converter 4, an inverter 5, and a counter 6. The power system panel 100 is connected between the three-phase AC power supply 1 and the motor 7.

[0011] The three-phase AC power supply 1 supplies three-phase AC current to the converter 4 either directly or through the LCL filter 3.

[0012] Switch 2 switches the electrical connection state between the three-phase AC power supply 1 and the converter 4 in the path that supplies AC power from the three-phase AC power supply 1 to the converter 4. For example, switch 2 can be operated so that it turns on when the motor 7 is driven and turns off when the motor 7 is stopped.

[0013] The LCL filter 3 suppresses the harmonic components of the AC current (or AC voltage) output from the three-phase AC power supply 1. The LCL filter 3 outputs the three-phase AC current, with its harmonic components suppressed, to the converter 4.

[0014] The converter 4 comprises a main circuit 41 and a control circuit 42.

[0015] The main circuit 41 receives the alternating current output from the three-phase AC power supply 1 via the LCL filter 3. The main circuit 41 comprises a plurality of switching elements (not shown). The switching elements of the main circuit 41 operate based on gate commands received from the control circuit 42, converting the supplied alternating current into direct current. The main circuit 41 outputs the generated direct current to the inverter 5.

[0016] The control circuit 42 is an arithmetic circuit comprising at least one processor and memory in which a program executed by the processor is stored. The control circuit 42 can control the main circuit 41 by software, or by a combination of software and hardware.

[0017] The control circuit 42 acquires the values ​​of each phase current input to the main circuit 41, the system voltage from the three-phase AC power supply 1, and the DC voltage output by the main circuit 41, in response to a trigger from the counter 6. The control circuit 42 also generates a voltage command based on the acquired values ​​of the phase current, system voltage, and DC voltage, and outputs a gate command based on the generated voltage command to the main circuit 41.

[0018] The inverter 5 generates an AC voltage from the DC voltage supplied from the converter 4. The inverter 5 outputs the generated AC voltage to the motor 7 which is the load. Note that the inverter 5 may be any inverter capable of generating an AC voltage from a DC voltage. For example, when the load operates as a generator, the inverter 5 is a bidirectional three-phase AC inverter capable of converting the AC voltage supplied from the load into a DC voltage current and supplying it to the converter 4.

[0019] The counter 6 receives an interrupt instruction signal from the carrier generation unit. An interrupt instruction signal is input to the counter 6 every half cycle of the carrier wave generated by a carrier generation unit (not shown). The counter 6 counts the number of times the interrupt instruction signal is input, and outputs a trigger to the control circuit 42 every time a predetermined odd number of times greater than 1, for example, 2n + 1 (n is a positive integer), the interrupt instruction signal is received. For example, when n = 1, after the counter 6 outputs the first trigger, when it receives three interrupt instruction signals, it outputs the second trigger, and after outputting the second trigger, when it receives three interrupt instruction signals, it outputs the third trigger. The counter 6 may reset the counted value to zero after outputting the trigger. The counter 6 may be included in the carrier generation unit.

[0020] FIG. 2 is a diagram schematically showing an example of the relationship between a carrier wave, an interrupt instruction signal, and a voltage command used for PWM control in a power conversion device of an embodiment. In this example, the carrier wave is, for example, a triangular wave with a half cycle of 50 μs, and the carrier frequency is 10 kHz. Here, the carrier frequency of the carrier wave may be a fixed frequency. A carrier generation unit (not shown) outputs an interrupt instruction signal to the counter 6 every half cycle of the carrier wave, that is, every peak (hill and valley) of the triangular wave. The counter 6 counts the number of times the interrupt instruction signal is received. The counter 6 outputs a trigger to the control circuit 42 every time the count value becomes a predetermined odd number.

[0021] In the example of FIG. 2, the control circuit 42 generates a voltage command by a power conversion procedure described later during 1.5 periods (150 μs) of this carrier wave. Then, the control circuit 42 receives the next trigger, that is, outputs the voltage command to the converter 412 at the timing when the counter 6 issues a trigger. Thus, the control circuit 42 generates a voltage command in response to a trigger and outputs the voltage command to the converter 412 at the timing of receiving the next trigger.

[0022] FIG. 3 is a block diagram schematically showing a configuration example of a control circuit of a power conversion device according to an embodiment. The main circuit 41 includes a detection unit 411, a converter 412, a switching element 413, and a smoothing capacitor 414.

[0023] The detection unit 411 is a current detector that detects the value of the phase current (or a value equivalent to current) input from the AC power supply 1 to the converter 412 via the LCL filter 3. The values detected by the detection unit 411 (phase current values of at least two phases) are supplied to the control circuit 42.

[0024] The converter 412 converts the three-phase alternating current output from the LCL filter 3 into a direct current and outputs it to the inverter 5.

[0025] The switching element 413 may be used, for example, when initially charging the smoothing capacitor 414. The switching element 413 is connected in parallel with a resistor, and is turned off when initially charging the smoothing capacitor 414, and supplies a charging current to the smoothing capacitor 414 from the converter 412 via the resistor.

[0026] The smoothing capacitor 414 is connected between the positive DC terminal and the negative DC terminal of the converter 412. Note that the value of the voltage of the smoothing capacitor 414 (DC bus voltage Vdc) is detected by a voltage detector and supplied to a DC voltage control unit (AVR: Automatic Voltage Regulator) 4206 and a DC voltage compensation unit 4214 described later.

[0027] The control circuit 42 includes a first UVW / dq conversion unit 4201, a sum of squares root unit 4202, a UV / OV detection unit 4203, a PLL (Phase Locked Loop) control unit 4204, a first subtractor 4205, a DC voltage control unit 4206, a limiter 4207, a second UVW / dq conversion unit 4208, a second subtractor 4209, a third subtractor 4210, a q-axis current control unit (ACR: Auto Current Regulator) 4211, a d-axis current control unit (ACR) 4212, a dq / UVW conversion unit 4213, a DC voltage compensation unit 4214, an overmodulation processing unit 4215, a dead time compensation unit 4216, and a PWM generation unit 4217.

[0028] The first UVW / dq conversion unit 4201 acquires the values ​​of the system voltages Vgrid_u, Vgrid_v, and Vgrid_w output by the three-phase AC power supply 1 when a trigger is input. The first UVW / dq conversion unit 4201 only needs to acquire the values ​​of at least two phases of the system voltages Vgrid_u, Vgrid_v, and Vgrid_w. Based on the power supply phase θ described later, the first UVW / dq conversion unit 4201 performs a vector coordinate transformation on the values ​​of the system voltages Vgrid_u, Vgrid_v, and Vgrid_w and calculates the d-axis system voltage Vgrid_d value and the q-axis system voltage Vgrid_q value, which are in the dq rotation coordinate system. The first UVW / dq conversion unit 4201 outputs the calculated d-axis system voltage Vgrid_d and q-axis system voltage Vgrid_q values ​​to the sum of squares root unit 4202. Furthermore, the first UVW / dq conversion unit 4201 outputs the value of the q-axis system voltage Vgrid_q to the PLL control unit 4204.

[0029] The square root of the sum of squares unit 4202 squares the values ​​of the d-axis system voltage Vgrid_d and the q-axis system voltage Vgrid_q, adds them up, and calculates the square root of the sum of squares. It then outputs the calculation result to the UV / OV detection unit 4203.

[0030] The UV / OV detection unit 4203 detects overvoltage (OV) and undervoltage (UV) of the system voltage based on the root sum of squares calculated by the root sum of squares unit 4202. The UV / OV detection unit 4203 then outputs the detection result as GB (Gate Block). If the system voltage is UV (undervoltage) or 0V (overvoltage), the output value GB of the UV / OV detection unit 4203 activates a protection circuit (not shown) to interrupt the gate command supplied to the main circuit of the converter 412. When the gate command is interrupted, the output of the converter 412 is stopped.

[0031] The PLL control unit 4204 operates as an identification unit. For example, the PLL control unit 4204 identifies the power supply phase θ by performing PLL control on the q-axis system voltage Vgrid_q. Using the power supply phase θ identified by the PLL control unit 4204, the first UVW / dq conversion unit 4201, the second UVW / dq conversion unit 4208, and the dq / UVW conversion unit 4213, described later, perform vector conversion, enabling the control circuit 42 to perform control that follows power supply frequency fluctuations.

[0032] The first subtractor 4205 outputs the difference obtained by subtracting the value of the DC section voltage Vdc from the DC voltage command value Vdcref. The DC voltage command value Vdcref may be a value input from the higher-level control device of the voltage converter, a value preset within the voltage converter, or a value generated within the voltage converter according to the drive state of the load or the power supplied from the grid power supply.

[0033] When the DC voltage control unit 4206 receives a trigger from the counter 6, it obtains the difference between the DC voltage Vdc and the set DC voltage Vdcref from the first subtractor 4205. The DC voltage control unit 4206 generates the d-axis current command value Idref so that the DC voltage Vdc follows the set DC voltage Vdcref (so that the obtained difference becomes zero).

[0034] The limiter 4207 limits and outputs the upper and lower limits of the d-axis current command value Idref generated by the DC voltage control unit 4206. When the d-axis current command value Idref exceeds a predetermined upper limit, the limiter 4207 sets the d-axis current command value Idref to the upper limit. When the d-axis current command value Idref is less than a predetermined lower limit, the limiter 4207 sets the d-axis current command value Idref to the lower limit. The limiter 4207 outputs the d-axis current command value Idref to the third subtractor 4210.

[0035] The second UVW / dq conversion unit 4208, upon receiving a trigger signal, acquires the phase currents Iu, Iv, and Iw input to the converter 412 from the detection unit 411, and uses the power supply phase θ to perform a vector coordinate transformation of the phase currents Iu, Iv, and Iw in the three-phase fixed coordinate system into the d-axis current value Id and q-axis current value Iq in the dq rotating coordinate system. The second UVW / dq conversion unit 4208 outputs the d-axis current value Id to the second subtractor 4209 and the q-axis current value Iq to the third subtractor 4210.

[0036] The q-axis current control unit 4211 obtains the difference between the q-axis current command value Iqref (zero in the example in Figure 3) and the q-axis current value Iq from the second subtractor 4209. The reason for setting the q-axis current command value Iqref to zero is to achieve power factor = 1 control, i.e., to reduce reactive current to zero. The q-axis current control unit (ACR) 4211 executes q-axis current control so that the difference between the received d-axis current command value Iqref and the q-axis current value Iq becomes zero, and generates the q-axis voltage command value Vq. The q-axis current control unit 4211 outputs the q-axis voltage command value Vq to the dq / UVW conversion unit 4213.

[0037] The d-axis current control unit 4212 obtains the difference between the d-axis current command value Idref and the d-axis current value Id from the third subtractor 4210. The d-axis current control unit (ACR) 4212 performs d-axis current control based on the received difference between the d-axis current command value Idref and the d-axis current value Id, and generates a d-axis voltage command value Vd. The d-axis current control unit 4212 outputs the d-axis voltage command value Vd to the dq / UVW conversion unit 4213.

[0038] Here, the control circuit 42 can control the power supply power factor to be approximately 1 by setting the q-axis current command value Iqref to zero and the d-axis current command value Idref to the output value of the DC voltage control unit 4206.

[0039] The dq / UVW conversion unit 4213 uses the power supply phase θ to perform vector coordinate transformations on the d-axis voltage command value Vd and the q-axis voltage command value Vq of the dq rotating coordinate system to the three-phase voltage command values ​​Vu, Vv, and Vw of the UVW fixed coordinate system. The dq / UVW conversion unit 4213 outputs the transformed three-phase voltage command values ​​Vu, Vv, and Vw to the DC voltage compensation unit 4214.

[0040] The DC voltage compensation unit 4214 acquires the value of the DC voltage Vdc when a trigger is input. Based on the acquired value of the DC voltage Vdc, the DC voltage compensation unit 4214 compensates the three-phase voltage command values ​​Vu, Vv, and Vw, and outputs the compensated three-phase voltage command values ​​Vu, Vv, and Vw to the overmodulation processing unit 4215.

[0041] The overmodulation processing unit 4215 performs overmodulation processing on the three-phase voltage command values ​​Vu, Vv, and Vw compensated by the DC voltage compensation unit 4214. The overmodulation processing unit 4215 controls the modulation rate of the converter 412 to 1 or less in order to suppress harmonics. However, for example, if it is necessary to increase the output voltage, the modulation rate of the converter 412 may be increased to more than 1. In such cases, the overmodulation processing unit 4215 performs processing to compensate for distortion of the output current waveform. The overmodulation processing unit 4215 outputs the modulated and compensated three-phase voltage command values ​​Vu, Vv, and Vw to the dead time compensation unit 4216.

[0042] The dead time compensation unit 4216 performs dead time compensation processing based on the three-phase voltage command values ​​Vu, Vv, Vw after overmodulation processing and the values ​​of the phase currents Iu, Iv, Iw. The dead time compensation unit 4216 compensates for the distortion of the output waveform of the converter 412 that occurs due to the introduction of dead time. For example, the dead time compensation unit 4216 calculates the actual voltage value input to the converter 412 based on the values ​​of the phase currents Iu, Iv, Iw. Then, the dead time compensation unit 4216 calculates the difference between the calculated actual voltage value and the three-phase voltage command values ​​Vu, Vv, Vw. This difference is then used to compensate the three-phase voltage command values ​​Vu, Vv, Vw for the next cycle. The dead time compensation unit 4216 outputs the three-phase voltage command values ​​Vu, Vv, Vw after dead time compensation processing to the PWM generation unit. Note that the dead time compensation unit 4216 is not limited to the method of calculating the dead time compensation value described above, and may perform general dead time compensation. Generally, a dead time needs to be set to prevent the upper and lower elements from short-circuiting during the switching operation delay of the elements. As a result, the actual voltage will differ from the ideal voltage, so it is common practice to compare the voltage of the ideal PWM waveform before setting the dead time with the voltage of the actual voltage waveform and compensate for the difference in the next cycle.

[0043] The PWM generation unit 4217 compares the three-phase voltage command values ​​Vu, Vv, and Vw with the carrier wave and generates gate commands to control the switching elements of the converter 412 on and off. The PWM generation unit 4217 may, for example, store the generated gate commands in a buffer and output the gate commands to the converter 412 when it receives the next trigger from the counter 6, that is, 2n+1 carrier periods after receiving the trigger.

[0044] Figure 4 shows an example of a more detailed circuit diagram of converter 412. As shown in Figure 4, the converter 412 includes, for example, six switching elements (N-channel MOSFETs) M1 to M6. Each of the switching elements M1 to M6 is located on the upper and lower arms of the three-phase leg. For example, switching elements M1 and M2 are directly connected in one of the three-phase legs. An alternating current (either U-phase, V-phase, or W-phase) is supplied to node N1, which is the connection point between switching elements M1 and M2, via the LCL filter 3. The other switching elements M3 to M6 are configured similarly.

[0045] Furthermore, gate commands from the PWM generation unit 4217 are supplied to the gates of switching elements M1 to M6. Diodes are connected between the source and drain of the N-channel MOSFETs of switching elements M1 to M6.

[0046] When the power converter performs a motoring operation, that is, when the torque of the load motor is positive, energy flows from left to right in the diagram (from AC power source 1 to converter 412). When the power converter performs a regenerative operation, that is, when the speed and torque have opposite signs, energy flows from right to left in the diagram (from converter 412 to AC power source 1).

[0047] (operation) Figure 5 is a flowchart showing an example of the power conversion procedure in the power system panel 100 shown in Figure 1. The operation of this flowchart is realized when the processor of the power system panel 100, which is a power conversion device, reads and executes a program stored in its memory.

[0048] This flowchart starts, for example, when counter 6 receives an interrupt instruction signal from the carrier generation unit.

[0049] Counter 6 performs a count-up (step ST101). When an interrupt instruction signal is received, counter 6 counts up. For example, if counter 6 was counting 0, it counts up to counting 1.

[0050] Counter 6 determines whether the count is 3 (step ST102). If the count of counter 6 is 1 or 2, the process returns to step ST101. That is, counter 6 will wait until it receives another interrupt instruction signal. On the other hand, if the count is 3, the process proceeds to step ST103.

[0051] Counter 6 resets the count to 0 (step ST103). Counter 6 resets the count to 0 before receiving the next interrupt instruction signal. Then, counter 6 outputs a trigger to the first UVW / dq converter 4201, the DC voltage control unit (AVR) 4206, and the second UVW / dq converter 4208.

[0052] The control circuit 42 acquires the A / D input (step ST104). The first UVW / dq conversion unit 4201, the second UVW / dq conversion unit 4208, and the DC voltage control unit (AVR) 4206 of the control circuit 42 each acquire current or voltage. For example, upon receiving a trigger, the first UVW / dq conversion unit 4201 acquires the values ​​of the system voltages Vgrid_u, Vgrid_v, and Vgrid_w of the three-phase AC power supply 1. The second UVW / dq conversion unit 4208, upon receiving a trigger, acquires the values ​​of the phase currents Iu, Iv, and Iw from the detection unit 411. Furthermore, upon receiving a trigger, the DC voltage control unit 4206 acquires the difference between the value of the DC voltage Vdc from the smoothing capacitor 414 and the value of the set DC voltage Vdcref from the first subtractor 4205.

[0053] The first UVW / dq conversion unit 4201 performs a coordinate transformation on the system voltages Vgrid_u, Vgrid_v, and Vgrid_w (step ST105). The first UVW / dq conversion unit 4201 performs a coordinate transformation on the values ​​of the system voltages Vgrid_u, Vgrid_v, and Vgrid_w and calculates the d-axis system voltage Vgrid_d value and the q-axis system voltage Vgrid_q value of the dq rotation coordinate system. Then, the first UVW / dq conversion unit 4201 outputs the values ​​of the d-axis system voltage Vgrid_d and the q-axis system voltage Vgrid_q to the sum of squares root unit 4202 and outputs the value of the q-axis system voltage Vgrid_q to the PLL control unit 4204.

[0054] The PLL control unit 4204 identifies the power supply phase θ of the grid voltage (step ST106). The PLL control unit 4204 identifies the power supply phase θ of the three-phase AC power supply 1 by PLL control of the q-axis grid voltage Vgrid_q. The PLL control unit 4204 outputs the identified power supply phase θ to the first UVW / dq conversion unit 4201, the second UVW / dq conversion unit 4208, and the dq / UVW conversion unit 4213.

[0055] The second UVW / dq conversion unit 4208 performs a coordinate transformation on the phase currents (step ST107). The second UVW / dq conversion unit 4208 acquires the phase currents Iu, Iv, and Iw detected by the detection unit 411, and uses the power supply phase θ to perform a vector coordinate transformation on the phase currents Iu, Iv, and Iw in the three-phase fixed coordinate system into the d-axis current value Id and q-axis current value Iq in the dq rotating coordinate system. The second UVW / dq conversion unit 4208 then outputs the q-axis current value Iq to the second subtractor 4209 and the d-axis current value Id to the third subtractor 4210.

[0056] The DC voltage control unit 4206 generates a d-axis current command value Idref (step ST108). Based on the difference received from the first subtractor 4205, the DC voltage control unit 4206 generates the d-axis current command value Idref so that the value of the DC voltage Vdc matches the value of the set DC voltage Vdcref. Furthermore, the DC voltage control unit 4206 outputs the generated d-axis current command value Idref to the limiter 4207. The limiter 4207 sets the d-axis current command value Idref as an upper limit when it exceeds a predetermined upper limit and as a lower limit when it falls below a predetermined lower limit. Then, the limiter 4207 outputs the d-axis current command value Idref to the third subtractor 4210.

[0057] The q-axis current control unit 4211 and the d-axis current control unit 4212 perform current control based on the q-axis current command value and the d-axis current command value, respectively (step ST109). The q-axis current control unit 4211 receives the difference between the value of the q-axis current command (e.g., zero) and the q-axis current value Iq from the second subtractor 4209. Then, the q-axis current control unit 4211 performs current control based on the difference between the received q-axis current command value Iqref and the q-axis current value Iq, and outputs the q-axis voltage command value Vq. Furthermore, the d-axis current control unit 4212 obtains the difference between the set DC current value Idref, which is the d-axis current command, and the DC phase current value Id from the third subtractor 4210. Then, the d-axis current control unit 4212 performs current control based on the difference between the received d-axis current command value and the value of the d-axis current Id, and generates the d-axis voltage command value Vd. The d-axis current control unit 4212 then outputs the d-axis voltage command Vd to the dq / UVW conversion unit 4213.

[0058] The control circuit 42 generates a PWM waveform (step ST110). The dq / UVW conversion unit 4213 of the control circuit 42 uses the power supply phase θ received from the PLL control unit 4204 to perform vector coordinate transformation of the d-axis voltage command value Vd and the q-axis voltage command value Vq in the dq rotation axis coordinate system into three-phase voltage command values ​​Vu, Vv, and Vw in the UVW fixed coordinate system. The dq / UVW conversion unit 4213 then outputs the three-phase voltage command values ​​Vu, Vv, and Vw to the DC voltage compensation unit 4214.

[0059] The DC voltage compensation unit 4214 performs compensation based on the difference between the DC voltage value Vdc and the three-phase voltage command values ​​Vu, Vv, and Vw, and outputs the compensated three-phase voltage command values ​​Vu, Vv, and Vw to the overmodulation processing unit 4215.

[0060] The overmodulation processing unit 4215 converts the waveforms of the three-phase voltage command values ​​Vu, Vv, and Vw, which have been compensated by increasing the modulation rate, into a square wave. The overmodulation processing unit 4215 outputs the modulated and compensated three-phase voltage command values ​​Vu, Vv, and Vw to the dead time compensation unit 4216.

[0061] The dead time compensation unit 4216 performs dead time compensation processing based on the compensated three-phase voltage command values ​​Vu, Vv, Vw and the phase current values ​​Iu, Iv, Iw. The dead time compensation unit 4216 adds this dead time compensation amount to the three-phase voltage command values ​​Vu, Vv, Vw to calculate the voltage command values ​​Vu, Vv, Vw after dead time compensation. The dead time compensation unit 4216 outputs the compensated voltage command values ​​Vu, Vv, Vw to the PWM generation unit 4217. The dead time compensation unit 4216 may also compensate the voltage command values ​​Vu, Vv, Vw to shorten the dead time. Shortening the dead time has the effect of reducing the second and fourth harmonic components.

[0062] The PWM generation unit 4217 generates a voltage command (gate command) for the converter 412 based on the voltage command value supplied from the dead time compensation unit 4216 and the carrier wave. The PWM generation unit 4217 stores the generated voltage command in a buffer, for example, and outputs the voltage command to the converter 412 when it receives the next trigger.

[0063] (Effects of the embodiment) According to the embodiment described above, taking into account the processing capacity of the processor located in the power system panel 100, which is a power conversion device, the control circuit 42 acquires analog data from the main circuit and calculates a voltage command for the converter 412 every predetermined odd number of half-periods of the carrier wave. This makes it possible to control the inverter so as to suppress harmonic components included in the output current.

[0064] For example, when counter 6 outputs a trigger every two periods of the carrier wave, i.e., every odd-numbered trough of the carrier wave, and control circuit 42 generates a voltage command based on the acquired current and voltage values, it was not possible to suppress the even-order harmonic components included in the inverter's output current. Therefore, when the control interrupt period was changed to every one period of the carrier wave, i.e., counter 6 outputs a trigger every trough of the carrier wave, and control circuit 42 generates a voltage command based on the acquired current and voltage values, it was still not possible to suppress the even-order harmonic components included in the inverter's output current.

[0065] The inventors of this application have concluded that the factors causing the above-mentioned even-order harmonic components may be the control period (carrier wave period × 2), which is the interrupt period of the control circuit 42, or current detection only at the timing of the bottom (trough) of the carrier wave.

[0066] For example, when the control period is set to twice the carrier wave period, the interrupt of the control circuit 42 is executed at the bottom (trough) of the carrier wave. When a simulation was performed to shorten the dead time, the level of even-order harmonics decreased. Also, when the control period was set to twice the carrier wave period, the level of even-order harmonics decreased more with three-phase control than with two-phase control. Furthermore, even when the system voltage detection was assumed to be the ideal sinusoidal portion before the system impedance, even-order harmonics were generated. From these results, it is thought that the even-order harmonics are not caused by the system voltage detection, but rather by the dead time and the bias in the detection of the peaks / troughs of the carrier wave during current detection, in relation to the behavior of the current near the current zero crossing due to dead time compensation. One possible reason why the generation of even-order harmonics is more pronounced in two-phase control is that, compared to three-phase control, the timing of the IGBT switching is closer to the carrier peak in two-phase control. Therefore, controlling the converter 412 requires obtaining voltage and current values ​​at the timing of the carrier wave's peaks and troughs, and performing interrupt control.

[0067] Based on the above considerations, the inventors of this application performed a simulation with the control period of the converter 412 set to carrier half-cycle × 3, and were able to suppress the harmonic components contained in the output current of the inverter.

[0068] In other words, according to this embodiment, the objective is to provide a power conversion device that suppresses harmonic components while taking into account the processing power of the processor.

[0069] Furthermore, by controlling the dead time to be shortened using the dead time compensation unit 4216, it becomes possible to suppress second-order, fourth-order, and other harmonic components.

[0070] [Other embodiments] It should be noted that this invention is not limited to the embodiments described above. For example, although the embodiments show an example using a three-phase AC power supply 1, it is also possible to use a two-phase power supply, i.e., to implement this embodiment with two-phase control. In this case, the first UVW / dq conversion unit 4201 receives the two-phase system voltage, and the second UVW / dq conversion unit 4208 receives the two-phase phase current.

[0071] Furthermore, in the above embodiment, the interrupt period (control period) of the control circuit 42 is set as carrier half-period × N, so N = (2n + 1) (n = 1, 2, 3...). However, for example, the optimal n may be determined by detecting the harmonic content of the inverter's output current or the computational load.

[0072] In short, this invention is not limited to the embodiments described above, and can be modified in various ways during implementation without departing from its essence. Furthermore, each embodiment may be combined as appropriately as possible, and in that case, the combined effects can be obtained. Moreover, the embodiments described above include inventions at various stages, and various inventions can be extracted by appropriate combinations of the multiple constituent elements disclosed. [Explanation of Symbols]

[0073] 100... Power system panel 1…Three-phase AC power supply 2…Switch 3…LCL filter 4…Converter 41…Main circuit 411...Detection unit 412... Converter 413… Switching element 414…Smoothing Capacitor 42...Control circuits 4201...UVW / dq conversion unit 4202...Root of the sum of squares 4203...UV / OV detection unit 4204...PLL control unit 4205... Subtractor 4206... DC Voltage Control Unit 4207... Limiter 4208...UVW / dq conversion unit 4209... Subtractor 4210... Subtractor 4211...q-axis current control unit 4212...d-axis current control unit 4213...dq / UVW conversion unit 4214... DC voltage compensation section 4215... Overmodulation Processing Unit 4216...Dead Time Compensation Department 4217...PWM generation section 5…Inverter 6... Counter 7…motor

Claims

1. A converter that converts AC power output from an AC power source into DC power, A counter that receives an interrupt signal every half-period of the carrier wave and outputs a first trigger each time it receives the interrupt signal a predetermined odd number of times greater than 1, A control circuit that, based on the first trigger, acquires the system voltage and phase current values ​​of the AC power supply and the DC voltage value which is the voltage value of the DC power, generates a voltage command to the converter based on the system voltage, the phase current, and the DC voltage values, and outputs it to the converter, A power supply device equipped with the following features.

2. The power supply device according to claim 1, wherein the control circuit outputs the voltage command to the converter at the timing of receiving a second trigger, which is output when the interrupt signal is received a predetermined odd number of times after the first trigger has been received.

3. The power supply device according to claim 1 or 2, wherein the counter outputs a trigger every three times it receives the interrupt signal.

4. The aforementioned control circuit is An identification unit that identifies the phase of the grid power supply by PLL control of the vector coordinate-transformed voltage value, A first transformation unit that uses the phase of the aforementioned power supply system to perform a vector coordinate transformation of the value of the system voltage in a fixed coordinate system to the voltage value in a rotating coordinate system, A second transformation unit that uses the phase of the aforementioned power supply system to perform a vector coordinate transformation of the phase current value in a fixed coordinate system to the current value in a rotating coordinate system, A power supply device according to claim 1 or 2, comprising:

5. The control circuit further includes a DC voltage control unit that acquires the difference between the DC voltage value and the set DC voltage value, and generates a d-axis current command value based on the difference. The control circuit includes a d-axis current control unit that receives the difference between the d-axis current command value and the current value of the rotation coordinate system and generates a d-axis voltage command value, The power supply device according to claim 4, further comprising a q-axis current control unit that receives the difference between a q-axis current command value of zero and the current value of the rotating coordinate system, and generates a q-axis voltage command value.

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