Hardware-aided software modem

Abstract

To provide a hardware-aided software modem capable of improving processing speed when a modem is implemented by software and improving communication speed as modem performance.SOLUTION: A hardware-aided software modem includes a processor 29, a plurality of macro processing circuits 21-24 that execute a portion of modem signal processing, and a memory 20 that stores a modem software program that causes the processor to execute remaining processing excluding at least the portion from the modem signal processing. The processor is equipped in its inside with a plurality of control and arithmetic cores 25-28 that cooperate with the macro processing circuits, and each of the plurality of macro processing circuits and control and arithmetic cores performs pipeline processing so that the processing time for the modem signal processing is uniform.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a hardware-aided software modem that realizes a modem used in a mobile phone or the like by software.

Background Art

[0002] Historically, modems have evolved from the initial 300 bps for data communication in the late 1960s to digital modems for facsimile at 4800 bps in the 1970s, and in the current era of mobile phones, they have been accelerated to several hundred Mbps. In 5G communication, gigabit per second speeds are being pursued for further acceleration. As a technology for constructing a modem, since the digital modem era, with the increase in speed, many methods use dedicated LSIs, but there are also software modems configured by software. Software modems are inferior in processing speed, that is, communication speed as modem performance, compared to dedicated LSIs, but they have features such as being inexpensive and being able to install application software that further uses the modem in addition to the modem software. [[ID=1�]]

[0003] As described in Reference Document 1, some software modems devise software processing methods such as interrupt processing on the premise that they are composed of only a CPU and a memory as hardware. However, for speed increase, a CPU with a large number of CPU cores is used, or a special CPU with a structure that can use many cores such as a GPU (Graphics Processing Unit) for parallel processing is used.

[0004] On the other hand, regardless of modems, pipeline processing that can execute a plurality of instructions in parallel has been used for a long time to increase the processing speed of computers, and in the present invention, pipeline processing can be made more efficient.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] Even with a software modem, it enables high speeds, achieving communication speeds of several hundred Mbps, comparable to local 5G and 4G. [Effects of the Invention]

[0007] It can deliver communication speeds comparable to 5G and 4G, and can also be equipped with application software that utilizes the modem. It can be customized to suit a wide variety of customer needs, and a system particularly well-suited for local 5G applications can be built. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows a typical configuration of a software modem. [Figure 2] Figure 2 shows the signal processing flow of the modem according to the present invention. [Figure 3] Figure 3 shows the hardware configuration of the software modem according to the present invention. [Figure 4] Figure 4 shows how the software processing of the macro circuit according to the present invention is pipelined. [Figure 5] Figure 5 shows an example where the processing times for pipeline processing are inconsistent. [Modes for carrying out the invention]

[0009] Figure 1 shows a simplified general configuration of a software modem. Like a personal computer, it has a CPU and memory (shown as MEMORY in the figure), and the modem software is installed within MEMORY as application software for the personal computer, along with the OS (Operating System), which is the basic software that runs the personal computer. The DAC / ADC in Figure 1 has the function of converting digital data processed by the personal computer into analog data and transmitting it, that is, generating it as the output signal of the modem, and conversely, the function of converting the input signal of the modem, which is received as analog data, into digital data for processing by the personal computer.

[0010] Today, CPU performance has improved by incorporating multiple cores, such as six, but the communication speed of modems remains limited to a few Mbps, a speed typical of 3G mobile phones. On the other hand, as seen in recent 4G (LTE) communications, video streaming now requires communication speeds of several hundred Mbps from modems.

[0011] Figure 2 shows the signal processing (modem signal processing) flow in a mobile phone modem, with the left side being the transmitting side and the right side being the receiving side. On the transmitting side, user data is divided into predetermined lengths and framed. For each frame, a redundant error detection code called CRC is added by the CRC addition unit 1 to detect errors that may occur during communication, thus formatting the frame signal. In the encoding unit 2, the FEC (Forward Error Correction) function is executed as a countermeasure against transmission errors, and the data is encoded using LDPC (Low-Density Parity Check) code or turbo code.

[0012] In the scrambling section 3, the data is randomized to ensure uniform radio energy distribution, and the encoding efficiency using LDPC coding is improved (by avoiding the creation of unusual patterns such as consecutive zeros). Subsequently, in the modulation section 4, multiple bits from the output of the scrambling section are combined into one symbol, and a coordinate point in 2D coordinates for QAM (quadrature amplitude modulation) is determined for each symbol. In this invention, there are 64 coordinate points, and one symbol is 64QAM consisting of 6 bits of data. In the precoding section 5, for MIMO (Multiple Input and Multiple Output) control, spatial channels are formed orthogonally to each other for the multiple antennas used, and weighting is performed to appropriately control the transmission power allocated to each channel.

[0013] In the resource element mapping section 6, the output data from the pre-coding section is converted to a multi-carrier format and frequency-division multiplexed. In the IFFT (Inverse Fast Fourier Transform) section 7, the data sequence is converted from frequency space to time space, and in the DAC section 8, the digital data is converted to analog and transmitted as radio waves.

[0014] On the receiving end, the analog radio waves are first converted to digital in the ADC unit 17, the data sequence is converted from time-space to frequency-space in the FFT (Fast Fourier Transform) unit 16, and the resource element demapping unit 15 extracts data for the frequency components at predetermined positions from the frequency-division multiplexed signal.

[0015] In the equivalent processing unit 14, the time difference when radio waves arrive (the time difference between radio waves received directly between antennas and radio waves received after being reflected by obstacles such as mountains, multipath fading) is corrected, and FFT processing and IFFT processing are also used here. Subsequently, the demodulation unit 13, descrambling unit 12, decoding unit 11, and CRC check unit 10 perform signal processing in the reverse direction of the transmitting side.

[0016] Table 1 estimates the amount of computation for processing elements as software. To improve the speed (communication speed) as a software modem, it is important to circuitize (hardwareize) elements with a large amount of computation and integrate the circuit into an LSI. Therefore, it is effective to group such computations, namely arithmetic operations such as addition, multiplication, and division, logical operations such as AND and OR, shift operations, bit operations, etc., and form a macro processing circuit together with a basic circuit and a sequence circuit that realizes a specific algorithm, and then integrate it into an LSI. (Such an LSI is called a custom LSI by those skilled in the art.) The basic circuits described above include, in addition to logical operations such as AND and OR, shift operations, bit operations, etc., a temporary register for temporarily storing data during computation. The sequence circuit is a sequencer that executes an algorithm for efficiently performing computations and has an instruction function (computation program) for computations.

[0017]

Table 1

[0018] From Table 1, as candidates for macro processing circuitization (LSI integration), it is preferable to first select at least one of the encoding process and the FFT / IFFT process, which have a relatively large amount of computation. Processes with a medium amount of computation, such as bit processing, scrambling processing, and modulation / demodulation processing, may be collectively integrated into an LSI together with processes with a small amount of computation (for example, grouping bit processing and CRC processing, etc.). Processes with a small amount of computation may be processed by software without being integrated into an LSI. [[ID=​Figure 3 shows a configuration example of hardware (e.g., a hardware-added software modem (described later) or a system-on-chip) in the present invention. In the configuration of this figure, there are a processor 29, four macro processing circuits 21, 22, 23, 24 that each execute part of the modem signal processing, and a memory 20 in which a program (modem software program) is stored to cause at least the processor 29 to execute the remaining processing other than the processing executed by the four macro processing circuits 21, 22, 23, 24 in the modem signal processing. The encoding processing circuit 21 performs the processing of the encoding unit 2 and the decoding unit 11 in FIG. 2. Also, the processing of the scrambling unit 3 and the descrambling unit 12 in FIG. 2 performed by the bit processing circuit 22 is software processing by the processor 29 because it writes horizontally and reads vertically for the data in the memory, which makes the memory access complicated and time-consuming. Therefore, the vertical and horizontal conversion is hardened to shorten the time.

[0020] Also, the addition and check processing of CRC in FIG. 2 are also performed by this bit processing circuit. The modulation / demodulation processing circuit 23 performs the processing of the modulation unit and the demodulation unit in FIG. 2. The FFT / IFFT processing circuit (in the present invention, the term "fast Fourier transform" is used as a word combining FFT and IFFT) 24 performs fast Fourier transform processing that requires high computing power. Control arithmetic cores 25, 26, 27, 28 corresponding to each of the above four macro processing circuits are built into the processor 29. The processor 29 is equivalent to the CPU in FIG. 1 and is what those skilled in the art would commonly call a microprocessor or a CPU as a common noun.

[0021] Furthermore, the analog front end 30 executes the functions of the DAC unit 8 and the ADC unit 17 in FIG. 2 and performs wireless radio wave transmission (such as modulation) and reception (such as demodulation). This analog front end 30 corresponds to the DAC / ADC in FIG. 1. The processor 29, the memory 20, and the four macro processing circuits 21, 22, 23, 24 shown in FIG. 3 are implemented on one chip as an LSI. The analog front end 30 can also be housed on one chip.

[0022] The four macro processing circuits 25, 26, 27, and 28 described above may work in cooperation with the control arithmetic cores 25, 26, 27, and 28 to perform pipeline processing as software. For example, if some of the calculations performed by each macro processing circuit are performed by the corresponding control arithmetic core, the calculation time can be shortened and the pipeline processing time can be made uniform compared to when the macro processing circuits perform the calculations individually. As shown in Figure 4, the pipeline processing is uniform and there is no idle time (or waiting time), so the processing is executed efficiently.

[0023] Furthermore, data can be stored and transferred for each processing unit in each macro processing circuit. Since the basic circuit of the macro processing circuit has a temporary register, it becomes unnecessary to store and transfer data for each operation, thus reducing the memory capacity required for storing and transferring intermediate data.

[0024] Figure 5 shows an example where the processing times for each of the pipelined processes A, B, C, and D are not equal and are inconsistent, making it difficult to take advantage of the pipelined processing feature, which allows for the parallel processing of multiple instructions, and resulting in reduced processing efficiency. In Figure 3, memory 20 implements, as programs, modem software, protocol software for 5G communication, and customized software to respond to customer requirements.

[0025] In addition to the three software programs mentioned above, memory 20 also includes program memory containing the operating system as basic software (not shown in the diagram), working memory for temporarily storing computation data, and flash memory for storing data that needs to be permanently stored.

[0026] To describe the implemented software in terms of the OSI 7-layer protocol defined by ISO (International Organization for Standardization), it consists of modem software as Layer 1 (physical layer), protocol software including MAC (Medium Access Control), RLC (Radio Link Control), and PDCP (Packet Data Convergence Protocol) as Layer 2, and RPC (Radio Resource Control) as Layer 3, and protocol software including Layer 4 which executes the Internet protocol as well. Furthermore, the customized software, at Layers 6 and 7, transmits image data and sensor data, and performs various functions required by the customer system.

[0027] In on-premises wireless network systems like local 5G, it's common for numerous sensor terminals and surveillance cameras to be connected to the network, along with a management center that collects data received from these terminals and performs data analysis and management as requested by the customer. Customized software performs the data transfer and analysis / management functions required for this purpose.

[0028] The analysis and management function includes a centralized management function for all sensor terminal information managed by the management sensor, as well as analysis and management functions for each sensor terminal, such as determining the normality or abnormality of sensor information, managing sensor information chronologically, and querying other sensor terminals for sensor sensitivity settings. This customizable software enables flexible adaptation to customer systems.

[0029] A major feature of 5G mobile phones is their ability to transmit ultra-high-definition video in a short time at communication speeds of several gigabits per second. However, in local 5G, customer demands often state that communication speeds of several hundred Mbps are sufficient, and many prioritize customization features over speed. Therefore, this invention is highly practical.

[0030] The modem of this invention implements many functions through software processing, but some functions are implemented by macro processing circuits, i.e., hardware, so it can be called a hardware-aided software modem.

[0031] In the example shown in Figure 3, four macro processing circuits (e.g., LSIs) are provided to perform some of the modem signal processing shown in Figure 2, but the number of macro processing circuits can be one or more. Also, in Figure 3, in order to equalize the processing time of the pipeline processing, a configuration is adopted in which a control arithmetic core corresponding to each macro processing circuit assists in the processing performed by that macro processing circuit, but each macro processing circuit may perform processing independently without assistance from the control arithmetic core. Furthermore, in Figure 3, the memory 20 implements modem software, protocol software and customization software, but software other than protocol software and customization software may be implemented, and the implementation of protocol software and customization software may be omitted. [Industrial applicability]

[0032] Because it can perform modem functions capable of achieving communication speeds of several hundred megabits per second using software, it can be used not only as a modem for 4G mobile phones but also in 5G mobile phone systems (especially local 5G), making its industrial applicability extremely large. [Explanation of symbols]

[0033] 1. CRC addition part 2. Encoding section 3. Scrambling section 4. Modulation section 5. Pre-coding section 6. Resource Element Mapping Section 7.IFFT section 8.DAC section 10. CRC Check Section 11. Decoding section 12. Desk Lambing Department 13. Demodulation section 14. Equivalence Processing Unit 15. Resource Element Demapping Section 16.FFT section 17.ADC section 20. Memory 21. Encoding Processing Circuit 22. Bit Processing Circuit 23. Modulation / Demodulation Processing Circuit 24. FFT / IFFT Processing Circuit 25. Control Processing Core 1 26. Control Processing Core 2 27. Control Processing Core 3 28. Control Processing Core 4 29. Processor 30. Analog Front End

Claims

[Claim 1] A hardware-aided software modem comprising a processor, a plurality of macro processing circuits that perform some of the processing of modem signal processing, and a memory storing a modem software program that causes the processor to perform at least the remaining processing of the modem signal processing excluding the aforementioned partial processing, wherein the processor is equipped with a plurality of control arithmetic cores that cooperate with the macro processing circuits, and each of the plurality of macro processing circuits and control arithmetic cores is pipelined so that the processing time for modem signal processing is uniform.

Images