System and design method for a clock synchronizer for an integrated, aggregated, and distributed unit.

Abstract

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a basic application for remote communication. More specifically, the present disclosure relates to the design of a clock synchronizer for an integrated centralized distributed unit (CCDU).

Background Art

[0002] The following description of related art is intended to provide information on the background of the field of the present disclosure. This section can include certain aspects of the technology that can be related to various features of the present disclosure. However, it should be understood that this section should only be used to improve the reader's understanding of the present disclosure and should not be used as an approval of the prior art.

[0003] Fifth-generation (5G) technology is expected to fundamentally change the role that telecommunications technology plays in general industry and society. gNodeB is a 3GPP® compliant implementation of a 5G-NR base station. As shown in Figure 1, gNodeB consists of independent network functions that implement the 3GPP® compliant NR Radio Access Network (RAN) protocol, namely the Physical Layer (PHY), Media Access Control Layer (MAC), Radio Link Control (RLC), Packet Data Convergence Protocol (PDCP), Service Data Adaptive Protocol (SDAP), Radio Resource Control (RRC), and Network Real-Time Analytics Platform (NRAP). gNB further incorporates three functional modules, CU, DU, and Radio Unit (RU), which can be deployed in multiple combinations. They can operate together or independently and can be deployed on either physical resources (e.g., small cell chipsets) or virtual resources (e.g., dedicated COTS servers or shared cloud resources). CUs provide support for higher layers of the protocol stack, such as SDAP, PDCP, and RRC, while DUs provide support for lower layers of the protocol stack, such as Radio Link Control (RLC), Media Access Control (MAC), and the physical layer. In a 5G radio access network (RAN) architecture, the DU in the baseband unit (BBU) is responsible for the real-time Layer 1 and Layer 2 scheduling functions of the 5G protocol stack layer, while the CU is responsible for the non-real-time higher Layer 2 and Layer 3 of the 5G protocol stack layer.

[0004] However, in existing architectures, the DU unit and CU unit are physically separated, requiring costly and complex methods and protocol support to split the gNB into DU and CU. If the CU and DU are integrated together, internal and external synchronization problems to the system may arise.

[0005] Therefore, in this field, it is necessary to realize the design of a clock synchronizer module that enables a compact CCDU that can overcome the shortcomings of existing prior art. [Overview of the project] [Problems that the invention aims to solve]

[0006] Some of the purposes of this disclosure that at least one embodiment of this specification satisfies are listed below.

[0007] The purpose of this disclosure is to provide a system in a single unit in order to reduce costs and increase reliability.

[0008] The purpose of this disclosure is to provide a synchronizer hardware design that synchronizes all CCDU-related components in the mounted SoC. [Means for solving the problem]

[0009] This section is provided to introduce certain objects and aspects of the invention in a simplified form, which will be further described below in the detailed description. This summary is not intended to identify any key features or scope of the claimed subject matter.

[0010] To achieve the above objectives, the present invention provides a synchronizer system in a Combined Integrated Distributed Unit (CCDU) ​​system. The system may include a single integrated board, which further comprises a housing comprising a clock synchronizer module. The clock synchronizer module may further include a boundary clock (BC) having one or more synchronization blocks, one or more high-precision timing protocol (PTP) engines, and a Global Positioning System (GPS). The GPS is a primary source of clock operation that supports holdover of a predetermined time interval. The BC, one or more PTP engines, and GPS work together to achieve synchronization to one or more components of the CCDU.

[0011] In one embodiment, one or more PTP engines can serve as secondary sources of synchronization that can be automatically activated in the absence of GPS.

[0012] In one embodiment, a GPS holdover operably coupled to the synchronizer system is activated when both the GPS and one or more PTP engines are unavailable.

[0013] In one embodiment, the clock synchronizer module can be configured to make decisions that allow prioritizing synchronization or GPS holdover in one or more PTPs beyond GPS, without requiring manual intervention.

[0014] In one embodiment, the clock synchronizer module can synchronize a system on a single board and can further synchronize one or more external components associated with the system.

[0015] In one embodiment, the clock and synchronization module may further include an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.

[0016] In one embodiment, the present invention provides a method for facilitating synchronization of a CCDU system with a synchronizer system. The method may include the steps of: generating a clock signal of a predetermined frequency using a Global Positioning System (GPS), wherein the GPS is a primary synchronizer module; locking the clock signal generated by the GPS at a predetermined frequency; and generating a second clock signal of a second predetermined frequency using a boundary clock (BC) to provide a second clock signal for synchronizing one or more components of the CCDU system.

[0017] In one embodiment, the method may include the step of reading one or more NEMA packets over a GPS communication channel within a predetermined time range based on the generated clock signal.

[0018] In one embodiment, the method may include the step of generating a predetermined high-precision time protocol (PTP) packet using a predetermined reference clock and phase information obtained from a clock signal, wherein the one or more PTP engines are secondary synchronizer modules.

[0019] In one embodiment, the method may include the step of locking a clock signal by one or more PTP engines in the event of GPS failure, wherein a secondary module acts as a slave.

[0020] In one embodiment, the method may further include the step of providing multiple clock signals by one or more PTP engines by recovering multiple clock signals from a backhaul network.

[0021] In one embodiment, the method may include the step of entering holdover mode by GPS holdover when both GPS and one or more PTP engines fail to perform.

[0022] In one embodiment, the present disclosure relates to a non-temporary computer-readable medium including a processor-executable instruction that provides a second clock signal for synchronizing one or more components of an integrated aggregated distributed unit (CCDU) ​​system, which includes processor-executable instruction that provides a second clock signal for synchronizing one or more components of an integrated aggregated distributed unit (CCDU) ​​system.

[0023] The accompanying drawings incorporated herein and constituting part of the present invention illustrate exemplary embodiments of the disclosed methods and systems, and similar reference figures refer to the same parts throughout different drawings. Components in the drawings are not necessarily to scale, but rather emphasis is placed to clearly illustrate the principles of the present invention. Some drawings may use block diagrams to show components, and the internal circuits of each component may not be shown. It will be understood by those skilled in the art that inventions of such drawings may include inventions of electrical components, electronic components, or circuits commonly used to implement such components. [Brief explanation of the drawing]

[0024] [Figure 1A] This figure illustrates an exemplary network architecture in which the proposed system of this disclosure can be implemented in or together with embodiments of this disclosure. [Figure 1B] This figure illustrates an exemplary system architecture of an integrated aggregated distributed unit (CCDU) ​​according to an embodiment of the present disclosure. [Figure 2]A diagram illustrating exemplary existing representations of the gNodeB's centralized unit and distributed unit. [Figure 3] A diagram illustrating an exemplary synchronizer system of the CCDU according to an embodiment of the present disclosure. [Figure 4] A flowchart illustrating an exemplary method of a synchronizer system according to an embodiment of the present disclosure. [Figure 5] A diagram illustrating an exemplary computer system in which or with which embodiments of the present invention can be utilized according to an embodiment of the present disclosure. **Embodiments for Carrying Out the Invention**

[0025] The above will become even more apparent from the following more detailed description of the present invention.

[0026] In the following description, for the purpose of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. However, it will be apparent that embodiments of the present disclosure can be practiced without these specific details. Some of the features described hereinafter may each be used independently of one another or in any combination with other features. An individual feature may not address all of the issues discussed above, or may only address some of the issues discussed above. Some of the issues discussed above may not be fully addressed by any of the features described herein.

[0027] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, the following description of exemplary embodiments will provide those skilled in the art with an enabling description for implementing the exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the invention as described.

[0028] To provide a complete understanding of this embodiment, specific details are given in the following description. However, it will be understood by those skilled in the art that this embodiment can be implemented without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams, so as not to obscure this embodiment with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details, so as not to obscure this embodiment.

[0029] It is also noted that individual embodiments can be described as processes, which may be represented as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as a continuous process, many of the operations can be performed in parallel or simultaneously. In addition, the order of operations can be rearranged. A process terminates when its operations are complete, but may have additional steps not shown in the diagram. A process may correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the return of the function to the called function or main function.

[0030] The terms “exemplary” and / or “exemplifying” are used herein to mean that they serve as examples, cases, or illustrations. To avoid any doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and / or “exemplifying” should not necessarily be construed as being preferable or advantageous to other aspects or designs, nor is it meant to exclude equivalent exemplary structures and techniques known to those skilled in the art. Furthermore, to the extent that terms such as “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive, in a similar manner to the term “comprising” as an open transitional term, without excluding any additions or other elements.

[0031] Any reference throughout this specification to “one embodiment” or “an example” or “an instance” means that any particular feature, structure, or characteristic described in relation to an embodiment is included in at least one embodiment of the present invention. Therefore, the phrases “in one embodiment” or “in one embodiment” in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, any particular feature, structure, or characteristic can be combined in any preferred manner within one or more embodiments.

[0032] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural form unless the context clearly indicates otherwise. It will be further understood that, as used in this specification, the terms “comprises” and / or “comprising” specify the existence of the mentioned features, integers, steps, actions, elements, and / or components, but do not exclude the existence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any combination of one or more of the related listed items.

[0033] In this disclosure, various embodiments are described using terminology used in several communication standards (e.g., the Third Generation Partnership Project (3GPP®), Extensible Radio Access Networks (xRAN), and Open Radio Access Networks (O-RAN)), but these are merely examples for illustrative purposes. Various embodiments of this disclosure can be easily modified and applied to other communication systems.

[0034] Typically, a base station is network infrastructure that provides wireless access to one or more terminals. A base station has coverage defined to be a predetermined geographical area based on the distance over which it can transmit signals. In addition to “base station,” a base station may also be called “access point (AP),” “evolutionary node B (eNodeB) (eNB),” “5G node (fifth generation node),” “next-generation node B (gNB),” “wireless point,” “transmit / receive point (TRP),” or other terms with equivalent technical meaning.

[0035] Furthermore, a protocol stack or network stack is an implementation of a computer network protocol suite or family of protocols for a telecommunication system consisting of multiple network devices. A 5G protocol stack may include Layer 1 (L1), which is the physical layer. 5G Layer 2 (L2) may include MAC, RLC, and PDCP. 5G Layer 3 (L3) is the RRC layer.

[0036] The present invention provides an efficient hardware architecture for an ORAN-compliant clock synchronizer module of integrated aggregated unit and distributed unit (CCDU) ​​for 5G foundational applications required to handle L1, L2, and L3 scheduling of a network. The CCDU design enables the functionality of CU and DU in a single unit and can operate over a wide temperature range. The single-board approach of the CCDU makes the CCDU more reliable and less expensive. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for external alarm devices. In this description, many specific details such as logic implementation, types of system components and their interrelationships could be described to give a more complete understanding of some embodiments. However, it will be understood by those skilled in the art that the present invention can be implemented without such specific details. In other instances, control structures, gate-level circuits, and / or complete software instruction sequences are not shown in detail so as not to obscure the invention. Those skilled in the art will be able to implement suitable functionality using the included description without excessive experimentation.

[0037] Referring to Figure 1A, Figure 1A illustrates an exemplary network architecture for a 5G new radio (NR) network (100) (also called a network architecture (100)) in which an embodiment of the present disclosure may implement the proposed system (110) therein or with it. As illustrated, the exemplary network architecture (100) may comprise a proposed system (110) which may be associated with a 5G base station (104) (also called a gNodeB (104)). The gNodeB (104) may include at least three functional modules, such as an aggregation unit (CU), a distributed unit (DU), and a radio unit (RU). gNodeB can be communicatively coupled to a plurality of first computing devices (102-1, 102-2, 102-3, ..., 102-N) (interchangeably referred to as user equipment (102-1, 102-2, 102-3, ..., 102-N)) and (individually referred to as user equipment (UE) (124), and collectively referred to as UE (102)) via an open radio access network radio unit (O-RU) (114).

[0038] In exemplary embodiments, the system (110) may consist of an integrated CU and DU on a single platform or PCB, which is briefly referred to as a CCDU (106) as shown in Figure 1B. The CCDU (106) can be operably coupled to a radio unit (RU) (108) via one or more network interface card (NIC) cards, such as a backhaul network interface card (NIC) (114), a fronthaul NIC (116), etc. The CCDU (106) may include a processing unit (118), an accelerator unit which may include a soft-decision forward error correction (SD-FEC) module (116), a local area network controller unit which includes a backhaul network interface card (NIC) (114), a fronthaul NIC (116), etc. The backhaul NIC (114) can be further communically coupled to a backhaul network (112).

[0039] Generally, the existing gNodeB internal structure (200) for the 5G core (206) is shown in Figure 2, and it should be very clear even to a person not skilled in the art that the existing CU (202) and DU (204) are separate units connected by the F1 interface (208).

[0040] In exemplary embodiments, as illustrated in Figure 3, the system (110) or CCDU (106) may include one or more processors coupled to memory, which may store instructions that, when executed by one or more processors, cause the system (110) to perform L1 and L2 functionalities. One or more processors (302) may be implemented as one or more microprocessors, microcomputers, microcontrollers, edge or fog microcontrollers, digital signal processors, central processing units, logic circuits, and / or any device that processes data based on operational instructions. Among other functions, one or more processors (302) may be configured to fetch and execute computer-readable instructions stored in the memory of the CCDU (106). The memory may be configured to store one or more computer-readable instructions or routines in a non-temporary computer-readable storage medium, which may be fetched and executed to create or share data packets over network services. The memory (304) may include any non-temporary storage device, including volatile memory such as RAM or non-volatile memory such as EPROM, flash memory.

[0041] In one embodiment, the system (110) may include a plurality of interfaces (306). The interfaces (306) may provide interfaces for various types of data input / output devices, such as I / O devices and storage devices. The interfaces (306) may facilitate communication of the system (110) across multiple platforms, such as FPGAs or ASICs (318) consisting of a platform controller hub (320) and system-on-chip (System-on-Chip) SoC components related to the functionality of the CCDU (106). In exemplary embodiments, the SoC may include, but is not limited to, a soft-decision forward error correction (SD-FEC) module (116). The interfaces (306) may also provide a communication path for one or more components of the CCDU (106). Examples of such components include, but is not limited to, a processing unit / engine (118) and a database (310).

[0042] In exemplary embodiments, the CCDU(106) can be designed for outdoor applications operating over a predetermined temperature range and predetermined environmental conditions, unlike COTS (Commercially Available) servers used in AC environments. For example, the predetermined temperature range may range from 0° to at least 60°C in deserts and other tropical and equatorial regions, while the predetermined environmental conditions may include dry, humid, cold, or dusty environments.

[0043] In exemplary embodiments, a CCDU on a single board may have a chip-down approach, where one or more components corresponding to the NIC card may be part of the single board, thereby increasing the mean time between failures (MTBF) and significantly reducing costs. This is because all components are integrated onto a single board, and therefore separate components (cards) may not be required, allowing for the use of a single board that not only reduces the manufacturing process but also lowers costs and improves system reliability.

[0044] In exemplary embodiments, the system (110) can be assembled on a single board (interchangeably referred to as the LAN on Motherboard (LOM)) having a predetermined number of layers. The predetermined number of layers ensures that the system is not bulky or heavy. The predetermined number of layers may be at least 14, but not limited to this example. In one example, the system (110) may include one or more network connections that connect directly to the LOM. Instead of requiring a separate network interface card for accessing a local area network, such as Ethernet, the circuitry can be mounted on a single board. An advantage of the system (110) may be additional available PCI slots that are not used by network adapters.

[0045] In exemplary embodiments, the system (110) may include, but not limited to, at least four (x4) 25G optical fibers (SFPs) as fronthaul connections to a fronthaul NIC (116) in the eCPRI protocol, and at least two (x2) 10G optical fibers (SFPs) as backhaul connections to a backhaul network (112).

[0046] In exemplary embodiments, the system (110) may be further coupled to one or more alarm devices (not shown in Figure 1B) capable of transmitting alarm signals over dry contacts, temperature rise, critical environmental conditions, and critical electrical conditions. The system (110) may, but is not limited to, operate on a standard telecommunications power supply of -48VDC, and all required protective measures for telecommunications field use may be provided.

[0047] A processing unit / engine (118) can be implemented as a combination of hardware and programming (e.g., programmable instructions) to implement one or more functionalities of the processing unit (118). In the examples described herein, such a combination of hardware and programming can be implemented in several different ways. For example, the programming for the processing unit (118) may be processor-executable instructions stored on a non-temporary machine-readable storage medium, and the hardware for the processing unit (118) may comprise processing resources (e.g., one or more processors) for executing such instructions. In this example, the machine-readable storage medium can store instructions that, when executed by the processing resources, perform the processing unit (118). According to such an example, the system (110) may include a machine-readable storage medium for storing instructions and processing resources for executing instructions, or the machine-readable storage medium may be separate but accessible to the CCDU (106) and processing resources. In other examples, the processing engine (118) can be implemented by electronic circuits.

[0048] The processing unit (118) may include one or more modules / engines selected from a base mode management controller (BMC) (312), a local area network controller (314) (substitutable herein for Ethernet controller (314)), a clock synchronizer module (316), and other modules (322). In one example, the processing unit may be a 32-core processing engine, but is not limited. The memory (204) may include, but is not limited, 256 GB of random access memory (RAM).

[0049] Clock synchronizer module: In exemplary embodiments, the clock synchronizer module (316) may include a clock synchronizer capable of supporting a boundary clock (BC) having a synchronization block such as IEEE 1588, and one or more high-precision timing protocol (PTP) engines having the Global Positioning System (GPS) as the primary source of the clock, which must support a predetermined time range holdover of at least 24 hours, but not limited to 24 hours. For example, the boundary clock implements a local PTP clock that can synchronize with a master on one port and act as a master on other ports. For the boundary clock to be a complete PTP clock implementation, both the time and frequency must be updated simultaneously with the local PTP clock on each PHY. The boundary clock may have a main reference clock of 156.25 MHz from fronthaul to backhaul. The fronthaul may have an internal 1588 engine capable of generating 1588 PTP packets on the fronthaul network with phase information from the 156.25 MHz reference clock and a 1 PPS clock.

[0050] In one embodiment, the GPS will lock and generate a predefined clock signal, such as a 1PPS clock. The GPS 1PPS is further used to generate the 1PPS signal for the CCDU's fronthaul, backhaul, and fronthaul sink PHY. In an exemplary embodiment, NEMA packets are read from the GPS by a driver interfaced at the Platform Controller Hub (PCH) (UART over USB). The synchronizer system may further provide a frequency reference clock of 156.25MHz to the fronthaul, which can generate 1588PTP packets having phase information from the 156.25MHz reference clock and the 1PPS clock.

[0051] In exemplary embodiments, one or more PTP engines may be secondary sources of synchronization and can be automatically activated in the absence of GPS. If GPS fails, one or more PTP engines switch to 1PPS and lock. The one or more PTP engines may also include 1588PTP engines that will act as PTP slaves once they discover a PTP master on the 10G / 1G backhaul network, and can further provide two 1PPS signals that can be recovered from the backhaul network, and a reference 1PPS clock to the fronthaul and sink E PHYs.

[0052] In exemplary embodiments, GPS holdover can be activated when both GPS and one or more PTPs are unavailable. In one embodiment, the clock synchronizer module can be configured to make a decision that allows prioritizing synchronization with one or more PTPs beyond GPS or GPS holdover without requiring manual intervention. In exemplary embodiments, the clock synchronizer module (316) can synchronize the system (110) on a single board and can further synchronize external components associated with the system (110) using the onboard clock and synchronization circuitry. In exemplary embodiments, the onboard clock and synchronization circuitry may include an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.

[0053] In exemplary embodiments, the clock synchronizer module (316) may further process holdover requests in accordance with telecommunication standards.

[0054] In exemplary embodiments, the communication network may include, for example, at least part of one or more networks having one or more nodes that transmit, receive, forward, generate, buffer, store, route, switch, process, or perform any combination thereof of one or more messages, packets, signals, waves, voltage or current levels, or any combination thereof. The network may include, for example, one or more wireless networks, wired networks, the Internet, intranets, public networks, private networks, packet-switched networks, circuit-switched networks, ad-hoc networks, infrastructure networks, public switched telephone networks (PSTNs), cable networks, cellular networks, satellite networks, fiber optic networks, or any combination thereof.

[0055] In one embodiment, one or more user devices (102) can communicate with the system (110) via a set of executable instructions residing on any operating system, including, but not limited to, Android®, iOS®, Kai OS®. In one embodiment, one or more user devices (102) and one or more mobile devices can include, but not limited to, one or more combinations of any electrical, electronic, electromechanical, or apparatus or devices on which any computing device is located, such as a mobile phone, smartphone, virtual reality (VR) device, augmented reality (AR) device, laptop, general-purpose computer, desktop, personal digital assistant, tablet computer, mainframe computer, or any other computing device, wherein the computing device can include, but not limited to, one or more built-in or externally coupled accessories, such as a visual assistance device such as a camera, an auditory assistance device, a microphone, a keyboard, a touchpad, a touch-enabled screen, an electronic pen, an input device for receiving user input, a receiving device for receiving any acoustic or visual signal in any range of frequencies, and a transmitting device capable of transmitting any acoustic or visual signal in any range of frequencies. It can be understood that one or more user devices (102) and one or more mobile devices are not limited to the devices described and a variety of other devices may be used. A smart computing device may be one of the preferred systems for storing data and other private / confidential information.

[0056] Figure 4 illustrates a flowchart (400) of an exemplary method of a synchronizer system according to an embodiment of the present disclosure. This method facilitates the synchronization of a combined aggregated distributed unit (CCDU) ​​system by the synchronizer system.

[0057] The method may include step 402, where the Global Positioning System (GPS) generates a clock signal of a predetermined frequency, wherein the GPS is a primary synchronizer module. For example, the GPS would lock and generate a predetermined clock signal such as a 1PPS clock. The GPS 1PPS is further used to generate the 1PPS signal for the fronthaul, backhaul, and fronthaul sink PHY of the CCDU.

[0058] The method may include step 404 of locking a clock signal generated by GPS at a predetermined frequency.

[0059] The method may further include step 406 of providing a second clock signal to synchronize one or more components of the CCDU system by having a boundary clock (BC) generate a second clock signal of a second predetermined frequency. For example, the boundary clock runs a local PTP clock that can synchronize with a master on one port and act as a master on other ports. For the boundary clock to be a complete PTP clock implementation, both the time and frequency must be updated simultaneously with the local PTP clock on each PHY. The boundary clock may have a main reference clock of 156.25 MHz from fronthaul to backhaul. The fronthaul may have an internal 1588 engine that can generate 1588 PTP packets on the fronthaul network with phase information from the 156.25 MHz reference clock and a 1 PPS clock.

[0060] In one embodiment, the method may include the step of reading one or more NEMA packets over a GPS communication channel within a predetermined time range based on the generated clock signal.

[0061] In one embodiment, the method may include the step of generating a predetermined high-precision time (PTP) protocol packet using a predetermined reference clock and phase information obtained from a clock signal, wherein one or more PTP engines are secondary synchronizer modules.

[0062] In one embodiment, the method may include the step of locking a clock signal by one or more PTP engines in the event of GPS failure, wherein a secondary module acts as a slave.

[0063] In one embodiment, the method may include the step of providing multiple clock signals by one or more PTP engines by recovering multiple clock signals from a backhaul network.

[0064] In one embodiment, the method may include the step of entering holdover mode by GPS holdover when both GPS and one or more PTP engines fail to perform.

[0065] Exemplary computer system 500 Figure 5 illustrates an exemplary computer system that utilizes embodiments of the present invention, in or in conjunction with embodiments thereof, according to embodiments of the present disclosure. As shown in Figure 5, the computer system 500 may include an external storage device 510, a bus 520, main memory 530, read-only memory 540, a large storage device 550, a communication port 560, and a processor 570. Those skilled in the art will understand that the computer system may include more than one processor and communication ports. The processor 570 may include various modules relevant to embodiments of the present invention. The communication port 560 may be an RS-232 port used for modem-based dial-up connections, a 10 / 100 Ethernet port, a Gigabit or 10 Gigabit port using copper or fiber, a serial port, a parallel port, or any other existing or future port. The communication port 560 may be selected depending on the network, such as a local area network (LAN), a wide area network (WAN), or any network to which the computer system is connected. The memory 530 may be random access memory (RAM) or any other dynamic storage device commonly known in the art. The read-only memory 540 may be any static storage device, such as a programmable read-only memory (PROM) chip for storing static information, such as boot or BIOS instructions for the processor 570, but is not limited to such devices. The large storage device 550 may be any current or future large storage solution that can be used to store information and / or instructions.

[0066] Bus 520 connects the processor 570 to other memory, storage, and communication blocks in a communicative manner. Bus 520 may be other buses such as Peripheral Component Interconnection (PCI) / PCI Extend (PCI-X) buses, Small Computer Peripheral Interface (SCSI), USB, etc., for connecting expansion cards, drives, and other subsystems, as well as a Front Side Bus (FSB) for connecting the processor 570 to a software system.

[0067] Optionally, operator and management interfaces, such as a display, keyboard, and cursor control device, may also be coupled to bus 520 to support direct operator interaction with the computer system. Other operator and management interfaces may be provided through network connections connected via communication port 560. The components described above are intended to illustrate various possibilities only. In no way should the computer systems described above limit the scope of this disclosure.

[0068] Thus, this disclosure provides a unique and efficient clock synchronizer for an integrated aggregated distributed unit (CCDU) ​​that can realize the functionality of CU and DU in a single-box solution. Unlike commercially available (COTS) servers, which are very often used in AC environments, the CCDU is designed for outdoor applications that operate over a wide temperature range and different environmental conditions. The CCDU has a chip-down approach, and all components corresponding to the NIC card are part of a single board, which increases the mean time between failures (MTBF) and significantly reduces costs.

[0069] While this specification places considerable emphasis on preferred embodiments, it will be understood that many embodiments can be made and many modifications can be made to preferred embodiments without departing from the principles of the invention. These and other modifications in preferred embodiments of the invention will be apparent to those skilled in the art from this disclosure, and it should be clearly understood that the above description should be made merely as a description of the invention and not as a limitation.

[0070] Parts of the disclosures in this patent document include materials that are subject to intellectual property rights, including but not limited to copyrights, designs, trademarks, IC layout designs, and / or trade dress protections, belonging to Jio Platforms Limited (JPL) or its affiliates (hereinafter referred to as the Owner). The Owner does not object to anyone reproducing the patent document or patent disclosure, for it will be published in the patent file or records of the Patent Office, otherwise the Owner will retain all rights whatsoever. All rights to such intellectual property are fully secured by the Owner. This patent document includes systems and methods as defined in 3GPP® Technical Specification (TS) 38.816, etc.

[0071] Benefits of this disclosure This disclosure enables a system in a single unit to reduce costs and improve reliability.

[0072] This disclosure provides a synchronizer hardware design for synchronizing all CCDU-related components in an onboard SoC. [Explanation of symbols]

[0073] 100 New 5G Wireless (NR) Network, Network Architecture 102 User equipment, UE 102-1 First computing device, user equipment 102-2 First computing device, user equipment 102-3 First computing device, user equipment 102-N First computing device, user equipment 104 gNodeB, 5G base station 106 Integrated Integrated Distributed Unit, CCDU 108 Wireless Unit (RU) 110 System 112 Backhaul Network 114 Backhaul Network Interface Card (NIC), Backhaul NIC, Open Wireless Access Network Radio Unit (O-RU) 116. Soft-Decision Forward Error Correction (SD-FEC) Module, Fronthaul NIC 118 ICX-SP processing unit, processing unit, processing engine, processing unit / engine 120 NIC backhaul 124 User Equipment (UE) 124-1 Sector 1 E-CPRI 124-2 Sector 2 E-CPRI 124-3 Sector 3 E-CPRI 200 gNodeB internal structure 202 CU 204 DU, memory 206 5G cores 208 F1 Interface 302 Processors 304 memory 306 Interface 310 Databases 312 Base Mode Management Controller (BMC), Board Management Controller (BMC) 314 Local Area Network Controller, Ethernet Controller 316 Clock Synchronizer Module 318 FPGAs, ASICs 320 Platform Controller Hub 322 Other modules 500 Computer Systems 510 External storage devices 520 Bus 530 Main Memory 540 Read-only memory 550 Large-Scale Storage Devices 560 communication ports 570 processor

Claims

1. A synchronizer system in an integrated aggregated distributed unit (CCDU) ​​system, It comprises a single integrated board, and the single integrated board is It also features a chassis equipped with a clock synchronizer module, The clock synchronizer module, A boundary clock (BC) having one or more synchronization blocks, One or more high-precision timing protocol (PTP) engines, A primary synchronizer module using Global Positioning System (GPS) signals, which is a primary source of clock operation that supports holdover of a predetermined time interval, and Furthermore, The BC, the one or more PTP engines, and the primary synchronizer module work together to achieve synchronization with one or more components of the CCDU system. A synchronizer system in which one or more PTP engines are secondary sources of synchronization, and the one or more PTP engines are automatically activated if the primary synchronizer module fails to lock and generate a clock signal.

2. The system according to claim 1, wherein the holdover mode of the clock synchronizer module is activated if both the primary synchronizer module and the one or more PTP engines fail to lock the clock signal.

3. The system according to claim 1, wherein the clock synchronizer module is configured to make a determination that allows synchronization in one or more PTP or holdover modes to take precedence over synchronization in the primary synchronizer module, without manual intervention.

4. The system according to claim 1, wherein the clock synchronizer module synchronizes the synchronizer system on a single board and further synchronizes one or more external components associated with the synchronizer system.

5. The system according to claim 1, wherein the clock and synchronization modules mounted on the clock synchronizer module further include an ultra-low noise clock generation phase-locked loop (PLL), a programmable oscillator, and a system synchronizer.

6. A method for facilitating synchronization of a Integrated Concentrated Distributed Unit (CCDU) ​​system using a synchronizer system, The steps include: generating a clock signal of a predetermined frequency using a primary synchronizer module that utilizes the Global Positioning System (GPS) signal; The steps include locking the clock signal generated by the primary synchronizer module at the predetermined frequency, A step of generating a predetermined high-precision time protocol (PTP) packet using a predetermined reference clock and phase information obtained from the clock signal, wherein the one or more PTP engines are secondary synchronizer modules; If the primary synchronizer module fails to lock and generate the clock signal, the step of locking the clock signal with one or more PTP engines, wherein the secondary synchronizer module acts as a slave. The steps include: generating a second clock signal of a second predetermined frequency using a boundary clock (BC) to provide the second clock signal for synchronizing one or more components of the CCDU system; Methods that include...

7. The method according to claim 6, comprising the step of reading one or more NMEA (National Marine Electronics Association) packets within a predetermined time range via the GPS communication channel based on the generated clock signal.

8. The method according to claim 6, further comprising the step of providing the plurality of clock signals by one or more PTP engines by recovering the plurality of clock signals from a backhaul network.

9. The method according to claim 6, further comprising the step of entering holdover mode when both the primary synchronizer module and the one or more PTP engines fail to lock the clock signal.

10. In the processor, A primary synchronizer module using the Global Positioning System (GPS) signal generates a clock signal of a predetermined frequency. The clock signal generated by the primary synchronizer module is locked at the predetermined frequency. One or more high-precision timing protocol (PTP) engines generate predefined high-precision timing protocol (PTP) packets using a predefined reference clock and phase information obtained from the clock signal, and the one or more PTP engines are secondary synchronizer modules. If the primary synchronizer module fails to lock and generate the clock signal, one or more PTP engines will lock the clock signal, and the secondary synchronizer module will act as a slave. A non-temporary computer-readable medium including a processor-executable instruction that causes a boundary clock (BC) to generate a second clock signal of a second predetermined frequency, thereby providing the second clock signal to synchronize one or more components of an integrated aggregated distributed unit (CCDU) ​​system.

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