Indication device

Abstract

To provide a display device capable of mitigating current imbalance in a configuration having power source voltage applied thereto.SOLUTION: A display device according to one embodiment disclosed herein comprises: a display area having a plurality of pixels disposed therein to display an image; a non-display area located outside the display area, the non-display area including a pad area; a power shorting bar located on one side of the display area in the non-display area; a power pad provided in the pad area; and a bottleneck portion connecting the power shorting bar to a power pad. The power shorting bar has a mesh structure consisting of a plurality of first power lines extending in a first direction connected to a plurality of second power lines extending in a second direction.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images are increasing in various forms. As a result, in recent years, various display devices such as liquid crystal display devices (LCDs), plasma display devices (PDPs), quantum dot light emitting display devices (QLEDs), and organic light emitting display devices (OLEDs) have been utilized.

[0003] A display device includes two substrates and can display an image by including a plurality of pixels between the two substrates. The pixels can be driven by receiving power supply via a power line. Since a high voltage is applied to the power line, a large amount of heat can be generated when current is biased in a predetermined region. As a result, phenomena such as damage to the power line, generation of static electricity between the power line and peripheral signal lines, and rupture can occur.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This specification aims to provide a display device capable of alleviating current bias in a configuration to which a power supply voltage is applied as a technical problem.

[0005] Another technical problem of this specification is to provide a display device that can reduce the generation of greenhouse gas that may be generated by a manufacturing process for manufacturing a display device and can constitute ESG (Environment / Social / Governance).

Means for Solving the Problems

[0006] A display device according to one embodiment of this specification includes a display area in which a plurality of pixels are arranged to display an image, a non-display area arranged around the outer edge of the display area and including a pad area, a power short bar located in the non-display area on one side of the display area, a power pad located in the pad area, and a bottleneck portion connecting the power short bar and the power pad. The power short bar has a mesh structure in which a plurality of first power lines extending in a first direction and a plurality of second power lines extending in a second direction are connected to each other. [Effects of the Invention]

[0007] This specification describes how a power short bar can be formed with a mesh structure consisting of multiple first power lines and multiple second power lines, and how the widths of the multiple first power lines and multiple second power lines can be designed to be unequal, thereby mitigating current unevenness in the end region of the bottleneck.

[0008] Furthermore, this specification reduces metal stress and prevents damage caused by metal stress compared to forming the power short bar as an electrode on a flat plate (or thin film).

[0009] Furthermore, this specification allows for a reduction in the thickness of the insulating film between the power short bar and the pixel power line, thereby reducing the overall thickness of the display panel.

[0010] Furthermore, this specification can prevent the occurrence of static electricity bursts between the power short bar and the pixel power line.

[0011] Furthermore, this specification allows for the current to be dispersed in the end region of the bottleneck by forming a streamlined or curved recess in the bottleneck's inlet portion.

[0012] Furthermore, this specification reduces the failure rate of power supply short bars, thereby saving manufacturing costs, shortening manufacturing time, and further reducing production energy. In addition, this specification can reduce the generation of greenhouse gases that may occur during the manufacturing process, thus contributing to ESG (Environment / Social / Governance) compliance. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic perspective view showing a display device according to one embodiment of this specification. [Figure 2] This is a schematic plan view showing a display panel according to one embodiment of this specification. [Figure 3] This is a plan view showing an example of a subpixel provided in a display panel according to one embodiment of this specification. [Figure 4] Figure 3 is a circuit diagram showing an example of a subpixel. [Figure 5] Figure 3 is a cross-sectional view showing an example of a configuration arranged in the opaque and transparent regions. [Figure 6] This is a schematic plan view showing a power supply shorting bar and bottleneck section according to one embodiment of this specification. [Figure 7] This is a magnified view of area A in Figure 6. [Figure 8] This is a cross-sectional view showing an example of a stacked structure of power supply short bars and pixel power lines. [Figure 9] This figure shows the current flow in a power supply short bar and bottleneck section according to one embodiment of this specification. [Figure 10] This figure shows an example of current flow when the first power line and the second power line have a certain width. [Figure 11] This figure shows an example of current flow in a first power line and a second power line according to one embodiment of this specification. [Figure 12] This figure shows an example of current flow when the bottleneck entry point has a certain width. [Figure 13]It is a diagram showing an example of the flow of current in the drawing-in part of the bottleneck part according to an embodiment of this specification.

Mode for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of this specification will be described in detail with reference to the accompanying drawings.

[0015] FIG. 1 is a perspective view schematically showing a display device according to an embodiment of this specification, and FIG. 2 is a plan view schematically showing a display panel according to an embodiment of this specification.

[0016] Hereinafter, the X-axis indicates a direction parallel to the scan line, the Y-axis indicates a direction parallel to the data line, and the Z-axis indicates the height direction of the display device 100.

[0017] The display device 100 according to an embodiment of this specification has been mainly described as being composed of an organic light emitting display device (Organic Light Emitting Display), but it can also be composed of a liquid crystal display device (Liquid Crystal Display), a plasma display device (PDP: Plasma Display Panel), a quantum dot light emitting display device (QLED: Quantum dot Light Emitting Display), or an electrophoresis display device (Electrophoresis display).

[0018] Referring to FIGS. 1 to 2, the display device 100 according to an embodiment of this specification includes a display panel 110, a source drive integrated circuit (integrated circuit, hereinafter referred to as "IC") 210, a flexible film 220, a circuit board 230, and a timing control unit 240.

[0019] The display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be a sealing substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or a sealing film. Such first substrates 111 and second substrates 112 may be made of transparent materials.

[0020] The display panel 110 can be divided into a display area (DA) where pixels are formed and an image is displayed, and a non-display area (NDA) where no image is displayed.

[0021] The display area (DA) may include a first signal line (SL1), a second signal line (SL2), and subpixels, while the non-display area (NDA) may include a pad area (PA) where pads are located, and at least one scan drive unit 205.

[0022] The first signal line (SL1) can be extended in a first direction (e.g., the Y-axis direction) and can intersect with the second signal line (SL2) in the display area (DA). The first signal line (SL1) may include pixel power lines, data lines, and common power lines. In one embodiment, the first signal line (SL1) may further include a reference line.

[0023] A pixel power line can supply a first power supply voltage to the drive transistor of each subpixel. A common power supply line can supply a second power supply voltage to the cathode electrode of the subpixel. Here, the second power supply voltage may be a common power supply supplied to all subpixels.

[0024] The reference line can supply an initialization voltage (or reference voltage) to each drive transistor of a subpixel. Each data line can supply a data voltage to a subpixel.

[0025] The second signal line (SL2) can be extended in a second direction (e.g., the X-axis direction) within the display area (DA). The second signal line (SL2) may include scan lines. Scan lines can supply scan signals to subpixels.

[0026] Subpixels are provided in the region where the first signal line (SL1) is located or in the region where the first signal line (SL1) and the second signal line (SL2) intersect, and emit predetermined light to display an image.

[0027] Multiple pads can be placed in the pad area (PA). Since the size of the first substrate 111 is larger than the size of the second substrate 112, a portion of the first substrate 111 can be exposed without being covered by the second substrate 112. The portion of the first substrate 111 that is exposed without being covered by the second substrate 112 can be equipped with pads such as power pads and data pads.

[0028] The scan driver unit 205 connects to the scan line and supplies the scan signal. Such a scan driver unit 205 can be formed in the non-display area (NDA) on one or both sides of the display area (DA) of the display panel 110 using a GIP (gate driver in panel) method. Alternatively, the scan driver unit 205 can be manufactured as a drive chip, mounted on a flexible film, and attached to the non-display area (NDA) on one or both sides of the display area (DA) of the display panel 110 using a TAB (tape automated bonding) method.

[0029] The source drive IC 210 receives digital video data and data control signals from the timing control unit 240. The source drive IC 210 converts the digital video data into analog data voltages using the data control signals and supplies them to the data lines. If the source drive IC 210 is manufactured as a drive chip, it can be mounted on the flexible film 220 using a COF (chip on film) or COP (chip on plastic) method.

[0030] The flexible film 220 can have wiring formed on it that connects the pad to the source drive IC 210 and wiring that connects the pad to the circuit board 230. The flexible film 220 is attached to the pad using an anisotropic conductive film, thereby enabling the wiring between the pad and the flexible film 220 to be connected.

[0031] The circuit board 230 can be attached to the flexible film 220. The circuit board 230 can mount multiple circuits configured as drive chips. For example, a timing control unit 240 can be mounted on the circuit board 230. The circuit board 230 may be a printed circuit board or a flexible printed circuit board.

[0032] The timing control unit 240 receives digital video data and timing signals from an external system board (not shown). Based on the timing signals, the timing control unit 240 generates a scan control signal to control the operating timing of the scan drive unit and a data control signal to control the source drive IC 210. The timing control unit 240 supplies the scan control signal to the scan drive unit 205 and the data control signal to the source drive IC 210.

[0033] Figure 3 is a plan view showing an example of a subpixel provided in a display panel according to one embodiment of this specification, Figure 4 is a circuit diagram showing an example of the subpixel in Figure 3, and Figure 5 is a cross-sectional view showing an example of a configuration arranged in the opaque and transparent regions of Figure 3.

[0034] A display panel 110 according to one embodiment of this specification may include a display area (DA) and a non-display area (NDA, Figure 2). The display area (DA) may include a first area (NTA) where a plurality of subpixels (SP1, SP2, SP3, SP4) are arranged and a second area (TA) where no plurality of subpixels (SP1, SP2, SP3, SP4) are arranged. The first area (NTA) may be an opaque area that does not transmit most of the light incident from the outside, and the second area (TA) may be a transparent area that transmits most of the light incident from the outside.

[0035] For example, a transparent region (TA) may be a region with a light transmittance greater than α%, and an opaque region (NTA) may be a region with a light transmittance less than β%, where α can be greater than β. The display panel 110 can see objects or the background placed behind it through the transparent region (TA).

[0036] The non-transparent region (NTA) 1 contains multiple subpixels (SP1, SP2, SP3, SP4), multiple circuit elements, and multiple signal lines (SL1, SL2), which prevent light incident from the outside from passing through.

[0037] Multiple signal lines may include a first signal line (SL1) and a second signal line (SL2). The first signal line (SL1) may extend in a first direction (e.g., the Y-axis direction) in the non-transparent region (NTA). The first signal line (SL1) may include a pixel power line (VDDL), a data line (DL), and a common power line (VSSL). In one embodiment, the first signal line (SL1) may further include a reference line.

[0038] The pixel power supply line (VDDL) can supply a first power supply voltage to the drive transistors of each sub-pixel (SP1, SP2, SP3, SP4). The common power supply line (VSSL) can supply a second power supply voltage to the cathode electrodes of the sub-pixels (SP1, SP2, SP3, SP4). Here, the second power supply voltage can be a common power supply supplied to all sub-pixels (SP1, SP2, SP3, SP4). The common power supply line (VSSL) can be positioned separated from the pixel power supply line by a transparent region (TA).

[0039] The reference line can supply an initialization voltage (or reference voltage) to the drive transistor of each sub-pixel (SP1, SP2, SP3, SP4). Each data line (DL) can supply a data voltage to the sub-pixel (SP1, SP2, SP3, SP4).

[0040] The second signal line (SL2) may extend in a second direction (e.g., the X-axis direction) in the non-transparent region (NTA). The second signal line (SL2) may include a scan line (SCANL). The scan line (SCANL) can supply scan signals to subpixels (SP1, SP2, SP3, SP4).

[0041] The non-transparent area (NTA) is equipped with subpixels (SP1, SP2, SP3, SP4) that emit predetermined light to display an image.

[0042] Each subpixel (SP1, SP2, SP3, SP4) may be one of the following: a first subpixel (SP1) that emits red light, a second subpixel (SP2) that emits green light, a third subpixel (SP3) that emits blue light, and a fourth subpixel (SP4) that emits white light. A unit pixel (P) may contain at least two subpixels (SP1, SP2, SP3, SP4). For example, a unit pixel (P) may contain a first subpixel (SP1), a second subpixel (SP2), a third subpixel (SP3), and a fourth subpixel (SP4). Another example is that one unit pixel (P) may contain a first subpixel (SP1) and a second subpixel (SP2), while another unit pixel (P) may contain a second subpixel (SP2) and a third subpixel (SP3). The arrangement order of each subpixel (SP1, SP2, SP3, SP4) can be varied in many ways.

[0043] Each of the first subpixel (SP1), second subpixel (SP2), third subpixel (SP3), and fourth subpixel (SP4) may include circuit elements and light-emitting elements. Referring to Figure 4, each subpixel (SP1, SP2, SP3, SP4) may have a 2T (Transistor) 1C (Capacitor) structure including two transistors (DT, ST) and one capacitor (Cst), but is not necessarily limited to this. Each subpixel (SP1, SP2, SP3, SP4) may further include a compensation circuit (CC), in which case it may have a variety of structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0044] Each of the transistors (DT, ST) in each subpixel (SP1, SP2, SP3, SP4) includes a gate electrode, a source electrode, and a drain electrode. The source and drain electrodes are not fixed and can be changed by the direction of the voltage and current applied to the gate electrode; therefore, one of the source and drain electrodes can be represented as the first electrode and the other as the second electrode. Each of the transistors (DT, ST) in each subpixel (SP1, SP2, SP3, SP4) can be made of at least one of the following: polysilicon semiconductor, amorphous silicon semiconductor, or oxide semiconductor. The transistors (DT, ST) can be P-type or N-type, or a mixture of P-type and N-type.

[0045] A light-emitting element (ED) may comprise an anode electrode connected to a drive transistor (DT), a cathode electrode receiving a second power supply voltage (EVSS) from a second power supply line (VSSL), and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode is an independent electrode for each light-emitting element, but the cathode electrode may be a common electrode shared by the entire light-emitting element. When a drive current is supplied from the drive transistor (DT), electrons from the cathode electrode are injected into the light-emitting layer, and holes from the anode electrode are injected into the light-emitting layer. The recombination of electrons and holes in the light-emitting layer causes a fluorescent or phosphorescent substance to emit light, thereby generating light with a brightness proportional to the value of the drive current.

[0046] In each subpixel (SP1, SP2, SP3, SP4), a drive transistor (DT) is connected between the anode electrode of the light-emitting element (ED) and a first power supply line (VDDL) that supplies the drive voltage (EVDD). Here, the drive voltage (EVDD) is applied to the first electrode of the drive transistor (DT).

[0047] Such a drive transistor (DT) is a transistor that drives a light-emitting element (ED), and is controlled by the voltage applied to its gate electrode, supplying current to the light-emitting element (ED). This drives the light-emitting element (ED).

[0048] In each subpixel (SP1, SP2, SP3, SP4), a switching transistor (ST) is connected between the first node (N1) of the drive transistor (DT) and the data line (DL). The switching transistor (ST) is controlled by a scan signal (Scan) supplied from the scan line (SCANL) and applies a data voltage (Vdata) supplied from the data line (DL) to the first node (N1).

[0049] In each subpixel (SP1, SP2, SP3, SP4), a capacitor (Cst) is connected to the first node (N1) and charges with the voltage applied to the first node (N1). The capacitor (Cst) can supply the charged drive voltage to the drive transistor (DT). The capacitor (Cst) is a storage capacitor.

[0050] A compensation circuit (CC) can be provided to compensate for the threshold voltage of the drive transistor (DT). A compensation circuit (CC) can consist of one or more transistors. A compensation circuit (CC) can include one or more transistors and a capacitor, and can be configured in various ways depending on the compensation method. Pixels containing a compensation circuit (CC) can have diverse structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0051] In the following section, we will provide a more detailed explanation of the configurations arranged in the non-transparent area (NTA) and transparent area (TA), referring to Figure 5.

[0052] Referring to Figure 5, a display panel 110 according to one embodiment of this specification includes a first substrate 111 and a second substrate 112 facing each other, and circuit elements, light-emitting elements (EDs), a sealing layer 180, a color filter (CF), and a black matrix (BM) can be arranged between the first substrate 111 and the second substrate circuit 112.

[0053] Circuit elements are arranged in the non-transparent region (NTA) for each sub-pixel (SP1, SP2, SP3, SP4) and may include various signal lines, thin-film transistors, capacitors, etc. Signal lines may include pixel power lines, common power lines, scan lines, data lines, etc., and thin-film transistors may include switching transistors and drive transistors (DTs). Switching transistors are switched by scan signals supplied to scan lines and can charge capacitors with data voltages supplied from data lines.

[0054] The driver transistor (DT) is switched by the data voltage charged in the capacitor (Cst, Figure 4) and generates data current from the power supply provided by the pixel power line (VDDL, Figure 4), which it supplies to the first electrode (E1) of the subpixels (SP1, SP2, SP3, SP4). Such a driver transistor (DT) may include an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0055] Specifically, a light-shielding layer (LS) can be provided on the first substrate 111. The light-shielding layer (LS) is provided so as to overlap with the region where the drive transistor (DT) is formed, and can serve to block external light incident on the active layer (ACT) of the drive transistor (DT). A display panel 110 with a transparent region (TA) can be used more often in environments exposed to the outside than indoors. Because the display panel 110 is exposed to external light for a longer period of time, the characteristics of circuit elements such as the drive transistor (DT) may differ. Due to the change in the characteristics of the circuit elements, the brightness of the display panel 110 may decrease, and the screen may become darker.

[0056] In one embodiment of this specification, the display panel 110 can block external light from entering the drive transistor (DT) by placing a light-shielding layer (LS) below the drive transistor (DT). In one embodiment of this specification, the display panel 110 can prevent changes in the characteristics of the drive transistor (DT) and allow the sub-pixels to maintain high brightness.

[0057] Such light-shielding layers (LS) can be formed as single or multi-layer structures made of one of the following materials: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof.

[0058] A buffer film 120 may be provided on the light-shielding layer (LS). The buffer film 120 can protect the transistor (DT) from moisture penetrating through the moisture-vulnerable first substrate 111. For this purpose, the buffer film 120 may be provided in non-transparent regions (NTA) and transparent regions (TA). Such a buffer film 120 can be formed from an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film thereof.

[0059] The buffer film 120 may include an active layer (ACT) for a drive transistor (DT). The active layer (ACT) for the drive transistor (DT) can be formed from a silicon-based semiconductor material or an oxide-based semiconductor material.

[0060] A gate insulating film 130 may be provided on the active layer (ACT) of the drive transistor (DT). The gate insulating film 130 may be provided in the non-transparent region (NTA) and the transparent region (TA). The gate insulating film 130 may be formed from an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multiple film thereof.

[0061] The gate dielectric film 130 may be provided with the gate electrode (GE), source electrode (SE), and drain electrode (DE) of the drive transistor (DT). The gate electrode (GE), source electrode (SE), and drain electrode (DE) of the drive transistor (DT) may be formed in the same layer and of the same material as shown in Figure 5, but are not necessarily limited to this. In other embodiments, the source electrode (SE) and drain electrode (DE) of the drive transistor (DT) may be formed in a different layer and of a different material than the gate electrode (GE). The source electrode (SE) and drain electrode (DE) may be connected to the active layer (ACT) through a first contact hole (CH1).

[0062] The gate electrode (GE), source electrode (SE), and drain electrode (DE) of a drive transistor (DT) can be formed from a single layer or multiple layers of one of the following materials, or an alloy thereof: molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0063] The gate electrode (GE), source electrode (SE), and drain electrode (DE) of the drive transistor (DT) may be provided with a first interlayer insulating film 140 and a second interlayer insulating film 150. The first interlayer insulating film 140 and the second interlayer insulating film 150 may be provided only in the non-transparent region (NTA) and not in the transparent region (TA) in order to increase the light transmittance of the transparent region (TA). Each of the first interlayer insulating film 140 and the second interlayer insulating film 150 can be formed from an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film thereof.

[0064] A planarization film 160 can be provided on the second interlayer insulating film 150 to flatten the step created by the drive transistor (DT). The planarization film 160 can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The planarization film 160 is provided in the non-transparent region (NTA) and may not be provided in at least a portion of the transparent region (TA). In one embodiment of this specification, the display panel 110 can improve the light transmittance of the transparent region (TA) by not providing the planarization film 160 in the transparent region (TA).

[0065] The planarized film 160 is equipped with a light-emitting element (ED) consisting of a first electrode (E1), an emissive layer (EL), and a second electrode (E2), as well as a bank 165.

[0066] The first electrode (E1) is provided on the planarization film 160 and can be electrically connected to the drive transistor (DT). Specifically, the first electrode (E1) can be connected to one of the source electrode (SE) and drain electrode (DE) of the drive transistor (DT) through the first interlayer insulating film 140, the second interlayer insulating film 150, and the second contact hole (CH2) that penetrates the planarization film 160.

[0067] Such first electrodes (E1) are provided for each sub-pixel (SP1, SP2, SP3, SP4) and may not be provided in the transmission region (TA). Banks 165 are provided between adjacent first electrodes (E1) to electrically isolate them.

[0068] The first electrode (E1) can be formed from highly reflective metallic materials such as aluminum-titanium laminated structures (Ti / Al / Ti), aluminum-ITO laminated structures (ITO / Al / ITO), Ag alloy, Ag alloy-ITO laminated structures (ITO / Ag alloy / ITO), MoTi alloy, and MoTi alloy-ITO laminated structures (ITO / MoTi alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), copper (Cu), etc. The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). Such a first electrode (E1) may be the anode electrode.

[0069] The bank 165 can be provided on the planarization film 160. The bank 165 can also be formed to cover the end of the first electrode (E1) while exposing a portion of the first electrode (E1). This prevents the bank 165 from causing a problem in which current concentrates at the end of the first electrode (E1), resulting in a decrease in luminous efficiency.

[0070] Bank 165 can define the light-emitting regions (EAs) of each subpixel (SP1, SP2, SP3, SP4). Each light-emitting region (EA) of a subpixel (SP1, SP2, SP3, SP4) represents a region where a first electrode (E1), an emissive layer (EL), and a second electrode (E2) are stacked in order, and holes from the first electrode (E1) and electrons from the second electrode (E2) combine in the emissive layer (EL) to emit light. In this case, the region where Bank 165 is formed does not emit light and becomes a non-emissive region (NEA), while the region where Bank 165 is not formed and the first electrode (E1) is exposed can become a light-emitting region (EA). Bank 165 may be present in non-transparent regions (NTA) and may not be present in at least a portion of the transmissive regions (TA).

[0071] Such banks 165 can be formed from organic films such as acrylic, epoxy, phenolic, polyamide, and polyimide materials.

[0072] The light-emitting layer (EL) can be placed on the first electrode (E1). The light-emitting layer (EL) may include an Emission Material Layer (EML) containing a light-emitting material. The light-emitting material may be an organic, inorganic, or hybrid material. The light-emitting layer (EL) may have a multilayer structure. For example, the light-emitting layer (EL) may further include at least one of a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL). In this case, when a voltage is applied to the first electrode (E1) and the second electrode (E2), holes and electrons move to the light-emitting material layer via the hole transport layer and electron transport layer, respectively, where they combine with each other and emit light.

[0073] In one embodiment, the light-emitting layer (EL) may be a common layer formed in common on subpixels (SP1, SP2, SP3, SP4). Here, the light-emitting layer (EL) may be a white light-emitting layer that emits white light. In this case, the light-emitting layer (EL) can be formed not only on the subpixels (SP1, SP2, SP3, SP4) but also on the non-light-emitting regions (NEA) between the subpixels (SP1, SP2, SP3, SP4). The light-emitting layer (EL) can be formed continuously between the subpixels (SP1, SP2, SP3, SP4) and the subpixels (SP1, SP2, SP3, SP4). Furthermore, the light-emitting layer (EL) may be present not only on the non-transparent region (NTA) which includes the light-emitting region (EA) and the non-light-emitting region (NEA), but also on the transmissive region (TA), although it is not necessarily limited to this. The light-emitting layer (EL) may also be patterned only on the non-transparent region (NTA) which includes the light-emitting region (EA) and the non-light-emitting region (NEA).

[0074] In other embodiments, the light-emitting layer (EL) can be formed by creating separate light-emitting material layers for each subpixel (SP1, SP2, SP3, SP4). For example, a green light-emitting layer emitting green light can be formed in the first subpixel (SP1), a red light-emitting layer emitting red light can be formed in the second subpixel (SP2), a blue light-emitting layer emitting blue light can be formed in the third subpixel (SP3), and a white light-emitting layer emitting white light can be formed in the fourth subpixel (SP4). In such cases, the light-emitting material layer of the light-emitting layer (EL) may not be formed in the transmission region (TA). However, the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL), excluding the light-emitting material layer, can be formed in common for the subpixels (SP1, SP2, SP3, SP4) and can also be formed in the transmission region (TA).

[0075] The second electrode (E2) can be placed on the light-emitting layer (EL). The second electrode (E2) may be a common layer formed in common for subpixels (SP1, SP2, SP3, SP4). The second electrode (E2) can be formed not only in the light-emitting region (EA) of the subpixels (SP1, SP2, SP3, SP4) but also in the non-light-emitting region (NEA) between the subpixels (SP1, SP2, SP3, SP4). The second electrode (E2) can be formed continuously between subpixels (SP1, SP2, SP3, SP4) and between subpixels (SP1, SP2, SP3, SP4).

[0076] The second electrode (E2) can be formed from a transparent metallic material (TCO, Transparent Conductive Material) such as ITO or IZO, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the upper electrode (E2) is formed from a semi-transmissive metallic material, the light emission efficiency can be increased by a microcavity. Such a second electrode (E2) can be a cathode electrode.

[0077] A sealing layer 180 may be provided on the light-emitting element (ED). The sealing layer 180 may be formed on the second electrode (E2) so as to cover the second electrode (E2). The sealing layer 180 serves to prevent oxygen or moisture from penetrating the light-emitting layer (EL) and the second electrode (E2). For this purpose, the sealing layer 180 may include at least one inorganic film and at least one organic film. The sealing layer 180 may also have a structure in which inorganic films and organic films are alternately stacked, but is not necessarily limited to this.

[0078] A color filter (CF) may be provided on the sealing layer 180. The color filter (CF) can be patterned for each subpixel (SP1, SP2, SP3, SP4). Specifically, the color filter (CF) may include a first color filter, a second color filter, a third color filter, and a fourth color filter. The first color filter may be positioned to correspond to the first subpixel (SP1) and, for example, may be a red color filter that transmits red light. The second color filter may be positioned to correspond to the second subpixel (SP2) and may be a green color filter that transmits green light. The third color filter (CF3) may be positioned to correspond to the third subpixel (SP3) and may be a blue color filter that transmits blue light. The fourth color filter may be positioned to correspond to the fourth subpixel (SP4) and may be a white color filter that transmits white light. The white color filter may, but is not limited to, a transparent organic material that transmits white light.

[0079] A black matrix (BM) can be provided between the patterned color filters (CF) for each subpixel (SP1, SP2, SP3, SP4). The black matrix (BM) is provided between the subpixels (SP1, SP2, SP3, SP4) and can prevent color mixing from occurring between adjacent subpixels (SP1, SP2, SP3, SP4). In addition, the black matrix (BM) can prevent light incident from the outside from being reflected by the multiple signal lines provided between the subpixels (SP1, SP2, SP3, SP4).

[0080] Furthermore, a black matrix (BM) is provided between the transmission region (TA) and multiple subpixels (SP1, SP2, SP3, SP4) to prevent light emitted from each of the subpixels (SP1, SP2, SP3, SP4) from propagating into the transmission region (TA). Such a black matrix (BM) may include a light-absorbing material, such as a black dye that absorbs all light in the visible light wavelength range.

[0081] A first substrate 111, equipped with a color filter (CF) and a black matrix (BM), can be bonded to a second substrate 112 by a separate adhesive layer 190. Here, the adhesive layer 190 may be an optically clear resin layer (OCR) or an optically clear adhesive film (OCA).

[0082] Figure 6 is a schematic plan view showing a power supply short bar and bottleneck section according to one embodiment of this specification, Figure 7 is an enlarged view of area A in Figure 6, and Figure 8 is a cross-sectional view showing an example of a stacked structure of a power supply short bar and pixel power lines. Figure 9 is a diagram showing the current flow in the power supply short bar and bottleneck section according to one embodiment of this specification, Figure 10 is a diagram showing the current flow when the first power line and the second power line have a constant width, and Figure 11 is a diagram showing an example of the current flow in the first power line and the second power line according to one embodiment of this specification. Figure 12 is a diagram showing an example of the current flow when the pull-in section of the bottleneck has a constant width, and Figure 13 is a diagram showing an example of the current flow in the pull-in section of the bottleneck according to one embodiment of this specification.

[0083] A display panel 110 according to one embodiment of this specification can be divided into a display area (DA) where pixels are formed to display an image, and a non-display area (NDA) located around the display area (DA), as shown in Figure 6. The non-display area (NDA) may include a pad area (PA) where power pads are located. The power pads may include a first power pad (PAD1) to which a first power supply voltage (high potential power supply voltage, EVDD) is applied, and a second power pad (PAD2) to which a second power supply voltage (low potential power supply voltage, EVSS) is applied. A flexible film 220 (Figure 1) is attached to the first power pad (PAD1) and the second power pad (PAD2), and can receive the first power supply voltage (high potential power supply voltage, EVDD) and the second power supply voltage (low potential power supply voltage, EVSS) from an external source.

[0084] A display panel 110 according to one embodiment of this specification may include a power short bar 610 and a bottleneck portion 620 in the non-display area (NDA).

[0085] The power short bar 610 can be placed on one side of the display area (DA) of the non-display area (NDA). Specifically, the power short bar 610 can be placed on one of the multiple sides of the display area (DA) where the pad area (PA) is located. The power short bar 610 can be placed between the display area (DA) and the pad area (PA).

[0086] The power short bar 610 can be formed to extend in a second direction (e.g., the X-axis direction) between the display area (DA) and the pad area (PA). The power short bar 610 can connect to a plurality of common power lines (VSSL) provided in the display area (DA) and supply a second power supply voltage (low potential power supply voltage, EVSS) to the plurality of common power lines (VSSL).

[0087] Multiple common power lines (VSSLs) can extend in a first direction (e.g., the Y-axis direction) within the display area (DA). Each of the multiple common power lines (VSSLs) can be located in an opaque area (NTA, Figure 3) and spaced apart from one another. Multiple common power lines (VSSLs) can extend from the display area (DA) to the non-display area (NDA) and connect to a power short bar 610 at one end. Multiple common power lines (VSSLs) can be formed on the same layer as the power short bar 610, but are not necessarily limited to this. Multiple common power lines (VSSLs) can also be located on a different layer from the power short bar 610, in which case they can be connected to the power short bar 610 at one end through a contact hole.

[0088] Multiple common power lines (VSSL) can be connected to multiple light-emitting elements (EDs) in the display area (DA). Multiple common power lines (VSSL) can supply a second power supply voltage (low potential power supply voltage, EVSS) supplied from the power supply short bar 610 to the cathode electrodes (E2) of the multiple light-emitting elements (EDs).

[0089] The bottleneck portion 620 is positioned between the power shorting bar 610 and the second power pad (PAD2), connecting the power shorting bar 610 and the second power pad (PAD2). The bottleneck portion 620 can contact the power shorting bar 610 on one side and the second power pad (PAD2) on the other side. The power shorting bar 610, the bottleneck portion 620, and the second power pad (PAD2) can be formed from the same material in the same layer. That is, the power shorting bar 610, the bottleneck portion 620, and the second power pad (PAD2) can be formed integrally.

[0090] The bottleneck section 620 is formed with a first width (W1) smaller than the power shorting bar 610, and multiple bottleneck sections 620 can be arranged. Here, the first width (W1) can represent the length of the side in contact with the power shorting bar 610. The first width (W1) can be the width in a second direction (e.g., the X-axis direction). Multiple bottleneck sections 620 can be arranged spaced apart from each other. Each of the multiple bottleneck sections 620 is connected to each of the multiple second power pads (PAD2), and can receive a second power supply voltage (low potential power supply voltage, EVSS) from the outside via the multiple second power pads (PAD2). The second power supply voltage (low potential power supply voltage, EVSS) can be applied to the power shorting bar 610 via the multiple bottleneck sections 620 and applied to multiple common power lines (VSSL) of the display area (DA) via the power shorting bar 610.

[0091] Thus, when the second power supply voltage (low potential power supply voltage, EVSS) is transmitted to the power supply short bar 610 and the bottleneck section 620, current can flow from the power supply short bar 610 to the bottleneck section 620. Here, since the bottleneck section 620 has a first width (W1) smaller than that of the power supply short bar 610, current can accumulate in a portion of the bottleneck section 620. The bottleneck section 620 can be damaged by the large amount of heat generated in the area where the current accumulates.

[0092] In one embodiment of this specification, the display panel 110 can mitigate the phenomenon of current accumulation in the bottleneck portion 620 by forming the power supply short bar 610 with a mesh structure.

[0093] Specifically, as shown in Figure 7, the power supply short bar 610 may have a mesh structure in which a plurality of first power lines 612 extending in a first direction (e.g., the Y-axis direction) and a plurality of second power lines 614 extending in a second direction (e.g., the X-axis direction) are connected to each other. The plurality of first power lines 612 and the plurality of second power lines 614 can be integrally formed in the same layer. The plurality of first power lines 612 and the plurality of second power lines 614 can be provided in the same layer and of the same material as the gate electrode (GE, Figure 5) of the drive transistor (DT, Figure 5).

[0094] Multiple first power lines 612 can extend in a first direction (e.g., the Y-axis direction) between the pad area (PA) and the display area (DA) and be spaced apart from each other in a second direction (e.g., the X-axis direction). Some of the multiple first power lines 612 may be in contact with the bottleneck portion 620, while others may not be in contact with the bottleneck portion 620. The multiple first power lines 612 may include a first group (G1) that is in contact with the bottleneck portion 620 at one end and a second group (G2) that is not in contact with the bottleneck portion 620 at one end. The first power lines 612 included in the second group (G2) can be spaced apart from the bottleneck portion 620.

[0095] The first power lines 612 included in the second group (G2) may have a width different from at least one of the first power lines 612 included in the first group (G1). The first power lines 612 included in the second group (G2) may have a width smaller than at least one of the first power lines 612 included in the first group (G1). At least one of the first power lines 612 included in the first group (G1) may have a second width. Among the first power lines 612 included in the first group (G1), the first power lines 612 located in areas excluding the end regions may have a second width. The first power lines 612 included in the second group (G2) may have a third width smaller than the second width. In other words, among the plurality of first power lines 612, the first power lines 612 that do not come into contact with the bottleneck portion 620 may be formed to be relatively thin. On the other hand, of the multiple first power lines 612, most of the first power lines 612 that are in contact with the bottleneck portion 620 can be formed to be relatively thicker.

[0096] Since resistance is inversely proportional to the cross-sectional area, the resistance of the first power line 612 can be low if the cross-sectional area is large, and high if the cross-sectional area is small. Of the multiple first power lines 612, most of the first power lines 612 that are in contact with the bottleneck portion 620 have a relatively large second width, so a large cross-sectional area can be formed and the resistance can be low. Since current is inversely proportional to resistance, a relatively large amount of current can flow through the first power lines 612 included in the first group (G1), as shown in Figure 9.

[0097] On the other hand, among the multiple first power lines 612, the first power lines 612 that do not come into contact with the bottleneck portion 620 have a small third width, so they are formed with a small cross-sectional area and their resistance may increase. As a result, the first power lines 612 included in the second group (G2) can carry a relatively smaller amount of current than the first power lines 612 included in the first group (G1), as shown in Figure 9.

[0098] On the other hand, the first power line 612 included in the first group (G1) may have a width that differs from other parts in at least one part. Specifically, the first power line 612 included in the first group (G1) may include a first subgroup (G11) provided in the first region, a second subgroup (G12) provided in the second region located on one side of the first region, and a third subgroup (G13) provided in the third region located on the other side of the first region.

[0099] The second subgroup (G12) may include the first power line 612 located on the left outermost edge of the first power line 612 included in the first group (G1). The second subgroup (G12) may include, but is not limited to, only one of the first power lines 612 located on the left outermost edge of the first power line 612 included in the first group (G1). The second subgroup (G12) may also include multiple first power lines 612 located in the left end region of the first power line 612 included in the first group (G1).

[0100] The third subgroup (G13) may include the first power line 612 located at the outermost right edge of the first power line 612 included in the first group (G1). The third subgroup (G13) may include, but is not limited to, only one of the first power lines 612 located at the outermost right edge of the first power line 612 included in the first group (G1). The third subgroup (G13) may also include multiple first power lines 612 located at the right end region of the first power line 612 included in the first group (G1).

[0101] The first power lines 612 included in the first subgroup (G11) may have a different width than the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13). The first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) may have a smaller width than the first power line 612 included in the first subgroup (G11).

[0102] The first power lines 612 included in the first subgroup (G11) may have a second width. The first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) may have a fourth width smaller than the second width. In one embodiment, the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) may have the same width as the first power line 612 included in the second group (G2). That is, the fourth width of the first power lines 612 included in the second subgroup (G12) and the third subgroup (G13) may be the same as the third width of the first power line 612 included in the second group (G2).

[0103] Multiple second power lines 614 can extend in a second direction (e.g., the X-axis direction) between the pad area (PA) and the display area (DA), and be spaced apart from each other in a first direction (e.g., the Y-axis direction). Of the multiple second power lines 614, the uppermost second power line 614 may have a portion of its area in contact with the bottleneck portion 620, while other portions may not be in contact with the bottleneck portion 620.

[0104] Multiple second power lines 614 may have different widths in some parts compared to others. A second power line 614 located at a first separation distance from the bottleneck 620 may have a different width than a second power line 614 located at a second separation distance from the bottleneck 620. The first separation distance may be smaller than the second separation distance. In such a case, a second power line 614 located at a first separation distance from the bottleneck 620 may have a fifth width. A second power line 614 located at a second separation distance from the bottleneck 620 may have a sixth width (W5) that is larger than the fifth width. That is, a second power line 614 located closer to the bottleneck 620 may be formed thinner than a second power line 614 located further away from the bottleneck 620.

[0105] The second power line 614, positioned near the bottleneck 620, has a fifth width, resulting in a smaller cross-sectional area and potentially higher resistance. As a result, a relatively small amount of current can flow through the second power line 614 positioned near the bottleneck 620, as shown in Figure 9.

[0106] On the other hand, the second power line 614, which is located far from the bottleneck 620, has a relatively large sixth width, so a large cross-sectional area is formed, and the resistance can be reduced. Since current is inversely proportional to resistance, the second power line 614 located far from the bottleneck 620 can carry a relatively larger amount of current than the second power line 614 located closer to the bottleneck 620, as shown in Figure 9.

[0107] In one embodiment, the width of the multiple second power lines 614 may gradually increase as they move away from the bottleneck 620, as shown in Figure 7. In such a case, the current flow of the multiple second power lines 614 may gradually increase as they move away from the bottleneck 620.

[0108] In one embodiment of this specification, the display panel 110 is formed by a mesh structure consisting of a plurality of first power lines 612 and a plurality of second power lines 614, and the widths of each of the plurality of first power lines 612 and the plurality of second power lines 614 can be designed to be different.

[0109] In one embodiment of this specification, the display panel 110 can be designed with different widths for the multiple first power lines 612. Specifically, in one embodiment of this specification, the display panel 110 can be designed so that a relatively small amount of current flows through the first power lines 612 that do not come into contact with the bottleneck portion 620 by making the first power lines 612 that do not come into contact with the bottleneck portion 620 thinner.

[0110] Furthermore, in one embodiment of this specification, the display panel 110 allows for a thinner first power line 612, specifically the outermost one among the first power lines 612 that contact the bottleneck portion 620. Current flowing through the first power lines 612 that do not contact the bottleneck portion 620 can flow into the first power lines 612 that contact the bottleneck portion 620 via the second power line 614. Here, if all the first power lines 612 that contact the bottleneck portion 620 have the same thickness, the current can be collected in the outermost first power line 612 that has the shortest distance, as shown in Figure 10.

[0111] In one embodiment of this specification, the display panel 110 can prevent current from concentrating in the outermost first power line 612 that is in contact with the bottleneck portion 620 by forming the outermost first power line 612 that is in contact with the bottleneck portion 620 relatively thin. In one embodiment of this specification, the display panel 110 can guide current to flow in the first power line 612 that is in contact with the bottleneck portion 620 by forming the first power line 612 that is in the central region that is in contact with the bottleneck portion 620 relatively thick.

[0112] Furthermore, the display panel 110 according to one embodiment of this specification can be designed to have different widths for the multiple second power lines 614. Specifically, the display panel 110 according to one embodiment of this specification can form the second power lines 614 located near the bottleneck portion 620 to be thinner, and the second power lines 614 located far from the bottleneck portion 620 to be thicker. As a result, the display panel 110 according to one embodiment of this specification can induce a relatively small amount of current to flow through the second power lines 614 located near the bottleneck portion 620, and a relatively large amount of current to flow through the second power lines 614 located far from the bottleneck portion 620.

[0113] In one embodiment of this specification, the display panel 110 can distribute the current flowing from the multiple first power lines 612 and the multiple second power lines 614 into the bottleneck section 620, as shown in Figure 11, by designing the widths of the multiple first power lines 612 and the multiple second power lines 614 to be unequal as described above.

[0114] Current has the characteristic of flowing along the shortest path with the same resistance. Therefore, when the widths of the multiple first power lines 612 and the multiple second power lines 614 are designed to be constant, as shown in Figure 10, current flowing through the power lines 612 and 614 that do not come into contact with the bottleneck 620 can flow into the end region of the bottleneck 620, which is the shortest distance away. This can cause the phenomenon of current accumulating in the end region of the bottleneck 620.

[0115] In contrast, the display panel 110 according to one embodiment of this specification can be designed so that the multiple first power lines 612 and multiple second power lines 614 have different resistances from each other by designing the widths of the multiple first power lines 612 and multiple second power lines 614 to be equal. In the display panel 110 according to one embodiment of this specification, the first power lines 612 that are in contact with the central region of the bottleneck portion 620 and the second power lines 614 that are located far from the bottleneck portion 620 have low resistances, so that, as shown in Figure 11, a relatively large amount of current from the common power line (VSSL) to the power short bar 610 is guided to flow in a distributed manner in the central region of the bottleneck portion 620. As a result, the display panel 110 according to one embodiment of this specification can mitigate the phenomenon of current accumulating in the edge region of the bottleneck portion 620.

[0116] On the other hand, the display panel 110 according to one embodiment of this specification can reduce metal stress by forming the power supply short bar 610 in a mesh structure, compared to forming the power supply short bar 610 as an electrode on a flat plate (or thin film). The power supply short bar 610 can be superimposed on a pixel power line (VDDL) in at least a portion of the area. The pixel power line (VDDL) can extend from the display area (DA) to the pad area (PA) of the non-display area (NDA) and connect to a first power pad (PAD1). The pixel power line (VDDL) can supply a first power supply voltage (high potential power supply voltage, EVDD) supplied from the first power pad (PAD1) to the anode electrodes (E1) of a plurality of light-emitting elements (ED) arranged in the display area (DA). Such a pixel power line (VDDL) can be superimposed on a power supply short bar 610 in at least a portion of the area. Here, the pixel power line (VDDL) and the power supply short bar 610 can have a stacked structure as shown in Figure 8. The power supply short bar 610 can be provided in the same layer as the gate electrode (GE, Figure 5) of the drive transistor (DT, Figure 5) and made of the same material. The pixel power supply line (VDDL) can be provided in the same layer as the light-shielding layer (LS, Figure 5) and made of the same material. In this case, a gate insulating film 130 and a buffer film 120 are provided between the power supply short bar 610 and the pixel power supply line (VDDL) to insulate the power supply short bar 610 from the pixel power supply line (VDDL).

[0117] When the power short bar 610 is formed as a flat (or thin film) electrode, the metal stress caused by the power short bar 610 becomes large, which limits the reduction in the thickness of the insulating film between the power short bar 610 and the pixel power line (VDDL). If the insulating film between the power short bar 610 and the pixel power line (VDDL) is made thin, the metal stress can damage the power short bar 610 and the pixel power line (VDDL), as well as the surrounding insulating film. In one embodiment of this specification, the display panel 110 reduces the metal stress caused by the power short bar 610 by forming the power short bar 610 in a mesh structure, and further prevents damage caused by metal stress. In addition, in one embodiment of this specification, the thickness of the insulating film between the power short bar 610 and the pixel power line (VDDL) can be reduced, thereby reducing the overall thickness of the display panel 110.

[0118] Furthermore, in the display panel 110 according to one embodiment of this specification, the power shorting bar 610 has a mesh structure, which reduces the area in which the power shorting bar 610 and the pixel power line (VDDL) overlap. This prevents the phenomenon of static electricity being discharged between the power shorting bar 610 and the pixel power line (VDDL).

[0119] The bottleneck section 620 is positioned between the power shorting bar 610 and the second power pad (PAD2), connecting the power shorting bar 610 and the second power pad (PAD2). The bottleneck section 620 can be in contact with the power shorting bar 610 on one side and with the second power pad (PAD2) on the other side. Multiple bottleneck sections 620 can be arranged spaced apart in the second direction (for example, the X-axis direction).

[0120] Each bottleneck section 620 includes a pull-in section 622 into which current flows when in contact with the power supply shorting bar 610, and a connection section 624 for connecting the second power supply pad (PAD2) to the pull-in section 622.

[0121] The entry point 622 can make contact with the power supply shorting bar 610 on one side. The entry point 622 makes contact with a portion of the multiple first power supply lines 612, allowing current to flow in from the first power supply line 612 it makes contact with. In addition, the entry point 622 makes contact with a portion of the uppermost second power supply line 614 among the multiple second power supply lines 614, allowing current to flow in from the uppermost second power supply line 614 it makes contact with.

[0122] Such a pull-in section 622 may include a recess 623 formed in a concave shape on at least one side so as to face the central line (CL). The pull-in section 622 may include a recess 623 on at least one side provided between the side in contact with the power shorting bar 610 and the side in contact with the connection section 624.

[0123] As an example, the retractable portion 622 may include a first recess 623a formed in a concave shape on the left end so as to face the center line (CL), and a second recess 623b formed in a concave shape on the right end so as to face the center line (CL). The first recess 623a and the second recess 623b may be formed in a rounded, streamlined or curved shape. As an example, the first recess 623a and the second recess 623b may have a semicircular shape.

[0124] The retraction portion 622 may include a first region (A1) whose width decreases as it moves from the side in contact with the power shorting bar 610 toward the second power pad (PAD2), with a recess 623 formed on at least one side. In one embodiment, the retraction portion 622 may further include a second region (A2) whose width increases as it moves from the first region (A1) toward the second power pad (PAD2).

[0125] In one embodiment of this specification, the display panel 110 has a first region (A1) in which the width of the inlet portion 622 is not constant, and the width decreases as it approaches the second power pad (PAD2) on the side in contact with the power shorting bar 610, thereby distributing the current flowing into the end region of the inlet portion 622. Specifically, the inlet portion 622 of the bottleneck portion 620 can have a constant width as shown in Figure 12. That is, the inlet portion 622 of the bottleneck portion 620 and the power shorting bar 610 can be in contact perpendicularly. In such a case, the inlet portion 622 of the bottleneck portion 620 and the second power line 614 of the power shorting bar 610 can be at a right angle. In such a case, the current flowing into the inlet portion 622 can be concentrated at the end of the inlet portion 622.

[0126] To illustrate with an analogy, current flowing in through the first power line 612a, which does not contact the inlet 622 of the bottleneck section 620, can flow along the shortest path to the second power pad (PAD2). Thus, current flowing in through the first power line 612a, which does not contact the inlet 622 of the bottleneck section 620, can flow to the connection section 624 along the end of the inlet 622 or the recess 623.

[0127] Furthermore, the current flowing in through at least one of the first power lines 612b, 612c located in the end region of the first power line 612 that is in contact with the inlet 622 of the bottleneck section 620 can flow in a direction that is in line with the first power lines 612b, 612c. However, since the inlet 622 is perpendicular to the power shorting bar 610, the first path through which the current flowing in through the first power lines 612b, 612c flows along the end of the inlet 622 after it has flowed to the end on the side where the inlet 622 and the power shorting bar 610 are in contact may be the same distance as the second path through which the current flows in a direction that is in line with the first power lines 612b, 612c. Therefore, of the first power lines 612b, 612c located in the end region of the first power lines 612 that are in contact with the pull-in section 622 of the bottleneck section 620, a portion of the current flowing through them can flow along the second path, while the remaining portion can flow along the first path as shown in Figure 12. As a result, more current can accumulate at the ends of the pull-in section 622 than in the central region, particularly at the end on the side where the pull-in section 622 is in contact with the power short bar 610, which can cause the temperature to rise and damage the pull-in section 622.

[0128] On the other hand, the display panel 110 according to one embodiment of this specification can disperse the current in the end region of the inlet portion 622 by forming a streamlined or curved recess 623 in the inlet portion 622 of the bottleneck portion 620.

[0129] To illustrate with an example, current flowing in through the first power line 612a, which does not contact the draw-in section 622 of the bottleneck section 620, flows along the shortest path to the second power pad (PAD2), and can therefore flow along the end of the draw-in section 622 to the connection section 624. However, the draw-in section 622 according to one embodiment of this specification is provided with a curved recess 623. As a result, the first path through which current flowing in through the first power lines 612b and 612c flows along the end of the draw-in section 622 after it has flowed to the end on the side where the draw-in section 622 and the power short bar 610 are in contact is larger than the second path through which it flows in a direction that is in a straight line with the first power lines 612b and 612c. As a result, current flowing in through at least one of the first power lines 612b and 612c located in the end region of the first power lines 612 that are in contact with the draw-in section 622 of the bottleneck section 620 flows along the second path instead of the first path. As a result, the current can be distributed without concentrating at the end where the pull-in section 622 and the power supply shorting bar 610 are in contact.

Claims

1. A display area where multiple pixels are arranged to display an image, Arranged around the outer edge of the display area, a non-display area including a pad area, In the non-display area, a power short bar is located on one side of the display area, A power pad located in the aforementioned pad area, The bottleneck portion connecting the power shorting bar and the power pad Includes, The power supply short bar has a mesh structure in which a plurality of first power lines extending in a first direction and a plurality of second power lines extending in a second direction are connected to each other. The aforementioned bottleneck portion is A recess formed in a concave shape toward the center line is provided on at least one side, and a pull-in portion is in contact with a part of the plurality of first power lines so that current flows in, A connecting part that connects the aforementioned retraction part and the power pad. including, Display device.

2. The display device according to claim 1, wherein the plurality of second power lines have different widths from each other.

3. The display device according to claim 2, wherein the second power line having a first separation distance from the bottleneck portion has a width smaller than the width of the second power line having a second separation distance from the bottleneck portion, and the first separation distance is smaller than the second separation distance.

4. The display device according to claim 2, wherein the width of the plurality of second power lines increases as they move further away from the bottleneck.

5. The display device according to claim 1, wherein the pull-in portion is not in contact with any of the first power lines other than the portion of the plurality of first power lines.

6. The plurality of first power lines include a first group that contacts the bottleneck at one end and a second group that does not contact the bottleneck at one end. The display device according to claim 1, wherein the first power line included in the second group has a width different from the width of at least one of the first power lines included in the first group.

7. The display device according to claim 6, wherein the first power line included in the second group has a width smaller than the width of at least one of the first power lines included in the first group.

8. The first power line included in the first group includes a first subgroup provided in a first region, a second subgroup provided in a second region located on one side of the first region, and a third subgroup provided in a third region located on the other side of the first region. The first power line included in the first subgroup has a width different from the width of the first power line included in the second subgroup and the third subgroup. The display device according to claim 6.

9. The display device according to claim 8, wherein the second subgroup includes a first power line located on the leftmost outermost edge of the first power lines included in the first group, and the third subgroup includes a first power line located on the rightmost outermost edge of the first power lines included in the first group.

10. The display device according to claim 8, wherein the first power supply line included in the first subgroup has a width greater than the width of the first power supply lines included in the second subgroup and the third subgroup.

11. The display device according to claim 8, wherein the first power lines included in the second subgroup and the third subgroup have the same width as the first power line included in the second group.

12. The display device according to claim 1, wherein the intake portion is in contact with a portion of the uppermost second power line among the plurality of second power lines, and current flows in from the uppermost second power line that is in contact with it.

13. The display device according to claim 1, wherein the pull-in portion includes a region in which the width decreases as it moves from the side in contact with the power supply shorting bar toward the power supply pad.

14. The display device according to claim 1, wherein the recess has a curve.

15. The display device according to claim 1, further comprising a plurality of common power lines extending in the first direction from the display area to the non-display area, one end of which is connected to the power short bar.

16. The display area includes a transparent area through which external light passes, and an opaque area provided between adjacent transparent areas. The display device according to claim 15, wherein each of the plurality of common power lines is arranged in the non-transparent region.

17. The non-transparent region further includes a light-emitting element comprising an anode electrode, a light-emitting layer, and a cathode electrode, The display device according to claim 16, wherein the common power line supplies a power voltage to the cathode electrode of the light-emitting element.

18. The display device according to claim 15, wherein each of the plurality of common power lines is connected to each of the plurality of first power lines of the power short bar.

19. The plurality of common power lines are provided on a different layer from the plurality of first power lines of the power short bar. The display device according to claim 18, wherein each of the plurality of common power lines is connected to each of the plurality of first power lines of the power short bar through a contact hole.

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