Codeword synchronization method, communication device, chip, and chip system

Abstract

The present application provides a codeword synchronization method, a communication device, a chip, and a chip system, and relates to the field of communication technology. The method includes the steps of: entering a synchronization position determination state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determination state, where the synchronization position indicates a start position of a codeword in the data sequence; entering a lock loss detection state in response to determining the synchronization position; verifying a number of selected codewords based on the synchronization position in the lock loss detection state, and re-entering the synchronization position determination state in response to a verification failure. According to the solution of the present application, codeword synchronization can be implemented continuously without inserting additional alignment markers, thereby saving transmission resources.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202210113601.8, named "STATE MACHINE BASED BLOCK CODE SELF-SYNCHRONIZATION METHOD", filed on January 30, 2022, and Chinese Patent Application No. 202210520888.6, named "CODEWORD SYNCHRONIZATION METHOD, COMMUNICATION DEVICE, CHIP, AND CHIP SYSTEM", filed on May 12, 2022, both of which are hereby incorporated by reference in their entirety.

[0002] This application relates to the field of communication technologies, and particularly to codeword synchronization methods, communication devices, chips, and chip systems.

Background Art

[0003] Currently, with the development of communication technologies, channel loss and noise have become important factors restricting data transmission speed and distance. Forward error correction (FEC) provides error correction protection for data during transmission, thereby increasing the data transmission speed and transmission distance of the channel. FEC includes block codes, and block codes include linear block codes and non-linear block codes. Since the encoding and decoding of linear block codes are simple, linear block codes are widely applied in the physical layer and media access control (MAC) sublayer of the data link layer within the open system interconnection model (OSI) model of Ethernet.

[0004] Error detection and correction functions in linear block codes must be implemented based on complete codewords. Therefore, codeword boundaries must be determined in the data sequence; that is, the start and end of complete codewords must be found. This process is called codeword synchronization or frame synchronization.

[0005] Currently, synchronization solutions applicable to linear block codes are available in the industry. One example is the alignment marker (AM) synchronization solution used in the 802.3 standard 200 / 400 GE. In this solution, fixed AM sequences must be inserted at intervals of codewords of a specific length, and the receiver can perform codeword synchronization by identifying the AM sequences. However, the presence of AM sequences is equivalent to inserting additional data into the data stream transmitted by the transmitter, thus adding redundant information. [Overview of the project]

[0006] This application provides a codeword synchronization method, a communication device, a chip, and a chip system, which enable codeword synchronization to be implemented without inserting AM, thereby saving transmission resources. [Means for solving the problem]

[0007] According to a first aspect, the present application provides a codeword synchronization method. The method includes: entering a synchronization position determination state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determination state, wherein the synchronization position indicates the starting position of a codeword in the data sequence; entering a lock loss detection state in response to determining the synchronization position; and verifying a plurality of codewords selected based on the synchronization position in the lock loss detection state, and returning to the synchronization position determination state in response to a verification failure.

[0008] In the solution of this application, the system enters a synchronization position determination state in response to a start signal, and the synchronization position is determined in the synchronization position determination state. After the synchronization position is determined, the system enters a lock loss detection state. In the lock loss detection state, if it is determined that the synchronization position does not meet the verification conditions, the synchronization position is re-determined. Thus, the synchronization method is a self-synchronizing method, and codeword synchronization can be implemented without inserting AM into the transmitter, thereby saving transmission resources. In addition, if the detected synchronization position is inaccurate, the synchronization position may be re-determined, and as a result, continuous codeword synchronization can also be performed. Furthermore, a state machine may be used to implement continuous codeword synchronization, and as a result, continuous codeword synchronization can be implemented more accurately.

[0009] In possible implementations, the step of determining the synchronization position in a received data sequence in a synchronization position determination state includes the step of selecting N observation bits from the data sequence and determining the synchronization position based on the positions of the N observation bits in the synchronization position determination state, where N is an integer of 1 or more.

[0010] In the solution of this application, the observed bit belongs to the data sequence, and the position of the observed bit is a position that can be a synchronous position within the data sequence.

[0011] In possible implementations, the step of determining the synchronization position based on the positions of N observed bits includes the step of selecting the synchronization position from the positions of N observed bits.

[0012] In the solution of this application, the synchronization position can be determined directly from the positions of N observed bits.

[0013] In a possible implementation, the synchronization position determination state includes a first counter reset substate and a first codeword verification substate, and the step of selecting N observation bits from a data sequence and selecting a synchronization position from the positions of the N observation bits in the synchronization position determination state is to set an initial value for the first codeword counter in the first counter reset substate, select one observation bit from a data sequence, and enter the first codeword verification substate in response to selecting one first test block from a data sequence based on the current observation bit. The method includes the steps of: the length of a first test block being equal to the codeword length, and the starting position of the first test block being separated from the current observed bit position by an integer amount equal to the codeword length; verifying the first test block in a first codeword verification substate; in response to a first test block that satisfies the verification conditions, increasing the count value of a first codeword counter by X, where X is an integer greater than or equal to 1; and determining the current observed bit position as the synchronization position in response to the count value of the first codeword counter being equal to a first threshold.

[0014] In the solution of this application, in the test block selected using the current observed bit, a sequence of test blocks of a first threshold satisfies the verification condition, and the position of the current observed bit is determined as the synchronization position. In this way, because the amount of state machine states is relatively small, the synchronization position can be determined quickly.

[0015] In possible implementations, the step of selecting N observed bits from a data sequence and selecting a synchronization position from the positions of the N observed bits in a synchronization position determination state further includes, in response to the count value of a first codeword counter being less than a first threshold, re-entering a first codeword verification sub-state and verifying the next first test block selected based on the current observed bits.

[0016] In possible implementations, the synchronization position determination state further includes a first codeword valid part state, and the step of incrementing the count value of a first codeword counter by X in response to a first test block that satisfies the verification condition includes the step of entering the first codeword valid part state in response to a first test block that satisfies the verification condition, and the step of incrementing the count value of the first codeword counter by X in the first codeword valid part state.

[0017] In possible implementations, the steps of selecting N observed bits from a data sequence and selecting a synchronization position from the positions of the N observed bits in a synchronization position determination state further include the step of verifying the next observed bit selected from the data sequence in response to a first test block that does not satisfy the verification conditions.

[0018] In the solution of this application, after a first test block is selected based on the current observed bit, if the first test block does not satisfy the verification conditions, it indicates that the position of the current observed bit is not the synchronized position, and it is then determined whether the next observed bit is the synchronized position. In this way, the synchronized position can be determined quickly.

[0019] In possible implementations, the synchronization position determination state further includes a first slip portion state, and the step of verifying the next observed bit selected from the data sequence in response to a first test block that does not satisfy the verification condition includes entering a first slip portion state in response to a first test block that does not satisfy the verification condition, slipping to the next observed bit in the first slip portion state, and in response to slipping to the next observed bit, entering a first counter reset portion state again and verifying the next observed bit.

[0020] In the solution of this application, if the first test block does not satisfy the verification conditions, the system enters a first slip partial state, a slip process is performed to slip to the next observed bit, and the system enters the first counter reset partial state again.

[0021] In possible implementations, the synchronization position determination state further includes a first synchronization lock initialization substate, and prior to the step of setting the initial value of the first codeword counter in the first counter reset substate, the method further includes the step of setting the value of the first synchronization lock variable to a first value in the first counter reset substate.

[0022] In possible implementations, the synchronization position determination state further includes a first synchronization lock success substate, and the step of determining the current observed bit position as the synchronization position in response to the count value of a first codeword counter being equal to a first threshold includes the step of entering a first synchronization lock success substate in response to the count value of a first codeword counter being equal to a first threshold, and the step of setting the value of a first synchronization lock variable to a second value in the first synchronization lock success substate, wherein the value of the first synchronization lock variable being the second value indicates that the current observed bit position is the synchronization position.

[0023] In possible implementations, the method further includes the step of setting the value of a first codeword variable to be verified to a third value in a first synchronization lock initialization substate, the step of entering a first codeword verification substate in response to selecting a first test block from a data sequence based on the current observed bits, the step of setting the value of a first codeword variable to a fourth value in response to selecting a first test block from a data sequence based on the current observed bits, and the step of entering a first codeword verification substate in response to the value of the first codeword variable to be verified being the fourth value and the value of the first synchronization lock variable being the first value.

[0024] In a possible implementation form, the lock loss detection state includes a second codeword verification partial state. In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position includes, in response to determining the synchronization position, the step of re-entering the first counter reset partial state, and in response to selecting one first codeword based on the synchronization position, the step of entering the second codeword verification partial state, and the step of verifying the first codeword in the second codeword verification partial state.

[0025] In a possible implementation form, in the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position further includes the step of setting the initial values of the first codeword counter and the first invalid codeword counter in the first counter reset partial state. In response to a verification failure, the step of re-entering the synchronization position determination state is the step of increasing the count value of the first codeword counter by Y and increasing the count value of the first invalid codeword counter by Z in response to a first codeword that does not meet the verification condition, where both Y and Z are integers greater than or equal to 1. The step further includes, when the count value of the first codeword counter is less than or equal to a second threshold and a third threshold is less than the second threshold, the step of re-entering the synchronization position determination state in response to the count value of the first invalid codeword counter being equal to the third threshold.

[0026] In the solution of this application, the synchronization position determination process and the lock loss detection process can share several states. As a result, the process of implementing continuous codeword synchronization can be simplified.

[0027] In a possible implementation form, the synchronization position determination state includes a first slip partial state. The step of re-entering the synchronization position determination state includes the step of entering the first slip partial state, the step of slipping to the next observed bit in the first slip partial state, and in response to slipping to the next observed bit, the step of re-entering the first counter reset partial state and verifying the next observed bit.

[0028] In a possible implementation form, the step of determining the synchronization position based on the positions of N observation bits includes a step of selecting candidate positions in the data sequence from the positions of the N observation bits, and a step of determining the synchronization position based on the candidate positions.

[0029] In the solution of this application, the position with the highest possibility of being the synchronization position, that is, the candidate position, can be first selected from the positions of the N observation bits, and then the candidate position is used to determine the synchronization position, as a result, the determined synchronization position becomes more accurate.

[0030] In possible implementations, N is greater than 1, the synchronization position determination state includes a second counter reset substate and a third codeword verification substate, the step of selecting N observation bits from a data sequence, and in the synchronization position determination state, selecting a candidate position in the data sequence from the positions of the N observation bits, the step of setting an initial value for a second codeword counter and an initial value for a first currently valid codeword counter in the second counter reset substate, the step of selecting one observation bit from a data sequence, and the step of entering a third codeword verification substate in response to selecting a second test block from a data sequence based on the current observation bit, wherein the length of the second test block is equal to the codeword length, and the starting position of the second test block and the position of the current observation bit are separated by an integer amount of the codeword length, and in the third codeword verification substate, The process includes the steps of: verifying two test blocks; increasing the count value of a second codeword counter by W, where W is an integer greater than or equal to 1; increasing the count value of a first currently valid codeword counter by P, where P is an integer greater than or equal to 1, in response to a second test block that satisfies the verification conditions; increasing the value of the observed bit count variable by 1, updating the value of the candidate synchronization position variable to the current observed bit position, updating the current value of the maximum valid codeword count variable to the count value of the first currently valid codeword counter, in response to the count value of the second codeword counter being equal to a fourth threshold and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword count variable; and determining the current value of the candidate synchronization position variable as a candidate position in response to the value of the observed bit count variable being equal to N.

[0031] In the solution of this application, verification is performed sequentially on N observation bits, and the observation bits corresponding to the maximum number of test blocks that satisfy the verification conditions are selected from among the N observation bits, and the position of the observation bits is determined as a candidate position. In this way, each observation bit is verified to select a candidate position, so the determined candidate position may be more accurate, in other words, the determined candidate position is more likely to be a synchronization position.

[0032] In possible implementations, the synchronization position determination state further includes a candidate position selection substate, and in response to the count value of the second codeword counter being equal to a fourth threshold and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword count variable, the step of incrementing the value of the observed bit count variable by 1, updating the value of the candidate synchronization position variable to the position of the current observed bit, and updating the current value of the maximum valid codeword count variable to the count value of the first currently valid codeword counter, wherein the count value of the second codeword counter is The process includes the steps of entering a candidate position selection substate in response to the value being equal to a fourth threshold, and in the candidate position selection substate, in response to the count value of the second codeword counter being equal to the fourth threshold and the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword count variable, the steps of incrementing the value of the observed bit count variable by 1, updating the value of the candidate synchronization position variable to the position of the current observed bit, and updating the current value of the maximum valid codeword count variable to the count value of the first currently valid codeword counter.

[0033] In possible implementations, the steps of selecting N observed bits from a data sequence and selecting a candidate position in the data sequence from the positions of the N observed bits in a synchronized position determination state further include the step of verifying the next observed bit selected from the data sequence in response to the value of the number of observed bits variable being less than N.

[0034] In possible implementations, the synchronization position determination state further includes a second slip partial state, and the step of verifying the next observed bit selected from the data sequence in response to the value of the observed bit number variable being less than N includes the step of entering the second slip partial state in response to the value of the observed bit number variable being less than N, the step of slipping to the next observed bit in the second slip partial state, and the step of re-entering the second counter reset partial state in response to slipping to the next observed bit and verifying the next observed bit.

[0035] In possible implementations, the synchronization position determination state further includes a second synchronization lock initialization substate, and prior to the step of setting the initial value of the second codeword counter and the initial value of the first currently valid codeword counter in the second counter reset substate, the method further includes the step of setting the value of the observed bit count variable to a fifth value, the value of the candidate synchronization position variable to a sixth value, and the value of the maximum valid codeword count variable to a seventh value in the second synchronization lock initialization substate.

[0036] In a possible implementation, the method further includes the step of setting the value of a second codeword variable to be verified to a third value in a second synchronization lock initialization substate, and the step of entering a third codeword verification substate in response to selecting a second test block from a data sequence based on the current observed bits includes the step of setting the value of a second codeword variable to a fourth value in response to selecting a second test block from a data sequence based on the current observed bits, and the step of entering a third codeword verification substate in response to the value of the second codeword variable to be verified being the fourth value.

[0037] In possible implementations, the step of selecting N observed bits from a data sequence and selecting candidate positions in the data sequence from the positions of the N observed bits in the synchronization position determination state further includes, in response to the count value of a second codeword counter being less than a fourth threshold, the step of re-entering a third codeword verification substate and verifying the next second test block selected based on the current observed bits.

[0038] In possible implementations, the synchronization position determination state includes a third counter reset substate and a fourth codeword verification substate, and the step of selecting N observation bits from a data sequence and selecting a candidate position in the data sequence from the positions of the N observation bits in the synchronization position determination state includes setting an initial value for a third codeword counter and an initial value for a first effective codeword counter in the third counter reset substate, selecting one observation bit from a data sequence, and entering a fourth codeword verification substate in response to selecting a third test block from a data sequence based on the current observation bit, wherein the length of the third test block is equal to the codeword length, and the third The process includes the steps of: separating the start position of the test block and the current observed bit position by an integer amount equal to the codeword length; verifying the third test block in a fourth codeword verification substate; in response to a third test block that satisfies the verification conditions, increasing the count value of the third codeword counter by M and increasing the count value of the first effective codeword counter by Q, where both M and Q are integers greater than or equal to 1; and determining the current observed bit position as a candidate position in response to the count value of the first codeword counter being equal to the sixth threshold, provided that the count value of the third codeword counter is less than or equal to a fifth threshold and the fifth threshold is greater than or equal to a sixth threshold.

[0039] In the solution of this application, N observation bits are sequentially verified, and when the number of test blocks that satisfy the verification conditions reaches a specific number within the test blocks selected based on a particular observation bit, the position of the observation bit is determined as a candidate position. In this way, it is not necessary to perform verification for all observation bits, and as a result, candidate positions can be determined quickly.

[0040] In possible implementations, the synchronization position determination state further includes a second codeword valid part state, and the step of increasing the count value of the third codeword counter by M and the count value of the first valid codeword counter by Q in response to a third test block that satisfies the verification condition includes the step of entering the second codeword valid part state in response to a third test block that satisfies the verification condition, and in the second codeword valid part state, the step of increasing the count value of the third codeword counter by M and the count value of the first valid codeword counter by Q.

[0041] In possible implementations, the step of selecting N observed bits from a data sequence and selecting a candidate position in the data sequence from the positions of the N observed bits in a synchronization position determination state further includes the step of verifying the next observed bit selected from the data sequence in a second codeword valid part state, in response to the count value of a third codeword counter being equal to a fifth threshold and the count value of a first valid codeword counter being less than a sixth threshold.

[0042] In possible implementations, the step of selecting N observed bits from a data sequence and selecting candidate positions in the data sequence from the positions of the N observed bits in the synchronization position determination state further includes the step of re-entering the fourth codeword verification part state in response to the count value of the third codeword counter being less than a fifth threshold and the count value of the first valid codeword counter being less than a sixth threshold in the second codeword valid part state, and verifying the next third test block selected based on the current observed bits.

[0043] In possible implementations, the synchronization position determination state further includes a first codeword invalidation part state, and the step of selecting N observed bits from a data sequence and selecting a candidate position in the data sequence from the positions of the N observed bits in the synchronization position determination state further includes entering the first codeword invalidation part state in response to a third test block that does not satisfy the verification condition, incrementing the count value of a third codeword counter by M in the first codeword invalidation part state, and verifying the next observed bit selected from the data sequence in response to the count value of the third codeword counter being equal to a fifth threshold.

[0044] In a possible implementation, the step of selecting N observed bits from a data sequence and determining a candidate position in the data sequence based on the N observed bits in a synchronization position determination state further includes, in a first codeword invalidation state, in response to the count value of a third codeword counter being less than a fifth threshold, entering a fourth codeword verification state again and verifying the next third test block selected based on the current observed bits.

[0045] In possible implementations, the synchronization position determination state includes a third slip partial state, and the step of verifying the next observed bit selected from the data sequence further includes entering the third slip partial state, slipping to the next observed bit in the third slip partial state, and in response to slipping to the next observed bit, entering the third counter reset partial state again and verifying the next observed bit.

[0046] In possible implementations, the synchronization position determination state further includes a third synchronization lock initialization substate, and prior to the step of setting the initial value of the third codeword counter and the initial value of the first effective codeword counter in the third counter reset substate, the method further includes the step of setting the value of the third codeword variable to be verified to the third value in the third synchronization lock initialization substate.

[0047] In possible implementations, the step of entering a fourth codeword verification substate in response to selecting a third test block from a data sequence based on the current observed bits includes the steps of setting the value of a third codeword variable to be verified to a fourth value in response to selecting a third test block from a data sequence based on the current observed bits, and entering a fourth codeword verification substate in response to the value of the third codeword variable to be verified being a fourth value.

[0048] In possible implementations, the step of determining the synchronization position based on candidate positions includes verifying the candidate positions and, after successful verification, determining the candidate positions as the synchronization positions.

[0049] In the solution of this application, candidate positions are selected, then verified, and if the verification is successful, the candidate positions are determined to be the synchronized positions. Because further verification is performed on the candidate positions, the determined synchronized positions can be more accurate.

[0050] In possible implementations, the synchronization position determination state further includes a fourth counter reset substate and a fifth codeword verification substate, and the steps of verifying a candidate position and determining that the candidate position is a synchronization position after successful verification include: setting an initial value for the fourth codeword counter in the fourth counter reset substate and selecting one fourth test block from a data sequence based on the candidate position; entering the fifth codeword verification substate in response to selecting one fourth test block from a data sequence based on the candidate position; verifying the fourth test block in the fifth codeword verification substate; incrementing the count value of the fourth codeword counter by R in response to a fourth test block that satisfies the verification condition, where R is an integer greater than or equal to 1; and determining that the candidate position is a synchronization position in response to the count value of the fourth codeword counter being equal to a seventh threshold.

[0051] In the solution of this application, a fourth test block selected based on the candidate position is sequentially verified, and when the number of fourth test blocks that satisfy the verification conditions reaches a certain number, the candidate position is determined to be a synchronized position. This allows for the determination of whether or not the candidate position is a synchronized position.

[0052] In possible implementations, the synchronization position determination state further includes a third codeword valid part state, and the step of incrementing the count value of the fourth codeword counter by R in response to a fourth test block that satisfies the verification condition includes the step of entering the third codeword valid part state in response to a fourth test block that satisfies the verification condition, and the step of incrementing the count value of the fourth codeword counter by R in the third codeword valid part state.

[0053] In possible implementations, the step of verifying a candidate position and, after successful verification, determining the candidate position as a synchronization position further includes, in response to the count value of the fourth codeword counter being less than the seventh threshold, re-entering the fifth codeword verification substate and verifying the next fourth test block selected based on the candidate position.

[0054] In possible implementations, the step of verifying candidate positions and, after successful verification, determining a candidate position as a synchronized position further includes the step of re-selecting a candidate position in response to a fourth test block that does not satisfy the verification conditions.

[0055] In the solution of this application, if one fourth test block does not satisfy the verification conditions, a candidate position is re-selected, and as a result, the selected candidate position may be more likely to be a synchronized position.

[0056] In possible implementations, the synchronization position determination state further includes a first resynchronization partial state, and the step of re-selecting a candidate position in response to a fourth test block that does not satisfy the verification condition includes the steps of entering the first resynchronization partial state in response to a fourth test block that does not satisfy the verification condition, and setting the value of a first resynchronization lock variable to a second value in the first resynchronization partial state, wherein the value of the first resynchronization lock variable being the second value indicates that a candidate position in the data sequence is being re-selected.

[0057] In possible implementations, the synchronization position determination state further includes a second synchronization lock success partial state, and the step of determining a candidate position as a synchronization position in response to the count value of a fourth codeword counter being equal to a seventh threshold includes the step of entering the second synchronization lock success partial state in response to the count value of a fourth codeword counter being equal to a seventh threshold, and the step of setting the value of a second synchronization lock variable to a second value in the second synchronization lock success partial state, wherein the value of the second synchronization lock variable being a second value indicates that the candidate position is a synchronization position.

[0058] In possible implementations, the step of determining the synchronization position based on candidate positions includes the step of determining the candidate positions as synchronization positions.

[0059] In the solution of this application, candidate positions are directly determined as synchronization positions, and as a result, synchronization positions can be determined quickly.

[0060] In a possible implementation, the steps of verifying a set of codewords selected based on the synchronization position in a lock loss detection state, and re-entering the synchronization position determination state in response to a verification failure, include: verifying a codeword in a set of codewords selected based on the synchronization position in a lock loss detection state, wherein the set of codewords includes a target number of codewords; and re-entering the synchronization position determination state in response to the number of codewords in the set of codewords that do not satisfy the verification conditions reaching an eighth threshold.

[0061] In the solution of this application, after a synchronization position is selected, it is sequentially determined whether the synchronization position is correct, and as a result, sequential codeword synchronization may be performed. In addition, it is determined whether the number of codewords that do not satisfy the verification conditions reaches a certain value, and the number of codewords that do not satisfy the verification conditions is relatively small. Therefore, it is determined whether the synchronization position is accurate based on the number of codewords that do not satisfy the verification conditions, and as a result, it is possible to determine whether the synchronization position is accurate more quickly.

[0062] In possible implementations, the lock loss detection state includes a fifth counter reset substate and a sixth codeword verification substate, and in the lock loss detection state, the steps include verifying a codeword in a codeword set selected based on the synchronization position, wherein the codeword set includes a target number of codewords, and in response that the number of codewords in the codeword set that do not satisfy the verification condition has reached an eighth threshold, the steps include setting an initial value for the fifth codeword counter and an initial value for the second invalid codeword counter in the fifth counter reset substate, and the synchronization position The process includes: entering a sixth codeword verification substate in response to selecting a second codeword from a data sequence based on the above; verifying the second codeword in the sixth codeword verification substate; in response to a second codeword that does not satisfy the verification condition, incrementing the count value of the fifth codeword counter by 1 and incrementing the count value of the second invalid codeword counter by 1; and, if the count value of the fifth codeword counter is less than a target value, entering the synchronization position determination state again in response to the count value of the second invalid codeword counter being equal to an eighth threshold.

[0063] In the solution of this application, after a synchronization position is selected, it is continuously determined whether the synchronization position is correct, and as a result, continuous codeword synchronization may be performed.

[0064] In possible implementations, the lock loss detection state further includes a second codeword invalidation state, and the step of incrementing the count value of a fifth codeword counter by 1 in response to a second codeword that does not satisfy the verification condition, and incrementing the count value of a second invalid codeword counter by 1, includes the step of entering a second codeword invalidation state in response to a second codeword that does not satisfy the verification condition, and in the second codeword invalidation state, the step of incrementing the count value of a fifth codeword counter by 1 and incrementing the count value of a second invalid codeword counter by 1.

[0065] In a possible implementation, the steps include: verifying a codeword in a codeword set selected based on the synchronization position in a lock loss detection state, wherein the codeword set includes a target number of codewords; and re-entering the synchronization position determination state in response to the number of codewords in the codeword set that do not satisfy the verification condition reaching an eighth threshold; incrementing the count value of a fifth codeword counter by 1 in response to a second codeword that satisfies the verification condition; and re-entering the fifth counter reset partial state and performing the next verification on the synchronization position in response to the count value of the fifth codeword counter being equal to the target value.

[0066] In possible implementations, the lock loss detection state further includes a fourth codeword valid partial state, and the step of incrementing the count value of a fifth codeword counter by 1 in response to a second codeword that satisfies the verification condition includes the step of entering the fourth codeword valid partial state in response to a second codeword that satisfies the verification condition, and the step of incrementing the count value of the fifth codeword counter by 1 in the fourth codeword valid partial state.

[0067] In a possible implementation, the steps of verifying a codeword in a codeword set selected based on the synchronization position in a lock loss detection state, wherein the codeword set includes a target number of codewords, and re-entering the synchronization position determination state in response to the number of codewords in the codeword set that do not satisfy the verification conditions reaching an eighth threshold, further include the steps of re-entering the sixth codeword verification state in a third codeword validity state in response to the count value of a fifth codeword counter being less than a target value, and verifying the next second codeword selected based on the synchronization position.

[0068] In a possible implementation, the steps of verifying a codeword in a codeword set selected based on the synchronization position in a lock loss detection state, wherein the codeword set includes a target number of codewords, and re-entering the synchronization position determination state in response to the number of codewords in the codeword set that do not satisfy the verification conditions reaching an eighth threshold, further include the steps of re-entering the sixth codeword verification state in response to the count value of a fifth codeword counter being less than a target value and the count value of a second invalid codeword counter being less than an eighth threshold in a second codeword invalid part state, and verifying the next second codeword selected based on the synchronization position.

[0069] In a possible implementation, the steps include: in a lock loss detection state, verifying a codeword in a codeword set selected based on the synchronization position, wherein the codeword set includes a target number of codewords; and in response that the number of codewords in the codeword set that do not satisfy the verification condition has reached an eighth threshold, re-entering the synchronization position determination state; and in a second codeword invalidation partial state, in response that the count value of a fifth codeword counter is equal to the target value and the count value of a second invalid codeword counter is less than the eighth threshold, re-entering the fifth counter reset partial state and performing the next verification on the synchronization position.

[0070] In possible implementations, the verification conditions are that the number of zero elements in the syndrome of the test block or codeword is greater than the synchronization threshold, or that the number of non-zero elements in the syndrome of the test block or codeword is less than the asynchronous threshold, or that the test block or codeword is an error-correction test block, or that the reparity bit of the test block or codeword is the same as the original parity bit.

[0071] In the solution of this application, verification can be performed on test blocks or codewords in multiple ways, resulting in more flexible verification of test blocks and codewords.

[0072] In possible implementations, the start signal may include a system reset or start signal, a data reception failure signal, or a resynchronization signal.

[0073] In possible implementations, the data sequence is a bitstream encoded via FEC. Thus, the codeword synchronization method can be applied to a bitstream encoded via FEC.

[0074] According to a second aspect, the present application provides a codeword synchronization device. The device is A synchronization position determination module is configured to enter a synchronization position determination state in response to a start signal, determine the synchronization position within the received data sequence in the synchronization position determination state, and determine the synchronization position to indicate the starting position of a codeword within the data sequence. A lock loss detection module is configured to enter a lock loss detection state in response to determining the synchronization position, to verify a set of codewords selected based on the synchronization position in the lock loss detection state, and to re-enter the synchronization position determination state in response to a verification failure. Includes.

[0075] According to a third aspect, the present application provides a communication device. The communication device includes a processor and memory. The memory stores at least one computer instruction. The computer instruction is loaded and executed by the processor to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect.

[0076] According to a fourth aspect, the present application provides a chip configured to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect.

[0077] According to a fifth aspect, the present application provides a chip system comprising a cascaded first chip and a second chip. The first chip is configured to implement a codeword synchronization method according to the first aspect or a possible implementation of the first aspect. The second chip is configured to perform codeword synchronization based on AM mode. [Brief explanation of the drawing]

[0078] [Figure 1] This is a diagram illustrating the principle of a state machine according to an exemplary embodiment of this application. [Figure 2] This is a diagram of a codeword and synchronization position according to an exemplary embodiment of the present application. [Figure 3] This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application. [Figure 4] This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application. [Figure 5] This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application. [Figure 6] This is a diagram illustrating an application scenario according to an exemplary embodiment of the present application. [Figure 7] This is a schematic logic diagram of codeword synchronization according to an exemplary embodiment of the present application. [Figure 8] This is a flowchart of a method for implementing codeword synchronization based on a state machine, according to an exemplary embodiment of the present application. [Figure 9] This is a state diagram for determining the synchronization position according to an exemplary embodiment of the present application. [Figure 10] This is a state diagram of synchronization position determination and lock loss detection according to an exemplary embodiment of the present application. [Figure 11] This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application. [Figure 12] This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application. [Figure 13] This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application. [Figure 14] This is a state diagram showing the determination of whether to verify a candidate position according to an exemplary embodiment of the present application. [Figure 15] This is a state diagram showing the determination of whether to verify a candidate position according to an exemplary embodiment of the present application. [Figure 16] This is a state diagram of a lock loss detection process according to an exemplary embodiment of the present application. [Figure 17] This is a state diagram of a lock loss detection process according to an exemplary embodiment of the present application. [Figure 18] This is a state diagram illustrating the determination of a candidate position according to an exemplary embodiment of the present application. [Figure 19] This is a schematic diagram of the structure of a codeword synchronization device according to an exemplary embodiment of the present application. [Figure 20] This is a diagram showing the structure of a communication device according to an exemplary embodiment of the present application. [Figure 21] This is a diagram showing the structure of a communication device according to an exemplary embodiment of the present application. [Modes for carrying out the invention]

[0079] To clarify the purpose, technical solution, and advantages of this application, the implementation of this application will be described in detail from here on with reference to the attached drawings.

[0080] The following sections will explain and describe some of the terms and concepts used in the embodiments of this application.

[0081] 1. Codeword Synchronization: Codeword synchronization refers to the process of determining the start and end positions of complete codewords within a data sequence. A data sequence is sometimes called a data stream or bitstream, and codeword synchronization is sometimes called frame synchronization.

[0082] 2. State Machine: The full name is finite state machine (FSM). A state machine is a mathematical model obtained by extracting and abstracting the operations necessary to implement a particular function. A state machine divides all the operations necessary to implement the function into a finite number of related states. Each state contains one or more suboperations. Transitions between states are triggered by input signals or changes in specific parameters. Specific parameters are stored in registers and are considered register variables. A state machine can be in only one state at any given moment.

[0083] When a state machine is implemented in hardware, it includes combinational logic circuits and registers. The combinational logic circuits are configured to perform operations, and the registers are configured to store register variables.

[0084] State machines can be represented in several ways, but state diagrams (or state transition diagrams) are the most common due to their intuitiveness. In a state diagram, each state is represented using a rectangle, which is divided into two parts by a horizontal line within the rectangle: the upper part is the state name, and the lower part is the operation to be performed in that state. Transitions between states are represented using one-way arrows, and the text description on the arrow indicates the conditions that must be met for the transition; these conditions are called transition conditions. Figure 1 provides an example of a single state and the conditions for entering and exiting that state. When a state machine enters a state, the operations in that state are performed first, then it is checked whether the transition conditions are met, and if the transition conditions are met, it enters the next corresponding state.

[0085] In Figure 1, states are represented using rectangles. This is merely an example as used herein. States may be represented alternatively using other shapes, such as circles, and state transitions may be represented alternatively using other arrows or shapes. This is not limited to the embodiments of this application.

[0086] The background to this application will be explained below.

[0087] Signal loss and noise can cause errors when signals are transmitted over a channel, affecting the reliability of communication systems. When a signal is represented in the form of a data sequence containing multiple bits, transmission errors manifest specifically as changes in the values ​​of some bits within the data sequence, i.e., bit errors. FEC is a technique for controlling transmission errors in communication systems. In FEC techniques, redundant information is transmitted along with the original data sequence to recover errors during transmission and reduce the bit error rate. FEC can be classified into block codes and convolutional codes based on different data sequence processing modes. Block codes may be further subdivided into linear block codes and nonlinear block codes. A systematic code, a linear block code, is used as an example. The transmitter groups the original data sequence. The length of each group is k bits. In each group, nk bits of redundant information are added according to a specific coding rule, and this redundant information is called a parity bit. Finally, a codeword of length n bits is obtained, where both n and k are integers. Thus, in a codeword of length n bits, the first k bits are the original data, also called information bits, and the last nk bits are parity bits. A complete codeword includes the information bits and the parity bits. After a codeword is transmitted from the transmitter to the receiver over a channel, if the number of error bits in the codeword is within the error correction range, the receiver can check and correct the error bits by decoding, and restore the received codeword to the original data transmitted by the transmitter. This reduces interference caused by the channel and improves the reliability of the communication system. The error detection and error correction functions of linear block codewords must be implemented based on the complete codeword. Therefore, before the data sequence received by the receiver is decoded, the boundaries of the codeword must be determined within the data sequence; that is, the start and end positions of the complete codeword must be found. This process is called codeword synchronization or frame synchronization.If codeword synchronization is incorrect, that is, if the correct starting position is not determined, error detection or error correction cannot be achieved in the subsequent decoding process, potentially even increasing the bit error rate and causing performance degradation of the communication system. This highlights the importance of codeword synchronization.

[0088] Organizational coding is used as an example. Figure 2 shows the synchronization position of a codeword. As shown in Figure 2, the total length of a codeword is n bits, the first k bits are the original data, the last nk bits are the parity bits, and the synchronization position in the data sequence is the starting position of the codeword, i.e., the position of the first bit in the codeword. In a data sequence, there are multiple synchronization positions, and these synchronization positions are related to one another. In other words, the interval between adjacent synchronization positions is fixed, and this interval is equal to the length of the codeword, which is abbreviated as the codeword length.

[0089] In embodiments of this application, organizational codes are used as illustrative examples below, but this application is not limited to organizational codes and is applicable to non-organizational codes as well. This application is applicable to all communication systems that use linear block codes. Linear block codes include, but are not limited to, Reed-Solomon code (RS code), Bose-Chaudhuri-Hocquenghem code (BCH code), Low-Density Parity-Check code (LDPC code), Hamming code, Golay code, and Reed-Muller code.

[0090] The following describes the hardware devices and application scenarios in the embodiments of this application.

[0091] The embodiments of this application are applicable to communication devices that perform FEC, such as routers, switches, or servers.

[0092] The following provides three application scenarios implemented by referencing the physical layer of the Ethernet standard. For example, in a two-level cascaded FEC scenario, the Reed-Solomon code (RS) of the Ethernet standard is used as the outer cascaded FEC (FEC1). Since the AM solution is already used in the Ethernet standard to perform receiver RS-FEC codeword synchronization, the codeword synchronization solution in the embodiments of this application may be applied to the inner FEC (FEC2) of the two-level cascaded FEC. The inner FEC may also be called the first FEC, and the outer FEC may also be called the second FEC.

[0093] In Application Scenario 1, the two-level cascaded FECs are located on different chips. The chip on which FEC1 is located can use transmit-end and receive-end structures defined in existing standards, and codeword synchronization is performed during decoding using an AM solution. Referring to Figure 3, in the transmitter and receiver, FEC1 is typically integrated into an application-specific integrated circuit (ASIC), and codeword synchronization is performed during decoding using an AM solution, while FEC2 is typically integrated into a clock and data recovery (CDR), retimer, optical digital signal processor (oDSP), etc., and codeword synchronization is performed during decoding using the solution in the embodiments of this application. Application Scenario 1 is typically a long-distance or high-rate transmission scenario where FEC2 is needed at a relay node to enhance error correction capability. In this specification, if the relay node is an oDSP, the link can transmit optical signals.

[0094] In application scenario 2, the two-level cascade FEC is located on the same chip in both the transmitter and receiver. Referring to Figure 4, in the transmitter and receiver, FEC1 is integrated into the ASIC and codeword synchronization is performed during decoding using an AM solution, and FEC2 is integrated into the ASIC and codeword synchronization is performed during decoding using the codeword synchronization solution of the embodiments of this application. In application scenario 2, additional physical units of FEC2 are added to the transmitter end chip and the receiver end chip.

[0095] In application scenario 3, the two-level cascade FEC is located on the same chip at one end of the transmitter and receiver, and on different chips at the other end. In FEC1, codeword synchronization is performed during decoding using an AM solution, and in FEC2, codeword synchronization is performed during decoding using the codeword synchronization solution of the embodiments of this application. In application scenario 3, the physical unit of FEC2 is added to one end of the two-level cascade FEC where the same chip is located, and FEC1 at the other end still uses the transmit-end or receive-end structure defined by the Ethernet standard, while FEC2 is integrated into a CDR, retimer, oDSP, etc. Referring to Figure 5, in the transmitter, FEC1 and FEC2 are integrated into an ASIC, and in the receiver, FEC1 is integrated into an ASIC, and FEC2 is integrated into a CDR, retimer, or oDSP. Referring to Figure 6, in the transmitter, FEC1 is integrated into the ASIC, and FEC2 is integrated into the CDR, retimer, or oDSP. In the receiver, FEC1 and FEC2 are integrated into the ASIC.

[0096] It should be noted that the three application scenarios are described using a two-level cascaded FEC as an example. The codeword synchronization solution in the embodiments of this application may be applied alternatively to multi-level cascaded FEC scenarios and may be applied not only to the inner FEC technology but also to the technology of each layer FEC. This is not limited to the embodiments of this application.

[0097] In addition, this embodiment of the present application may be applied alternatively to non-cascaded FEC scenarios. In other words, both the transmitter and receiver perform FEC once, and the codeword synchronization solution in the embodiment of the present application may also be applied once to FEC.

[0098] The following describes the steps of a method for implementing codeword synchronization based on a state machine in one embodiment of this application.

[0099] In this embodiment of the present application, the full synchronization procedure includes two phases, a synchronization lock phase and a lock loss detection phase, to form a closed loop such that the receiving side of the communication system is in a synchronization lock state as much as possible, as shown in Figure 7. For example, in the synchronization lock phase, the synchronization position is determined, and in the lock loss detection phase, it is continuously determined whether the synchronization position is accurate, and if the synchronization position is incorrect, the synchronization position is re-determined.

[0100] In this embodiment of the present application, each state is represented using a rectangle, divided into two parts by a horizontal line within the rectangle, the upper part being the state name and the lower part being the operation to be performed in that state. The state representations are merely examples; this is not limited to the embodiments of the present application. In text descriptions, {} indicates the name of a single state, and [] indicates the name of a register variable. In state diagrams, "+" indicates logical OR, "*" indicates logical AND, "!" indicates logical negation, "<=" indicates that the value of the variable on the right is assigned to the variable on the left, and "+++" indicates that the value of a register variable stored in a register is increased by 1. UCT stands for unconditional transition.

[0101] Figure 8 is a flowchart of a method according to one embodiment of the present application. The method is applied to a communication device in a communication network, specifically a receiver device configured to receive data. The communication device may be various devices that perform FEC, including but not limited to routers, switches, and servers. The method comprises steps 801 to 804.

[0102] Step 801: In response to detecting the start signal, enter the synchronization position determination state.

[0103] In this embodiment, during synchronization position determination, after the [start signal] is detected, an unconditional transition is triggered to enter the {synchronization position determination state}.

[0104] For example, the [start signal] includes a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal. The system reset signal indicates that the part used for decoding in the receiver is being reconfigured. The system start signal indicates that the part used for decoding in the receiver has been activated. For example, the system start signal is detected, for example, when a data sequence is received. The data reception failure signal indicates a decoding failure in the receiver. The resynchronization signal indicates that the synchronization position is being re-determined.

[0105] In this specification, the system reset signal, system start signal, system receive signal, and resynchronization signal are all register variables and are represented as [system reset signal], [system start signal], [system receive signal], and [resynchronization signal], respectively.

[0106] Step 802: The state machine determines the synchronization position within the data sequence in the synchronization position determination state, and the synchronization position indicates the starting position of a codeword within the data sequence.

[0107] A data sequence is received from a transmitter. A data sequence contains multiple bits, each bit being binary data. A data sequence is sometimes called a bit sequence. A data sequence uses linear block coding. When a data sequence is transmitted over a channel, bit errors may exist, and error detection, error correction, and other operations must be performed.

[0108] In this embodiment, the state machine determines the synchronization position within the data sequence in the {synchronization position determination state}, and the synchronization position is the starting position of a codeword within the data sequence.

[0109] Step 803: The state machine enters a lock loss detection state in response to determining the synchronization position.

[0110] The lock loss detection state is a state of the state machine and is represented as {lock loss detection state}.

[0111] Step 804: In the lock loss detection state, the state machine verifies a set of codewords selected based on the synchronization position and updates the synchronization position in response to a verification failure.

[0112] According to the solution of this application, codeword synchronization of the data sequence transmitted by the transmitter can be implemented at the receiver without inserting additional overhead bits into the data sequence, resulting in high synchronization reliability. In addition, after the synchronization position is determined, a lock loss detection mechanism is further used to determine whether the synchronization position is accurate, thereby further improving synchronization reliability.

[0113] In step 802, the synchronization position determination process is specifically as follows:

[0114] N observation bits are selected from the data sequence, and the synchronization position is determined based on the position of the observation bits in the {synchronization position determination state}, where N is an integer greater than or equal to 1. A specific observation bit position may also be the synchronization position. Multiple observation bit selection methods exist. Three possible implementations are provided below.

[0115] In one implementation, N observation bits are selected from the data sequence. If N is greater than 1, the spacing between adjacent observation bits is the same across multiple observation bits.

[0116] In another implementation, the concept of test blocks is introduced in the codeword synchronization process. A test block belongs to a data sequence and contains multiple bits. The length of a test block is the same as the codeword length. Each test block can be thought of as simulating one codeword. If N is greater than 1, N observed bits may be placed in one test block, and the positions of the N observed bits in one test block move sequentially backward. For example, the number of N observed bits is equal to the test block length, in other words, the positions of all bits in a single test block are traversed by traversing the positions of the N observed bits. Since traversing the positions of all bits in a single test block can be considered equivalent to traversing the positions of all bits in a single codeword, the determined synchronization position may be more accurate. However, as the number of observed bits increases, the resources consumed in the codeword synchronization process also increase. As another example, the number of N observed bits is less than the test block length, and one observed bit may be selected for every M bits in the test block, where M is an integer greater than or equal to 1, and M is less than n, where n is the number of bits in the codeword.

[0117] In yet another implementation, the positions of the N observed bits within each test block move sequentially backward. For example, one bit is selected as an observed bit every L*n+M bits, where L is the number of test blocks in the interval, L is an integer greater than or equal to 1, and the test block length is n, i.e., each test block contains n bits. Selecting observed bits in this way results in relatively large spacing between adjacent observed bits and low correlation between observed bits, thereby reducing the impact of burst bit errors and further improving codeword synchronization accuracy. In this specification, the number of observed bits is less than or equal to n. When the number of observed bits is equal to n, the positions of the first bit in each of the multiple test blocks are considered equivalent, and the position of the i-th bit is also considered equivalent. Therefore, when the number of observed bits is equal to n, all equivalent positions can be traversed by traversing the positions of the N observed bits, and as a result, all positions in multiple test blocks can be traversed by traversing the N observed bits, where i is greater than 1 and less than or equal to n.

[0118] For example, the following provides two possible implementations for determining the synchronization position based on the position of the observed bits.

[0119] In one implementation, the synchronization position is selected from the positions of N observed bits.

[0120] In this implementation, the principle for selecting the synchronization position is as follows: a step of sequentially selecting observed bits; a step of sequentially selecting multiple test blocks based on one observed bit selected each time; and a step of determining the position of an observed bit as the synchronization position if all of the multiple test blocks satisfy the verification conditions for a particular observed bit, wherein the positions of the multiple test blocks in the data sequence may be continuous or discontinuous. For ease of explanation, in this implementation, the test blocks are referred to as the first test blocks. The number of test blocks may be determined based on empirical values ​​or based on simulation analysis results. In this embodiment of the present application, a test block satisfying the verification conditions means that the test block is an acceptable block codeword, and a test block not satisfying the verification conditions means that the test block is not an acceptable block codeword. In this specification, a test block is an acceptable block codeword and is considered an acceptable block codeword based on the current verification scheme.

[0121] Specifically, Figure 9 is a diagram illustrating the implementation of codeword synchronization. As shown in Figure 9, the {synchronization position determination state} includes the {first counter reset partial state} and the {first codeword verification partial state}, where the {first counter reset partial state} is the state in which the counter required for the codeword synchronization process has been reset, and the {first codeword verification partial state} is the state in which the test block has been verified. The processing method for selecting the synchronization position based on the positions of N observed bits is as follows.

[0122] The initial value of the [first codeword counter] is set to the {first counter reset partial state}, which can be 0 or another value. One observation bit is selected from the received data sequence, and based on the observation bit, one first test block is selected from the data sequence. The starting position of the first test block and the current position of the observation bit are separated by an integer amount of the codeword length. For the observation bit selection method, please refer to the description above. Details are not described again in this specification.

[0123] In response to selecting one first test block, the {first codeword verification substate} is entered, the first test block is verified in the {first codeword verification substate}, and the count value of the [first codeword counter] is incremented by X in response to the first test block that satisfies the verification condition, where X is a value of 1 or greater.

[0124] The relationship between the count value of the [first codeword counter] and the first threshold is determined, and in response to the count value of the [first codeword counter] being equal to the first threshold, the current position of the observed bit is determined to be the synchronization position.

[0125] If X is equal to 1, the first threshold is the number of first test blocks selected based on the observed bits. If X is greater than 1, the first threshold is X times the number of first test blocks selected based on the observed bits.

[0126] Optionally, in response to the count value of the [first codeword counter] being less than a first threshold, the next first test block is selected based on the currently observed bits, the next first test block is selected from the data sequence based on the currently observed bits, and the next first test block is validated. In this specification, selecting the next first test block based on the currently observed bits means sequentially selecting the first test blocks from the data sequence back and forth. The spacing between adjacent first test blocks may or may not be equal, and the positions of adjacent first test blocks in the data sequence may or may not be adjacent.

[0127] Optionally, the {Synchronization Position Determination State} further includes the {First Codeword Valid Part State}. In response to a first test block that satisfies the verification conditions, the {First Codeword Valid Part State} is entered. In the {First Codeword Valid Part State}, the count value of the [First Codeword Counter] is incremented by X.

[0128] Optionally, the value of [First Codeword Effectiveness Variable] is set to the second value in response to a first test block that satisfies the verification condition, and the {First Codeword Effectiveness Part State} is entered in response to the value of [First Codeword Effectiveness Variable] being the second value.

[0129] Optionally, in response to the first test block failing to satisfy the verification conditions, the next observed bit is selected from the data sequence and verified. The verification method is the same for all observed bits. In this specification, observed bits are selected sequentially; that is, observed bits selected twice consecutively are sequentially moved to the end of the data sequence.

[0130] Optionally, the {Synchronization Position Determination State} further includes a {First Slip Partial State}, which is the state in which an observed bit slips. In response to a first test block that does not satisfy the verification condition, the {First Slip Partial State} is entered. The next observed bit in the data sequence slips into the {First Slip Partial State}. The slip operation may be implemented using a SLIP function. In response to slipping to the next observed bit, the {First Counter Reset Partial State} is entered, and the next observed bit is verified.

[0131] Optionally, the value of [First Slip Completion Variable] is set to true or another value after the next observed bit has slipped, and in response to the value of [First Slip Completion Variable] being true or another value indicating slip completion, the {First Counter Reset Part State} is entered.

[0132] The value of [First Slip Completion Variable] is set to false or another value each time in {First Counter Reset Part State}.

[0133] Optionally, the value of [First Codeword Effectiveness Variable] is set to the first value in response to a first test block that does not satisfy the verification condition, and in response to the value of [First Codeword Effectiveness Variable] being the first value, {First Slip Partial State} is entered.

[0134] Optionally, the {synchronization position determination state} further includes the {first synchronization lock initialization partial state}, and the {first synchronization lock initialization partial state} is the synchronization start state.

[0135] In response to detecting the [start signal], the system enters the {first synchronous lock initialization partial state}, and the value of the [first synchronous lock variable] is set to the first value of the {first synchronous lock initialization partial state}, which may be false, 0, or the like.

[0136] Optionally, after the value of [First Synchronization Lock Variable] is set to the first value in the {First Synchronization Lock Initialization Part-State}, the system enters the {First Counter Reset Part-State} via an unconditional transition.

[0137] Optionally, the value of [First Codeword Variable to Validate] is set to the third value of {First Synchronization Lock Initialization Part-State}, which may be false, 0, etc. The value of [First Codeword Variable to Validate] is set to the fourth value after one first test block has been selected, which may be true, 1, etc. In response to the value of [First Codeword Variable to Validate] being the fourth value and the value of [First Synchronization Lock Variable] being the first value, {First Codeword Validation Part-State} is entered, and the value of [First Codeword Variable to Validate] is set to the third value upon entering {First Codeword Validation Part-State}.

[0138] Optionally, if the {Synchronization Position Determination State} further includes the {First Synchronization Lock Initialization Partial State}, the value of the [First Synchronization Lock Variable] is set to the second value in response to the count value of the [First Codeword Counter] being equal to the first threshold, the second value may be true, 1, etc. If the value of the [First Synchronization Lock Variable] is the second value, it indicates that the current observed bit position is the synchronization position.

[0139] Optionally, if {Synchronization Position Determination State} further includes {First Synchronization Lock Initialization Part State}, then {Synchronization Position Determination State} further includes {First Synchronization Lock Success Part State}, and {First Synchronization Lock Success Part State} is a state in which synchronization is complete.

[0140] In response to the count value of the [first codeword counter] being equal to the first threshold, the {first synchronization lock success partial state} is entered. The value of the [first synchronization lock variable] is set to the second value of the {first synchronization lock success partial state}, which may be true, 1, etc. If the value of the [first synchronization lock variable] is the second value, it indicates that the current observed bit position is the synchronization position.

[0141] Optionally, whether the first test block satisfies the verification conditions is determined by the first test block. characteristics The determination may be based on the value. characteristics The value includes the syndrome, parity bit, or error correction. characteristics If the value is a syndrome, the validation function may be the Computer Syndrome (CAL_SYNDROME) function. characteristics If the value is a reparity bit, the verification function may be the reparity bit comparison (COMPARE_PARITY) function. characteristics If the value is an error correction, the verification function may be the error correction (ERROR_CORRECTION) function. The verification function shown in Figure 9 is the CAL_SYNDROME function.

[0142] For example, the first test block characteristicsIf the value is a syndrome, it is determined whether the number of zero elements in the syndrome is greater than the synchronization threshold. If the number of zero elements is greater than the synchronization threshold, the first test block is determined to satisfy the verification condition, i.e., the first test block is an acceptable block codeword. Otherwise, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword. Alternatively, it is determined whether the number of non-zero elements in the syndrome is less than the asynchronous threshold. If the number of non-zero elements is less than the asynchronous threshold, the first test block is determined to satisfy the verification condition, i.e., the first test block is an acceptable block codeword. Otherwise, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0143] The first test block characteristics If the value is a reparity bit, it is determined whether the reparity bit is the same as the original parity bit. If the reparity bit is the same as the original parity bit, the first test block may be determined to satisfy the verification condition, i.e., the first test block is an acceptable block codeword. Otherwise, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0144] The first test block characteristics If the value is error correction, it is determined whether the first test block can be corrected by the decoding algorithm. If the first test block can be corrected by the decoding algorithm, the first test block may be determined to satisfy the verification condition, i.e., the first test block is an acceptable block codeword. Otherwise, the first test block does not satisfy the verification condition, i.e., the first test block is not an acceptable block codeword.

[0145] It should be noted that each of the three possible verification methods described above can be used for test block verification, or two or all of the three possible verification methods described above can be used for test block verification. In addition, verification may be performed by alternative methods. This is not limited to the embodiments of this application.

[0146] The principle for verifying that the test block satisfies the verification conditions in order to determine the position of the observed bit as the synchronization position is as follows:

[0147] For each linear block codeword, a check matrix can be generated. The check matrix describes the linear relationships between data within the linear block codeword and can be applied to the decoding process. When a data sequence is a linear block codeword, the data sequence also has a check matrix, which is sometimes called the check matrix of the data sequence. For a specific relationship between a data sequence and its check matrix, see equation (1).

number

[0148] In equation (1), C is a codeword in the data sequence, S is the codeword syndrome, and H is the check matrix of the data sequence. From equation (1), it can be seen that the codeword syndrome in the data sequence is obtained by multiplying by the transpose of the check matrix of the data sequence, and that the syndrome is a zero vector.

[0149] When the data sequence is a data sequence received by a receiver, the starting position of the codeword within the data sequence is determined. If a codeword is selected from the data sequence without using the correct starting position, the resulting codeword does not satisfy equation (1). In this case, the codeword syndrome in the data sequence may be expressed by equation (2). S R =R·H T (2)

[0150] In equation (2), R is a codeword in the data sequence received by the receiver, and S R is the codeword syndrome, and H is the check matrix of the original data sequence transmitted by the transmitter. The codeword syndrome in the data sequence received by the receiver is the product of the codeword and the transpose of the check matrix of the original data sequence transmitted by the transmitter. From equations (1) and (2), if the codeword contains an error bit, S R It can be seen that it is not an all-zero matrix. Thus, the syndrome of the first test block in the data sequence received by the receiver can be used to determine whether the first test block satisfies the verification conditions.

[0151] In the state diagram shown in Figure 9, the {first synchronous lock initialization partial state} is represented as FEC_LOCK_INIT_1, the {first counter reset partial state} is represented as RESET_CNT_1, the {first codeword verification partial state} is represented as CW_CHECK_1, the {first slip partial state} is represented as SLIP_1, and the {first synchronous lock success partial state} is represented as FEC_LOCK_GOOD_1. The [first synchronization lock variable] is represented as fec_cw_sync_1, the [first codeword to be validated variable] is represented as test_cw_1, the count value of the [first codeword counter] is represented as cw_cnt_1, the value of the [first codeword validity variable] is represented as valid_cw_1 when set to the second value, the value of the [first codeword validity variable] is represented as !valid_cw_1 when set to the first value, and the [first slip completion variable] is represented as slip_done_1.

[0152] Another principle for selecting the synchronization position is to traverse N observation bits and determine the synchronization position at the positions of the N observation bits. For example, N observation bits are traversed, and test blocks of a fourth threshold are successively selected based on each observation bit, and the number of test blocks that satisfy the verification condition within the test blocks of the fourth threshold is determined, and the positions of the test blocks of the fourth threshold in the data sequence may be continuous or discontinuous. The position of the observation bits corresponding to the maximum number of test blocks that satisfy the verification condition is determined as the synchronization position, or the position of the observation bits corresponding to the minimum number of test blocks that do not satisfy the verification condition is determined as the synchronization position. In this specification, the fourth threshold is a value obtained when W is 1 or less. The fourth threshold may be set based on empirical values ​​or based on simulation analysis results.

[0153] Specifically, for the state diagram used to determine the synchronization position, please refer to the explanation of Figure 11 below. This is equivalent to the signal output in Figure 11 being the second transition signal. The second transition signal is used to trigger the {lock loss detection state}.

[0154] Another principle for selecting a synchronization location is a step of sequentially verifying whether all observation bits satisfy the synchronization condition, starting with the first observation bit, where the synchronization condition may be that at least the sixth threshold test block satisfies the verification condition in a fifth threshold test block sequentially selected based on the observation bits, and the positions of the fifth threshold test blocks in the data sequence may be continuous or discontinuous, and the positions of the sixth threshold test blocks in the data sequence may be continuous or discontinuous; and a step of determining the position of a particular observation bit as the synchronization location if the synchronization condition is met. In this way, the observation bit verification can be completed in advance, thereby saving resources for determining the synchronization location.

[0155] In this specification, the fifth threshold is the value obtained when M is 1 or less, and the sixth threshold is the value obtained when Q is 1 or less. The fifth and sixth thresholds may be set based on empirical values ​​or based on simulation analysis results.

[0156] Specifically, please refer to the explanation of Figure 12 below for the state diagram used to determine the synchronization position. This is equivalent to the signal output in Figure 12 being the second transition signal. The second transition signal is used to trigger the {lock loss detection state}.

[0157] For example, after the synchronization position is determined, the system enters the {lock loss detection state}. Figure 10 is a state diagram in which a state machine implements the codeword synchronization process. In the state diagram shown in Figure 10, the synchronization position determination process and the lock loss detection process share the {first counter reset partial state} and the {first slip partial state}.

[0158] Specifically, referring to Figure 10, the {lock loss detection state} includes the {second codeword verification substate}, which is the state in which the codeword has been verified. In response to the determination of the synchronization position, the system enters the {first counter reset substate}, or enters the {first counter reset substate} unconditionally if the value of the [first synchronization lock variable] is the second value. The {first counter reset substate} is set to the initial values ​​of the [first codeword counter] and the [first invalid codeword counter]. Both initial values ​​may be 0. A codeword is selected from the data sequence based on the synchronization position. For the purposes of this specification, the codeword selected based on the synchronization position is referred to as the first codeword.

[0159] In response to selecting one first codeword, the system enters the {second codeword verification substate}, where the first codeword is verified.

[0160] In response to a first codeword that does not satisfy the verification condition, the count value of the [first codeword counter] is increased by Y, and the count value of the [first invalid codeword counter] is increased by Z, where both Y and Z are integers greater than or equal to 1. If the count value of the [first codeword counter] is less than or equal to the second threshold, in response to the count value of the [first invalid codeword counter] being equal to the third threshold, it is indicated that the number of invalid codewords has reached the number of updated synchronization positions, and the {synchronization position determination state} is re-entered to perform the synchronization position update operation. If Y is equal to 1, the second threshold is the number of first codewords selected based on the synchronization position. If Y is greater than 1, the second threshold is Y times the number of first codewords selected based on the synchronization position. If Z is equal to 1, the third threshold is the number of first codewords that do not satisfy the verification condition. If Z is greater than 1, the third threshold is Z times the number of first codewords that do not satisfy the verification condition. The second and third thresholds may be set based on empirical values ​​or based on simulation analysis results.

[0161] Optionally, whether the first codeword satisfies the verification conditions is determined by the first codeword. characteristics The determination may also be based on the value. For the principle, please refer to equations (1) and (2).

[0162] Optionally, the {lock loss detection state} further includes the {codeword invalid partial state}, which is the state entered when the first codeword does not satisfy the verification condition. In response to the first codeword not satisfying the verification condition, the {codeword invalid partial state} is entered. In the {codeword invalid partial state}, the count value of the [first codeword counter] is increased by Y, and the count value of the [first invalid codeword counter] is increased by Z.

[0163] Optionally, in response to the count value of the [first codeword counter] being less than the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, the {second codeword verification partial state} is re-entered, the next first codeword is selected based on the synchronization position, and the next first codeword is verified. In this specification, the count value of the [first invalid codeword counter] being less than the third threshold indicates that the number of invalid codewords is relatively small, and verification may be performed on the next first codeword.

[0164] Optionally, in response to the count value of the [first codeword counter] being equal to the second threshold and the count value of the [first invalid codeword counter] being less than the third threshold, the {first counter reset partial state} is re-entered and the next verification continues for the synchronization position. In this specification, the number of invalid codewords in the first codewords at the second threshold is relatively small, which indicates that the synchronization position is currently accurate and verification can continue.

[0165] Optionally, the value of [codeword validity variable] is set to the first value in response to a first codeword that does not satisfy the verification condition, and the {codeword invalidity substate} is entered in response to the value of [codeword validity variable] being the first value.

[0166] Optionally, the count value of the [first codeword counter] is incremented by Y in response to a first codeword that satisfies the verification condition, and the {first counter reset partial state} is re-entered in response to the count value of the [first codeword counter] being equal to the second threshold, indicating that the synchronization position is accurate, and the next verification continues to be performed against the synchronization position.

[0167] In response to the count value of the [first codeword counter] being less than the second threshold, the {second codeword verification substate} is re-entered, the next first codeword is selected based on the synchronization position, and the next first codeword is verified.

[0168] Optionally, the {lock loss detection state} further includes the {codeword valid partial state}, which is the state entered when the first codeword satisfies the verification condition. In response to the first codeword satisfying the verification condition, it enters the {codeword valid partial state}.

[0169] Optionally, the value of [codeword validity variable] is set to a second value in response to a first codeword that satisfies the verification condition, and enters {codeword validity partial state} in response to the value of [codeword validity variable] being the second value.

[0170] If, optionally, the {synchronous position determination state} further includes the {first slip partial state}, the process of re-entering the {synchronous position determination state} is the step of entering the {first slip partial state} in response to the count value of the [first invalid codeword counter] being equal to the third threshold, the step of slipping to the next observed bit in the data sequence in the {first slip partial state}, and the step of entering the {first counter reset partial state} in response to slipping to the next observed bit and verifying the next observed bit.

[0171] Optionally, the value of [First Slip Completion Variable] is set to the second value after the next observed bit slips, and in response to the value of [First Slip Completion Variable] being the second value, the {First Counter Reset Part State} is re-entered, in which the value of [First Slip Completion Variable] is set to the first value, and the next observed bit is verified.

[0172] Optionally, the value of [First Codeword to Validate Variable] is set to the fourth value after one first codeword is selected, and in response to the value of [First Codeword to Validate Variable] being the fourth value and the value of [First Synchronization Lock Variable] being the second value, the system enters the {Second Codeword Validation Part-State}, and the value of [First Codeword to Validate Variable] is set to the third value after entering the {Second Codeword Validation Part-State}.

[0173] In the state diagram shown in Figure 10, the {first synchronous lock initialization partial state} is represented as FEC_LOCK_INIT_1, the {first counter reset partial state} is represented as RESET_CNT_1, the {second codeword verification partial state} is represented as CW_CHECK_2, the {codeword valid partial state} is represented as VALID_CW_0, the {first slip partial state} is represented as SLIP_1, the {first synchronous lock success partial state} is represented as FEC_LOCK_GOOD_1, and the {codeword invalid partial state} is represented as INVALID_CW_0. The [first synchronization lock variable] is represented as fec_cw_sync_1, the [first codeword to be validated variable] is represented as test_cw_1, the count value of the [first codeword counter] is represented as cw_cnt_1, the value of the [codeword validity variable] is represented as valid_cw_0 when set to the second value, the value of the [codeword validity variable] is represented as !valid_cw_0 when set to the first value, the count value of the [first invalid codeword counter] is represented as invalid_cw_cnt_1, and the [first slip completion variable] is represented as slip_done_1.

[0174] In the state diagram shown in Figure 10, the first test block selected based on the observed bits belongs to the first subsequence, the first codeword selected based on the synchronization position belongs to the second subsequence, both the first and second subsequences belong to the data sequence, and the second subsequence is placed after the first subsequence.

[0175] In another implementation, N observation bits are selected from the data sequence in the {synchronization position determination state}, where N is 1 or greater, the candidate position is selected from the positions of the N observation bits, and the synchronization position is determined based on the candidate position.

[0176] The candidate location is the place that is most likely to be the synchronization location. The candidate location may be determined to be the synchronization location. Alternatively, several test blocks selected based on the candidate location are validated, and after successful validation, the candidate location is determined to be the synchronization location.

[0177] For example, there are several methods for determining candidate positions. Below, we provide three possible implementations. Please refer to Methods 1 through 3.

[0178] Method 1: Traverse N observed bits and determine candidate positions at the locations of the N observed bits. For example, N observed bits are traversed, and based on each observed bit, test blocks of the fourth threshold are successively selected, the number of test blocks that satisfy the verification condition within the test blocks of the fourth threshold is determined, and the positions of the test blocks of the fourth threshold in the data sequence may be continuous or discontinuous. The position of the observed bit corresponding to the maximum number of test blocks that satisfy the verification condition is determined as a candidate position, or the position of the observed bit corresponding to the minimum number of test blocks that do not satisfy the verification condition is determined as a candidate position. In this way, since N observed bits are traversed, the determined candidate position is most likely to be the synchronization position. In this implementation, the value of N may be the number of bits contained in a single codeword.

[0179] Specifically, referring to the state diagram shown in Figure 11, the {synchronization position determination state} includes the {second counter reset partial state}, the {third codeword verification partial state}, and the {candidate position selection partial state}, where the {second counter reset partial state} is the state in which the counter has been reset, the {third codeword verification partial state} is the state in which the test block has been verified, and the {candidate position selection partial state} is the state in which a candidate position has been selected.

[0180] The {second counter reset partial state} is set to the initial values ​​of the [second codeword counter] and the [first currently active codeword counter], one observation bit is selected from the received data sequence, and one test block is selected from the data sequence based on the current observation bit. For ease of explanation, the selected test block is called the second test block, the length of the second test block is equal to the codeword length, and one second test block simulates one codeword.

[0181] In response to selecting the second test block, the {third codeword verification substate} is entered.

[0182] The second test block is verified in the {third codeword verification substate}. For the verification method, see the verification method described above for the first test block. Details are not described again in this specification. In the {third codeword verification substate}, the count value of the [second codeword counter] is incremented by W. The count value of the [first currently valid codeword counter] is incremented by P in response to the second test block satisfying the verification conditions, where both W and P are integers greater than or equal to 1.

[0183] In response to the count value of the [second codeword counter] being equal to the fourth threshold, the {candidate position selection substate} is entered. In this specification, the count value of the [second codeword counter] is equal to the fourth threshold. If W is equal to 1, it indicates that verification has been performed on the second test block of the fourth threshold corresponding to the current observed bit, and it can be determined whether the position of the current observed bit is a candidate position. If W is greater than 1, it indicates that verification has been performed on multiple second test blocks corresponding to the current observed bit, and it can be determined whether the position of the current observed bit is a candidate position.

[0184] In the {candidate position selection partial state}, the value of the [observation bit count variable] is increased by 1.

[0185] In the {Candidate Position Selection Part State}, if the count value of the [First Currently Active Codeword Counter] is greater than the current value of the [Maximum Active Codeword Count Variable], the value of the [Candidate Synchronization Position Variable] is updated to the position of the currently observed bit, and the value of the [Maximum Active Codeword Count Variable] is updated to the count value of the [First Currently Active Codeword Counter]. If the count value of the [First Currently Active Codeword Counter] is less than the current value of the [Maximum Active Codeword Count Variable], the [Candidate Synchronization Position Variable] is not updated. If the count value of the [First Currently Active Codeword Counter] is equal to the current value of the [Maximum Active Codeword Count Variable], the [Candidate Synchronization Position Variable] may or may not be updated.

[0186] In response to the value of [Number of Observed Bits Variable] being less than N, the next observed bit in the data sequence is validated after the current observed bit. In this specification, the value of [Number of Observed Bits Variable] being less than N indicates that N observed bits have not been fully validated, the next observed bit should be selected, and the next observed bit is validated.

[0187] In response to the value of [Observation Bit Count Variable] being equal to N, the value of [Candidate Synchronization Position Variable] is determined to be a candidate position. Optionally, after the candidate position is determined, a first transition signal may be output. The first transition signal may be a candidate position, or it may be a signal that triggers the next state.

[0188] If the second test block does not satisfy the verification conditions, the relationship between the count value of the [second codeword counter] and the fourth threshold is determined. In response that the count value of the [second codeword counter] is less than the fourth threshold, the next second test block is selected based on the currently observed bits, and the next second test block is verified. In response that the count value of the [second codeword counter] is equal to the fourth threshold, the {candidate position selection substate} is entered.

[0189] Optionally, the {synchronous position determination state} further includes the {second synchronous lock initialization partial state}.

[0190] Before entering the {second counter reset partial state}, the system enters the {second synchronization lock initialization partial state} in response to detecting the [start signal]. In the {second synchronization lock initialization partial state}, the value of the [observed bit count variable] is set to the fifth value, which may be 0; the value of the [candidate synchronization position variable] is set to the sixth value, which may be 0; and the value of the [maximum effective codeword count variable] is set to the seventh value, which may be 0.

[0191] Optionally, after these variables are set, the system enters the {second counter reset partial state} unconditionally.

[0192] Optionally, the value of [Second Synchronization Lock Variable] is set to the first value in {Second Synchronization Lock Initialization Part State}.

[0193] Optionally, in the {second synchronization lock initialization partial state}, the value of the [current position number variable] is set to 0, and in the {candidate position selection partial state}, the value of the [current position number variable] is increased by 1. In this way, the current position variable is recorded, and as a result, the position of the traversed current observation bit can be obtained.

[0194] Optionally, the value of [second codeword variable to be verified] is set to a third value in {second synchronization lock initialization partial state}.

[0195] Optionally, the value of [Second codeword variable to be verified] is set to a fourth value in response to selecting a second test block from the data sequence based on the currently observed bits, the fourth value may be true or another value, and in response to the value of [Second codeword variable to be verified] being the fourth value, the {Third codeword verification substate} is entered, in the {Third codeword verification substate}, in order to verify the second test block, the value of [Second codeword variable to be verified] is set to the third value.

[0196] Optionally, in response to the count value of the [second codeword counter] being less than the fourth threshold and the value of the [second codeword variable to be verified] being the fourth value, the {third codeword verification substate} is re-entered, the next second test block is selected based on the currently observed bits, and the next second test block is verified.

[0197] Optionally, the {Synchronization Position Determination State} further includes a {Second Slip Partial State}, which is a state in which an observed bit slips. In response to the value of [Number of Observed Bits Variable] being less than N, it indicates that N observed bits have not been fully traversed, and the {Second Slip Partial State} is entered. The position of the next observed bit in the data sequence slips into the {Second Slip Partial State}. In response to slipping to the next observed bit, the {Second Counter Reset Partial State} is entered, and the next observed bit is verified. Thus, all observed bits may be traversed, or the most likely candidate position may be selected, so the selected candidate position can be more precise.

[0198] After slipping to the next observed bit, the value of [Second Slip Completion Variable] is set to the second value, which is true or another value. In response to the value of [Second Slip Completion Variable] being the second value, the {Second Counter Reset Part State} is entered and the next observed bit is verified. The value of [Second Slip Completion Variable] is set to the first value of the {Second Counter Reset Part State}, which is false or another value.

[0199] In this specification, all observed bits are verified using the same process. For details on the observed bit selection method, please refer to the previous explanation. Further details are not provided in this specification.

[0200] In the state diagram shown in Figure 11, the {second synchronization lock initialization partial state} is represented as FEC_LOCK_INIT_2, the {second counter reset partial state} is represented as RESET_CNT_2, the {third codeword verification partial state} is represented as CW_CHECK_3, the {candidate position selection partial state} is represented as SELECT_SYNC_LOCK, and the {second slip partial state} is represented as SLIP_2. The second synchronization lock variable is represented as fec_cw_sync_2, the second codeword to be validated variable is represented as test_cw_2, the count value of the second codeword counter is represented as cw_cnt_2, the second slip completion variable is represented as slip_done_2, the observed bit count variable is represented as location_num, the candidate synchronization location variable is represented as sync_location, the maximum valid codeword count variable is represented as max_valid_cw_cnt, the current location count variable is represented as current_location, the count value of the first currently valid codeword counter is represented as current_valid_cw_cnt, "codeword valid" is represented as valid_cw, and "if" indicates a case.

[0201] Method 2: Starting with the first observed bit, all observed bits are sequentially verified to see if they satisfy the synchronization condition. The synchronization condition may be that at least a certain number of test blocks satisfy the verification condition in a series of test blocks selected sequentially based on the observed bits. The positions of the test blocks in the data sequence may be continuous or discontinuous. The positions of a certain number of test blocks in the data sequence may be continuous or discontinuous. If a particular observed bit satisfies the synchronization condition, the position of that observed bit is determined as a candidate location. In this way, the verification of observed bits can be completed in advance, thereby saving resources for determining candidate locations.

[0202] Specifically, referring to the state diagram shown in Figure 12, the {synchronization position determination state} includes the {third counter reset partial state}, the {fourth codeword verification partial state}, and the {second codeword valid partial state}. The {third counter reset partial state} is the state in which the counter has been reset, the {fourth codeword verification partial state} is the state in which the test block has been verified, and the {second codeword valid partial state} is the state entered when the test block satisfies the verification conditions.

[0203] The {third counter reset partial state} is set to the initial values ​​of the [third codeword counter] and the [first effective codeword counter]. One observation bit is selected from the data sequence, and one test block is selected from the data sequence based on the current observation bit. For ease of explanation, the selected test block is called the third test block. The length of the third test block is equal to the codeword length, and the start position of the third test block and the position of the observation bit are separated by an integer amount of the codeword length.

[0204] In response to selecting one third test block, the system enters the {fourth codeword verification substate}. The third test block is verified in the {fourth codeword verification substate}. For example, the third test block is... characteristics It is verified based on the value.

[0205] In response to a third test block that satisfies the verification conditions, the program enters the {second codeword valid partial state}. In the {second codeword valid partial state}, the count value of the [third codeword counter] is increased by M, and the count value of the [first valid codeword counter] is increased by Q, where both M and Q are integers greater than or equal to 1.

[0206] If the count value of the [third codeword counter] is less than or equal to the fifth threshold, the current observed bit position is determined as a candidate position in response to the count value of the [first effective codeword counter] being equal to the sixth threshold. Optionally, after the candidate position is determined, a first transition signal may be output. The first transition signal may be a candidate position or a signal that triggers entry into the next state. If M is equal to 1, the fifth threshold is the number of third test blocks selected based on the observed bits. If M is greater than 1, the fifth threshold is M times the number of third test blocks selected based on the observed bits. If Q is equal to 1, the sixth threshold is the number of third test blocks that satisfy the verification condition. If Q is greater than 1, the sixth threshold is Q times the number of third test blocks that satisfy the verification condition. The fifth and sixth thresholds may be set based on empirical values ​​or based on simulation analysis results.

[0207] Optionally, in {second codeword valid partial state}, in response to the count value of [third codeword counter] being equal to the fifth threshold and the count value of [first valid codeword counter] being less than the sixth threshold, the third test block of the fifth threshold does not contain the third test block of the sixth threshold that satisfies the verification condition, and the next observed bit selected from the data sequence is verified.

[0208] In the {second codeword valid partial state}, in response to the count value of the [third codeword counter] being less than the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold, it is indicated that the third test block of the fifth threshold is not fully verified. Entering the {fourth codeword verification partial state} again, the next third test block selected based on the currently observed bits is verified.

[0209] Optionally, the value of [Second codeword validity variable] is set to the second value in response to a third test block that satisfies the verification condition, and the {Second codeword validity partial state} is entered in response to the value of [Second codeword validity variable] being the second value.

[0210] Optionally, the {Synchronization Position Determination State} further includes the {First Codeword Invalid Part State}, which is the state entered when a test block does not satisfy the verification conditions. In response to a third test block that does not satisfy the verification conditions, the {First Codeword Invalid Part State} is entered, and in the {First Codeword Invalid Part State}, the count value of the [Third Codeword Counter] is increased by M.

[0211] The next observed bit selected from the data sequence is validated in response to the count value of the [third codeword counter] being equal to the fifth threshold. In response to the count value of the [third codeword counter] being less than the fifth threshold, it indicates that the third test block of the fifth threshold is not fully validated. Entering the {fourth codeword validation substate} again, the next third test block selected based on the current observed bit is validated.

[0212] Optionally, the value of [Second codeword validity variable] is set to the first value in response to a third test block that does not satisfy the verification condition, and the {First codeword invalidation substate} is entered in response to the value of [Second codeword validity variable] being the first value.

[0213] Optionally, the {Synchronization Position Determination State} further includes a {Third Slip Partial State}, which is the state in which the next observed bit slips. In response to the count value of the [Third Codeword Counter] being equal to the fifth threshold, the {Third Slip Partial State} enters the {First Codeword Invalid Partial State}. Alternatively, in response to the count value of the [Third Codeword Counter] being equal to the fifth threshold and the count value of the [First Valid Codeword Counter] being less than the sixth threshold, the {Third Slip Partial State} enters the {Second Codeword Valid Partial State}. The next observed bit slips into the {Third Slip Partial State}. In response to slipping to the next observed bit, the {Third Counter Reset Partial State} is entered again, and the next observed bit is verified.

[0214] After slipping to the next observed bit, the value of the [third slip completion variable] is set to the second value, which is true or another value. In response to the value of the [third slip completion variable] being the second value, the {third counter reset partial state} is entered and the next observed bit is verified. The value of the [third slip completion variable] is set to the first value of the {third counter reset partial state}, which is false or another value.

[0215] Optionally, the {synchronous position determination state} further includes the {third synchronous lock initialization partial state}, which is the initialization state. Before entering the {third counter reset partial state}, the {third synchronous lock initialization partial state} is entered in response to the detection of a start signal.

[0216] In the {third synchronization lock initialization partial state}, the value of the [third synchronization lock variable] is set to the first value, and the value of the [third codeword variable to be verified] is set to the third value, which is false or another value. After processing is complete, the {third counter reset partial state} is entered unconditionally. The value of the [third codeword variable to be verified] is set to the fourth value after one third test block is selected based on the currently observed bits, which is true or another value.

[0217] In the {third counter reset substate}, in response to the value of [third codeword variable to be verified] being the fourth value, the {fourth codeword verification substate} is entered.

[0218] In the {second codeword valid partial state}, in response to the value of the [third codeword variable to be verified] being the fourth value, and in response to the count value of the [third codeword counter] being less than the fifth threshold and the count value of the [first valid codeword counter] being less than the sixth threshold, the {fourth codeword verification partial state} is re-entered and the next third test block selected based on the currently observed bits is verified.

[0219] In the {first codeword invalidation substate}, in response to the value of the [third codeword variable to be verified] being the fourth value, and in response to the count value of the [third codeword counter] being less than the fifth threshold, the {fourth codeword verification substate} is re-entered, and the next third test block selected based on the currently observed bits is verified.

[0220] In the procedure shown in Figure 12, all observed bits are verified using the same process. For details on the observed bit selection method, please refer to the previous explanation. Further details are not provided in this specification.

[0221] Method 3: Starting with the first observed bit, all observed bits are sequentially verified to see if they satisfy the synchronization condition. The synchronization condition may be that multiple test blocks selected sequentially based on the observed bits satisfy the verification condition, and the positions of the multiple test blocks in the data sequence may be continuous or discontinuous. If a particular observed bit satisfies the synchronization condition, the position of the observed bit is determined as a candidate location. In this way, the verification of observed bits can be completed in advance, thereby saving resources for determining candidate locations. This implementation is a special example of Method 2.

[0222] Specifically, referring to the state diagram shown in Figure 13, the {synchronization position determination state} includes the {third counter reset partial state}, the {fourth codeword verification partial state}, and the {second codeword valid partial state}.

[0223] The initial value of the third codeword counter is set to {third counter reset partial state}. One observation bit is selected from the data sequence, and one test block is selected from the data sequence based on the current observation bit. For ease of explanation, the selected test block is called the third test block.

[0224] In response to selecting a third test block, the system enters the {fourth codeword verification substate}. The third test block is verified in the {fourth codeword verification substate}. For example, the third test block is verified based on its eigenvalues.

[0225] In response to a third test block that satisfies the verification conditions, the program enters the {second codeword valid partial state}. In the {second codeword valid partial state}, the count value of the [third codeword counter] is incremented by M.

[0226] The current position of the observed bit is determined as a candidate position in response to the count value of the [third codeword counter] being equal to the fifth threshold. Optionally, after a candidate position has been determined, a first transition signal may be output. The first transition signal may be a candidate position or a signal that triggers entry into the next state.

[0227] The next third test block, selected based on the currently observed bit, is verified in response to the count value of the [third codeword counter] being less than the fifth threshold.

[0228] In response to a third test block that does not satisfy the verification conditions, the {third slip substate} is entered. The next observed bit slips into the {third slip substate}. In response to the slip to the next observed bit, the {third counter reset substate} is entered, and the next observed bit is verified.

[0229] Optionally, the value of the [second codeword validity variable] is set to the second value in response to a third test block that satisfies the verification conditions, and the {second codeword validity partial state} is entered in response to the value of the [second codeword validity variable] being the second value. For a detailed explanation of slip, please refer to the explanation in Figure 12.

[0230] Optionally, the {synchronous position determination state} further includes the {third synchronous lock initialization partial state}. See the previous explanation for details. Further details are not provided in this specification.

[0231] In the state diagrams shown in Figures 12 and 13, the {third counter reset partial state} is represented as RESET_CNT_3, the {fourth codeword verification partial state} is represented as CW_CHECK_4, the {third slip partial state} is represented as SLIP_3, the {third synchronization lock initialization partial state} is represented as FEC_LOCK_INIT_3, the {first codeword invalid partial state} is represented as INVALID_CW_1, and the {second codeword valid partial state} is represented as VALID_CW_2. The [third synchronization lock variable] is represented as fec_cw_sync_3, the [third codeword to be validated variable] is represented as test_cw_3, the count value of the [third codeword counter] is represented as cw_cnt_3, the [third slip completion variable] is represented as slip_done_3, the count value of the [first valid codeword counter] is represented as valid_cw_cnt_1, the value of the [second codeword validity variable] is represented as valid_cw_2 when set to the second value, and as !valid_cw_2 when set to the first value.

[0232] For example, after a candidate position is selected, the synchronization position is determined based on that candidate position.

[0233] In the first implementation, which determines the synchronization position based on candidate positions, the candidate positions are determined as synchronization positions. Specifically, the {synchronization position determination state} further includes the {third synchronization lock success partial state}. When a candidate position is determined using method 1, the {third synchronization lock success partial state} is entered in response to the value of the [observed bit count variable] being equal to N. When a candidate position is determined using method 2, the {third synchronization lock success partial state} is entered in response to the count value of the [second effective codeword counter] being equal to the sixth threshold. When a candidate position is determined using method 3, the {third synchronization lock success partial state} is entered in response to the count value of the [third codeword counter] being equal to the fifth threshold. In the {third synchronization lock success partial state}, the value of the [synchronization lock variable] is set to the second value. In the first implementation, which determines the synchronization position based on candidate positions, since the candidate positions are directly determined as synchronization positions, resources for determining the synchronization position can be saved.

[0234] In the second implementation, which determines the synchronization position based on candidate positions, the candidate positions are verified, and after successful verification, they are determined to be the synchronization position.

[0235] Specifically, in one implementation, referring to the state diagram shown in Figure 14, multiple test blocks are selected sequentially based on candidate positions. For the sake of simplicity, the test blocks selected in this implementation are referred to as the fourth test block. If all of the multiple test blocks satisfy the verification conditions, the candidate positions are determined to be synchronous positions, and the positions of the multiple test blocks in the data sequence may be continuous or discontinuous.

[0236] The {synchronization position determination state} further includes the {fourth counter reset substate} and the {fifth codeword verification substate}, where the {fourth counter reset substate} is the state in which the counter has been reset, and the {fifth codeword verification substate} is the state in which the test block has been verified.

[0237] The initial value of the [Fourth Codeword Counter] is set to the {Fourth Counter Reset Part State}. For candidate positions, the [Fourth Codeword Counter] is used to record the number of test blocks selected based on the candidate position. The fourth test block is selected from the data sequence based on the candidate position. In response to selecting one fourth test block, the {Fifth Codeword Verification Part State} is entered.

[0238] The fourth test block is verified in {the fifth codeword verification substate}. For the verification method, please refer to the verification method described above for the first test block. Details are not described again in this specification.

[0239] In response to a fourth test block that satisfies the verification conditions, the count value of the [fourth codeword counter] is incremented by R, where R is an integer greater than or equal to 1. A candidate position is determined to be a synchronization position in response to the count value of the [fourth codeword counter] being equal to the seventh threshold.

[0240] If R is equal to 1, the seventh threshold is the number of fourth test blocks selected based on the candidate positions. If R is greater than 1, the seventh threshold is R times the number of fourth test blocks selected based on the candidate positions. The seventh threshold may be set based on empirical values ​​or based on simulation analysis results.

[0241] Optionally, the synchronization position determination state further includes the {third codeword valid part state}, which is the state entered when a test block satisfies the verification conditions. In response to a fourth test block that satisfies the verification conditions, the state enters the {third codeword valid part state}. In the {third codeword valid part state}, the count value of the [fourth codeword counter] is incremented by R. The candidate position is determined to be a synchronization position in response to the count value of the [fourth codeword counter] being equal to the seventh threshold. In response to the count value of the [fourth codeword counter] being less than the seventh threshold, the state enters the {fifth codeword verification part state} again, and the next fourth test block selected based on the candidate position is verified.

[0242] Optionally, the candidate position is re-selected in response to the fourth test block failing to meet the verification conditions.

[0243] Optionally, the value of [Third Codeword Effectiveness Variable] is set to the second value in response to a fourth test block that satisfies the verification condition, and the second value is true or another value. In response to the value of [Third Codeword Effectiveness Variable] being the second value, the {Third Codeword Effectiveness Partial State} is entered.

[0244] The value of the [third codeword validity variable] is set to the first value in response to the fourth test block not satisfying the verification condition, and the first value is false or another value. The candidate position is reselected in response to the value of the [third codeword validity variable] being the first value.

[0245] Optionally, the {Synchronization Position Determination State} further includes the {First Restart State}. In response to the value of the [Third Codeword Validity Variable] being the first value, the {First Restart State} is entered. In the {First Restart State}, the value of the [Resynchronization Lock Variable] is set to the second value. In response to the value of the [Resynchronization Lock Variable] being the second value, it is determined that a start signal has been detected, and a candidate position is reselected.

[0246] Optionally, the {Synchronization Position Determination State} further includes a {Third Synchronization Lock Success Substate}, which is the state in which the synchronization position is determined. The {Third Synchronization Lock Success Substate} is entered in response to the count value of the [Fourth Codeword Counter] being equal to the seventh threshold. In the {Third Synchronization Lock Success Substate}, the value of the [Third Synchronization Lock Variable] is set to the second value. In response to the value of the [Third Synchronization Lock Variable] being the second value, the state may unconditionally transition and output a second transition signal, indicating that the candidate position is the synchronization position. The second transition signal is used to trigger the {Lock Loss Detection State}, which may be the synchronization position or another trigger signal.

[0247] Optionally, the value of [Fourth Codeword Validation Variable] is set to the second value in response to selecting a fourth test block based on the synchronization position, and the system enters the {Fifth Codeword Validation Substate} in response to the value of [Fourth Codeword Validation Variable] being the second value. Alternatively, the system enters the {Fifth Codeword Validation Substate} in response to the value of [Fourth Codeword Validation Variable] being the second value and the count value of [Fourth Codeword Counter] being less than the seventh threshold. In the {Fifth Codeword Validation Substate}, the value of [Fourth Codeword Validation Variable] is set to the first value.

[0248] In this way, after a candidate position is determined, it is further determined whether that candidate position is a synchronized position, thereby further improving the accuracy of the synchronized position.

[0249] In the state diagram shown in Figure 14, the {third synchronization lock success partial state} is represented as FEC_LOCK_GOOD_3, the {fourth counter reset partial state} is represented as RESET_CNT_4, the {fifth codeword verification partial state} is represented as CW_CHECK_5, the {third codeword valid partial state} is represented as VALID_CW_3, and the {first restart partial state} is represented as RESTART_1. The [third synchronization lock variable] is represented as fec_cw_sync_3, the [fourth codeword to be validated variable] is represented as test_cw_4, the count value of the [fourth codeword counter] is represented as cw_cnt_4, the [resynchronization lock variable] is represented as restart_fec_lock, the value of the [third codeword validity variable] is represented as !valid_cw_3 when it is the first value, and as valid_cw_3 when it is the second value.

[0250] In another implementation, multiple test blocks are selected sequentially based on candidate positions. For ease of explanation, the test blocks selected in this implementation are referred to as the fifth test block. If a certain number of test blocks within a set of test blocks satisfy the verification conditions, the candidate positions are determined to be synchronized positions, and the positions of the multiple test blocks in the data sequence may be continuous or discontinuous, and the positions of a certain number of test blocks in the data sequence may be continuous or discontinuous.

[0251] Specifically, referring to the state diagram shown in Figure 15, the {synchronization position determination state} further includes the {sixth counter reset partial state}, the {seventh codeword verification partial state}, and the {fifth codeword valid partial state}, where the {sixth counter reset partial state} is the state in which the counter has been reset, the {seventh codeword verification partial state} is the state in which the test block has been verified, and the {fifth codeword valid partial state} is the state entered when the test block satisfies the verification conditions.

[0252] The {6th counter reset partial state} is entered when the initial values ​​of the [6th codeword counter] and the [4th valid codeword counter] are set. For candidate positions, the [6th codeword counter] is used to record the number of test blocks selected based on the candidate position, and the [4th valid codeword counter] is used to record the number of test blocks that satisfy the verification conditions. One 5th test block is selected from the data sequence based on the candidate position. In response to selecting one 5th test block, the {7th codeword verification partial state} is entered.

[0253] Optionally, in the {sixth counter reset partial state}, the value of the [fourth slip completion variable] may be further set to the first value to indicate that a slip does not need to be performed at this time.

[0254] The fifth test block is verified in {the seventh codeword verification substate}. For the verification method, please refer to the verification method described above for the first test block. Details are not described again in this specification.

[0255] In response to a fifth test block that satisfies the verification conditions, the system enters the {fifth codeword valid partial state}. In the {fifth codeword valid partial state}, the count value of the [sixth codeword counter] is increased by E, where E is a greater than or equal to 1, and the count value of the [fourth valid codeword counter] is increased by F, where F is a greater than or equal to 1. If the count value of the [sixth codeword counter] is less than or equal to the ninth threshold, the candidate position is determined to be a synchronization position in response to the count value of the [fourth valid codeword counter] being equal to the tenth threshold. The candidate position is reselected in response to the count value of the [sixth codeword counter] being equal to the ninth threshold and the count value of the [fourth valid codeword counter] being less than the tenth threshold. In response to the count value of the [6th codeword counter] being less than the 9th threshold and the count value of the [4th valid codeword counter] being less than the 10th threshold, the {7th codeword verification substate} is re-entered, and the next 5th test block selected based on the candidate position continues to be verified. If E is equal to 1, the 9th threshold is the number of 5th test blocks selected based on the candidate position. If E is greater than 1, the 9th threshold is E times the number of 5th test blocks selected based on the candidate position. If F is equal to 1, the 10th threshold is the number of 5th test blocks that satisfy the verification condition. If F is greater than 1, the 10th threshold is F times the number of 5th test blocks that satisfy the verification condition. The 9th and 10th thresholds may be set based on empirical values ​​or based on simulation analysis results.

[0256] Optionally, the {Synchronization Position Determination State} further includes the {Third Codeword Invalid Part State}, which is the state entered when a test block does not satisfy the verification conditions. In response to a fifth test block that does not satisfy the verification conditions, the {Third Codeword Invalid Part State} is entered. In the {Third Codeword Invalid Part State}, the count value of the [Sixth Codeword Counter] is incremented by E. The candidate position is re-evaluated in response to the count value of the [Sixth Codeword Counter] being equal to the ninth threshold. In response to the count value of the [Sixth Codeword Counter] being less than the ninth threshold, the {Seventh Codeword Verification Part State} is entered again, and the next fifth test block selected based on the candidate position continues to be verified.

[0257] Optionally, the value of [the fourth codeword validity variable] is set to the second value in response to a fifth test block that satisfies the verification condition, and the {fifth codeword validity partial state} is entered in response to the value of [the fourth codeword validity variable] being the second value.

[0258] The value of the [fourth codeword validity variable] is set to the first value in response to a fifth test block that does not satisfy the verification condition, and the {third codeword invalidation substate} is entered in response to the value of the [fourth codeword validity variable] being the first value.

[0259] Optionally, the {Synchronization Position Determination State} further includes the {Second Restart State}, which is a state in which a signal is output to re-determine the candidate position. The {Second Restart State} enters the {Third Codeword Invalid State} in response to the count value of the [Sixth Codeword Counter] being equal to the ninth threshold. Alternatively, the {Second Restart State} enters the {Fifth Codeword Valid State} in response to the count value of the [Sixth Codeword Counter] being equal to the ninth threshold and the count value of the [Fourth Valid Codeword Counter] being less than the tenth threshold. In the {Second Restart State}, the value of the [Resynchronization Lock Variable] is set to the second value. In response to the value of the [Resynchronization Lock Variable] being set to the second value, it is determined that a start signal has been detected and the candidate position is re-selected.

[0260] Optionally, the {Synchronization Position Determination State} further includes the {Fourth Synchronization Lock Success Substate}, which is the state in which synchronization is complete. The {Fourth Synchronization Lock Success Substate} is entered in response to the count value of the [Fourth Effective Codeword Counter] being equal to the tenth threshold. In the {Fourth Synchronization Lock Success Substate}, the value of the [Fourth Synchronization Lock Variable] is set to the second value. The value of the [Fourth Synchronization Lock Variable] being the second value indicates that the candidate position is a synchronized position, and an unconditional transition may occur, outputting the second transition signal. The second transition signal is used to trigger the {Lock Loss Detection State}.

[0261] Optionally, the value of [Fifth Codeword Validation Variable] is set to the second value in response to selecting one fifth test block based on the candidate position, and the system enters {Seventh Codeword Validation Part-State} in response to the value of [Fifth Codeword Validation Variable] being the second value. Alternatively, the system enters {Seventh Codeword Validation Part-State} again in response to the value of [Fifth Codeword Validation Variable] being the second value and the count value of [Sixth Codeword Counter] being less than the ninth threshold. Alternatively, the system enters {Seventh Codeword Validation Part-State} again in response to the value of [Fifth Codeword Validation Variable] being the second value, the count value of [Sixth Codeword Counter] being less than the ninth threshold and the count value of [Fourth Valid Codeword Counter] being less than the tenth threshold. In {Seventh Codeword Validation Part-State}, the value of [Fifth Codeword Validation Variable] is set to the first value.

[0262] In the state diagram shown in Figure 15, the {6th counter reset partial state} is represented as RESET_CNT_6, the {7th codeword verification partial state} is represented as CW_CHECK_7, the {4th synchronization lock success partial state} is represented as FEC_LOCK_GOOD_4, the {5th codeword valid partial state} is represented as VALID_CW_5, the {3rd codeword invalid partial state} is represented as INVALID_CW_3, and the {2nd restart partial state} is represented as RESTART_2. The [fourth synchronization lock variable] is represented as fec_cw_sync_4, the [fifth codeword to be verified variable] is represented as test_cw_5, the count value of the [sixth codeword counter] is represented as cw_cnt_6, the count value of the [fourth valid codeword counter] is represented as valid_cw_cnt_4, the [resynchronization lock variable] is represented as restart_fec_lock, and when the value of the [fourth codeword validity variable] is the first value, it corresponds to !valid_cw_4, and when the value of the [fourth codeword validity variable] is the second value, it corresponds to valid_cw_4.

[0263] In the state diagrams shown in Figures 9 and 11 to 13, the test block selected based on the observed bit belongs to the first subsequence. In the state diagrams shown in Figures 14 and 15, the test block selected based on the candidate position belongs to the third subsequence, both the first and third subsequences belong to the receiving sequence, and the third subsequence is placed after the first subsequence. In addition, the first and third subsequences may alternatively partially overlap.

[0264] In another implementation, the fifth test block of the ninth threshold may be selected sequentially based on candidate positions, the fifth test block of the ninth threshold is traversed, the fifth test block of the tenth threshold within the fifth test block of the ninth threshold satisfies the verification condition, and the candidate position is determined to be the synchronization position.

[0265] For example, in step 804, the system enters the {lock loss detection state} and performs lock loss detection. There are several ways to perform lock loss detection. Below, we provide three possible methods.

[0266] Method 1: In the {lock loss detection state}, multiple codewords selected based on the synchronization position are verified, and in response to the number of codewords that do not satisfy the verification conditions among the multiple codewords reaching a certain value, the system returns to the synchronization position determination state. For example, the target number of codewords is selected sequentially based on the synchronization position, and if the codeword of the eighth threshold among the target number of codewords does not satisfy the verification conditions, the synchronization position is determined to be incorrect and the synchronization position is updated; otherwise, the synchronization position is determined to be correct. When the synchronization position is correct, the number of codewords that do not satisfy the verification conditions is relatively small. Therefore, it is possible to determine whether the number of codewords that do not satisfy the verification conditions has reached the eighth threshold and to determine whether the synchronization position is incorrect more quickly. In this specification, the target number of codewords may be continuous or discontinuous in the data sequence.

[0267] Specifically, referring to the state diagram shown in Figure 16, the {lock loss detection state} includes the {fifth counter reset partial state} and the {sixth codeword verification partial state}, where the {fifth counter reset partial state} is the state in which the counter has been reset, and the {sixth codeword verification partial state} is the state in which the codeword has been verified.

[0268] After the synchronization position is determined, the system enters the {fifth counter reset partial state}. In the {fifth counter reset partial state}, the initial values ​​of the [fifth codeword counter] and the [second invalid codeword counter] are set. In this specification, both initial values ​​may be 0.

[0269] Based on the synchronization position, one codeword is selected from the data sequence. For ease of explanation, the codeword selected based on the synchronization position is called the second codeword. Optionally, one codeword is selected from a fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence differs from both the first and third subsequences described above; the fourth subsequence is placed after the third subsequence.

[0270] In response to selecting a second codeword, the system enters the {sixth codeword verification substate}. The second codeword is verified in the {sixth codeword verification substate}. The verification method for the second codeword is the same as that for the first codeword. Further details are not described herein.

[0271] In accordance with the fact that the second codeword does not satisfy the verification condition, the count value of the [fifth codeword counter] is increased by 1, and the count value of the [second invalid codeword counter] is increased by 1. The next verification is performed on the synchronization position in response to the count value of the [fifth codeword counter] being equal to the target value and the count value of the [second invalid codeword counter] being less than the eighth threshold. In this specification, the fact that the count value of the [fifth codeword counter] is equal to the target value and the count value of the [second invalid codeword counter] is less than the eighth threshold indicates that the number of codewords that do not satisfy the verification condition among the target number of codewords is relatively small, and that the synchronization position is correct.

[0272] The synchronization position of the data sequence is re-determined in response to the count value of the [second invalid codeword counter] being equal to the eighth threshold. In this specification, the count value of the [second invalid codeword counter] being equal to the eighth threshold indicates that there is a relatively large number of codewords that do not satisfy the verification conditions, and that the synchronization position is inaccurate.

[0273] Optionally, the {lock loss detection state} further includes a {second codeword invalid partial state}, which is a state entered when the codeword does not meet the verification condition. In response to the second codeword not meeting the verification condition, the {second codeword invalid partial state} is entered. In the {second codeword invalid partial state}, the count value of the [fifth codeword counter] is incremented by 1, and the count value of the [second invalid codeword counter] is incremented by 1.

[0274] Optionally, in the {second codeword invalid partial state}, in response to the count value of the [fifth codeword counter] being less than the target value and the count value of the [first invalid codeword counter] being less than the eighth threshold value, the {sixth codeword verification partial state} is entered again, and the next second codeword selected based on the synchronization position is verified.

[0275] Optionally, the {lock loss detection state} further includes a {fourth codeword valid partial state}, which is a state entered when the codeword meets the verification condition. In response to the second codeword meeting the verification condition, the {fourth codeword valid partial state} is entered. In the {fourth codeword valid partial state}, the count value of the [fifth codeword counter] is incremented by 1. The next verification is performed for the synchronization position in response to the count value of the [fifth codeword counter] being equal to the target value. The next second codeword selected based on the synchronization position is verified in response to the count value of the [fifth codeword counter] being less than the target value.

[0276] Optionally, the value of the [fifth codeword valid variable] is set to the second value in response to the second codeword meeting the verification condition, and in response to the value of the [fifth codeword valid variable] being the second value, the {fourth codeword valid partial state} is entered.

[0277] The value of the [fifth codeword valid variable] is set to the first value in response to the second codeword meeting the verification condition, and in response to the value of the [fifth codeword valid variable] being the first value, the {second codeword invalid partial state} is entered.

[0278] Optionally, the value of [Sixth Codeword Validation Variable] is set to the second value in response to selecting a second codeword based on the synchronization position, and the system enters the {Sixth Codeword Validation Part-State} in response to the value of [Sixth Codeword Validation Variable] being the second value. Alternatively, in response to the value of [Sixth Codeword Validation Variable] being the second value and the count value of [Fifth Codeword Counter] being less than the target value, the {Sixth Codeword Validation Part-State} returns to the {Fourth Codeword Validation Part-State}. Alternatively, in the {Second Codeword Invalidation Part-State}, in response to the value of [Sixth Codeword Validation Variable] being the second value, the count value of [Fifth Codeword Counter] being less than the target value, and the count value of [Second Invalid Codeword Counter] being less than the eighth threshold, the system returns to the {Sixth Codeword Validation Part-State}. In the {Sixth Codeword Validation Part-State}, the value of [Sixth Codeword Validation Variable] is set to the first value.

[0279] Optionally, the system enters the {fifth counter reset partial state} in response to the value of the [second synchronization lock parameter] being the second value. Alternatively, the system enters the {fifth counter reset partial state} in response to the value of the [third synchronization lock parameter] being the second value. The system enters the {fifth counter reset partial state} in response to the value of the [fourth synchronization lock parameter] being the second value. Alternatively, the system enters the {fifth counter reset partial state} in response to the second transition signal, which is the signal output when position determination is complete.

[0280] Optionally, a third transition signal is output in response to the count value of the [second invalid codeword counter] being equal to the eighth threshold, and the third transition signal indicates that the synchronization position of the data sequence is to be re-determined.

[0281] Optionally, the lock loss detection state further includes a {third restart state}, which is a state in which a signal is output to re-determine the synchronization position. The {third restart state} is entered in response to the count value of the [first invalid codeword counter] being equal to the eighth threshold. In the {third restart state}, the value of the [resynchronization lock variable] is set to the second value. The value of the [resynchronization lock variable] being the second value indicates that the synchronization position is being re-determined.

[0282] In the state diagram shown in Figure 16, the {5th counter reset partial state} is represented as RESET_CNT_5, the {6th codeword verification partial state} is represented as CW_CHECK_6, the {4th codeword valid partial state} is represented as VALID_CW_4, and the {2nd codeword invalid partial state} is represented as INVALID_CW_2. The [6th codeword variable to be verified] is represented as test_cw_6, the count value of the [5th codeword counter] is represented as cw_cnt_5, the count value of the [2nd invalid codeword counter] is represented as invalid_cw_cnt_2, the [resynchronization lock variable] is represented as restart_fec_lock, and when the value of the [5th codeword valid variable] is the first value, it corresponds to !valid_cw_5, and when the value of the [5th codeword valid variable] is the second value, it corresponds to valid_cw_5.

[0283] Method 2: Select a target number of codewords sequentially based on the synchronization position, traverse the target number of codewords, and if the codeword of the 11th threshold among the target number of codewords satisfies the verification condition, the synchronization position is determined to be correct; otherwise, the synchronization position is determined to be incorrect, and the 11th threshold is greater than the 8th threshold.

[0284] Specifically, referring to the state diagram shown in Figure 17, the {lock loss detection state} includes the {seventh counter reset partial state} and the {eighth codeword verification partial state}, where the {seventh counter reset partial state} is the state in which the counter has been reset, and the {eighth codeword verification partial state} is the state in which the codeword is being verified.

[0285] After the synchronization position is determined, the system enters the {seventh counter reset partial state}. In the {seventh counter reset partial state}, the initial values ​​of the [seventh codeword counter] and the [fifth effective codeword counter] are set. In this specification, both initial values ​​may be 0.

[0286] Based on the synchronization position, one codeword is selected from the data sequence. For ease of explanation, the codeword selected based on the synchronization position is called the second codeword. Optionally, one codeword is selected from a fourth subsequence of the data sequence based on the synchronization position. The fourth subsequence differs from both the first and third subsequences described above; the fourth subsequence is placed after the third subsequence.

[0287] In response to selecting a second codeword, the system enters the {eighth codeword verification substate}. In the {eighth codeword verification substate}, the second codeword is verified, and the count value of the [seventh codeword counter] is incremented by 1. The verification method for the second codeword is the same as that for the first test block. Further details are not described herein.

[0288] In the {eighth codeword verification substate}, the count value of the [fifth valid codeword counter] is incremented by 1 in response to a second codeword that satisfies the verification condition.

[0289] The next second codeword, selected based on the synchronization position, is validated in response to the count value of the [seventh codeword counter] being less than the target value.

[0290] The next verification continues for the synchronization position in response to the count value of the [7th codeword counter] being equal to the target value and the count value of the [5th valid codeword counter] being greater than or equal to the 11th threshold.

[0291] A third transition signal is output in response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth effective codeword counter] being less than the eleventh threshold, and the third transition signal indicates that the synchronization position in the data sequence is to be re-determined. Alternatively, the lock loss detection state further includes a {fourth restart partial state}. The {fourth restart partial state} is re-entered in response to the count value of the [seventh codeword counter] being equal to the target value and the count value of the [fifth effective codeword counter] being less than the eleventh threshold. In the {fourth restart partial state}, the value of the [resynchronization lock variable] is set to the second value. The value of the [resynchronization lock variable] being the second value indicates that the synchronization position is to be re-determined.

[0292] Optionally, the value of [7th Codeword Validation Variable] is set to a second value (e.g., true) in response to selecting a second codeword based on the synchronization position, and the system enters {8th Codeword Validation Substate} in response to the value of [7th Codeword Validation Variable] being the second value. Alternatively, the system enters {8th Codeword Validation Substate} again in response to the value of [7th Codeword Validation Variable] being the second value and the count value of [7th Codeword Counter] being less than the target value. In {8th Codeword Validation Substate}, the value of [7th Codeword Validation Variable] is set to a first value (e.g., false).

[0293] In the state diagram shown in Figure 17, the {7th counter reset partial state} is represented as RESET_CNT_7, and the {8th codeword verification partial state} is represented as CW_CHECK_8. The [7th codeword variable to be verified] is represented as test_cw_7, the count value of the [7th codeword counter] is represented as cw_cnt_7, the count value of the [5th valid codeword counter] is represented as valid_cw_cnt_5, and the fact that the second codeword satisfies the verification condition is represented as valid_cw, where "if" indicates a case.

[0294] Method 3: Continuously verify the codewords selected based on the synchronization position, and determine the number of codewords that meet the verification conditions until the maximum number of codewords reaches the target value. In this process, when the number of codewords that meet the verification conditions reaches the 11th threshold value, it is determined that the synchronization position is correct.

[0295] It should be noted that the above-mentioned synchronization position determination process and lock loss detection process may be combined in any manner. In addition, the above-mentioned synchronization position determination and lock loss detection may be implemented using the same state machine. Alternatively, two partial state machines, namely partial state machine 1 and partial state machine 2, are used in the implementation. Partial state machine 1 is used to implement the synchronization position determination process, and partial state machine 2 is used to implement the lock loss detection process. Alternatively, three partial state machines, namely partial state machine 3, partial state machine 4, and partial state machine 5, are used in the implementation. Partial state machine 3 is used to implement the candidate position determination process, partial state machine 4 is used to implement the synchronization position determination process, and partial state machine 5 is used to implement the lock loss detection process.

[0296] For example, FIG. 18 is a state diagram in which one state machine realizes the synchronization position determination process. For the description of the state diagram shown in FIG. 18, refer to the description of the state diagrams shown in FIGS. 13 and 14. Compared with FIGS. 13 and 14, the {third synchronization lock success partial state} is added, which is represented as (FEC_LOCK_GOOD_3), and the {first resume partial state} is replaced by the {third slip partial state}.

[0297] It should be noted that in the state diagram in the present embodiment of the present application, an example where the added value of the register variable is 1 is used.

[0298] Hereinafter, the configuration of the codeword synchronization device will be described.

[0299] Figure 19 is a schematic diagram of the structure of a codeword synchronization device according to an exemplary embodiment of the present application. The device may be implemented as part or as whole through a combination of hardware. The device provided in this embodiment of the present application can implement the procedure of Figure 8 of the embodiment of the present application. The device includes a synchronization position determination module 1910 and a lock loss detection module 1920.

[0300] The synchronized position determination module 1910 is, In response to the start signal, the system enters a synchronized position determination state. In the synchronization position determination state, the synchronization position in the received data sequence is determined, and the synchronization position indicates the starting position of a codeword in the data sequence, which can be specifically used to implement the synchronization position determination function in steps 801 and 802 and to perform the implicit steps included in steps 801 and 802. It is configured in this way.

[0301] In response to determining the synchronization position, the lock loss detection module 1920 enters a lock loss detection state. In the lock loss detection state, multiple codewords selected based on the synchronization position are verified, and in response to verification failure, the system returns to the synchronization position determination state, which can be used to implement the lock loss detection function in steps 803 and 804 and to perform the implicit steps included in steps 803 and 804. It is configured in this way.

[0302] In possible implementations, the synchronous position determination module 1910 is: N observation bits are selected from the data sequence, and the synchronization position is determined based on the positions of the N observation bits in the synchronization position determination state, where N is an integer greater than or equal to 1. It is configured in this way.

[0303] In possible implementations, the synchronization position determination module 1910 is configured to select a synchronization position from the positions of N observed bits.

[0304] In possible implementations, the synchronization position determination state includes a first counter reset substate and a first codeword verification substate.

[0305] The synchronized position determination module 1910 is, In the first counter reset partial state, the initial value of the first codeword counter is set, and one observation bit is selected from the data sequence. A step of entering a first codeword verification substate in response to selecting a first test block from a data sequence based on the currently observed bit, wherein the length of the first test block is equal to the codeword length, and the starting position of the first test block and the position of the currently observed bit are separated by an integer amount of the codeword length. In the first codeword verification substate, the first test block is verified. In response to a first test block that satisfies the verification conditions, the count value of the first codeword counter is incremented by X, where X is an integer greater than or equal to 1. In response to the count value of the first codeword counter being equal to the first threshold, the current position of the observed bit is determined to be the synchronization position. It is configured in this way.

[0306] In possible implementations, the synchronous position determination module 1910 is: In response to the count value of the first codeword counter being less than the first threshold, the first codeword verification substate is re-entered and the next first test block selected based on the currently observed bits is verified. It is further configured in this way.

[0307] In possible implementations, the synchronization position determination state further includes the first codeword valid partial state.

[0308] The synchronous position determination module 1910 enters a first codeword valid part state in response to a first test block that satisfies the verification conditions. In the first codeword valid part state, the count value of the first codeword counter is increased by X. It is further configured in this way.

[0309] In possible implementations, the synchronous position determination module 1910 is: In response to the first test block that does not satisfy the verification conditions, the next observed bit selected from the data sequence is verified. It is further configured in this way.

[0310] In possible implementations, the synchronization position determination state further includes a first slip portion state.

[0311] The synchronous position determination module 1910 enters a first slip portion state in response to a first test block that does not satisfy the verification conditions. In the first slip portion state, slip to the next observed bit, In response to slipping to the next observed bit, the first counter reset partial state is re-entered, and the next observed bit is verified. It is further configured in this way.

[0312] In possible implementations, the synchronization position determination state further includes a first synchronization lock initialization substate.

[0313] The synchronization position determination module 1910 is further configured to set the value of the first synchronization lock variable to a first value in the first synchronization lock initialization partial state, before setting the initial value of the first codeword counter in the first counter reset partial state.

[0314] In possible implementations, the synchronization position determination state further includes a first synchronization lock success partial state.

[0315] The synchronized position determination module 1910 is, In response to the count value of the first codeword counter being equal to the first threshold, the system enters the first synchronization lock success partial state. In the first synchronization lock success partial state, the value of the first synchronization lock variable is set to the second value, and the fact that the value of the first synchronization lock variable is the second value indicates that the current observed bit position is the synchronization position. It is further configured in this way.

[0316] In possible implementations, the synchronous position determination module 1910 is: In the first synchronization lock initialization phase, the value of the first codeword variable to be verified is set to the third value. In response to selecting a first test block from the data sequence based on the currently observed bits, the value of the first codeword variable to be validated is set to the fourth value. In response to the value of the first codeword variable being verified being the fourth value and the value of the first synchronization lock variable being the first value, the system enters the first codeword verification substate. It is further configured in this way.

[0317] In possible implementations, the lock loss detection state includes a second codeword verification substate.

[0318] The lock loss detection module 1920 is, In response to determining the synchronization position, the system re-enters the first counter reset partial state. In response to selecting a first codeword based on the synchronization position, the system enters a second codeword verification substate. The first codeword is verified in the second codeword verification substate. It is configured in this way.

[0319] In possible implementations, the lock loss detection module 1920 is: In the first counter reset state, the initial value of the first codeword counter and the initial value of the first invalid codeword counter are set. It is further configured in this way.

[0320] The lock loss detection module 1920 is, In response to a first codeword that does not satisfy the verification conditions, the count value of the first codeword counter is increased by Y, and the count value of the first invalid codeword counter is increased by Z, where both Y and Z are integers greater than or equal to 1. If the count value of the first codeword counter is less than or equal to the second threshold, and the third threshold is less than the second threshold, the system re-enters the synchronization position determination state in response to the count value of the first invalid codeword counter being equal to the third threshold. It is configured in this way.

[0321] In possible implementations, the synchronization position determination state includes a first slip portion state.

[0322] The lock loss detection module 1920 is, Entering the first slip portion state, In the first slip portion state, slip to the next observed bit, In response to slipping to the next observed bit, the first counter reset partial state is re-entered, and the next observed bit is verified. It is configured in this way.

[0323] In possible implementations, the synchronous position determination module 1910 is: Select candidate positions in the data sequence from the positions of N observed bits. Determine the synchronization position based on the candidate positions. It is configured in this way.

[0324] In possible implementations, N is greater than 1, and the synchronization position determination state includes a second counter reset substate and a third codeword verification substate.

[0325] The synchronized position determination module 1910 is, In the second counter reset partial state, the initial value of the second codeword counter and the initial value of the first currently valid codeword counter are set, and one observation bit is selected from the data sequence. In response to selecting a second test block from the data sequence based on the currently observed bit, a third codeword verification substate is entered, where the length of the second test block is equal to the codeword length, and the starting position of the second test block and the position of the currently observed bit are separated by an integer amount of the codeword length. In the third codeword verification substate, the second test block is verified, and the count value of the second codeword counter is incremented by W, where W is an integer greater than or equal to 1. In response to the second test block that satisfies the verification condition, the count value of the first currently valid codeword counter is incremented by P, where P is an integer greater than or equal to 1. In response to the count value of the second codeword counter being equal to the fourth threshold, and in response to the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword count variable, the value of the observed bit count variable is incremented by 1, the value of the candidate synchronization position variable is updated to the position of the current observed bit, and the current value of the maximum valid codeword count variable is updated to the count value of the first currently valid codeword counter. In response to the value of the observed bit count variable being equal to N, the value of the current candidate synchronization position variable is determined to be the candidate position. It is configured in this way.

[0326] In possible implementations, the synchronized position determination state further includes the candidate position selection state.

[0327] The synchronized position determination module 1910 is, In response to the count value of the second codeword counter being equal to the fourth threshold, the candidate position selection substate is entered. In the candidate position selection partial state, in response to the count value of the second codeword counter being equal to the fourth threshold, and in response to the count value of the first currently valid codeword counter being greater than the current value of the maximum valid codeword count variable, the value of the observed bit count variable is increased by 1, the value of the candidate synchronization position variable is updated to the position of the current observed bit, and the current value of the maximum valid codeword count variable is updated to the count value of the first currently valid codeword counter. It is configured in this way.

[0328] In possible implementations, the synchronous position determination module 1910 is further configured to verify the next observed bit selected from the data sequence in response to the value of the observed bit count variable being less than N.

[0329] In possible implementations, the synchronization position determination state further includes a second slip portion state.

[0330] The synchronized position determination module 1910 is, In response to the observed bit number variable having a value less than N, a second slip substate is entered. In the second slip portion state, slip to the next observed bit, In response to slipping to the next observed bit, the system re-enters the second counter reset partial state and verifies the next observed bit. It is configured in this way.

[0331] In possible implementations, the synchronization position determination state further includes a second synchronization lock initialization substate.

[0332] The synchronized position determination module 1910 is, In the second synchronization lock initialization phase, the value of the observed bit count variable is set to the fifth value, the value of the candidate synchronization position variable is set to the sixth value, and the value of the maximum effective codeword count variable is set to the seventh value. It is further configured in this way.

[0333] In possible implementations, the synchronous position determination module 1910 is: In the second synchronization lock initialization phase, the value of the second codeword variable to be verified is set to the third value. It is further configured in this way.

[0334] The synchronized position determination module 1910 is, In response to selecting a second test block from the data sequence based on the currently observed bits, the value of the second codeword variable to be validated is set to the fourth value. In response to the value of the second codeword variable being verified being the fourth value, the system enters the third codeword verification substate. It is configured in this way.

[0335] In possible implementations, the synchronous position determination module 1910 is: In response to the second codeword counter's count value being less than the fourth threshold, the system re-enters the third codeword verification phase and verifies the next second test block selected based on the currently observed bits. It is further configured in this way.

[0336] In possible implementations, the synchronization position determination state includes a third counter reset substate and a fourth codeword verification substate.

[0337] The synchronized position determination module 1910 is, In the third counter reset partial state, the initial value of the third codeword counter and the initial value of the first effective codeword counter are set, and one observation bit is selected from the data sequence. In response to selecting a third test block from the data sequence based on the currently observed bit, the system enters a fourth codeword verification substate where the length of the third test block is equal to the codeword length, and the starting position of the third test block and the position of the currently observed bit are separated by an integer amount equal to the codeword length. In the fourth codeword verification substate, the third test block is verified. In response to a third test block that satisfies the verification conditions, the count value of the third codeword counter is incremented by M, and the count value of the first valid codeword counter is incremented by Q, where both M and Q are integers greater than or equal to 1. If the count value of the third codeword counter is less than or equal to the fifth threshold, and the fifth threshold is less than or equal to the sixth threshold, then in response to the count value of the first codeword counter being equal to the sixth threshold, the current observed bit position is determined as a candidate position. It is configured in this way.

[0338] In possible implementations, the synchronization position determination state further includes a second codeword valid partial state.

[0339] The synchronized position determination module 1910 is, In response to a third test block that satisfies the verification conditions, the system enters the second codeword valid part state. In the second codeword valid part state, the count value of the third codeword counter is increased by M, and the count value of the first valid codeword counter is increased by Q. It is configured in this way.

[0340] In possible implementations, the synchronous position determination module 1910 is: In the second codeword valid partial state, in response to the count value of the third codeword counter being equal to the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, the next observed bit selected from the data sequence is verified. It is further configured in this way.

[0341] In possible implementations, the synchronous position determination module 1910 is: In the second codeword valid partial state, in response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, the system re-enters the fourth codeword verification partial state and verifies the next third test block selected based on the currently observed bits. It is further configured in this way.

[0342] In possible implementations, the synchronization position determination state further includes a first codeword invalidation substate.

[0343] The synchronized position determination module 1910 is, In response to a third test block that does not satisfy the verification conditions, the system enters the first codeword invalidation state. In the first invalid codeword partial state, the count value of the third codeword counter is increased by M. In response to the count value of the third codeword counter being equal to the fifth threshold, the next observed bit selected from the data sequence is verified. It is further configured in this way.

[0344] In possible implementations, the synchronization position determination module 1910 is further configured to re-enter the fourth codeword verification phase in response to the first codeword invalid phase being less than the fifth threshold of the third codeword counter, and to verify the next third test block selected based on the currently observed bits.

[0345] In possible implementations, the synchronization position determination state further includes a third slip portion state.

[0346] The synchronized position determination module 1910 is, Entering the third slip phase, In the third slip state, slip to the next observed bit, In response to slipping to the next observed bit, the third counter reset partial state is re-entered, and the next observed bit is verified. It is configured in this way.

[0347] In possible implementations, the synchronization position determination state further includes a third synchronization lock initialization substate.

[0348] The synchronized position determination module 1910 is, In the third synchronization lock initialization phase, the value of the third codeword variable to be verified is set to the third value. It is further configured in this way.

[0349] In possible implementations, the synchronous position determination module 1910 is: In response to selecting a third test block from the data sequence based on the currently observed bits, the value of the third codeword variable to be validated is set to the fourth value. In response to the value of the third codeword variable being verified being the fourth value, the system enters the fourth codeword verification substate. It is configured in this way.

[0350] In possible implementations, the synchronous position determination module 1910 is: The system verifies the candidate positions, and if the verification is successful, it determines that the candidate positions are the synchronized positions. It is configured in this way.

[0351] In possible implementations, the synchronization position determination state further includes a fourth counter reset substate and a fifth codeword verification substate.

[0352] The synchronized position determination module 1910 is, In the fourth counter reset partial state, the initial value of the fourth codeword counter is set, and a fourth test block is selected from the data sequence based on the candidate position. In response to selecting a fourth test block from the data sequence based on the candidate position, the system enters a fifth codeword verification substate. In the fifth codeword verification substate, the fourth test block is verified. In response to a fourth test block that satisfies the verification conditions, the count value of the fourth codeword counter is incremented by R, where R is an integer greater than or equal to 1. In response to the count value of the fourth codeword counter being equal to the seventh threshold, the candidate position is determined to be the synchronization position. It is configured in this way.

[0353] In possible implementations, the synchronization position determination state further includes a third codeword valid partial state.

[0354] The synchronized position determination module 1910 is, In response to a fourth test block that satisfies the verification conditions, the system enters the third codeword valid part state. In the third codeword valid part state, the count value of the fourth codeword counter is increased by R. It is configured in this way.

[0355] In possible implementations, the synchronous position determination module 1910 is: In response to the count value of the fourth codeword counter being less than the seventh threshold, the fifth codeword verification phase is re-entered, and the next fourth test block, selected based on the candidate position, is verified. It is further configured in this way.

[0356] In possible implementations, the synchronous position determination module 1910 is: In response to the fourth test block that does not meet the verification conditions, the candidate position is re-selected. It is further configured in this way.

[0357] In possible implementations, the synchronization position determination state further includes a first resynchronization substate.

[0358] The synchronized position determination module 1910 is, In response to a fourth test block that does not meet the verification conditions, the system enters the first resynchronization partial state. In the first resynchronization partial state, the value of the first resynchronization lock variable is set to the second value, and the fact that the value of the first resynchronization lock variable is the second value indicates that a candidate position in the data sequence is being reselected. It is further configured in this way.

[0359] In possible implementations, the synchronization position determination state further includes a second synchronization lock success partial state.

[0360] The synchronized position determination module 1910 is, In response to the count value of the fourth codeword counter being equal to the seventh threshold, the system enters the second synchronization lock success partial state. In the second synchronization lock success partial state, the value of the second synchronization lock variable is set to the second value, and the fact that the value of the second synchronization lock variable is the second value indicates that the candidate position is a synchronization position. It is configured in this way.

[0361] In possible implementations, the synchronous position determination module 1910 is: Determine the candidate position as the synchronization position. It is configured in this way.

[0362] In possible implementations, the lock loss detection module 1920 is: In the lock loss detection state, the system verifies the codewords in the codeword set selected based on the synchronization position. The codeword set contains the target number of codewords, and in response to the number of codewords in the codeword set that do not satisfy the verification conditions reaching an eighth threshold, the system returns to the synchronization position determination state. It is configured in this way.

[0363] In possible implementations, the lock loss detection state includes a fifth counter reset substate and a sixth codeword verification substate.

[0364] The lock loss detection module 1920 is, In the fifth counter reset partial state, the initial value of the fifth codeword counter and the initial value of the second invalid codeword counter are set. In response to selecting a second codeword from the data sequence based on the synchronization position, the system enters a sixth codeword verification substate. In the sixth codeword verification substate, the second codeword is verified. In response to a second codeword that does not satisfy the verification conditions, the count value of the fifth codeword counter is increased by 1, and the count value of the second invalid codeword counter is increased by 1. If the count value of the fifth codeword counter is less than the target value, the system re-enters the synchronization position determination state in response to the count value of the second invalid codeword counter being equal to the eighth threshold. It is configured in this way.

[0365] In possible implementations, the lock loss detection state further includes a second codeword invalidation substate.

[0366] The lock loss detection module 1920 is, In response to a second codeword that does not satisfy the verification conditions, the system enters the second codeword invalidation state. In the second invalid codeword state, the count value of the fifth codeword counter is increased by 1, and the count value of the second invalid codeword counter is increased by 1. It is configured in this way.

[0367] In possible implementations, the lock loss detection module 1920 is: In response to a second codeword that satisfies the verification conditions, the count value of the fifth codeword counter is incremented by 1. In response to the count value of the fifth codeword counter being equal to the target value, the fifth counter reset partial state is re-entered, and the following verification is performed against the synchronization position. It is further configured in this way.

[0368] In possible implementations, the lock loss detection state further includes a fourth codeword valid partial state.

[0369] The lock loss detection module 1920 is, In response to a second codeword that satisfies the verification conditions, the system enters a fourth codeword valid partial state. In the fourth codeword valid part state, the count value of the fifth codeword counter is increased by 1. It is further configured in this way.

[0370] In possible implementations, the lock loss detection module 1920 is: In the fourth codeword validity phase, in response to the count value of the fifth codeword counter being less than the target value, the system re-enters the sixth codeword verification phase and verifies the next second codeword selected based on the synchronization position. It is further configured in this way.

[0371] In possible implementations, the lock loss detection module 1920 is: In the second invalid codeword substate, in response to the count value of the fifth codeword counter being less than the target value and the count value of the second invalid codeword counter being less than the eighth threshold, the system re-enters the sixth codeword verification substate and verifies the next second codeword selected based on the synchronization position. It is further configured in this way.

[0372] In possible implementations, the lock loss detection module 1920 is: In the second invalid codeword partial state, in response to the count value of the fifth codeword counter being equal to the target value and the count value of the second invalid codeword counter being less than the eighth threshold, the system re-enters the fifth counter reset partial state and performs the following verification against the synchronization position. It is further configured in this way.

[0373] In possible implementations, the verification condition is that the number of zero elements in the syndrome of a test block or codeword is greater than the synchronization threshold, or The verification condition is that the number of non-zero elements in the syndrome of the test block or codeword is less than the asynchronous threshold, or The verification conditions are that the test block or codeword is an error correction test block, or The verification condition is that the reparity bit of the test block or codeword is the same as the original parity bit.

[0374] In possible implementations, the start signal may include a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal.

[0375] In possible implementations, the data sequence is a bitstream encoded via FEC.

[0376] The following describes the configuration of the communication device.

[0377] Figure 20 is a diagram of the structure of a communication device according to one embodiment of the present application. Referring to Figure 20, the communication device 2000 is optionally implemented using a general bus architecture. The communication device 2000 includes at least one processor 2001, a communication bus 2002, a memory 2003, and at least one network interface 2004. The communication device with the structure shown in Figure 20 may be a router, switch, or the like described above.

[0378] The processor 2001 is, for example, a central processing unit (CPU), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits configured to implement the solution of this application. For example, the processor 2001 includes an ASIC, a programmable logic device (PLD), or a combination thereof. A PLD is, for example, a complex programmable logic device (CPLD), a field programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0379] The communication bus 2002 is configured to transfer information between the aforementioned components. The communication bus 2002 can be classified into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line represents the bus in Figure 20, but this does not mean that there is only one bus or only one type of bus.

[0380] Memory 2003 is, for example, read-only memory (ROM) or another type of static storage device capable of storing static information and instructions; another example is random access memory (RAM) or another type of dynamic storage device capable of storing information and instructions; another example is electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other compact disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital multipurpose discs, Blu-ray optical discs, etc.), magnetic disk storage media or another magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer. However, it is not limited to these. Memory 2003 may exist independently, for example, and be connected to processor 2001 via communication bus 2002. Alternatively, memory 2003 and processor 2001 may be integrated together.

[0381] Network interface 2004 is a transceiver-type device configured to communicate with another device or communication network. Network interface 2004 may include a wired network interface or a wireless network interface. The wired network interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless network interface may be a wireless local area network (WLAN) interface, a cellular network interface, or a combination thereof, etc.

[0382] In a specific implementation, for example, processor 2001 may include one or more CPUs.

[0383] In a specific implementation, for example, the communication device 2000 may include multiple processors. Each processor may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor as used herein may be one or more devices, circuits, and / or processing cores configured to process data (e.g., computer program instructions).

[0384] Figure 21 is a diagram of another structure of a communication device according to one embodiment of the present application. When the communication device is a forwarding device on a network, such as a router or switch, refer to the device structure diagram shown in Figure 21 for the communication device. Device 2100 includes a main control board and one or more interface boards. The main control board is communicatively connected to the interface boards. The main control board is also called a main processing unit (MPU) or route processor card. The main control board controls and manages each component within device 2100, including route calculation, device management, and function maintenance. Interface boards are also called line processing units (LPUs) or line cards and are configured to transfer data.

[0385] In some embodiments, device 2100 may also include a switching board. The switching board is communicatively connected to a main control board and interface boards. The switching board is configured to transfer data between interface boards. The switching board is sometimes referred to as a switch fabric unit (SFU). The interface board includes a central processing unit, memory, a transfer chip, and a physical interface card (PIC). The central processing unit is communicatively connected to memory, a network processor, and the physical interface card. The memory is configured to store a transfer table. The transfer chip is configured to transfer received data frames based on the transfer table stored in memory. If the destination address of a data frame is an address of device 2100, the data frame is sent to the CPU for processing. If the destination address of a data frame is not an address of device 2100, the next-hop and outbound interfaces corresponding to the destination address are found in the transfer table based on the destination address, and the data frame is transferred to the outbound interface corresponding to the destination address. The transfer chip may be a network processor (NP). A PIC, also known as a subcard, may be implemented on an interface board and is responsible for converting optical or electrical signals into data frames, verifying the validity of the data frames, and then transferring the data frames to a transfer chip for processing.

[0386] In some embodiments, the central processing unit may also perform the functions of a transfer chip, for example, by implementing software transfers based on a general-purpose CPU, and as a result, a transfer chip is not required on the interface board. Communication connections between the main control board, interface board, and switching board may be implemented via a bus. In some embodiments, the transfer chip may be implemented via an ASIC or FPGA.

[0387] Logically, device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board and a central processing unit. The forwarding plane includes components for performing forwarding, such as memory, a PIC, and an NP. The control plane performs functions such as router functions, generates a forwarding table, processes signaling packets and protocol packets, and configures and maintains the status of PE1. The control plane transmits the generated forwarding table to the forwarding plane. On the forwarding plane, the NP looks up the table to forward packets received by the PIC of device 2100 based on the forwarding table delivered by the control plane. The forwarding table delivered by the control plane may be stored in memory. In some embodiments, the control plane and the forwarding plane may be completely separate and not on the same device.

[0388] In certain embodiments, the interface board is configured to receive a data sequence, which includes multiple bits.

[0389] The main control board is configured to determine the synchronization position within the data sequence, which indicates the starting position of a codeword in the data sequence, and to perform lock loss detection. For a detailed explanation of the process, please refer to the description in Figure 8. Further details are not provided herein.

[0390] In possible implementations, an interprocess communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate with each other via the IPC channel.

[0391] One embodiment of this application further provides a chip configured to implement the codeword synchronization method described above.

[0392] One embodiment of the present application further provides a chip system. The chip system includes a cascaded first chip and a second chip. The first chip is configured to implement the codeword synchronization method described above. The second chip is configured to perform codeword synchronization based on AM mode. In other words, the codeword synchronization method in the present application is used for the inner FEC, and the codeword synchronization method based on AM mode is used for the outer FEC.

[0393] In some embodiments provided in this application, it should be understood that the disclosed system architectures, devices, and methods may be implemented in other ways. For example, the embodiments of the described devices are merely examples. For example, the division into modules is merely a division of logical functions, and other divisions may be used in actual implementations. For example, multiple modules or components may be combined or integrated as separate systems, or some features may be ignored or not performed. In addition, the mutual coupling, direct coupling, or communication connection shown or discussed may be implemented through some interfaces. Indirect coupling or communication connection between devices or modules may be implemented electronically, mechanically, or in other forms.

[0394] In this application, terms such as "first" and "second" are used to distinguish the same or similar items that have essentially the same purpose or function. It should be understood that there is no logical or temporal order dependency between "first" and "second," and that the quantity and execution order are not limited. In the following description, terms such as "first" and "second" are used to describe various elements, but it should be further understood that these elements should not be limited by these terms. These terms are simply used to distinguish one element from another. For example, without deviating from the scope of various examples, a first test block may be called a second test block, and similarly, a second test block may be called a first test block. Both the first and second test blocks may be test blocks, or in some cases, they may be separate and different test blocks.

[0395] In this application, the term "at least one" means one or more, and the term "multiple" in this application means two or more.

[0396] The foregoing description is merely an exemplary implementation of the present application and is not intended to limit the scope of protection of this application. Equivalent modifications or substitutions readily conceivable by those skilled in the art within the scope of the art disclosed herein shall be included within the scope of protection of this application. Accordingly, the scope of protection of this application shall be subject to the scope of protection of the claims. [Explanation of symbols]

[0397] 1910 Synchronized position determination module 1920 Lock Loss Detection Module 2000 Communication Devices 2001 Processor 2002 Communications Bus 2003 Memory 2004 Network Interface 2100 devices

Claims

1. A codeword synchronization method, wherein the method is Steps include entering a synchronized position determination state in response to a start signal, The step of selecting a candidate position in the received data sequence in the synchronization position determination state, The aforementioned synchronization position determination state includes a step, which includes a seventh codeword verification substate, After entering the seventh codeword verification phase, the process involves increasing the count value of the sixth codeword counter by E, After entering the seventh codeword verification substate, the step of increasing the count value of the fourth valid codeword counter by F in response to a test block that satisfies the verification conditions, wherein both E and F are integers greater than or equal to 1, and the test block is selected based on the candidate position, A step in which, in response that the count value of the sixth codeword counter is less than or equal to the ninth threshold and the count value of the fourth valid codeword counter is equal to the tenth threshold, the candidate position is determined to be a synchronization position in the data sequence, wherein E is equal to 1, the ninth threshold is the number of test blocks selected based on the candidate position, F is equal to 1, the tenth threshold is the number of test blocks that satisfy the verification condition, and the synchronization position indicates the starting position of a codeword in the data sequence. A codeword synchronization method, including the following.

2. The aforementioned method, A step of determining whether the test block satisfies the verification conditions based on the characteristic values ​​of the test block. The method according to claim 1, further comprising:

3. The method according to claim 2, wherein the characteristic value includes a syndrome.

4. The step of determining whether the test block satisfies the verification conditions based on the characteristic values ​​of the test block is: A step in which it is determined that the test block satisfies the verification condition based on the fact that the syndrome of the test block is a zero vector. The method according to claim 3, including the method described in claim 3.

5. The aforementioned method, In response to the count value of the sixth codeword counter being less than the ninth threshold and the count value of the fourth valid codeword counter being less than the tenth threshold, the seventh codeword verification phase is re-entered to verify the next test block selected based on the candidate position. The method according to claim 1, further comprising:

6. The aforementioned method, Steps to reselect candidate positions in response to the count value of the sixth codeword counter being equal to the ninth threshold and the count value of the fourth valid codeword counter being less than the tenth threshold. The method according to claim 1, further comprising:

7. The synchronization position determination state further includes a sixth counter reset partial state, and the method is After entering the sixth counter reset state, the steps include setting the initial value of the sixth codeword counter and the initial value of the fourth effective codeword counter. The method according to claim 1, further comprising:

8. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: A step of selecting N observation bits from the data sequence, and selecting the synchronization position from the positions of the N observation bits in the synchronization position determination state, wherein N is an integer of 1 or more. The method according to claim 1, including the method described in claim 1.

9. The synchronization position determination state further includes a fourth codeword verification substate, and the step of selecting a candidate position in the received data sequence in the synchronization position determination state is: After entering the fourth codeword verification phase, the process involves increasing the count value of the third codeword counter by M, After entering the fourth codeword verification substate, the step of increasing the count value of the first valid codeword counter by Q in response to a test block that satisfies the verification condition, wherein both M and Q are integers greater than or equal to 1, and the test block is selected based on the currently observed bit, In response to the count value of the third codeword counter being less than or equal to the fifth threshold and the count value of the first effective codeword counter being equal to the sixth threshold, the step of determining the position of the current observed bit as the candidate position, The method according to claim 8, including the method described in claim 8.

10. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: In response to the count value of the third codeword counter being less than the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold, the fourth codeword verification substate is re-entered to verify the next test block selected based on the currently observed bits. The method according to claim 9, further comprising:

11. The step of selecting a candidate position in the received data sequence in the aforementioned synchronization position determination state is: Steps to verify the next observed bit selected from the data sequence in response to the count value of the third codeword counter being equal to the fifth threshold and the count value of the first valid codeword counter being less than the sixth threshold: The method according to claim 9, further comprising:

12. The synchronization position determination state further includes a third counter reset partial state, and the method is After entering the third counter reset state, the step of setting the initial value of the third codeword counter and the initial value of the first effective codeword counter. The method according to claim 11, further comprising:

13. The aforementioned synchronization position determination state further includes a third slip portion state, The step of verifying the next observed bit selected from the aforementioned data sequence is: The step of entering the third slipping state, After entering the third slip portion state, the step of slipping to the next observation bit, In response to slipping to the next observed bit, the third counter reset partial state is re-entered, and the next observed bit is verified. The method according to claim 12, including the method described in claim 12.

14. The method according to claim 9, wherein the test block selected based on the current observed bit belongs to a first subsequence in the data sequence, and the test block selected based on the candidate position belongs to a second subsequence in the data sequence, the second subsequence being positioned after the first subsequence.

15. The aforementioned method, In response to determining the synchronization position, the step is to enter a lock loss detection state, In the lock loss detection state, the steps include verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, re-entering the synchronization position determination state, The method according to claim 1, further comprising:

16. The lock loss detection state includes a sixth codeword verification substate, In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, After entering the sixth codeword verification phase, the step is to increase the count value of the fifth codeword counter by 1, After entering the sixth codeword verification phase, the process includes the step of increasing the count value of the second invalid codeword counter by 1 in response to a codeword that does not satisfy the verification conditions, wherein the codeword is selected based on the synchronization position. The steps include: re-entering the synchronization position determination state in response to the count value of the fifth codeword counter being less than or equal to the target value and the count value of the second effective codeword counter being equal to the eighth threshold; The method according to claim 15, including the method described in claim 15.

17. In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, In response to the count value of the fifth codeword counter being equal to the target value and the count value of the second invalid codeword counter being less than the eighth threshold, the following verification is performed on the synchronization position: The method according to claim 16, further comprising:

18. In the lock loss detection state, the step of verifying a plurality of codewords selected based on the synchronization position, and in response to a verification failure, returning to the synchronization position determination state, Steps to verify the next codeword selected based on the synchronization position in response to the count value of the fifth codeword counter being less than the target value and the count value of the second invalid codeword counter being less than the eighth threshold: The method according to claim 16, further comprising:

19. The lock loss detection state further includes a fifth counter reset partial state, and the method After entering the fifth counter reset state, the step of setting the initial value of the fifth codeword counter and the initial value of the second invalid codeword counter. The method according to claim 16, further comprising:

20. The method according to claim 1, wherein the start signal includes a system reset signal, a system start signal, a data reception failure signal, or a resynchronization signal.

21. The method according to claim 1, wherein the data sequence is a bitstream encoded by forward error correction (FEC).

22. A communication device, wherein the communication device is configured to implement a codeword synchronization method, and the method is Steps include entering a synchronized position determination state in response to a start signal, The step of selecting a candidate position in the received data sequence in the synchronization position determination state, The aforementioned synchronization position determination state includes a step, which includes a seventh codeword verification substate, After entering the seventh codeword verification phase, the process involves increasing the count value of the sixth codeword counter by E, After entering the seventh codeword verification substate, the step of increasing the count value of the fourth valid codeword counter by F in response to a test block that satisfies the verification conditions, wherein both E and F are integers greater than or equal to 1, and the test block is selected based on the candidate position, Steps to determine the candidate position as a synchronization position in the data sequence in response to the count value of the sixth codeword counter being less than or equal to the ninth threshold and the count value of the fourth valid codeword counter being equal to the tenth threshold, wherein E is equal to 1, the ninth threshold is the number of test blocks selected based on the candidate position, F is equal to 1, the tenth threshold is the number of test blocks that satisfy the verification condition, and the synchronization position indicates the starting position of a codeword in the data sequence. Communication devices, including

23. A chip, wherein the chip is configured to implement a codeword synchronization method, and the method is Steps include entering a synchronized position determination state in response to a start signal, The step of selecting a candidate position in the received data sequence in the synchronization position determination state, The aforementioned synchronization position determination state includes a step, which includes a seventh codeword verification substate, After entering the seventh codeword verification phase, the process involves increasing the count value of the sixth codeword counter by E, After entering the seventh codeword verification substate, the step of increasing the count value of the fourth valid codeword counter by F in response to a test block that satisfies the verification conditions, wherein both E and F are integers greater than or equal to 1, and the test block is selected based on the candidate position, Steps to determine the candidate position as a synchronization position in the data sequence in response to the count value of the sixth codeword counter being less than or equal to the ninth threshold and the count value of the fourth valid codeword counter being equal to the tenth threshold, wherein E is equal to 1, the ninth threshold is the number of test blocks selected based on the candidate position, F is equal to 1, the tenth threshold is the number of test blocks that satisfy the verification condition, and the synchronization position indicates the starting position of a codeword in the data sequence. Including, tips.

24. A chip system comprising a first chip and a second chip connected in cascade, The first chip is configured to implement a codeword synchronization method, the method is Steps include entering a synchronized position determination state in response to a start signal, The step of selecting a candidate position in the received data sequence in the synchronization position determination state, The aforementioned synchronization position determination state includes a step, which includes a seventh codeword verification substate, After entering the seventh codeword verification phase, the process involves increasing the count value of the sixth codeword counter by E, After entering the seventh codeword verification substate, the step of increasing the count value of the fourth valid codeword counter by F in response to a test block that satisfies the verification conditions, wherein both E and F are integers greater than or equal to 1, and the test block is selected based on the candidate position, Steps to determine the candidate position as a synchronization position in the data sequence in response to the count value of the sixth codeword counter being less than or equal to the ninth threshold and the count value of the fourth valid codeword counter being equal to the tenth threshold, wherein E is equal to 1, the ninth threshold is the number of test blocks selected based on the candidate position, F is equal to 1, the tenth threshold is the number of test blocks that satisfy the verification condition, and the synchronization position indicates the starting position of a codeword in the data sequence. Includes, The second chip is configured to perform codeword synchronization using the alignment marker AM method. Chip system.

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