Data processing device and control method for data processing device
By employing a data processing device with shared queues managed by a queue selection circuit and a queue management table, packet reordering is prevented and circuit size is minimized, ensuring efficient packet processing across multiple cores.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- エフサステクノロジーズ株式会社
- Filing Date
- 2022-08-08
- Publication Date
- 2026-05-15
AI Technical Summary
As the number of cores in processors increases, packet processing delays occur due to competition among multiple cores sharing a single queue and processing circuit, leading to potential reordering of packets and increased circuit size.
Implementing a data processing device with fewer queues than cores, each core sharing a queue through a queue selection circuit that manages packet storage and processing, ensuring each core's packets are stored and processed in the same queue, using a queue management table to maintain core-queue correspondence.
This approach prevents packet reordering and maintains processing order while keeping circuit size minimal by using shared queues and independent processing circuits, allowing packet overtaking between cores.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a data processing apparatus and a method for controlling the data processing apparatus.
Background Art
[0002] A network device having a first selector that outputs each of a plurality of inputs to any one of a plurality of queues, and a second selector that selects any one of the outputs of the plurality of queues is known (for example, see Patent Document 1). A network device is known that classifies a received packet group according to a predetermined rule, holds it in a queue, and performs a cache miss process only on the first packet held in the queue, thereby causing subsequent packets to hit in the cache (for example, see Patent Document 2). A network device is known that classifies received packets according to priority, stores them in a queue, and determines the timing to send a packet from the queue by a scheduling management means, thereby making it possible to efficiently use a wireless line (for example, see Patent Document 3).
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Patent Document 2
Patent Document 3
Summary of the Invention
Problems to be Solved by the Invention
[0004] For example, a processor with multiple cores, each capable of outputting packets containing a history of its own core's operating status, may have a single queue that commonly holds packets output from multiple cores, and a single processing circuit that processes the packets held in the queue. However, recently, the number of cores installed in processors has tended to increase, and if packets from multiple cores compete, the processing of subsequent packets by the processing circuit may be delayed. This delay in packet processing can be solved by providing a queue and processing circuit for each core, but in this case, the size of the processor's circuitry increases.
[0005] In one aspect, the present invention aims to suppress the reordering of packet processing for each data processing unit through simple control, while keeping the circuit size from increasing. [Means for solving the problem]
[0006] From one perspective, the data processing device includes a plurality of queues, fewer than the number of data processing units, for storing packets output from each of the plurality of data processing units; a queue selection circuit that stores the packets output sequentially from each of the plurality of data processing units into one of the plurality of queues for each data processing unit; and a plurality of processing circuits provided corresponding to the plurality of queues, which sequentially process the packets held in the corresponding queues. [Effects of the Invention]
[0007] While suppressing an increase in circuit size, it is possible to prevent the reordering of packets in each data processing unit through simple control. [Brief explanation of the drawing]
[0008] [Figure 1] Block diagram showing an example of a data processing device in one embodiment. [Figure 2] This figure shows an example of a queue management table. [Figure 3]This diagram illustrates an example of how trace packets are sequentially stored in a queue through the control of the queue selection circuit shown in Figure 1. [Figure 4] Figure 1 is a flowchart showing an example of the operation of the queue selection circuit. [Figure 5] Block diagram of an example of a data processing device in another embodiment. [Figure 6] Figure 5 shows an example of a queue management table. [Figure 7] Figure 5 is an explanatory diagram showing an example of the inflow and outflow of trace packets in the queue. [Figure 8] Figure 5 is a flowchart showing an example of the operation of the queue selection circuit. [Figure 9] Figure 5 is a flowchart showing an example of the operation of the leading packet determination circuit. [Figure 10] An example of another data processing device. (Blockhole.) [Figure 11] This is a block diagram showing another example of a different data processing device. [Modes for carrying out the invention]
[0009] The embodiments will be described below with reference to the drawings.
[0010] Figure 1 shows an example of a data processing device in one embodiment. The data processing device 100 shown in Figure 1 is a processor such as a CPU (Central Processing Unit). The data processing device 100 has n+1 cores 10 (10(0), 10(1), ..., 10(n)), a multiplexer 20, and a queue selection circuit 30. The data processing device 100 also has 4 queues 50 (50(0), 50(1), 50(2), 50(3)) and 4 processing circuits 60 (60(0), 60(1), 60(2), 60(3)). Core 10 is an example of a data processing unit and is an example of a processor core.
[0011] Each core 10 has a function of performing arithmetic processing by executing instructions and tracing the history of the operating status during the execution of the arithmetic processing. For example, the history traced by each core 10 includes a status log, a history log, or both a status log and a history log. Then, each core 10 generates and outputs a trace packet TP (TP0, DP1,..., TPn) including the traced history.
[0012] Although not particularly limited, whether each core 10 is operating normally may be evaluated based on the history included in the trace packet TP. That is, the history may be used for testing or debugging of the core 10. Also, the plurality of cores 10 may generate the trace packet TP during a pre-specified period or while executing a pre-specified instruction group.
[0013] The multiplexer 20 outputs the received trace packet TP to the queue selection circuit 30 in the order in which the trace packets TP are received from the plurality of cores 10. The number of queues 50 is less than the number of cores 10. For this reason, the queues 50 are shared by the plurality of cores 10 under the control of the queue selection circuit 30. By sharing the plurality of queues 50, which are fewer than the number of cores, among the plurality of cores 10, it is possible to reduce the circuit scale of the queues 50 while suppressing queue overflow.
[0014] The queue selection circuit 30 has a queue management table 40. When the queue selection circuit 30 stores the trace packet TP in the queue 50, it stores information indicating the correspondence between the stored queue 50 and the core 10 that is the source of the trace packet TP in the queue management table 40. The queue selection circuit 30 refers to the queue management table 40 and determines the queue 50 in which to store the trace packet TP received from the core 10. The queue selection circuit 30 stores the trace packet TP in the determined queue 50. Examples of the operation of the queue selection circuit 30 are shown in FIGS. 3 and 4.
[0015] The queue management table 40 holds, for each trace packet TP, identification information that identifies the core 10 that output the trace packet TP held in each queue 50. For example, the identification information is the core number. The identification information held in the queue management table 40 is erased under the control of the queue 50 when the corresponding trace packet TP is sent from the queue 50 to the processing circuit 60. The signal line connected from each queue 50 to the queue management table 40 is used to erase the identification information held in the queue management table 40. An example of the queue management table 40 is shown in FIG. 2.
[0016] Each queue 50 has six entries ENT (ENT0 - ENT5) that sequentially hold trace packets TP. For example, each queue 50 is a FIFO (First-In First-Out). Note that the data processing apparatus 100 has four queues 50(0) - 50(3), but the number of queues 50 may be any plurality less than the number of cores 10.
[0017] For example, when the corresponding processing circuit 60 can receive the trace packet TP, the queue 50 sends the oldest trace packet TP among the trace packets TP held in the entry ENT to the processing circuit 60. For example, the oldest trace packet TP is the trace packet TP held in the entry ENT0. The queue 50 erases the identification information of the core 10 that output the trace packet TP sent to the processing circuit 60 from the queue management table 40.
[0018] In FIG. 1, each queue 50 has six entries ENT, but the number of entries ENT may be any plurality. Note that, for simplicity in FIG. 1, it is described that each queue 50 has physical entries ENT0 - ENT5 and the trace packet TP sequentially shifts from the entry ENT5 toward the entry ENT0. However, for example, each queue 50 may be a ring buffer or the like managed by a pointer indicating the position of the entry ENT0.
[0019] Each processing circuit 60 processes the trace packet TP received from the corresponding queue 50. For example, the processing circuit 60 performs the process of converting the destination address of the packets contained in the trace packet TP for each core 10 that issued the trace packet TP.
[0020] For example, in a processor that includes multiple cores, each capable of outputting a packet containing a history of its own core's operating status, and multiple processing circuits that process the packets output from the cores, multiple queues for holding packets may be provided between the cores and the processing circuits. The closer the number of queues and processing circuits are to the number of cores, the higher the packet processing performance, but the larger the circuit size.
[0021] If the number of queues and processing circuits is less than the number of cores, and packets output from one core are stored in multiple queues, there is a risk that the processing order of packets in the processing circuits may be altered. Furthermore, to prevent delays in the processing of packets output from one core due to dependence on the processing of packets output from other cores, it is preferable that packets output from each core be stored in the same queue.
[0022] Figure 2 shows an example of the queue management table 40 in Figure 1. The queue management table 40 has an area for each entry ENT of all queues 50 that holds a usage flag and a core number as queue management information. The queue management information is an example of identification information that identifies the core 10 that issued the trace packet TP. The usage flag indicates whether or not the trace packet TP is held in the entry ENT of the corresponding queue 50.
[0023] The usage flag is set by the queue selection circuit 30 when a trace packet TP is stored in entry ENT. The usage flag is reset by queue 50 when the trace packet TP is sent from entry ENT to processing circuit 60. The core number, when the usage flag is set, indicates the core 10 that output the trace packet TP held in entry ENT of the corresponding queue 50. Core numbers with reset usage flags are invalid and indicate the erased state of queue management information.
[0024] Figure 3 shows an example in which trace packets TP are sequentially stored in queue 50 by the control of the queue selection circuit 30 in Figure 1. In other words, Figure 3 shows an example of a control method for the data processing device 100.
[0025] State (a) through State (o) indicate the holding status of the trace packet TP in each queue 50(0)-50(3). The number at the end of the trace packet TP indicates the core number of the core 10 that output the trace packet TP. Note that in Figure 3, for the sake of simplicity, the operation of sending the trace packet TP from queue 50 to the processing circuit 60 is omitted.
[0026] The numbers in entry ENT indicate the core number that output the trace packet TP, and that the trace packet TP output from the corresponding core 10 is held in entry ENT. Additionally, states (a) through (o) also indicate the state of the queue management table 40. In the initial state (before reaching state (a)), all queues 50 are empty.
[0027] First, in state (a), the queue selection circuit 30 receives trace packet TP0 from core 10(0). The queue selection circuit 30 searches the queue management table 40 and determines that no other trace packet TP0 output from core 10(0) is held in any of the queues 50. In this case, the queue selection circuit 30 stores trace packet TP0 in any queue 50 (in this example, queue 50(0)). For example, the queue selection circuit 30 selects any queue 50 using a random number, or selects the queue 50 with the fewest number of trace packets TP stored in it. The queue selection circuit 30 associates the queue 50 that stores the trace packet TP with entry ENT and stores the core number of the core 10 that issued the trace packet TP in the queue management table 40. Note that storing the core number in the queue management table 40 includes setting the usage flag.
[0028] Next, in state (b), the queue selection circuit 30 receives trace packet TP1 from core 10(1). The queue selection circuit 30 searches the queue management table 40 and determines that no other trace packet TP1 output from core 10(1) is held in any of the queues 50. Therefore, the queue selection circuit 30 stores trace packet TP1 in an empty queue 50(1) that does not hold trace packet TP. The queue selection circuit 30 stores the number of the core 10 that issued the trace packet TP in the queue management table 40, associating it with the queue 50 that stores the trace packet TP and entry ENT. The following description of the queue selection circuit 30's update operation of the queue management table 40 is omitted.
[0029] Next, in state (c), the queue selection circuit 30 receives trace packet TP0 from core 10(0). The queue selection circuit 30 searches the queue management table 40 and determines that other trace packets TP0 output from core 10(0) are held in queue 50(0). In this case, the queue selection circuit 30 stores the newly received trace packet TP0 in queue 50(0), which already contains trace packets TP0 from core 10(0).
[0030] Next, in state (d), the queue selection circuit 30 receives trace packet TP5 from core 10(5). The queue selection circuit 30 refers to the queue management table 40 and, since there is no queue 50 to hold other trace packets TP5 output from core 10(5), it stores trace packet TP5 in an empty queue 50(2), similar to state (b). In state (e), the queue selection circuit 30 also stores trace packet TP2 received from core 10(2) in an empty queue 50(3), similar to state (d).
[0031] Next, in state (f), the queue selection circuit 30 receives trace packet TP1 from core 10(1). The queue selection circuit 30 searches the queue management table 40 and determines that another trace packet TP1 output from core 10(1) is held in queue 50(1). Therefore, the queue selection circuit 30 stores the trace packet TP1 received from core 10(1) in queue 50(1), similar to state (c).
[0032] Next, in state (g), the queue selection circuit 30 receives trace packet TP3 from core 10(3). The queue selection circuit 30 searches the queue management table 40 and determines that no other trace packets TP3 output from core 10(3) are held in any of the queues 50. Therefore, the queue selection circuit 30 stores trace packet TP3 in any of the queues 50, for example. In this example, the queue selection circuit 30 stores trace packet TP3 in queue 50(2), which is one of the two queues 50(2) and 50(3) that have the fewest stored packet TPs.
[0033] Next, in state (h), the queue selection circuit 30 receives trace packet TP5 from core 10(5). The queue selection circuit 30 searches the queue management table 40 and stores the new trace packet TP5 in queue 50(2), which holds other trace packets TP5 output from core 10(5). In state (i), as in states (c) and (h), the queue selection circuit 30 stores the trace packet TP0 newly received from core 10(0) in queue 50(0).
[0034] Next, in state (j), the queue selection circuit 30 receives trace packet TP4 from core 10(4). The queue selection circuit 30 searches the queue management table 40 and determines that no other trace packet TP4 output from core 10(3) is held in any of the queues 50. Therefore, the queue selection circuit 30 stores trace packet TP4 in the queue 50(3) with the fewest stored packet TPs.
[0035] Next, in state (k), the queue selection circuit 30 receives trace packet TP6 from core 10(6). Trace packet TP6 is not held in any of the queues 50. Therefore, the queue selection circuit 30 stores trace packet TP6 in queue 50(1), which is one of the two queues 50(1) and 50(3) that have the fewest stored packet TPs.
[0036] Even when transitioning from state (l) to state (o), the queue selection circuit 30 stores the trace packets TP received from each core 10 into the queue 50, which already holds trace packets TP output from the same core 10.
[0037] For example, in state (o), the trace packets TP output from each core 10 are grouped and held in one of the multiple queues 50. Each of the multiple processing circuits 60 processes the trace packets TP held in the corresponding queue 50 one by one in the order they were held in the queue 50.
[0038] Therefore, while suppressing an increase in the circuit size of the data processing device 100, the processing order of trace packets TP for each core 10 can be prevented from being changed by simple control using the queue selection circuit 30. In addition, since each queue 50 operates independently and sends trace packets TP to the corresponding processing circuit 60, it is possible to overtake trace packets TP between different cores 10.
[0039] Figure 4 shows an example of the operation flow of the queue selection circuit 30 in Figure 1. In other words, Figure 4 shows an example of the control method of the data processing device 100. The operation shown in Figure 4 is performed each time the queue selection circuit 30 receives a trace packet TP from any of the cores 10.
[0040] First, in step S100, the queue selection circuit 30 obtains the number of the core 10 that output the trace packet TP based on the identification information contained in the trace packet TP. Next, in step S102, the queue selection circuit 30 searches the queue management table 40.
[0041] Next, in step S104, the queue selection circuit 30 determines whether there is a queue 50 holding trace packets TP output from core 10 with the core number acquired in step S100. If there is a queue 50 holding trace packets TP from the same core 10, the queue selection circuit 30 executes step S106. If there is no queue 50 holding trace packets TP from the same core, the queue selection circuit 30 executes step S108.
[0042] In step S106, the queue selection circuit 30 selects a queue 50 that holds trace packets TP from the same core 10 and executes step S110. In step S108, the queue selection circuit 30 selects any queue 50 and executes step S110.
[0043] In step S110, the queue selection circuit 30 updates the queue management table 40 according to the queue 50 where the trace packet TP will be stored. For example, the queue selection circuit 30 stores the core number of the core 10 that issued the received trace packet TP in the area of the queue management table 40 corresponding to entry ENT of the queue 50 where the trace packet TP will be stored, and sets the usage flag. Next, in step S112, the queue selection circuit 30 stores the trace packet TP received from the core 10 in the queue 50 selected in step S106 or step S108, and terminates the operation shown in Figure 4.
[0044] In this embodiment, the queue selection circuit 30 stores the trace packets TP received from the cores 10 into one of the queues 50, which is fewer than the number of cores 10, for each core 10. The processing circuits 60, each corresponding to one of the queues 50, sequentially process the trace packets TP held in the queues 50. This suppresses an increase in the circuit size of the data processing device 100, while preventing changes in the processing order of trace packets TP for each core 10 through simple control. Furthermore, since each queue 50 operates independently and sends trace packets TP to the corresponding processing circuit 60, it is possible to allow trace packets TP to overtake each other between different cores 10.
[0045] The queue management table 40 maintains the correspondence between the core 10 that output the trace packet TP and the queue 50 where the trace packet TP is stored. The queue selection circuit 30 refers to the queue management table 40 to determine whether the core 10 that issued the trace packet TP is associated with the queue 50. This allows the simple queue selection circuit 30 to determine the appropriate queue 50 to store each trace packet TP.
[0046] Figure 5 shows an example of a data processing device in another embodiment. Elements identical or similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The data processing device 100A shown in Figure 5 is, for example, a processor such as a CPU. The data processing device 100A has a queue selection circuit 30A instead of the queue selection circuit 30 in Figure 1, and newly includes a leading packet determination circuit 70A.
[0047] The other configurations of the data processing unit 100A are the same as those of the data processing unit 100 in Figure 1. That is, in the data processing unit 100A, as in the data processing unit 100 in Figure 1, the number of queues 50 is less than the number of cores 10, and the queues 50 are shared by multiple cores 10 under the control of the queue selection circuit 30A. The queue selection circuit 30A has a queue management table 40A instead of the queue management table 40 in Figure 1.
[0048] The queue management table 40A maintains a core number for each queue 50 that identifies the core 10 that issued the most recent trace packet TP stored most recently. An example of the queue management table 40A is shown in Figure 6. Hereafter, entry ENT0 will also be referred to as the first entry ENT0.
[0049] In addition to the functions of the queue selection circuit 30 shown in Figure 1, the queue selection circuit 30A has the function of determining whether trace packets TP from a core 10 different from the core 10 that output the received trace packet TP are held in all queues 50. If trace packets TP from a core 10 different from the core 10 that output the received trace packet TP are held in all queues 50, the queue selection circuit 30A stores the synchronization packet S in all queues 50. Note that the update operation of the queue management table 40A by the queue selection circuit 30A is the same as the update operation of the queue management table 40A by the queue selection circuit 30A, except that the configuration of the queue management table 40A is different from the configuration of the queue management table 40. Examples of the operation of the queue selection circuit 30A are shown in Figures 7 and 8.
[0050] The leading packet determination circuit 70A monitors the trace packet TP held by the leading entry ENT0 of each queue 50 and controls the transmission of the trace packet TP to the processing circuit 60. The leading packet determination circuit 70A is an example of a packet transmission circuit that controls the transmission of trace packets TP from each queue 50 to each processing circuit 60.
[0051] The leading packet determination circuit 70A stops the operation of the queue 50 holding the synchronous packet S in its leading entry ENT0 until all leading entries ENT0 hold the synchronous packet S. In other words, the leading packet determination circuit 70A suppresses the transmission of trace packets TP from the queue 50 holding the synchronous packet S in its leading entry ENT0 to the processing circuit 60 until all leading entries ENT0 hold the synchronous packet S. If all leading entries ENT0 of the queue 50 hold the synchronous packet S, the leading packet determination circuit 70A deletes the synchronous packet S held in the entry ENT0. An example of the operation of the leading packet determination circuit 70A is shown in Figure 9.
[0052] Figure 6 shows an example of the queue management table 40A in Figure 5. Detailed explanations of elements identical to those in Figure 2 are omitted. The queue management table 40A has an area for each queue 50 that holds usage flags and core numbers as queue management information. For example, each area of the queue management table 40A holds a core number for each queue 50 that identifies the core 10 that issued the most recent trace packet TP stored most recently. The purpose of the usage flag is the same as that of the usage flag in the queue management table 40 in Figure 2.
[0053] Figure 7 shows an example of the insertion and removal of trace packets TP in queue 50 in Figure 5. In other words, Figure 7 shows an example of the control method of the data processing device 100A. The operation shown in Figure 7 is the same as the operation shown in Figure 3, except that the synchronous packet S is stored in queue 50 and the state of the queue management table 40A is added.
[0054] In the state immediately preceding state (a), two trace packets TP0 output from core 10(0) are stored in queue 50(0), and four trace packets TP1 output from core 10(1) are stored in queue 50(1). Additionally, four trace packets TP output from core 10(3) are stored in queue 50(3). Queue 50(2) is empty and contains no trace packets TP.
[0055] Then, in state (a), the queue selection circuit 30A receives trace packet TP2 from core 10(2). The queue selection circuit 30A searches the queue management table 40A and determines that there is no queue 50 holding any other trace packets TP2 output from core 10(2), the source of trace packet TP2. The queue selection circuit 30A also detects that there is an empty queue 50(2) that does not hold trace packet TP.
[0056] In this case, the queue selection circuit 30A stores the core number "2", which indicates core 10(2), in the area of the queue management table 40A corresponding to queue 50(2). Note that storing the core number in the queue management table 40A includes setting the usage flag. Then, the queue selection circuit 30A stores the trace packet TP2 in queue 50(2). As a result, trace packets TP are stored in all queues 50.
[0057] Next, in state (b), the queue selection circuit 30A receives trace packet TP4 from core 10(4). The queue selection circuit 30A searches the queue management table 40A and determines that trace packets TP from cores 10 different from the core 10(4) that issued trace packet TP4 are held in all queues 50.
[0058] Therefore, the queue selection circuit 30A stores the synchronization packets S in all queues 50. The queue selection circuit 30A also clears the queue management table 40A. As a result, the apparent state of the queues 50 shown in the queue management table 40A is that none of the queues 50 hold trace packets TP.
[0059] The queue selection circuit 30A then stores the trace packet TP4 in one of the queues 50 that appear to be all empty. For example, the queue selection circuit 30A stores the trace packet TP received from core 10(4) in queue 50(0) and stores the core number "4", which indicates core 10(4), in the area of the queue management table 40A corresponding to queue 50(0).
[0060] In this way, the queue selection circuit 30A can use the cleared queue management table 40A to control the storage of trace packet TP4 and subsequent trace packets TP output from the core 10 into one of the queues 50. Furthermore, since the queue management table 40A does not hold information corresponding to entry ENT, each queue 50 does not reset its usage flag when sending trace packet TP to the processing circuit 60. The usage flag is reset by the queue selection circuit 30A when the queue management table 40A is cleared. For this reason, unlike in Figure 1, the signal lines for erasing the core 10's identification information are not wired from each queue 50 to the queue management table 40A. Also, since each queue 50 does not control the queue management table 40A, the circuit size of each queue 50 can be reduced.
[0061] In each of the four queues 50, only one trace packet TP from a single core 10 can be held in the entry ENT separated by the synchronization packet S. This prevents the processing order of trace packets TP held before and after the synchronization packet S from being reversed, and prevents the processing order of trace packets TP output from a single core 10 from being reversed.
[0062] Next, in state (c), the queue selection circuit 30A receives trace packet TP0 from core 10(0). The queue selection circuit 30A searches the queue management table 40A and determines that no other trace packet TP0 output from core 10(0) is held in any of the queues 50. Therefore, the queue selection circuit 30A stores trace packet TP0 in the empty queue 50(2), which does not appear to hold trace packet TP0. Then, the queue selection circuit 30A stores the core number "0", which indicates core 10(0), in the area of the queue management table 40A corresponding to queue 50(2).
[0063] Subsequently, trace packets TP1, which were held in entries ENT0 and ENT1 of queue 50(1), are sequentially sent to the corresponding processing circuits 60 and processed by the processing circuits 60. Similarly, trace packets TP3, which were held in entries ENT0-ENT3 of queue 50(3), are sequentially sent to the corresponding processing circuits 60 and processed by the processing circuits 60.
[0064] As a result, in state (d), queue 50(1) holds trace packet TP1 in entries ENT0 and ENT1, and queue 50(3) holds synchronization packet S in entry ENT0. The leading packet determination circuit 70A stops the operation of queue 50(3) until synchronization packet S is held in entry ENT0 of all queues 50. Therefore, the synchronization packet S of queue 50(3) is held in entry ENT0 without being erased, and the transmission of trace packet TP, which is stored after the synchronization packet S, to the processing circuit 60 is suppressed.
[0065] In state (d), the queue selection circuit 30A receives trace packet TP2 from core 10(2). The queue selection circuit 30A searches the queue management table 40A and determines that no other trace packet TP2 output from core 10(2) is held in any of the queues 50. Therefore, the queue selection circuit 30A stores trace packet TP2 in the seemingly empty queue 50(3), which does not hold trace packet TP2. Then, the queue selection circuit 30A stores the core number "2", which indicates core 10(2), in the area of the queue management table 40A corresponding to queue 50(3).
[0066] In this state, trace packet TP2 is held in entries ENT0 and ENT1 of queue 50(2) and entry ENT1 of queue 50(3). However, because the operation of queue 50(3) is stopped, it is possible to prevent trace packet TP2 held in queue 50(3) from being processed ahead of trace packet TP held in queue 50(2).
[0067] Next, in state (e), the queue selection circuit 30A receives trace packet TP3 from core 10(3). Similar to state (c), the queue selection circuit 30A stores trace packet TP3 in an empty queue 50(1) that does not appear to hold trace packet TP3. Then, the queue selection circuit 30A stores the core number "3", indicating core 10(3), in the area of the queue management table 40A corresponding to queue 50(1). As a result, in all queues 50, trace packet TP is held in the entry ENT after the entry ENT where the synchronization packet S is held.
[0068] Next, in state (f), the queue selection circuit 30A receives trace packet TP1 from core 10(1). The queue selection circuit 30A searches the queue management table 40A and determines that trace packets TP from cores different from the core 10(1) that issued trace packet TP1 are seemingly held in all queues 50.
[0069] Therefore, the queue selection circuit 30A stores the synchronization packet S in all queues 50, similar to state (b), and clears the queue management table 40A. As a result, the apparent state of the queues 50 shown in the queue management table 40A becomes one in which no trace packet TP is held in any of the queues 50.
[0070] Then, the queue selection circuit 30A stores the trace packet TP1 in queue 50(3) among the queues 50 which appear to be all empty, and stores the core number "1" indicating core 10(1) in the area of the queue management table 40A corresponding to queue 50(3).
[0071] As shown in state (f), even when multiple synchronization packets S are held in each queue 50, each queue 50 can hold only one trace packet TP from a single core 10 in the entry ENT separated by the synchronization packets S. By making it possible to hold multiple synchronization packets S in the multiple entries ENT of each queue 50, it is possible to prevent the processing order of trace packets TP output from a single core 10 from being changed.
[0072] Subsequently, trace packets TP0, which were held in entries ENT0 and ENT1 of queue 50(0), are sequentially sent to the corresponding processing circuits 60 and processed by the processing circuits 60. Trace packets TP1, which were held in entries ENT0 and ENT1 of queue 50(1), are sequentially sent to the corresponding processing circuits 60 and processed by the processing circuits 60. Also, trace packets TP2, which were held in entries ENT0 and ENT1 of queue 50(2), are sequentially sent to the corresponding processing circuits 60 and processed by the processing circuits 60. Then, the state of queue 50 becomes state (g).
[0073] Trace packet TP2 held in entry ENT1 of queue 50(3) is prevented from being sent to processing circuit 60 by synchronization packet S held in entry ENT0. This prevents trace packet TP2 held in queue 50(3) from being processed ahead of trace packet TP2 held in queue 50(2).
[0074] As shown in state (g), all waiting queues 50 are in a state where they are holding the synchronous packet S in entry ENT0. Therefore, the leading packet determination circuit 70A deletes the synchronous packet S held in entry ENT0 of each queue 50.
[0075] Next, in state (h), the queue selection circuit 30A receives trace packet TP2 from core 10(2). The queue selection circuit 30A refers to the queue management table 40A and determines that no other trace packet TP2 output from core 10(2) is apparently held in any of the queues 50. Therefore, the queue selection circuit 30A stores trace packet TP2 in the empty queue 50(1), which does not appear to hold trace packet TP2. Then, the queue selection circuit 30A stores the core number "2", which indicates core 10(2), in the area of the queue management table 40A corresponding to queue 50(1).
[0076] Next, in state (i), the queue selection circuit 30A receives trace packet TP3 from core 10(3). The queue selection circuit 30A refers to the queue management table 40A and determines that no other trace packet TP3 output from core 10(3) is apparently held in any of the queues 50. Therefore, the queue selection circuit 30A stores trace packet TP3 in the empty queue 50(0), which does not appear to hold trace packet TP3. Then, the queue selection circuit 30A stores the core number "3", which indicates core 10(3), in the area of the queue management table 40A corresponding to queue 50(0).
[0077] Figure 8 shows an example of the operation flow of the queue selection circuit 30A in Figure 5. In other words, Figure 8 shows an example of the control method of the data processing device 100A. Detailed explanations of operations that are the same as or similar to those in Figure 4 are omitted. The operations shown in Figure 8 are performed each time the queue selection circuit 30A receives a trace packet TP from any of the cores 10. The operations of steps S200, S202, S204, S206, S216, and S218 are the same as the operations of steps S100, S102, S104, S106, S110, and S112 in Figure 4, respectively.
[0078] First, in step S200, the queue selection circuit 30A obtains the number of the core 10 that output the trace packet TP based on the identification information contained in the trace packet TP. Next, in step S202, the queue selection circuit 30A searches the queue management table 40A. Here, the queue management information held in the queue management table 40A indicates not only the actual state of the queue 50, but also the apparent state of the queue 50 due to the queue 50 holding the synchronization packet S. Therefore, steps S204 and S208 are determined based on the actual state of the queue 50 or the apparent state of the queue 50.
[0079] In step S204, if there is a queue 50 holding a trace packet TP output from core 10 with the core number acquired in step S200, the queue selection circuit 30A executes step S206. If there is no queue 50 holding a trace packet TP output from core 10 with the core number acquired in step S200, the queue selection circuit 30A executes step S208.
[0080] In step S208, the queue selection circuit 30A determines, based on the search results of the queue management table 40A, whether or not there is an empty queue 50 that does not store trace packets TP. If there is an empty queue 50, the queue selection circuit 30A executes step S214; otherwise, it executes step S210.
[0081] In step S210, the queue selection circuit 30A stores the synchronous packets S in all queues 50. Next, in step S212, the queue selection circuit 30A clears the queue management table 40A and executes step S214.
[0082] In step S214, the queue selection circuit 30A selects any available queue 50. After steps S206 and S214, in step S216, the queue selection circuit 30A updates the queue management table 40A. Then, in step S218, the queue selection circuit 30A stores the trace packet TP received from the core 10 in the queue 50 selected in step S206 or step S214, and terminates the operation shown in Figure 8.
[0083] Figure 9 shows an example of the operation flow of the leading packet determination circuit 70A in Figure 5. In other words, Figure 9 shows an example of the control method of the data processing device 100A. The operation shown in Figure 9 is performed for each queue 50.
[0084] First, in step S300, the leading packet determination circuit 70A acquires a packet from the leading entry ENT0 of queue 50. The packet acquired by the leading packet determination circuit 70A is either a trace packet TP or a synchronous packet S.
[0085] Next, in step S302, the leading packet determination circuit 70A determines whether the packet acquired in step S300 is a synchronous packet S. If the acquired packet is a synchronous packet S, the leading packet determination circuit 70A executes step S304. If the acquired packet is not a synchronous packet S, i.e., it is a trace packet TP, the leading packet determination circuit 70A executes step S308.
[0086] In step S304, the leading packet determination circuit 70A determines whether the leading entry ENT0 of all queues 50 holds the synchronous packet S. If all leading entries ENT0 hold the synchronous packet S, the leading packet determination circuit 70A executes step S306. If at least one of the leading entries ENT0 of all queues 50 does not hold the synchronous packet S, the leading packet determination circuit 70A terminates the operation shown in Figure 9.
[0087] In step S306, the leading packet determination circuit 70A deletes the synchronization packets S held in the leading entry ENT0 of all queues 50. Meanwhile, in step S308, the leading packet determination circuit 70A sends the trace packet TP held in the leading entry ENT0 to the corresponding processing circuit 60, and terminates the operation shown in Figure 9.
[0088] As described above, this embodiment also provides the same effects as the embodiments described above. For example, while suppressing an increase in the circuit size of the data processing device 100A, it is possible to suppress the reordering of the trace packet TP for each core 10 with simple control. In addition, since each queue 50 operates independently and sends trace packet TP to the corresponding processing circuit 60, it is possible to enable the overtaking of trace packet TP between different cores 10.
[0089] Furthermore, in this embodiment, the queue selection circuit 30A inserts a synchronization packet S into all queues 50 if trace packets TP from a different core 10 than the issuer of the trace packet TP are held in each queue 50. This ensures that each entry ENT separated by the synchronization packet S holds only trace packets TP from one core 10. By holding information for one entry ENT per queue 50, it is possible to control the queues 50 in a way that prevents the reordering of the trace packet TP processing. In other words, the increase in the circuit size of the data processing device 100A can be further suppressed, and the reordering of the trace packet TP for each core 10 can be suppressed with simple control.
[0090] When the queue selection circuit 30A inserts a synchronization packet S into all queues 50, it erases the core number held in the queue management table 40A corresponding to each queue 50. The queue selection circuit 30A then treats any trace packets TP stored in a queue 50 before the synchronization packet S is stored as non-existent. As a result, the queue management table 40A can show not only the actual state of the queues 50, but also the apparent state of the queues 50, which hides the existence of trace packets TP stored before the synchronization packet S.
[0091] The leading packet determination circuit 70A stops the operation of the queue 50 holding the synchronous packet S in the leading entry ENT0 until all entries ENT0 hold the synchronous packet S.
[0092] This prevents trace packets TP stored in queue 50 later than synchronous packets S from being sent to the processing circuit 60 before trace packets TP stored in queue 50 earlier than synchronous packets S. For example, even if multiple trace packets TP output from one core 10 are stored before a synchronous packet S in one queue 50 and after a synchronous packet S in another queue 50, it is possible to prevent the processing order of the trace packets TP from changing for each core 10.
[0093] Figure 10 is a block diagram showing an example of another data processing device. Elements identical or similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The data processing device 200 shown in Figure 10 has n+1 cores 10(0)-10(n), a multiplexer 20, one queue 50, one processing circuit 62, and an address translation table 80. The processing circuit 62 includes an address translation circuit 64. The processing circuit 62 is connected to a memory 90 located outside the data processing device 200.
[0094] The data processing device 200 sequentially stores trace packets TP output from multiple cores 10 into a single queue 50 via a multiplexer 20. For example, trace packets TP output from different cores 10 are sequentially stored in queue 50. Queue 50 then sequentially outputs the held trace packets TP to the processing circuit 62.
[0095] The address translation circuit 64 uses the address translation table 80 to translate the destination address of a packet contained in a trace packet TP to another destination address. For example, the addresses translated by the address translation circuit 64 differ for each core 10, and the contents of the address translation table 80 used by the address translation circuit 64 also differ for each core 10. Therefore, if the address translation table 80 is stored in a cache, a cache miss occurs each time a trace packet TP from a different core 10 is processed, and the address translation table 80 is read from memory 90 or the like each time.
[0096] As shown in Figure 10, when trace packets TP output from multiple cores 10 are stored in a single queue 50 and processed by a single processing circuit 62, the frequency of trace packet TP conflicts increases compared to when there are multiple queues 50. As a result, the likelihood of trace packets TP output from a single core 10 being stored consecutively in queue 50 decreases, and the frequency of the address translation table 80 being updated to match the core 10 that issued the trace packet TP to be processed by the processing circuit 62 increases.
[0097] While the address translation table 80 is being updated, the processing circuit 62 does not process trace packets TP. As a result, the processing time in the processing circuit 62 increases, and the processing performance of trace packets TP decreases. Furthermore, when the processing performance of trace packets TP decreases, the frequency of sending trace packets TP from queue 50 decreases, which may cause queue 50 to overflow.
[0098] Figure 11 shows another example of a data processing device. Elements identical or similar to those in Figure 1 are denoted by the same reference numerals, and detailed descriptions are omitted. The data processing device 200A shown in Figure 11 has four cores 10(0)-10(3), four queues 50(0)-50(3), and four processing circuits 60(0)-60(3). That is, a queue 50 and a processing circuit 60 are provided for each core 10.
[0099] In the data processing device 200A, a dedicated queue 50 is provided for each core 10, so trace packets TP output from one core 10 do not conflict with trace packets TP output from other cores 10. Also, since a dedicated processing circuit 60 is provided for each core 10, when performing address translation of trace packets TP, no swapping of the address translation table (not shown) occurs.
[0100] However, if a queue 50 and a processing circuit 60 are provided for each core 10, the circuit size increases in a data processing device 200A containing a large number of cores 10. For this reason, for example, if the data processing device 200A is on a single chip, it may be difficult to mount all the circuits on the chip. In addition, an increase in chip size may lead to a decrease in yield.
[0101] The data processing device 100 shown in Figure 1 and the data processing device shown in Figure 5 can solve the problems described in Figures 10 and 11. In the embodiments described above, the case in which the data processing devices 100 and 100A are processors having multiple cores 10 was described. However, the data processing device 100 may also be a device having multiple I / O (Input / Output) devices.
[0102] In this case, instead of the core 10 in Figure 1 or Figure 5, an I / O device that outputs trace packets TP may be placed. For example, the I / O device may be a non-volatile storage device or various sensors. Also, the data processing devices 100 and 100A may be other than the core 10 or I / O devices, as long as they include a device that outputs trace packets TP.
[0103] The features and advantages of the embodiments will become clear from the detailed description above. This is intended to be so as not to deviate from the spirit and scope of the claims, that the features and advantages of the embodiments described above are included. Furthermore, any improvement and modification should be readily conceivable to a person with ordinary skill in the art. Therefore, there is no intention to limit the scope of inventive embodiments to those described above, and it is also possible to rely on appropriate improvements and equivalents that fall within the scope disclosed in the embodiments. [Explanation of Symbols]
[0104] 10 cores 20 Multiplexer 30, 30A Queue Selection Circuit 40, 40A Queue Management Table 50 cues 60 Processing Circuits 62 Processing Circuits 64 Address Translation Circuits 70A First packet determination circuit 80 Address Translation Table 90 memory 100, 100A Data Processing Device 200, 200A Data Processing Unit ENT entry TP trace packets
Claims
1. Multiple queues, each storing packets output from multiple data processing units, and fewer than the number of data processing units, A queue selection circuit that stores the packets sequentially output from each of the plurality of data processing units into one of the plurality of queues for each data processing unit, The system includes a plurality of processing circuits provided in relation to the plurality of queues, which sequentially process the packets held in the corresponding queues. Data processing device.
2. The data processing unit that outputs the packet has a queue management table that maintains the correspondence between the data processing unit that outputs the packet and the queue in which the packet is stored. The queue selection circuit determines the queue to store the packets output from the data processing unit by referring to the queue management table. The data processing device according to claim 1.
3. When the queue selection circuit receives the packet from any of the multiple data processing units, it refers to the queue management table, If the data processing unit that issued the packet is associated with the queue, the packet is stored in the associated queue and the queue management table is updated. If the data processing unit that issued the packet is not associated with the queue, the packet is stored in one of the queues and the queue management table is updated. The data processing device according to claim 2.
4. Each of the plurality of queues has a queue management table that stores the identification information of the data processing unit that issued the most recently stored packet, associated with the queue. The aforementioned queue selection circuit is If the identification information of the data processing unit that issued the packet is held in the queue management table, the packet is stored in the corresponding queue. If the identification information of the data processing unit that issued the packet is not stored in the queue management table, and the queue management table indicates that there is an empty queue to which the identification information is not associated, the packet is stored in the empty queue. If the identification information of the data processing unit that issued the packet is not stored in the queue management table, and the queue management table indicates that there are no available queues to which the identification information is not associated, then a synchronization packet is inserted into all of the multiple queues, and the identification information stored in the queue management table is erased. The data processing device according to claim 1.
5. If the queue selection circuit erases the identification information held in the queue management table, it will treat any packets stored in the queue earlier than the storage of the synchronization packets as non-existent. The data processing device according to claim 4.
6. The packet transmission circuit has the following characteristics: If the packet is held at the head of each of the plurality of queues, it sends the packet at the head to the corresponding processing circuit; if the synchronization packet is held at the head of any of the plurality of queues, it stops the operation of the queue that has the synchronization packet at its head until the synchronization packet is held at the head of all of the queues. The data processing device according to claim 4.
7. Each of the aforementioned plurality of data processing units is a processor core, The packet includes the status log, history log, or status log and history log of the processor core. A data processing device according to any one of claims 1 to 6.
8. A control method for a data processing device having a plurality of queues, each less than the number of data processing devices, where packets output from each of the plurality of data processing devices are stored, A queue selection circuit provided in the data processing device stores the packets sequentially output from each of the plurality of data processing units into one of the plurality of queues for each data processing unit. A plurality of processing circuits, each provided in the data processing device in relation to the plurality of queues, sequentially process the packets held in the corresponding queue. A method for controlling a data processing device.