Indication device

Abstract

To provide a display that includes an improved structure for supplying voltage to an upper electrode.SOLUTION: A display according to an embodiment comprises: a substrate; an insulating layer arranged above the substrate; a lower electrode arranged above the insulating layer in a display area including pixels; a rib having an opening overlapping the lower electrode; a partition wall having conductivity and arranged above the rib in the display area; an upper electrode facing the lower electrode and connected with the partition wall; an organic layer at least partially located between the lower electrode and the upper electrode, and emitting light according to the potential difference between the lower electrode and the upper electrode; a feeder line arranged in a peripheral area around the display area; and a conductive layer arranged above the rib in the peripheral area, and connected with the feeder line and the partition wall.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] A voltage is supplied to the lower electrode from a pixel circuit arranged for each pixel. On the other hand, a voltage common to each sub-pixel is supplied to the upper electrode. There is room for various improvements in the structure for supplying a voltage to the upper electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device having an improved structure for supplying a voltage to an upper electrode.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a substrate, an insulating layer disposed above the substrate, a lower electrode disposed above the insulating layer in a display area including pixels, a rib having an opening that overlaps with the lower electrode, a conductive partition disposed above the rib in the display area, and a device facing the lower electrode and on the partition. Electrically A connected upper electrode, an organic layer which is at least partially located between the lower electrode and the upper electrode and emits light in accordance with the potential difference between the lower electrode and the upper electrode, a power supply line arranged in the peripheral region around the display area, and arranged above the rib in the peripheral region, between the power supply line and the partition wall Electrically It comprises a connected conductive layer. The power supply line is located between the insulating layer and the rib. The rib has a plurality of contact holes arranged in the peripheral region. The conductive layer has a plurality of openings and is electrically connected to the power supply line through the plurality of contact holes, and surrounds the display area in plan view. The partition and the conductive layer include a lower portion located above the rib and an upper portion located above the lower portion and having an end protruding from the side surface of the lower portion. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to one embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the display device. [Figure 5] Figure 5 is an enlarged view of the area enclosed by the dashed line frame in Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view of the display device along the VI-VI line in Figure 5. [Modes for carrying out the invention]

[0008] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0010] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0011] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. The pixel PX includes a plurality of sub-pixels SP. In one example, the pixel PX includes a red sub-pixel SP1 (first sub-pixel), a green sub-pixel SP2 (second sub-pixel), and a blue sub-pixel SP3 (third sub-pixel). Note that the pixel PX may include sub-pixels SP of other colors such as white, either together with the sub-pixels SP1, SP2, SP3 or in place of any of the sub-pixels SP1, SP2, SP3.

[0014] The sub-pixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and the drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the driving transistor 3 and the capacitor 4. In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element 20.

[0016] Note that the configuration of the pixel circuit 1 is not limited to the illustrated example. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element 20 is an organic light emitting diode (OLED) as a light emitting element. For example, the sub-pixel SP1 includes a display element 20 that emits light in a red wavelength range, the sub-pixel SP2 includes a display element 20 that emits light in a green wavelength range, and the sub-pixel SP3 includes a display element 20 that emits light in a blue wavelength range.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP1 and SP2 are aligned in the second direction Y. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the first direction X.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2.

[0022] The partition wall 6 overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP2 in the second direction Y, and between two adjacent openings AP3 in the second direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP3 in the first direction X, and between adjacent openings AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid that surrounds the openings AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has openings in the sub-pixels SP1, SP2, and SP3.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3. In the example in Figure 2, the outer shapes of upper electrode UE1 and organic layer OR1 match, upper electrode UE2 and organic layer OR2 match, and upper electrode UE3 and organic layer OR3 match.

[0025] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0026] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0027] In the example in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent openings AP1 and AP2 in the second direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent openings AP3 in the second direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0028] In the example shown in Figure 2, the lower electrodes LE1 and LE2 each have protrusions PR1 and PR2. Protrusion PR1 extends from the main body of the lower electrode LE1 (the part overlapping with the opening AP1) toward the contact hole CH1. Protrusion PR2 extends from the main body of the lower electrode LE2 (the part overlapping with the opening AP2) toward the contact hole CH2. The contact holes CH1 and CH2 overlap with the protrusions PR1 and PR2, respectively.

[0029] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring, such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered by an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 12.

[0030] The lower electrodes LE1, LE2, and LE3 are positioned on the insulating layer 12. The rib 5 is positioned on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5.

[0031] The bulkhead 6 includes a lower section 61 positioned on the rib 5 and an upper section 62 covering the upper surface of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, in Figure 3, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of the bulkhead 6 can also be described as overhanging.

[0032] The organic layer OR1 shown in Figure 2 includes a first organic layer OR1a and a second organic layer OR1b, which are spaced apart from each other. Similarly, the upper electrode UE1 shown in Figure 2 also includes a first upper electrode UE1a and a second upper electrode UE1b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a portion of the rib 5. The second organic layer OR1b is located above the upper part 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a contacts the side surface of the lower part 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0033] The organic layer OR2 shown in Figure 2 includes a first organic layer OR2a and a second organic layer OR2b, which are spaced apart from each other. Similarly, the upper electrode UE2 shown in Figure 2 also includes a first upper electrode UE2a and a second upper electrode UE2b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper part 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. Furthermore, the first upper electrode UE2a contacts the side surface of the lower part 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0034] The organic layer OR3 shown in Figure 2 includes a first organic layer OR3a and a second organic layer OR3b, which are spaced apart from each other. Similarly, the upper electrode UE3 shown in Figure 2 also includes a first upper electrode UE3a and a second upper electrode UE3b, which are spaced apart from each other. As shown in Figure 3, the first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper part 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. Furthermore, the first upper electrode UE3a contacts the side surface of the lower part 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0035] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers 71, 72, and 73. Sealing layer 71 continuously covers the first upper electrode UE1a, the side of the lower part 61, and the second upper electrode UE1b. Sealing layer 72 continuously covers the first upper electrode UE2a, the side of the lower part 61, and the second upper electrode UE2b. Sealing layer 73 continuously covers the first upper electrode UE3a, the side of the lower part 61, and the second upper electrode UE3b.

[0036] In the example shown in Figure 3, the second organic layer OR1b, the second upper electrode UE1b, and the sealing layer 71 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the same partition wall 6. Similarly, the second organic layer OR2b, the second upper electrode UE2b, and the sealing layer 72 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, the second upper electrode UE3b, and the sealing layer 73 on the same partition wall 6.

[0037] The sealing layers 71, 72, and 73 are covered by the resin layer 13. The resin layer 13 is covered by the sealing layer 14. Furthermore, the sealing layer 14 is covered by the resin layer 15.

[0038] The insulating layer 12 and the resin layers 13 and 15 are made of organic materials. The ribs 5 and the sealing layers 14, 71, 72, and 73 are made of inorganic materials such as silicon nitride (SiNx).

[0039] The lower part 61 of the partition wall 6 is conductive. The upper part 62 of the partition wall 6 may also be conductive. The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or they may have a laminated structure of a metallic material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, and UE3 may also be formed of a transparent conductive material such as ITO.

[0040] When the potentials of the lower electrodes LE1, LE2, and LE3 are relatively higher than the potentials of the upper electrodes UE1, UE2, and UE3, the lower electrodes LE1, LE2, and LE3 correspond to the anodes, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes. Also, when the potentials of the upper electrodes UE1, UE2, and UE3 are relatively higher than the potentials of the lower electrodes LE1, LE2, and LE3, the upper electrodes UE1, UE2, and UE3 correspond to the anodes, and the lower electrodes LE1, LE2, and LE3 correspond to the cathodes.

[0041] The organic layers OR1, OR2, and OR3 include a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0042] The sub-pixels SP1, SP2, and SP3 may further include cap layers to adjust the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3. Such cap layers may be provided between the upper electrode UE1 and the sealing layer 71, between the upper electrode UE2 and the sealing layer 72, and between the upper electrode UE3 and the sealing layer 73, respectively.

[0043] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the first upper electrodes UE1a, UE2a, and UE3a, which are in contact with the sides of the lower part 61. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0044] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0045] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0046] The thickness of the rib 5, which is made of inorganic material, is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. For example, the thickness of the rib 5 is between 200 nm and 400 nm. The thicknesses of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3, and the organic layers OR1, OR2, OR3 are all smaller than the thickness of the rib 5.

[0047] Next, we will explain the structures that can be applied to the surrounding SA region. Figure 4 is a schematic plan view of the display device DSP. The display device DSP includes a first gate drive circuit GD1, a second gate drive circuit GD2, a selector circuit ST, and a terminal section T as elements arranged in the peripheral region SA. The first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST are examples of drive circuits that supply signals to the pixel circuit 1, and are included in the circuit layer 11 shown in Figure 3.

[0048] The first gate drive circuit GD1 and the second gate drive circuit GD2 supply scanning signals to the scanning line GL shown in Figure 1. A flexible circuit board, for example, is connected to the terminal T. The selector circuit ST supplies the video signal input from this flexible circuit board to the signal line SL shown in Figure 1.

[0049] The substrate 10 has a first end E1, a second end E2, a third end E3, and a fourth end E4. The first end E1 and the second end E2 extend parallel to the second direction Y. The third end E3 and the fourth end E4 extend parallel to the first direction X.

[0050] In the example shown in Figure 4, the first gate drive circuit GD1 is located between the display area DA and the first end E1, the second gate drive circuit GD2 is located between the display area DA and the second end E2, and the selector circuit ST and terminal section T are located between the display area DA and the third end E3.

[0051] Furthermore, the display device DSP includes a conductive layer CL and a dam section DP located in the peripheral region SA. In the example in Figure 4, the conductive layer CL surrounds the display region DA. The dam section DP surrounds the conductive layer CL. For example, the dam section DP plays the role of damming the resin layer 13 shown in Figure 2.

[0052] The conductive layer CL is connected to the partition wall 6 located in the display area DA. In a plan view, the conductive layer CL overlaps with the first gate drive circuit GD1, the second gate drive circuit GD2, and the selector circuit ST.

[0053] Furthermore, the conductive layer CL does not necessarily have to have a shape that surrounds the display area DA. For example, the conductive layer CL does not need to be placed between the display area DA and the third end E3, or between the display area DA and the fourth end E4.

[0054] Figure 5 is an enlarged view of the area enclosed by the dashed-line frame V in Figure 4. Figure 6 is a schematic cross-sectional view of the display device DSP along the line VI-VI in Figure 5. The dotted areas in Figure 5 correspond to the conductive layer CL and the partition walls 6 (first partition wall 6x and second partition wall 6y). The conductive layer CL and the partition walls 6 are integrally formed from the same material using the same manufacturing process.

[0055] In the example shown in Figure 6, the circuit layer 11 comprises insulating layers 31, 32, 33 and metal layers 41, 42, 43. The insulating layer 31 covers the substrate 10. The metal layer 41 is placed on top of the insulating layer 31 and covered by the insulating layer 32. The metal layer 42 is placed on top of the insulating layer 32 and covered by the insulating layer 33. The metal layer 43 is placed on top of the insulating layer 33 and covered by the insulating layer 12.

[0056] The first gate drive circuit GD1 is formed by metal layers 41, 42, 43 and semiconductor layers. Similarly, the second gate drive circuit GD2 and selector circuit ST shown in Figure 5 are also formed by metal layers 41, 42, 43 and semiconductor layers.

[0057] Rib 5 is also located in the surrounding region SA. The conductive layer CL is located on top of rib 5. The conductive layer CL includes a lower section 61 and an upper section 62, similar to the partition wall 6 shown in Figure 3. In the conductive layer CL as well, both ends of the upper section 62 protrude beyond the sides of the lower section 61.

[0058] In the cross-section shown in Figure 6, the feed line PW is positioned between the insulating layer 12 and the rib 5. The feed line PW is connected to, for example, a portion of the metal layer 43. A common voltage is applied to the feed line PW. The feed line PW is formed from the same material and using the same manufacturing process as, for example, the lower electrodes LE1, LE2, and LE3. The rib 5 has a contact hole CHa. The lower part 61 of the conductive layer CL is connected to the feed line PW through the contact hole CHa.

[0059] In the example shown in Figure 5, multiple contact holes CHa are provided in the peripheral region SA. These contact holes CHa all extend elongated in the first direction X and are aligned in the second direction Y. The shape and arrangement of the contact holes CHa are not limited to this example and can be modified in various ways.

[0060] The conductive layer CL has multiple apertures APa arranged at regular intervals in the first direction X and the second direction Y. In the example in Figure 5, some of these apertures APa are located between adjacent contact holes CHa in the second direction Y. The apertures APa are smaller than the contact holes CHa, for example, in a plan view.

[0061] In forming the conductive layer CL and partition wall 6, the base layers for the lower 61 and upper 62 are first formed over the entire display area DA and surrounding area, and these layers are then patterned into the shapes of the conductive layer CL and partition wall 6 by etching. In the display area DA, there are many openings corresponding to each sub-pixel SP1, SP2, SP3 (areas enclosed by the first partition wall 6x and the second partition wall 6y). If the density of such openings differs between the display area DA and the surrounding area SA, it may not be possible to achieve uniform etching. In contrast, by providing multiple openings APa in the conductive layer CL, the etching process can be made uniform between the display area DA and the surrounding area SA.

[0062] As shown in Figure 6, the peripheral region SA contains the organic layer ORc (third organic layer), the upper electrode UEc (third upper electrode), and the sealing layer 74. In the example in Figure 6, the organic layer ORc and the upper electrode UEc are shown as a single layer, but in reality, the organic layer ORc is located beneath the upper electrode UEc. The organic layer ORc and the upper electrode UEc cover the conductive layer CL. The sealing layer 74 covers the organic layer ORc and the upper electrode UEc.

[0063] The organic layer ORc is formed from one of the organic layers OR1, OR2, or OR3, or in one example from the same material and using the same process as organic layer OR3. The upper electrode UEc is formed from one of the upper electrodes UE1, UE2, or UE3, or in one example from the same material and using the same process as upper electrode UE3. The sealing layer 74 is formed from one of the sealing layers 71, 72, or 73, or in one example from the same material and using the same process as sealing layer 73.

[0064] Because the conductive layer CL, like the partition wall 6, is in an overhanging shape, the organic layer ORc and the upper electrode UEc are separated near the edge of the conductive layer CL. That is, a portion of the organic layer ORc and the upper electrode UEc are located on the upper part 62 of the conductive layer CL, while the edges of the other portions are in contact with the side surface of the lower part 61 of the conductive layer CL.

[0065] As shown in Figure 5, the dam section DP has ridges Ra, Rb, Rc, and Rd. Between the display area DA and the first end E1, these ridges Ra, Rb, Rc, and Rd extend parallel to the second direction Y. For example, the ridges Ra, Rb, Rc, and Rd form a frame surrounding the display area DA and the conductive layer CL. That is, the conductive layer CL is located between the ridges Ra, Rb, Rc, and Rd and the display area DA. Note that the number of ridges in the dam section DP is not limited to four; it may be three or fewer, or five or more.

[0066] In the example shown in Figure 6, no ribs 5 are placed on the dam section DP, and the ridges Ra, Rb, Rc, and Rd are all placed on the insulating layer 33. In another example, ribs 5 may be placed on the dam section DP, and at least one of the ridges Ra, Rb, Rc, and Rd may be placed on top of the ribs 5.

[0067] In the example shown in Figure 6, the ridges Ra, Rb, Rc, and Rd have greater thickness than the sealing layer 74 and the conductive layer CL. The ridges Ra, Rb, Rc, and Rd are formed using the same material and process as, for example, the insulating layer 12. The organic layer ORc, the upper electrode UEc, and the sealing layer 74 cover the ridges Ra, Rb, Rc, and Rd.

[0068] The resin layer 13 is formed, for example, by an inkjet method. The unevenness of the sealing layer 74 caused by the ridges Ra, Rb, Rc, and Rd suppresses the spreading of the resin layer 13 before curing. In Figure 6, the edge of the resin layer 13 is located near the ridge Rc, but this is not the only example. The sealing layer 14 is in contact with the sealing layer 74 on the outside of the edge of the resin layer 13. The resin layer 15 completely covers the sealing layer 14.

[0069] While Figures 5 and 6 focus on the structure between the display area DA and the first end E1, a similar structure can be applied between the display area DA and the second end E2, between the display area DA and the third end E3, and between the display area DA and the fourth end E4.

[0070] In the DSP display device according to this embodiment, a partition wall 6 located in the display area DA is connected to a conductive layer CL located in the peripheral area SA. Furthermore, the partition wall 6 is connected to the upper electrodes UE1, UE2, and UE3 of the sub-pixels SP1, SP2, and SP3, and the conductive layer CL is connected to the power supply line PW. In such a structure, the common voltage of the power supply line PW can be supplied to the upper electrodes UE1, UE2, and UE3 via the conductive layer CL and the partition wall 6.

[0071] The partition wall 6 and the conductive layer CL have a lower part 61 and an upper part 62 having an end protruding from the side of the lower part 61. With this structure, in the display area DA, the organic layers OR1, OR2, and OR3 are separated by the partition wall 6, suppressing crosstalk between adjacent sub-pixels SP. In the peripheral area SA, the organic layer ORc is separated by the conductive layer CL, suppressing the intrusion of moisture through the organic layer ORc.

[0072] As shown in Figure 4, if the conductive layer CL surrounds the display area DA, it becomes possible to connect the power supply line PW to the conductive layer CL at various points around the display area DA, and also to connect the conductive layer CL to the partition wall 6. This allows for a good supply of a common voltage to the entire display area DA. Furthermore, the organic layer ORc can be divided by the conductive layer CL around the entire perimeter of the display area DA.

[0073] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0074] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0075] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0076] DSP...Display device, DA...Display area, SA...Peripheral area, PX...Pixel, SP1, SP2, SP3...Sub-pixel, LE1, LE2, LE3...Lower electrode, UE1, UE2, UE3...Upper electrode, OR1, OR2, OR3...Organic layer, CL...Conductive layer, PW...Power supply line, DP...Dam section, Ra, Rb, Rc, Rd...Ridge, APa...Aperture, CHa...Contact hole, 1...Pixel circuit, 5...Rib, 6...Partition, 10...Substrate, 12...Insulating layer, 61...Lower part of partition, 62...Upper part of partition, 71, 72, 73, 74...Sealing layer.

Claims

1. circuit board and An insulating layer disposed above the substrate, A lower electrode positioned above the insulating layer in a display area including a pixel, A rib having an opening that overlaps with the lower electrode, A conductive partition wall is positioned above the rib in the display area, An upper electrode, which is opposite the lower electrode and electrically connected to the partition wall, An organic layer, at least a portion of which is located between the lower electrode and the upper electrode, and which emits light in accordance with the potential difference between the lower electrode and the upper electrode, Power supply lines arranged in the peripheral region surrounding the display area, A conductive layer is provided in the peripheral region above the rib and electrically connected to the power supply line and the partition wall, Equipped with, The power supply line is located between the insulating layer and the rib, The rib has a plurality of contact holes arranged in the peripheral region, The conductive layer has a plurality of openings and is electrically connected to the power supply line through the plurality of contact holes, and surrounds the display area in a plan view. The partition wall and the conductive layer include a lower portion positioned on the rib and an upper portion positioned on the lower portion and having an end protruding from the side surface of the lower portion. Display device.

2. The plurality of contact holes extend elongated in a first direction and are arranged in a second direction intersecting the first direction. The display device according to claim 1.

3. The plurality of openings in the conductive layer are smaller than the contact holes. The display device according to claim 1.

4. A pixel circuit arranged in the display area and supplying voltage to the lower electrode, The system further comprises a drive circuit arranged in the peripheral region and supplying signals to the pixel circuit, At least a portion of the conductive layer overlaps with the drive circuit in a plan view. The display device according to any one of claims 1 to 3.

5. The organic layer includes a first organic layer that contacts the lower electrode through the opening in the rib, and a second organic layer located above the partition wall and spaced apart from the first organic layer. The display device according to any one of claims 1 to 4.

6. The organic layer further includes a third organic layer covering the conductive layer. The display device according to claim 5.

7. The upper electrode is in contact with the lower side surface. The display device according to any one of claims 1 to 6.

8. The lower part is conductive. The display device according to claim 7.

9. The peripheral region is further comprising a ridge that surrounds the conductive layer, The display device according to any one of claims 1 to 8.

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