Semiconductor equipment

Abstract

To provide a semiconductor device which uses an oxide semiconductor and achieves fining while maintaining good electrical characteristics.SOLUTION: A semiconductor device has: an oxide semiconductor film and a blocking film; a source electrode and a drain electrode which are electrically connected with the oxide semiconductor film; a gate insulation film contacting the oxide semiconductor film, the source electrode and the drain electrode; and a gate electrode contacting the gate insulation film. The blocking film uses the same material with the oxide semiconductor film formed on the same surface with the oxide semiconductor film and has higher conductivity than the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a product, method, or method of manufacture. Or, the present invention relates to a process, machine Relating to manufacturing, production, or composition of matter. In one aspect of the present invention, semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, and the This relates to a method for driving such devices, or a method for manufacturing them.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all types of devices. Display devices, electro-optical devices, semiconductor circuits, and electrical equipment include semiconductor devices. This can sometimes happen. [Background technology]

[0003] A transistor (thin film transistor) is formed using a semiconductor thin film on a substrate having an insulating surface. The technology for constructing transistors (also known as TFTs) is attracting attention. These transistors are integrated circuits. It is widely applied in electronic devices such as integrated circuits (ICs) and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, Oxide semiconductors are attracting attention as another material.

[0004] For example, amorphous acids containing indium (In), gallium (Ga), and zinc (Zn) A transistor using a synthetic semiconductor film is disclosed in Patent Document 1. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Overview of the project] [Problems that the invention aims to solve]

[0006] As circuits become more highly integrated, openings are provided in the interlayer insulating film between elements, and electrodes are placed in these openings. Sometimes, wiring or other connections are provided to electrically connect the elements. The elements use an oxide semiconductor film. In the case of a transistor, impurities such as hydrogen can enter the oxide semiconductor film through the aperture. Furthermore, oxygen vacancies and hydrogen in the oxide semiconductor film reduce resistance, impairing the electrical characteristics of the transistor. It leads to good things.

[0007] In view of these problems, one aspect of the present invention is a semiconductor device using an oxide semiconductor, One of the objectives is to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention is One of our objectives is to provide novel semiconductor devices.

[0008] Furthermore, it is possible to increase the speed of transistor operation, reduce the power consumption of transistors, lower the cost, and increase integration. Miniaturization of transistors is essential to achieve such advancements.

[0009] Therefore, one aspect of the present invention is a semiconductor device using an oxide semiconductor, which has good electrical characteristics One of the objectives is to provide a semiconductor device that achieves miniaturization while maintaining performance.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention It is not necessary to solve all of these problems. Furthermore, any other problems not mentioned above are clearly defined. This will become clear from the details and other descriptions, and any issues other than those mentioned above will not be identified from the specifications and other descriptions. It is possible to extract it. [Means for solving the problem]

[0011] One aspect of the present invention relates to an oxide semiconductor film and a blocking film, and the oxide semiconductor film and electrical Source electrodes and drain electrodes connected, and an oxide semiconductor film, source electrodes and drain It has a gate insulating film in contact with the in electrode and a gate electrode in contact with the gate insulating film, and a block The King film is formed using the same material as the oxide semiconductor film and on the same surface as the oxide semiconductor film. This semiconductor device is characterized by its higher conductivity.

[0012] Another aspect of the present invention relates to an oxide semiconductor film and a blocking film, and an oxide semiconductor Source and drain electrodes electrically connected to the film, oxide semiconductor film, source electrode It also has a gate insulating film in contact with the drain electrode and a gate electrode in contact with the gate insulating film. Furthermore, the blocking film is made of different materials from the oxide semiconductor film, source electrode, and drain electrode. It is used to form on the same surface as the oxide semiconductor film and to have higher conductivity than the oxide semiconductor film. This is a semiconductor device with distinctive features.

[0013] Furthermore, in the above configuration, an insulating film is provided directly beneath the oxide semiconductor film and the blocking film. An opening is provided in the insulating film, and the distance between the blocking film and the oxide semiconductor film is such that the opening and the acid It is shorter than the distance to the ionized semiconductor film.

[0014] Furthermore, in the above configuration, a first transistor is provided beneath the insulating film, and the first transistor The device includes a substrate containing a semiconductor material, and the source electrode or drain electrode is connected to the substrate through an opening. They are connected by energy. [Effects of the Invention]

[0015] By using one aspect of the present invention, water can be released from other layers into the oxide semiconductor film. Because it has the function of suppressing the intrusion of impurities such as elements, it prevents defects in the electrical characteristics of semiconductor devices. This can suppress [the problem]. Therefore, a highly reliable semiconductor device can be provided. However, one aspect of the present invention is not limited to these effects. For example, one aspect of the present invention In some cases, or depending on the circumstances, it may have effects other than those listed above. Or, for example, one aspect of the present invention may, depending on the circumstances, apply this These effects may not always be present. [Brief explanation of the drawing]

[0016] [Figure 1] Top view and cross-sectional view illustrating a transistor. [Figure 2] A diagram illustrating the method for manufacturing transistors. [Figure 3] A diagram illustrating the method for manufacturing transistors. [Figure 4] A diagram illustrating the method for manufacturing transistors. [Figure 5] A cross-sectional diagram illustrating a transistor. [Figure 6] Top view and cross-sectional view illustrating a transistor. [Figure 7] A diagram illustrating the method for manufacturing transistors. [Figure 8] A diagram illustrating the method for manufacturing transistors. [Figure 9] A diagram illustrating the method for manufacturing transistors. [Figure 10] A cross-sectional diagram illustrating a transistor. [Figure 11] A cross-sectional view and a circuit diagram of a semiconductor device according to an embodiment. [Figure 12] An example of a storage device configuration according to an embodiment. [Figure 13] An example of the configuration of an RF tag according to an embodiment. [Figure 14] An example of a CPU configuration according to an embodiment. [Figure 15]Circuit diagram of a memory element according to an embodiment. [Figure 16] An electronic device according to an embodiment. [Figure 17] An example of the use of an RF device according to an embodiment. [Figure 18] A diagram illustrating the characteristics of the transistor in the example. [Figure 19] A diagram illustrating a display device according to an embodiment. [Figure 20] A top view illustrating a transistor. [Figure 21] Top view and cross-sectional view illustrating a transistor. [Modes for carrying out the invention]

[0017] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may vary. Those skilled in the art will readily understand that modifications are possible. Therefore, the present invention is practical as follows: The interpretation is not limited to the description of the form of implementation. In construction, the same reference numeral is used for identical parts or parts having similar functions across different drawings. The explanation may be omitted if the phrase is used consistently and repeated.

[0018] Note that the "source" and "drain" functions of a transistor are different for transistors with opposite polarities. When adopting this method, or when the direction of current changes during circuit operation, the configuration may be reversed. Therefore, in this specification, the terms "source" and "drain" are used interchangeably. It may be used as a substitute.

[0019] Furthermore, in this specification, ordinal numbers such as "the first," "the second," etc., are used to avoid confusion with the constituent elements. It should be noted that this is added for the purpose of [specific purpose] and does not limit the number.

[0020] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0021] Figures 1(A) and 1(B) are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. Figure 1(A) is a top view, and the cross-section of the dashed line A1-A2 shown in Figure 1(A) is shown in Figure 1 This corresponds to (B). Note that in the top view of Figure 1(A), some elements have been omitted for clarity. This is illustrated in the diagram. Also, the direction of the dashed line A1-A2 is the channel length direction, and the dashed line A1-A The direction perpendicular to the two directions is sometimes referred to as the channel width direction. For an example of a top view, see Figure 1. (A) is not the only option. For example, a top view like that shown in Figure 20 is also acceptable.

[0022] The transistor 150 shown in Figures 1(A) and 1(B) is located on the substrate 100, in the under-insulating film. 102, and conductive films 104a, 104b, and 104c on the underlying insulating film 102. and between the layers on the underlayer insulating film 102, conductive film 104a, conductive film 104b and conductive film 104c Insulating film 106, oxide semiconductor film 108a on interlayer insulating film 106, blocking film 108 b and the blocking film 108c, via the opening 120a provided in the interlayer insulating film 106 This electrically connects to the conductive film 104b, and also connects to the oxide semiconductor film 108a and the blocking The source electrode 110a on the film 108b and the opening 120b provided in the interlayer insulating film 106 The conductive film 104c is electrically connected via and the oxide semiconductor film 108a and block Drain electrode 110b on King film 108c, oxide semiconductor film 108a, source electrode 1 10a and the gate insulating film 112 on the drain electrode 110b, and the oxide semiconductor film 108a It is superimposed on the gate electrode 114 on the gate insulating film 112, and the gate insulating film 112 and the gate It has an oxide insulating film 116 on the electrode 114.

[0023] The channel length is the region in the top view where the semiconductor film and the gate electrode overlap. The source (source region or source electrode) and the drain (drain region or drain electrode) This refers to the distance from the pole. In other words, in Figure 1(A), the channel length is the distance from the oxide semiconductor film 108 In the region where a and gate electrode 114 overlap, source electrode 110a and drain electrode 11 This is the distance to 0b. The channel width is the region where the semiconductor film and the gate electrode overlap. This refers to the width of the source or drain. In other words, in Figure 1(A), the channel width is the width of the oxide semicircular duct. In the region where the conductive film 108a and the gate electrode 114 overlap, the source electrode 110a or This refers to the width of the drain electrode 110b.

[0024] When miniaturizing the channel length and channel width of a transistor, the resist mask is retracted. When electrodes or semiconductor films are processed while doing so, the upper edges of the electrodes or semiconductor films become rounded (bent). (It may have a surface.) With this configuration, a shape is formed on the oxide semiconductor film 108a. The coating properties of the gate insulating film 112, gate electrode 114, and oxide insulating film 116 are improved. It can be raised. Also, at the ends of the source electrode 110a and the drain electrode 110b This can mitigate potential electric field concentration and suppress transistor degradation. can.

[0025] Furthermore, the blocking film 108b is closer to the oxide semiconductor film 108a than the aperture 120a. In other words, the distance between the blocking film 108b and the oxide semiconductor film 108a is equal to the opening 120a The distance between the oxide semiconductor film 108a and the blocking film 108c is shorter. Similarly, the blocking film 108c has an opening 1 20b is closer to the oxide semiconductor film 108a, that is, the blocking film 108c and the oxide semiconductor The distance to the conductive film 108a is shorter than the distance between the opening 120b and the oxide semiconductor film 108a. .

[0026] By providing a blocking film as described above, other layers (for example, silicon transistors) The blocking membrane adsorbs impurities such as hydrogen that enter through the opening from the layer between the two. Therefore, it has the function of suppressing the intrusion of impurities into the oxide semiconductor film, This can suppress defects in the electrical characteristics of the device.

[0027] Furthermore, the blocking film is formed on the same surface using the same material as the oxide semiconductor film. This allows for the formation of a blocking film without increasing the number of steps in the process. This is not limited to the above; blocking films include oxide semiconductor films, source electrodes (or drain electrodes). It may be made of different materials.

[0028] Because blocking films adsorb impurities such as hydrogen, they have a higher concentration of impurities compared to oxide semiconductor films. The degree is high. Therefore, blocking films have higher conductivity compared to oxide semiconductor films.

[0029] Furthermore, the electric field of the gate electrode 114 electrically surrounds the oxide semiconductor film 108a. (The electric field of the gate electrode electrically surrounds the oxide semiconductor film, The structure of the sta is called a surrounded channel (s-channel) structure. Therefore, channels are formed throughout the entire (bulk) oxide semiconductor film 108a. - In a channel structure, a large current can be passed between the source and drain of the transistor. This allows for obtaining a high on-current.

[0030] Because it provides a high on-current, the s-channel structure is used in miniaturized transistors. This structure is suitable for [the purpose]. Because the transistor can be miniaturized, semiconductors having the transistor The device can be made into a highly integrated, high-density semiconductor device. For example, The channel length of the transistor is preferably 40 nm or less, and more preferably 30 nm or less. More preferably, the wavelength is 20 nm or less, and the channel width of the transistor is preferably 4 The wavelength should be 0 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less.

[0031] The substrate 100 is not merely a support, but also forms other elements such as transistors and capacitors. A substrate may be made. In this case, the gate electrode, source electrode, and drain of the transistor are also included. At least one of the in electrodes may be electrically connected to the other elements mentioned above.

[0032] The underlying insulating film 102 has the role of preventing the diffusion of impurities from the substrate 100, as well as acid It can play a role in supplying oxygen to the ionized semiconductor film 108a. Therefore, it provides insulation to the underlying substrate. The film 102 is preferably an insulating film containing oxygen. For example, it is preferably more than the stoichiometric composition. It is more preferable that the insulating film contains oxygen. Also, as mentioned above, if the substrate 100 is not an element If the substrate has a layer formed on it, the underlying insulating film 102 also functions as an interlayer insulating film. In that case, the surface of the underlayer insulating film 102 may be flattened. For example, the underlayer insulating film 10 2. Using methods such as CMP (Chemical Mechanical Polishing) A blunting treatment should be performed.

[0033] The conductive film 104a can be used as a second gate electrode, further increasing the on-current. It is possible to control the threshold voltage. To increase the on current, the conductive film 10 4a and gate electrode 114 are electrically connected to the same potential, creating a dual-gate transistor. It can be driven as follows. Also, to control the threshold voltage, the conductive film 104a and the gate The electrode 114 is not electrically connected to the gate electrode 114, and a different constant potential is introduced. It should be supplied to the film 104a.

[0034] Furthermore, the conductive film 104b functions as wiring that electrically connects to the source electrode 110a. The conductive film 104c functions as wiring that electrically connects to the drain electrode 110b. Film 104b and conductive film 104c are electrically connected to other elements such as transistors and capacitors. It may be connected.

[0035] However, the embodiments of the present invention are not limited thereto. The conductive film 104a is not necessarily It is not necessary to provide them. Also, conductive films 104b and 104c are not necessarily provided. It is not necessary for them to be punctured. Conductive film 104a, conductive film 104b, and conductive film 104c are provided. Figures 21(A) and 21(B) show the top view and cross-sectional view when the bracket is not installed.

[0036] The interlayer insulating film 106, like the underlying insulating film 102, serves to prevent the diffusion of impurities. In addition, it can play a role in supplying oxygen to the oxide semiconductor film 108a. Therefore, The interlayer insulating film 106 is preferably an insulating film containing oxygen.

[0037] The oxide semiconductor film 108a will be described in detail below.

[0038] The oxide semiconductor film 108a is an oxide containing indium. Oxides include, for example, in When zinc is included, the carrier mobility (electron mobility) increases. Also, oxide semiconductor film 10 8a preferably contains element M. Examples of element M include aluminum, gallium, and Examples include tin or tincture. Element M is, for example, an element with a high bond energy with oxygen. It is a fundamental element. Element M is, for example, an element that has the function of increasing the energy gap of oxides. It is a basic element. Furthermore, it is preferable that the oxide semiconductor film 108a contains zinc. For example, this makes it easier to crystallize oxides. The energy at the top of the valence band of an oxide is, for example, For example, it can be controlled by the atomic ratio of zinc.

[0039] However, the oxide semiconductor film 108a is not limited to oxides containing indium. The semiconductor film 108a may be, for example, Zn-Sn oxide or Ga-Sn oxide. .

[0040] Furthermore, the oxide semiconductor film 108a uses an oxide with a large energy gap. The energy gap of the monocrystalline semiconductor film 108a is, for example, between 2.5 eV and 4.2 eV. Preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV. Let's assume that.

[0041] Furthermore, when depositing an oxide semiconductor film 108a by sputtering, the particle number is low. To reduce this, it is preferable to use a target containing indium. Also, the atomic ratio of element M is When using a highly oxide target, the target's conductivity may decrease. When using a target containing um, the conductivity of the target can be increased, and DC discharge Furthermore, AC discharge becomes easier, making it easier to handle large-area substrates. Therefore, semiconductor equipment This can increase productivity.

[0042] When depositing an oxide semiconductor film 108a by sputtering, the atomic ratio of the target is , In:M:Zn is 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1 You can set it to 1:1:2, for example.

[0043] When depositing an oxide semiconductor film 108a by sputtering, the atomic ratio of the target is... In some cases, a film with a misaligned atomic ratio may be formed. In particular, zinc may have a misaligned atomic ratio with the target. The atomic ratio of the rimo film may become smaller. Specifically, the amount of zinc contained in the target may decrease. The ratio of offspring may be between 40 and 90 atomic percent.

[0044] The following section explains the effects of impurities in the oxide semiconductor film 108a. To stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor film 108a is important. Reducing this, lowering carrier density, and increasing purity are effective. The carrier density of membrane 108a is 1 × 10⁻⁶ 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 Not yet Full, or 1 x 10 13 pieces / cm 3 The impurity concentration in the oxide semiconductor film 108a shall be less than the specified value. To reduce this, it is preferable to also reduce the concentration of impurities in the adjacent membrane.

[0045] For example, silicon in the oxide semiconductor film 108a may become a carrier trap or a carrier generation source. Therefore, the silicon concentration between the oxide semiconductor film 108a and the interlayer insulating film 106 is less than 1×10 atoms / cm in secondary ion mass spectrometry (SIMS), preferably less than 5×10 19 atoms / cm 3 , more preferably less than 2×10 atoms / cm 18 . Also, the silicon concentration between the oxide semiconductor film 108a and the gate insulating film 112 is less than 1×10 3 atoms / cm 18 in SIMS, preferably less than 5×10 atoms / cm 3 , more preferably less than 2×10 atoms / cm 19 . 3 Preferably less than 5×10 18 atoms / cm 3 , and even more preferably less than 2×10 18 atoms / cm 3 .

[0046] In addition, if hydrogen is contained in the oxide semiconductor film 108a, the carrier density may increase. The hydrogen concentration of the oxide semiconductor film 108a is 2×10 20 atoms / cm or less in SIMS, preferably 5×10 3 atoms / cm 19 or less, more preferably 3 1×10 atoms / cm 19 or less, even more preferably 5×10 3 atoms / cm 18 or less. Also, if nitrogen is contained in the oxide semiconductor film 108a, the carrier density m 3 will It may increase. The nitrogen concentration of the oxide semiconductor film 108a is in SIMS , 5×10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 Below Below, fer 1 × 10 18 atoms / cm 3 More preferably 5 × 10 1 7 atoms / cm 3 The following applies:

[0047] Furthermore, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a, the underlying insulating film 102 and the interlayer film are used. It is preferable to reduce the hydrogen concentration of the insulating film 106. The hydrogen concentration in SIMS is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferably 5 × 1 0 19 atoms / cm 3 More preferably 1 × 10 19 atoms / cm 3 below, More preferably 5 × 10 18 atoms / cm 3 The following applies. Also, oxide semiconductor film 1 To reduce the nitrogen concentration of 08a, the nitrogen concentrations of the underlayer insulating film 102 and the interlayer insulating film 106 are It is preferable to reduce it. The nitrogen concentration of the underlayer insulating film 102 and the interlayer insulating film 106 is determined by SIMS. 5 x 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5×1 0 17 atoms / cm 3 The following applies:

[0048] Furthermore, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a, the water in the gate insulating film 112 It is preferable to reduce the elementary concentration. The hydrogen concentration of the gate insulating film 112 is 2 × in SIMS. 10 20 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following, Preferably 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 at oms / cm 3 The following applies. In addition, in order to reduce the nitrogen concentration of the oxide semiconductor film 108a It is preferable to reduce the nitrogen concentration of the gate insulating film 112. In SIMS, 5 × 10 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 Below, further Preferably 5 × 10 17 atoms / cm 3 The following applies:

[0049] The following describes the structure of an oxide semiconductor film applicable to oxide semiconductor film 108a. ru.

[0050] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films are CAAC-OS (C Axis Aligned Crystal Sturtine Oxide Semiconductor film, polycrystalline oxide semiconductor This refers to films, microcrystalline oxide semiconductor films, amorphous oxide semiconductor films, etc.

[0051] First, let's explain the CAAC-OS membrane.

[0052] CAAC-OS film is one of the oxide semiconductor films having multiple crystalline regions, and most The crystalline portion is small enough to fit within a cube with sides less than 100 nm. Therefore, CAA The crystalline portion contained in the C-OS film has sides of less than 10 nm, less than 5 nm, or less than 3 nm. This also includes cases where the object is small enough to fit inside a box.

[0053] CAAC-OS film is examined using a transmission electron microscope (TEM). When observed with a tron ​​microscope, a clear boundary between crystalline regions is observed, i.e. The grain boundaries (also called crystal grain boundaries) cannot be identified. Therefore, C AAC-OS films are less susceptible to the decrease in electron mobility caused by grain boundaries.

[0054] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM view). (Inference) It can be confirmed that in the crystalline part, metal atoms are arranged in layers. Each of these layers has irregularities on the surface (also called the surface to be formed) or upper surface that form the CAAC-OS film. The shape is reflected and is arranged parallel to the surface or top surface of the CAAC-OS film.

[0055] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T). EM observation reveals that in the crystalline region, metal atoms are arranged in a triangular or hexagonal shape. This can be confirmed. However, no regularity is observed in the arrangement of metal atoms between different crystalline regions. do not have.

[0056] Cross-sectional TEM observation and planar TEM observation revealed that the crystalline portion of the CAAC-OS film exhibits orientation. It can be seen that this is happening.

[0057] X-ray diffraction (XRD) of CAAC-OS film When structural analysis is performed using the instrument, for example, CAAC-OS having InGaZnO4 crystals is found. Out-of-plane analysis of the film showed a peak at a diffraction angle (2θ) of around 31°. This peak may appear. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have c-axis orientation, and the c-axis is on the surface to be formed or on the upper surface. It can be confirmed that it is oriented in a roughly vertical direction.

[0058] In this specification, if a crystal is trigonal or rhombohedral, it is listed as hexagonal. vinegar.

[0059] On the other hand, in the CAAC-OS film, X-rays are incident from a direction approximately perpendicular to the c-axis in an in-p In analysis using the lane method, a peak may appear when 2θ is around 56°. This is attributed to the (110) plane of the InGaZnO4 crystal. For a crystalline semiconductor film, fix 2θ to approximately 56° and use the normal vector of the sample surface as the axis (φ axis). When the analysis (φ scan) is performed while rotating the sample, a crystal plane equivalent to the (110) plane is found. Six peaks attributable to this are observed. In contrast, in the case of the CAAC-OS film, 2θ Even when fixed at approximately 56° and scanned using the φ scan function, no clear peak appears.

[0060] From the above, it can be concluded that in CAAC-OS films, the orientation of the a-axis and b-axis between different crystalline regions is Although irregular, it has c-axis orientation, and the c-axis is parallel to the normal vector of the formed surface or the upper surface. It can be seen that it is oriented in a specific direction. Therefore, the layer confirmed by the aforementioned cross-sectional TEM observation. Each layer of metal atoms arranged in a crystalline structure is a plane parallel to the ab-plane of the crystal.

[0061] Furthermore, the crystalline portion is formed when the CAAC-OS film is deposited, or during crystallization treatments such as heat treatment. It is formed when the process is carried out. As mentioned above, the c-axis of the crystal is aligned with the surface on which the CAAC-OS film is formed. Or it is oriented in a direction parallel to the normal vector of the top surface. Therefore, for example, CAAC-OS When the shape of the film is altered by etching or other means, the c-axis of the crystal is the surface of the CAAC-OS film. The normal vector may not be parallel to the forming surface or the top surface.

[0062] Furthermore, the degree of crystallinity in the CAAC-OS film does not need to be uniform. For example, CAAC-OS When the crystalline portion of the film is formed by crystal growth from near the upper surface of the CAAC-OS film, The region near the surface may have a higher degree of crystallinity than the region near the surface being formed. Also, CA When impurities are added to an AC-OS film, the degree of crystallinity in the region where the impurities are added changes, and Regions with varying degrees of crystallinity may also be formed.

[0063] Furthermore, the out-of-plane CAAC-OS film having InGaZnO4 crystals Analysis using this method revealed that in addition to the peak near 2θ = 31°, there is also a peak near 2θ = 36°. In some cases, this may occur. Peaks near 2θ of 36° indicate c-axis orientation in a portion of the CAAC-OS film. This indicates the presence of crystals that do not possess properties. The CAAC-OS film has a 2θ of approximately 31°. It is preferable that a peak is shown and that no peak is shown near 36° for 2θ.

[0064] CAAC-OS films are oxide semiconductor films with low impurity concentrations. The impurities include hydrogen and carbon. These are elements other than the main components of oxide semiconductor films, such as silicon and transition metal elements. In particular, silicon Elements such as condensate, which have a stronger bonding force with oxygen than the metal elements that make up oxide semiconductor films, are acidic. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. This is a contributing factor. Also, heavy metals such as iron and nickel, argon, and carbon dioxide have a high atomic ratio. Because of its large diameter (or molecular radius), when it is contained within an oxide semiconductor film, the oxide semiconductor film This disrupts the atomic arrangement and reduces crystallinity. Pure substances can act as carrier traps or carrier sources.

[0065] Furthermore, CAAC-OS films are oxide semiconductor films with a low defect level density. For example, oxidation Oxygen vacancies in semiconductor films can act as carrier traps or capture hydrogen. This can sometimes become a source of carrier transmission.

[0066] A low impurity concentration and low defect level density (few oxygen vacancies) are referred to as high-purity intrinsic or This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic. Because membranes have fewer carrier sources, they can have lower carrier densities. Therefore The transistor using the oxide semiconductor film exhibits electrical characteristics such as a negative threshold voltage. It rarely becomes (also called normally-on). Also, it is of high purity and is essentially high purity. Intrinsically pure oxide semiconductor films have few carrier traps. Therefore, the oxide semiconductor film Transistors using conductive films exhibit less variation in electrical characteristics and are highly reliable. Yes. Furthermore, the charge trapped in the carrier trap of the oxide semiconductor film requires time to be released. This process can last for a long time, sometimes behaving as if it were a fixed charge. Therefore, the impurity concentration... Transistors using oxide semiconductor films with high defect level density have unstable electrical properties. This can sometimes happen.

[0067] Furthermore, transistors using CAAC-OS films exhibit electrical properties when irradiated with visible light or ultraviolet light. Sexual variation is small.

[0068] Next, we will explain microcrystalline oxide semiconductor films.

[0069] Microcrystalline oxide semiconductor films can be clearly observed using TEM. In some cases, this may not be possible. The crystalline portion contained in the microcrystalline oxide semiconductor film is between 1 nm and 100 nm. They are often smaller than 1 nm, or between 1 nm and 10 nm in size. In particular, between 1 nm and 10 nm Nanocrystals (nc: nanocrystals) are microcrystals of a size of 1 nm or less, or between 1 nm and 3 nm. An oxide semiconductor film having tal is made nc-OS (nanocrystalline O It is called an xide Semiconductor film. Also, an nc-OS film is, for example, T In some cases, grain boundaries may not be clearly visible in images obtained using EM (Electromagnetic Wave) imaging.

[0070] nc-OS films are used in minute regions (for example, regions between 1 nm and 10 nm, especially regions between 1 nm and 10 nm). The atomic arrangement has periodicity in the region of 3 nm or less. In addition, the nc-OS film is different There is no regularity in the crystal orientation between the crystalline regions. Therefore, no overall orientation is observed. Therefore, depending on the analytical method, nc-OS films may be indistinguishable from amorphous oxide semiconductor films. There are cases where this is not possible. For example, when using X-rays with a diameter larger than that of the crystalline region on an nc-OS film, XR When structural analysis is performed using instrument D, the out-of-plane method shows that the crystal plane No peak indicating this is detected. Also, the nc-OS film has a probe diameter larger than that of the crystalline portion. For example, electron diffraction (also called limited-field electron diffraction) using an electron beam of 50 nm or more. When this is done, a diffraction pattern resembling a halo pattern is observed. On the other hand, for nc-OS films... , probe diameter close to or smaller than the size of the crystal (for example, 1 nm to 30 nm) When electron diffraction (also called nanobeam electron diffraction) is performed using an electron beam, the spot This is observed. Furthermore, when nanobeam electron diffraction is performed on the nc-OS film, it appears to trace a circle. In some cases, a region of high brightness (ring-shaped) may be observed in relation to the nc-OS film. When performing electron diffraction, multiple spots may be observed within a ring-shaped region. ru.

[0071] nc-OS films are oxide semiconductor films with higher orderliness than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect level density than amorphous oxide semiconductor films. However, Furthermore, the nc-OS film does not show any regularity in crystal orientation between different crystalline regions. Therefore, nc- OS films have a higher defect level density compared to CAAC-OS films.

[0072] Note that oxide semiconductor films include, for example, amorphous oxide semiconductor films, microcrystalline oxide semiconductor films, and C The AAC-OS film may contain two or more types.

[0073] The oxide semiconductor film 108a may be a stacked film of oxide semiconductor films. For example, oxide The semiconductor film 108a may have a two-layer structure or a three-layer structure.

[0074] For example, let's consider the case where the oxide semiconductor film 108a has a three-layer structure. Figure 1(C) shows, Oxide semiconductor film 108a, oxide semiconductor film 108a1, oxide semiconductor film 108a2, acid This shows a case where a laminated film is formed by sequentially providing two ionized semiconductor films 108a3.

[0075] The oxide semiconductor film 108a2 (middle layer) is related to the oxide semiconductor film 108a up to this point. Refer to the description. Oxide semiconductor film 108a1 (lower layer) and oxide semiconductor film 108a3 ( The upper layer consists of one or more elements other than oxygen that constitute the oxide semiconductor film 108a2, or two or more elements. It is an oxide semiconductor film composed from top to bottom. Other than oxygen, which constitutes the oxide semiconductor film 108a2... One or more elements of the oxide semiconductor film 108a1 and oxide semiconductor film 1 Since 08a3 is formed, the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2 At the interface, and at the interface between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3, Interface states are less likely to form.

[0076] Furthermore, when the oxide semiconductor film 108a1 is an In-M-Zn oxide, Zn and O are excluded. The atomic ratio of In and M is preferably less than 50 atomic% for In and 50% for M. Atomic% or more, more preferably less than 25 atomic% of In and 75 atomic% of M. The mic% must be 1% or higher. Also, when the oxide semiconductor film 108a2 is In-M-Zn oxide, The atomic ratio of In and M, excluding Zn and O, is preferably 25 atoms of In. c% or more, M less than 75 atomic%, and more preferably In 34 atomic% or less. Above, M is assumed to be less than 66 atomic%. Also, the oxide semiconductor film 108a3 is In-M- In the case of Zn oxide, the atomic ratio of In and M excluding Zn and O is preferably I n is less than 50 atomic%, M is 50 atomic%, and more preferably In is 2 The atomicity is less than 5, and M is 75 atomicity or more. Note that the oxide semiconductor film 10 8a3 may be made of the same oxide as the oxide semiconductor film 108a1.

[0077] Here, between the oxide semiconductor film 108a1 and the oxide semiconductor film 108a2, It may have a mixed region of the conductive film 108a1 and the oxide semiconductor film 108a2. Between oxide semiconductor film 108a2 and oxide semiconductor film 108a3, oxide semiconductor film 10 It may have a mixed region of 8a2 and the oxide semiconductor film 108a3. The mixed region is the interface. The energy level density decreases. Therefore, oxide semiconductor film 108a1, oxide semiconductor film 108a2 And the laminate of oxide semiconductor film 108a3 has energy near each interface. This results in a band structure that changes continuously (also called a continuous junction).

[0078] The oxide semiconductor film 108a2 is composed of oxide semiconductor film 108a1 and oxide semiconductor film 108 An oxide with a higher electron affinity than a3 is used. For example, an oxide semiconductor film 108a2 is used. Therefore, the electron affinity is 0 compared to oxide semiconductor film 108a1 and oxide semiconductor film 108a3. 0.7eV to 1.3eV, preferably 0.1eV to 0.7eV, even more preferably For the electron affinity, use an oxide with an electron affinity between 0.15 eV and 0.4 eV. This is the difference between the energy level and the energy at the bottom of the conduction band.

[0079] At this time, when an electric field is applied to the gate electrode 114, the oxide semiconductor film 108a1, oxide Of the semiconductor film 108a2 and oxide semiconductor film 108a3, the oxide semiconductor film with high electron affinity A channel is formed in the body membrane 108a2.

[0080] Furthermore, for the on-current of the transistor, the thickness of the oxide semiconductor film 108a3 should be thin. It is preferable that the oxide semiconductor film 108a3 is less than 10 nm, preferably 5 nm or less. Furthermore, it is more preferably 3 nm or less. On the other hand, the oxide semiconductor film 108a3 has a channel To the oxide semiconductor film 108a2 that is formed, elements other than oxygen that constitute the gate insulating film 112 It has a function to block the entry of elements (such as silicon). Therefore, oxide semiconductors The conductive film 108a3 preferably has a certain thickness. For example, an oxide semiconductor film. The thickness of 108a3 is 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm. That concludes this section.

[0081] Furthermore, in order to improve reliability, the oxide semiconductor film 108a1 is thicker, and the oxide semiconductor film 1 It is preferable that 08a3 be thin. Specifically, the thickness of the oxide semiconductor film 108a1 is 20 nm or more, preferably 30 nm or more, more preferably 40 nm or more, more preferably 6 The thickness shall be 0 nm or greater. The thickness of the oxide semiconductor film 108a1 shall be 20 nm or greater, preferably 30 nm. By setting the wavelength to 40 nm or more, more preferably 60 nm or more, A channel is formed at the interface between the interlayer insulating film 106 and the oxide semiconductor film 108a1. The semiconductor film up to 108a2 should be 20 nm or more, preferably 30 nm or more, and more preferably 4 The distance can be 0 nm or more, more preferably 60 nm or more. However, in the production of semiconductor devices... Because performance may decrease, the thickness of the oxide semiconductor film 108a1 should be 200 nm or less. The wavelength is 120 nm or less, and more preferably 80 nm or less.

[0082] For example, silicon between oxide semiconductor film 108a2 and oxide semiconductor film 108a1 The concentration of 1 × 10 in SIMS is 19 atoms / cm 3 Less than 5 × 1 0 18 atoms / cm 3 Less than 2 × 10 18 atoms / cm 3 less than Furthermore, the interaction between the oxide semiconductor film 108a2 and the oxide semiconductor film 108a3 is also considered. The ricon concentration in SIMS is 1 × 10⁻⁶ 19 atoms / cm 3 Less than 5 ×10 18 atoms / cm 3 Less than 2 × 10 18 atoms / cm 3 Less than.

[0083] Furthermore, in order to reduce the hydrogen concentration of the oxide semiconductor film 108a2, It is preferable to reduce the hydrogen concentration of a1 and the oxide semiconductor film 108a3. The hydrogen concentrations of 108a1 and oxide semiconductor film 108a3 are 2 × 10⁻¹⁰ in SIMS. 2 0 atoms / cm 3 The following is preferably 5 × 10 19 atoms / cm 3 The following are more preferred Or 1 x 10 19 atoms / cm 3 More preferably 5 × 10 18 atoms / cm 3 The following applies. In addition, in order to reduce the nitrogen concentration of the oxide semiconductor film 108a2, acid It is preferable to reduce the nitrogen concentration of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3. The nitrogen concentrations of the oxide semiconductor film 108a1 and the oxide semiconductor film 108a3 are determined by SIMS to be less than 5×10 19 atoms / cm 3 , preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 , even more preferably less than 5 ×10 17 atoms / cm 3 or less.

[0084] The above three-layer structure is an example. For example, a two-layer structure without the oxide semiconductor film 108a1 or the oxide semiconductor film 108a3 may be used.

[0085] It is preferable to use a conductive film having the property of extracting oxygen from the oxide semiconductor film for the source electrode 110a and the drain electrode 110b. For example, as the conductive film having the property of extracting oxygen from the oxide semiconductor film, conductive films containing aluminum, titanium, chromium, nickel, molybdenum, tantalum, tungsten, etc. can be mentioned. tantalum, tungsten, etc. can be mentioned.

[0086] Due to the action of the conductive film having the property of extracting oxygen from the oxide semiconductor film, oxygen in the oxide semiconductor film may desorb, and oxygen vacancies may be formed in the oxide semiconductor film. The extraction of oxygen is more likely to occur at higher heating temperatures. Since there are several heating processes in the manufacturing process of the transistor, there is a high possibility that oxygen vacancies are formed in the region near the source electrode or the drain electrode of the oxide semiconductor film where they are in contact. Also, due to heating, oxygen vacancies may occur at the sites of the oxygen vacancies in the vicinity of the source electrode or the drain electrode of the oxide semiconductor film. Hydrogen can enter, causing the oxide semiconductor film to become n-type. Therefore, the source electrode and Due to the action of the drain electrode, the oxide semiconductor film and the source electrode or drain electrode are By reducing the resistance of the contact area, the on-resistance of the transistor can be reduced.

[0087] Note that transients with small channel lengths (e.g., 200nm or less, or 100nm or less) When creating a sta, the formation of the n-type region can cause a short circuit between the source and drain. Therefore, when forming a transistor with a small channel length, the source electrode is A conductive film having the property of moderately extracting oxygen from the oxide semiconductor film is used for the drain electrode. That's all that's needed. Examples of conductive films that have the property of moderately extracting oxygen include nickel, molybdenum, and Examples include conductive films containing butene or tungsten.

[0088] Also, transients with very small channel lengths (e.g., 40nm or less, or 30nm or less) When fabricating a sta, the source electrode and drain electrode are made from an oxide semiconductor film. A conductive film that does not extract oxygen should be used. Almost no oxygen is extracted from oxide semiconductor films. Examples of conductive films that do not pull out include tantalum nitride, titanium nitride, or ruthenium nitride. Examples include conductive films containing um. Furthermore, multiple types of conductive films can be laminated.

[0089] The gate insulating film 112 is made of aluminum oxide, magnesium oxide, silicon oxide, and nitrogen oxide. Silicon oxide, silicon nitride, silicon nitride, gallium oxide, germanium oxide, oxide Yttrium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and An insulating film containing one or more types of tantalum oxide may be used. Furthermore, the gate insulating film 112 is made of the above material. The materials may be layered. Furthermore, the gate insulating film 112 may contain lanthanum, nitrogen, and zirconium. These may be included as impurities.

[0090] The gate electrode 114 is made of aluminum, titanium, chromium, cobalt, nickel, copper, and Thorium, zirconium, molybdenum, ruthenium, silver, tantalum, tungsten, etc. A conductive film containing one or more selected types should be used.

[0091] The oxide insulating film 116 is made of aluminum oxide, magnesium oxide, silicon oxide, and nitrogen oxide. Silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, One or more elements selected from lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. An insulating film containing this material can be used.

[0092] Next, the method for fabricating transistors will be explained using Figures 2 to 4.

[0093] First, a base insulating film 102 is formed on the substrate 100 (see Figure 2(A)).

[0094] The underlayer insulating film 102 is formed by sputtering, chemical vapor deposition (CVD). vapor deposition) method, metal organic chemical deposition (MOCVD: Metal Organic CVD (Organic Chemical Vapor Deposition) method, Plasma Chemical Vapor Deposition (PECVD: Plasma-En Processed CVD method, Molecular Beam Epitaxy (MBE) m Epitaxy) method, Atomic Layer Deposition (ALD) method (Diagram) or pulsed laser deposition (PLD) method It may be formed by a (certain method). To reduce the damage caused by plasma, MO The CVD method or the ALD method is preferred.

[0095] Next, in order to planarize the surface of the base insulating film 102, CMP processing may be performed. CM By performing the CMP process, the average surface roughness (Ra) of the base insulating film 102 is set to 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. By setting Ra to be below the above-mentioned numerical values, the crystallinity of the oxide semiconductor film 108a may increase. Ra can be measured with an atomic force microscope (AFM: Atomic Force Microscope).

[0096] Next, by adding oxygen to the base insulating film 102, an insulating film containing excess oxygen may be formed The addition of oxygen may be performed by plasma processing or ion implantation method or the like. When the addition of oxygen is performed by the ion implantation method, for example, the acceleration voltage is set to 2 kV or more and 100 kV or less, and the dose amount is 5×10 14 ions / cm 2 or more and 5×10 16 ions / cm 2 or less, and that's fine.

[0097] Next, a conductive film 104a, a conductive film 104b, and a conductive film 104c are formed on the base insulating film 102 (see Fig. 2(B)). The conductive film 104a, the conductive film 104b, and the conductive film 104c may be formed by a sputtering method, a CVD method, a MOCVD method, a PECVD method, a MBE method, an ALD method, or a PLD method, and the same material as that of the gate electrode 114 can be used. To reduce the damage caused by plasma, the MOCVD method or the ALD method is preferred.

[0098] ​Next, on the underlayer insulating film 102, conductive film 104a, conductive film 104b and conductive film 104c An interlayer insulating film 105 is formed (see Figure 2(C)). The interlayer insulating film 105 is formed by sputtering. Using the following methods: CVD method, MOCVD method, PECVD method, MBE method, ALD method, or PLD method Then the film can be deposited. To reduce damage caused by plasma, use the MOCVD method or ALD. The method is preferred. CMP treatment may be performed to planarize the surface of the interlayer insulating film 105. By performing CMP treatment, the average surface roughness (Ra) of the interlayer insulating film 105 can be reduced to 1 nm or less, preferably. The Ra value should be 0.3 nm or less, and more preferably 0.1 nm or less. This can sometimes increase the crystallinity of the oxide semiconductor film 108a.

[0099] Next, the interlayer insulating film 105 has an opening 120a that reaches the conductive film 104b, and the conductive film 104c has an opening 120a that reaches the conductive film 104b. An opening 120b is formed, and an interlayer insulating film 106 is formed (see Figure 3(A)).

[0100] Next, an oxide semiconductor film 108a, a blocking film 108b and Blocking film 108c is processed by sputtering, CVD, MOCVD, PECVD, Formed using MBE, ALD, or PLD (see Figure 3(B)). To reduce the damage, the MOCVD method or ALD method is preferred. In this case, interlayer insulation The edge film 106 may be etched to a moderate degree. This makes it easier to cover the oxide semiconductor film 108a with the gate electrode 114 that will be formed later. Yes, it is possible. Furthermore, in order to miniaturize the transistor, the oxide semiconductor film 108a, Blocking A hard mask may be used when processing the 108b film and the 108c blocking film.

[0101] Also, when forming a stacked film including the oxide semiconductor film 108a, the oxide semiconductor film 108a1, the oxide semiconductor film 1 08a2, and the oxide semiconductor film 108a3, it is preferable to form each layer continuously without exposing it to the atmosphere .

[0102] In order to reduce the incorporation of impurities and form an oxide semiconductor film with high crystallinity, the oxide semiconductor film 108a is formed at a substrate temperature of 100°C or higher, preferably 150°C or higher, more preferably 2 00°C or higher. Also, the oxygen gas and argon gas used as the film-forming gas are highly purified gases with a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower. Note that a low impurity concentration and a low defect level density (less oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic .

[0103] After the formation of the oxide semiconductor film 108a, the blocking film 108b, and the blocking film 108c, a first heat treatment may be performed. The first heat treatment is performed at a temperature of 250°C or higher and 650°C or lower , preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas, or under reduced pressure. Also, the atmosphere of the first heat treatment is , after heat treatment in an inert gas atmosphere, it may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas to supplement the desorbed oxygen. By the first heat treatment, the crystallinity of the oxide semiconductor film 108a is enhanced, and further, impurities such as hydrogen and water can be removed from the oxide semiconductor film 108a, the underlying insulating film 102, and the interlayer insulating film 10 6 .

[0104] Note that after forming an opening in the interlayer insulating film, the oxide semiconductor film and the blocking film are formed​​​ However, this is not limited to the above, and an oxide semiconductor film and a blocking film are formed before opening an interlayer insulating film. It may form.

[0105] Next, electrical electrical contact occurs between the conductive film 104b and the interlayer insulating film 106 through the opening 120a provided in the interlayer insulating film 106. The source electrodes on the oxide semiconductor film 108a and the blocking film 108b are connected to the above, and oxide semiconductor film 108a and the blocking film 108b. The conductive film 104c passes through 110a and the opening 120b provided in the interlayer insulating film 106. It is electrically connected to and the oxide semiconductor film 108a and the blocking film 108c Form the rain electrode 110b (see Figure 3(C)). Source electrode 110a and drain Electrode 110b was processed using sputtering, CVD, MOCVD, PECVD, and MBE methods. The film can be deposited using the ALD method or PLD method. To reduce damage caused by plasma... The MOCVD method or ALD method is preferred. When etching the conductive film that will become the drain electrode 110b, the source electrode 110a and the drain electrode The upper end of electrode 110b may be rounded (have a curved surface). Also, source electrode 11 When etching the conductive film that will become 0a and the drain electrode 110b, the interlayer insulating film 106 It's okay if it's etched to a certain extent.

[0106] Next, on the oxide semiconductor film 108a, on the source electrode 110a, and on the drain electrode 110b A gate insulating film 112 is formed on top (see Figure 4(A)). The gate insulating film 112 is spa Tarting method, CVD method, MOCVD method, PECVD method, MBE method, ALD method, or PL The film should be deposited using the D method. To reduce damage caused by plasma, the MOCVD method is available. The ALD method is preferred.

[0107] Next, a gate electrode 114 is formed on the gate insulating film 112 (see Figure 4(B)).

[0108] Next, an oxide insulating film 116 is formed on the gate insulating film 112 and the gate electrode 114. (See Figure 4(C)). The oxide insulating film 116 was produced by sputtering, CVD, MBE, The film can be deposited using the ALD method or the PLD method.

[0109] Next, a second heat treatment may be performed. The second heat treatment is carried out under the same conditions as the first heat treatment. This can be done in one step. The second heat treatment reduces the oxygen vacancies in the oxide semiconductor film 108a. It may be possible to reduce it.

[0110] By following the above steps, the transistors shown in Figures 1(A) and 1(B) can be fabricated. ru.

[0111] <Modified Transistor Structure> Furthermore, as shown in Figure 5(A), the source electrode 110a and drain electrode Conductive films 118a and 118b are electrically connected to 110b and function as wiring. The conductive films 118a and 118b may be provided on the oxide insulating film 116. It may be electrically connected to elements such as transistors and capacitors.

[0112] Furthermore, as shown in Figure 5(B), the oxide semiconductor film 108a is made into a three-layer structure. On the interlayer insulating film, oxide semiconductor film 108a1, oxide semiconductor film 108a2, blocking Film 108b1, blocking film 108b2, blocking film 108c1, and block A sizing film 108c2 is provided, and an oxide semiconductor film 108a3 is placed on the source electrode and drain electrode. It may be configured to provide. Also, the oxide semiconductor film 108a3 and the gate insulating film may be etched using the gate electrode as a mask.

[0113] <Modified Example of Transistor Structure> Also, a channel protection film 128 may be provided on the oxide semiconductor film 108a as in the transistor shown in FIG. 10. By providing the channel protection film 128, the oxide semiconductor film 108a is not exposed to the etching gas, and impurities between the oxide semiconductor film 108a and the channel protection film 128 can be reduced. As a result, the leakage current flowing between the source electrode and the drain electrode of the transistor can be reduced.

[0114] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0115] (Embodiment 2) In the present embodiment, a semiconductor device different from that of Embodiment 1 will be described with reference to the drawings.

[0116] FIGS. 6(A) and 6(B) are a top view and a cross-sectional view of a transistor according to an aspect of the present invention. FIG. 6(A) is a top view, and the cross-section along the dashed-dotted line B1 - B2 shown in FIG. 6(A) corresponds to FIG. 6 (B). In the top view of FIG. 6(A), some elements are omitted for clarity of the drawing. Also, the direction of the dashed-dotted line B1 - B2 may be referred to as the channel length direction, and the direction perpendicular to the dashed-dotted line B1 - B 2 may be referred to as the channel width direction.

[0117] The transistor 250 shown in FIGS. 6(A) and 6(B) includes an underlying insulating film 102 on the substrate 100, a gate electrode 114 on the underlying insulating film 102, and the underlying insulating film 102 and the gate electrode ​​​​​​​The gate insulating film 112 on the pole 114, and the source electrode 110a and on the gate insulating film 112 Drain electrode 110b, gate insulating film 112, source electrode 110a and drain electrode Oxide semiconductor film 108a on 110b and blocking film 108 on source electrode 110a b, the blocking film 108c on the drain electrode 110b, the source electrode 110a, drain In electrode 110b, oxide semiconductor film 108a, blocking film 108b and blocking An interlayer insulating film 106 on the film 108c, a conductive film 104a on the interlayer insulating film 106, and an interlayer insulating film The source electrode 110a is electrically connected through the opening 120a provided in the edge film 106. Furthermore, the conductive film 104b on the interlayer insulating film 106 and the opening 1 provided in the interlayer insulating film 106 The drain electrode 110b is electrically connected via 20b, and the conduction on the interlayer insulating film 106 It has an electrical film 104c.

[0118] The blocking film 108b is closer to the oxide semiconductor film 108a than the aperture 120a, that is The distance between the blocking film 108b and the oxide semiconductor film 108a is such that the opening 120a and the oxide The distance to the semiconductor film 108a is shorter than the distance to the aperture 120b. Similarly, the blocking film 108c is shorter than the distance to the aperture 120b. It is closer to the oxide semiconductor film 108a, that is, the blocking film 108c and the oxide semiconductor film The distance to 108a is shorter than the distance between the aperture 120b and the oxide semiconductor film 108a.

[0119] By providing a blocking membrane as described above, hydrogen and other substances that enter from other layers through the openings can be prevented. By adsorbing impurities with a blocking film, impurities can penetrate into the oxide semiconductor film. Because it has a function to suppress [unclear], it can suppress defects in the electrical characteristics of semiconductor devices.

[0120] Furthermore, the blocking film is formed on the same surface using the same material as the oxide semiconductor film. This allows for the formation of a blocking film without increasing the number of steps in the process. This is not limited to the above; blocking films include oxide semiconductor films, source electrodes (or drain electrodes). It may be made of different materials.

[0121] Because blocking films adsorb impurities such as hydrogen, they have a higher concentration of impurities compared to oxide semiconductor films. The degree is high. Therefore, blocking films have higher conductivity compared to oxide semiconductor films.

[0122] Next, the method for fabricating transistors will be explained using Figures 7 to 9.

[0123] First, a base insulating film 102 is formed on the substrate 100 (see Figure 7(A)). The materials and manufacturing method for 02 can be referenced to Embodiment 1.

[0124] Next, a gate electrode 114 is formed on the underlying insulating film 102 (see Figure 7(B)). The material and manufacturing method of electrode 114 can be found in reference to Embodiment 1.

[0125] Next, a gate insulating film 112 is formed on the underlayer insulating film 102 and the gate electrode 114. See Figure 7(C). The material and method of fabricating the gate insulating film 112 shall be as described in Embodiment 1. It is possible.

[0126] Next, the source electrode 110a and the drain electrode 110b are formed on the gate insulating film 112. (See Figure 8(A)). Materials of source electrode 110a and drain electrode 110b and The manufacturing method can be described in Embodiment 1.

[0127] Next, oxidation is performed on the gate insulating film 112, source electrode 110a, and drain electrode 110b. A monosemiconductor film 108a, a blocking film 108b, and a blocking film 108c are formed. (See Figure 8(B)). Oxide semiconductor film 108a, blocking film 108b and block The material and method for producing the coating film 108c can be found in reference to Embodiment 1.

[0128] Furthermore, the oxide semiconductor film 108a is defined as oxide semiconductor film 108a1, oxide semiconductor film 1 When forming a multilayer film including 08a2 and oxide semiconductor film 108a3, each layer is exposed to the atmosphere. It is preferable to deposit the film continuously without allowing it to come into contact with the surface.

[0129] Shapes of oxide semiconductor film 108a, blocking film 108b, and blocking film 108c A first heat treatment may be performed after maturation. For details of the first heat treatment, please refer to Embodiment 1. It is possible.

[0130] Next, oxide semiconductor film 108a, blocking film 108b, blocking film 108c, An interlayer insulating film 105 is formed on the source electrode 110a and the drain electrode 110b (Figure 8). (See (C)). The material and method of preparing the interlayer insulating film 105 may be described with reference to Embodiment 1. can.

[0131] Next, the interlayer insulating film 105 has an opening 120a that reaches the source electrode 110a, and a drain electrode An opening 120b reaching 110b is formed, and an interlayer insulating film 106 is formed (see Figure 9(A)). (see).

[0132] Next, the conductive film 104a on the interlayer insulating film 106 and the opening provided in the interlayer insulating film 106 It is electrically connected to the source electrode 110a via 120a, and the conductor on the interlayer insulating film 106 The film 104b and the drain electrode 1 are connected via the opening 120b provided in the interlayer insulating film 106. It is electrically connected to 10b and forms with the conductive film 104c on the interlayer insulating film 106. See Figure 9(B). Conductive films 104a, 104b, and 104c are in their respective forms. State 1 can be taken into consideration.

[0133] Next, a second heat treatment may be performed. The second heat treatment is carried out under the same conditions as the first heat treatment. This can be done in one step. The second heat treatment reduces the oxygen vacancies in the oxide semiconductor film 108a. It may be possible to reduce it.

[0134] By following the above steps, the transistor shown in Figure 6 can be fabricated.

[0135] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0136] (Embodiment 3) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. See the explanation below.

[0137] [Cross-sectional structure] Figure 11(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. The device has a transistor 2200 made of a first semiconductor material at the bottom and a second at the top It has a transistor 2100 made of semiconductor material. Figure 11(A) shows the second semiconductor As the transistor 2100 using a solid material, the transistor exemplified in Embodiment 1 is suitable Examples of its use are shown.

[0138] It is preferable that the first and second semiconductor materials have different band gaps. For example, if the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon, germanium) (e.g., silicon germanium, silicon carbide, or gallium arsenide), and the second semiconductor The main material can be an oxide semiconductor. Other materials besides oxide semiconductors include single-crystal silicon Transistors using materials such as semiconductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors Transistors have a low off-current.

[0139] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either transistor will work; the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses an oxide semiconductor, the materials and structure used are different. It is not necessary to limit the specific configuration of semiconductor devices shown here to those examples.

[0140] In the configuration shown in Figure 11(A), an insulating film 2201 and an insulating film are placed on top of the transistor 2200. Transistor 2100 is provided via film 2207. Also, transistor 220 Multiple wires 2202 are provided between 0 and transistor 2100. Multiple plugs 2203 embedded in the insulating film provide the upper and lower layers respectively The wires and electrodes are electrically connected. Also, the insulating film 2204 covers the transistor 2100. Then, the wiring 2205 is placed on the insulating film 2204, and the same conductive material is used for the pair of electrodes of the transistor 2100. A wiring 2206 obtained by processing an electrical film is provided.

[0141] In this way, stacking two types of transistors reduces the circuit footprint. This allows for the arrangement of multiple circuits at a higher density.

[0142] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer... The hydrogen in the insulating film provided near the semiconductor film of transistor 2200 is a silicon dumbbell. This terminates the Gring bond and improves the reliability of transistor 2200. When an oxide semiconductor is used for the transistor 2100 located in the upper layer, transistor 2 Hydrogen in the insulating film placed near the 100 semiconductor film generates carriers in the oxide semiconductor. This is one of the contributing factors, and therefore a factor that reduces the reliability of transistor 2100. There is a compatibility. Therefore, acid is present in the upper layer of transistor 2200 using silicon-based semiconductor material. When stacking transistors 2100 using a synthetic semiconductor, hydrogen is expanded between them. Providing an insulating film 2207 that has the function of preventing dispersion is particularly effective. By trapping hydrogen in the lower layer, the reliability of transistor 2200 is improved. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, which is why transistor 2100 This also allows for an improvement in reliability.

[0143] Examples of insulating film 2207 include aluminum oxide, aluminum oxide nitride, and gallium oxide. Um, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxidizride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0144] Furthermore, the transistor 2100, which is composed of an oxide semiconductor film, is covered by the transistor A dielectric film 2208 having the function of preventing hydrogen diffusion is formed on the zista 2100. Preferred. The insulating film 2208 can be made of the same material as insulating film 2207. In particular, it is preferable to apply aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, etc. It has a high blocking effect, preventing the passage of both impurities and oxygen through the membrane. Therefore, an aluminum oxide film is used as the insulating film 2208 covering the transistor 2100. By using this, the desorption of oxygen from the oxide semiconductor film contained in transistor 2100 is prevented. This also prevents water and hydrogen from entering the oxide semiconductor film.

[0145] [Circuit Configuration Example] In the above configuration, the connection configuration of the electrodes of transistor 2100 and transistor 2200 is By varying the parameters, various circuits can be constructed. The following describes one aspect of the present invention. This section describes an example of a circuit configuration that can be realized using semiconductor equipment.

[0146] [CMOS circuit] The circuit diagram shown in Figure 11(B) is a p-channel type transistor 2200 and an n-channel type This is a so-called CM configuration, where two transistors 2100 are connected in series, and their gates are connected. This shows the configuration of the OS circuit.

[0147] [Analog switch] Furthermore, the circuit diagram shown in Figure 11(C) is for transistors 2100 and 2200. This shows a configuration where each source and drain is connected. It can function as a so-called analog switch.

[0148] [Examples of storage devices] Using a transistor according to one aspect of the present invention, the stored contents can be stored even when power is not supplied. Figure 1 shows an example of a semiconductor device (memory device) that can retain data and has no limit on the number of write cycles. As shown in 2.

[0149] The semiconductor device shown in Figure 12(A) is a transistor 3200 using a first semiconductor material and It has a transistor 3300 and a capacitive element 3400 made of a second semiconductor material. Furthermore, the transistor 3300 is the transistor described in the above embodiment. It is possible.

[0150] Transistor 3300 is a transistor in which a channel is formed in a semiconductor film having an oxide semiconductor. It is a transistor. The 3300 transistor is used because it has a low off-current. It is possible to retain memory content for a longer period of time. In other words, refresh operations are unnecessary. To create a semiconductor memory device that does not require refresh operations, or one that requires extremely infrequent refresh operations. This makes it possible to significantly reduce power consumption.

[0151] In Figure 12(A), the first wiring 3001 is connected to the source electrode of transistor 3200. The second wire 3002 is electrically connected to the drain electrode of transistor 3200. They are connected. Also, the third wire 3003 is the source electrode of transistor 3300 or Electrically connected to one of the drain electrodes, the fourth wire 3004 is connected to transistor 3300. It is electrically connected to the gate electrode of transistor 3200. The source electrode or drain electrode of transistor 3300, and the other side of the source electrode, are connected to capacitive element 3400. The fifth wire 3005 is electrically connected to one of the electrodes of the capacitive element 3400, and the fifth wire 3005 is electrically connected to the other electrode of the capacitive element 3400. It is electrically connected to it.

[0152] In the semiconductor device shown in Figure 12(A), the potential of the gate electrode of transistor 3200 is maintained. By taking advantage of this capability, it is possible to write, store, and read information as follows: be.

[0153] The writing and retention of information will be explained. First, the potential of the fourth wiring 3004 is set to The potential is set to turn on transistor 3300, thereby turning on transistor 3300. This causes the potential of the third wiring 3003 to be the gate electrode of transistor 3200. And is supplied to the capacitance element 3400. That is, the gate electrode of transistor 3200 is supplied Then, a predetermined charge is applied (written). Here, two different potential levels are given by electricity. A charge (hereinafter referred to as Low-level charge or High-level charge) is given to a device Then, the potential of the fourth wiring 3004 is set to the point where transistor 3300 is in the off state. By setting it to the OFF state, transistor 3300 is turned OFF. The charge applied to the gate electrode is retained (held).

[0154] Because the off-current of transistor 3300 is extremely small, the gate of transistor 3200 The charge on the electrodes is retained for a long period of time.

[0155] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. When the appropriate potential (readout potential) is applied to the fifth wiring 3005 while the current is being applied, the transient Depending on the amount of charge held at the gate electrode of terminal 3200, the second wiring 3002 will have different powers. To take a position. Generally, if transistor 3200 is an n-channel type, then transistor 320 Apparent threshold V when a high level charge is applied to a terminal station with zero charge. th_ HThis is the case when a low level charge is applied to the gate electrode of transistor 3200. The threshold value V th_L This is because it becomes lower. Here, the apparent threshold voltage is The potential of the fifth wire 3005, which is necessary to turn on transistor 3200, Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L During By setting the potential V0, the charge applied to the gate electrode of transistor 3200 can be determined. They can be separated. For example, in the case of writing, if a high-level charge is given, The potential of the fifth wire 3005 is V0 (>V th_H ) In that case, transistor 3200 is " It becomes "on". If a low-level charge is applied, the fifth wiring 3005 The potential is V0( <V th_L Even if this happens, transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the information being held can be read. It is possible to break free.

[0156] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell can be read. It becomes necessary to be able to extract the information. If the information is not read in this way, the state of the gate electrode Regardless, the potential at which transistor 3200 is in the "off state" is V th_ H A smaller potential should be applied to the fifth wire 3005. Alternatively, depending on the state of the gate electrode... The potential at which transistor 3200 remains "on" is, that is, V th_L Yo A larger potential should be applied to the fifth wiring 3005.

[0157] The semiconductor device shown in Figure 12(B) is mainly similar to Figure 1 in that it does not have transistor 3200. This differs from 2(A). In this case, information is written and retained using the same operation as described above. It is operational.

[0158] Next, we will explain how to read the information. When transistor 3300 is turned ON, The third wiring 3003, which is in a floating state, and the capacitive element 3400 are electrically connected, and the third wiring 3003 The charge is redistributed between the capacitor and the capacitive element 3400. As a result, the potential of the third wiring 3003 is It changes. The amount of change in the potential of the third wiring 3003 is equal to the potential of one of the electrodes of the capacitive element 3400. It takes on different values ​​depending on (or the charge stored in the capacitive element 3400).

[0159] For example, let V be the potential of one electrode of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and The capacitive component of the third wiring 3003 is CB, and the third wiring 3003 before the charge is redistributed. If the potential of is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB The formula becomes (×VB0+C×V) / (CB+C). Therefore, the state of the memory cell is capacity If one of the electrodes of element 3400 takes on two states, V1 and V0 (V1 > V0), The potential of the third wiring 3003 when the potential V1 is maintained is (=(CB×VB0+C×V1 ) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=( It can be seen that this is higher than (CB × VB0 + C × V0) / (CB + C)).

[0160] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information can be read out. It is possible.

[0161] In this case, the first semiconductor material described above is applied to the drive circuit for driving the memory cell. Using a transistor, a second semiconductor material was applied to transistor 3300. The inverters can be stacked on top of the drive circuit.

[0162] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-voltage applications. By using transistors with extremely low current, it is possible to retain memory content for extremely long periods of time. It is possible to do so. In other words, a refresh operation will become unnecessary, or a refresh will be required. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. It is possible. Also, in the absence of power supply (however, it is desirable that the potential be fixed). Even if memory is impaired, it is possible to retain the contents of that memory over a long period of time.

[0163] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information. There are no issues with element degradation. For example, unlike conventional non-volatile memory, floating-point memory... Because there is no need to inject electrons into the gate or extract electrons from the floating gate. Furthermore, problems such as degradation of the gate insulating film do not occur at all. In other words, semiconductor according to the disclosed invention In this device, there is no limitation on the number of rewrite cycles, which is a problem with conventional non-volatile memory. Reliability improves dramatically. Furthermore, information is obtained depending on the on and off states of the transistor. Because data is written to the system, high-speed operation can be easily achieved.

[0164] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0165] (Embodiment 4) In this embodiment, R includes the transistor or memory device described in the previous embodiment. The F tag will be explained with reference to Figure 13.

[0166] The RF tag in this embodiment has a memory circuit inside, and the memory circuit records the necessary information. This involves using contactless means, such as wireless communication, to exchange information with the outside world. Based on these characteristics, RF tags identify items by reading individual information about those items. It can be used in individual authentication systems, etc. However, to use it for these purposes... Extremely high reliability is required.

[0167] The configuration of an RF tag will be explained using Figure 13. Figure 13 shows an example of an RF tag configuration. This is a block diagram.

[0168] As shown in Figure 13, the RF tag 800 is connected to the communicator 801 (interrogator, reader / writer, etc.) An antenna that receives a radio signal 803 transmitted from antenna 802 connected to (also known as) It has 804. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit. It has a path 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, ensure that sufficient reverse current is supplied to the rectifying transistor included in the demodulation circuit 807. A configuration using a material capable of suppressing this, such as an oxide semiconductor, may also be used. This suppresses the decrease in rectification effect caused by reverse current and prevents the output of the demodulation circuit from saturating. This prevents the following: In other words, it makes the output of the demodulation circuit closer to linear with respect to the input of the demodulation circuit. This is possible. The data transmission method involves placing a pair of coils opposite each other and transmitting signals through mutual induction. Electromagnetic coupling methods for communication, electromagnetic induction methods for communication using induced electromagnetic fields, and communication using radio waves. It can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment does not use any of these. It can also be used in the system.

[0169] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with the antenna 802. Also, a rectifier circuit... 805 processes the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is then smoothed by a capacitive element placed in the subsequent stage. This is a circuit for generating input potential by smoothing. Note that the input side of the rectifier circuit 805... Alternatively, a limiter circuit may be provided on the output side. A limiter circuit controls the amplitude of the input AC signal. When the internally generated voltage is high, do not input power above a certain level to the subsequent circuit. This is a circuit for controlling it in that way.

[0170] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is the circuit. Note that the constant voltage circuit 806 has a reset signal generation circuit inside. Good. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 8. This is a circuit for generating the 09 reset signal.

[0171] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 is used to process the data output from the antenna 804. This is a circuit for modulating accordingly.

[0172] The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is It is a circuit that holds the input information, such as a row decoder, column decoder, and memory area. It has the following. Furthermore, ROM811 stores a unique number (ID), etc., and outputs according to the processing. This is the circuit for performing the action.

[0173] Furthermore, the circuits described above can be selected or omitted as needed.

[0174] Here, the memory device described in the previous embodiment can be used in the memory circuit 810. A storage device according to one aspect of the present invention can retain information even when the power supply is cut off. It can be suitably used in RF tags. Furthermore, a storage device according to one aspect of the present invention is suitable for data Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to eliminate the difference in the maximum communication distance between data reading and writing. This suppresses malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0175] Furthermore, a storage device according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will need to provide the ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Therefore, instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. This makes it possible to assign a unique number to each individual product, preventing discontinuity in the unique numbers of products after shipment. This eliminates the need for customer management after product shipment, making it easier to handle customer issues related to the product.

[0176] This embodiment may be appropriately combined with other embodiments described herein, at least in part. They can be implemented in combination.

[0177] (Embodiment 5) In this embodiment, at least the transistors described in the above embodiment are used. Next, we will describe a CPU that includes the memory device described in the previous embodiment.

[0178] Figure 14 shows a CPU that uses at least some of the transistors described in the previous embodiment. This is a block diagram showing an example of a configuration.

[0179] The CPU shown in Figure 14 is an ALU1191 (ALU: Arithmetic) mounted on board 1190. tic logic unit (arithmetic circuit), ALU controller 1192, instruction Action decoder 1193, interrupt controller 1194, timing controller R1195, Register 1196, Register Controller 1197, Bus Interface 1198 (Bus I / F), rewritable ROM1199, and ROM interface It has a face 1189 (ROM I / F). The substrate 1190 is a semiconductor substrate, SOI A circuit board, glass substrate, etc. are used. ROM1199 and ROM interface1189 This may be provided on a separate chip. Of course, the CPU shown in Figure 14 has a simplified configuration. This is just one example; actual CPUs have a wide variety of configurations depending on their application. For example, a configuration including the CPU or arithmetic circuit shown in Figure 14 is considered one core, and multiple such cores are... It is also possible to configure the CPU so that each core operates in parallel. The number of bits that can be handled by arithmetic circuits and data buses is, for example, 8 bits, 16 bits, 32 bits, 6 bits. It can be set to 4 bits, for example.

[0180] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to the decoder 1193, decoded, and then sent to the ALU controller 1192. Trap controller 1194, register controller 1197, timing controller This is entered into Ra1195.

[0181] ALU controller 1192, interrupt controller 1194, register controller The driver 1197 and timing controller 1195 perform various operations based on the decoded instructions. It performs control. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal to do so. In addition, the interrupt controller 1194 generates a signal to the CPU's program. During RAM execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and mass. The system determines and processes based on the state. The register controller 1197 processes the state of register 1196. The system generates a dress and reads or writes to register 1196 depending on the CPU state.

[0182] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 11 92, Instruction decoder 1193, Interrupt controller 1194, It generates signals to control the timing of the operation of the register controller 1197. The timing controller 1195 uses the reference clock signal CLK1 to determine the internal clock signal It is equipped with an internal clock generation unit that generates the CLK2 signal, and the internal clock signal CLK2 is raised It supplies power to the various circuits listed.

[0183] In the CPU shown in Figure 14, a memory cell is located in register 1196. The transistor shown in the previous embodiment can be used as the memory cell of TA1196. Cut.

[0184] In the CPU shown in Figure 14, the register controller 1197 receives from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 1 In the memory cell of 196, data is retained by a flip-flop, or Select whether to use quantitative elements for data retention. (Data retention using flip-flops) If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, the data will not be rewritten to the capacitive element. This process can be performed to stop the supply of power voltage to the memory cell in register 1196. ru.

[0185] Figure 15 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data volatilizes when the power is cut off, and a memory element 1200 that volatilizes when the power is cut off. Circuit 1202 that prevents data loss, switch 1203, switch 1204, and logic It comprises element 1206, capacitive element 1207, and a circuit 1220 having a selection function. The path 1202 is connected to the capacitive element 1208, transistor 1209, and transistor 1210. , has. The memory element 1200 may include a diode, a resistor, an industrial diode as needed. It may also have other elements such as connectors.

[0186] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 12 of circuit 1202 The gate of transistor 09 is input to ground potential (0V) or the potential that turns off transistor 1209. The configuration will continue to be such that the gate of transistor 1209 is connected via a load such as a resistor. The configuration will be grounded.

[0187] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The configuration is such that the switch 1204 has a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example is shown using transistor 1214. Here, the first of switch 1203 The terminals correspond to one of the source and drain terminals of transistor 1213, and the other terminal of switch 1203. Terminal 2 corresponds to the source and drain of transistor 1213, and switch 1203 The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. The continuity or non-continuity between the terminals (i.e., the ON or OFF state of transistor 1213) The state is selected. The first terminal of switch 1204 is connected to the source and dot of transistor 1214. Corresponding to one side of the rain, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of transistor 1214 is selected.

[0188] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One of them is electrically connected to the gate of transistor 1210. Here, the connection Let the section be node M2. One of the sources and drains of transistor 1210 is connected to the low power supply. It is electrically connected to a wire that can supply a value (e.g., a GND wire), and the other is a switch The first terminal of transistor 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminals of switch 1203 (source and drain of transistor 1213) are connected. The other side is the first terminal of switch 1204 (source and drain of transistor 1214) The second terminal of switch 1204 (of transistor 1214) is electrically connected to the other terminal. The source and drain (the other side) are electrically connected to wiring capable of supplying the power potential VDD. The second terminal of switch 1203 (in addition to the source and drain of transistor 1213) is used. (one side) and the first terminal of switch 1204 (one side of the source and drain of transistor 1214) (one side) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207 , are electrically connected. Here, the connection point is called node M1. The other electrode in a pair can be configured to receive a constant potential input. For example, low The configuration can be configured to receive either a power supply potential (GND, etc.) or a high power supply potential (VDD, etc.) as input. The other electrode of the pair of electrodes of the capacitive element 1207 is capable of supplying a low power supply potential. It is electrically connected to the wiring (e.g., the GND wire). Of the pair of electrodes of the capacitive element 1208 The other configuration can be one in which a constant potential is input. For example, a low power supply potential (GND). The configuration can be such that a high power supply potential (VDD, etc.) is input. Capacitive element 12 The other of the pair of electrodes in 08 is a wire capable of supplying a low power potential (e.g., GN It is electrically connected to the D line.

[0189] Capacitive elements 1207 and 1208 are used to reduce parasitic capacitance in transistors and wiring, etc. It is also possible to omit this by actively using [a specific method / technique].

[0190] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal R than control signal WE. D selects a conductive or non-conductive state between the first terminal and the second terminal, and one of them When there is conductivity between the first and second terminals of one switch, the first terminal of the other switch and The second terminal becomes non-conductive.

[0191] The source and drain of transistor 1209 are connected to the data held by circuit 1201. A signal corresponding to the traffic signal is input. In Figure 15, the signal output from circuit 1201 is the traffic signal. An example is shown where the source and drain of the inverter 1209 are input to the other side. Switch 1203 The signal output from the second terminal (the other of the source and drain of transistor 1213) is The logic value is inverted by the logic element 1206, becoming an inverted signal, and then transmitted through the circuit 1220. This is then input to circuit 1201.

[0192] Note that in Figure 15, the second terminal of switch 1203 (the source of transistor 1213 and The signal output from the other side of the drain is transmitted via logic element 1206 and circuit 1220. An example of input to circuit 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from the child (the other side of the source and drain of transistor 1213) is the logical value It may be input to circuit 1201 without being inverted. For example, in circuit 1201 In the case where there exists a node that holds a signal inverted from the logical value of the signal input from the input terminal In addition, the second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from ) can be input to the node in question.

[0193] Furthermore, in Figure 15, among the transistors used in the memory element 1200, The transistors other than STA1209 are made of a layer or substrate 11 made of a semiconductor other than an oxide semiconductor. A transistor can be formed with a channel at 90. For example, a silicon layer or This can be a transistor in which a channel is formed on a silicon substrate. All transistors used in the child 1200 have channels formed from oxide semiconductor films. It can also be a transistor. Alternatively, the memory element 1200 is a transistor 1209 or higher. In addition, it may include transistors in which the channel is formed of an oxide semiconductor film, and the rest The transistor has a channel formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be considered a transistor.

[0194] In Figure 15, circuit 1201 can be, for example, a flip-flop circuit. Furthermore, the logic element 1206 can be, for example, an inverter or a clocked inverter. It is possible.

[0195] In one aspect of the present invention, a power supply voltage is not supplied to the memory element 1200. During this process, the data stored in circuit 1201 is transferred to the capacitive element 12 provided in circuit 1202. It can be held by 08.

[0196] Furthermore, transistors with channels formed in oxide semiconductor films exhibit extremely low off-currents. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor film depends on the crystalline properties. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. Therefore, by using the transistor as transistor 1209, the memory element Even when power voltage is not supplied to 1200, the signal held in the capacitive element 1208 will remain for a long period of time. The memory element 1200 retains its stored contents even when the power supply voltage is interrupted. It is possible to retain data.

[0197] Furthermore, by providing switches 1203 and 1204, pre-charge Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, circuit 1201 This can shorten the time it takes to re-store the original data.

[0198] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is a transistor It is input to the gate of TA 1210. Therefore, the power supply voltage to memory element 1200 is restored. After opening, the signal held by the capacitive element 1208 is transmitted to the state of transistor 1210. It can be converted to (on state or off state) and read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal remains. It is possible to read the issue number accurately.

[0199] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. It is possible to restore the system to its state before the power supply was interrupted in a short time after the power supply voltage is restored. Therefore, it can be attributed to the entire processor, or to one of the components of the processor. Alternatively, in multiple logic circuits, power can be shut off even for a short time, thus reducing power consumption. It can suppress this.

[0200] In this embodiment, the memory element 1200 was described as an example of being used in a CPU, but the memory element 1200 is a DSP (Digital Signal Processor), custom LSI, PLD (Programmable Logic Device), etc. It can also be applied to RF (Radio Frequency) devices.

[0201] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0202] (Embodiment 6) This embodiment describes an example of the configuration of a display panel according to one aspect of the present invention.

[0203] [Example Configuration] Figure 19(A) is a top view of a display panel according to one embodiment of the present invention, and Figure 19(B) is a top view of a display panel according to one embodiment of the present invention. A pixel circuit that can be used when applying liquid crystal elements to the pixels of a display panel in one embodiment of the present invention. This is a circuit diagram to explain the present invention. Also, Figure 19(C) shows a display panel according to one embodiment of the present invention. A circuit diagram illustrating a pixel circuit that can be used when applying organic EL elements to pixels. This is a diagram.

[0204] The transistors placed in the pixel area can be formed according to the above embodiment. Furthermore, since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A portion of the drive circuit, which can be constructed using Nell-type transistors, is the same as the transistors in the pixel section. It is formed on a single substrate. In this way, the pixel portion and the drive circuit are formed using the transistors shown in the above embodiment. By using this technology, a highly reliable display device can be provided.

[0205] An example of a block diagram of an active-matrix display device is shown in Figure 19(A). On the substrate 700 are a pixel section 701, a first scan line drive circuit 702, and a second scan line drive circuit. It has a path 703 and a signal line drive circuit 704. Multiple signal lines are driven by the signal line drive circuit in the pixel section 701. Extending from the drive circuit 704, multiple scan lines are arranged in the first scan line drive circuit 702, It is arranged as an extension from the second scan line drive circuit 703. Note the intersection of the scan line and signal line. Each region has pixels, each containing a display element, arranged in a matrix. The circuit board 700 is a connecting FPC (Flexible Printed Circuit) and the like. It is connected via a connecting part to a timing control circuit (also called a controller or control IC). ru.

[0206] Figure 19(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal The line drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, externally Since the number of components such as drive circuits is reduced, costs can be lowered. 700 If an external drive circuit is installed, it becomes necessary to extend the wiring, increasing the number of connections between wires. It is possible to reduce the number of connections between the wiring when the drive circuit is placed on the same circuit board 700. This can lead to improved reliability or increased yield.

[0207] [LCD panel] Furthermore, an example of the pixel circuit configuration is shown in Figure 19(B). Here, a VA-type liquid crystal display panel is shown. This shows a pixel circuit that can be applied to the pixels.

[0208] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to be movable. This allows for the individual images of pixels in a multi-domain design. The signals applied to the elementary electrode layer can be controlled independently.

[0209] The gate wiring 712 of transistor 716 and the gate wiring 713 of transistor 717 These are separated so that different gate signals can be applied. On the other hand, the data line is The source electrode layer or drain electrode layer 714 that functions is connected to the transistor 716. It is commonly used in transistor 717. Transistors 716 and 717 are implemented as described above. A transistor described in the form described can be used as appropriate. This allows for a highly reliable liquid A crystal display panel can be provided.

[0210] A first pixel electrode layer electrically connected to transistor 716, and a transistor 717 and an electric The shape of the second pixel electrode layer, which is electrically connected to the first pixel electrode layer, will be described. The shape of the elementary electrode layers is separated by slits. The first pixel electrode layer extends in a V-shape. The second pixel electrode layer has a shape such that it surrounds the outside of the first pixel electrode layer.

[0211] The gate electrode of transistor 716 is connected to gate wiring 712, and transistor 717 The gate electrode is connected to gate wiring 713. Gate wiring 712 and gate wiring 71 By applying different gate signals to 3, the operating timing of transistors 716 and 717 can be determined. By changing the angle, the alignment of the liquid crystals can be controlled.

[0212] Furthermore, the capacitive wiring 710, the gate insulating film which functions as a dielectric, and the first pixel electrode layer Alternatively, a retaining capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0213] The multi-domain structure comprises a first liquid crystal element 718 and a second liquid crystal element 719 in each pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. It can be done.

[0214] Note that the pixel circuit shown in Figure 19(B) is not limited to this. For example, Figure 19(B) A new switch, resistor, capacitive element, transistor, sensor, or logic circuit is added to the indicated pixel. You may add things like this.

[0215] [OLED panel] Another example of a pixel circuit configuration is shown in Figure 19(C). Here, a table using an organic EL element is shown. The pixel structure of the display panel is shown.

[0216] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected from the other side into layers containing luminescent organic compounds, and an electric current flows. Then, through the recombination of electrons and holes, the luminescent organic compound forms an excited state. It emits light when the excited state returns to the ground state. From this mechanism, such emission Optical devices are called current-excited light-emitting devices.

[0217] Figure 19(C) shows an example of an applicable pixel circuit. Here, an n-channel type is shown. An example of using two transistors in one pixel is shown. Note that the metal oxide film according to one aspect of the present invention This can be used in the channel formation region of an n-channel transistor. The pixel circuit can be fitted with digital time-based grayscale driving.

[0218] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0219] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light emitter. It has element 724 and capacitive element 723. The switching transistor 721 is The source electrode layer is connected to scan line 726, and the first electrode (source electrode layer and drain electrode layer) is connected to scan line 726. The other side is connected to the signal line 725, and the second electrode (the other side of the source electrode layer and drain electrode layer) It is connected to the gate electrode layer of the drive transistor 722. (Driver transistor 722) In this configuration, the gate electrode layer is connected to the power line 727 via a capacitive element 723, and the first electrode is connected to the power line It is connected to 727, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is on the same substrate. It is electrically connected to the common potential line formed above.

[0220] The switching transistor 721 and the driving transistor 722 are as described above. The transistors described below can be used as appropriate. This allows for highly reliable organic LEDs. A display panel can be provided.

[0221] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. Low power supply potential is a potential lower than the high power supply potential set on power line 727, for example, GN D, 0V, etc. can be set as low power supply potentials. The forward direction of the light-emitting element 724 The high and low power supply potentials are set so that the voltage is greater than or equal to a certain value, and the potential difference between them is used by the light-emitting element 72 By applying a current to 4, the light-emitting element 724 is made to emit light. The forward voltage of 24 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage.

[0222] Furthermore, the capacitive element 723 is used by substituting the gate capacitance of the drive transistor 722. This can be omitted. Regarding the gate capacitance of the drive transistor 722, the channel formation region and the gate A capacitance may be formed between the electrode layer and the electrode layer.

[0223] Next, we will explain the signal input to the drive transistor 722. Voltage input, voltage drive. In this method, the drive transistor 722 is either fully on or completely off. A video signal is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for driving it. It is applied to the gate electrode layer of transistor 722. Also, the signal line 725 is subjected to the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of the dynamic transistor 722.

[0224] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 7 A voltage greater than or equal to the sum of the forward voltage of transistor 24 and the threshold voltage Vth of the drive transistor 722. Apply the signal. Also, input the video signal so that the drive transistor 722 operates in the saturation region. Then, current is passed to the light-emitting element 724. Also, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, a current corresponding to the video signal is supplied to the light-emitting element 724. Furthermore, it can perform analog grayscale driving.

[0225] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 19(C). For example, Figure 1 The pixel circuit shown in 9(C) may have a switch, resistor, capacitive element, sensor, transistor or You can add circuits and other components.

[0226] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 19, the low power The source electrode (first electrode) is on the high-potential side, and the drain electrode (second electrode) is on the high-potential side. The configuration is designed to be electrically connected. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. Furthermore, the second gate electrode is supplied with a potential lower than that supplied to the source electrode by wiring (not shown). The configuration should be such that it can accept the potentials exemplified above.

[0227] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0228] (Embodiment 7) A semiconductor device according to one aspect of the present invention is a display device, a personal computer, and a recording medium. Equipped with an image playback device (typically DVD: Digital Versatile Disc) (Used in a device that has a display capable of playing back recording media such as c and displaying the images thereof) This is possible. In addition, electronic devices that can use a semiconductor device according to one aspect of the present invention. Examples include mobile phones, portable game consoles, portable data terminals, e-books, video cameras, Cameras such as digital still cameras, goggle-type displays (head-mounted displays) i) Navigation systems, sound playback devices (car audio, digital audio players) Layers, etc.), photocopiers, fax machines, printers, multifunction printers, ATMs Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 16. .

[0229] Figure 16(A) shows a portable game console, consisting of a casing 901, casing 902, display unit 903, and display Unit 904, microphone 905, speaker 906, operation key 907, stylus 90 It has 8, etc. Note that the portable game console shown in Figure 16(A) has two display units 903 and Although it has a display unit 904, the number of display units that a portable game console has is not limited to this. stomach.

[0230] Figure 16(B) shows a portable data terminal, consisting of a first housing 911, a second housing 912, and a first display unit. It has 913, a second display unit 914, a connection unit 915, an operation key 916, etc. First display unit 91 3 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. And the first housing 911 and the second housing 912 are connected by a connecting part 915. The angle between the first housing 911 and the second housing 912 can be changed by the connecting part 915. The video in the first display unit 913 is connected to the first housing 911 and the second housing in the connection unit 915. The configuration may also be configured to switch according to the angle between 912 and 913. A display in which at least one of the and the second display unit 914 has a function as a position input device. A device may be used. Note that the function as a position input device is controlled by touching the display device. It can be added by installing a panel. Alternatively, the function as a position input device is It can also be added by installing a photoelectric conversion element, also called an optical sensor, in the pixel section of the display device. It is possible.

[0231] Figure 16(C) shows a notebook personal computer, comprising a casing 921, a display unit 922, It includes a keyboard 923, a pointing device 924, and the like.

[0232] Figure 16(D) shows an electric refrigerator-freezer, consisting of a casing 931, a refrigerator door 932, and a freezer door 9 It has 33, etc.

[0233] Figure 16(E) shows a video camera, consisting of a first housing 941, a second housing 942, and a display unit 943. It has an operation key 944, a lens 945, a connecting part 946, etc. The operation key 944 and lens The Z945 is provided in the first housing 941, and the display unit 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connecting part 946. The angle between the first housing 941 and the second housing 942 can be changed by the connecting part 946. Yes. The video in the display unit 943 is connected to the first housing 941 and the second housing 9 in the connection unit 946. It could also be configured to switch according to the angle between 42 and 42.

[0234] Figure 16(F) is a regular passenger car, consisting of a body 951, wheels 952, dashboard 953, It has lights such as the 954.

[0235] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0236] (Embodiment 8) In this embodiment, Figure 17 illustrates an example of the use of an RF device according to one aspect of the present invention. Let me explain. RF devices have a wide range of applications, such as banknotes, coins, and securities. Categories, bearer bonds, certificates (such as driver's licenses and resident registration certificates, see Figure 17(A)), recording media (D VDs and videotapes, etc. (see Figure 17(B)), packaging containers (wrapping paper, bottles, etc., see Figure 17) (See (C)), vehicles (bicycles, etc., see Figure 17(D)), personal belongings (bags, glasses, etc.), Food products, plants, animals, human bodies, clothing, household goods, medical products including medicines and drugs, or electricity Items such as sub-devices (LCD displays, EL displays, television equipment, or mobile phones), Alternatively, it can be attached to luggage tags (see Figures 17(E) and 17(F)) attached to each item. It is possible.

[0237] An RF device 4000 according to one aspect of the present invention can be attached to or embedded on a surface. It is then fixed to an object. For example, in the case of a book, it is embedded in the paper, and the package is made of organic resin. If so, it is embedded inside the organic resin and fixed to each article. R according to one aspect of the present invention The F-device 4000 is small, thin, and lightweight, and even after being fixed to an object, it remains attached to the object. It does not detract from the design of the item itself. Also, banknotes, coins, securities, bearer bonds, Alternatively, by providing the RF device 4000 according to one aspect of the present invention on the certificate or other document, authentication This feature can be implemented, and by utilizing this authentication function, forgery can be prevented. Also, packaging containers, recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching an RF device according to one aspect of the present invention to systems such as inspection systems, The efficiency of the system can be improved. Furthermore, even in the case of vehicles, according to one aspect of the present invention, R By installing the F device, security against theft and other theft can be enhanced. Cut.

[0238] As described above, the RF device according to one aspect of the present invention can be used for each of the applications listed in this embodiment. By using this method, the operating power, including information writing and reading, can be reduced, thus maximizing performance. It becomes possible to extend the communication range. Also, even when the power is cut off, information can be transmitted. Because it can retain data for a long period, it is also suitable for applications where the frequency of writing and reading is low. It is possible.

[0239] This embodiment can be appropriately combined with other embodiments shown herein. ru. [Examples]

[0240] In this example, a transistor with a configuration similar to that shown in Figure 5(B) was used as the example sample. We fabricated an inverter and evaluated its electrical characteristics.

[0241] First, we will describe the method for preparing the sample used in the example.

[0242] A 900nm thick TEOS (Tetra) interlayer insulating film is applied to the silicon transistor. A silicon oxide film made from Ethyl Ortho Silicate (Ethyl Ortho Silicate) is processed by CVD. It was formed more.

[0243] Next, the silicon oxide film was subjected to CMP treatment to flatten the surface of the silicon oxide film. The conditions were: using polyurethane abrasive cloth as the CMP polishing pad, and NP8 as the slurry. Using the undiluted solution of 020 (manufactured by Nitta Haas Co., Ltd.) (silica particle size 60nm to 80nm) The slurry temperature was set to room temperature, the polishing pressure to 0.08 MPa, and the spindle on the side that holds the substrate in place. Assuming a rotational speed of 51 rpm and a table rotation speed of 50 rpm to which the abrasive cloth is fixed, 1. It was processed for 6 minutes.

[0244] Next, the openings reaching the electrodes of the silicon transistor are etched into the silicon oxide film. Formed. The etching conditions were, first, ICP (Inductive) etching as the first etching step. Inductively coupled plasma (Etching) A mixture of difluoromethane and helium (CHF3: He = 50 sccm: 100 sccm) Under atmospheric conditions, with a power supply of 475W, bias power of 300W, and a pressure of 5.5Pa, for 3 seconds. Etching is performed, and then, as a second etching, the trifluoromethyl etchant is used by the ICP etching method. mixed atmosphere of tan and helium (CHF3:He=7.5sccm:142.5sccm) Under low pressure, with a power supply of 475W, a bias power of 300W, and a pressure of 5.5Pa, the system ran for 79 seconds. After etching, etch again under the first etching conditions, then etch under the second etching conditions. I checked.

[0245] Next, a tungsten film with a thickness of 150 nm, which will serve as the relay wiring, is formed by sputtering. The film deposition conditions were as follows: using a tungsten target and an argon (Ar=80 sccm) atmosphere. Under ambient conditions, a pressure of 0.8 Pa and a power supply of 1 kW were applied, and the distance between the target and the substrate was measured. The film was deposited with a gap of 60 mm and a substrate temperature of 230°C.

[0246] Next, the tungsten film was etched to form relay wiring. The etching conditions were as follows: IC By P etching, chlorine, carbon tetrafluoride, and oxygen (Cl2:CF4:O2 = 45s) are extracted. (ccm:55sccm:55sccm) Mixed atmosphere, power supply 3000W, bias current Etching was performed for 5 seconds at a force of 110W and a pressure of 0.67Pa.

[0247] Next, a silicon oxide film made from TEOS with a thickness of 500 nm, which will serve as the interlayer insulating film, is CV Formed using method D.

[0248] Next, the silicon oxide film was subjected to CMP treatment to expose the relay wiring. The treatment conditions were CM Polyurethane abrasive cloth is used as the polishing pad, and NP8020 (Nippon) is used as the slurry. Using the stock solution (silica particle size 60nm to 80nm) manufactured by Ta Haas Co., Ltd., the slurry temperature Assuming room temperature, a polishing pressure of 0.08 MPa, and a spindle rotation speed of 51 on the side fixing the substrate, the temperature is set to room temperature. The table rotation speed to which the abrasive cloth is fixed is set to 50 rpm, and the process is performed for 1.4 minutes. Ta.

[0249] Next, a silicon oxide film made from TEOS with a thickness of 100 nm, which will become the interlayer insulating film, and oxidation A silicon nitride film with a thickness of 50 nm on a silicon film, and an acid film with a thickness of 300 nm on a silicon nitride film. A silicon dioxide film was formed by the CVD method.

[0250] Next, a first oxide semiconductor film with a thickness of 20 nm and a second oxide semiconductor film with a thickness of 15 nm are used. The films were formed by stacking. The deposition conditions were as follows: For the first oxide semiconductor film, In:Ga:Zn=1:3:2 By sputtering using an oxide target (atomic ratio), argon and oxygen ( Under a mixed atmosphere of Ar:O2 (30 sccm:15 sccm), at a pressure of 0.4 Pa, electricity was applied. A power source of 0.5kW was applied, the distance between the target and the substrate was 60mm, and the substrate temperature was 200℃. The first film is formed as follows, and the second oxide semiconductor film is an acid with an In:Ga:Zn ratio of 1:1:1 (atomic ratio). Sputtering method using a chromium target to extract argon and oxygen (Ar:O2=30 Under a mixed atmosphere (sccm:15sccm), pressure 0.4Pa, power supply 0.5kW The film was deposited by applying a solvent, maintaining a distance of 60 mm between the target and the substrate, and setting the substrate temperature to 300°C. Furthermore, the first oxide semiconductor film and the second oxide semiconductor film were deposited continuously without exposure to air. went.

[0251] Next, heat treatment was performed. The heat treatment was carried out at 450°C for 1 hour under a nitrogen atmosphere, followed by acid treatment. The process was carried out at 450°C for 1 hour under normal atmospheric conditions.

[0252] Next, the first oxide semiconductor film and the second oxide semiconductor film are subjected to ICP etching. A mixed atmosphere of boron trichloride and chlorine (BCl3:Cl2 = 60 sccm:20 sccm) Under ambient conditions, with a power supply of 450W, bias power of 100W, and a pressure of 1.9Pa, the system was tested for 89 seconds. The film was processed into island-shaped first oxide semiconductor film and second oxide semiconductor film by cutting. At the same time, island-like first blocking is formed from the first oxide semiconductor film and the second oxide semiconductor film. A blocking film and a second blocking film were formed.

[0253] Next, a silicon oxide film made from TEOS with a thickness of 100 nm, and a film on the silicon oxide film. A silicon nitride film with a thickness of 50 nm, and a silicon oxide film with a thickness of 300 nm on top of the silicon nitride film. An opening reaching the connecting wiring was formed by etching. The etching conditions were as follows: First, the first etching As etching, trifluoromethane and helium (CHF3) were etched using the ICP etching method. Under a mixed atmosphere (He=50sccm:100sccm), power supply 475W, bias current Etching is performed for 3 seconds at a force of 300W and a pressure of 5.5Pa, and then as a second etching... ICP etching is used to remove trifluoromethane and helium (CHF3:He=7). (5 sccm:142.5 sccm) Mixed atmosphere, Power supply 475W, Bias power 30 Etching was performed for 69 seconds at 0W and a pressure of 5.5Pa, and then again under the first etching conditions. After etching, etching was performed using the second etching conditions.

[0254] Next, a tungsten film with a thickness of 100 nm was deposited to serve as the source and drain electrodes. The film deposition conditions are achieved by sputtering using a tungsten target with argon (Ar Under an atmosphere of 80 sccm, with a pressure of 0.8 Pa and a power supply (power output) of 1.0 kW. Apply the specified voltage and set the distance between the substrate and the target to 60 mm and the substrate temperature to 230°C. The film was deposited.

[0255] Next, a resist mask was formed on the tungsten film, and etching was performed. The etched material is made of carbon tetrafluoride, chlorine, and oxygen (CF4:Cl2:O2) by the ICP etching method. =55sccm:45sccm:55sccm) Mixed atmosphere, power supply 3000W, The first etching process was performed for 13 seconds at a power of 110W and a pressure of 0.67Pa, and then, Under an oxygen (O2 = 100 sccm) atmosphere, power supply 2000W, bias power 0W, pressure A second etching process is performed at 3.0 Pa for 15 seconds, followed by carbon tetrafluoride, chlorine, and Oxygen (CF4:Cl2:O2=55sccm:45sccm:55sccm) mixed atmosphere Under pressure of 3000W, bias power of 110W, and pressure of 0.67Pa, the third etching process was performed. The process was performed for 14 seconds to form the source and drain electrodes.

[0256] Next, a third film with a thickness of 5 nm is placed on the second oxide semiconductor film, the source electrode, and the drain electrode. An oxide semiconductor film was deposited. The deposition conditions were In:Ga:Zn = 1:3:2 (atomic ratio). By sputtering using an oxide target, argon and oxygen (Ar:O2=3) are extracted. Under a mixed atmosphere of 0 sccm:15 sccm, with a pressure of 0.4 Pa and a power supply of 0.5 kWh, the pressure was 0.4 Pa. W was applied, the distance between the target and the substrate was set to 60 mm, and the substrate temperature to 200°C.

[0257] Next, a 20 nm silicon oxidnitride film, which will serve as the gate insulating film, is prepared by CVD using silane. Under a mixed atmosphere of nitrous oxide (SiH4:N2O=1 sccm:800 sccm), pressure A force of 200 Pa and a power supply of 150 kW were applied, and the distance between the target and the substrate was 28 mm. The film was deposited at a substrate temperature of 350°C.

[0258] Next, a titanium nitride film with a thickness of 30 nm and a tungsten film with a thickness of 135 nm are applied using a spatula. The film was deposited using the taring method. The deposition conditions for the titanium nitride film were under a nitrogen (N2 = 50 sccm) atmosphere. Under ambient air conditions, a pressure of 0.2 Pa and a power supply of 12 kW were applied between the target and the substrate. The distance was set to 400 mm and the substrate temperature to 25°C. The tungsten film deposition conditions were argon (A Under an atmosphere of r=100 sccm, a pressure of 2.0 Pa and a power supply of 4 kW were applied, and The distance between the connector and the substrate was set to 60 mm, and the substrate temperature was set to 230°C.

[0259] Next, using the ICP etching method, titanium nitride films with a thickness of 30 nm and films with a thickness of 135 nm were produced. The tungsten film stack was etched. The etching conditions were chlorine, carbon tetrafluoride and Oxygen (Cl2:CF4:O2 = 45 sccm:55 sccm:55 sccm) mixed atmosphere Below, with a power supply of 3000W, bias power of 110W, and pressure of 0.67Pa, the first E After etching, chlorine and boron trichloride (Cl2:BCl3=5) are removed. (0 sccm:150 sccm) Mixed atmosphere, Power supply 1000W, Bias power 50W Then, a second etching was performed at a pressure of 0.67 Pa to form a gate electrode.

[0260] Next, using the gate electrode as a mask, the gate insulating film and the third oxide semiconductor film are stacked. Etching was performed. The etching conditions were under a boron trichloride (BCl3 = 80 sccm) atmosphere. Etching was performed under a power supply of 450W, a bias power of 100W, and a pressure of 1.0Pa. .

[0261] Next, an aluminum oxide film with a thickness of 150 nm is applied to the gate electrode by sputtering. The film was deposited. The deposition conditions were argon:oxygen (Ar:O2 = 25 sccm:25 sccm) mixture. Under atmospheric conditions, a pressure of 0.4 Pa and a power supply of 2.5 kW were applied to the target and substrate. The distance between them was set to 60 mm, and the substrate temperature to 250°C.

[0262] After the above steps, the transient of the example with a channel length of 0.8 μm and a channel width of 10 μm was obtained. A transistor was fabricated. Furthermore, as a comparative example, the first blocking film and the second blocking film of the above transistor were fabricated. A transistor was fabricated that lacked only the blocking film.

[0263] Next, in the two types of transistors fabricated, the drain voltage (V d :[V]) is 0.1 Set to V or 2.7V, and the gate voltage (V g When sweeping [V]) from -3V to 3V , drain current (I d Measurements were taken at [A]). The measurement results are shown in Figure 18. The solid line represents the drain voltage (V d This is the measurement result when [V]) is 0.1V, and the dotted line is DU voltage (V d The measurement results are shown when [V]) is 2.7V, and the horizontal axis represents the gate voltage ( V g :[V]), the vertical axis is the drain current (I d :[A]) indicates. Note that "drain voltage ( V d :[V]) is the potential difference between the drain and the source with respect to the source, and is the gate Voltage (V) g :[V]) is the potential difference between the gate and the source, with the source as the reference. Figure 18(A) shows the measurement results of the comparative example transistor, and Figure 18(B) shows the measurement results of the example transistor. The measurement results are shown below.

[0264] Figure 18(A) shows that there is a large variation in characteristics. On the other hand, Figure 18(B) shows that It was confirmed that the variation in characteristics was small. By providing a blocking film, the characteristics This suggests that variability can be reduced. [Explanation of Symbols]

[0265] 100 circuit boards 102 Underlying insulating film 104a Conductive film 104b Conductive film 104c Conductive film 105 Interlayer insulating film 106 Interlayer insulating film 108a Oxide semiconductor film 108a1 Oxide semiconductor film 108a2 oxide semiconductor film 108a3 Oxide semiconductor film 108b blocking membrane 108b1 Blocking membrane 108b2 blocking membrane 10⁸c blocking membrane 108c1 blocking membrane 108c2 blocking membrane 110a Source electrode 110b Drain electrode 112 Gate Insulator 114 Guard gate 116 Oxide insulating film 118a Conductive film 118b Conductive film 120a opening 120b opening 128-channel protective film 150 transistors 250 transistors 700 circuit boards 701 pixel section 702 Scan Line Drive Circuit 703 Scan line drive circuit 704 Signal Line Drive Circuit 710 Capacitance wiring 712 Gate Wiring 713 Gate wiring 714 Drain electrode layer 716 transistors 717 transistors 718 Liquid crystal elements 719 Liquid crystal elements 720 pixels 721 Switching Transistors 722 Driver Transistor 723 Capacitive element 724 Light-emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 800 RF tags 801 Communication device 802 Antenna 803 Wireless signal 804 Antenna 805 Rectifier circuit 806 Constant Voltage Circuit 807 Demodulation Circuit 808 Modulation Circuit 809 Logic Circuits 810 Memory circuit 811 ROM 901 cabinet 902 cabinet 903 Display section 904 Display section 905 Microphone 906 Speakers 907 Operation Keys 908 Stylus 911 First cabinet 912 Second cabinet 913 Display section 914 Display section 915 Connection part 916 Operation Keys 921 cabinet 922 Display section 923 Keyboard 924 Pointing Devices 931 cabinet 932 Refrigerator door 933 Freezer door 941 First cabinet 942 Second cabinet 943 Display section 944 Operation Keys 945 lens 946 Connection part 951 Body 952 wheels 953 Dashboard 954 Light 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 1200 memory elements 1201 Circuit 1202 Circuit 1203 Switch 1204 Switch 1206 Logic Element 1207 Capacitive element 1208 Capacitive element 1209 Transistors 1210 Transistors 1213 Transistors 1214 Transistors 1220 Circuit 2100 transistors 2200 transistors 2201 Insulating film 2202 Wiring 2203 Plug 2204 Insulating film 2205 Wiring 2206 Wiring 2207 Insulating film 2208 Insulating film 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3200 transistors 3300 transistors 3400 Capacitive element 4000 RF devices

Claims

1. A first insulating film and A first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode, A second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode, A first oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the second conductive film, and having a channel-forming region, A second oxide semiconductor film having a region in contact with the upper surface of the first conductive film, A second insulating film having a region in contact with the upper surface of the first conductive film, a region in contact with the upper surface of the second conductive film, a region in contact with the upper surface of the first oxide semiconductor film, and a region in contact with the upper surface of the second oxide semiconductor film, A third conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the first conductive film through an opening provided in the second insulating film, The present invention comprises a fourth conductive film having a region in contact with the upper surface of the second insulating film and functioning as a gate electrode, The second oxide semiconductor film has lower resistance than the first oxide semiconductor film. The distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the opening and the first oxide semiconductor film. In a plan view, the second oxide semiconductor film is a semiconductor device that intersects with the first conductive film.

2. A first insulating film and A first conductive film having a region in contact with the upper surface of the first insulating film and functioning as a source electrode, A second conductive film having a region in contact with the upper surface of the first insulating film and functioning as a drain electrode, A first oxide semiconductor film having a region in contact with the upper surface of the first insulating film, a region in contact with the upper surface of the first conductive film, and a region in contact with the upper surface of the second conductive film, and having a channel-forming region, A second oxide semiconductor film having a region in contact with the upper surface of the first conductive film, A third oxide semiconductor film having a region in contact with the upper surface of the second conductive film, A second insulating film having a region in contact with the upper surface of the first conductive film, a region in contact with the upper surface of the second conductive film, a region in contact with the upper surface of the first oxide semiconductor film, a region in contact with the upper surface of the second oxide semiconductor film, and a region in contact with the upper surface of the third oxide semiconductor film, A third conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the first conductive film through a first opening provided in the second insulating film, A fourth conductive film having a region in contact with the upper surface of the second insulating film and a region in contact with the upper surface of the second conductive film through a second opening provided in the second insulating film, The present invention comprises a fifth conductive film having a region in contact with the upper surface of the second insulating film and functioning as a gate electrode, The second oxide semiconductor film has lower resistance than the first oxide semiconductor film. The third oxide semiconductor film has lower resistance than the first oxide semiconductor film. The distance between the second oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the first opening and the first oxide semiconductor film. The distance between the third oxide semiconductor film and the first oxide semiconductor film is shorter than the distance between the second opening and the first oxide semiconductor film. In a plan view, the second oxide semiconductor film intersects with the first conductive film. In a plan view, the third oxide semiconductor film is a semiconductor device that intersects with the second conductive film.

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