Display board and method for manufacturing the same, display device

Abstract

The present disclosure provides a display substrate and its manufacturing method, and a display device. The display substrate includes a display area 100 and at least one hole area 200 located in the display area 100, the hole area 200 includes a functional hole 210 and a partition area 220 surrounding the functional hole 210, the partition area 220 is provided with at least one partition dam 300 surrounding the functional hole 210, the partition dam 300 includes a first partition layer 40 disposed on a base 10 and a second partition layer 50 disposed on a side of the first partition layer 40 away from the base 10, the at least one partition layer includes a second sub-layer and a third sub-layer disposed on a side of the second sub-layer away from the base 10, the third sub-layer has a protrusion with respect to a sidewall of the second sub-layer, and the protrusion and the sidewall of the second sub-layer form a recess structure.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and particularly relates to a display substrate, a manufacturing method thereof, and a display device.

Background Art

[0002] An organic light-emitting diode (abbreviated as OLED) is an active light-emitting display device, which has advantages such as self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, lightweight, bendability, and low cost. With the continuous development of display technology, a display that uses an OLED as a light-emitting device and performs signal control by a thin film transistor (abbreviated as TFT) has become the main product in the current display field.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The following is an overview of the theme described in this specification. This overview does not limit the protection scope of the claims.

Means for Solving the Problems

[0004] In one aspect, the present disclosure provides a display substrate, which includes a display area and at least one hole area located in the display area. The hole area includes a functional hole and a partition area surrounding the functional hole. At least one partition dam surrounding the functional hole is installed in the partition area. The partition dam includes a first partition layer installed on a base and a second partition layer installed on a side of the first partition layer away from the base. At least one partition layer includes a second sub-layer and a third sub-layer installed on a side of the second sub-layer away from the base. The third sub-layer has a protrusion with respect to a side wall of the second sub-layer, and the protrusion and the side wall of the second sub-layer form a concave structure.

[0005] In an exemplary embodiment, at least one partition layer further includes a first sublayer, the second sublayer being located on the side of the first sublayer away from the base.

[0006] In an exemplary embodiment, the first partition layer includes a first conductive sublayer, a second conductive sublayer located on the side of the first conductive sublayer away from the base, and a third conductive sublayer located on the side of the second conductive sublayer away from the base, wherein, along the direction away from the functional hole, the width of the second conductive sublayer is smaller than the widths of the first and third conductive sublayers, the orthographic projection of the second conductive sublayer on the base is within the range of the orthographic projections of the first and third conductive sublayers on the base, thereby the first and third conductive sublayers having projections relative to the sidewall of the second conductive sublayer, and the projections and the sidewall of the second conductive sublayer form a recessed structure.

[0007] In an exemplary embodiment, the second partition layer includes a first metal sublayer installed on the side of the first partition layer away from the base, a second metal sublayer installed on the side of the first metal sublayer away from the base, and a first metal sublayer installed on the side of the second metal sublayer away from the base, wherein, along the direction away from the functional hole, the width of each of the second metal sublayers is smaller than the width of the first and third metal sublayers, and the orthographic projection of each of the second metal sublayers on the base is within the range of the orthographic projections of the first and third metal sublayers on the base, thereby the first and third metal sublayers having projections relative to the sidewall of the second metal sublayer, and the projections and the sidewall of the second metal sublayer form a recessed structure.

[0008] In exemplary embodiments, along the direction away from the functional hole, the width of the first metal sublayer is smaller than the width of the first conductive sublayer, and the orthographic projection of the first metal sublayer on the base lies within the range of the orthographic projection of the first conductive sublayer on the base.

[0009] In exemplary embodiments, along the direction away from the functional hole, the width of the second metal sublayer is smaller than the width of the second conductive sublayer, and the orthographic projection of the second conductive sublayer on the base lies within the range of the orthographic projection of the second metal sublayer on the base.

[0010] In exemplary embodiments, along the direction away from the functional hole, the width of the third metal sublayer is smaller than the width of the third conductive sublayer, and the orthographic projection of the third conductive sublayer on the base lies within the range of the orthographic projection of the third metal sublayer on the base.

[0011] In exemplary embodiments, along the direction away from the functional hole, the width of the third metal sublayer is less than or equal to the width of the first metal sublayer, the orthographic projection of the third metal sublayer on the base is within the range of the orthographic projection of the first metal sublayer on the base, the width of the third conductive sublayer is less than or equal to the width of the first conductive sublayer, the orthographic projection of the third conductive sublayer on the base is within the range of the orthographic projection of the first conductive sublayer on the base, the width of the first metal sublayer is less than or equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base is within the range of the orthographic projection of the third conductive sublayer on the base.

[0012] In an exemplary embodiment, along the direction away from the functional hole, the width of the third metal sublayer is greater than the width of the first metal sublayer, the orthographic projection of the first metal sublayer on the base is within the range of the orthographic projection of the third metal sublayer on the base, the width of the third conductive sublayer is smaller than the width of the first conductive sublayer, the orthographic projection of the third conductive sublayer on the base is within the range of the orthographic projection of the first conductive sublayer on the base, the width of the first metal sublayer is equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base and the orthographic projection of the third conductive sublayer on the base substantially overlap.

[0013] In an exemplary embodiment, the distance between the edge of the third metal sublayer and the base is smaller than the distance between the surface of the second metal sublayer away from the base and the base.

[0014] In an exemplary embodiment, the second partition layer includes a first metal sublayer installed on the side of the first partition layer away from the base, a second metal sublayer installed on the side of the first metal sublayer away from the base, and a third metal sublayer installed on the side of the second metal sublayer away from the base, wherein the cross-sectional shape of the second metal sublayer is a second trapezoid, the second trapezoid includes a second lower base on the side closer to the base and a second upper base on the side further away from the base, and along the direction away from the functional hole, the width of the second upper base is smaller than the width of the second lower base, the orthographic projection of the second upper base on the base is within the range of the orthographic projection of the second lower base on the base, the width of the third metal sublayer is less than or equal to the width of the second upper base, the orthographic projection of the third metal sublayer on the base is within the range of the orthographic projection of the second upper base on the base, the width of the second lower base is less than or equal to the width of the first metal sublayer, and the orthographic projection of the second lower base on the base is within the range of the orthographic projection of the first metal sublayer on the base.

[0015] In an exemplary embodiment, the width of the first metal sublayer is less than or equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base is located within the range of the orthographic projection of the third conductive sublayer on the base.

[0016] In an exemplary embodiment, the second partition layer includes a first metal sublayer installed on the side of the first partition layer away from the base, a second metal sublayer installed on the side of the first metal sublayer away from the base, and a third metal sublayer installed on the side of the second metal sublayer away from the base, wherein, along the direction away from the functional hole, the width of each of the second metal sublayers is smaller than the widths of the first and third metal sublayers, the orthographic projection of each of the second metal sublayers on the base is within the range of the orthographic projections of the first and third metal sublayers on the base, thereby the first and third metal sublayers having projections relative to the sidewall of the second metal sublayer, and the projections and the sidewall of the second metal sublayer form a recessed structure.

[0017] In an exemplary embodiment, the first partition layer includes a first conductive sublayer, a second conductive sublayer located on the side of the first conductive sublayer away from the base, and a third conductive sublayer located on the side of the second conductive sublayer away from the base, wherein the cross-sectional shape of the second conductive sublayer is a first trapezoid, the first trapezoid includes a first lower base on the side closer to the base and a first upper base on the side further away from the base, and along the direction away from the functional hole, the width of the first upper base is smaller than the width of the first lower base, the orthographic projection of the first upper base on the base is within the range of the orthographic projection of the first lower base on the base, the width of the third conductive sublayer is less than or equal to the width of the first upper base, the orthographic projection of the third conductive sublayer on the base is within the range of the orthographic projection of the first upper base on the base, the width of the first lower base is less than or equal to the width of the first conductive sublayer, and the orthographic projection of the first lower base on the base is within the range of the orthographic projection of the first conductive sublayer on the base.

[0018] In an exemplary embodiment, the width of the first metal sublayer is less than or equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base is located within the range of the orthographic projection of the third conductive sublayer on the base.

[0019] In an exemplary embodiment, the display area includes a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially installed on the base, wherein the first partition layer and the third conductive layer are installed on the same layer, and the second partition layer and the fourth conductive layer are installed on the same layer.

[0020] In other embodiments, the present disclosure further provides a display device comprising the above-described display board.

[0021] In other embodiments, the Disclosure further provides a method for manufacturing a display substrate, wherein the display substrate includes a display area and at least one hole area located in the display area, the hole area includes a functional hole and a partition area surrounding the functional hole, and the manufacturing method is Forming at least one partition dam surrounding the functional hole in the partition area, the partition dam includes a first partition layer and a second partition layer which are stacked, and at least one partition layer includes a second sub-layer and a third sub-layer installed on a side away from the base of the second sub-layer, the third sub-layer has a protrusion with respect to the side wall of the second sub-layer, and the protrusion and the side wall of the second sub-layer form a recess structure.

[0022] After reading and understanding the drawings and the detailed description, other aspects can be understood.

[0023] The drawings are for providing a further understanding of the technical solutions of the present disclosure, are a part of the specification, are for interpreting the technical solutions of the present disclosure together with the embodiments of the present disclosure, and are not for limiting the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual proportions and are for schematically explaining the content of the present disclosure.

Brief Description of the Drawings

[0024] [Figure 1] It is a schematic structural diagram of a display substrate. [Figure 2] It is a schematic plan view of the display substrate. [Figure 3] It is a schematic plan view of the display area. [Figure 4] It is an equivalent circuit schematic diagram of a pixel driving circuit. [Figure 5] It is an operation timing diagram of the pixel driving circuit. [Figure 6] It is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 7] It is a schematic structure diagram of a partition dam according to an exemplary embodiment of the present disclosure. [Figure 8] It is a schematic diagram after the formation of a structural layer pattern of a transistor according to an embodiment of the present disclosure. [Figure 9] It is a schematic diagram after the formation of a first planar layer pattern according to an embodiment of the present disclosure. [Figure 10] It is a schematic structural diagram of the first partition layer in FIG. 9. [Figure 11] This is a schematic diagram showing the fourth conductive layer pattern after it has been formed according to the embodiment of this disclosure. [Figure 12] Figure 11 shows a schematic diagram of the structure of the first and second partition layers. [Figure 13] This is a schematic diagram showing the second flat layer pattern after it has been formed according to the embodiment of the present disclosure. [Figure 14] Figure 13 shows schematic diagrams of the structure of the first and second partition dams. [Figure 15] This is a schematic diagram showing the anodic conductive layer pattern after it has been formed according to the embodiment of the present disclosure. [Figure 16] Figure 15 shows a schematic diagram of the structure of the first and second partition layers. [Figure 17] Figure 15 shows other schematic diagrams of the first and second partition layers. [Figure 18] This is a schematic diagram showing the pixel definition layer pattern after it has been formed according to the embodiment of the present disclosure. [Figure 19] This is a schematic diagram showing the organic light-emitting layer pattern after it has been formed according to the embodiment of the present disclosure. [Figure 20] Figure 19 is a schematic diagram illustrating the blocking of organic light-emitting materials by a partition dam. [Figure 21] This is a schematic diagram showing the cathode pattern after it has been formed according to the embodiment of this disclosure. [Figure 22] Figure 21 is a schematic diagram of cathode isolation by a partition dam. [Figure 23] This is a schematic diagram showing the sealing structure layer pattern after it has been formed according to the embodiment of the present disclosure. [Figure 24] Figure 23 is a schematic diagram showing the partition dam structure surrounded by the first sealing layer. [Figure 25] This is a schematic diagram of the structure of another partition dam according to an exemplary embodiment of the present disclosure. [Figure 26] This is a schematic diagram of the structure of another partition dam according to an exemplary embodiment of the present disclosure. [Figure 27] This is a schematic diagram of a further partition dam structure according to an exemplary embodiment of the present disclosure. [Modes for carrying out the invention]

[0025] To further clarify the purpose, technical proposals, and advantages of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments may be implemented in many different forms. The methods and content may be transformed into various forms without departing from the gist and scope of this disclosure, so as can be easily understood by those skilled in the art. Therefore, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, the embodiments and features of the embodiments of this disclosure may be combined with each other. To maintain clarity and brevity in the following descriptions of the embodiments of this disclosure, detailed descriptions of some known functions and known components are omitted in this disclosure. The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure; for other structures, conventional designs may be referenced.

[0026] The proportions in the drawings in this disclosure may, but are not limited to, those shown in the drawings for reference in actual processes. For example, the ratio of channel width to length, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels on the display substrate and the number of subpixels in each pixel are not limited to those shown in the drawings, and the drawings described in this disclosure are merely schematic diagrams of the structure. One aspect of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0027] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion regarding the constituent elements and do not limit them in terms of quantity.

[0028] In this specification, for convenience, the positional relationships of components are described with reference to the drawings using terms indicating direction or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or implicitly suggest that the described apparatus or element has a specific direction or must be configured and operated in a specific direction. Therefore, it is not intended to limit this disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0029] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or an electrical connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will understand the specific meaning of these terms in this disclosure depending on the specific circumstances.

[0030] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0031] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" may be converted to each other.

[0032] In this specification, “electrical connection” includes cases where components are connected via an element having an electrical function. The “element having an electrical function” is not particularly limited and only needs to be capable of transmitting and receiving electrical signals between the connected components. Examples of “elements having an electrical function” include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and various other elements with different functions.

[0033] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0034] In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0035] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, advanced angles, arcs, and other deformations.

[0036] In this disclosure, "approximately" means that the boundary is not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0037] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device comprises a timing controller, a data driver, a scanning driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scanning driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array includes a plurality of sub-pixels Pxij, where i and j are natural numbers. At least one sub-pixel Pxij includes a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit includes at least one scanning signal line, at least one data signal line, at least one light-emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller provides the data driver with gray values ​​and control signals conforming to the data driver's specifications, the scanning driver with clock signals, scan start signals, etc. conforming to the scanning driver's specifications, and the light-emitting driver with clock signals, fire stop signals, etc. conforming to the light-emitting driver's specifications. The data driver generates data voltages to be supplied to data signal lines D1, D2, D3, ..., Dn using gray values ​​and control signals received from the timing controller. For example, the data driver can sample gray values ​​using a clock signal and apply data voltages corresponding to the gray values ​​to data signal lines D1 to Dn on a pixel row basis, where n is a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially supply scan signals having turn-on level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and generate scan signals by sequentially transporting scan start signals, provided in the form of turn-on level pulses under the control of a clock signal, to the next stage circuit, where m is a natural number.The light-emitting driver can generate firing signals to be supplied to the light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, firing stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially supply firing signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured in the form of a shift register and generate firing signals by sequentially transporting firing stop signals, which are provided in the form of cutoff level pulses under the control of a clock signal, to the next stage circuit, where o is a natural number.

[0038] Intelligent terminals and similar products generally require the installation of devices such as front cameras, fingerprint sensors, or light sensors. To improve the display-to-body ratio, products with full screens or narrow bezels typically employ display area perforation technology, placing devices such as front cameras, fingerprint sensors, or light sensors within functional holes. However, the side walls of the functional holes expose the organic light-emitting layer and cathode, allowing water and oxygen in the air to penetrate the display substrate along the organic light-emitting layer, rendering it ineffective and leading to display malfunctions. Therefore, one of the problems with perforating the display substrate is the effectiveness of the seal.

[0039] Figure 2 is a schematic diagram of the planar structure of the display board. As shown in Figure 2, in a plane parallel to the display board, the display board may include a display area 100 and at least one hole area 200 located within the display area 100, the display area 100 being configured for image display and the hole area 200 being configured for mounting an optical device. In an exemplary embodiment, the hole area 200 may include at least one functional hole 210 and a partition area 220 surrounding the functional hole 210, that is, the partition area 220 is installed between the functional hole 210 and the display area 100, and the partition area 220 is configured to accommodate at least one partition structure, the partition structure being configured to block the ingress of water and oxygen from the functional hole into the display board and ensure the effectiveness of the display board.

[0040] In exemplary embodiments, the position of the hole area 200 within the display area 100 is not limited, and the hole area 200 may be located within the display area 100, for example, at the top or bottom of the display area 100, or at the edge of the display area 100, and is not limited herein.

[0041] In exemplary embodiments, the shape of the hole area 200 in a plane parallel to the display substrate may be one or more of rectangular, polygonal, circular, and elliptical shapes, and the optical device may be an optical sensor such as a camera, fingerprint recognition device, or 3D imaging device, but is not limited thereto.

[0042] In exemplary embodiments, the base and structural film layer in the functional hole 210 are completely removed to form a via structure, or some of the base and some of the structural film layer in the functional hole 210 are removed to form a blind hole structure, and the disclosure is not limited herein.

[0043] Figure 3 is a schematic diagram of the planar structure of the display area. As shown in Figure 3, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first subpixel P1 that emits a first color ray, a second subpixel P2 that emits a second color ray, a third subpixel P3 that emits a third color ray, and a fourth subpixel P4 that emits a fourth color ray. Each of the four subpixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the four subpixels are connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is set to receive a data voltage transmitted from the data signal line under the control of the scan signal line and the light-emitting signal line, and to output a corresponding current to the light-emitting device. The light-emitting device in the four subpixels is connected to the pixel driving circuit of the subpixel in which it is located. The light-emitting device is set to emit light of a corresponding brightness in response to the current output from the pixel driving circuit of the subpixel in which it is located.

[0044] In exemplary embodiments, the first subpixel P1 may be a red subpixel emitting red (R) light rays, the second subpixel P2 may be a green subpixel emitting green (G) light rays, the third subpixel P3 may be a blue subpixel emitting blue (B) light rays, and the fourth subpixel P4 may be a green subpixel emitting green (G) light rays. In exemplary embodiments, the shape of the subpixels in the pixel unit may be rectangular, rhombus, pentagonal, or hexagonal, and they may be arranged in a horizontal, vertical, square, or diamond pattern, but this disclosure is not limited thereto.

[0045] In exemplary embodiments, the four subpixels may include a red subpixel, a green subpixel, a blue subpixel, and a white subpixel emitting white (W) light. In exemplary embodiments, the pixel unit may include three subpixels, for example, a red subpixel, a blue subpixel, and a green subpixel. The three subpixels may be arranged in a horizontal, vertical, or U-shape, etc., and are not limited herein.

[0046] Figure 4 is a schematic equivalent circuit diagram of a pixel driving circuit. In exemplary embodiments, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. As shown in Figure 4, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C, and the pixel driving circuit is connected to seven signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT, first partition structure VDD, and second partition structure VSS).

[0047] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Of these, the first node N1 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, respectively. The second node N2 is connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively.

[0048] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first partition structure VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3.

[0049] The control pole of the first transistor T1 is connected to the second scan signal line S2, the first pole of the first transistor T1 is connected to the initial signal line INIT, and the second pole of the first transistor is connected to the second node N2. When a turn-on level scan signal is applied to the second scan signal line S2, the first transistor T1 transports an initialization voltage to the control pole of the third transistor T3, thereby initializing the charge amount of the control pole of the third transistor T3.

[0050] The control pole of the second transistor T2 is connected to the first scan signal line S1, the first pole of the second transistor T2 is connected to the second node N2, and the second pole of the second transistor T2 is connected to the third node N3. When a turn-on level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control pole of the third transistor T3 to its second pole.

[0051] The control pole of the third transistor T3 is connected to the second node N2, that is, the control pole of the third transistor T3 is connected to the second terminal of the storage capacitor C, the first pole of the third transistor T3 is connected to the first node N1, and the second pole of the third transistor T3 is connected to the third node N3. The third transistor T3 may also be called a drive transistor. The third transistor T3 determines the amount of drive current flowing between the first partition structure VDD and the second partition structure VSS based on the potential difference between its control pole and its first pole.

[0052] The control pole of the fourth transistor T4 is connected to the first scanning signal line S1, the first pole of the fourth transistor T4 is connected to the data signal line D, and the second pole of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may also be called a switch transistor, scanning transistor, etc. When a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0053] The control pole of the fifth transistor T5 is connected to the light emission signal line E, the first pole of the fifth transistor T5 is connected to the first partition structure VDD, and the second pole of the fifth transistor T5 is connected to the first node N1. The control pole of the sixth transistor T6 is connected to the light emission signal line E, the first pole of the sixth transistor T6 is connected to the third node N3, and the second pole of the sixth transistor T6 is connected to the first pole of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 may also be referred to as light-emitting transistors. When a turn-on level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a drive current path between the first partition structure VDD and the second partition structure VSS.

[0054] The control pole of the seventh transistor T7 is connected to the first scanning signal line S1, the first pole of the seventh transistor T7 is connected to the initial signal line INIT, and the second pole of the seventh transistor T7 is connected to the first pole of the light-emitting device. When a turn-on level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 transports an initialization voltage to the first pole of the light-emitting device to initialize the amount of charge stored in the first pole of the light-emitting device, or to release the amount of charge stored in the first pole of the light-emitting device.

[0055] In an exemplary embodiment, the second pole of the light-emitting device is connected to a second first partition structure VSS, where the signal of the second first partition structure VSS is a low-level signal, and the signal of the first first partition structure VDD is a signal that continues to provide a high level. The first scan signal line S1 is the scan signal line in the display row pixel driving circuit, and the second scan signal line S2 is the scan signal line in the previous display row pixel driving circuit. That is, for the nth display row, the first scan signal line S1 is S(n) and the second scan signal line S2 is S(n-1). The second scan signal line S2 of the display row and the first scan signal line S1 in the previous display row pixel driving circuit are the same signal line, which reduces the number of signal lines in the display panel and enables a narrower frame for the display panel.

[0056] In exemplary embodiments, the first to seventh transistors T1 to T7 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In several possible realizations, the first to seventh transistors T7 may include both P-type and N-type transistors.

[0057] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission signal line E, and the initial signal line INIT extend horizontally, while the second first partition structure VSS, the first first partition structure VDD, and the data signal line D extend vertically.

[0058] In exemplary embodiments, the light-emitting device may be an organic light-emitting transistor (OLED) and includes a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) that are stacked together.

[0059] Figure 5 is an operation timing diagram of the pixel driving circuit. Hereinafter, exemplary embodiments of this disclosure will be described with reference to the operation process of the pixel driving circuit illustrated in Figure 4. The pixel driving circuit in Figure 4 includes seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C.

[0060] In an exemplary embodiment, the operation process of the pixel driving circuit may include the following first stage A1, second stage A2, and third stage A3.

[0061] The first stage A1 is called the reset stage, in which the signal on the second scan signal line S2 is a low-level signal, and the signals on the first scan signal line S1 and the light emission signal line E are high-level signals. The low-level signal on the second scan signal line S2 turns on the first transistor T1, provides the signal on the initial signal line INIT to the second node N2, initializes the storage capacitor C, and clears the original data voltage in the storage capacitor. The high-level signals on the first scan signal line S1 and the light emission signal line E cut off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, and the OLED does not emit light during this stage.

[0062] The second stage A2 is called the data writing stage or threshold compensation stage. The signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light emission signal line E are high-level signals, and the data signal line D outputs a data voltage. At this stage, the second terminal of the storage capacitor C is low-level, so the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line D is supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged to the storage capacitor C. The voltage at the second terminal (second node N2) of the storage capacitor C is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the initial voltage of the initial signal line INIT is supplied to the first pole of the OLED, initializing (resetting) the first pole of the OLED, clearing the pre-stored voltage inside it, completing the initialization, and ensuring that the OLED does not emit light. The signal on the second scan signal line S2 is a high-level signal, which cuts off the first transistor T1. The signal on the light emission signal line E is a high-level signal, which cuts off the fifth transistor T5 and the sixth transistor T6.

[0063] The third stage A3 is called the light emission stage, where the signal on the light emission signal line E is a low-level signal, and the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light emission signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first partition structure VDD provides a drive voltage to the first pole of the OLED via the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light emission of the OLED.

[0064] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. The voltage at the second node N2 is Vd-|Vth| Therefore, the drive current of the third transistor T3 is given by the following formula.

[0065] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0066] In the equation, I is the drive current flowing through the third transistor T3, i.e., the drive current that drives the OLED; K is a constant; Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3; Vth is the threshold voltage of the third transistor T3; Vd is the data voltage output from the data signal line D; and Vdd is the power supply voltage output from the first partition structure VDD.

[0067] Figure 6 is a schematic cross-sectional view of a display substrate according to an exemplary embodiment of the present disclosure. In the exemplary embodiment, the display substrate may include a display area 100 and at least one hole area 200 located within the display area 100, the hole area 200 may include a functional hole 210 and a partition area 220 surrounding the functional hole 210. Figure 6 shows the cross-sectional structure of the display area 100 and the partition area 220, and is a cross-sectional view in the AA direction in Figure 2. In the exemplary embodiment, at least one partition dam 300 surrounding the functional hole 210 is installed in the partition area 220, and the partition dam 300 is configured to block the ingress of water and oxygen from the functional hole into the display substrate.

[0068] In an exemplary embodiment, the partition dam 300 may include a first partition layer 40 installed on a base 10 and a second partition layer 50 installed on the side of the first partition layer 40 away from the base 10, and at least one partition layer may include a second sub-layer and a third sub-layer installed on the side of the second sub-layer away from the base, the third sub-layer having a projection relative to the side wall of the second sub-layer, and the projection and the side wall of the second sub-layer forming a recess structure.

[0069] In exemplary embodiments, at least one partition layer may further include a first sublayer, the second sublayer being located on the side away from the base of the first sublayer.

[0070] In exemplary embodiments, the first partition layer 40 may include a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer that are stacked, and the second partition layer 50 may include a first metal sublayer, a second metal sublayer, and a third metal sublayer that are stacked.

[0071] In an exemplary embodiment, the three conductive sublayers of the first partition layer 40 can form an "I" shape structure, and the three metal sublayers of the second partition layer 50 can form an "I" shape structure, and the first partition layer 40 and the second partition layer 50 together constitute a partition dam structure in which a double "I" shape structure is stacked.

[0072] In other exemplary embodiments, the three conductive sublayers of the first partition layer 40 may form an "I" shaped structure, and the three metal sublayers of the second partition layer 50 may form a trapezoidal structure, and the first partition layer 40 and the second partition layer 50 together constitute a partition dam structure in which the upper trapezoidal structure and the lower "I" shaped structure are stacked.

[0073] In another exemplary embodiment, the three conductive sublayers of the first partition layer 40 may form a trapezoidal structure, and the three metal sublayers of the second partition layer 50 may form an "I" shaped structure, and the first partition layer 40 and the second partition layer 50 together constitute a partition dam structure in which the upper "I" shaped structure and the lower trapezoidal structure are stacked.

[0074] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display area may include a drive structure layer 101 installed on the base 10, a light-emitting structure layer 102 installed on the side of the drive structure layer 101 away from the base, and a sealing structure layer 103 installed on the side of the light-emitting structure layer 102 away from the base. In an exemplary embodiment, the drive structure layer 101 may include a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, a third conductive layer, a first flat layer 15, a fourth conductive layer, and a second flat layer 16, which are sequentially installed on the base 10. The semiconductor layer may include a first active layer, the first conductive layer may include a first gate electrode and a first electrode plate, the second conductive layer may include a second electrode plate, and the third conductive layer may include a first source electrode and a first drain electrode. The first active layer, first gate electrode, first source electrode, and first drain electrode may constitute a transistor 100A, and the first and second plates may constitute a storage capacitor 100B. The light-emitting structure layer 102 may include an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 25, and the sealing structure layer 103 may include a stacked first sealing layer 31, a second sealing layer 32, and a third sealing layer 33.

[0075] In exemplary embodiments, the first partition layer 40 may be placed on the same layer as the third conductive layer and formed simultaneously in the same patterning process, and the second partition layer 50 may be placed on the same layer as the fourth conductive layer and formed simultaneously in the same patterning process.

[0076] In an exemplary embodiment, multiple partition dams 300 surrounding the functional hole 210 are installed in the partition area 220, thereby forming a partition structure with multiple perimeters.

[0077] Figure 7 is a schematic diagram of the structure of a partition dam according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the partition dam of this exemplary embodiment may include a first partition layer 40 and a second partition layer 50 installed on the side away from the base of the first partition layer 40. The first partition layer 40 may include a first conductive sublayer 41, a second conductive sublayer 42 installed on the side away from the base of the first conductive sublayer 41, and a third conductive sublayer 43 installed on the side away from the base of the second conductive sublayer 42. The second partition layer 50 may include a first metal sublayer 51 installed on the side away from the base of the third conductive sublayer 43, a second metal sublayer 52 installed on the side away from the base of the first metal sublayer 51, and a third metal sublayer 53 installed on the side away from the base of the second metal sublayer 52.

[0078] In an exemplary embodiment, the first conductive sublayer 41 and the third conductive sublayer 43 have protrusions relative to the side wall 40B of the second conductive sublayer 42, and the two upper and lower protrusions and the side wall 40B of the second sublayer form a recessed structure, thereby forming a first "I" shaped structure when the first conductive sublayer 41, second conductive sublayer 42, and third conductive sublayer 43 are stacked together.

[0079] In an exemplary embodiment, the first metal sublayer 51 and the third metal sublayer 53 have protrusions relative to the side wall 50B of the second metal sublayer 52, and the two upper and lower protrusions and the side wall 50B of the second metal layer form a recessed structure, thereby forming a second "I" shaped structure when the first metal sublayer 51, second metal sublayer 52, and third metal sublayer 53 are stacked together.

[0080] In an exemplary embodiment, the first "I" shaped structure and the second "I" shaped structure installed on the side away from the base of the first "I" shaped structure constitute a partition dam structure in which double "I" shaped structures are stacked.

[0081] In an exemplary embodiment, the overall width of the second "I" shaped structure may be smaller than the overall width of the first "I" shaped structure, that is, the partition dam structure has an overall form in which the upper layer is smaller and the lower layer is larger, and the width is the size in the direction away from the functional hole.

[0082] In exemplary embodiments, the width LT1 of the third conductive sublayer 43 may be less than or equal to the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third conductive sublayer 43 on the base may be located within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0083] In exemplary embodiments, the width LM1 of the second conductive sublayer 42 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0084] In exemplary embodiments, the width LM1 of the second conductive sublayer 42 may be smaller than the width LT1 of the third conductive sublayer 43, and the orthographic projection of the second conductive sublayer 42 at the base may be within the range of the orthographic projection of the third conductive sublayer 43 at the base.

[0085] In an exemplary embodiment, the width LT2 of the third metal sublayer 53 may be less than or equal to the width LB2 of the first metal sublayer 51, and the orthographic projection of the third metal sublayer 53 at the base may be within the range of the orthographic projection of the first metal sublayer 51 at the base.

[0086] In an exemplary embodiment, the width LM2 of the second metal sublayer 52 may be smaller than the width LB2 of the first metal sublayer 51, and the orthographic projection of the second metal sublayer 52 at the base may be within the range of the orthographic projection of the first metal sublayer 51 at the base.

[0087] In an exemplary embodiment, the width LM2 of the second metal sublayer 52 may be smaller than the width LT2 of the third metal sublayer 53, and the orthographic projection of the second metal sublayer 52 at the base may be within the range of the orthographic projection of the third metal sublayer 53 at the base.

[0088] In exemplary embodiments, the width LB2 of the first metal sublayer 51 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the first metal sublayer 51 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0089] In exemplary embodiments, the width LM2 of the second metal sublayer 52 may be smaller than the width LM1 of the second conductive sublayer 42, and the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projection of the second metal sublayer 52 on the base.

[0090] In exemplary embodiments, the width LT2 of the third metal sublayer 53 may be smaller than the width LT1 of the third conductive sublayer 43, and the orthographic projection of the third metal sublayer 53 on the base may be within the range of the orthographic projection of the third conductive sublayer 43 on the base.

[0091] In exemplary embodiments, the width LB2 of the first metal sublayer 51 may be less than or equal to the width LT1 of the third conductive sublayer 43, and the orthographic projection of the first metal sublayer 51 on the base may be located within the range of the orthographic projection of the third conductive sublayer 43 on the base.

[0092] The manufacturing process of a display substrate will be described below with examples. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching. This disclosure is not limited. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the manufacturing process, the “thin film” is also referred to as a “layer.” If the “thin film” requires a patterning process throughout the manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process includes at least one “pattern.” As described in this disclosure, “A and B are placed on the same layer” means that A and B are formed simultaneously by the same patterning process. The “thickness” of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0093] In exemplary embodiments, the display substrate may include a display area 100 and a hole area 200, the hole area 200 may include a functional hole 210 and a partition area 220 surrounding the functional hole 210, and the partition area 220 is provided with at least one full partition dam. In exemplary embodiments, taking a full partition dam in the partition area 220 and one subpixel in the display area 100 as examples, the manufacturing process of the display substrate of the exemplary embodiment of this disclosure may include the following operations.

[0094] (11) As shown in Figure 8, a transistor structure layer pattern is formed on the base. In an exemplary embodiment, forming a transistor structure layer pattern on the base may include the following:

[0095] A first insulating thin film and a semiconductor thin film are sequentially deposited on a base, and the semiconductor thin film is patterned by a patterning process to form a first insulating layer 11 to be placed on the base and a semiconductor layer pattern to be placed on the first insulating layer 11, the semiconductor layer pattern including at least a first active layer located in the display area 100.

[0096] Then, the second insulating thin film and the first conductive thin film are deposited sequentially, and the first conductive thin film is patterned by a patterning process to form a second insulating layer 12 that covers the semiconductor layer pattern, and a first conductive layer pattern that is installed on the second insulating layer 12. The first conductive layer pattern includes at least a first gate electrode and a first electrode plate located in the display area 100.

[0097] Then, the third insulating thin film and the second conductive thin film are deposited sequentially, and the second conductive thin film is patterned by a patterning process to form the third insulating layer 13 covering the first conductive layer, and the second conductive layer pattern placed on the third insulating layer 13. The second conductive layer pattern includes at least the second electrode plate located in the display area 100, and the orthographic projection of the base of the second electrode plate and the orthographic projection of the base of the first electrode plate overlap at least partially.

[0098] Then, a fourth insulating thin film is deposited and patterned by a patterning process to form a fourth insulating layer 14 pattern that covers the second conductive layer pattern, and a plurality of active vias are formed in the fourth insulating layer 14, the plurality of active vias include at least two active vias located in the display area 100, and the two active vias each expose both ends of the first active layer.

[0099] Then, a third conductive thin film is deposited and patterned by a patterning process to form a third conductive layer pattern on the fourth insulating layer 14, the third conductive layer pattern including at least a first source electrode located in the display area 100, a first drain electrode, and a first partition layer 40 located in the partition area 220, the first source electrode and the first drain electrode are each connected to both ends of the first active layer via active vias. In exemplary embodiments, the third conductive layer may be referred to as the first source-drain metal layer (SD1).

[0100] As shown in Figure 8, the manufacturing of the transistor structure layer pattern is completed. In an exemplary embodiment, the transistor structure layer of each subpixel in the display area 100 may include a plurality of transistors and a storage capacitor that constitute a pixel driving circuit, with one transistor 100A and one storage capacitor 100B being an example in Figure 8. In an exemplary embodiment, the transistor 100A may include a first active layer, a first gate electrode, a first source electrode, and a first drain electrode, and the storage capacitor 100B may include a first plate and a second plate. In an exemplary embodiment, the transistor may also be a driving transistor in the pixel driving circuit, and the driving transistor may be a thin-film transistor (TFT).

[0101] In exemplary embodiments, the transistor structure layer of the partition region 220 may include a composite insulating layer installed on the base 10, and a first partition layer 40 installed on the side of the composite insulating layer away from the base. The composite insulating layer may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 that are laminated on the base 10.

[0102] In exemplary embodiments, the base may be a rigid base or a flexible base. In exemplary embodiments, the rigid base may be made of a material such as glass or quartz, and the flexible base may be made of a material such as polyimide (PI). The flexible base may be a single-layer structure or a laminated structure consisting of an inorganic material layer and a flexible material layer, and this disclosure is not limited thereto.

[0103] In exemplary embodiments, the first, second, third, and fourth insulating layers may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first insulating layer may be called a buffer layer, the second and third insulating layers may be called gate insulating (GI) layers, and the fourth insulating layer may be called an interlayer insulating (ILD) layer. The first, second, and third conductive layers may be metallic materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer or multi-layer composite structure. The semiconductor layer may employ various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0104] In exemplary embodiments, the third conductive layer may include a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer that are stacked together. The first and third conductive sublayers may be made of metallic titanium (Ti), and the second conductive sublayer may be made of metallic aluminum (Al), thereby forming a Ti / Al / Ti composite structure.

[0105] In exemplary embodiments, during the patterning process of the fourth insulating thin film, a first transition hole (not shown) may be formed at the location of a functional hole in the hole region. The first transition hole may be a via, and the fourth insulating layer, third insulating layer, second insulating layer, first insulating layer and base within the first transition hole may be removed, or the first transition hole may be a blind hole, and the fourth insulating layer, third insulating layer, second insulating layer and first insulating layer within the first transition hole may be removed, but the disclosure is not limited herein.

[0106] (12) Forming a first flat layer pattern. In an exemplary embodiment, as shown in Figure 9, forming a first flat layer pattern may include coating a first flat thin film onto a base on which the pattern is to be formed, and then patterning the first flat thin film by a patterning process to form a first flat layer 15 pattern.

[0107] In an exemplary embodiment, the first flat layer 15 is formed only in the display area 100, and the first flat thin film in the partition area 220 is removed. A first connection via K1 is opened in the first flat layer 15 of the display area 100, the first flat thin film within the first connection via K1 is removed, exposing the surface of the first drain electrode of the transistor 100A, and the first connection via K1 is configured such that a subsequently formed anode connection electrode is connected to the first drain electrode via the via.

[0108] In exemplary embodiments, patterning of the first flat thin film may include first exposing the first flat thin film, and then developing the first flat thin film after exposure to form a patterned first flat layer 15.

[0109] In exemplary embodiments, a strong alkaline solution may be used as the developer for the developing process. After the first flat thin film of the partition region 220 is removed, the sides of the first partition layer 40 are exposed, and under the action of the strong alkaline solution, the sides of the first partition layer 40 are eroded by the developer. For the first partition layer 40, which employs a multi-layer composite structure of Ti / Al / Ti, the erosion rate of the developer on the aluminum layer (second conductive sublayer) is greater than the erosion rate on the titanium layers (first conductive sublayer and third conductive sublayer). As a result, side depressions are formed on the eroded sides of the first partition layer 40, and the aluminum layer and the upper titanium layer protrude a certain distance from the aluminum layer, forming an "I" shape structure.

[0110] Figure 10 is a schematic diagram of the structure of the first partition layer in Figure 9. As shown in Figure 10, the first partition layer 40 may include a first conductive sublayer 41, a second conductive sublayer 42, and a third conductive sublayer 43 that are laminated on the fourth insulating layer 14. Specifically, the first conductive sublayer 41 is installed on the side away from the base of the fourth insulating layer 14, the second conductive sublayer 42 is installed on the side away from the base of the first conductive sublayer 41, and the third conductive sublayer 43 is installed on the side away from the base of the second conductive sublayer 42.

[0111] In exemplary embodiments, the materials for the first conductive sublayer 41 and the third conductive sublayer 43 may be metallic titanium, and the material for the second conductive sublayer 423 may be metallic aluminum. Since the erosion rate of the developer on the second conductive sublayer 42 (aluminum) is greater than the erosion rate on the first conductive sublayer 41 and the third conductive sublayer 43 (titanium), after being eroded by the developer, the amount of etching on the side surface of the second conductive sublayer 42 is greater than the amount of etching on the side surfaces of the first conductive sublayer 41 and the third conductive sublayer 43, forming a side recess on the side surface of the first partition layer 40, and the first conductive sublayer 41 and the third conductive sublayer 43 protrude a certain distance from the second conductive sublayer 42, forming an "I" shaped structure.

[0112] In exemplary embodiments, in the first partition layer 40 having an "I" shaped structure, the width of the second conductive sublayer 42 may be smaller than the width of the first conductive sublayer 41, the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base, the width of the second conductive sublayer 42 may be smaller than the width of the third conductive sublayer 43, and the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projection of the third conductive sublayer 43 on the base.

[0113] (13) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in Figure 11, the formation of the fourth conductive layer pattern may include depositing a fourth conductive thin film on a base on which the pattern is to be formed, and then patterning the fourth conductive thin film by a patterning process to form the fourth conductive layer pattern. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal layer (SD2).

[0114] In an exemplary embodiment, the fourth conductive layer may include an anode connection electrode 17 located in the display area 100 and a second partition layer 50 located in the partition area 220. The anode connection electrode 17 is placed in the first flat layer 15 of the display area 100 and is connected to the first drain electrode of the transistor 100A via a first connection via K1. The second partition layer 50 is placed over the first partition layer 40 in the partition area 220, thereby directly connecting the second partition layer 50 and the first partition layer 40.

[0115] Figure 12 is a schematic diagram of the structure of the first and second partition layers in Figure 11. As shown in Figure 12, the second partition layer 50 may include a first metal sublayer 51, a second metal sublayer 52, and a third metal sublayer 53 which are laminated on the third conductive sublayer 43, namely the first metal sublayer 51 which is installed on the side away from the base of the third conductive sublayer 43, the second metal sublayer 52 which is installed on the side away from the base of the first metal sublayer 51, and the third metal sublayer 53 which is installed on the side away from the base of the second metal sublayer 52. In an exemplary embodiment, the materials for the first metal sublayer 51 and the third metal sublayer 53 may be titanium metal, and the material for the second metal sublayer 52 may be aluminum metal.

[0116] In exemplary embodiments, the sides of the second partition layer 50 are substantially aligned, and the sides of the second partition layer 50 and the sides of the third conductive sublayer 43 are substantially aligned, and the orthographic projections of the base of the first metal sublayer 51, the base of the second metal sublayer 52, the base of the third metal sublayer 53, and the base of the third conductive sublayer 43 may substantially overlap. In possible embodiments, during the patterning process of the fourth conductive thin film, the etching rates of the etching solution on the titanium layer and the aluminum layer may differ, so that after etching, the sides of the first metal sublayer 51 and the third metal sublayer 53 protrude a certain distance from the second metal sublayer 52, and the disclosure is not limited herein.

[0117] (14) Forming a second flat layer pattern. In an exemplary embodiment, as shown in Figure 13, forming a second flat layer pattern may include coating a second flat thin film onto a base on which the pattern is to be formed, and then patterning the second flat thin film by a patterning process to form a second flat layer 16 pattern.

[0118] In an exemplary embodiment, the second flat layer 16 is formed only in the display area 100, and the second flat thin film in the partition area 220 is removed. The second flat layer 16 in the display area 100 covers the anode connection electrode 17, and a second connection via K2 is opened in the second flat layer 16. The second flat thin film within the second connection via K2 is removed, exposing the surface of the anode connection electrode 17. The second connection via K2 is configured such that a subsequently formed anode is connected to the anode connection electrode via the via.

[0119] In exemplary embodiments, patterning of the second flat thin film may include first exposing the second flat thin film, and then developing the exposed second flat thin film to form a patterned second flat layer 16.

[0120] In exemplary embodiments, the second flat layer may be made of an organic material, such as a resin.

[0121] Figure 14 is a schematic diagram of the structure of the first and second partition dams in Figure 13. As shown in Figure 14, in exemplary embodiments, a strong alkaline solution may be used as the developer for the developing process. After the second flat thin film of the partition region 220 is removed, the sides of the first partition layer 40 and the second partition layer 50 are exposed, and under the action of the strong alkaline solution, the sides of the first partition layer 40 and the second partition layer 50 are eroded by the developer. For the first partition layer 40 and the second partition layer 50, which employ a multi-layer composite structure of Ti / Al / Ti, the erosion rate of the developer on the aluminum layer is greater than the erosion rate on the titanium layer, so a lateral depression is formed on the eroded side of the second partition layer 50, and the upper part of the aluminum layer and the upper titanium layer protrude a certain distance from the aluminum layer, forming an "I" shaped structure.

[0122] In an exemplary embodiment, in the second partition layer 50 having an "I" shaped structure, the width of the second metal sublayer 52 may be smaller than the width of the first metal sublayer 51, the orthographic projection of the second metal sublayer 52 on the base may be within the range of the orthographic projection of the first metal sublayer 51 on the base, the width of the second metal sublayer 52 may be smaller than the width of the third metal sublayer 53, and the orthographic projection of the second metal sublayer 52 on the base may be within the range of the orthographic projection of the third metal sublayer 53 on the base.

[0123] In exemplary embodiments, the width of the first metal sublayer 51 may be equal to the width of the third conductive sublayer 43, the sides of the first metal sublayer 51 and the sides of the third conductive sublayer 43 may be aligned, and the orthographic projection of the base of the first metal sublayer 51 and the orthographic projection of the base of the third conductive sublayer 43 may substantially overlap.

[0124] In exemplary embodiments, a fifth insulating layer may be formed first to cover the anode connection electrode 17, and then a second flat layer 16 may be formed on the fifth insulating layer, or the fifth insulating layer may be formed only on the display area 100, and the disclosure is not limited thereto. In exemplary embodiments, the fifth insulating layer may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layer, and the fifth insulating layer may be referred to as a blunted (PVX) layer.

[0125] To date, the manufacturing of the patterns for the drive structure layer 101 of the display area 100 and the hole area structure layer 201 of the partition area 220 has been completed.

[0126] In an exemplary embodiment, the drive structure layer 101 of the display area 100 may include a first insulating layer 11, a semiconductor layer, a second insulating layer 12, a first conductive layer, a third insulating layer 13, a second conductive layer, a fourth insulating layer 14, a third conductive layer, a first flat layer 15, a fourth conductive layer, and a second flat layer 16, which are sequentially stacked on the base 10. The semiconductor layer may include a first active layer, the first conductive layer may include a first gate electrode and a first electrode plate, the second conductive layer may include a second electrode plate, the third conductive layer may include a first source electrode and a first drain electrode, and the fourth conductive layer may include an anode connection electrode, the anode connection electrode being connected to the first drain electrode via a first connection via.

[0127] In an exemplary embodiment, the hole region structure layer 201 of the partition region 220 may include a composite insulating layer, a first partition layer 40 and a second partition layer 50 that are sequentially laminated on the base 10, the first partition layer 40 being installed on the side of the composite insulating layer away from the base, and the second partition layer 50 being installed on the side of the first partition layer 40 away from the base, and the laminated first partition layer 40 and the second partition layer 50 constitute a partition dam structure. The first partition layer 40 may be installed on the same layer as the third conductive layer in the drive structure layer 101 and formed simultaneously in the same patterning process, and the second partition layer 50 may be installed on the same layer as the fourth conductive layer in the drive structure layer 101 and formed simultaneously in the same patterning process.

[0128] (15) Forming an anodic conductive layer pattern. In an exemplary embodiment, as shown in Figure 15, the formation of an anodic conductive layer pattern may include depositing an anodic conductive thin film on a base on which the pattern is to be formed, and then patterning the anodic conductive thin film by a patterning process to form an anodic conductive layer pattern.

[0129] In an exemplary embodiment, the anode conductive layer pattern may include an anode 21 located at least in the display area 100, and the anode 21 is connected to the anode connection electrode 17 via a second connection via K2.

[0130] In exemplary embodiments, the anode conductive layer (AND) may be made of a metallic material or a transparent conductive material. The metallic material may include one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). In exemplary embodiments, the anode conductive layer may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0131] Figure 16 is a schematic diagram of the structure of the first and second partition layers in Figure 15. As shown in Figure 16, in exemplary embodiments, the etching process for patterning the anodic conductive thin film may employ a wet etching process. After the anodic conductive thin film of the partition region 220 is removed, the sides of the first partition layer 40 and the second partition layer 50 are exposed, and under the action of the etching solution, the sides of the first partition layer 40 and the second partition layer 50 are etched by the etching solution. Since the etching rate of the etching solution for the aluminum layer is greater than the etching rate for the titanium layer, the lateral depressions of the first partition layer 40 and the second partition layer 50 become more pronounced, the upper part of the aluminum layer and the upper titanium layer protrude a certain distance from the aluminum layer, and the first partition layer 40 and the second partition layer 50 each form an "I" shape structure.

[0132] In the exemplary embodiment, since the second partition layer 50 is located on the side away from the base of the first partition layer 40, the degree of etching of the second partition layer 50 by the etching solution is greater than the degree of etching of the first partition layer 40 by the etching solution. That is, the amount of etching of the second metal sublayer 52 in the second partition layer 50 is greater than the amount of etching of the second conductive sublayer 42 in the first partition layer 40, and the amount of etching of the first metal sublayer 51 and the third metal sublayer 53 in the second partition layer 50 is greater than the amount of etching of the first conductive sublayer 41 and the third conductive sublayer 43 in the first partition layer 40.

[0133] In the exemplary embodiment, along the direction away from the functional hole, the width LT2 of the third metal sublayer 53 may be less than or equal to the width LB2 of the first metal sublayer 51, and the orthographic projection of the base of the third metal sublayer 53 may be located within the range of the orthographic projection of the base of the first metal sublayer 51.

[0134] In exemplary embodiments, along the direction away from the functional hole, the width LM2 of the second metal sublayer 52 may be smaller than the width LB2 of the first metal sublayer 51, and the orthographic projection of the second metal sublayer 52 at the base may be within the range of the orthographic projection of the first metal sublayer 51 at the base.

[0135] In exemplary embodiments, along the direction away from the functional hole, the width LM2 of the second metal sublayer 52 may be smaller than the width LT2 of the third metal sublayer 53, and the orthographic projection of the base of the second metal sublayer 52 may be located within the range of the orthographic projection of the base of the third metal sublayer 53.

[0136] In exemplary embodiments, along the direction away from the functional hole, the width LT1 of the third conductive sublayer 43 may be less than or equal to the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third conductive sublayer 43 at the base may be within the range of the orthographic projection of the first conductive sublayer 41 at the base.

[0137] In exemplary embodiments, along the direction away from the functional hole, the width LM1 of the second conductive sublayer 42 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the second conductive sublayer 42 at the base may be within the range of the orthographic projection of the first conductive sublayer 41 at the base.

[0138] In exemplary embodiments, along the direction away from the functional hole, the width LM1 of the second conductive sublayer 42 may be smaller than the width LT1 of the third conductive sublayer 43, and the orthographic projection of the second conductive sublayer 42 at the base may be within the range of the orthographic projection of the third conductive sublayer 43 at the base.

[0139] In exemplary embodiments, along the direction away from the functional hole, the width LB2 of the first metal sublayer 51 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the first metal sublayer 51 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0140] In exemplary embodiments, along the direction away from the functional hole, the width LM2 of the second metal sublayer 52 may be smaller than the width LM1 of the second conductive sublayer 42, and the orthographic projection of the second conductive sublayer 42 at the base may be within the range of the orthographic projection of the second metal sublayer 52 at the base.

[0141] In exemplary embodiments, along the direction away from the functional hole, the width LT2 of the third metal sublayer 53 may be smaller than the width LT1 of the third conductive sublayer 43, and the orthographic projection of the third metal sublayer 53 at the base may be within the range of the orthographic projection of the third conductive sublayer 43 at the base.

[0142] In exemplary embodiments, along the direction away from the functional hole, the width LB2 of the first metal sublayer 51 may be less than or equal to the width LT1 of the third conductive sublayer 43, and the orthographic projection of the first metal sublayer 51 on the base may be located within the range of the orthographic projection of the third conductive sublayer 43 on the base.

[0143] In the exemplary embodiment, the width LB1 of the first conductive sublayer 41 may be approximately 5.0 μm to 5.8 μm, the width LM1 of the second conductive sublayer 42 may be approximately 4.2 μm to 4.8 μm, the width LT1 of the third conductive sublayer 43 may be approximately 4.8 μm to 5.6 μm, the width LB2 of the first metal sublayer 51 may be approximately 4.6 μm to 5.4 μm, the width LM2 of the second metal sublayer 52 may be approximately 3.8 μm to 4.6 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.4 μm to 5.2 μm. For example, the width LB1 of the first conductive sublayer 41 may be approximately 5.4 μm, the width LM1 of the second conductive sublayer 42 may be approximately 4.6 μm, the width LT1 of the third conductive sublayer 43 may be approximately 5.2 μm, the width LB2 of the first metal sublayer 51 may be approximately 5.0 μm, the width LM2 of the second metal sublayer 52 may be approximately 4.2 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.8 μm.

[0144] Figure 17 is a schematic diagram of the other structure of the first and second partition layers in Figure 15. As shown in Figure 17, since the second partition layer 50 is located on the side away from the base of the first partition layer 40, the degree of etching of the second partition layer 50 by the etching solution is greater than the degree of etching of the first partition layer 40 by the etching solution. Furthermore, for the second conductive sublayer 42 and the second metal sublayer 52, the degree of etching of the region away from the base is greater than the degree of etching of the region closer to the base, resulting in a trapezoidal cross-sectional shape for the second conductive sublayer 42 and the second metal sublayer 52.

[0145] In exemplary embodiments, the trapezoidal side walls may be straight or curved.

[0146] In the exemplary embodiment, since the cross-sectional shape of the second metal sublayer 52 is trapezoidal, the portion of the third metal sublayer 53 that protrudes from the second metal sublayer 52 is not supported and forms an arc that hangs downwards towards the base.

[0147] In an exemplary embodiment, the distance H1 between the edge of the third metal sublayer 53 and the base may be smaller than the distance H2 between the surface of the second metal sublayer 52 away from the base and the base. The edge of the third metal sublayer 53 refers to the edge of the third metal sublayer 53 closer to the display area and the edge of the third metal sublayer 53 away from the display area.

[0148] (16) Form a Pixel Define Layer (PDL) pattern. In an exemplary embodiment, as shown in Figure 18, the formation of the Pixel Define Layer pattern may include coating a Pixel Define Thin Film onto a base on which the pattern is to be formed, and then patterning the Pixel Define Thin Film by a patterning process to form a Pixel Define Layer 22 pattern.

[0149] In an exemplary embodiment, the pixel definition layer 22 may be formed only in the display area 100, and the pixel definition thin film in the partition area 220 is removed. A pixel aperture is provided in the pixel definition layer 22 of each subpixel in the display area 100, the pixel definition thin film within the pixel aperture is removed, and the surface of the anode 21 of the subpixel is exposed.

[0150] In exemplary embodiments, the material of the pixel definition layer may include polyimide or acrylic. In exemplary embodiments, a half-tone mask patterning process is used to form a spacer pillar pattern when forming the pixel definition layer, and the spacer pillars may be positioned outside the pixel aperture, and the spacer pillars are configured to support a fine metal mask in a subsequent deposition process, but the disclosure is not limited thereto.

[0151] In exemplary embodiments, the shape of the pixel aperture in a plane parallel to the base may be rectangular, square, pentagonal, hexagonal, circular, or elliptical, etc. In a plane perpendicular to the base, the cross-sectional shape of the pixel aperture may be rectangular or trapezoidal, etc., and the inner side walls of the pixel aperture may be flat or curved, but this disclosure is not limited thereto.

[0152] (17) Forming an organic light-emitting layer pattern. In an exemplary embodiment, as shown in Figure 19, the organic light-emitting layer pattern is formed by forming a pattern of the organic light-emitting layer 23 and the organic light-emitting block 24 on a base on which the pattern is formed by a vapor deposition method or an inkjet printing method.

[0153] In exemplary embodiments, the organic light-emitting layer 23 may be located in the display area 100 and the partition area 220, the organic light-emitting layer 23 in the display area 100 may be connected to the anode 21 of the subpixel located thereon via a pixel aperture, and the organic light-emitting layer 23 in the partition area 220 may be located in an area of ​​the partition area 220 other than the partition dam structure. In exemplary embodiments, the organic light-emitting block 24 may be located on the side of the partition area 220 away from the base of the partition dam structure, and the organic light-emitting block 24 and the organic light-emitting layer 23 in the partition area 220 are separated from each other.

[0154] Figure 20 is a schematic diagram of the blocking of the organic light-emitting material by the partition dam in Figure 19. As shown in Figure 20, the second partition layer 50 in the partition dam structure has an "I" shaped structure, and the upper third metal sublayer 53 has an "eaves" structure that protrudes from the second metal sublayer 52. Therefore, the organic light-emitting material is cut at the "eaves" structure of the second partition layer 50, forming an organic light-emitting block 24 on the side away from the base of the third metal sublayer 53. In an exemplary embodiment, the orthographic projection of the organic light-emitting block 24 on the base may substantially overlap with the orthographic projection of the third metal sublayer 53 on the base.

[0155] In an exemplary embodiment, the first partition layer 40 in the partition dam structure is an "I" shaped structure, and the upper third conductive sub-layer 43 has an "eaves" structure that protrudes from the second conductive sub-layer 42. Therefore, even if the organic light-emitting material is not cut in the "eaves" structure of the second partition layer 50, the organic light-emitting material is also cut in the "eaves" structure of the first partition layer 40, forming an organic light-emitting block 24 on the side away from the base of the third conductive sub-layer 43, effectively ensuring the separation of the organic light-emitting block 24 and the organic light-emitting layer 23. In this disclosure, by installing a partition dam in which double "I" shaped structures are stacked, the separation of the organic light-emitting block 24 and the organic light-emitting layer 23 can be maximized, the transmission path for water and oxygen is cut off, the intrusion of water and oxygen is effectively prevented, and the effectiveness and reliability of the seal can be ensured.

[0156] In the exemplary embodiment, compared to cases where the partition dam structure includes only the first partition layer 40 or only the second partition layer 50, the partition dam structure includes the first partition layer 40 and the second partition layer 50 which are installed in a stacked manner. As a result, the height of the partition dam structure is greater, maximizing the performance of blocking organic light-emitting materials and effectively enhancing the effectiveness and reliability of the sealing.

[0157] In exemplary embodiments, the organic light-emitting layer may include a light-emitting layer (EML) and one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0158] In exemplary embodiments, the organic light-emitting layer may be manufactured by the following manufacturing method. First, a hole injection layer, a hole transport layer, and an electron blocking layer are sequentially formed using an open mask (OPM) deposition process or an inkjet printing process to form a common layer of the hole injection layer, a hole transport layer, and an electron blocking layer on the display substrate. Then, a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer are formed in the corresponding subpixels using a fine metal mask (FMM) deposition process or an inkjet printing process. There may be a small overlap between the light-emitting layers of adjacent subpixels (for example, the area occupied by the overlapping portion in each light-emitting layer pattern is less than 10%), or they may be separated. Then, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially formed using an open mask deposition process or an inkjet printing process to form a common layer of the hole blocking layer, an electron transport layer, and an electron injection layer on the display substrate.

[0159] In exemplary embodiments, the organic light-emitting layer may include a microcavity regulating layer that satisfies the design of the microcavity length to the thickness of the organic light-emitting layer between the cathode and anode. In exemplary embodiments, a hole transport layer, an electron blocking layer, or an electron transport layer may be used as the microcavity regulating layer, and the disclosure is not limited herein.

[0160] In exemplary embodiments, the light-emitting layer may include a host material and a dopant material doped into the host material, with the doping ratio of the dopant material in the light-emitting layer being 1% to 20%. Within this range of doping ratios, on the one hand, the host material of the light-emitting layer can effectively transfer exciton energy to the dopant material of the light-emitting layer to excite the luminescence of the dopant material. On the other hand, the host material of the light-emitting layer "dilutes" the dopant material of the light-emitting layer, effectively improving fluorescence quenching due to intermolecular collisions and energy collisions of the dopant material of the light-emitting layer, thereby improving luminescence efficiency and device lifespan. In exemplary embodiments, the doping ratio refers to the ratio of the mass of the dopant material to the mass of the light-emitting layer, i.e., the mass percentage. In exemplary embodiments, both the host material and the dopant material can be deposited by a multi-component deposition process to uniformly disperse the host material and the dopant material in the light-emitting layer. The doping ratio can be adjusted by controlling the deposition rate of the dopant material during the deposition process, or by controlling the deposition rate ratio of the host material and the dopant material. In an exemplary embodiment, the thickness of the light-emitting layer may be approximately 10 nm to 50 nm.

[0161] In exemplary embodiments, the hole injection layer may be made of an inorganic oxide, such as molybdenum oxide, titanium oxide, vanadium oxide, rhenium oxide, ruthenium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silver oxide, tungsten oxide, or manganese oxide, or it may be made of a strongly electron-withdrawing p-type dopant and a hole transport material dopant. In exemplary embodiments, the thickness of the hole injection layer may be about 5 nm to 20 nm.

[0162] In exemplary embodiments, the hole transport layer may be made of a material with high hole mobility, such as aromatic amine compounds, and its substituents may be carbazole, methylfluorene, spirofluorene, dibenzothiophene, or furan. In exemplary embodiments, the thickness of the hole transport layer may be about 40 nm to 150 nm.

[0163] In exemplary embodiments, the hole blocking layer and electron transport layer may be aromatic heterocyclic compounds, such as imidazole derivatives including benzimidazole derivatives, imidazopyridine derivatives, benzimidazole phenanthridine derivatives, pyrimidine derivatives, triazine derivatives, din derivatives, quinoline derivatives, isoquinoline derivatives, phenanthroline derivatives, and other compounds containing a nitrogen-containing six-membered ring structure (including compounds having phosphine oxide substituents in the heterocycle). In exemplary embodiments, the thickness of the hole blocking layer may be about 5 nm to 15 nm, and the thickness of the electron transport layer may be about 20 nm to 50 nm.

[0164] In exemplary embodiments, the electron injection layer may be made of an alkali metal or other metal, such as lithium fluoride (LiF), ytterbium (Yb), magnesium (Mg), or calcium (Ca), or a compound of these alkali metals or metals. In exemplary embodiments, the thickness of the electron injection layer may be approximately 0.5 nm to 2 nm.

[0165] (18) Forming the cathode pattern. In an exemplary embodiment, as shown in Figure 21, the cathode pattern is formed by forming the cathode 25 and cathode block 26 patterns on the base on which the pattern is formed using an open mask deposition method.

[0166] In exemplary embodiments, the cathode 25 may be located in the display area 100 and the partition area 220, or it may be a full-surface structure. The cathode 25 in the display area 100 is connected to the organic light-emitting layer 23, achieving simultaneous connection between the organic light-emitting layer and the anode and cathode. The cathode 25 in the partition area 220 may be located in an area of ​​the partition area 220 other than the partition dam structure, and the cathode block 26 in the partition area 220 may be located on the side away from the base of the organic light-emitting block 24, so that the cathode block 26 and the cathode 25 in the partition area 220 are separated from each other.

[0167] Figure 22 is a schematic diagram of the cathode blocking by the partition dam in Figure 21. As shown in Figure 22, the second partition layer 50 in the partition dam structure has an "I" shaped structure, and the upper third metal sublayer 53 has an "eaves" structure that protrudes from the second metal sublayer 52. Therefore, the cathode material is cut at the "eaves" structure of the second partition layer 50, forming a cathode block 26 on the side away from the base of the organic light-emitting block 24. In an exemplary embodiment, the orthographic projection of the cathode block 26 on the base may substantially overlap with the orthographic projection of the organic light-emitting block 24 on the base.

[0168] In an exemplary embodiment, the first partition layer 40 in the partition dam structure is an "I" shaped structure, and the upper third conductive sub-layer 43 has an "eaves" structure that protrudes from the second conductive sub-layer 42. Therefore, even if the cathode material is not cut in the "eaves" structure of the second partition layer 50, the cathode material is cut in the "eaves" structure of the first partition layer 40, forming a cathode block 26 on the side away from the base of the organic light-emitting block 24, effectively ensuring the separation of the cathode block 26 and the cathode 25. In this disclosure, by installing a partition dam structure in which double "I" shaped structures are stacked, the separation of the cathode block 26 and the cathode 25 can be maximized, the transmission path for water and oxygen is cut off, the intrusion of water and oxygen is effectively prevented, and the effectiveness and reliability of the seal can be ensured.

[0169] In the exemplary embodiment, compared to cases where the partition dam structure includes only the first partition layer 40 or only the second partition layer 50, the partition dam structure includes the first partition layer 40 and the second partition layer 50 which are installed in a stacked manner. As a result, the height of the partition dam structure is greater, maximizing the performance of blocking the cathode material and maximizing the effectiveness and reliability of the sealing.

[0170] In exemplary embodiments, the cathode may be one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy consisting of one or more of the above metals.

[0171] In some possible exemplary embodiments, an optical coupling layer pattern may be formed after the cathode pattern is formed, the optical coupling layer being located at the cathode, and the refractive index of the optical coupling layer may be greater than that of the cathode, contributing to light extraction and increasing the light extraction efficiency. The material of the optical coupling layer may be an organic material, an inorganic material, or both an organic and an inorganic material, and may be a single layer, multiple layers, or a composite layer, but is not limited herein.

[0172] To date, the manufacturing of the luminescent structure layer 102 patterns has been completed. The luminescent structure layer 102 of the display area 100 may include an anode 21, a pixel definition layer 22, an organic luminescent layer 23, and a cathode 25, with the organic luminescent layer 23 being placed between the anode 21 and the cathode 25.

[0173] (19) Forming a sealing structure layer pattern. In an exemplary embodiment, as shown in Figure 23, the formation of the sealing structure layer pattern is as follows: First, a first sealing thin film is deposited by an open-mask deposition method to form a first sealing layer 31 pattern in the display area 100 and the partition area 220, with the first sealing layer 31 in the display area 100 covering the cathode 25 and the first sealing layer 31 in the partition area 220 surrounding the partition dam structure. Then, a second sealing material is printed using an inkjet printing process to form a second sealing layer 32 pattern in the display area 100, with the second sealing layer 32 in the display area 100 being placed on the first sealing layer 31. Then, a third sealing thin film is deposited by an open-mask deposition method to form a third sealing layer 33 pattern in the display area 100 and the partition area 220, with the third sealing layer 33 in the display area 100 being placed on the second sealing layer 32 and the third sealing layer 33 in the partition area 220 being placed outside the first sealing layer 31 surrounding the partition dam structure.

[0174] In exemplary embodiments, the first and third sealing layers may be one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single layers, multiple layers, or composite layers. Chemical vapor deposition (CVD) or atomic layer deposition (ALD) methods may be employed, ensuring that external water and oxygen cannot penetrate the light-emitting structure layer. The second sealing layer may be an organic material, such as a resin, which surrounds each film layer of the display area, improving structural stability and flatness. In this way, the first, second, and third sealing layers, which are stacked, constitute a sealing structure layer, and the resulting inorganic / organic / inorganic stacked structure ensures the integrity of the sealing and effectively isolates it from external water and oxygen.

[0175] Figure 24 is a schematic diagram showing the partition dam structure in Figure 23 surrounded by the first sealing layer. As shown in Figure 24, the first sealing layer 31 surrounding the partition dam structure means that the first sealing layer 31 covers all surfaces exposed from the partition dam structure, i.e., the first sealing layer 31 covers the cathode block 26 on the side away from the base of the partition dam structure, the inner surface on the side facing the display area 100 of the partition dam structure, and the outer surface on the side away from the display area 100 of the partition dam structure, thereby forming a complete enclosure of the partition dam structure by the first sealing layer 31. In exemplary embodiments of this disclosure, by installing the partition dam structure and completely surrounding it with the first and third sealing layers, the transmission paths for water and oxygen can be severed, the intrusion of water and oxygen can be effectively prevented, and the effectiveness and reliability of the seal can be ensured.

[0176] To this end, a sealing structure layer pattern is formed to ensure the integrity of the seal and effectively isolate it from external water and oxygen. In the display area 100, the sealing structure layer includes a first sealing layer, a second sealing layer, and a third sealing layer that are stacked, and can form a laminated structure of inorganic material / organic material / inorganic material. In the partition area 220, the sealing structure layer includes a first sealing layer and a third sealing layer that are stacked, and can form a laminated structure of inorganic material / inorganic material.

[0177] In exemplary embodiments, a touch structure layer (TSP) may be formed on the encapsulation layer after the encapsulation layer has been manufactured, and the touch structure layer may include a touch electrode layer, or may include a touch electrode layer and a touch insulating layer, but is not limited herein.

[0178] In exemplary embodiments, when manufacturing a flexible display substrate, the manufacturing process of the display substrate may further include processes such as attaching and cutting a backing film, and this disclosure is not limited thereto.

[0179] In the display substrate, the partition area 220 forms a partition dam with multiple perimeters using a third conductive layer (SD1). Not only is the process remaining amount demanded, but the barrier effect of the partition dam structure is effective. In particular, as reliability requirements become increasingly stringent and reliability test times become longer, there is a risk that water vapor will penetrate the single-layer partition dam and be transmitted to the display area. Furthermore, because the height of the single-layer partition dam employing an "I" shaped structure is low, in the subsequent process of forming the first and third sealing layers using a deposition method, the "eaves" structure on the upper side of the "I" shaped structure blocks the particles of gas phase deposition. As a result, the sealing material cannot be filled into the side depressions of the single-layer partition dam, forming cavities. In addition, the steep slope of the side walls of the "I" shaped structure causes cracks (CVD cracks) to appear in the first and third sealing layers. After the external water vapor enters the cavities or cracks, it diffuses into the display area, causing product failure.

[0180] As can be seen from the structure and manufacturing process of the display substrate in the exemplary embodiment of this disclosure, the partition dam structure in the exemplary embodiment of this disclosure includes a first partition layer consisting of a third conductive layer (SD1) and a second partition layer consisting of a fourth conductive layer (SD2), and the height of the partition dam structure is approximately the sum of the thicknesses of the third and fourth conductive layers. The large height of the partition dam structure not only effectively reduces the requirements for process residue but also effectively improves the barrier effect of the partition dam structure, eliminates the risk of water vapor being transmitted beyond the partition dam structure to the display area, and effectively enhances the effectiveness and reliability of the sealing. In this disclosure, by increasing the height of the partition dam structure, the swirling space for gas-phase deposited particles in the subsequent process of forming the first and third sealing layers using a deposition method becomes larger, making it easier to fill the sealing material into the side recesses of the partition dam and avoiding the formation of cavities. In this disclosure, both the first and second partition layers are installed in an "I" shape, and the two-layered "I" shape structure forms at least two "eaves" structures, thereby maximizing the cutting of the organic light-emitting material and improving the barrier effect of the partition dam structure, as well as maximizing the shear stress resistance capacity of the first and third sealing layers and effectively avoiding delamination failure of the first and third sealing layers. In this disclosure, the width of the second partition layer is set to be smaller than the width of the first partition layer, that is, the width of the third metal sublayer is smaller than the width of the third conductive sublayer, the width of the second metal sublayer is smaller than the width of the second conductive sublayer, and the width of the first metal sublayer is smaller than the width of the first conductive sublayer, thereby reducing the overall slope of the side walls of the partition dam structure, effectively reducing the deposition slope of the first and third sealing layers, effectively avoiding cavity formation in the side walls of the partition dam structure, and effectively avoiding crack formation in the first and third sealing layers. The display substrate according to the exemplary embodiments of this disclosure can effectively avoid encapsulation failure, improve the yield rate and product reliability of the display substrate, and enhance product quality and service life. The manufacturing process of the display substrate according to the exemplary embodiments of this disclosure has good process compatibility and utilizes a patterning process to form a first flat layer, a second flat layer and an anode, while simultaneously forming a two-layer "I" shaped partition dam structure, making the process easy to implement, easy to carry out, highly efficient, low in production costs, and with a high yield rate.

[0181] Figure 25 is a schematic diagram of the structure of another partition dam according to an exemplary embodiment of the present disclosure. As shown in Figure 25, the partition dam of this exemplary embodiment may include a first partition layer 40 and a second partition layer 50 which are stacked together, the first partition layer 40 may include a first conductive sublayer 41, a second conductive sublayer 42, and a third conductive sublayer 43 which are stacked together, and the second partition layer 50 may include a first metal sublayer 51, a second metal sublayer 52, and a third metal sublayer 53 which are stacked together. The first conductive sublayer 41 and the third conductive sublayer 43 have projections relative to the side wall 40B of the second conductive sublayer 42, and the two upper and lower projections and the side wall 40B of the second sublayer form a recessed structure, thereby forming a first "I" shaped structure for the first partition layer 40. The first metal sublayer 51 and the third metal sublayer 53 have protrusions relative to the side wall 50B of the second metal sublayer 52, and the two upper and lower protrusions and the side wall 50B of the second metal layer form a recessed structure, thereby forming a second "I" shaped structure for the second partition layer 50.

[0182] In an exemplary embodiment, the first "I" shaped structure and the second "I" shaped structure installed on the side away from the base of the first "I" shaped structure constitute a partition dam structure in which double "I" shaped structures are stacked.

[0183] In an exemplary embodiment, the overall width of the upper and lower parts of the partition dam structure may be greater than the overall width of the middle part of the partition dam structure, that is, the partition dam structure has an overall shape with a large upper and lower part and a small middle part, and the side walls of the partition dam structure form a "C" shape.

[0184] In exemplary embodiments, the width LT1 of the third conductive sublayer 43 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third conductive sublayer 43 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0185] In exemplary embodiments, the width LM1 of the second conductive sublayer 42 may be smaller than the width LB1 of the first conductive sublayer 41 and the width LT1 of the third conductive sublayer 43, and the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projections of the first conductive sublayer 41 and the third conductive sublayer 43 on the base.

[0186] In an exemplary embodiment, the width LT2 of the third metal sublayer 53 may be greater than the width LB2 of the first metal sublayer 51, and the orthographic projection of the base of the first metal sublayer 51 may be located within the range of the orthographic projection of the base of the third metal sublayer 53.

[0187] In an exemplary embodiment, the width LM2 of the second metal sublayer 52 may be smaller than the width LB2 of the first metal sublayer 51 and the width LT2 of the third metal sublayer 53, and the orthographic projection of the second metal sublayer 52 on the base may be within the range of the orthographic projections of the first metal sublayer 51 and the third metal sublayer 53 on the base.

[0188] In exemplary embodiments, the width LT2 of the third metal sublayer 53 may be equal to the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third metal sublayer 53 on the base may be substantially the same as the orthographic projection of the first conductive sublayer 41 on the base.

[0189] In an exemplary embodiment, the width LM2 of the second metal sublayer 52 may be equal to the width LM1 of the second conductive sublayer 42, and the orthographic projection of the second conductive sublayer 42 on the base may be substantially the same as the orthographic projection of the second metal sublayer 52 on the base.

[0190] In exemplary embodiments, the width LB2 of the first metal sublayer 51 may be equal to the width LT1 of the third conductive sublayer 43, and the orthographic projection of the first metal sublayer 51 on the base may be substantially the same as the orthographic projection of the third conductive sublayer 43 on the base.

[0191] In the exemplary embodiment, the width LB1 of the first conductive sublayer 41 may be approximately 5.0 μm to 5.8 μm, the width LM1 of the second conductive sublayer 42 may be approximately 3.8 μm to 4.6 μm, the width LT1 of the third conductive sublayer 43 may be approximately 4.0 μm to 4.8 μm, the width LB2 of the first metal sublayer 51 may be approximately 4.0 μm to 4.8 μm, the width LM2 of the second metal sublayer 52 may be approximately 3.8 μm to 4.6 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.4 μm to 5.2 μm. For example, the width LB1 of the first conductive sublayer 41 may be approximately 5.4 μm, the width LM1 of the second conductive sublayer 42 may be approximately 4.2 μm, the width LT1 of the third conductive sublayer 43 may be approximately 4.4 μm, the width LB2 of the first metal sublayer 51 may be approximately 4.4 μm, the width LM2 of the second metal sublayer 52 may be approximately 4.2 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.8 μm.

[0192] In exemplary embodiments, the manufacturing process of the display substrate in this exemplary embodiment is substantially the same as in the above embodiment, and includes the formation of a transistor structure layer, a first flat layer, a fourth conductive layer, a second flat layer, an anode conductive layer, a pixel definition layer, an organic light-emitting layer, a cathode, and a sealing structure layer. The difference is that in patterning the anode conductive layer, the third metal sublayer 53 in the second partition layer 50 is first protected with an anode conductive thin film, the second metal sublayer 52 and the first metal sublayer 51 in the second partition layer 50, the first conductive sublayer 41, the second conductive sublayer 42, and the third conductive sublayer 43 in the first partition layer 40 are etched by a wet etching process, and then further etching is performed by a dry etching process (e.g., SF6). Because SF6 has different etching rates for the titanium layer and the aluminum layer, it is mainly possible to remove the third conductive sublayer 43 and the first metal sublayer 51. Then, a wet etching process is used to etch the anodic conductive thin film protecting the third metal sublayer 53, ultimately forming a partition dam structure with side walls in a "C" shape.

[0193] In this exemplary embodiment, increasing the height of the partition dam structure not only effectively enhances the barrier effect of the partition dam structure, but also, by forming the side walls of the partition dam in a "C" shape, the sealing material layer effectively covers the side walls of the partition dam, effectively avoiding the formation of cavities in the side walls of the partition dam, effectively avoiding the occurrence of cracks in the sealing material layer, effectively avoiding seal failure, and improving the yield rate and product reliability of the display substrate.

[0194] Figure 26 is a schematic diagram of a further partition dam structure according to an exemplary embodiment of the present disclosure. As shown in Figure 26, the partition dam of this exemplary embodiment may include a first partition layer 40 and a second partition layer 50 that are stacked together. The first partition layer 40 may include a first conductive sublayer 41, a second conductive sublayer 42, and a third conductive sublayer 43 that are stacked together, and the second partition layer 50 may include a first metal sublayer 51, a second metal sublayer 52, and a third metal sublayer 53 that are stacked together. The cross-sectional shape of the first partition layer 40 is a trapezoidal structure, and the cross-sectional shape of the second partition layer 50 is an "I" shaped structure. The trapezoidal structure and the "I" shaped structure installed on the side away from the base of the trapezoidal structure together constitute a partition dam structure in which the lower trapezoidal structure and the upper "I" shaped structure are stacked together.

[0195] In an exemplary embodiment, the cross-sectional shape of the second conductive sublayer 42 is trapezoidal and includes a first upper base on the side away from the base, a first lower base on the side closer to the base, and a first side wall 40B connected between the first upper base and the first lower base. In an exemplary embodiment, the first side wall 40B may be linear or arc-shaped.

[0196] In an exemplary embodiment, the first metal sublayer 51 and the third metal sublayer 53 have protrusions relative to the side wall 50B of the second metal sublayer 52, and the two upper and lower protrusions and the side wall 50B of the second metal layer form a recessed structure, thereby forming a second "I" shaped structure for the second partition layer 50.

[0197] In exemplary embodiments, the width LT1 of the third conductive sublayer 43 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third conductive sublayer 43 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0198] In the exemplary embodiment, the width LT1 of the third conductive sublayer 43 may be equal to the width of the first upper base of the second conductive sublayer 42, and the width LB1 of the first conductive sublayer 41 may be equal to the width of the first lower base of the second conductive sublayer 42.

[0199] In an exemplary embodiment, the width LT2 of the third metal sublayer 53 may be less than or equal to the width LB2 of the first metal sublayer 51, and the orthographic projection of the third metal sublayer 53 at the base may be within the range of the orthographic projection of the first metal sublayer 51 at the base.

[0200] In an exemplary embodiment, the width LM2 of the second metal sublayer 52 may be smaller than the width LB2 of the first metal sublayer 51 and the width LT2 of the third metal sublayer 53, and the orthographic projection of the second metal sublayer 52 on the base may be within the range of the orthographic projections of the first metal sublayer 51 and the third metal sublayer 53 on the base.

[0201] In exemplary embodiments, the width LT2 of the third metal sublayer 53 may be smaller than the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third metal sublayer 53 on the base may be within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0202] In exemplary embodiments, the width LB2 of the first metal sublayer 51 may be equal to the width LT1 of the third conductive sublayer 43, and the orthographic projection of the first metal sublayer 51 on the base may be substantially the same as the orthographic projection of the third conductive sublayer 43 on the base.

[0203] In exemplary embodiments, the width LB1 of the first conductive sublayer 41 may be approximately 5.0 μm to 5.8 μm, the width LT1 of the third conductive sublayer 43 may be approximately 4.8 μm to 5.6 μm, the width LB2 of the first metal sublayer 51 may be approximately 4.6 μm to 5.4 μm, the width LM2 of the second metal sublayer 52 may be approximately 3.8 μm to 4.6 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.4 μm to 5.2 μm. For example, the width LB1 of the first conductive sublayer 41 may be approximately 5.4 μm, the width LT1 of the third conductive sublayer 43 may be approximately 5.2 μm, the width LB2 of the first metal sublayer 51 may be approximately 5.0 μm, the width LM2 of the second metal sublayer 52 may be approximately 4.2 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.8 μm.

[0204] In an exemplary embodiment, the manufacturing process of the display substrate in this exemplary embodiment is substantially the same as in the above embodiment, and includes the formation of a transistor structure layer, a first flat layer, a fourth conductive layer, a second flat layer, an anode conductive layer, a pixel definition layer, an organic light-emitting layer, a cathode, and a sealing structure layer. The difference is that a trapezoidal first partition layer 40 is formed when patterning the third conductive thin film, the first flat film is used to protect the first partition layer 40 when forming the first flat layer pattern, a second partition layer 50 with an "I" shape is formed when protecting the first partition layer 40 during the patterning of the second flat layer and the anode conductive layer, and finally a partition dam structure is formed in which the lower trapezoidal structure and the upper "I" shape structure are stacked.

[0205] In this exemplary embodiment, increasing the height of the partition dam structure not only effectively enhances the barrier effect of the partition dam structure, but also constructs the partition dam by combining a trapezoidal structure and an "I"-shaped structure. The upper "I"-shaped structure achieves barrier protection for the organic light-emitting material, and the lower trapezoidal structure achieves good adhesion of the sealing material layer. As a result, the sealing material layer effectively covers the side walls of the partition dam, effectively avoiding the formation of cavities in the side walls of the partition dam, effectively avoiding the occurrence of cracks in the sealing material layer, effectively avoiding sealing failure, and improving the yield rate and product reliability of the display substrate.

[0206] Figure 27 is a schematic diagram of a further partition dam structure according to an exemplary embodiment of the present disclosure. As shown in Figure 27, the partition dam of this exemplary embodiment may include a first partition layer 40 and a second partition layer 50 that are stacked together. The first partition layer 40 may include a first conductive sublayer 41, a second conductive sublayer 42, and a third conductive sublayer 43 that are stacked together, and the second partition layer 50 may include a first metal sublayer 51, a second metal sublayer 52, and a third metal sublayer 53 that are stacked together. The cross-sectional shape of the first partition layer 40 is an "I" shape structure, and the cross-sectional shape of the second partition layer 50 is a trapezoidal structure. The "I" shape structure and the trapezoidal structure installed on the side away from the base of the "I" shape structure together constitute a partition dam structure in which the upper trapezoidal structure and the lower "I" shape structure are stacked together.

[0207] In an exemplary embodiment, the first conductive sublayer 41 and the third conductive sublayer 43 have protrusions relative to the side wall 40B of the second conductive sublayer 42, and the two upper and lower protrusions and the side wall 40B of the second sublayer form a recessed structure, thereby forming a first "I" shaped structure for the first partition layer 40.

[0208] In an exemplary embodiment, the cross-sectional shape of the second metal sublayer 52 is trapezoidal and includes a second upper base on the side away from the base, a second lower base on the side closer to the base, and a second side wall 50B connecting the second upper base and the second lower base. In an exemplary embodiment, the second side wall 50B may be straight or curved.

[0209] In exemplary embodiments, the width LT1 of the third conductive sublayer 43 may be less than or equal to the width LB1 of the first conductive sublayer 41, and the orthographic projection of the third conductive sublayer 43 on the base may be located within the range of the orthographic projection of the first conductive sublayer 41 on the base.

[0210] In exemplary embodiments, the width LM1 of the second conductive sublayer 42 may be smaller than the width LB1 of the first conductive sublayer 41 and the width LT1 of the third conductive sublayer 43, and the orthographic projection of the second conductive sublayer 42 on the base may be within the range of the orthographic projections of the first conductive sublayer 41 and the third conductive sublayer 43 on the base.

[0211] In exemplary embodiments, the width LT2 of the third metal sublayer 53 may be smaller than the width LB2 of the first metal sublayer 51, and the orthographic projection of the third metal sublayer 53 at the base may be within the range of the orthographic projection of the first metal sublayer 51 at the base.

[0212] In the exemplary embodiment, the width LT2 of the third metal sublayer 53 may be equal to the width of the second upper base of the second metal sublayer 52, and the width LB2 of the first metal sublayer 51 may be equal to the width of the second lower base of the second metal sublayer 52.

[0213] In exemplary embodiments, the width LB2 of the first metal sublayer 51 may be less than or equal to the width LT1 of the third conductive sublayer 43, and the orthographic projection of the base of the first metal sublayer 51 and the orthographic projection of the base of the third conductive sublayer 43 may be substantially the same.

[0214] In exemplary embodiments, the width LB1 of the first conductive sublayer 41 may be approximately 5.0 μm to 5.8 μm, the width LM1 of the second conductive sublayer 42 may be approximately 4.6 μm to 5.4 μm, the width LT1 of the third conductive sublayer 43 may be approximately 4.8 μm to 5.6 μm, the width LB2 of the first metal sublayer 51 may be approximately 4.6 μm to 5.4 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.4 μm to 5.2 μm. For example, the width LB1 of the first conductive sublayer 41 may be approximately 5.4 μm, the width LM1 of the second conductive sublayer 42 may be approximately 5.0 μm, the width LT1 of the third conductive sublayer 43 may be approximately 5.2 μm, the width LB2 of the first metal sublayer 51 may be approximately 5.0 μm, and the width LT2 of the third metal sublayer 53 may be approximately 4.8 μm.

[0215] In exemplary embodiments, the manufacturing process of the display substrate in this exemplary embodiment is substantially the same as in the above embodiment, and includes the formation of a transistor structure layer, a first flat layer, a fourth conductive layer, a second flat layer, an anode conductive layer, a pixel definition layer, an organic light-emitting layer, a cathode, and a sealing structure layer. The difference is that in the patterning of the first flat layer, the side etching of the first partition layer 40 is completed using both development and a wet etching process to form the first partition layer 40 with an "I" shaped structure, and in the patterning of the second flat layer and the anode conductive layer, the second partition layer 50 is surrounded and protected by photoresist throughout and is not side-etched, ultimately forming a partition dam structure in which the upper trapezoidal structure and the lower "I" shaped structure are stacked.

[0216] In this exemplary embodiment, increasing the height of the partition dam structure not only effectively enhances the barrier effect of the partition dam structure, but also constructs the partition dam by combining a trapezoidal structure and an "I"-shaped structure. The lower "I"-shaped structure achieves barrier protection for the organic light-emitting material, and the upper trapezoidal structure achieves good adhesion of the sealing material layer. As a result, the sealing material layer effectively covers the side walls of the partition dam, effectively avoiding the formation of cavities in the side walls of the partition dam, effectively avoiding the occurrence of cracks in the sealing material layer, effectively avoiding sealing failure, and improving the yield rate and product reliability of the display substrate.

[0217] The structure of the display substrate and the manufacturing process thereof in the exemplary embodiments of this disclosure are for illustrative purposes only. In the exemplary embodiments, the corresponding structure may be modified or the patterning process may be increased or decreased according to actual demand, and this disclosure is not limited thereto.

[0218] In exemplary embodiments, the display substrate of the present disclosure may be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), and the present disclosure is not limited thereto.

[0219] This disclosure further provides a method for manufacturing a display substrate. In exemplary embodiments, the display substrate may include a display area and at least one hole area located within the display area, wherein the hole area includes a functional hole and a partition area surrounding the functional hole, and the manufacturing method is as follows: The present invention may include forming at least one partition dam in the partition region that surrounds the functional hole, the partition dam comprising a first partition layer and a second partition layer installed in a stacked manner, the at least one partition layer comprising a second sub-layer and a third sub-layer installed on the side of the second sub-layer away from the base, the third sub-layer having a projection relative to the side wall of the second sub-layer, the projection and the side wall of the second sub-layer forming a recess structure.

[0220] This disclosure further provides a display device comprising a display substrate of the above embodiment. The display device may be a product or component having a display function such as a mobile phone, tablet, television, display, notebook computer, digital frame, or navigator.

[0221] The above are embodiments disclosed herein, but these are merely embodiments used to facilitate understanding of the disclosure and are not intended to limit it. Those skilled in the art may make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed herein, but the scope of protection of the patent of this application shall be limited to the claims attached. [Explanation of Symbols]

[0222] 10 Base 11 First insulating layer 12 Second insulating layer 13 Third insulating layer 14 Fourth insulating layer 15 First flat layer 16 Second flat layer 17 Anode connection electrode 21 Anode 22 Pixel definition layer 23 Organic light-emitting layer 24 Organic light-emitting block 25 Cathode 26 Cathode block 31 First sealing layer 32 Second sealing layer 33 Third sealing layer 40 First partition layer 41 First conductive sublayer 42 Second conductive sublayer 43 Third conductive sublayer 50 Second partition layer 51 First metal sublayer 52 Second metal sublayer 53 Third metal sublayer 100 Display area 101 Drive structure layer 102 Light-emitting structure layer 103 Sealing structure layer 200 Hole region 201 Hole area structural layer 210 Functional hole 220 Partition area 300 partition dams

Claims

1. The display area includes at least one hall area located within the display area, the hall area includes a functional hall and a partition area surrounding the functional hall, the partition area is provided with at least one partition dam surrounding the functional hall, the partition dam includes a first partition layer installed on a base and a second partition layer installed on the side of the first partition layer away from the base, The first partition layer includes a first conductive sublayer, a second conductive sublayer installed on the side of the first conductive sublayer away from the base, and a third conductive sublayer installed on the side of the second conductive sublayer away from the base, wherein, along the direction away from the functional hole, the width of the second conductive sublayer is smaller than the width of the first conductive sublayer and the third conductive sublayer, the orthographic projection of the second conductive sublayer on the base is within the range of the orthographic projection of the first conductive sublayer and the third conductive sublayer on the base, thereby the first conductive sublayer and the third conductive sublayer have protrusions relative to the sidewall of the second conductive sublayer, and the protrusions and the sidewall of the second conductive sublayer form a recessed structure. The second partition layer includes a first metal sublayer installed on the side of the first partition layer away from the base, a second metal sublayer installed on the side of the first metal sublayer away from the base, and a third metal sublayer installed on the side of the second metal sublayer away from the base, wherein, along the direction away from the functional hole, the width of each of the second metal sublayers is smaller than the width of the first and third metal sublayers, the orthographic projection of each of the second metal sublayers on the base is within the range of the orthographic projections of the first and third metal sublayers on the base, thereby the first and third metal sublayers having projections relative to the sidewall of the second metal sublayer, and the projections and the sidewall of the second metal sublayer form a recessed structure. A display substrate in which the distance between the edge of the third metal sublayer and the base is smaller than the distance between the surface of the second metal sublayer away from the base and the base.

2. Along the direction away from the functional hole, the width of the first metal sublayer is smaller than the width of the first conductive sublayer, and the orthographic projection of the first metal sublayer on the base is located within the range of the orthographic projection of the first conductive sublayer on the base. Alternatively, along the direction away from the functional hole, the width of the second metal sublayer is smaller than the width of the second conductive sublayer, and the orthographic projection of the second metal sublayer on the base is located within the range of the orthographic projection of the second conductive sublayer on the base. Alternatively, along the direction away from the functional hole, the width of the third metal sublayer is smaller than the width of the third conductive sublayer, and the orthographic projection of the third metal sublayer on the base is within the range of the orthographic projection of the third conductive sublayer on the base. Alternatively, the display substrate according to claim 1, wherein, along the direction away from the functional hole, the width of the third metal sublayer is less than or equal to the width of the first metal sublayer, the orthographic projection of the third metal sublayer on the base is located within the range of the orthographic projection of the first metal sublayer on the base, the width of the third conductive sublayer is less than or equal to the width of the first conductive sublayer, the orthographic projection of the third conductive sublayer on the base is located within the range of the orthographic projection of the first conductive sublayer on the base, the width of the first metal sublayer is less than or equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base is located within the range of the orthographic projection of the third conductive sublayer on the base.

3. The display substrate according to claim 1, wherein, along the direction away from the functional hole, the width of the third metal sublayer is greater than the width of the first metal sublayer, the orthographic projection of the first metal sublayer on the base is within the range of the orthographic projection of the third metal sublayer on the base, the width of the third conductive sublayer is smaller than the width of the first conductive sublayer, the orthographic projection of the third conductive sublayer on the base is within the range of the orthographic projection of the first conductive sublayer on the base, the width of the first metal sublayer is equal to the width of the third conductive sublayer, and the orthographic projection of the first metal sublayer on the base and the orthographic projection of the third conductive sublayer on the base substantially overlap.

4. The display substrate according to claim 1, wherein the display area includes a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially installed on the base, the first partition layer and the third conductive layer being installed on the same layer, and the second partition layer and the fourth conductive layer being installed on the same layer.

5. A display device comprising the display board described in claim 1.

6. A method for manufacturing a display board, wherein the display board includes a display area and at least one hole area located in the display area, the hole area includes a functional hole and a partition area surrounding the functional hole, and the manufacturing method is This includes forming at least one partition dam surrounding the functional hole in the partition region, wherein the partition dam includes a first partition layer and a second partition layer that are installed in a stacked manner. The first partition layer includes a first conductive sublayer, a second conductive sublayer installed on the side of the first conductive sublayer away from the base, and a third conductive sublayer installed on the side of the second conductive sublayer away from the base, wherein, along the direction away from the functional hole, the width of the second conductive sublayer is smaller than the width of the first conductive sublayer and the third conductive sublayer, the orthographic projection of the second conductive sublayer on the base is within the range of the orthographic projection of the first conductive sublayer and the third conductive sublayer on the base, thereby the first conductive sublayer and the third conductive sublayer have protrusions relative to the sidewall of the second conductive sublayer, and the protrusions and the sidewall of the second conductive sublayer form a recessed structure. The second partition layer includes a first metal sublayer installed on the side of the first partition layer away from the base, a second metal sublayer installed on the side of the first metal sublayer away from the base, and a third metal sublayer installed on the side of the second metal sublayer away from the base, wherein, along the direction away from the functional hole, the width of each of the second metal sublayers is smaller than the width of the first and third metal sublayers, the orthographic projection of each of the second metal sublayers on the base is within the range of the orthographic projections of the first and third metal sublayers on the base, thereby the first and third metal sublayers having projections relative to the sidewall of the second metal sublayer, and the projections and the sidewall of the second metal sublayer form a recessed structure. A method for manufacturing a display substrate, wherein the distance between the edge of the third metal sublayer and the base is smaller than the distance between the surface of the second metal sublayer away from the base and the base.

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