Display panel and manufacturing method, and display device.

Abstract

The display panel includes a base substrate, a driving circuit layer, a connection layer, and an anode layer. The driving circuit layer is provided on one side of the base substrate and includes a plurality of first-type pixel driving circuits located in a first display region. The connection layer is provided on a side of the driving circuit layer away from the base substrate and includes at least one conductive layer and at least one insulating layer, and each conductive layer has an insulating layer on its side away from the base substrate, the conductive layer includes a plurality of connection wirings, and the plurality of connection wirings include a plurality of first wirings. The anode layer is provided on a side of the connection layer away from the base substrate and includes a plurality of first-type anodes located in a second display region. The plurality of first-type anodes includes a plurality of first anodes, and each of two adjacent first anodes is electrically connected to one first-type pixel driving circuit via one first wiring.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a display panel, a manufacturing method, and a display device.

Background Art

[0002] A full display cell (FDC) uses an under-screen camera technology to hide a camera and other sensors directly below the screen, thereby achieving a full-screen display.

[0003] When the full display is displayed normally, the light-emitting elements in the light-emitting element layer emit light to form a display screen. When the camera and other sensors of the full display operate, some of the light-emitting elements facing the sensors stop emitting light, and the camera or other sensors operate by receiving external light rays through the light-emitting element layer that transmits light.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, some embodiments of the present disclosure provide a display panel including a display area. The display area includes a first display area and a second display area.

[0005] The display panel includes a display area, and the display area includes a first display area and a second display area.

[0006] The display panel includes a base substrate, a driving circuit layer provided on one side of the base substrate, a connection layer, and an anode layer. The driving circuit layer includes a plurality of first-type pixel driving circuits located in the first display area. The connection layer includes a plurality of connection wirings. The plurality of connection wirings includes a plurality of first wirings. The anode layer includes a plurality of first-type anodes located in the second display area. The plurality of first-type anodes includes a plurality of first anodes. At least two first anodes are electrically connected to one first-type pixel driving circuit via a first wiring.

[0007] In some embodiments, the multiple connection wires further comprise multiple third wires. The third wires connect at least two first anodes. The first wires connect one third wire to one first-type pixel driving circuit in order to electrically connect at least two first anodes to the first-type pixel driving circuit.

[0008] In some embodiments, the multiple first-type anodes further comprise multiple second-type anodes and multiple third-type anodes. The multiple connecting wires further comprise multiple second-type wires. The second-type anodes are electrically connected to one first-type pixel driving circuit via the second-type wires. The third-type anodes are electrically connected to one first-type pixel driving circuit via the second-type wires.

[0009] In some embodiments, at least two first anodes constitute a first anode group. Of an adjacent first anode group, a second anode, and a third anode, the length of the first wire electrically connected to the first anode group is smaller than the length of the second wire electrically connected to the second anode and also smaller than the length of the second wire electrically connected to the third anode.

[0010] In some embodiments, the connection layer is located on the side of the drive circuit layer away from the base substrate. The anode layer is located on the side of the connection layer away from the base substrate.

[0011] In some embodiments, the connecting layer comprises at least one conductive layer and at least one insulating layer, with one insulating layer provided on the side of each conductive layer away from the base substrate. In some embodiments, the connecting layer comprises a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer. The first conductive layer is provided on the side of the drive circuit layer away from the base substrate. The first insulating layer is provided on the side of the first conductive layer away from the base substrate. The second conductive layer is provided on the side of the first insulating layer away from the base substrate. The second insulating layer is provided on the side of the second conductive layer away from the base substrate. The first conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, and the second conductive layer comprises a plurality of first wirings and / or a plurality of second wirings. The plurality of connecting wirings further comprises a plurality of third wirings, and the connected third wirings and first wirings are located on the same conductive layer. The first insulating layer has a first via hole, the second insulating layer has a second via hole, the first conductive layer is electrically connected to the second conductive layer via the first via hole, and the second conductive layer is electrically connected to the anode layer via the second via hole.

[0012] In some embodiments, multiple Type 1 anodes are arranged in multiple Type 1 anode rows. At least one Type 1 anode row comprises at least two first anodes, at least one second anode, and at least one third anode, arranged in a row. At least two first anodes in the Type 1 anode row are electrically connected to a first wiring.

[0013] In some other embodiments, the multiple Type 1 anodes are arranged in multiple Type 1 anode rows. At least one Type 1 anode row comprises at least two first anodes, at least one second anode, and at least one third anode arranged in a row. At least two first anodes in the Type 1 anode row are electrically connected to a first wiring.

[0014] In some embodiments, at least one TheThe Type 1 anode row is arranged periodically in the order of second anode, first anode, third anode, and first anode. Multiple connection wires are arranged in multiple wiring groups. Each wiring group comprises at least one first wire and at least two second wires. Multiple connection wires extend along a first direction. The first direction is multiple Type 1 This is the row direction in which the anodes are arranged. In the wiring group, the first wiring is connected to correspond to at least two first anodes in the first type anode row, and the second wiring is connected to correspond to one second anode or one third anode in the first type anode row.

[0015] In some other embodiments, in a wiring group, the first wiring is connected to correspond to at least two first anodes in a first type anode row. At least two second wirings in the wiring group comprise at least one first subwiring and at least one second subwiring. The first subwiring is connected to correspond to one second anode or one third anode in a first type anode row. The second subwiring is electrically connected to one second anode or one third anode in another first type anode row adjacent to the first type anode row.

[0016] In some embodiments, at least one first-type anode array is arranged periodically in the order of second anode, first anode, third anode, and first anode. Multiple connection wires are arranged in multiple wiring groups. Each wiring group comprises at least one first wire and at least two second wires. Multiple connection wires extend along a second direction, and the second direction is multiple Type 1 This is the direction in which the anodes are arranged in rows. In the wiring group, the first wiring is connected to correspond to at least two first anodes in the first type anode row, and the second wiring is connected to correspond to one second anode or one third anode in the first type anode row.

[0017] In some other embodiments, in a wiring group, the first wiring is connected to correspond to at least two first anodes in a first type anode array. At least two second wirings in the wiring group comprise at least one first sub-wiring and at least one second sub-wiring. The first sub-wiring is connected to correspond to one second anode or one third anode in a first type anode array. The second sub-wiring is electrically connected to one second anode or one third anode in another first type anode array.

[0018] In some embodiments, the orthographic projections on the base substrate of multiple Type 1 pixel driving circuits are located on one or both sides of the orthographic projections on the base substrate of multiple Type 1 anodes, along the direction of extension of multiple connection wirings.

[0019] In some embodiments, the second conductive layer further comprises a plurality of second connectors. The second connectors are electrically connected to the first anode. Connecting wiring located in the second conductive layer is electrically connected to the first anode via the second connectors. The first conductive layer further comprises a plurality of first connectors. The first connectors are electrically connected to the second connectors. Connecting wiring located in the first conductive layer is electrically connected to the first anode via the connected first and second connectors.

[0020] In some embodiments, multiple first and third wirings are located in the second conductive layer. Of the connected first and third wirings, the third wiring is connected to two adjacent first anodes by being connected to two adjacent second connectors. The first wiring is connected to one of the two adjacent second connectors. Of the two adjacent second connectors, the one connected to the first wiring has a closer distance between the orthogonal projection on the base substrate and the orthogonal projection on the base substrate of the first pixel driver circuit electrically connected to the two adjacent first anodes, compared to the other.

[0021] In some other embodiments, multiple first and multiple third wirings are located in a first conductive layer. Of the connected first and third wirings, the third wiring is connected to two adjacent first anodes by being connected to two adjacent first connection points. The first wiring is connected to one of the two adjacent first connection points. Of the two adjacent first connection points, the one connected to the first wiring has a closer distance between the orthogonal projection on the base substrate and the orthogonal projection on the base substrate of the first type pixel driver circuit electrically connected to the two adjacent first anodes, compared to the other.

[0022] In some embodiments, the drive circuit layer further comprises a plurality of Type 2 pixel drive circuits arranged in an array in a first display area. The plurality of Type 1 pixel drive circuits are provided in the array gap of the plurality of Type 2 pixel drive circuits. The anode layer further comprises a plurality of Type 2 anodes located in the first display area. The Type 2 anodes are electrically connected to the Type 2 pixel drive circuits.

[0023] In another embodiment, several embodiments of the present disclosure further provide a display device. The display device comprises a display panel according to any of the above embodiments and at least one sensor. The sensor is provided on the non-display side of the display panel, and the orthographic projection of the sensor on the display panel is located in a second display area.

[0024] In another aspect, several embodiments of the present disclosure further provide a method for manufacturing a display panel. The display panel includes a display area, the display area including a first display area and a second display area. The method for manufacturing the display panel includes providing a base substrate; forming a drive circuit layer on the base substrate, the drive circuit layer comprising a plurality of first type pixel drive circuits, the plurality of first type pixel drive circuits being provided in the first display area; forming a connection layer, the connection layer comprising a plurality of connection wirings, the plurality of connection wirings comprising a first wiring; and forming an anode layer, the anode layer comprising a plurality of first type anodes located in the second display area, the plurality of first type anodes comprising a plurality of first anodes, a plurality of second anodes, and a plurality of third anodes, the minimum two of the first anodes being electrically connected to one first type pixel drive circuit via a first wiring, the second anodes being electrically connected to one first type pixel drive circuit via a second wiring, and the third anodes being electrically connected to one first type pixel drive circuit via a second wiring.

[0025] In some embodiments, the connection layer comprises a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, arranged in order on the side away from the base substrate of the drive circuit layer. Forming the connection layer on the side away from the base substrate of the drive circuit layer includes: forming a first conductive material layer on the side away from the base substrate of the drive circuit layer and patterning the first conductive material layer with a first mask to form a first conductive layer having a pattern; forming a first insulating material layer on the side of the first conductive layer away from the base substrate and patterning the first insulating material layer with a second mask to form a first insulating layer having a pattern; forming a second conductive material layer on the side of the first insulating layer away from the base substrate and patterning the second conductive material layer with a third mask to form a second conductive layer having a pattern; and forming a second insulating material layer on the side of the second conductive layer away from the base substrate and patterning the second insulating material layer with a fourth mask to form a second insulating layer having a pattern. The pattern of the first conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, the pattern of the second conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, the pattern of the first insulating layer comprises a first via hole, and the pattern of the second insulating layer comprises a second via hole.

Brief Description of the Drawings

[0026] In the following, in order to more clearly explain the technical solutions according to the present disclosure, the drawings used in some embodiments of the present disclosure will be briefly described. However, it is clear that the drawings in the following description are only a part of some embodiments of the present disclosure. Those skilled in the art can also obtain other drawings based on these drawings. Further, the drawings in the following description can be regarded as schematic diagrams, and do not limit the actual dimensions of the products according to the embodiments of the present disclosure, the actual flow of the method, the actual timing of signals, etc.

[0027] [Figure 1] It is a structural diagram of a display device provided by some embodiments.

[0028] [Figure 2] It is a structural diagram of a display panel provided by some embodiments.

[0029] [Figure 3] It is a cross-sectional view of a display panel provided by the related art.

[0030] [Figure 4] It is a diagram showing a connection method between a pixel driving circuit and a light emitting element provided by the related art.

[0031] [Figure 5] It is a cross-sectional view of a display panel provided by some embodiments.

[0032] [Figure 6] It is another diagram showing a connection method between a pixel driving circuit and a light emitting element provided by some embodiments.

[0033] [Figure 7A] It is a cross-sectional view of a connection layer provided by some embodiments.

[0034] [Figure 7B] This is a cross-sectional view of another connecting layer provided by several embodiments.

[0035] [Figure 8A] This figure shows a connection method between the connecting wiring and the anode layer provided by several embodiments. [Figure 8B] This figure shows a connection method between the connecting wiring and the anode layer provided by several embodiments. [Figure 8C] This figure shows a connection method between the connecting wiring and the anode layer provided by several embodiments.

[0036] [Figure 9A] Another diagram shows a connection method between the connecting wiring and the anode layer, as provided by several embodiments. [Figure 9B] Another diagram shows a connection method between the connecting wiring and the anode layer, as provided by several embodiments. [Figure 9C] Another diagram shows a connection method between the connecting wiring and the anode layer, as provided by several embodiments.

[0037] [Figure 10A] This is another diagram showing the connection method between the connecting wiring and the anode layer, as provided by several embodiments. [Figure 10B] This is another diagram showing the connection method between the connecting wiring and the anode layer, as provided by several embodiments. [Figure 10C] This is another diagram showing the connection method between the connecting wiring and the anode layer, as provided by several embodiments.

[0038] [Figure 11] This figure shows a connection method between an anode layer and a wiring group provided by several embodiments.

[0039] [Figure 12] This is another diagram showing a connection method between a pixel driving circuit and a light-emitting element, provided by several embodiments.

[0040] [Figure 13] This is another diagram showing a connection method between the anode layer and the wiring group provided by several embodiments.

[0041] [Figure 14] This is another diagram showing the connection method between the pixel driving circuit and the light-emitting element, as provided by several embodiments.

[0042] [Figure 15] This is another diagram showing the connection method between the pixel driving circuit and the light-emitting element, as provided by several embodiments.

[0043] [Figure 16] This is a cross-sectional view of a display device provided by several embodiments.

[0044] [Figure 17] This is a flowchart of a method for manufacturing a display panel, as provided by several embodiments.

[0045] [Figure 18A] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments. [Figure 18B] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments. [Figure 18C] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments. [Figure 18D] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments. [Figure 18E] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments. [Figure 18F] This is a diagram illustrating the manufacturing steps of a display panel provided by several embodiments.

[0046] [Figure 19] This is a flowchart of a method for manufacturing a connecting layer, as provided by several embodiments.

[0047] [Figure 20A] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20B] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20C] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20D] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20E] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20F] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20G] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20H] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20I] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20J] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20K] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20L] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20M] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20N] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20O] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Figure 20P] This is a step diagram illustrating the manufacturing process of a connecting layer provided by several embodiments. [Modes for carrying out the invention]

[0048] The following describes, with reference to the drawings, some technical examples of embodiments of this disclosure clearly and completely, although it is clear that the embodiments described are only a part of the embodiments of this disclosure and not all of them. All other embodiments obtained by those skilled in the art based on some embodiments of this disclosure are all within the scope of protection of this disclosure.

[0049] Unless otherwise required by context, throughout this specification and the claims, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted as having an open, inclusive meaning, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that a particular feature, structure, material, or property related to that embodiment or example is included in at least one embodiment or example of this disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any particular feature, structure, material, or property described may be included in any one or more embodiments or examples in any suitable manner.

[0050] In the following, the terms “first” and “second” are merely for illustrative purposes and should not be understood as indicating or implying relative importance or the quantity of the indicated technical features. Accordingly, features defined as “first” and “second” may explicitly or implicitly include one or more such features. In the description of the embodiments of this disclosure, unless otherwise specified, “multiple” means two or more.

[0051] When describing some embodiments, the terms “coupled” and “connected,” and expressions derived therefrom, may be used. For example, when describing some embodiments, the term “connected” may be used to indicate that two or more components have direct physical or electrical contact with one another. Or, when describing some embodiments, the term “coupled” may be used to indicate that two or more components have direct physical or electrical contact with one another. However, the terms “coupled” or “communicatively coupled” can also mean that two or more components do not have direct contact with one another but still cooperate or interact with one another. The embodiments disclosed herein are not necessarily limited to those disclosed herein.

[0052] Furthermore, the use of "based on" implies that a process, step, calculation, or other action based on one or more stated conditions or values ​​may, in fact, be based on additional conditions or exceed the stated values, thus being open and inclusive.

[0053] As used herein, “parallel,” “perpendicular,” and “equal” include the conditions described and conditions that approximate the conditions described, the range of these approximate conditions being within an acceptable deviation range, the acceptable deviation range being determined in consideration of the errors (i.e., limitations of the measuring system) associated with the measurement and the measurement of a particular quantity under consideration by a person skilled in the art. For example, “parallel” includes true parallel and approximate parallel, of which the acceptable deviation range for approximate parallel is, for example, a deviation of 5° or less; “perpendicular” includes true perpendicular and approximate perpendicular, of which the acceptable deviation range for approximate perpendicular may be, for example, a deviation of 5° or less; “equal” includes true equal and approximate equal, within the acceptable deviation range for approximate equal, for example, the difference between two equals may be less than 5% of either or equal.

[0054] When it is mentioned that a layer or component is located on another layer or substrate, it should be understood that this means the layer or component is directly on the other layer or substrate, or that there may be an intermediate layer between the layer or component and the other layer or substrate.

[0055] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thickness of layers and areas is enlarged for clarity. The exemplary embodiments of this disclosure should be interpreted as including deviations in shape due to manufacturing, etc., and are not limited to the shapes of the areas illustrated herein. For example, an etching area shown as a rectangle typically has curved characteristics. Accordingly, the areas shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of areas in equipment, nor are they intended to limit the scope of the exemplary embodiments.

[0056] As shown in Figure 1, the display device 1000 may further include electrical components such as sensors 200 in addition to the display panel 100, such as optical sensors. Taking the example that the display device 1000 is a mobile phone, the display device 1000 may include optical sensors such as a front camera, proximity light sensor, and 3D sensing module. These optical components need to receive light rays from the display surface side of the display device 1000 in order to perform their corresponding functions. In the display device 1000, the optical sensors are usually mounted on the non-display side of the display panel 100, and the photosensitive side of the optical sensors faces the display panel 100.

[0057] In some embodiments of this disclosure, a display panel 100 is provided, which may be, for example, an OLED (Organic Light-Emitting Diode) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Quantum Dot Light-Emitting Diode (QLED) display panel, a Mini Light-Emitting Diode (Mini LED) display panel, or a Micro Light-Emitting Diode (Micro LED) display panel. In the following description, the display panel will be described using an OLED display panel as an example. As shown in Figure 2, the display panel 100 comprises a display area 10a and a peripheral area 10b. The peripheral area 10b is located on one side of the display area 10a or surrounds the display area 10a. The display area 10a is provided with a plurality of pixels P, each pixel P comprising a red subpixel R, a blue subpixel B, and a green subpixel G. Each subpixel is equipped with a light-emitting element and a pixel driving circuit that controls the emission of light from the light-emitting element. The pixel driving circuit adjusts the brightness (grayscale) of subpixels of different colors, enabling the display of multiple colors through color combinations and superpositions, thereby realizing full-color display on the display panel 100.

[0058] As shown in Figure 3, the display panel 100 comprises a base substrate 10, a drive circuit layer 20, a connection layer 30, a light-emitting element layer 40, and a packaging layer 50. The drive circuit layer 20 is provided on the base substrate 10 and comprises a plurality of pixel drive circuits 21. The light-emitting element layer 40 comprises a plurality of light-emitting elements 41 such as OLEDs. Each light-emitting element 41 is an anode 43a Light-emitting layer 45a and cathode 46a Each pixel driving circuit 21 is electrically connected to the light-emitting element 41. Specifically, the pixel driving circuit 21 is connected to the anode of the light-emitting element 41. 43aIt is electrically connected to and controls the light emission of the light-emitting element 41. The packaging layer 50 covers the side of the light-emitting element layer 40 away from the base substrate 10, realizing packaging for the display panel 100.

[0059] In some embodiments, As shown in Figure 3, The drive circuit layer 20 is provided on one side of the base substrate 10. The drive circuit layer 20 comprises a semiconductor layer 22, a gate insulating layer 23, a gate layer 24, an interlayer insulating layer 25, a source-drain metal layer 26, and a planarization layer 27, which are sequentially stacked on the base substrate 10. Multiple pixel drive circuits 21 in the drive circuit layer 20 are arranged in an array, and each pixel drive circuit 21 comprises multiple thin-film transistors TFTs. The connection layer 30 is provided on the side of the drive circuit layer 20 away from the base substrate 10. The connection layer 30 comprises at least one conductive layer and at least one insulating layer, and one insulating layer is provided on the side of each conductive layer away from the base substrate 10. The connection layer 30 comprises multiple connection wirings 31, and the drive circuit layer 20 achieves electrical connection with the light-emitting element layer 40 via the connection layer 30.

[0060] The light-emitting element layer 40 is provided on the side of the connecting layer 30 away from the base substrate 10. The light-emitting element layer 40 comprises a pixel definition layer 44, an anode layer 43, an emissive film layer 45, and a cathode layer 46. The anode layer 43 comprises a plurality of anodes 43a, the emissive film layer 45 comprises a plurality of emissive layers 45a, the pixel definition layer 44 comprises a plurality of openings, each opening exposing one anode 43a, each emissive layer 45a is located within one opening and in contact with the anode 43a, and the portion of the cathode layer 46 located within the opening becomes a cathode 46a. Thus, the sequentially stacked anodes 43a, emissive layers 45a, and cathodes 46a constitute a light-emitting element 41. The plurality of light-emitting elements 41 in the light-emitting element layer 40 are arranged in an array, that is, the plurality of anodes 43a are arranged in an array.

[0061] As shown in Figures 2 and 3, in the full-screen display panel 100, the display area 10a is divided into a first display area 11b and a second display area 11a. The second display area 11a may be located inside the first display area 11b, that is, the first display area 11b surrounds the second display area 11a, for example, the second display area 11a is a circular or rectangular area. In some embodiments, the base substrate 10 and the drive circuit layer 20 have high light transmittance in the portion located in the second display area 11a, and exemplary, the base substrate 10 uses a transparent glass substrate to provide high transparency. The drive circuit layer 20 does not have a circuit structure in the second display area 11a in order to maintain sufficient transparency of the drive circuit layer. A sensor 200 is located on the side of the base substrate 10 away from the drive circuit layer. (As shown in Figure 1) A sensor is provided, for example, an optical sensor such as a camera, proximity light sensor, or 3D sensing module, and the projection of the sensor 200 onto the base substrate 10 is located in the second display area 11a. The photosensitive surface of the optical sensor faces the display surface side of the display panel 100 and is used to receive ambient light from the display surface side of the display panel 100. Exemplarily, the light-emitting element layer 40 and the packaging layer 50 have a transparent structure at least in the second display area 11a. For example, the anode layer of the light-emitting element layer 40 43 Because it uses transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO), the second display area 11a has high light transmittance, making it suitable for placing equipment that requires high transmittance, such as cameras. As a result, the display panel 100 can achieve full-screen display in the display area 10a, and an optical sensor can be provided in the second display area 11a. The optical sensor can receive external light rays through the light-emitting element layer 40 and the packaging layer 50, and realize the corresponding function.

[0062] As shown in Figure 3, among the multiple anodes 43a provided in the anode layer 43, the anode 43a located in the second display area 11a is called the first type anode 43a1, and the anode 43a located in the first display area 11b is called the second type anode 43a2. That is, anode layer 43The device comprises a plurality of first-type anodes 43a1 and a plurality of second-type anodes 43a2. Similarly, among the plurality of pixel driving circuits 21 provided in the driving circuit layer 20, the pixel driving circuit 21 electrically connected to the first-type anode 43a1 is called the first-type pixel driving circuit 211, and the pixel driving circuit 21 electrically connected to the second-type anode 43a2 is called the second-type pixel driving circuit 212. Both the first-type pixel driving circuit 211 and the second-type pixel driving circuit 212 are provided in the first display area 11b. For example, the driving circuit layer 20 further comprises a plurality of second-type pixel driving circuits 212 arranged in an array in the first display area 11b, and the plurality of first-type pixel driving circuits 211 are provided within the array gap of the plurality of second-type pixel driving circuits 212. For example, multiple Type 1 pixel driving circuits 211 are located near the second display area 11a in the first display area 11b, and multiple Type 1 pixel driving circuits 211 are located around the second display area 11a.

[0063] In some embodiments, one first-type pixel driver circuit 211 is electrically connected to one first-type anode 43a1, and one second-type pixel driver circuit 212 is electrically connected to one second-type anode 43a2. In some embodiments, as shown in Figure 3, the electrically connected second-type pixel driver circuit 212 and second-type anode 43a2 have an orthographic overlap on the base substrate 10, and the second-type pixel driver circuit 212 and second-type anode 43a2 are connected by via holes penetrating the insulating layer in the planarization layer 27 and the connecting layer 30. In some other examples, the first type pixel driving circuit 211 is located in the first display area 11b, and the first type anode 43a1 is located in the second display area 11a. Since the electrically connected first type pixel driving circuit 211 and the first type anode 43a1 do not have overlapping orthographic projections on the base substrate 10 and there is a certain distance between them, the first type pixel driving circuit 211 and the first type anode 43a1 are electrically connected via connection wiring 31 in the connection layer 30. Each connection wiring 31 communicates the first display area 11b and the second display area 11a, thereby transmitting the current signal from the first type pixel driving circuit 211 located in the first display area 11b to the first type anode 43a1 located in the second display area 11a, and controlling the light emission of the light-emitting element 41 where the first type anode 43a1 is located. This satisfies the requirements for normal display of the full-screen display panel 100 and the requirement for high transmittance of optical sensors such as cameras located on the non-display side of the display panel 100.

[0064] As shown in Figures 3 and 4, taking the display device 1000 as a mobile phone as an example, in the display panel 100, the second display area 11a is a circular area, the diameter of the second display area 11a is generally about 2.5 mm, and an under-screen camera is provided in this area. Taking the mobile phone display panel 100 as an example, the light-emitting elements of the second display area 11a are arranged in 40 rows × 80 columns. In related technologies, each first type anode 43a1 is electrically connected to one first type pixel driving circuit 211 via one connecting wire 31, and the connecting wire 31 transmits the driving current signal output by the first type pixel driving circuit 211, that is, the number of connecting wires 31 is the same as the number of first type anodes 43a1. As a result, when there are many connecting wires 31, it is necessary to insulate the connecting wires 31 from each other, so it is necessary to distribute multiple connecting wires 31 across multiple conductive layers.

[0065] For example, in the connection method shown in Figure 4, if the first type pixel driving circuit 211 is provided in the first display area 11b and is located on both sides along the first direction (row direction in which multiple first type anodes are arranged in an array) of the second display area 11a, then taking the row with the largest number of light-emitting elements 41 (passing through the diameter of the circular area) as an example, this row has 80 light-emitting elements 41, and in order to satisfy the control requirements, 80 connection wires 31 need to be arranged in the lateral direction. Considering the width and insulation requirements of the connection wires 31, and the large number of connection wires 31, as shown in Figure 3, the 80 connection wires 31 need to be evenly distributed within the three conductive layers. The number of connection wires 31 distributed in each conductive layer is such that each conductive layer has 26 to 30 connection wires 31 that are parallel to each other, and insulating layers need to be provided between each conductive layer and between the conductive layers and the anode layer, for a total of three insulating layers. In other words, the full-screen display panel requires the addition of three conductive layers and three insulating layers, and many of these conductive and insulating layers can reduce the light transmittance of the second display area 11a. Furthermore, manufacturing the three conductive layers and three insulating layers requires the addition of six masks to the manufacturing process, which complicates the process, reduces production efficiency, increases costs, and makes it impossible to meet production capacity needs.

[0066] Based on this, as shown in Figures 5 and 6, Figure 5 shows a cross-sectional view of the display panel 100, and Figure 6 shows the 2 Display area 11 a Multiple anodes 43a in, and 1 Display area 11 b The diagram shows a plurality of first-type pixel driving circuits 211 and second-type pixel driving circuits 212. Some embodiments of the present disclosure provide a display panel 100 comprising a base substrate 10, a driving circuit layer 20, a connection layer 30, a light-emitting element layer 40, and a packaging layer 50. The structure and location of each film layer are described above and will not be repeated. In the light-emitting element layer 40, the anode layer 43 comprises a plurality of anodes 43a, which comprises a plurality of first anodes 431, a plurality of second anodes 432, and a plurality of third anodes 433. The first anodes 431, second anodes 432, and third anodes 433 each correspond to subpixels of different colors. Of the plurality of first anodes 431, a plurality of second anodes 432, and a plurality of third anodes 433, the anodes 43a located in the second display area 11a belong to the first-type anodes 43a1. Type 2 anode located in the first display area 11b 43a2 The structure of the first type anode 43a1 of the second display area 11a and the electrical connection method between the first type anode 43a1 and the first type pixel driving circuit 211 will be described below.

[0067] As shown in Figures 5 and 6, the multiple connection wires 31 in the connection layer 30 comprise multiple first wires 311. The multiple first type anodes 43a1 comprise multiple first anodes 431, and at least two first anodes 431 are electrically connected to one first type pixel driving circuit 211 via the first wires 311. For example, two adjacent first anodes 431 are electrically connected to one first type pixel driving circuit 211 via one first wire 311. As shown in Figure 5, if we take the first and second first type anodes 43a1 from the left among the first type anodes 43a1 located in the second display area 11a as first anodes 431, it can be seen that these two first anodes 431 are electrically connected to one first type pixel driving circuit 211 via one first wire 311.

[0068] In some embodiments, as shown in Figure 6, a plurality of first-type anodes 43a1 further comprises a plurality of second anodes 432 and a plurality of third anodes 433. The connecting wiring 31 further comprises a plurality of second wirings 312. The second anodes 432 are electrically connected to one first-type pixel driver circuit 211 via the second wirings 312. The third anodes 433 are electrically connected to one first-type pixel driver circuit 211 via the second wirings 312. A second-type pixel driver circuit 212 is also present between the two first-type pixel driver circuits 211.

[0069] In the display panel 100 described above, by providing multiple first wirings 311, the two first anodes 431 are electrically connected to one first-type pixel driving circuit 211 via the first wirings 311, and the one first-type pixel driving circuit 211 controls the two first anodes 431. That is, one first-type pixel driving circuit 211 drives the two light-emitting elements 41 to emit light, and the second anode 432 and the third anode 433 are electrically connected to one first-type pixel driving circuit 211 via the second wirings 312, thereby ensuring the display effect and reducing the number of connecting wirings 31, and correspondingly reducing the number of conductive and insulating layers in the connecting layer 30. For example, if the area of ​​the second display area 11a is constant, that is, if the number of anodes 43a in the second display area 11a is constant, the number of conductive layers and insulating layers in the connecting layer 30 can be reduced from three conductive layers and three insulating layers in related technologies to two conductive layers and two insulating layers by reducing the number of first wirings 311. This reduces the number of masks required to manufacture the conductive and insulating layers in the process of manufacturing the display panel 100, for example from six masks in related technologies to four masks, thereby reducing costs and process complexity, as well as improving the light transmittance of the second display area 11a by reducing the number of conductive and insulating layers, which is advantageous for the normal operation of the optical sensor in this area.

[0070] In some embodiments, as shown in Figure 5, the display panel 100 comprises a base substrate 10, a drive circuit layer 20, a connection layer 30, a light-emitting element layer 40, and a packaging layer 50. The connection layer 30 is located on the side of the drive circuit layer 20 away from the base substrate 10. The connection layer 30 comprises at least one conductive layer and at least one insulating layer. For example, as shown in Figure 7A, the connection layer 30 comprises a first conductive layer 32 and a first insulating layer 33, or as shown in Figure 7B, the connection layer 30 comprises a first conductive layer 32, a first insulating layer 33, a second conductive layer 34, and a second insulating layer 35. The first conductive layer 32 comprises a plurality of connection wires 31, or the first conductive layer 32 and the second conductive layer 34 comprise a plurality of connection wires 31, and the connection wires 31 comprise a first wire 311 and a second wire 312.

[0071] The above example merely illustrates one possible positional relationship of the connection layer 30, and does not particularly limit the positional relationship between the upper and lower layers of the connection layer 30 and the drive circuit layer 20. In some embodiments, the connection layer 30 may also be located in the drive circuit layer, that is, a certain layer in the drive circuit layer may be multiplexed as a connection layer to realize an electrical connection between the anode and the corresponding pixel drive circuit.

[0072] The light-emitting element layer 40 is located on the side of the connection layer 30 away from the base substrate 10. The light-emitting element layer 40 comprises a green subpixel light-emitting element 41, a red subpixel light-emitting element 41, and a blue subpixel light-emitting element 41. The anodes 43a of the green subpixel light-emitting element 41, the red subpixel light-emitting element 41, and the blue subpixel light-emitting element 41 are provided in the anode layer 43. The anode 43a located in the first display area 11b is a type 2 anode 43a2, and the anode 43a located in the second display area 11a is a type 1 anode 43a1. Each type 2 anode 43a2 is connected to one type 2 pixel driving circuit. 212It is electrically connected to the first anode 43a1, for example, the anode 43a of the green subpixel light-emitting element 41 is the first anode 431, the anode 43a of the red subpixel light-emitting element 41 is the second anode 432, and the anode 43a of the blue subpixel light-emitting element 41 is the third anode 433. Alternatively, the anode 43a of the green subpixel light-emitting element 41 is the first anode 431, the anode 43a of the blue subpixel light-emitting element 41 is the second anode 432, and the anode 43a of the red subpixel light-emitting element 41 is the third anode 433. Two first anodes 431 are electrically connected to one type first pixel driving circuit 211 via a first wiring 311, a second anode 432 is electrically connected to one type first pixel driving circuit 211 via a second wiring 312, and a third anode 433 is electrically connected to one type first pixel driving circuit 211 via a second wiring 312. That is, one type first pixel driving circuit 211 drives the light-emitting elements of two green subpixels to emit light, and one type first pixel driving circuit 211 drives the light-emitting element of one red subpixel or one blue subpixel to emit light.

[0073] In some embodiments, as shown in Figure 7B, the connecting layer 30 comprises a first conductive layer 32, a first insulating layer 33, a second conductive layer 34, and a second insulating layer 35. The first conductive layer 32 is provided on the side of the drive circuit layer 20 away from the base substrate 10, the first insulating layer 33 is provided on the side of the first conductive layer 32 away from the base substrate 10, the second conductive layer 34 is provided on the side of the first insulating layer 33 away from the base substrate 10, and the second insulating layer 35 is provided on the side of the second conductive layer 34 away from the base substrate 10. The first conductive layer 32 comprises a plurality of first wirings 311 and / or a plurality of second wirings 312, the second conductive layer 34 comprises a plurality of first wirings 311 and / or a plurality of second wirings 312, the first insulating layer 33 has a first via hole 331, the second insulating layer 35 has a second via hole 351, the first conductive layer 32 is electrically connected to the second conductive layer 34 via the first via hole 331, and the second conductive layer 34 is electrically connected to the anode layer 43 via the second via hole 351.

[0074] For example, the display area 10a is provided with a first conductive layer 32, a first insulating layer 33, a second conductive layer 34, and a second insulating layer 35. Multiple connection wires 31 are provided on the first conductive layer 32 and the second conductive layer, and each conductive layer is isolated from other layers by an insulating layer. In the second display area 11a, the optical sensor is provided on the side of the connection layer 30 away from the light-emitting element layer 40. The first conductive layer 32, the first insulating layer 33, the second conductive layer 34, and the second insulating layer 35 are all transparent, and the requirements for the light transmittance of the optical sensor can be met.

[0075] In some other embodiments, as shown in Figure 7A, the connection layer 30 comprises a first conductive layer 32 and a first insulating layer 33. The first conductive layer 32 is provided on the side of the drive circuit layer 20 away from the base substrate 10. The first insulating layer 33 is provided on the side of the first conductive layer 32 away from the base substrate 10. The first conductive layer 32 has a plurality of connection wires 31, and the first insulating layer 33 has a first via hole 331, and the first conductive layer 32 is electrically connected to the anode layer 43 via the first via hole 331.

[0076] For example, a first conductive layer 32 is provided in the display area 10a, a plurality of connection wires 31 are provided in the first conductive layer 32, and a first insulating layer 33 is provided on the side of the first conductive layer 32 away from the base substrate 10, and the first insulating layer 33 isolates the first conductive layer 32 from the anode layer. In the second display area 11a, the optical sensor is provided on the side of the connection layer 30 away from the light-emitting element layer 40, and the first conductive layer 32 and the first insulating layer 33 have a transparent structure, which can satisfy the light transmittance requirements of the optical sensor.

[0077] In some embodiments, as shown in Figure 11, there are multiple Type 1 anodes. 43a1 The arrangement scheme is multiple Type 1 anodes 43a1 These are arranged in multiple rows, and multiple Type 1 anodes are arranged in one row. 43a1This is referred to as the first type anode row 42, and at least one first type anode row 42 comprises at least two first anodes 431, at least one second anode 432, and at least one third anode 433 arranged in a row. At least two first anodes 431 in at least one first type anode row 42 are electrically connected to one first wiring 311.

[0078] In some examples, as shown in Figures 8A, 9A, 10A, and 11, the first type anode row 42 is arranged periodically in the order of second anode 432, first anode 431, third anode 433, and first anode 431.

[0079] Exemplary, multiple Type 1 anodes are arranged in multiple rows, and each row of Type 1 anodes 42 comprises a first sub-row 421 and a second sub-row 422 arranged in parallel. The first sub-row 421 is provided with alternating second anodes 432 and third anodes 433, and the second sub-row 422 is provided sequentially by multiple first anodes 431. The number of first anodes 431 in the second sub-row 422 is, 1 Sub-row 421 The number of second anodes 432 and third anodes 433 is equal to the sum of the number of second anodes 432 and third anodes 433, and the first anode 431 is located on the central axis between the adjacent second anodes 432 and third anodes 433. The first anode 431 belongs to the anode of the light-emitting element of the green subpixel, the second anode 432 belongs to the light-emitting element of the blue subpixel, and the third anode 433 belongs to the light-emitting element of the red subpixel, or the first anode 431 belongs to the anode of the light-emitting element of the green subpixel, the second anode 432 belongs to the light-emitting element of the red subpixel, and the third anode 433 belongs to the light-emitting element of the blue subpixel, that is, one first wiring 311 transmits a signal to the light-emitting elements of two green subpixels.

[0080] As shown in Figure 11, multiple Type 1 anodes are arranged in multiple rows, and multiple connecting wires 31 are arranged in multiple wiring groups Ls, each wiring group Ls comprising at least one first wire 311 and at least two second wires 312. The multiple connecting wires 31 extend along a first direction, which is the row direction in which the multiple anodes are arranged. The connection relationship between the wiring groups Ls and the Type 1 anode rows 42 will be described below.

[0081] In some examples, as shown in Figure 8A, in a wiring group Ls, one first wiring 311 is connected to two first anodes 431 in one first type anode row 42. At least two second wirings 312 in the wiring group Ls include at least one first sub-wiring 3121 and at least one second sub-wiring 3122. One first sub-wiring 3121 is connected to one second anode 432 or one third anode 423 in the first type anode row 42. One second sub-wiring 3122 is electrically connected to one second anode 432 or one third anode 433 in another first type anode row 42 adjacent to the first type anode row 42.

[0082] In some other examples, as shown in Figure 9A, in a wiring group Ls, one first wire 311 is connected to two first anodes 431 in one first type anode row 42, and one second wire 312 is connected to one second anode 432 or one third anode 423 in the same first type anode row 42. At least one first type anode row 42 is electrically connected to multiple first type pixel driving circuits via one wiring group Ls, and the wiring group Ls comprises multiple first wires 311 and multiple second wires 312.

[0083] Furthermore, in some examples, as shown in Figure 10A, in the wiring group Ls, one first wire 311 is connected to two first anodes 431 in one first type anode row 42, and one second wire 312 is connected to one second anode 432 or one third anode 423 in another first type anode row 42. For example, another first type anode row 42 may be adjacent to the above one first type anode row 42. That is, one wiring group Ls connects two first type anode rows 42. For one first type anode row 42, the first anode 431 in that first type anode row 42 is connected to the first wire 311 in one wiring group Ls, and the second anode 432 or third anode 433 is connected to the second wire in another wiring group Ls. 312 At least one Type 1 anode row 42 is electrically connected to multiple Type 1 pixel driver circuits via two wiring groups Ls. Exemplarily, one wiring group Ls is located between two adjacent Type 1 anode rows.

[0084] The above describes only some examples of connection relationships between the wiring group Ls and the first anode row 42. Other examples exist, provided that one first wiring 311 is connected to two first anodes 431, and one second wiring 312 is connected to one second anode 432 or one third anode 433. That is, one first wiring 311 can transmit signals to two green subpixel light-emitting elements, and one second wiring 312 can transmit signals to one blue subpixel light-emitting element or one red subpixel light-emitting element. The above examples do not limit the present disclosure to connection methods between connecting wiring and anodes.

[0085] In some other embodiments, as shown in Figures 12 and 13, there are multiple Type 1 anodes. 43a1 Another arrangement scheme involves multiple Type 1 anodes. 43a1 These are arranged in multiple columns, followed by multiple Type 1 anodes arranged in a single column. 43a1This is referred to as the first type anode array 42', and at least one first type anode array 42' comprises at least two first anodes 431, at least one second anode 432, and at least one third anode 433 arranged in a row. At least two first anodes 431 in the first type anode array 42' are electrically connected to one first wiring 311.

[0086] In some examples, the first type anode array 42' is arranged periodically in the order of second anode 432, first anode 431, third anode 433, and first anode 431.

[0087] Exemplary, multiple Type 1 anodes are arranged in multiple rows, and each row of Type 1 anodes 42' comprises a parallel first sub-row 421' and a second sub-row 422'. The first sub-row 421' is provided with alternating second anodes 432 and third anodes 433, and the second sub-row 422' is provided sequentially by multiple first anodes 431. The number of first anodes 431 in the second sub-row 422' is equal to the sum of the number of second anodes 432 and third anodes 433 in the first sub-row 421', and each first anode 431 is provided on the central axis between it and adjacent second anodes and third anodes 433. The first anode 431 belongs to the anode of the light-emitting element of the green subpixel, the second anode 432 belongs to the anode of the light-emitting element of the blue subpixel, and the third anode 433 belongs to the anode of the light-emitting element of the red subpixel, or the first anode 431 belongs to the anode of the light-emitting element of the green subpixel, the second anode 432 belongs to the anode of the light-emitting element of the red subpixel, and the third anode 433 belongs to the anode of the light-emitting element of the blue subpixel, that is, one first wiring 311 transmits a signal to the light-emitting elements of two green subpixels.

[0088] As shown in Figure 13, multiple Type 1 anodes 43a1 The multiple connection wires 31 are arranged in multiple rows, and the multiple connection wires 31 are arranged in multiple wiring groups Ls', each wiring group Ls' comprising at least one first wire 311 and at least two second wires 312. The multiple connection wires 31 extend along a second direction, and the second direction is a multiple anode 43a1This is the direction in which the arrays are arranged. Below, the connection relationship between the wiring group Ls' and the first type anode row will be explained, but you can also refer to the explanation of the connection relationship between the wiring group Ls and the first type anode row and the related diagrams.

[0089] In some examples, in the wiring group Ls', one first wiring 311 is connected to two first anodes 431 in one type first anode array 42', and one second wiring 312 is connected to one second anode 432 or one third anode 433 in the same type first anode array 42'. At least one type first anode array 42' is connected to a type first pixel driving circuit 21 via one wiring group Ls'. 1 They are electrically connected. One wiring group Ls' comprises a plurality of first wirings 311 and a plurality of second wirings 312. That is, one first wiring 311 transmits a signal to the light-emitting elements of two green subpixels, and one second wiring 312 transmits a signal to the light-emitting element of one blue subpixel or a red subpixel.

[0090] In some other examples, in wiring group Ls', one first wiring 311 is connected to two first anodes 431 in one type first anode row 42'. At least two second wirings 312 in wiring group Ls' comprise at least one first subwiring and at least one second subwiring. At least one first subwiring is connected to one second anode 432 or one third anode 433 in one type first anode row 42'. Each second subwiring is electrically connected to one second anode 432 or one third anode 433 in another type first anode row 42' adjacent to the first type first anode row 42'.

[0091] In some examples, within a wiring group Ls', one first wire 311 is connected to two first anodes 431 in one type first anode array 42', and one second wire 312 is connected to one second anode 432 or one third anode 433 in another type first anode array 42'. For example, another type first anode array 42' may be adjacent to the above one type first anode array 42'. That is, one wiring group Ls' connects two type first anode arrays 42'. For one type first anode array 42', the first anode 431 in that type first anode array 42' is connected to the first wire 311 in one wiring group Ls', and the second anode 432 or third anode 433 is connected to the second wire 312 in another wiring group Ls'. At least one Type 1 anode array 42' is electrically connected to multiple Type 1 pixel driver circuits via two wiring groups Ls'. Exemplarily, one wiring group Ls' is located between two adjacent Type 1 anode arrays 42'.

[0092] The above only describes some examples of connection relationships between the wiring group Ls' and the first type anode array 42'; other examples exist, such as a single first wiring 311 2 It is sufficient that one first anode 431 is connected, and one second wire 312 is connected to one second anode 432 or one third anode 433. The above examples do not limit the present disclosure to connection methods between connecting wires and anodes.

[0093] In some embodiments, as shown in Figures 6, 12, 14, and 15, the positions of the multiple Type 1 pixel driving circuits 21 in the first display area 11b are such that the orthographic projection of the multiple Type 1 pixel driving circuits 21 on the base substrate 10 is such that the multiple Type 1 anodes 43a1 It is provided so as to be located on one or both sides of the extension direction of the plurality of connection wirings 31 in the orthographic projection of the base substrate 10.

[0094] In some examples, as shown in Figure 6, multiple connection wires 31 extend along a first direction, and multiple first-type pixel driving circuits 211 are located on both sides of the second display area 11a, for example, on the left or right side. In some other examples, as shown in Figure 14, multiple connection wires 31 extend along a first direction, and multiple first-type pixel driving circuits 211 are located on one side of the second display area 11a, for example, on the left side.

[0095] In some examples, as shown in Figure 12, multiple connection wires 31 extend along the second direction, and multiple first-type pixel driving circuits 211 are located on both sides of the second display area 11a, for example, the upper and lower sides. In some other examples, as shown in Figure 15, multiple connection wires 31 extend along the second direction, and multiple first-type pixel driving circuits 211 are located on one side of the second display area 11a, for example, the upper side.

[0096] In some embodiments, the first conductive layer 32 comprises a plurality of first wirings 311 and / or a plurality of second wirings 312, and the second conductive layer 34 comprises a plurality of first wirings 311 and / or a plurality of second wirings 312. Hereinafter, with reference to Figures 8A to 10C, the distribution of the first wirings 311 and second wirings 312 in the first and second conductive layers 34 will be described using several connection relationships between the wiring group Ls and the first type anode row 42 as examples.

[0097] In some examples, multiple first wirings 311 provided in a wiring group Ls may be located in one conductive layer. Some of the multiple second wirings 312 provided in the wiring group Ls may be located in the same conductive layer, and other parts may be located in other conductive layers. As shown in Figures 6, 8A, 8B, and 8C, for the sake of clarity, the connecting wirings 31 located in different conductive layers in Figure 8A are each depicted in two separate drawings. Figure 8B is a connection diagram between a portion of the connecting wirings 31 located in the second conductive layer and the first type anode, and Figure 8C is a connection diagram between a portion of the connecting wirings 31 located in the first conductive layer and the first type anode. In one wiring group Ls, as shown in Figure 8B, all first wirings 311 are provided on the second conductive layer 34, a portion of the second wiring 312 is provided on the second conductive layer 34, and another portion of the second wiring 312 is provided on the first conductive layer, as shown in Figure 8C. The multiple connecting wires 31 provided in the wiring group Ls are evenly distributed across the two conductive layers, and by rationally arranging the positions of the connecting wires 31, problems such as short circuits and crosstalk caused by the spacing between adjacent connecting wires 31 being too small are avoided.

[0098] As an example, the arrangement of light-emitting elements in the second display area 11a is arranged in a 40x80 grid; that is, the first type anodes 43a1 located in the second display area 11a are arranged in a 40x80 grid. As shown in Figure 6, if the second display area 11a is a circular area, the one first type anode row 42 with the largest number of anodes 43a is a row that passes through the diameter of the circular area, and the number of first type anode rows 42 is 80, and the first type pixel driving circuits 211 located on both sides of the second display area 11a are electrically connected to the first type anodes 43a1 of that row via connecting wires 31. The 80 first-type anodes 43a1 in the first-type anode row 42 are divided into two equal parts. A first-type pixel driving circuit 211 located on one side of the second display area 11a is electrically connected to 40 first-type anodes 43a1 in that row, and a first-type pixel driving circuit 211 located on the other side of the second display area 11a is electrically connected to another 40 first-type anodes 43a1 in that row. In the following, we will use a first-type anode row 42 with the largest number of anodes 43a as an example and describe the connections between the first-type anodes 43a1 and the anodes 43a1. wiring I will now explain the specific connection method with 31.

[0099] The 40 first-type anodes 43a1 comprise 10 second-type anodes 432, 10 third-type anodes 433, and 20 first-type anodes 431, and are arranged periodically in the order of first-type anodes 431, second-type anodes 432, first-type anodes 431, and third-type anodes 433. The connection wiring electrically connected to the 40 first-type anodes 43a1 comprises 10 first-type wires 311 and 20 second-type wires 312.

[0100] The 10 first wires 311 and 5 second wires 312 are located in the second conductive layer, and each first wire 311 is connected to two first anodes 431, and all of the above 20 first anodes 431 and the first typeThis achieves the purpose of connecting to the pixel driving circuit 211. Five second wires 312 are located in the second conductive layer and are electrically connected to two second anodes 432 and three third anodes 433, or two third anodes 433 and three second anodes 432, respectively, with each second wire 312 electrically connected to one second anode or one third anode. The remaining 15 second wires 312 are located in the first conductive layer, with each second wire electrically connected to one of the remaining 15 second anodes 432 and third anodes 433, thereby achieving the purpose of uniformly distributing the connection wires across the first and second conductive layers.

[0101] The five second wires 312 located in the second conductive layer are electrically connected from one side of the first type anode row 42 with the largest number of anodes 43a, and the ten first wires 311 located in the second conductive layer are electrically connected from the other side of the first type anode row 42 with the largest number of anodes 43a. This avoids cross-short circuits between the first wires 311 and the second wires 312 on the same conductive layer.

[0102] In some other examples, all first wires 311 in a wiring group Ls are located in the same conductive layer, which may be, for example, the first conductive layer or the second conductive layer. All second wires 312 in a wiring group Ls are located in a different conductive layer, which may be, for example, the second conductive layer or the first conductive layer. As shown in Figures 9A, 9B, and 9C, for the sake of clarity, the connecting wires located in different conductive layers in Figure 9A are each drawn in two separate diagrams, Figure 9B is a connection diagram between a portion of the connecting wires 31 located in the second conductive layer among the multiple connecting wires 31 in Figure 9A and the first type anode, and Figure 9C is a connection diagram between a portion of the connecting wires 31 located in the first conductive layer among the multiple connecting wires 31 in Figure 9A and the first type anode. As shown in Figure 9B, all first wires 311 in a wiring group Ls are located in the second conductive layer 34, and as shown in Figure 9C, all second wires 312 in the same wiring group Ls are located in the first conductive layer 32.

[0103] In some cases, a portion of the first wiring 311 and a portion of the second wiring 312 in a wiring group Ls are both located in the same conductive layer, and another portion of the first wiring 311 and 2nd wiring Another portion of 312 is located in a different conductive layer. As shown in Figures 10A, 10B, and 10C, for the sake of clarity, the connecting wires located in different conductive layers in Figure 10A are each depicted in two separate drawings: Figure 10B is a connection diagram between a portion of the connecting wire 31 located in the second conductive layer and the first type anode, and Figure 10C is a connection diagram between a portion of the connecting wire 31 located in the first conductive layer and the first type anode. In one wiring group Ls, as shown in Figure 10B, a portion of the first wiring 311 and a portion of the second wiring 312 are located in the second conductive layer 34, and as shown in Figure 10C, another portion of the first wiring 311 and another portion of the second wiring 312 are located in the first conductive layer 32.

[0104] The above connection method distributes 30 connection wires 31 within two conductive layers, and a sufficient number of conductive layers can support these connection wires 31. Because the number of connection wires in each conductive layer is small, the spacing between adjacent connection wires 31 can be sufficiently large, which is advantageous for processing, makes problems such as short circuits in the connection wires less likely, and results in a high product yield.

[0105] Furthermore, as shown in Figures 8A and 10A, when the first wiring 311 and the second wiring 312 of the same wiring group Ls are located on the same conductive layer, the first wiring 311 and the second wiring 312 of the same wiring group Ls are connected to different rows of Type 1 anodes, and the first wiring 311 and the second wiring 312 intersect on the same layer, preventing them from interfering with each other.

[0106] In some embodiments, at least two first anodes 431 constitute a first anode group, and among adjacent first anode groups, one second anode 432, and one third anode 433, the length of the first wiring 311 electrically connected to the first anode group is smaller than the length of the second wiring 312 electrically connected to the second anode 432 and also smaller than the length of the second wiring 312 electrically connected to the third anode 433.

[0107] In some examples, one end of the first wiring 311 is electrically connected to a first anode 431 in one first type anode row 42, and the other end of the first wiring 311 is preferentially electrically connected to a first type pixel drive circuit 211 that is closer to the second display area 11a. One end of a portion of the second wiring 312 is electrically connected to a second anode 432 or a third anode 433 in the same first type anode row 42, and the other end of the second wiring 312 is connected to a first type pixel drive circuit 211. The first type pixel drive circuits 211 connected to the other end of all second wirings 312 are further from the second display area 11a than the first type pixel drive circuits 211 connected to the first wiring 311. Thus, among the adjacent first anode group, the second anode 432, and the third anode 433, the length of the first wiring 311 electrically connected to the first anode group is smaller than the length of the second wiring 312 electrically connected to the second anode 432, and also smaller than the length of the second wiring 312 electrically connected to the third anode 433.

[0108] One first-type pixel driving circuit 211 provides voltage signals to two first anodes 431. If the distance between the two first wirings 311 is too long, it becomes susceptible to resistor-capacitor interference, causing the light-emitting element of the connected green subpixel to not light up in low grayscale. Therefore, in the above embodiment, by preferentially electrically connecting the other end of the first wiring 311 to the first-type pixel driving circuit 211 closer to the second display area 11a, the length of each first wiring 311 can be shortened, reducing the interference intensity of the first wiring due to resistors and capacitors, and ensuring that the light-emitting elements of the green subpixels in each second display area 11a operate normally in low grayscale.

[0109] In some embodiments, as shown in Figures 8A, 9A, and 10A, the multiple connection wires 31 further comprise multiple third wires 313. The third wires 313 connect at least two first anodes 431, and the first wires 311 are connected to the third wires 313 and the first type pixel driving circuit, so that the two first anodes 431 are electrically connected to one first type pixel driving circuit, and the connected third wires 313 and first wires 311 are located on the same conductive layer.

[0110] Exemplary, in a configuration in which two first anodes 431 are electrically connected to a first-type pixel driving circuit via a third wiring 313, the two first anodes 431 are electrically connected via the third wiring 313, one end of the first wiring 311 is electrically connected to the third wiring 313, and the other end of the first wiring 311 is electrically connected to the first-type pixel driving circuit. The first wiring 311 can be provided on the first conductive layer 32 or the second conductive layer 34, and the third wiring 313 and the first wiring 311 can be provided on the same conductive layer.

[0111] In some embodiments, as shown in Figures 8A, 9A, 10A, 7A, and 7B, the conductive layer is also provided with connecting portions 36. The connecting portions 36 are used to electrically connect the connecting wire 31 to the anode, or to connect the connecting wire 31 to the connecting wire 31. As shown in Figure 7B, the second conductive layer 34 further comprises a plurality of second connecting portions 362, and the first conductive layer 32 further comprises a plurality of first connecting portions 361.

[0112] Each second connection portion 362 is electrically connected to one type first anode, and the connection wiring 31 located in the second conductive layer 34 is electrically connected to the type first anode via the second connection portion 362. The first conductive layer 32 further comprises a plurality of first connection portions 361, each first connection portion 361 is electrically connected to one second connection portion 362. The connection wiring 31 located in the first conductive layer 32 is electrically connected to the type first anode via the connected first connection portions 361 and second connection portions 362.

[0113] In some examples, as shown in Figures 8A, 9A, and 10A, the first type anode row 42 comprises a first sub-row 421 and a second sub-row 422 arranged in parallel. The second sub-row 422 comprises a plurality of sequentially arranged first anodes 431, the centers of which lie on the same straight line. The first sub-row 421 comprises a plurality of alternately arranged second and third anodes, the centers of which lie on different straight lines. The plurality of second connectors 362 are arranged in a plurality of rows, and the orthographic projection of the second connector 362 of each row on the base substrate lies between the orthographic projections of two straight lines on the base substrate corresponding to one type anode row 42. That is, the second connector 362 of each row lies between the first sub-row 421 and the second sub-row 422 of one type anode row 42.

[0114] Exemplary, as shown in Figure 7B, the connecting wires 31 are all connected to a single connection portion 36 at their ends located in the second display area 11a. The connection portion 36 comprises a second connection portion 362 located in the second conductive layer 34 and a first connection portion 361 located in the first conductive layer 32. The orthographic projection of the second connection portion 362 on the base substrate is the first type anode connected thereto. 43a1 Because it overlaps with the orthographic projection on the base substrate, the first type anode 43a1 Through the second via hole 351 that penetrates the second insulating layer 35 Second connection section 362 The first connection part 361 and the second connection part 362 are connected. The vertical positions of the connected first connection part 361 and the second connection part 362 correspond to each other on the display panel 100, meaning that their orthographic projections on the base substrate 10 overlap. Therefore, the second connection part 362 is connected to the first connection part 361 via the first via hole 331 that penetrates the first insulating layer 33. As a result, by providing the connection part 36, the connection between the connection wiring 31 and the anode becomes more stable.

[0115] In some embodiments, Figure 7B As shown, the multiple first wirings 311 and the multiple third wirings 313 are connected to the second conductive layer 34It is located at . Of the connected first wiring 311 and third wiring 313, the first wiring 311 is connected to two second connection parts 362 and connects two first anodes 431, and the first wiring 311 is connected to one of the two connected second connection parts 362. Of the two connected second connection parts 362, the one connected to the first wiring 311 is located at . 431 The distance between the electrically connected Type 1 pixel driver circuit and the orthographic projection on the base substrate is small.

[0116] Exemplary, the first wiring 311 is located in the second conductive layer 34, and the third wiring 313 and the first wiring 311 are located in the same conductive layer. The third wiring 313 electrically connects two first anodes 431. For example, the two first anodes 431 may be two adjacent anodes. Each of the two connected first anodes 431 has a corresponding second connection portion 362. That is, the orthographic projection of the second conductive layer 34 of each first anode 431 overlaps with one second connection portion 362, and the third wiring 313 is provided between the two second connection portions 362, connecting the two second connection portions 362. The first wiring 311 is electrically connected to one of the two second connection portions 362, realizing the electrical connection between the first pixel driving circuit and the second connection portion 362. Of the two connected second connection parts 362, the orthographic projection on one base board electrically connected to one end of the first wiring 311 is the first projection, the orthographic projection on the other base board 10 is the second projection, and the orthographic projection on the base board of the first type pixel driving circuit electrically connected to the other end of the first wiring 311 is the third projection. Since the linear distance between the first projection and the third projection is smaller than the linear distance between the second projection and the third projection, the length of the first wiring can be shortened.

[0117] In some other examples, Figure 7AAs shown, the multiple first wirings 311 and the multiple third wirings 313 are located in the first conductive layer 32, and of the connected first wirings 311 and third wirings 313, the third wirings 313 are connected to two first connection parts 361 and connect two first anodes 431. For example, the two first anodes 431 may be two adjacent first anodes. The first wiring 311 is connected to one of the two first connection parts 361. Of the two connected first connection parts 361, the one connected to the first wiring 311 has a shorter distance between the orthographic projection on the base substrate and the orthographic projection on the base substrate of the first type pixel driving circuit electrically connected to the two first anodes compared to the other.

[0118] Exemplary, the first wiring 311 is located in the first conductive layer 32, and the third wiring 313 and the first wiring 311 are located in the same conductive layer. The third wiring 313 electrically connects two first anodes 431. Each of the two first anodes 431 has a corresponding first connection 361 and a second connection 362. That is, the orthographic projection of the second conductive layer 34 of the first anode 431 overlaps with the second connection 362, and the orthographic projection of the first conductive layer 32 of the first anode 431 overlaps with the first connection 361, and the first connection 361 and the second connection 362 are electrically connected by via holes. The two first connection 361s are connected via the third wiring 313, which connects the two second connection 362s. The first wiring 311 is electrically connected to one of the two first connection parts 361, thereby realizing an electrical connection between the first type pixel driving circuit and the first connection part 361. Of the two connected first connection parts 361, the orthographic projection on one base substrate electrically connected to one end of the first wiring 311 is the first projection', the orthographic projection on the other base substrate 10 is the second projection', and the orthographic projection on the base substrate of the first type pixel driving circuit electrically connected to the other end of the first wiring 311 is the third projection'. Since the linear distance between the first projection' and the third projection' is smaller than the linear distance between the second projection' and the third projection', the length of the first wiring 311 can be shortened.

[0119] The above installation reduces the length of each first wiring 311, improves the stability of the current signal transmitted through the first wiring 311, and ensures the normal operation of the light-emitting element of the green subpixel in the second display area 11a.

[0120] In some embodiments, the first wiring 311, the second wiring 312, and the third wiring 313 all comprise a transparent conductive material. For example, the first wiring 311, the second wiring 312, and the third wiring 313 can be made of indium tin oxide or indium zinc oxide.

[0121] In some embodiments, the insulating layer includes a transparent insulating material. For example, the first insulating layer 33 or the second insulating layer 35 can be made of polyimide (PI).

[0122] Furthermore, if the area of ​​the second display area 11a is small, or if the process precision for manufacturing the connecting wiring 31 is high and the width of the connecting wiring 31 can be further reduced, all the connecting wiring 31 can be placed on a single conductive layer. That is, the connecting layer shown in Figure 7A consists of only one conductive layer and one insulating layer, which further reduces the number of masks used in the manufacturing process, simplifies the process, and at the same time improves the light transmittance of the second display area 11a, reduces the overall thickness of the display panel 100, and makes the display panel 100 lighter and thinner.

[0123] The present disclosure further provides a display device 1000, as shown in Figure 16, which comprises a display panel 100 and at least one sensor 200 provided in any of the above embodiments. The sensor 200 is provided on the non-display side of the display panel 100, and the orthographic projection of the sensor 200 on the display panel 100 is located in the second display area 11a. The sensor 200 is an optical sensor 200.

[0124] In some embodiments, at least one sensor 200 is an optical sensor 200 such as a front camera, proximity light sensor 200, or 3D sensing module. Exemplarily, the display device 1000 comprises a display panel 100 and a front camera provided on the non-display side of the display panel 100. The base substrate 10 and drive circuit layer 20 of the display panel 100 are light-transmitting in the second display area 11a. For example, the second display area 11a is a circular area, the display panel 100 is entirely transparent in the second display area 11a, the orthographic projection of the front camera on the display panel 100 is located in the second display area 11a, and the front camera is light-sensitive. Side It is facing the display surface side of the display device 1000. The front camera performs image acquisition through the transparent second display area 11a.

[0125] In some examples, the display device 1000 further comprises a frame, a circuit board, a display driver IC (Integrate Circuit), and other electronic components, and the display panel 100 is housed within the frame.

[0126] The display device 1000 provided by embodiments of this disclosure may be any device that displays whether the content is moving (e.g., video) or stationary (e.g., still image) and regardless of whether it is text or images. The display device 1000 may be a mobile phone, computer, camera, video player, camcorder, game console, wristwatch, clock, calculator, television monitor, flat panel display, etc.

[0127] The display panel 100 provided by this disclosure uses the display panel 100 provided in the above embodiment and has the same beneficial effects as the above display panel 100, which will not be described again here.

[0128] This disclosure further provides a method for manufacturing the display panel 100, which includes S1 to S5 as shown in Figure 17.

[0129] S1 provides the base substrate 10.

[0130] For example, as shown in Figure 18A, the base substrate 10 may be a silicon substrate or a glass substrate. The base substrate 10 is divided into a peripheral region 10b and a display region 10a, and the display region 10a is divided into a first display region 11b and a second display region 11a.

[0131] S2, a drive circuit layer 20 is formed on the base substrate 10. The drive circuit layer 20 comprises a plurality of first-type pixel drive circuits, and the plurality of first-type pixel drive circuits drive a first display area 11b It will be placed there.

[0132] Exemplary, as shown in Figure 18B, a semiconductor layer 22, a gate insulating layer 23, a gate layer 24, an interlayer insulating layer 25, a source-drain metal layer 26, and a planarization layer 27 are sequentially formed on a base substrate 10. The corresponding film layers are formed using a normal deposition process and patterning process. For example, a semiconductor material layer is deposited on the base substrate 10, and the semiconductor material layer is patterned using an etching process to form the semiconductor layer 22. The manufacturing processes for the gate insulating layer 23, gate layer 24, interlayer insulating layer 25, source-drain metal layer 26, and planarization layer 27 can refer to the manufacturing of the semiconductor layer 22. The semiconductor layer 22, gate insulating layer 23, gate layer 24, interlayer insulating layer 25, source-drain metal layer 26, and planarization layer 27 constitute a drive circuit layer 20. The drive circuit layer 20 includes a first-type pixel drive circuit 211 and a second-type pixel drive circuit 212. Both the first-type pixel driving circuit 211 and the second-type pixel driving circuit 212 are located in the first display area 11b. The first-type pixel driving circuit 211 can be manufactured in the array gap of the second-type pixel driving circuit 212 using a pixel compression process.

[0133] S3, a connection layer 30 is formed. The connection layer 30 comprises a plurality of connection wires 31, and the plurality of connection wires 31 comprises a first wire 311 and a plurality of second wires 312.

[0134] As shown in Figure 18C, in some embodiments, the connection layer 30 is located on the side of the drive circuit layer 20 away from the base substrate 10. In S3, a conductive layer and an insulating layer are formed sequentially on the side of the drive circuit layer 20 away from the base substrate 10, and patterns corresponding to the conductive layer and the insulating layer are formed, for example, multiple connections are made in the conductive layer. wiring For example, a first conductive layer 32, a first insulating layer 33, a second conductive layer 34, and a second insulating layer 35 are sequentially formed on the side of the drive circuit layer 20 away from the base substrate 10.

[0135] S4, a light-emitting layer 40 is formed. The light-emitting layer 40 comprises a pixel definition layer 44, an anode layer 43, an emissive film layer 45, and a cathode layer 46. The anode layer 43 comprises a plurality of anodes 43a. The plurality of light-emitting elements 41 in the light-emitting layer 40 are arranged in an array, that is, the plurality of anodes 43a are arranged in an array.

[0136] As shown in Figure 18D, S4 includes S41. In S41, an anode layer 43 is formed on the side of the connecting layer 30 away from the base substrate 10. The anode layer 43 comprises a plurality of first type anodes 43a1 located in the second display area 11a. The plurality of first type anodes 43a1 comprises a plurality of first anodes 431, a plurality of second anodes 432, and a plurality of third anodes 433. Two adjacent first anodes 431 are electrically connected to a single first type pixel driving circuit 211 via a single first wiring 311. Each second anode 432 is electrically connected to a single first type pixel driving circuit 211 via a single second wiring 312. Each third anode 433 is electrically connected to a single first type pixel driving circuit 211 via a single second wiring 312. Similarly, the anode layer 43 further comprises a plurality of second type anodes 43a2 located in the first display area 11b. Each of the multiple Type 2 anodes 43a2 comprises multiple Type 1 anodes, multiple Type 2 anodes, and multiple Type 3 anodes. The arrangement of the multiple Type 1 anodes 43a1 and the multiple Type 2 anodes 43a2 is consistent.

[0137] S4 further includes S42. In S42, a pixel definition layer 44, an emissive film layer 45, and a cathode layer 46 are sequentially formed on the side of the anode layer 43 away from the base substrate 10. The pixel definition layer 44 has multiple openings, each opening exposing one anode 43a. The emissive film layer 45 has multiple emissive layers 45a, each emissive layer 45a located within one opening and in contact with the anode 43a, forming the cathode layer 46 on the side of the emissive film layer 45 and the pixel definition layer 44 away from the base substrate 10. Each anode 43a, one emissive layer 45a, and the portion located within the opening of the cathode layer 46 form one light-emitting element 41.

[0138] S5, as shown in Figure 18E, a packaging layer 50 is formed on the side of the light-emitting element layer 40 away from the base substrate 10. The packaging layer 50 covers the light-emitting element layer 40. The packaging layer 50 is used to protect the light-emitting element layer 40, preventing it from being damaged by the outside environment and also preventing corrosion by water and oxygen.

[0139] In some embodiments, as shown in Figures 5 and 18C, the connection layer 30 comprises a first conductive layer 32, a first insulating layer 33, a second conductive layer 34, and a second insulating layer 35, which are sequentially provided on the side of the drive circuit layer 20 away from the base substrate 10. As shown in Figure 19, S3 forms the connection layer 30 on the side of the drive circuit layer 20 away from the base substrate 10 and includes S31 to S34.

[0140] S31, a first conductive material layer 32a is formed on the side of the drive circuit layer 20 away from the base substrate 10, and the first conductive material layer 32a is patterned with a first mask 32'' to form a first conductive layer 32 having a pattern.

[0141] For example, as shown in Figures 20A to 20D, S31 includes S311 to S315.

[0142] In S311, as shown in Figure 20A, a first conductive material layer 32a is formed on the side of the drive circuit layer 20 away from the base substrate 10. The first conductive material layer 32a is a film layer that covers the entire display area 10a.

[0143] S312, as shown in Figure 20A, a first photoresist layer 32' is formed on the side of the first conductive material layer 32a that is away from the base substrate 10.

[0144] In step S313, as shown in Figure 20B, the first photoresist layer 32' is exposed using the first mask 32'', and then the exposed first photoresist layer 32' is developed to form a pattern corresponding to the first photoresist layer 32'.

[0145] As shown in Figure 20C, in step S314, the first conductive material layer 32a and the first photoresist layer 32' are etched using dry etching.

[0146] S315, as shown in Figure 20D, the first conductive material layer 32 a The portion of the first conductive material layer 32a exposed by the first photoresist layer 32' is removed, and the retained portion of the first conductive material layer 32a becomes the first conductive layer 32, which has a pattern, for example, the pattern of the first conductive layer 32 comprises a plurality of connection lines 31, which are, for example, first lines 311 and / or a plurality of second lines 312.

[0147] In S32, a first insulating material layer is formed on the side of the first conductive layer 32 away from the base substrate 10, and the first insulating material layer is patterned with a second mask to form a first insulating layer 33 having a pattern.

[0148] As shown in Figures 20E to 20H, exemplary, forming a patterned first insulating layer 33 on the first conductive layer 32 includes steps S321 to S325.

[0149] S321, as shown in Figure 20E, a first insulating material layer 33a is formed on the side of the first conductive layer 32 away from the base substrate 10. The first insulating material layer 33a is a film layer that covers the entire display area 10a, and the first insulating material layer 33a may be polyimide (PI).

[0150] S322, as shown in Figure 20E, a second photoresist layer 33' is formed on the side of the first insulating material layer 33a that is away from the base substrate 10.

[0151] In step S323, as shown in Figure 20F, the second photoresist layer 33' is exposed using the second mask 33'', and then the exposed second photoresist layer 33' is developed to form a pattern corresponding to the second photoresist layer 33'.

[0152] As shown in Figure 20G, in step S324, the first insulating material layer 33a and the second photoresist layer 33' are etched using dry etching.

[0153] S325, as shown in Figure 20H, the first insulation material layer 33 a The portion of the first insulating material layer 33a exposed by the second photoresist layer is removed, and the retained portion of the first insulating material layer 33a becomes the first insulating layer 33, which has a pattern, for example, the pattern of the first insulating layer 33 comprises a plurality of first via holes 331.

[0154] S33, a second conductive material layer is formed on the side of the first insulating layer away from the base substrate, and the second conductive material layer is patterned with a third mask to form a second conductive layer having a pattern.

[0155] As shown in Figures 20I to 20L, exemplary, a second conductive layer 34 having a pattern is formed on the side of the first insulating layer 33 away from the base substrate 10, as shown in S331 to S33. 5 Includes.

[0156] S331, as shown in Figure 20I, First insulating layer 33 A second conductive material layer 34a is formed on the side away from the base substrate 10. The second conductive material layer 34a is a film layer that covers the entire display area 10a.

[0157] S332, as shown in Figure 20I, a third photoresist layer 34' is formed on the side of the second conductive material layer 34a that is away from the base substrate 10.

[0158] As shown in Figure 20J, in step S333, the third photoresist layer 34' is exposed using the third mask 34'', and then the exposed third photoresist layer 34' is developed to form a pattern corresponding to the third photoresist layer 34'.

[0159] In step S334, as shown in Figure 20K, the second conductive material layer and the third photoresist layer 34' are etched using dry etching.

[0160] S335, as shown in Figure 20L, the second conductive material layer 34 a The portion of the second conductive material layer exposed by the third photoresist layer is removed, and the retained portion of the second conductive material layer becomes the second conductive layer 34, which has a pattern, for example, the pattern of the second conductive layer 34 comprises a plurality of first wirings and / or a plurality of second wirings.

[0161] S34, a second insulating material layer is formed on the side of the second conductive layer away from the base substrate, and the second insulating material layer is patterned with a fourth mask to form a second insulating layer having a pattern.

[0162] As shown in Figures 20M to 20P, exemplary, a second insulating layer 35 having a pattern is formed on the side of the second conductive layer 34 away from the base substrate 10, as shown in S341 to S34. 5 Includes.

[0163] As shown in Figure 20M, S341, a second insulating material layer 35a is formed on the side of the second conductive layer 34 away from the base substrate 10. The second insulating material layer 35a is a film layer that covers the entire display area 10a, and the second insulating material layer 35a may be polyimide (PI).

[0164] As shown in Figure 20M, S342, a fourth photoresist layer 35' is formed on the side of the second insulating material layer 35a that is away from the base substrate 10.

[0165] In step S343, as shown in Figure 20N, the fourth photoresist layer 35' is exposed using the fourth mask 35'', and then the exposed fourth photoresist layer 35' is developed to form a pattern corresponding to the fourth photoresist layer 35'.

[0166] As shown in Figure 20O, in step S344, the second insulating material layer 35a and the fourth photoresist layer 35' are etched using dry etching.

[0167] In step S345, as shown in Figure 20P, the portion of the second insulating layer 35 exposed by the fourth photoresist layer is removed, and the retained portion of the second insulating material layer becomes the second insulating layer 35, which has a pattern, for example, the pattern of the second insulating layer 35 comprises a plurality of second via holes 351.

[0168] The method for manufacturing the display panel 100 provided by this disclosure is used to manufacture a display panel as shown in Figure 5. Since the connecting layer comprises only two conductive layers and two insulating layers, four patterning operations are performed using four masks during the manufacturing process of the connecting layer, reducing the number of masks used, simplifying the manufacturing process, improving efficiency, and increasing production capacity. In addition, the thickness of the light transmitted through the optical sensor in the second display area can be reduced, improving the efficiency of light transmission, improving the operating performance of the optical sensor, and ensuring the display quality of the display panel.

[0169] The foregoing describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that are readily conceivable to a person skilled in the art within the technical scope of the Disclosure are all included within the technical scope of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be governed by the scope set forth in the claims.

Claims

1. A display panel including a display area, wherein the display area includes a first display area and a second display area. The aforementioned display area is Base board and A drive circuit layer provided on one side of the base substrate, comprising a plurality of first-type pixel drive circuits located in the first display area, A connection layer comprising multiple connection wirings, wherein the multiple connection wirings comprise a connection layer comprising a plurality of first wirings and a plurality of third wirings, An anode layer comprising a plurality of first type anodes located in the second display area, wherein the plurality of first type anodes comprises a plurality of first anodes, the third wiring connects at least two of the first anodes, and the first wiring connects one third wiring and one first type pixel driving circuit so that the at least two of the first anodes are electrically connected to one first type pixel driving circuit via one first wiring, Equipped with, The plurality of first-type anodes further comprises a plurality of second anodes and a plurality of third anodes, the plurality of connecting wires further comprises a plurality of second wires, the second anodes are electrically connected to one of the first-type pixel driving circuits via the second wires, and the third anodes are electrically connected to one of the first-type pixel driving circuits via the second wires. The at least two first anodes constitute a first anode group, and among an adjacent first anode group, a second anode, and a third anode, the length of the first wiring electrically connected to the first anode group is smaller than the length of the second wiring electrically connected to the second anode, and also smaller than the length of the second wiring electrically connected to the third anode. The first anode, the second anode, and the third anode are each the anodes of light-emitting elements of subpixels of different colors. Display panel.

2. The aforementioned connection layer is provided on the side of the drive circuit layer away from the base substrate, The anode layer is provided on the side of the connecting layer away from the base substrate. The display panel according to claim 1.

3. The connecting layer comprises at least one conductive layer and at least one insulating layer, and the insulating layer is provided on the side of the at least one conductive layer that is away from the base substrate. The display panel according to claim 2.

4. The aforementioned connecting layer is A first conductive layer provided on the side of the drive circuit layer away from the base substrate, A first insulating layer provided on the side of the first conductive layer away from the base substrate, A second conductive layer is provided on the side of the first insulating layer away from the base substrate, A second insulating layer provided on the side of the second conductive layer away from the base substrate, Equipped with, The first conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, and the second conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, The connected third and first wirings are located on the same conductive layer. The first insulating layer has a first via hole, the second insulating layer has a second via hole, the first conductive layer is electrically connected to the second conductive layer via the first via hole, and the second conductive layer is electrically connected to the anode layer via the second via hole. The display panel according to claim 3.

5. The plurality of first type anodes are arranged in a plurality of first type anode rows, and at least one of the first type anode rows comprises at least two first anodes, at least one second anode, and at least one third anode arranged in one row. At least two of the first anodes in the first type anode row are electrically connected to the first wiring, or The plurality of first type anodes are arranged in a plurality of first type anode rows, and at least one of the first type anode rows comprises at least two first anodes, at least one second anode, and at least one third anode arranged in a row. At least two of the first anodes in the first type anode array are electrically connected to the first wiring. The display panel according to claim 1.

6. The at least one first type anode row is arranged periodically in the order of second anode, first anode, third anode, and first anode, The plurality of connecting wires are arranged in a plurality of wiring groups, each wiring group comprising at least one first wire and at least two second wires, the plurality of connecting wires extend along a first direction, the first direction being the row direction in which the plurality of first type anodes are arranged, In the wiring group, the first wiring is connected to at least two of the first anodes in the first type anode row, and the second wiring is connected to one of the second anodes or one of the third anodes in the first type anode row. or In the wiring group, the first wiring is connected to at least two of the first anodes in the first type anode row, and at least two second wirings in the wiring group comprise at least one first sub-wiring and at least one second sub-wiring, the first sub-wiring being connected to one of the second anodes or one of the third anodes in the first type anode row, and the second sub-wiring being electrically connected to one of the second anodes or one of the third anodes in another first type anode row adjacent to the first type anode row. The display panel according to claim 5.

7. The at least one of the first type anode arrays is arranged periodically in the order of second anode, first anode, third anode, and first anode, The plurality of connecting wires are arranged in a plurality of wiring groups, each wiring group comprising at least one first wire and at least two second wires, the plurality of connecting wires extend along a second direction, the second direction being the row direction in which the plurality of first type anodes are arranged. In the wiring group, the first wiring is connected to at least two of the first anodes in the first type anode array, and the second wiring is connected to one of the second anodes or one of the third anodes in the first type anode array. or In the wiring group, the first wiring is connected to at least two of the first anodes in the first type anode array, and at least two second wirings in the wiring group comprise at least one first sub-wiring and at least one second sub-wiring, the first sub-wiring being connected to one of the second anodes or one of the third anodes in the first type anode array, and the second sub-wiring being electrically connected to one of the second anodes or one of the third anodes in another first type anode array. The display panel according to claim 5.

8. The orthographic projection of the plurality of first-type pixel driving circuits on the base substrate is located on one or both sides of the orthographic projection of the plurality of first-type anodes on the base substrate, along the extending direction of the plurality of connection wirings. The display panel according to claim 6 or 7.

9. The aforementioned connecting layer is A first conductive layer provided on the side of the drive circuit layer away from the base substrate, A first insulating layer provided on the side of the first conductive layer away from the base substrate, A second conductive layer is provided on the side of the first insulating layer away from the base substrate, A second insulating layer provided on the side of the second conductive layer away from the base substrate, Equipped with, The first conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, and the second conductive layer comprises a plurality of first wirings and / or a plurality of second wirings, The first insulating layer has a first via hole, the second insulating layer has a second via hole, the first conductive layer is electrically connected to the second conductive layer via the first via hole, and the second conductive layer is electrically connected to the anode layer via the second via hole. The second conductive layer further comprises a plurality of second connection portions, the second connection portions being electrically connected to the first type anode, and the connection wiring located in the second conductive layer being electrically connected to the first type anode via the second connection portions. The first conductive layer further comprises a plurality of first connection portions, the first connection portions are electrically connected to the second connection portions, and the connection wiring located in the first conductive layer is electrically connected to the first type anode via the connected first and second connection portions. The display panel according to claim 8.

10. The plurality of first wirings and the plurality of third wirings are located in the second conductive layer, and of the connected first wirings and third wirings, the third wiring is connected to two adjacent second connection points, thereby connecting to two adjacent first anodes, and the first wiring is connected to one of the two adjacent second connection points, and of the two adjacent second connection points, the one connected to the first wiring has a closer distance between the orthogonal projection on the base substrate and the orthogonal projection on the base substrate of the first type pixel driving circuit electrically connected to the two adjacent first anodes, compared to the other. or The plurality of first wirings and the plurality of third wirings are located in the first conductive layer, and of the connected first wirings and third wirings, the third wiring is connected to two adjacent first connection portions and thereby connected to two adjacent first anodes, and the first wiring is connected to one of the two adjacent first connection portions, and of the two adjacent first connection portions, the one connected to the first wiring has a shorter distance between the orthogonal projection on the base substrate and the orthogonal projection on the base substrate of the first type pixel driving circuit electrically connected to the two adjacent first anodes compared to the other. The display panel according to claim 9.

11. The drive circuit layer further comprises a plurality of second-type pixel drive circuits arranged in an array in the first display area, and the plurality of first-type pixel drive circuits are provided in the array gap of the plurality of second-type pixel drive circuits. The anode layer further comprises a plurality of second-type anodes located in the first display area, and the second-type anodes are electrically connected to the second-type pixel driving circuit. The display panel according to claim 10.

12. A display panel according to any one of claims 1 to 11, At least one sensor, provided on the non-display side of the display panel, and the orthographic projection of the display panel is located in the second display area, Equipped with, Display device.

13. A method for manufacturing a display panel, wherein the display panel includes a display area, and the display area includes a first display area and a second display area. The manufacturing method of the display panel is as follows: To provide a base substrate, A drive circuit layer is formed on the base substrate, wherein the drive circuit layer comprises a plurality of first-type pixel drive circuits, and the plurality of first-type pixel drive circuits are provided in the first display area. The method involves forming a connecting layer, wherein the connecting layer comprises a plurality of connecting wires, and the plurality of connecting wires comprises a first wire, a second wire, and a third wire. The present invention relates to the formation of an anode layer, wherein the anode layer comprises a plurality of first type anodes located in the second display area, the plurality of first type anodes comprises a plurality of first anodes, a plurality of second anodes, and a plurality of third anodes, the third wiring connects at least two of the first anodes, the first wiring connects one third wiring and one first type pixel driving circuit so that at least two of the first anodes are electrically connected to one first type pixel driving circuit via one first wiring, the second anode is electrically connected to one first type pixel driving circuit via one second wiring, and the third anode is electrically connected to one first type pixel driving circuit via the second wiring. Includes, The at least two first anodes constitute a first anode group, and among an adjacent first anode group, a second anode, and a third anode, the length of the first wiring electrically connected to the first anode group is smaller than the length of the second wiring electrically connected to the second anode, and also smaller than the length of the second wiring electrically connected to the third anode. The first anode, the second anode, and the third anode are each the anodes of light-emitting elements of subpixels of different colors. A method for manufacturing a display panel.

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