A turbo code design method, a turbo code design apparatus, and a recording medium for storing a turbo code design program.

Abstract

Provided is a turbo code design method for designing turbo codes using high-performance interleavers. A turbo encoder is provided with a first convolutional encoder, an interleaver, and a second convolutional encoder. The first convolutional encoder uses a predetermined RSC code to generate a first parity stream of input data. The interleaver rearranges the ordering of a series in the interior of the input data on the basis of a first rule, thus generating rearranged data. The second convolutional encoder uses an RSC code to generate a second parity stream of the rearranged data. The turbo code design method includes selecting a polynomial representing an RSC code from a Galois field of polynomials, and designing the first rule of the interleaver on the basis of the RSC code.

Description

[Technical Field]

[0001] The present invention relates to a turbo code design method, a turbo code design apparatus, and a recording medium for storing a turbo code design program. [Background technology]

[0002] Turbo codes are known as error correction codes that have performance relatively close to the so-called Shannon limit. In turbo codes, output data is generated by combining the input data, the parity stream of the input data, and the parity stream of swapped data obtained by rearranging the sequence within the input data.

[0003] A circuit that rearranges the order of sequences within input data is called an interleaver. Known interleavers include S-Random (Semi-Random) interleavers and QPP (Quadratic Permutation Polynomial) interleavers. However, S-Random interleavers have the drawback of requiring a relatively large amount of memory during sign-time and / or decomposition, and are not capable of parallel decomposition. QPP interleavers, on the other hand, perform worse than S-Random interleavers when the bit length is relatively long (e.g., 1024 bits).

[0004] In relation to the above, Non-Patent Document 1 ("LTE Envolved Universal Terrestrial Radio Access (E-UTRA): Multiplexing and Channel Coding," published by Third Generation Partnership Project (3GPP) Std., January 2011) discloses that LTE (Long-Term Evolution) employs turbo coding using QPP interleavers ("3GPP" is a registered trademark). [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] "LTE Envolved Universal Terrestrial Radio Access (E-UTRA): Multiplexing and Channel Coding", issued by Third Generation Partnership Project (3GPP) Std., January 2011 [Summary of the Invention]

[0006] In view of the above situation, one of the objectives of the present disclosure is to provide a turbo code design method, a turbo code design device, and a recording medium storing a turbo code design program for designing a turbo code using a high-performance interleaver. Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

[0007] According to one embodiment, the turbo code design method is a turbo code design method for designing a turbo code. The turbo coder that executes the turbo code comprises a first convolutional coder, an interleaver, and a second convolutional coder. The first convolutional coder generates a parity stream of the input data as a first parity stream using a predetermined RSC (Recursive Systematic Convolutional) code. The interleaver generates swapped data by rearranging the sequence order within the input data based on a first rule. The second convolutional coder generates a parity stream of the swapped data as a second parity stream using an RSC code. The turbo code design method includes selecting a polynomial representing the RSC code from among the elements of the Galois field generated by the generating polynomial, designing a first rule for the interleaver based on the RSC code, and outputting information representing the designed turbo code to the outside. The polynomial representing the RSC code includes a feedforward polynomial representing the feedforward connection and a feedback polynomial representing the feedback connection. Each of the feedforward and feedback polynomials is either a single polynomial selected from the elements of the Galois field, or the product of multiple polynomials selected from the elements of the Galois field.

[0008] According to one embodiment, the turbo code design device is a turbo code design device that designs turbo codes. The turbo coder that executes the turbo code comprises a first convolutional coder, an interleaver, and a second convolutional coder. The first convolutional coder generates a parity stream of the input data as a first parity stream using a predetermined RSC code. The interleaver generates swapped data by rearranging the sequence order within the input data based on a first rule. The second convolutional coder generates a parity stream of the swapped data as a second parity stream using an RSC code. The turbo code design device comprises an RSC code selection unit, a PM design unit, a coset design unit, and an output unit. The RSC code selection unit selects a polynomial representing the RSC code from among the Galois fields of polynomials. The PM design unit designs a PM (Permutation Matrix) that represents the correspondence between the sequence order of the internal data and the swapped data based on the period of the RSC code. The coset design unit designs a second rule for dividing the input data based on the period of the RSC code and generating multiple cosets from multiple disjoint sets. The output unit outputs information representing the designed turbo code to the outside. The polynomial representing the RSC code is either a single polynomial selected from the Galois field, or the product of multiple polynomials selected from the Galois field. The period of the RSC code is the cyclic period bit length when the output data of an RSC code, input data where the first bit is 1 and the subsequent bits are 0, cycles at a predetermined period from a predetermined bit onward.

[0009] According to one embodiment, the recording medium storing the turbo code design program stores a program that enables processing for designing a turbo code by having it executed by an arithmetic unit. The turbo coder that executes the turbo code comprises a first convolutional coder, an interleaver, and a second convolutional coder. The first convolutional coder generates a parity stream of the input data as a first parity stream using a predetermined RSC code. The interleaver generates swapped data by rearranging the sequence order within the input data based on a first rule. The second convolutional coder generates a parity stream of the swapped data as a second parity stream using an RSC code. The processing for designing a turbo code includes selecting a polynomial representing the RSC code from among the elements of the Galois field generated by the generating polynomial, designing a first rule for the interleaver based on the RSC code, and outputting information representing the designed turbo code to the outside. The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. A feedforward polynomial and a feedback polynomial are, respectively, a single polynomial selected from the elements of a Galois field, or the product of multiple polynomials selected from the elements of a Galois field.

[0010] According to one embodiment, a turbo code using a high-performance interleaver can be designed. [Brief explanation of the drawing]

[0011] [Figure 1A] Figure 1A is a block circuit diagram showing one example configuration of a turbocoder according to one embodiment. [Figure 1B] Figure 1B is a block circuit diagram showing one example configuration of a convolutional encoder according to one embodiment. [Figure 2] Figure 2 is a block circuit diagram showing one example configuration of a turbo code design device according to one embodiment. [Figure 3] Figure 3 is a flowchart showing an example of the processing configuration of a turbo code design method according to one embodiment. [Figure 4] Figure 4 is a table showing an example of the order of roots and the period of the RSC code corresponding to several polynomials. [Figure 5] Figure 5 is a table showing an example of the correspondence between the generating polynomial of the RSC code and the power representation of the elements of the Galois field generated by the generating polynomial. [Figure 6] Figure 6 is a table showing examples of combinations of codeword Hamming weights, common polynomials, input bit sequences as swap data, and output bit sequences as parity streams when (37 / 21)8 is selected as the RSC code. [Figure 7] Figure 7 is a table showing examples of parameter combinations used in the general formula for representing a permutation bit sequence when the Hamming weight of the input bit sequence is 4. [Figure 8] Figure 8 is a graph showing an example of the results of a computer simulation performed to verify the effectiveness of the RSC code according to one embodiment. [Figure 9] Figure 9 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed using a turbo code design method according to one embodiment. [Figure 10] Figure 10 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. [Figure 11] Figure 11 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. [Figure 12] Figure 12 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. [Figure 13] Figure 13 is a block circuit diagram showing one example configuration of a turbocoder according to one embodiment. [Modes for carrying out the invention]

[0012] With reference to the attached drawings, embodiments for implementing the turbo code design method, turbo code design apparatus, and recording medium for storing the turbo code design program according to this disclosure will be described below.

[0013] (Embodiment) As shown in Figure 1A, the turbocoder 1 that performs turbo coding comprises an interleaver 3, a first convolutional coder 41, and a second convolutional coder 42. The turbocoder 1 may further include a coupler (not shown).

[0014] The first convolutional encoder 41 applies RSC (Recursive Systematic Convolutional) encoding to the input data 2 to generate a parity stream 410 of the input data 2. The interleaver 3 rearranges the sequence order within the input data 2 according to a predetermined rule to generate rearranged data 30. The second convolutional encoder 42 applies RSC encoding to the rearranged data 30 to generate a parity stream 420 of the rearranged data 30.

[0015] A coupler (not shown) generates output data by turbo-coding input data 2 based on input data 2, the parity stream 410 of input data 2, and the parity stream 420 of swapping data 30. The coupler may also generate intermediate data by partially downsampling and multiplexing parity streams 410 and 420, and generate output data by multiplexing the intermediate data with input data 2.

[0016] As shown in Figure 1B, the convolutional encoders 41 and 42 comprise delay units 431, 432, and 433, and adders. The delay units 431, 432, and 433 are connected in series. Some adders add the output of one of the delay units 431, 432, or 433 to the input data 2 or swapped data 30. Other adders generate a parity stream 410 or 420 by adding the output of one of the delay units 431, 432, or 433 to the input data 2 or swapped data 30. The convolutional encoders 41 and 42 are configured to correspond to the RSC coding process they perform. More specifically, the total number of delay units 431, 432, and 433, the total number of adders, and the connection relationships between the delay units 431, 432, 433 and the adders are determined to correspond to the polynomial representing the RSC code realized by the convolutional encoders 41 and 42. The configurations of the convolutional encoders 41 and 42 are the same. The delayers 431, 432, and 433 may be shift registers.

[0017] Designing the turbo codes that turbo encoder 1 executes includes designing convolutional encoders 41 and 42 and designing interleaver 3. Designing convolutional encoders 41 and 42 includes selecting a polynomial representing the RSC code from the elements of the Galois field generated by the generating polynomial. Here, the polynomial representing the RSC code includes a feedforward polynomial representing the feedforward connection and a feedback polynomial representing the feedback connection. Each of the feedforward polynomial and the feedback polynomial is either a single polynomial selected from the elements of the Galois field, or a product of multiple polynomials selected from the elements of the Galois field. Designing interleaver 3 includes designing a PM (Permutation Matrix) based on the RSC code represented by the selected polynomial, and designing a coset based on the designed PM. Details of the PM and coset will be described later.

[0018] Turbo code design may be performed using a turbo code design device 5 as shown in Figure 2. In one embodiment, the turbo code design device 5 may be configured as a computer. The turbo code design device 5 comprises a bus 51, an arithmetic unit 52, a storage device 53, a communication device 54, and an input / output device 55. The bus 51 is configured to connect the arithmetic unit 52, the storage device 53, the communication device 54, and the input / output device 55 so that they can communicate with each other.

[0019] The arithmetic unit 52 comprises an RSC code selection unit 521, a PM design unit 522, a surplus design unit 523, and an output unit 524. The storage device 53 stores the turbo code design program in a readable format. The turbo code design program may be read from the recording medium 530 that stores the turbo code design program and stored in the storage device 53. The arithmetic unit 52 and the storage device 53 cooperate to realize the processing of the turbo code design program. More specifically, the arithmetic unit 52 reads the turbo code design program and executes the turbo code design program using the memory area of ​​the storage device 53, thereby realizing the processing of the RSC code selection unit 521, the PM design unit 522, the surplus design unit 523, and the output unit 524. The RSC code selection unit 521, the PM design unit 522, the surplus design unit 523, and the output unit 524 are virtual functional blocks that realize the processing of the turbo code design device 5.

[0020] The RSC code selection unit 521 selects an RSC code in step S01, which will be described later. The PM design unit 522 designs a PM in step S02, which will be described later. The residue design unit 523 designs residues in step S03, which will be described later. The output unit 524 outputs information representing the designed turbo code to the outside in step S04, which will be described later. The more specific operation of these functional blocks will be described later.

[0021] The communication device 54 transmits and receives information to and from the outside via a network (not shown). For example, the output unit 524 controls the communication device 54 to output information to the outside. The turbo code design program may be received from the outside via the network by the communication device 54 and stored in the storage device 53.

[0022] The input / output device 55 outputs information to the user and accepts user input. For example, the input / output device 55 includes a display device that outputs images, a keyboard and / or mouse that accept input.

[0023] Referring to the flowchart in Figure 3, the processing of a turbo code design method according to one embodiment will be described. The processing in the flowchart of Figure 3 may start, for example, when the turbo code design device 5 is started up.

[0024] When the flowchart in Figure 3 starts processing, step S01 is executed. In step S01, the RSC code selection unit 521 in Figure 2 selects an RSC code. More specifically, the RSC code selection unit 521 selects a polynomial representing the RSC code from among the elements of the Galois field of polynomials. In this polynomial element included in the Galois field, the coefficient of each term is either 0 or 1.

[0025] As shown in the example in Figure 1B, in the convolutional encoders 41 and 42 that execute the RSC code, several adders feedforward the outputs of some of the delays 431, 432, and 433 to the outputs of the convolutional encoders 41 and 42. The configuration of this feedforward connection is represented by a polynomial f(x). In the example in Figure 1B, the inputs of the convolutional encoders 41 and 42, the output of the first-stage delay 431, and the output of the third-stage delay 433 are feedforward connected to the output of the convolutional encoder 41. Here, the inputs of the convolutional encoders 41 and 42 are the outputs of a virtual 0th-stage delay. The polynomial f(x) representing this configuration is x 0 +x 1 +x 3 This is equivalent to the construction of this feedforward connection, and the polynomial f(x) = 1 + x + x3 It is expressed as follows.

[0026] Similarly, in the convolutional encoders 41 and 42 that execute the RSC code in Figure 1B, several adders feed back some of the outputs of the delayers 431, 432, and 433 to the inputs of the convolutional encoders 41 and 42. The configuration of this feedback connection is represented by a polynomial g(x). In the example in Figure 1B, the output of the second-stage delayer 432 and the output of the third-stage delayer 433 are fed back to the input of the convolutional encoder 42. The polynomial g(x) representing this configuration is x 2 +x 3 This is equivalent to the construction of this feedback connection, and the polynomial g(x) = x 2 +x 3 It is expressed as follows. In this case, the RSC code generation function G is expressed as shown in equation "Equation 1" below.

[0027]

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[0028] The input bit sequence input to the convolutional encoders 41 and 42 via a feedback connection is represented by the polynomial b(x). The output bit sequence output to the outputs of the convolutional encoders 41 and 42 via a feedforward connection is represented by the polynomial h(x). In this case, the output c(x) of the RSC code is expressed as shown in equation "Equation 2" below.

[0029]

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[0030] Furthermore, the output bit sequence h(x) is expressed as shown in equation "Equation 3" below.

[0031]

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[0032] From the above "Equation 2", the Hamming weight w H (c(x)) of the output c(x) of the RSC code is the Hamming weight w H (b(x)) of the input bit sequence b(x) and the Hamming weight w H (h(x)) of the output bit sequence h(x), and is calculated as in the following "Equation 4".

[0033]

Equation

[0034] The Hamming weight of a polynomial is the total number of terms in the polynomial whose coefficients are not zero. In one embodiment, to simplify the design of the turbo code interleaver 3, a polynomial g(x) representing the configuration of the feedback connection is selected such that the Hamming weight of the parity stream 420 (or parity stream 410) output by the convolutional encoder 42 (or convolutional encoder 41) is smaller than a predetermined first threshold only when the swapped data 30 (or input data 2) input to the convolutional encoder 42 (or convolutional encoder 41) satisfies predetermined conditions. This first threshold may be, for example, the free distance to be achieved by the turbo code, and the value of this free distance may be, for example, 42. Alternatively, the first threshold may be a value calculated based on the free distance to be achieved. As an example, the first threshold value may be obtained by subtracting the Hamming weight of the input bit sequence b(x) and the minimum Hamming weight of the output bit sequence h(x) from the desired free distance, and then dividing this value by the periodic weight determined by the selected polynomial f(x), for example, 3. This condition is also satisfied when the swapped data 30 (or input data 2) has a binary representation where the distance between digits with a value equal to 1 is an integer multiple of the period τ of the RSC code, or when it can be represented as a sum of such values. Here, the polynomial g(x) is divisible by a given generating polynomial, and this generating polynomial satisfies the condition that there are no combinations of at least three distinct polynomials that sum to zero in the elements contained in the Galois field generated by this generating polynomial.

[0035] Next, a polynomial f(x) representing the construction of the feedforward connection is selected in accordance with the chosen polynomial g(x). For example, once the polynomial g(x) is determined, polynomials f(x) that satisfy the conditions are enumerated, and from the enumerated polynomials f(x), the polynomial f(x) that maximizes the polynomial h(x) for a specific pattern is selected.

[0036] Furthermore, in one embodiment, a set of polynomials a(x) that are factors corresponding to a feedback polynomial g(x) selected such that the Hamming weights of parity streams 410 and 420 are smaller than a first threshold only when the input bit sequence (input data 2 or swapped data 30) satisfies the above conditions, and a feedforward polynomial f(x) selected such that the Hamming weights of parity streams 410 and 420 are larger than a second threshold only when the input bit sequence (input data 2 or swapped data 30) satisfies the above conditions, is conveniently referred to as a common polynomial used in the design of the turbo code according to one embodiment. This correspondence means that the product obtained by multiplying polynomials g(x) and a(x) satisfies the conditions for the input bit sequence b(x), and the product obtained by multiplying polynomials f(x) and a(x) satisfies the conditions for the output bit sequence h(x). The inventors confirmed that the bit error rate evaluated using only the codewords included in this determined set agreed with the results of computer simulations with sufficient accuracy. This means that there are no omissions in the counting of the main codeword patterns that contribute to the calculation of the bit error rate.

[0037] After step S01 in Figure 3, step S02 is executed. In step S02, the PM design unit 522 in Figure 2 designs the PM. More specifically, the PM design unit 522 designs a PM (Permutation Matrix) that represents the correspondence of the internal sequence order between the input data 2 and the swapped data 30, based on the period of the RSC code. This process is part of the process of designing rules for the interleaver 3 to swap the sequence order within the input data 2 and generate the swapped data 30.

[0038] The period of the RSC code is the bit length of the repeating portion of the output data output by the convolutional encoder 41 that executes this RSC code, when input data 2 in which the first bit is 1 and the second bit onward is 0 is input to the convolutional encoder 41, and the portion from a predetermined bit onward repeats at a predetermined period.

[0039] Figure 4 is a table showing an example of the order of roots and the period of the RSC code corresponding to several polynomials. Figure 5 is a table showing an example of the correspondence between the generating polynomial of the RSC code and the vector representation of the element for each power representation of the element of the Galois field generated by the generating polynomial. More specifically, the elements of the Galois field are generated by the remainder from the generating polynomial.

[0040] In one embodiment, the case where (37 / 21)8 is selected as the RSC code will be described based on Figures 4 and 5. (37 / 21)8 is a polynomial that represents the configuration of a feedforward connection, which is 37 in octal, or 11111 in binary, and is 1+x+x 2 +x 3 +x 4 Therefore, the polynomial that represents the individuality of the feedback connection is 1+x, which is expressed as 21 in octal, or 10001 in binary. 4 This indicates that something is the case.

[0041] Referring to Figure 5, we will explain the case in which a polynomial g(x) is divisible by a generating polynomial such that there are no combinations of at least three distinct polynomials whose sum is zero among the elements of the Galois field generated by that generating polynomial. Among the elements of the Galois field (more precisely, the extended Galois field) generated by the generating polynomial in Figure 5, for example, 1+x+x 2 The elements generated from include 1, x, and 1+x. Here, adding 1, x, and 1+x yields 0, so the above condition for the polynomial g(x) is not satisfied. Similarly, 1+x+x 4 The elements generated from also include 1, x, and 1+x. Here, adding 1, x, and 1+x gives 0, so the above condition of the polynomial g(x) is not satisfied. Also, 1+x 2 +x 3 The elements generated from this include 1 and x 2 And, 1+x 2Since it contains and the sum of the three elements is 0, the above condition for polynomial g(x) is not satisfied. On the other hand, no matter which combination of three elements is extracted from the elements generated from 1+x+x2+x3+x4 and added together, 0 cannot be obtained, so the above condition for polynomial g(x) is satisfied. Note that there is only one element generated from 1+x, and therefore it is not possible to choose three different elements, so the above condition for polynomial g(x) is satisfied.

[0042] Figure 6 shows the Hamming weights w of the codeword c(x) when (37 / 21)8 is selected as the RSC code. H This table shows an example of (c(x)), the common polynomial a(x), the input bit sequence b(x) as swap data 30, and the output bit sequence h(x) as parity stream 420 (also called "parity check bitstream"). In the first row of Figure 6, "b(x)" represents the input bit sequence, "h(x)" represents the output bit sequence, and "w H "(c(x))" represents the Hamming weight of the RSC code output c(x). Also, "a(x)" simultaneously satisfies "b(x)=a(x)g(x)" and "h(x)=a(x)f(x)". Here, "f(x)" is a function corresponding to the feedforward connection of the delays 431, 432, and 433 in the convolutional encoders 41 and 42, and "g(x)" is a function corresponding to the feedback connection of the delays 431, 432, and 433 in the convolutional encoders 41 and 42. In Figure 6, in each cell from the second row and below and from the second column below, the integer inside the parentheses represents the degree of the term in the polynomial whose coefficient is equal to 1. For example, "(0,1)" represents "x 0 +x 1 " represents "1+x", and "(0,1,4,5)" represents "x 0 +x 1 +x 4 +x 5 That is, "1+x+x 4 +x 5 This represents ".

[0043] Let's look at an example of how to select a polynomial f(x) that represents the configuration of a feedforward connection, using a specific example. Consider a case where there are two candidate polynomials g(x) that represent the configuration of a feedback connection. Here, the first candidate is g1(x) = 1 + x + x 2 Therefore, the second candidate is g2(x)=1+x 4 Therefore, in this case, we select the second candidate g2(x), which simplifies the design of interleaver 3, as the polynomial g(x) representing the configuration of the feedback connection. In this case, there are four candidate polynomials f(x) that satisfy the conditions. Here, the first candidate is f1(x) = 1 + x + x 4 Therefore, the second candidate is f2(x)=1+x 2 +x 4 Therefore, the third candidate is f3(x)=1+x 3 +x 4 Therefore, the fourth candidate is f4(x)=1+x+x 2 +x 3 +x 4 Therefore, among these candidates, we select f4(x) as the most suitable candidate. The reason is that the following equation "Equation 5" holds true.

[0044]

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[0045] When the length of input data 2 is N and the period of the RSC code is τ, PM is an intermediate matrix Π of τ x τ, divided by N / τ in the column direction. 2 It is generated by connecting multiple times. For example, when N=32 and τ=4, PM is generated as shown in equation "Equation 6" below.

[0046]

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[0047] Here, each element of the intermediate matrix Π is an integer from 0 to τ-1. Also, each column of the intermediate matrix Π contains exactly one integer from 0 to τ-1. Such an intermediate matrix Π is generated, for example, as shown in equation "Equation 7" or "Equation 8" below.

[0048]

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[0049]

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[0050] After step S02 in Figure 3, step S03 is executed. In step S03, the coset design unit 523 in Figure 2 designs the cosets. More specifically, the coset design unit 523 divides the input data 2 into a number of disjoint intermediate sets equal to the period τ of the RSC code. At this time, elements that have the same remainder when the order of the sequence inside the input data 2 is divided by the period τ are assigned to the same intermediate set. When the length of the input data 2 is a multiple of the period τ, the number of elements in each intermediate set will be the same. Then, by appropriately selecting integers disjoint from the period τ and rearranging the elements of each intermediate set in an order equal to the remainder when the product of the selected integer multiplied by a coefficient that increments from 1 is divided by the number of elements in the intermediate set, a coset equal to the period τ is generated.

[0051] For example, when the length of input data 2 is 32 bits and the period τ of the RSC code is equal to 4, a total of 4 intermediate sets are generated. When input data 2 is represented as {0,1,···,31} using the order of its internal sequence, the four intermediate sets M are generated. 0 M 1 M 2 M 3 This can be expressed as follows, using the order of the sequences within input data 2: M 0 ={0,4,8,12,16,20,24,28} M 1 ={1,5,9,13,17,21,25,29} M 2 ={2,6,10,14,18,22,26,30} M 3 ={3,7,11,15,19,23,27,31}

[0052] When we choose 3 as an integer relatively prime to the period τ, the intermediate set M 0 M 1 M 2 M 3 By applying the above sorting process, we obtain four residue classes C. 0 , C 1 , C 2 , C 3 It is generated as follows: C 0 ={0,12,24,4,16,28,8,20} C 1 ={1,13,25,5,17,29,9,21} C 2 ={2,14,26,6,18,30,10,22} C 3 ={3,15,27,7,19,31,11,23}

[0053] The interleaver 3 designed as described above is, for convenience, called the residue class interleaver. The above residue class C 0 , C 1 , C 2 , C 3 When the order of the sequences within the input data 2, which is converted to the above, is rearranged using a residue class interleaver designed as shown in equations "6" and "7" above, the rearranged data 30 is generated as follows. Swap data 30 = {0,1,2,3,13,14,15,12,26,27,24,25,7,4,5,6,16,17,18,19,29,30,31,28,10,11,8,9,23,20,21,22}

[0054] As an example, the inventors have confirmed through calculations that if the Hamming weight of the input bit sequence b(x) is 2, the Hamming weight of the input data 2 input to the interleaver 3 will be 14 or more, the Hamming weight of the swapped data 30 output by the interleaver 3 will also be 14 or more, and as a result, the Hamming weight of the RSC code output c(x) will be 30 or more.

[0055] As another example, if the Hamming weight of the input bit sequence b(x) is 4, then one of the following three patterns of interleaver 3 can be obtained.

[0056] In the first pattern, the first and second bits of input data 2 are swapped into the same residue class. In the first pattern, the input bit sequence b4(x) with a Hamming weight of 4 and the swapped bit sequence b'4(x) output by the interleaver 3 that receives this input bit sequence b4(x) are expressed as shown in equation "Equation 9" below.

[0057]

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[0058] In the second pattern, the first and third bits of input data 2 are swapped to the same residue class. In the second pattern, the input bit sequence b4(x) with a Hamming weight of 4 and the swapped bit sequence b'4(x) output by the interleaver 3 that receives this input bit sequence b4(x) can be expressed as shown in equation "Equation 10" below.

[0059]

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[0060] In the third pattern, the first and last bits of input data 2 are swapped to the same residue class. In the third pattern, the input bit sequence b4(x) with a Hamming weight of 4 and the swapped bit sequence b'4(x) output by the interleaver 3 that receives this input bit sequence b4(x) are expressed as shown in equation "Equation 11" below.

[0061]

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[0062] The swap bit sequence b'4(x) in the first to third patterns described above can be generalized as shown in equation "Equation 12" below.

[0063]

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[0064] After step S03 in Figure 3, step S04 is executed. In step S04, the output unit 524 in Figure 2 outputs the turbo code. More specifically, it outputs to the outside information representing the turbo code designed based on the RSC code selected in step S01 and the residue interleaver designed based on the PM designed in step S02 and the residues designed in step S03. The output unit 524 in Figure 2 may also output to the outside information representing the designed turbo code by controlling the communication device 54.

[0065] Once step S04 in Figure 3 is completed, the process in the flowchart in Figure 3 is finished.

[0066] Thus, in this disclosure, the convolutional encoders 41 and 42 are designed in step S01 of Figure 3, and then the interleaver 3 is designed in steps S02 and S03 of Figure 3. Note that this order is the reverse of that in related technologies.

[0067] (Computer simulation, part 1) Figure 8 is a graph showing an example of the results of a computer simulation performed to verify the effectiveness of an RSC code according to one embodiment. The graphs in Figure 8 include a total of five graphs G11, G12, G13, G14, and G15. Graph G11 shows the performance of a turbo code using an RSC code according to one embodiment. The generator polynomial of the RSC code in graph G11 is (37 / 21)8. Graph G12 shows the error rate bound of an RSC code based on a transfer function according to the prior art. Graph G13 shows the performance of a turbo code using a transformation function according to the related art when κ=1 in equation "Equation 13" below. Graph G14 shows the performance of a turbo code using a transformation function according to the related art when κ=2 in equation "Equation 13" below. Graph G15 shows the performance of a turbo code using a transformation function according to the related art when κ=3 in equation "Equation 13" below. In graphs G11 through G15, the horizontal axis represents the energy-to-noise density ratio per bit in dB (decibels), and the vertical axis represents the BER (Bit Error Rate). Also, in graphs G11 through G15, the bit length N of input data 2 is 1024 bits.

[0068]

number

[0069] The above equation "Equation 13" represents the evaluation of the error rate. In equation "Equation 13", "N" represents the bit length per frame of the input data 2 before encoding with RSC coding. "Pb(κ)" represents the average bit error rate in the received signal before decoding when N bits of input data 2 are transmitted using RSC coding. Strictly speaking, the upper limit of the range of "d" should be set to infinity, but as a practical approximation to reduce computational complexity, the upper limit is set to "d" here. free The function "Q" represents the probability of an error occurring. Also, the set of common polynomials a(x) is "A' c (d) is the set of common polynomials a(x) that satisfy the condition that the Hamming weights of the output bit sequence h(x) and the Hamming weights of the input bit sequence b(x) fall within a given range.

[0070] As can be seen from the graph in Figure 8, although there is some difference between the RSC code according to one embodiment and the conversion function according to the related technology, they converge to the same value as the energy-to-noise density ratio per bit increases. This means that the approximation used in the RSC code according to one embodiment has sufficient accuracy.

[0071] (Computer simulation, part 2) Figure 9 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. The graph in Figure 9 includes a total of three graphs G21, G22, and G23. Graph G21 shows an example of the performance of a turbo code using a residue class interleaver according to one embodiment. Graph G22 shows an example of the performance of a turbo code using an S-random interleaver. Graph G23 shows an example of the performance of a turbo code using a QPP interleaver. Common to graphs G21, G22, and G23, the horizontal axis represents the energy-to-noise density ratio per bit in dB, and the vertical axis represents the BER. Also common to graphs G21, G22, and G23, the bit length N of the input data 2 is 1024 bits.

[0072] As can be seen from the graph in Figure 9, when the bit length N of the input data 2 is a relatively long 1024 bits, and the energy-to-noise density ratio per bit is 1.2 dB or higher, the BER of the turbo code using the residue class interleaver according to one embodiment is significantly lower than the BER of the turbo code using the S-random interleaver or QPP interleaver. From this, it was confirmed that, at least under the above conditions, the performance of the turbo code using the residue class interleaver according to one embodiment is significantly higher than the performance of the turbo code using the S-random interleaver or QPP interleaver.

[0073] Figure 10 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. The graph in Figure 10 includes a total of two graphs, G31 and G32. Graph G31 shows an example of the performance of a turbo code using a residue class interleaver according to one embodiment. Graph G32 shows an example of the performance of a turbo code using an S-random interleaver. In both graphs G31 and G32, the horizontal axis represents the energy-to-noise density ratio per bit in dB, and the vertical axis represents the BER. Also in both graphs G31 and G32, the bit length N of the input data 2 is 2048 bits.

[0074] As can be seen from the graph in Figure 10, when the bit length N of the input data 2 is 2048 bits, which is longer than in the case of Figure 9, and the energy-to-noise density ratio per bit is 0.6 dB or higher, the BER of the turbo code using the residue class interleaver according to one embodiment is significantly lower than the BER of the turbo code using the S-random interleaver. From this, it was confirmed that, at least under the above conditions, the performance of the turbo code using the residue class interleaver according to one embodiment is significantly higher than the performance of the turbo code using the S-random interleaver.

[0075] Figure 11 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. The graph in Figure 11 includes a total of two graphs, G41 and G42. Graph G41 shows an example of the performance of a turbo code using a residue class interleaver according to one embodiment. Graph G42 shows an example of the performance of a turbo code using an S-random interleaver. In both graphs G41 and G42, the horizontal axis represents the energy-to-noise density ratio per bit in dB, and the vertical axis represents the BER. Also in both graphs G41 and G42, the bit length N of the input data 2 is 4096 bits.

[0076] As can be seen from the graph in Figure 11, when the bit length N of the input data 2 is 4096 bits, which is longer than in the case of Figure 10, and the energy-to-noise density ratio per bit is 0.4 dB or higher, the BER of the turbo code using the residue class interleaver according to one embodiment is significantly lower than the BER of the turbo code using the S-random interleaver. From this, it was confirmed that, at least under the above conditions, the performance of the turbo code using the residue class interleaver according to one embodiment is significantly higher than the performance of the turbo code using the S-random interleaver.

[0077] Figure 12 is a graph showing an example of the results of a computer simulation of the performance of a turbo code designed by a turbo code design method according to one embodiment. The graphs in Figure 12 include a total of three graphs G51, G52, and G53. Graph G51 shows an example of the performance of a turbo code using a residue class interleaver according to one embodiment. Graph G52 shows an example of the performance of a turbo code using an S-random interleaver. Graph G53 shows an example of the performance of a turbo code using a QPP interleaver. Common to graphs G51, G52, and G53, the horizontal axis represents the energy-to-noise density ratio per bit in dB, and the vertical axis represents the BER. Also common to graphs G51, G52, and G53, the bit length N of the input data 2 is 8192 bits.

[0078] As can be seen from the graph in Figure 12, when the bit length N of the input data 2 is 8192 bits, which is longer than in the case of Figure 11, and the energy-to-noise density ratio per bit is 0.4 dB or less, the BER of the turbo code using the residue class interleaver according to one embodiment is significantly lower than the BER of the turbo code using the S-random interleaver. From this, it was confirmed that, at least under the above conditions, the performance of the turbo code using the residue class interleaver according to one embodiment is significantly higher than the performance of the turbo code using the S-random interleaver.

[0079] As described above, the turbo code using the residue class interleaver designed using the turbo code design method, turbo code design apparatus 5, and turbo code design program of this disclosure has higher performance than the turbo code using the S-Random interleaver or QPP interleaver, at least under the conditions of the above simulation. Furthermore, the inventors have confirmed through computer simulation that in the turbo code according to one embodiment, when different values ​​are set for each residue class as depth D and bias R, better performance than the turbo code using the S-Random interleaver can be obtained even when the bit length N of the input data 2 is extended to 16832 bits.

[0080] (Variation 1) In the embodiment described above, as shown in Figure 1A, a configuration was described in which the turbo encoder 1 comprises one interleaver 3 and two convolutional encoders 41 and 42. As a variation of this configuration, as shown in Figure 13, the turbo encoder 1 may comprise two interleavers 3A and 3B and three convolutional encoders 41, 42A, and 42B.

[0081] The first convolutional encoder 41 in Figure 13 is configured similarly to the first convolutional encoder 41 in Figures 1A and 1B, and is supplied with input data 2 to output a first parity stream 410. The first parity stream 410 in Figure 13 is the same as the first parity stream 410 in Figures 1A and 1B.

[0082] The first interleaver 3A in Figure 13 is configured similarly to the interleaver 3 in Figure 1A, and is supplied with input data 2 to output the first swapped data 30A. The first swapped data 30A in Figure 13 is the same as the swapped data 30 in Figures 1A and 1B. The second convolutional encoder 42A in Figure 13 is configured similarly to the second convolutional encoder 42 in Figure 1A, and is supplied with the first swapped data 30A to output the second parity stream 420A. The second parity stream 420A in Figure 13 is the same as the second parity stream 420 in Figures 1A and 1B.

[0083] In Figure 13, the second interleaver 3B is supplied with input data 2 and outputs second swapping data 30B based on a different rule than that of the first interleaver 3A in Figure 13. The second swapping data 30B in Figure 13 is different from the first swapping data 30A in Figure 13. The third convolutional encoder 42B in Figure 13 is configured similarly to the second convolutional encoder 42A in Figure 13 and is supplied with second swapping data 30B to output a third parity stream 420B. The third parity stream 420B in Figure 13 is different from the second parity stream 420A in Figure 13.

[0084] The turbo encoder 1 in Figure 13, like the turbo encoder 1 in Figure 1A, further includes a coupler (not shown). This coupler generates output data by turbo encoding the input data 2 based on the input data 2, a first parity stream 410, a second parity stream 420A, and a third parity stream 420B. The coupler may generate intermediate data by partially decimating and multiplexing the parity streams 410, 420A, and 420B, and then generate output data by multiplexing the intermediate data with the input data 2.

[0085] When the interleavers 3A and 3B in Figure 13 are not distinguished, they are collectively referred to as interleaver 3. When the swapping data 30A and 30B in Figure 13 are not distinguished, they are collectively referred to as swapping data 30. When the convolutional encoders 42A and 42B in Figure 13 are not distinguished, they are collectively referred to as convolutional encoder 42. When the parity streams 420A and 420B in Figure 13 are not distinguished, they are collectively referred to as parity stream 420. Even in this generalized case, the relationship between interleaver 3, swapping data 30, convolutional encoder 42, and parity stream 420 remains the same as explained with reference to Figure 1B.

[0086] As a further modification of the configuration shown in Figure 13, additional sets of interleavers 3 and convolutional encoders 42 may be added in parallel.

[0087] The invention made by the inventor has been described in detail based on embodiments above, but it goes without saying that the present invention is not limited to these embodiments and can be modified in various ways without departing from its essence. Furthermore, the features described in the embodiments can be freely combined within a range that does not contradict the technical aspects.

[0088] This invention claims priority based on Japanese Patent Application No. 2022-182371, filed on 15 November 2022, and incorporates all of its disclosures herein.

Claims

1. A turbo code design method for designing turbo codes, The turbocoder that performs the turbocode is: A first convolutional encoder generates a parity stream of input data as a first parity stream using a predetermined RSC (Recursive Systematic Convolutional) code, An interleaver generates swapped data by rearranging the order of sequences within the aforementioned input data according to a first rule, A second convolutional encoder that generates the parity stream of the swapped data as a second parity stream using the RSC code, Equipped with, From among the elements of the Galois field generated by the generating polynomial, select the polynomial that represents the RSC code, Designing the first rule of the interleaver based on the RSC code, Outputting information representing the designed turbo code to the outside Includes, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. Each of the feedforward polynomial and the feedback polynomial is either a single polynomial selected from the elements of the Galois field, or the product of multiple polynomials selected from the elements of the Galois field. The second convolutional encoder described above is: Multiple delay devices connected in series, A group of first adders feedforward connects some of the outputs of the plurality of delayers to the output of the second convolutional encoder, A second group of adders that feeds back some of the outputs of the aforementioned plurality of delay devices to the inputs of the second convolutional encoder, Equipped with, Selecting the polynomial representing the RSC code means that The feedback polynomial g(x) representing the configuration of the feedback connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder becomes smaller than a predetermined first threshold only when the swapping data input to the second convolutional encoder satisfies predetermined conditions, The feedforward polynomial f(x) representing the configuration of the feedforward connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder is greater than a predetermined second threshold only when the swapping data input to the second convolutional encoder satisfies the predetermined conditions. Includes, The aforementioned predetermined conditions are: The swapped data is a value in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code, or each of the swapped data is the sum of multiple values ​​in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code. The feedback polynomial g(x) is divisible by a predetermined generating polynomial, and there are no combinations of at least three polynomials that are distinct from each other and whose sum is zero, among the elements contained in the Galois field generated by the predetermined generating polynomial. including Turbo code design method.

2. In the turbo code design method according to claim 1, The first threshold value is a value calculated based on the desired free distance in the turbo code. Turbo code design method.

3. In the turbo code design method according to claim 2, The first threshold is 42. Turbo code design method.

4. In the turbo code design method according to any one of claims 1 to 3, The configuration of the first convolutional encoder is the same as the configuration of the second convolutional encoder. Turbo code design method.

5. In the turbo code design method according to claim 4, Designing the first rule of the interleaver is Based on the period of the RSC code, a PM (Permutation Matrix) is designed that represents the correspondence in the order of the internal sequences between the input data and the swapped data. Based on the period of the RSC code, the input data is divided to generate multiple sets of disjoint entities as multiple residue classes. Includes, The period of the RSC code is the bit length of the cyclic portion when the output data of the RSC code, which is input data in which the first bit is 1 and the second bit onward is 0, cycles at a predetermined period from a predetermined bit onward. Turbo code design method.

6. In the turbo code design method according to claim 5, Designing the aforementioned PM is When the period of the RSC code is τ, a first matrix of τ x τ is generated in which each element is an integer from 0 to τ-1, and each column contains exactly one integer from 0 to τ-1. The first matrix is ​​repeatedly concatenated in the column direction based on the period and the length of the input data to generate a second matrix, which is the PM. including Turbo code design method.

7. In the turbo code design method according to claim 6, Generating the aforementioned plurality of sets as the aforementioned plurality of cosets is, The input data is divided into a number of disjoint intermediate sets equal to the period of the RSC code, In each of the aforementioned intermediate sets, the order of several elements is rearranged to generate the aforementioned multiple cosets. Includes, The division described above means The process involves assigning elements included in the input data that, when their sequence order within the input data is divided by the period, have the same remainder, to the same intermediate set among the multiple intermediate sets. Includes, Reversing the order mentioned above means In each of the aforementioned intermediate sets, an integer relatively prime to the period is provided, Prepare a coefficient that increments from 1, Rearranging the elements of each of the multiple intermediate sets in an order equal to the remainder obtained by dividing the product of the integer multiplied by the coefficient by the number of elements in each of the multiple intermediate sets. including Turbo code design method.

8. In the turbo code design method according to claim 1, The bit length of the input data is 16384 bits or less. Turbo code design method.

9. In the turbo code design method according to claim 1, The bit length of the input data is 8192 bits or less. Turbo code design method.

10. In the turbo code design method according to claim 1, The bit length of the input data is 1024 bits or less. Turbo code design method.

11. In the turbo code design method according to claim 1, When the Hamming weight of the input bit sequence input to the second convolutional encoder via a feedback connection is 2, the Hamming weight of the input data input to the interleaver is 14 or greater, and the Hamming weight of the swapped data output by the interleaver is 14 or greater. Turbo code design method.

12. In the turbo code design method according to claim 1, The turbocoder described above is A second interleaver, separate from the first interleaver, rearranges the sequence order within the input data based on a second rule separate from the first rule, thereby generating a second rearrangement data separate from the first rearrangement data. A third convolutional encoder that generates the parity stream of the second swapped data as a third parity stream using the RSC code, Furthermore, Design the second rule of the second interleaver based on the RSC code. Includes Turbo code design method.

13. A turbo code design device for designing turbo codes, The turbocoder that performs the turbocode is: A first convolutional encoder that generates a parity stream of input data as a first parity stream using a predetermined RSC code, An interleaver generates swapped data by rearranging the order of sequences within the aforementioned input data according to a first rule, A second convolutional encoder that generates the parity stream of the swapped data as a second parity stream using the RSC code, Equipped with, An RSC code selection unit that selects a polynomial representing the RSC code from among the elements of the Galois field generated by the generating polynomial, A PM design unit designs a PM (Permutation Matrix) that represents the correspondence in the order of the internal sequence between the input data and the swapped data, based on the period of the RSC code. A residue class design unit designs a second rule for dividing the input data based on the period of the RSC code and generating a plurality of disjoint sets as a plurality of residue classes, An output unit that outputs information representing the designed turbo code to the outside. Equipped with, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. Each of the feedforward polynomial and the feedback polynomial is either a single polynomial selected from the elements of the Galois field, or the product of multiple polynomials selected from the elements of the Galois field. The period of the RSC code is the bit length of the cyclic portion when the output data of the RSC code, which is input data in which the first bit is 1 and the second bit onward is 0, cycles at a predetermined period from a predetermined bit onward. The second convolutional encoder described above is: Multiple delay devices connected in series, A group of first adders feedforward connects some of the outputs of the plurality of delayers to the output of the second convolutional encoder, A second group of adders that feeds back some of the outputs of the aforementioned plurality of delay devices to the inputs of the second convolutional encoder, Equipped with, The RSC code selection unit is Only when the swapping data input to the second convolutional encoder satisfies predetermined conditions, a feedback polynomial g(x) representing the configuration of the feedback connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder becomes smaller than a predetermined first threshold. Only when the swapping data input to the second convolutional encoder satisfies the predetermined conditions, a feedforward polynomial f(x) representing the configuration of the feedforward connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder is greater than a predetermined second threshold. The aforementioned predetermined conditions are: The swapped data is a value in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code, or each of the swapped data is the sum of multiple values ​​in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code. The feedback polynomial g(x) is divisible by a predetermined generating polynomial, and there are no combinations of at least three polynomials that are distinct from each other and whose sum is zero, among the elements contained in the Galois field generated by the predetermined generating polynomial. including Turbo code design device.

14. A recording medium for storing a turbo code design program that enables processing for designing turbo codes by having it executed by an arithmetic unit, The turbocoder that performs the turbocode is: A first convolutional encoder that generates a parity stream of input data as a first parity stream using a predetermined RSC code, An interleaver generates swapped data by rearranging the order of sequences within the aforementioned input data according to a first rule, A second convolutional encoder that generates the parity stream of the swapped data as a second parity stream using the RSC code, Equipped with, The aforementioned process is, From among the elements of the Galois field generated by the generating polynomial, select the polynomial that represents the RSC code, Designing the first rule of the interleaver based on the RSC code, Outputting information representing the designed turbo code to the outside Includes, The polynomial representing the RSC code includes a feedforward polynomial representing a feedforward connection and a feedback polynomial representing a feedback connection. Each of the feedforward polynomial and the feedback polynomial is either a single polynomial selected from the elements of the Galois field, or the product of multiple polynomials selected from the elements of the Galois field. The second convolutional encoder described above is: Multiple delay devices connected in series, A group of first adders feedforward connects some of the outputs of the plurality of delayers to the output of the second convolutional encoder, A second group of adders that feeds back some of the outputs of the aforementioned plurality of delay devices to the inputs of the second convolutional encoder, Equipped with, Selecting the polynomial representing the RSC code means that The feedback polynomial g(x) representing the configuration of the feedback connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder becomes smaller than a predetermined first threshold only when the swapping data input to the second convolutional encoder satisfies predetermined conditions, The feedforward polynomial f(x) representing the configuration of the feedforward connection is selected such that the Hamming weight of the parity stream output by the second convolutional encoder is greater than a predetermined second threshold only when the swapping data input to the second convolutional encoder satisfies the predetermined conditions. Includes, The aforementioned predetermined conditions are: The swapped data is a value in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code, or each of the swapped data is the sum of multiple values ​​in the binary representation of the swapped data where the distance between digits equal in value is an integer multiple of the period of the RSC code. The feedback polynomial g(x) is divisible by a predetermined generating polynomial, and there are no combinations of at least three polynomials that are distinct from each other and whose sum is zero, among the elements contained in the Galois field generated by the predetermined generating polynomial. including A recording medium for storing turbo code design programs.

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