modulator

Abstract

To provide a modulator capable of preventing generation of an inter-stage loading effect when using a passive type integrator.SOLUTION: In a modulator 1, a passive type integrator 2 comprises: a sampling capacity CS; an integration capacity CI; and a plurality of switches φ1, φ2, φ21, and φ22 that is used for changing a connection state between an input terminal, each of capacities CS and CI, and output terminals. Then, a sampling phase performing sampling of the input voltage, an integration phase for distributing an electric charge of the sampling capacity CS with the integration capacity CI, and an output phase that outputs a terminal voltage of the sampling capacity CS from the output terminal in a state where the integration capacity CI is separated from the output terminal are executed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a modulator equipped with a passive integrator. [Background technology]

[0002] Passive integrators do not use operational amplifiers, and therefore consume less power than active integrators. Non-patent document 1 discloses an example of a modulator equipped with a passive integrator. In a passive integrator, summation is performed by charge distribution between the sampling capacitance Cs and the integrating capacitance Ci. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS,VOL.61,NO.2,FEBRUARY 2014,Low-Power Delta sigma Modulators Using SC PassiveFilters in 65nm CMOS Ali Fazli Yeknami, Fahad Qazi, and Atila Alvandpour [Non-Patent Document 2] IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS,VOL.67,NO.2,FEBRUARY 2020 Passive SCModulator Based on PipelinedCharge-Sharing Rotation in 28nm CMOS Hongying Wang,Filippo Schembari,,and Robert Bogdan Staszewski [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] As shown in Non-Patent Document 1, in a configuration where passive integrators are connected in series in two stages, at the timing of transmitting the output of the first stage to the input of the second stage, the charge accumulated in the sampling capacitance Cs of the second stage moves to the integrating capacitance Ci of the first stage, forming a feedback path from the second stage to the first stage. Due to this feedback path, there is a problem that the performance of noise shaping deteriorates. This is called the inter-stage loading effect. Hereinafter, the inter-stage loading effect may be referred to as ILE.

[0005] Also, in the configuration disclosed in Non-Patent Document 2, when the second-stage integration is performed by the technique of charge-sharing rotation, since the integrating capacitance CH1 of the first stage is disconnected, a secondary integrator can be realized without causing ILE. However, when a passive circuit is connected to the subsequent stage, since it is directly connected to the integrating capacitance, there is a problem that ILE occurs.

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide a modulator that can prevent the occurrence of the inter-stage loading effect when using a passive integrator.

Means for Solving the Problems

[0007] According to the modulator described in claim 1, the passive integrator includes one or more sampling capacitances (C S , C Sa , C Sb , C Sa1 , C Sa2 , C Sb1 , C Sb2 、C S1 、C S2 ), one or more integrating capacitances (C I , C I1 , C I2 ), an input terminal, and a plurality of switches (φ1, φ used to change the connection state between the respective capacitances and the output terminal1d , φ 1ad , φ 1bd , φ2, φ 21 , φ 22 , φ 21a , φ 22a , φ 21b , φ 22b , φ 23 , φ 23a , φ 23b It includes a φ3 capacitor. It then performs a sampling phase in which it samples the input voltage by controlling the ON / OFF state of multiple switches, an integration phase in which it distributes the charge of the sampling capacitor with the integrating capacitor, and an output phase in which it outputs the terminal voltage of the sampling capacitor from the output terminal with the integrating capacitor disconnected from the output terminal.

[0008] During the output phase, the integrated capacitor is disconnected from the output terminal, preventing the charge from the integrated capacitor from moving to the next stage circuit connected to the modulator's output terminal. Therefore, ILE (Intense Load Emission) can be prevented. [Brief explanation of the drawing]

[0009] [Figure 1] This is the first embodiment, and is a circuit diagram showing an integrator. [Figure 2] Diagram showing the transfer function of an integrator [Figure 3] Integrator operation timing chart [Figure 4] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 5] Diagram showing the ON / OFF state of each switch during the sampling phase. [Figure 6] Diagram showing the ON / OFF state of each switch during the integration phase. [Figure 7] Diagram showing the ON / OFF state of each switch during the output phase. [Figure 8] Functional block diagram showing the configuration of the modulator [Figure 9] This is a second embodiment, and is a circuit diagram showing the configuration of the modulator. [Figure 10]This is a third embodiment, and is a circuit diagram showing the configuration of the modulator. [Figure 11] This is the fourth embodiment, and is a circuit diagram showing an integrator. [Figure 12] Diagram showing the transfer function of an integrator [Figure 13] Integrator operation timing chart [Figure 14] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 15] Diagram showing the ON / OFF state of each switch during the sampling phase. [Figure 16] Diagram showing the ON / OFF state of each switch during the integration phase (1). [Figure 17] Diagram showing the ON / OFF state of each switch during the integration phase (2). [Figure 18] Diagram showing the ON / OFF state of each switch during the output phase. [Figure 19] This is the fifth embodiment, and is a circuit diagram showing an integrator. [Figure 20] Diagram showing the transfer function of an integrator [Figure 21] Integrator operation timing chart [Figure 22] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 23] Diagram showing the ON / OFF state of each switch during the sampling phase (side A) and the charge holding phase (side B). [Figure 24] Diagram showing the ON / OFF states of each switch during the integration phase (side A) and the output phase (side B). [Figure 25] Diagram showing the ON / OFF state of each switch during the charge holding phase (side A) and the sampling phase (side B). [Figure 26] Diagram showing the ON / OFF states of each switch during the output phase (side A) and the integration phase (side B). [Figure 27] This is the sixth embodiment, and is a circuit diagram showing the configuration of the modulator. [Figure 28] Integrator operation timing chart [Figure 29]This is the seventh embodiment, and is a circuit diagram showing the configuration of the modulator. [Figure 30] This is the eighth embodiment, and is a circuit diagram showing an integrator. [Figure 31] Diagram showing the transfer function of an integrator [Figure 32] Integrator operation timing chart [Figure 33] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 34] Diagram showing the ON / OFF states of each switch during the sampling phase (side A) and the quadratic integration phase (side B). [Figure 35] Diagram showing the ON / OFF states of each switch during the linear integration phase (side A) and the output phase (side B). [Figure 36] Diagram showing the ON / OFF state of each switch during the quadratic integration phase (side A) and the sampling phase (side B). [Figure 37] Diagram showing the ON / OFF states of each switch during the output phase (side A) and the first-order integration phase (side B). [Figure 38] This is the ninth embodiment, a circuit diagram showing an integrator. [Figure 39] Integrator operation timing chart [Figure 40] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 41] Diagram showing the ON / OFF state of each switch during the sampling phase. [Figure 42] Diagram showing the ON / OFF state of each switch during the first integration phase. [Figure 43] Diagram showing the ON / OFF state of each switch during the quadratic integration phase. [Figure 44] Diagram showing the ON / OFF state of each switch during the output phase. [Figure 45] This is the tenth embodiment, and it is a circuit diagram showing a modulator. [Figure 46] This is the 11th embodiment, and it is a circuit diagram showing a modulator. [Figure 47] This is the twelfth embodiment, and is a circuit diagram showing an integrator. [Figure 48] Integrator operation timing chart [Figure 49] Diagram showing the ON / OFF state of each switch during the reset phase. [Figure 50] Diagram showing the ON / OFF states of each switch during the sampling phase (side A) and the quadratic integration phase (side B). [Figure 51] Diagram showing the ON / OFF states of each switch during the linear integration phase (side A) and the output phase (side B). [Figure 52] Diagram showing the ON / OFF state of each switch during the quadratic integration phase (side A) and the sampling phase (side B). [Figure 53] Diagram showing the ON / OFF states of each switch during the output phase (side A) and the first-order integration phase (side B). [Figure 54] This is the 13th embodiment, and is a circuit diagram showing a modulator. [Figure 55] This is the 14th embodiment, and is a circuit diagram showing a modulator. [Modes for carrying out the invention]

[0010] (First Embodiment) As shown in Figure 8, the ΔΣ modulator 1 of this embodiment includes a passive integrator 2 and a quantizer 3, and the output of the quantizer 3 is fed back to the input side of the integrator 2 via a D / A converter (DAC) 4. The subtractor 5 subtracts the input voltage from the voltage output by the DAC 4, and the value integrated by the integrator 2 is input to the quantizer 3. This embodiment has a distinctive configuration of the integrator 2, which will be described below.

[0011] As shown in Figure 1, the integrator 2 has a switch φ connected between the input terminal and the output terminal. 1d , sampling capacity C S and switch φ 22 Series circuit, switch φ 1d and sampling capacity C S A switch φ2 and sampling capacitance C are connected between the common connection point and the common voltage terminal. S and switch φ22 A switch φ1 is connected between the common connection point and the common voltage terminal, and a switch φ is connected in parallel to this switch φ1. 21 and integral capacitance C I It is equipped with a series circuit. The ON / OFF control of each switch is performed by a control circuit (not shown). The transfer function of integrator 2 is shown in Figure 2.

[0012] The following diagram shows the transitions in the operation of integrator 2, with the paths created by turning each switch ON indicated by thick lines. The operation phase consists of three steps, repeated after reset: (1) sampling, (2) integration, and (3) output. Note that the names of each switch and the signals controlling their ON / OFF states are the same. Also, switch φ 1d Regarding the switch φ1, normally φ 1d The name is different because it imparts a slight delay compared to φ1, but for convenience, only φ1 is shown in Figure 3. <Reset Phase> As shown in Figure 4, with all switches turned ON, capacitance C S and C I The potential across both ends is the common voltage V CM I'll do that. <Sampling Phase> As shown in Figure 5, switch φ 1d And turn φ1 ON, sampling capacitance C S Input voltage V IN Charge it with this. <Integration Phase> As shown in Figure 6, switches φ2 and φ 21 Turn ON the charge sampling capacitor C S and the integral capacity C I Distribute it to them. <Output Phase> As shown in Figure 7, switches φ2 and φ 22 Turn ON the sampling capacitance C S The terminal voltage is V from the output terminal. OUT Output as follows.

[0013] As described above, according to this embodiment, in the modulator 1, the passive integrator 2 has a sampling capacitance C S And the integrating capacity C I And, input terminals, each capacitance C S , C I And multiple switches φ1, φ2, φ used to change the connection state between output terminals 21 and φ 22 It is equipped with the following. And each switch φ1~φ 22 The sampling phase controls the ON / OFF state to sample the input voltage, and the sampling capacitance C is controlled. S The charge of the integral capacitor C I The integral phase is distributed, and the integral capacitance C I With the output terminal disconnected, the sampling capacitance C S The output phase is performed, in which the terminal voltage of is output from the output terminal. That is, in the output phase, the integral capacitance C I Since it is disconnected from the output terminal, ILE can be prevented even if the subsequent circuit is a passive circuit.

[0014] (Second Embodiment) In the following description, parts identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted, while the differences are described. As shown in Figure 9, the modulator 6 of the second embodiment is the same as the configuration of the first embodiment with the addition of an adder 7. Switches constituting the adder 7 that are turned ON / OFF by the same signals as the switches constituting the integrator 2 are given the same names. Also, the DAC4 and other components are not shown in the illustration.

[0015] Adder 7 is connected between the input and output terminals of integrator 2, and includes switch φ1 and capacitance C. f and switch φ 22 A series circuit, switch φ1 and capacitor C f A switch φ is connected between the common connection point and the common voltage terminal. 22 , capacity C f and switch φ 22A switch φ1 is provided, connected between the common connection point and the common voltage terminal. The ON / OFF control of these switches is also performed by the aforementioned control circuit, and the operation timing chart is the same as in Figure 3 of the first embodiment. Note that the sampling capacitance C S This is also used in the addition operation of adder 7.

[0016] (Third embodiment) As shown in Figure 10, the modulator 8 of the third embodiment is configured in the same way as the second embodiment, but with an active integrator 9 added before the integrator 2. The active integrator 9 includes an amplifier 10, and a common voltage V is connected to the non-inverting input terminal of the amplifier 10. CM The following is given: The inverting input terminal of amplifier 10 has an input voltage V IN However, switch φ 2d and capacity C S1 It is provided via a series circuit. Additionally, a reference voltage V is supplied to the inverting input terminal. refp , V cm , V refm However, each switch φ 2t , φ 2m , φ 2b It is given through.

[0017] Between the inverting input terminal and the output terminal of amplifier 10, there is a switch φ1 and a capacitance C. I1 The series circuits of the amplifier and integrator are connected. The output terminal of the amplifier 10 is connected to the input terminal of the integrator 2 via switch φ1. The detailed operation of the active integrator 9 is not part of the gist of this embodiment, so its explanation is omitted. A similar configuration is disclosed, for example, in Japanese Patent Publication No. 6753330. With this configuration, the gain of the amplifier 10 can suppress noise components and improve the signal-to-noise ratio.

[0018] (Fourth Embodiment) As shown in Figure 11, the integrator 11 of the fourth embodiment has an integral capacitance C of the integrator 2. I to C I1 As, switch φ 21 and integral capacitance C I1 In the series circuit, a switch φ22 and integration capacitance C I2 It is a parallel connection of series circuits of. The transfer function of the integrator 11 is shown in FIG. 12, and the operation timing chart is shown in FIG. 13.

[0019] Next, the operation of the fourth embodiment will be described. <Reset phase> As shown in FIG. 14, turn on all switches. <Sampling phase> As shown in FIG. 15, turn on switches φ 1d and φ1, and charge the sampling capacitance C S with the input voltage V IN . <Integration phase (1)> As shown in FIG. 16, turn on switches φ2 and φ 21 , and distribute the charge to the sampling capacitance C S and the integration capacitance C I1 . <Integration phase (2)> As shown in FIG. 17, turn on switches φ2 and φ 22 , and distribute the charge to the sampling capacitance C S and the integration capacitance C I2 . <Output phase> As shown in FIG. 18, turn on switches φ2 and φ 23 , and output the terminal voltage of the sampling capacitance C S from the output terminal as V OUT . The above four phases are repeatedly executed as one control cycle. The integration phases (1) and (2) respectively correspond to the first integration phase and the second integration phase. The second integration phase can be implemented with the integration capacitance C[[ID=5…]] I1 disconnected from the distribution path, so the generation of ILE can be prevented.

[0020] (Fifth Embodiment) As shown in FIG. 19, in the integrator 12 of the fifth embodiment, the sampling capacitance C S of the integrator 2 is the capacitance C Sa and the capacitance C SbThis is a parallel arrangement. A switch φ is placed between the input terminal and the output terminal. 1ad , sampling capacity C Sa and switch φ 22a A series circuit and a switch φ 1bd , sampling capacity C Sb and switch φ 22b The series circuit and the parallel circuit are connected. Switch φ 1ad and sampling capacity C Sa Between the common connection point and the common voltage terminal, switch φ 1bd and sampling capacity C Sb Between the common connection point and the common voltage terminal, two separate switches, φ2 and φ2, are connected, although they share the same name.

[0021] Sampling capacity C Sa and switch φ 22a Between the common connection point and the common voltage terminal, sampling capacitance C Sb and switch φ 22b Between the common connection point and the common voltage terminal, there is a switch φ 1a , φ 1b It is connected. Also, sampling capacity C Sa and switch φ 22a Between the common connection point and the common voltage terminal, there is a switch φ 21a and integral capacitance C I A series circuit is connected. Switch φ 21a and integral capacitance C I The common connection point and sampling capacitance C Sb and switch φ 22b Between the common connection point, there is a switch φ 21b The connections are shown. The transfer function of integrator 12 is shown in Figure 20.

[0022] Next, the operation of the fifth embodiment will be described. Figure 21 shows the overall timing chart. Note that the sampling capacity C Sa Side A, sampling capacity C Sb Let's call this side side B. <Reset Phase> Turn all switches ON, as shown in Figure 22. <A side: Sampling phase / B side: Charge holding phase> As shown in FIG. 23, turn on switches φ 1ad and φ 1a to charge the sampling capacitor C Sa with the input voltage V IN . At this time, since the sampling capacitor C Sb is disconnected from the circuit, the charging charge is in a holding state. <A side: Integration phase / B side: Output phase> As shown in FIG. 24, turn on switches φ2 and φ 21a to distribute the charge between the sampling capacitor C Sa and the integration capacitor C I . At the same time, turn on switch φ 22b to output the terminal voltage of the sampling capacitor C Sb to the output terminal as V OUT .

[0023] <A side: Charge holding phase / B side: Sampling phase> As shown in FIG. 25, turn on switches φ 1bd and φ 1b to charge the sampling capacitor C Sb with the input voltage V IN . At this time, since the sampling capacitor C Sa is disconnected from the circuit, the charging charge is in a holding state. <A side: Output phase / B side: Integration phase> As shown in FIG. 26, turn on switches φ2 and φ 21b to distribute the charge between the sampling capacitor C Sb and the integration capacitor C I . At the same time, turn on switch φ 22a to output the terminal voltage of the sampling capacitor C Sa to the output terminal as V OUT . As described above, an interleaved operation is performed in parallel for the integration and output phases on the A side and the B side. As a result, it becomes possible to output the integration result in a 2-cycle period, and the control period can be shortened compared to the first embodiment.

[0024] (Embodiment 6) As shown in FIG. 27, the modulator 13 of the sixth embodiment is obtained by adding an adder 7 to the configuration of the fifth embodiment. Note that the switch φ 22 constituting the adder 7 is replaced with the switch φ3. FIG. 28 shows an operation timing chart.

[0025] (Embodiment 7) As shown in FIG. 29, the modulator 14 of the seventh embodiment is obtained by adding an active integrator 9 in front of the integrator 1 2 in the configuration of the sixth embodiment.

[0026] (Embodiment 8) As shown in FIG. 30, the integrator 15 of the eighth embodiment uses the integration capacitance C I in the integrator 12 of the fifth embodiment as C I1 , and the integration capacitance C I2 is connected in parallel via the switches φ 22a and φ 22b . Note that accordingly, the switches φ 22a and φ 22b that constituted the integrator 12 are replaced with the switches φ 23a and φ 23b . FIG. 31 shows the transfer function of the integrator 15.

[0027] Next, the operation of the eighth embodiment will be described. FIG. 32 is an overall operation timing chart. <Reset Phase> As shown in FIG. 33, turn on all the switches. <A side: Sampling Phase / B side: Second Integration Phase> As shown in FIG. 34, turn on the switches φ 1ad and φ 1a to charge the sampling capacitance C Sa with the input voltage V IN . At the same time, turn on the switches φ 2b and φ 22b to sample the charge into the sampling capacitance C Sb and the integration capacitance CI2 Distribute it to

[0028] <A side: First integration phase / B side: Output phase> As shown in FIG. 35, turn on switches φ 2a and φ 21a to sample the charge into sampling capacitor C Sa and integrating capacitor C I1 . At the same time, turn on switches φ 2b and φ 23b to output the terminal voltage of sampling capacitor C Sb to the output terminal as V OUT . <A side: Second integration phase / B side: Sampling phase> As shown in FIG. 36, turn on switches φ 2a and φ 22a to sample the charge into sampling capacitor C Sa and integrating capacitor C I2 . At the same time, turn on switches φ 1bd and φ 1b to charge sampling capacitor C Sb with input voltage V IN .

[0029] <A side: Output phase / B side: First integration phase> As shown in FIG. 37, turn on switches φ 2a and φ 23a to output the terminal voltage of sampling capacitor C Sa to the output terminal as V OUT . At the same time, turn on switches φ 2b and φ 21b to sample the charge into sampling capacitor C Sb and integrating capacitor C I1 . As described above, an interleaved operation is performed in parallel for the integration and output phases on the A side and the B side. As a result, it becomes possible to output the integration result in a 2-cycle period, and the control period can be shortened compared to the fourth embodiment. In addition, since the second integration phase can be performed with the integrating capacitor C I1 disconnected from the distribution path, the occurrence of ILE can be prevented.

[0030] (Ninth Embodiment) As shown in Figure 38, the integrator 16 of the ninth embodiment has two sampling capacitors C S1 , C S2 and two integrating capacities C I1 , C I2 And, two output terminals V OUT1 , V OUT2 It is equipped with a sampling capacity C S1 and C S2 One end is the switch φ 1d It is connected to the input terminal via [a specific method]. Sampling capacitance C S1 and C S2 The other end is connected to the common voltage terminal via two separate switches, φ1 and φ1, which have the same name but are distinct.

[0031] Also, sampling capacitance C S1 The other end is a switch φ 21 and integral capacitance C I1 It is connected to the common voltage terminal via a series circuit, and the sampling capacitance C S2 The other end is a switch φ 22 and integral capacitance C I2 It is connected to the common voltage terminal via a series circuit. Furthermore, sampling capacitance C S1 and C S2 The other end has separate switches, each with the same name φ 23 and φ 23 Output terminal V via OUT1 , V OUT2 It is connected. Also, the sampling capacity C S2 The other end is a switch φ 21 Integrating capacitance C via I1 It is connected to the upper end.

[0032] Next, the operation of the ninth embodiment will be described. Figure 39 is an overall operation timing chart. <Reset Phase> Turn all switches ON, as shown in Figure 40. <Sampling Phase> As shown in Figure 41, switch φ 1d And turn φ1 ON, sampling capacitance C S1 , C S2 Input voltage V IN Charge it with this.

[0033] <First-order integral phase> As shown in Figure 42, switches φ2 and φ 21 Turn ON the charge sampling capacitor C S1 and C S2 and the integral capacity C I1 Distribute it to them. <Quadratic Integral Phase> As shown in Figure 43, switches φ2 and φ 22 Turn ON the charge sampling capacitor C S2 and the integral capacity C I2 It is then distributed to and . At this time, the sampling capacity C S1 The charge is retained. The first and second integral phases correspond to the first and second integral phases, respectively. <Output Phase> As shown in Figure 44, switches φ2 and φ 23 Turn ON the sampling capacitance C S1 , C S2 The terminal voltages are set to V at each output terminal. OUT1 , V OUT2 Output as follows.

[0034] (Tenth embodiment) As shown in Figure 45, the modulator 17 of the 10th embodiment is equipped with two differential integrators 16 of the 9th embodiment, one of which is the illustrated integrator 16(+) and the other is the integrator 16(-) which is not shown. The output voltages of integrator 16(+) and integrator 16(-) have opposite signs, and the output voltage of integrator 16(+) is V OUT1 +, V OUT2 The output voltage of integrator 16(-) is V. OUT1 -, V OUT2 - is

[0035] And then, output terminal V OUT1 + and output terminal V OUT2- is short-circuited, meaning the output voltages of both are added together and input to one input terminal of the differential input quantizer 18, and the output terminal V OUT2 + and output terminal V OUT1 - is similarly short-circuited and input to the other input terminal of the quantizer 18. At this time, the sampling capacitance C S1 , C S2 The constant can be set appropriately considering the feedforward gain coefficient. Furthermore, although the input terminals of the quantizer 18 are shared between the integrator 16(+) and integrator 16(-), it is also possible to separate them and adjust the input gain by weighting the transconductance Gm of the transistors constituting the input of the quantizer 18.

[0036] (11th embodiment) As shown in Figure 46, the modulator 17 of the 11th embodiment is obtained by adding an active integrator 9 similar to the modulator 8 of the third embodiment to the input side of the integrator 16 of the 10th embodiment.

[0037] (12th embodiment) As shown in Figure 47, the integrator 21 of the 12th embodiment has a sampling capacitance C of the integrator 16 of the 9th embodiment. S1 and C S2 Capacity C Sb1 and C Sb2 Therefore, these have a sampling capacity C Sa1 and C Sa2 This configuration includes an additional input terminal and capacitance C. Sa1 and C Sa2 Between one end and the other, there is a switch φ 1ad The common voltage terminal and capacitance C are connected at the top of the diagram. Sa1 and C Sa2 Between one end and the other, there is a switch φ 2a The common voltage terminal and capacitance C are connected. Sa1 and C Sa2 Between the other end and the other end, there is a switch φ 1a , φ 1a It is connected.

[0038] Capacity C Sa1 , C Sa2and the other end of the integration capacitor C I1 Between the upper end of "...""," I1 ",""[-and the other end of the integration capacitor C-]"," 21a ","and φ"," 21a ","are connected respectively. For the capacitor C"," Sa2 ","between the other end of "...""," I2 ","and the upper end of the integration capacitor C"," 22a ","the switch φ"," Sa1 ","C"," Sa2 ","between the other end of "...""," OUT1 ","and the output terminals V"," OUT2 ","the switches φ"," 23a ","and φ"," 23a ","are connected respectively. The switches φ"," 21 ","to φ"," 23 ","corresponding to those in the integrator 16 of the ninth embodiment are shown as switches φ "," 21b ","to φ "," 23b ","respectively.

[0039] Next, the operation of the twelfth embodiment will be described. Fig. 48 is the overall operation timing chart. <Reset Phase> As shown in Fig. 49, turn on all the switches. <A side: Sampling Phase / B side: Second Integration Phase> As shown in Fig. 50, turn on the switches φ 1ad and φ 1a to charge the sampling capacitors C Sa1 and C Sa2 with the input voltage V IN . At the same time, turn on the switches φ 2b and φ 22b to distribute the charge to the sampling capacitor C Sb2 and the integration capacitor C I2 .

[0040] <A side: First Integration Phase / B side: Output Phase> As shown in Fig. 51, turn on the switches φ 2a and φ 21a to distribute the charge to the sampling capacitors C Sa1 and C Sa2 and the integration capacitor C I1 . At the same time, turn on the switches φ 2b and φ23b Turn on and set the sampling capacitance C Sb1 and C Sb2 The terminal voltages of are output as V OUT1 , V OUT2 to the output terminals respectively.

[0041] <A-side: Second integration phase / B-side: Sampling phase> As shown in FIG. 52, turn on switches φ 2a and φ 22a to distribute the charge to the sampling capacitance C Sa2 and the integration capacitance C I2 At the same time, turn on switch φ 1bd to charge the sampling capacitances C Sb1 and C Sb2 with the input voltage V IN .

[0042] <A-side: Output phase / B-side: First integration phase> As shown in FIG. 53, turn on switches φ 2a and φ 23a to output the terminal voltages of the sampling capacitances C Sa1 and C Sa2 as V OUT1 , V OUT2 to the output terminals respectively. At the same time, turn on switches φ 2b and φ 21b to distribute the charge to the sampling capacitances C Sb1 and C Sb2 and the integration capacitance C I1 . As described above, an interleaved operation is performed in parallel for the integration and output phases on the A-side and B-side.

[0043] (Embodiment 13) As shown in Figure 54, the modulator 22 of the 13th embodiment, like the 10th embodiment, is equipped with two differential integrators 21 of the 12th embodiment, one of which is the illustrated integrator 21(+) and the other is the integrator 21(-) which is not shown. The output voltages of integrator 21(+) are VOUT1+ and VOUT2+, and the output voltages of integrator 21(-) are VOUT1- and VOUT2-. Output terminals VOUT1+ and VOUT2- are short-circuited and input to one input terminal of the differential input quantizer 18, and output terminals VOUT2+ and VOUT1- are similarly short-circuited and input to the other input terminal of the quantizer 18.

[0044] (14th Embodiment) As shown in Figure 55, the modulator 23 of the 14th embodiment is modified by adding an active integrator 9 similar to the modulator 8 of the 3rd embodiment to the input side of the integrator 21 of the 13th embodiment.

[0045] (Other embodiments) In the modulator 1 shown in Figure 8, a secondary integrator may be added between the integrator 2 and the quantizer 3, and a path may be added to feed back the output of the DAC4 to the input side of the secondary integrator. Furthermore, if we consider adding an active integrator before the primary integrator 2, as shown in Figure 10, to the above configuration, the active integrator becomes primary, integrator 2 becomes secondary, and the aforementioned secondary integrator becomes tertiary. In this case, a feedback path similar to the one described above may be added to the input side of the secondary and tertiary integrators.

[0046] This case includes the invention described in the claims, as well as the following inventions: [1] A modulator comprising passive integrators (2, 11, 12, 15, 16, 21), The aforementioned passive integrator is, One or more sampling capacities (C S , C Sa , C Sb , C Sa1 , C Sa2 , CSb1 , C Sb2 、C S1 、C S2 )and, One or more integral capacities (C) I , C I1 , C I2 )and, Input terminal (V IN ), the aforementioned capacitances and output terminals (V OUT Multiple switches (φ1, φ) used to change the connection state between them 1d , φ 1ad , φ 1bd , φ2, φ 21 , φ 22 , φ 21a , φ 22a , φ 21b , φ 22b , φ 23 , φ 23a , φ 23b It is equipped with φ3) and By controlling the ON / OFF state of the aforementioned multiple switches, A sampling phase in which the input voltage is sampled using the sampling capacitance, An integration phase in which the charge of the sampling capacitor is distributed with the integrating capacitor, A modulator that performs an output phase in which the terminal voltage of the sampling capacitor is output from the output terminal while the integrating capacitor is disconnected from the output terminal. [2] One sampling capacity (C S )and, First and second integrating capacities (C I1 , C I2 ) and, The aforementioned integration phase includes a first and a second integration phase. The first integration phase distributes the charge of the sampling capacitor with the first integration capacitor. The modulator according to [1], wherein the second integration phase distributes the charge of the sampling capacitance with the second integration capacitance while the first integration capacitance is disconnected from the distribution path. [3] First and second sampling capacities (CSa , C Sb )and, One integral capacitance (C) I ) and, During the sampling phase of the first control cycle, sampling is performed using the first sampling capacitor, and the charge of the second sampling capacitor is held. During the integration phase and the output phase, the charge of the first sampling capacitor is distributed with the integration capacitor, and at the same time, the terminal voltage of the second sampling capacitor is output. The modulator described in [1], wherein in the sampling, integration, and output phases of the subsequent second control cycle, the first sampling capacitance and the second sampling capacitance are swapped and the same process is repeated. [4] First and second sampling capacities (C Sa , C Sb )and, First and second integrating capacities (C I1 , C I2 ) and, In the first control cycle, sampling is performed using the first sampling capacitor during the sampling phase, and simultaneously, during the integration phase, the charge of the second sampling capacitor is distributed with the second integrating capacitor while the first integrating capacitor is disconnected from the distribution path. In the subsequent second control cycle, the charge of the first sampling capacitor is distributed with the first integrating capacitor during the integration phase, and at the same time, the output is generated by the second sampling capacitor during the output phase. The modulator described in [1] repeatedly performs the same process in the following first and second control cycles, by swapping the first sampling capacity and the second sampling capacity, respectively. [5] The first and second sampling capacitors each consist of two capacitive elements (C Sa1 , C Sa2 , C Sb1 , C Sb2 ) consists of, First and second output terminals (V OUT1 , V OUT2 ) equipped, In the output phase, the modulator [4] outputs the terminal voltages of the two capacitive elements individually from the first and second output terminals. [6] First and second sampling capacities (C S1 , C S2 )and, First and second integrating capacities (C I1 , C I2 )and, First and second output terminals (V OUT1 , V OUT2 ) and, The aforementioned integration phase includes a first and a second integration phase. In the sampling phase, sampling is performed using the first and second sampling capacities. In the first integration phase, the charges of the first and second sampling capacitors are distributed with the first integrating capacitor. In the second integration phase, the charge of the first sampling capacitor is distributed with the second integrating capacitor. The modulator described in [1], wherein in the output phase, the terminal voltages of the first and second sampling capacitances are individually output from the first and second output terminals. [7] An adder (7) that adds the voltage input from the preceding stage and the voltage at the output terminal, The system includes a quantizer (3,18) connected to the output terminals [1] to [ 4 ] 1 The modulator described above. [8] The aforementioned Passive type The integrator (16) is a differential structure Formation( 16(+), 16(- ))in can be, A differential quantizer (18) is provided, The aforementioned Differential configuration The output terminals of the integrator are connected to the input terminals of the quantizer, with output signals of different signs directly connected to each other. 6 The modulator described in [ ]. [9] The passive integrator (21) has a differential configuration (21(+), 21(-)), A differential quantizer (18) is provided, The modulator described in [5], wherein the output terminals of the differential integrator are connected to the input terminals of the quantizer, with output signals of different signs directly connected to each other.

[10] A modulator according to any one of [1] to [7], comprising an active integrator (9) connected downstream of the aforementioned input terminal.

[11] A modulator according to [8] or [9], comprising an active integrator (9) connected downstream of the input terminal.

[0047] This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of symbols]

[0048] In the diagram, 1 is a ΔΣ modulator, 2 is an integrator, 3 is a quantizer, 4 is a D / A converter, 5 is a subtractor, C S C is the sampling capacity. I φ1, φ 1d , φ2, φ 22 This indicates a switch.

Claims

1. A modulator comprising passive integrators (2, 11, 12, 15, 16, 21), The aforementioned passive integrator is, One or more sampling capacities (C Ｓ , C Ｓａ , C Ｓｂ , C Ｓａ１ , C Ｓａ２ , C Ｓｂ１ , C Ｓｂ２ , C S1, C S2) and, One or more integration capacitances (C Ｉ , C Ｉ１ , C Ｉ２ ), and Input terminal (V ＩＮ ), each of the above capacities and output terminals (V ＯＵＴ Multiple switches (φ) used to change the connection state between ) １ , φ １ｄ , φ １ａｄ , φ １ｂｄ , φ ２ , φ ２１ , φ ２２ , φ ２１ａ , φ ２２ａ , φ ２１ｂ , φ ２２ｂ , φ ２３ , φ ２３ａ , φ ２３ｂ , φ ３ ) and, By controlling the ON / OFF state of the aforementioned multiple switches, A sampling phase in which the input voltage is sampled using the sampling capacitance, An integration phase in which the charge of the sampling capacitor is distributed with the integrating capacitor, A modulator that performs an output phase in which the terminal voltage of the sampling capacitor is output from the output terminal while the integrating capacitor is disconnected from the output terminal.

2. One sampling capacity (C Ｓ )and, First and second integrating capacities (C) Ｉ１ , C Ｉ２ ) and, The integration phase includes a first and a second integration phase. The first integration phase distributes the charge of the sampling capacitor with the first integration capacitor. The modulator according to claim 1, wherein the second integration phase distributes the charge of the sampling capacitance with the second integration capacitance while the first integration capacitance is disconnected from the distribution path.

3. The first and second sampling capacities (CSa, CSb), One integrating capacitance (C) Ｉ ) and, During the sampling phase of the first control cycle, sampling is performed using the first sampling capacitor, and the charge of the second sampling capacitor is held. During the integration phase and the output phase, the charge of the first sampling capacitor is distributed with the integration capacitor, and at the same time, the terminal voltage of the second sampling capacitor is output. The modulator according to claim 1, wherein in the sampling, integration, and output phases of the subsequent second control cycle, the first sampling capacitance and the second sampling capacitance are swapped and the same process is repeatedly performed.

4. First and second sampling capacities (C Ｓａ , C Ｓｂ )and, First and second integrating capacities (C) Ｉ１ , C Ｉ２ ) and, In the first control cycle, sampling is performed using the first sampling capacitor during the sampling phase, and simultaneously, during the integration phase, the charge of the second sampling capacitor is distributed with the second integrating capacitor while the first integrating capacitor is disconnected from the distribution path. In the subsequent second control cycle, the charge of the first sampling capacitor is distributed with the first integrating capacitor during the integration phase, and at the same time, the output is generated by the second sampling capacitor during the output phase. The modulator according to claim 1, wherein in the next first and second control cycles, the first sampling capacity and the second sampling capacity are swapped, and the same process is repeatedly performed in each.

5. The first and second sampling capacitances each consist of two capacitive elements (C Ｓａ１ , C Ｓａ２ , C Ｓｂ１ , C Ｓｂ２ ) consists of, First and second output terminals (V ＯＵＴ１ , V ＯＵＴ２ ) equipped, The modulator according to claim 4, wherein in the output phase, the terminal voltages of the two capacitive elements are individually output from the first and second output terminals.

6. First and second sampling capacities (C Ｓ１ , C Ｓ２ )and, First and second integrating capacities (C) Ｉ１ , C Ｉ２ )and, First and second output terminals (V ＯＵＴ１ , V ＯＵＴ２ ) and, The integration phase includes a first and a second integration phase. In the sampling phase, sampling is performed using the first and second sampling capacities. In the first integration phase, the charges of the first and second sampling capacitors are distributed with the first integrating capacitor. In the second integration phase, the charge of the first sampling capacitor is distributed with the second integrating capacitor. The modulator according to claim 1, wherein in the output phase, the terminal voltages of the first and second sampling capacitances are individually output from the first and second output terminals.

7. An adder (7) that adds the voltage input from the preceding stage and the voltage at the output terminal, A modulator according to any one of claims 1 to 4, comprising a quantizer (3) connected downstream of the output terminal.

8. The passive integrator (16) has a differential configuration (16(+), 16(-)), A differential quantizer (18) is provided, The modulator according to claim 6, wherein the output terminals of the differential integrator are connected to the input terminals of the quantizer in a state where the output signals with different signs are directly connected to each other.

9. The passive integrator (21) has a differential configuration (21(+), 21(-)), A differential quantizer (18) is provided, The modulator according to claim 5, wherein the output terminals of the differential integrator are connected to the input terminals of the quantizer in a state where the output signals with different signs are directly connected to each other.

10. The modulator according to any one of claims 1 to 4, further comprising an active integrator (9) connected downstream of the input terminal.

11. The modulator according to claim 8 or 9, further comprising an active integrator (9) connected downstream of the input terminal.

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